commit 03325b95023005758f9c31172b8666ef448c7962 Author: Alexandre Gut Date: Tue Mar 31 13:10:37 2026 +0200 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..1b535a1 --- /dev/null +++ b/.gitignore @@ -0,0 +1,58 @@ +# ── Compilation C / C++ ────────────────────────────────────────────────────── +*.o +*.a +*.so +*.so.* +*.dylib +*.dll +*.exe +*.out +*.elf +*.bin +*.hex +*.map +*.lst + +# ── CMake ───────────────────────────────────────────────────────────────────── +build/ +cmake-build-*/ +CMakeCache.txt +CMakeFiles/ +cmake_install.cmake +Makefile +_deps/ +install_manifest.txt + +# ── PlatformIO ──────────────────────────────────────────────────────────────── +.pio/ +.pioenvs/ +.piolibdeps/ + +# ── Raspberry Pi Pico / SDK ─────────────────────────────────────────────────── +pico-sdk/ +pico-examples/ +# (déjà disponibles sur GitHub officiel, inutile de les dupliquer) + +# ── Fichiers générés ───────────────────────────────────────────────────────── +*.d +*.dep +generated/ + +# ── Secrets / Config ────────────────────────────────────────────────────────── +.env +secret.env +secrets.h +config_secret.h + +# ── IDE ─────────────────────────────────────────────────────────────────────── +.vscode/ +.idea/ +*.swp +.DS_Store +Thumbs.db +*.user +*.suo + +# ── Logs / Debug ───────────────────────────────────────────────────────────── +*.log +*.trace diff --git a/AS5600 b/AS5600 new file mode 160000 index 0000000..5134633 --- /dev/null +++ b/AS5600 @@ -0,0 +1 @@ +Subproject commit 513463364f2c173ffcb07f933f358b2f1553083c diff --git a/AS5600L/AS5600L.c b/AS5600L/AS5600L.c new file mode 100644 index 0000000..3bfe825 --- /dev/null +++ b/AS5600L/AS5600L.c @@ -0,0 +1,93 @@ +#include "AS5600L.h" + +void as560x_init(AS5600L* as5600l, i2c_inst_t *I2C_ID, int frq , int sda, int scl ) { + i2c_init(I2C_ID, frq); + gpio_set_function(sda, GPIO_FUNC_I2C); + gpio_set_function(scl, GPIO_FUNC_I2C); + gpio_pull_up(sda); + gpio_pull_up(scl); + + AS5600L_I2C instance_i2c; + instance_i2c.I2C_PORT = I2C_ID; + instance_i2c.FREQUENCE = frq; + instance_i2c.I2C_SDA_PIN = sda; + instance_i2c.I2C_SCL_PIN = scl; + + as5600l->serial_instance = instance_i2c; + as5600l->abs_pos = 0; + as5600l->curr_angle = 0; + as5600l->last_angle = 0; + as5600l->start_pos = 0; + + + as5600l->start_pos = as560xReadAngle(as5600l); + as5600l->abs_pos = 0 - as5600l->start_pos; +} + +int update_pos(AS5600L* as5600l){ + // sensorData(); + as5600l->curr_angle = as560xReadAngle(as5600l); + + if(as5600l->last_angle > ENCODER_RESOLUTION/2 & as5600l->curr_angle < (as5600l->last_angle - ENCODER_RESOLUTION/2)){ + as5600l->abs_pos = as5600l->abs_pos + ENCODER_RESOLUTION - as5600l->last_angle + as5600l->curr_angle; + }else if(as5600l->curr_angle > ENCODER_RESOLUTION/2 & as5600l->last_angle < (as5600l->curr_angle - ENCODER_RESOLUTION/2) ){ + as5600l->abs_pos = as5600l->abs_pos -ENCODER_RESOLUTION - as5600l->last_angle + as5600l->curr_angle; + }else{ + as5600l->abs_pos = as5600l->abs_pos - as5600l->last_angle + as5600l->curr_angle; + } + + as5600l->last_angle = as5600l->curr_angle; + return as5600l->abs_pos; +} + +int __bswap16(int value) { + return (value >> 8) | (value << 8); +} + +void i2cError() { + printf("I2C Error\n"); +} + +int as560xReadReg(AS5600L* as5600l,int addr, bool wide, int mask) { + int buf; + int result = i2c_write_timeout_us(as5600l->serial_instance.I2C_PORT, AS5600L_ADDRESS, (uint8_t *)&addr, 1, true, I2C_TIMEOUT_US); + if (result <= 0) { + i2cError(); + } + result = i2c_read_timeout_us(as5600l->serial_instance.I2C_PORT, AS5600L_ADDRESS, (uint8_t *)&buf, (wide ? 2 : 1), false, I2C_TIMEOUT_US); + if (result <= 0) { + i2cError(); + } + if (wide) { + return __bswap16(buf) & mask; + } else { + return buf & mask; + } +} + +void AS560x_print_reg16(AS5600L* as5600l,const char *formatStr, int addr, int mask) { + int result = as560xReadReg(as5600l,addr, true, mask); + printf(formatStr, result & mask); +} + +void AS560x_print_reg8(AS5600L* as5600l,const char *formatStr, int addr, uint8_t mask) { + uint8_t result = (uint8_t)as560xReadReg(as5600l,addr, false, mask); + printf(formatStr, result & mask); +} + + +int as560xReadAngle(AS5600L* as5600l) { + return as560xReadReg(as5600l,AS560x_RAW_ANGLE_REG, true, 0xFFF) ; +} + +uint8_t as560xGetStatus(AS5600L* as5600l) { + return (uint8_t)as560xReadReg(as5600l,AS560x_STATUS_REG, false, 0x38); +} + +void sensorData(AS5600L* as5600l) { + AS560x_print_reg8(as5600l,"Status: %02x; ", AS560x_STATUS_REG, 0x38); + AS560x_print_reg8(as5600l,"AGC: %3x; ", 0x1a, 0xff); + AS560x_print_reg16(as5600l,"Angle: %d\n\r", AS560x_RAW_ANGLE_REG, 0xFFF); +} + + diff --git a/AS5600L/AS5600L.h b/AS5600L/AS5600L.h new file mode 100644 index 0000000..ab6833e --- /dev/null +++ b/AS5600L/AS5600L.h @@ -0,0 +1,47 @@ +#ifndef AS5600L_H +#define AS5600L_H + +#include "hardware/i2c.h" +#include "pico/stdlib.h" +#include "pico/time.h" +#include +#include +#include + +#define I2C_TIMEOUT_US (100000) + +#define AS560x_STATUS_REG (0x0B) +#define AS560x_RAW_ANGLE_REG (0x0C) +#define AS5600L_ADDRESS 0x40 +#define ENCODER_RESOLUTION 4096 + + + +typedef struct { + i2c_inst_t *I2C_PORT; + int FREQUENCE; + int I2C_SDA_PIN; + int I2C_SCL_PIN; +} AS5600L_I2C; + +typedef struct { + AS5600L_I2C serial_instance; + int last_angle; + int curr_angle ; + int abs_pos ; + int start_pos; +} AS5600L; + + +void as560x_init(AS5600L* as5600l, i2c_inst_t *I2C_ID, int frq , int sda, int scl); +int update_pos(AS5600L* as5600l); +int __bswap16(int value); +void i2cError(); +int as560xReadReg(AS5600L* as5600l,int addr, bool wide, int mask); +void AS560x_print_reg16(AS5600L* as5600l,const char *formatStr, int addr, int mask); +void AS560x_print_reg8(AS5600L* as5600l,const char *formatStr, int addr, uint8_t mask); +int as560xReadAngle(AS5600L* as5600l); +uint8_t as560xGetStatus(AS5600L* as5600l); +void sensorData(AS5600L* as5600l); + +#endif /* AS5600L_H */ diff --git a/AS5600L/CMakeLists.txt b/AS5600L/CMakeLists.txt new file mode 100644 index 0000000..14bd00f --- /dev/null +++ b/AS5600L/CMakeLists.txt @@ -0,0 +1,32 @@ +cmake_minimum_required(VERSION 3.12) + +#cmake -G "MinGW Makefiles" .. + +set(PROJECT_NAME "AS5600L_test") +set(PICO_SDK_PATH "E:/Beyon_Motion/pico-sdk") +set(PICO_TOOLCHAIN_PATH "C:/Users/spide/scoop/apps/gcc-arm-none-eabi/current/bin") +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +include(${PICO_SDK_PATH}/external/pico_sdk_import.cmake) + +project(${PROJECT_NAME} C CXX ASM) + +pico_sdk_init() + +add_executable(${PROJECT_NAME} + main.c + AS5600L.c + AS5600L.h +) + +target_link_libraries(${PROJECT_NAME} + pico_stdlib + hardware_i2c + hardware_dma +) + +pico_enable_stdio_usb(${PROJECT_NAME} 1) +pico_enable_stdio_uart(${PROJECT_NAME} 0) + +pico_add_extra_outputs(${PROJECT_NAME}) \ No newline at end of file diff --git a/AS5600L/main.c b/AS5600L/main.c new file mode 100644 index 0000000..012c377 --- /dev/null +++ b/AS5600L/main.c @@ -0,0 +1,28 @@ +#include "pico/stdlib.h" +#include "pico/time.h" +#include "hardware/i2c.h" +#include +#include "AS5600L.h" + +#define I2C_PORT i2c0 +#define I2C_SDA_PIN 8 +#define I2C_SCL_PIN 9 + +int main() { + stdio_init_all(); + sleep_ms(1000); + + AS5600L as5600l; + + as560x_init(&as5600l,I2C_PORT,100000,I2C_SDA_PIN,I2C_SCL_PIN); + + int abs = 0; + abs = update_pos; + while (true) { + // abs = update_pos(&as5600l); + // printf("Position absolue : %d\n",abs); + sensorData(&as5600l); + } + + return 0; +} diff --git a/BM/as5600l.py b/BM/as5600l.py new file mode 100644 index 0000000..9e8c03d --- /dev/null +++ b/BM/as5600l.py @@ -0,0 +1,151 @@ +import time +import setenv + +from machine import I2C, Pin + +ADDRESS = 0x40 +ZMCO = 0x00 +ZPOS = 0x01 +MPOS = 0x03 +MANG = 0x05 +CONF_REG = 0x07 +STATUS_REG = 0x0B +RAWANGLE = 0x0c +ANGLE_REG = 0x0E +AGC_REG = 0x1A +MAGNITUDE = 0x1b +BURN = 0xff + + +class AS5600L: + + def __init__(self, + i2c_id = setenv.ENCODER_NUMBER, + sda = setenv.ENCODER_SDA_PIN, + scl = setenv.ENCODER_SCL_PIN, + i2c_freq = setenv.ENCODER_I2C_FREQUENCE, + hyst = setenv.ENCODER_HYST, + power_mode = 0, + watchdog = 0, + fast_filter_threshold = 0, + slow_filter = 0, + pwm_freq = 0, + output_stage = 0): + """Init + Args: + i2c_id (int, optional): ID of the I2C bus. Defaults to 0. + sda (int, optional) : gpio of the I2C bus. Defaults to 0. + scl (int, optional) : gpio of clock for I2C bus. Defaults to 1. + i2c_freq (int, optional): I2C Ferequency. Default is max. Defaults to 1000000. + hyst (int, optional): Hysteresis: 0->3. Defaults to 0. + power_mode (int, optional): Power Mode: 0->3. Defaults to 0. + watchdog (int, optional): Enable the watchdog. Defaults to 0. + fast_filter_threshold (int, optional): Threshold value for the fast filter: 0->7. Defaults to 0. + slow_filter (int, optional): Slow filter mode: 0->3. Defaults to 0. + pwm_freq (int, optional): Output PWM frequency: 0->3. Defaults to 0. + output_stage (int, optional): Output mode (see datasheet): 0->2. Defaults to 0. + """ + self.i2c = I2C(i2c_id, scl=Pin(scl), sda=Pin(sda), freq=i2c_freq) + print(self.i2c.scan()) + time.sleep_ms(100) + c1 = 0x00 + c2 = 0x00 + # # set watchdog 0,1 + # if watchdog in range(0,2): + # c1 = c1 | (watchdog << 5) + # # set fast filter threshold 0->7 + # if fast_filter_threshold in range(0,8): + # c1 = c1 | (fast_filter_threshold << 2) + # # set the slow filter 0->3 + # if slow_filter in range(0,4): + # c1 = c1 | slow_filter + # # set PWM frequency 0->3 + # if pwm_freq in range(0,4): + # c2 = c2 | (pwm_freq << 6) + # # set output stage 0->2 + # if output_stage in range(0,2): + # c2 = c2 | (output_stage << 4) + # # set power_mode 0->3 + # if power_mode in range(0, 4): + # c2 = c2 | power_mode + # # set Hysteresis 0->3 + # if hyst in range(0, 4): + # c2 = c2 | (hyst << 2) + + self.i2c.writeto(ADDRESS, bytes([CONF_REG, c1, c2])) + + def get_status(self): + """Get the status of the ASL560L + + Returns: + Dict: Dictionary of the different statuses + """ + self.i2c.writeto(ADDRESS, bytes([STATUS_REG])) + status = int.from_bytes(self.i2c.readfrom(ADDRESS, 1), 'big') + mh = bool(status & 0b00001000) + ml = bool(status & 0b00010000) + md = bool(status & 0b00100000) + self.i2c.writeto(ADDRESS, bytes([AGC_REG])) + agc = int.from_bytes(self.i2c.readfrom(ADDRESS, 1), 'big') + + return { + "magnetDetected": md, + "magnetTooWeak": ml, + "magnetTooStrong": mh, + "agc": agc + } + + def is_ok(self) -> bool: + """Reads the status values to determine if the magnet is able to be read. + Returns: + bool: True if the magnet can be detercted accurately + """ + self.i2c.writeto(ADDRESS, bytes([STATUS_REG])) + status = int.from_bytes(self.i2c.readfrom(ADDRESS, 1), 'big') + mh = bool(status & 0b00001000) + ml = bool(status & 0b00010000) + md = bool(status & 0b00100000) + + if md and not mh and not ml: + return True + else: + return False + + def get_angle(self) -> int: + """Get the raw 12bit angle value + Returns: + int: 0->4095 + """ + self.i2c.writeto(ADDRESS, bytes([ANGLE_REG])) + return int.from_bytes(self.i2c.readfrom(ADDRESS, 2), 'big') + + + def get_angle_degrees(self): + """Get the angle in degrees, IF the magnet can be read + + Returns: + float: Degrees (0->359) if magnet can be read otherwise None. + """ + if self.is_ok(): + return (float(self.get_angle())) + else: + # if the magnet cannot be read then the angle is unreliable, so return None. + return None + + def get_angle_degrees_fast(self): + """Get the angle in degrees + + Returns: + float: Degrees (0->359) if magnet can be read otherwise None. + """ + self.i2c.writeto(ADDRESS, b'\x0c') + return (float(int.from_bytes(self.i2c.readfrom(ADDRESS, 2), 'big'))) + + def get_conf(self): + """Internal healper function to read the raw config value + + Returns: + int: raw value + """ + self.i2c.writeto(ADDRESS, bytes([CONF_REG])) + return int.from_bytes(self.i2c.readfrom(ADDRESS, 2), 'big') \ No newline at end of file diff --git a/BM/main.py b/BM/main.py new file mode 100644 index 0000000..de4d411 --- /dev/null +++ b/BM/main.py @@ -0,0 +1,27 @@ +from smart_motor import SmartMotor +import time + +tmc = SmartMotor() + +print("########") + + +#tmc.driver_status() +#tmc.general_config() + +print("########") + +#tmc.init_encoder() + +#tmc.rotate(5,degrees=18000,acceleration=1000,deceleration=1000) +print("begin1",tmc.get_microstepping_resolution()); +time.sleep(2) +tmc.set_microstepping_resolution(256) +time.sleep(2) + +print("begin",tmc.get_microstepping_resolution()); + +#print("encoder : ") +#print(tmc.get_encoder_position(0)) + +#0x55 0x00 0x6C 0x4D diff --git a/BM/setenv.py b/BM/setenv.py new file mode 100644 index 0000000..f96823c --- /dev/null +++ b/BM/setenv.py @@ -0,0 +1,39 @@ +SID = '#6' +BOARD_NAME = 'PICO' +PACKAGE_NAME = 'Prodigy' +VERSION = 0.1 + +#----------------------------------------------------------------------- +# Setup Pin Motor TMC2209 +#----------------------------------------------------------------------- +MOTOR_NUMBER = 1 +MOTOR_TX_PIN = 4 +MOTOR_RX_PIN = 5 +MOTOR_EN_PIN = 7 +MOTOR_STEP_PIN = 10 +MOTOR_DIR_PIN = 11 +MOTOR_BAUDRATE = 115200 +MOTOR_SENSOR_BEGIN_PIN = -1 +MOTOR_SENSOR_END_PIN = -1 +MOTOR_SENSOR_BEGIN_VALUE = 1 +MOTOR_SENSOR_END_VALUE = 1 +MOTOR_SOFT_UART = False + +#----------------------------------------------------------------------- +# Setup Motor TMC2209 +#----------------------------------------------------------------------- +MOTOR_STEP_MOTOR = 48 +MOTOR_SCREW_THREAD = 1.22 +MOTOR_MICROSTEP = 1 +MOTOR_VREF = 5.4 +MOTOR_AMP = 1800 + +#----------------------------------------------------------------------- +# Setup Pin I2C encoder AS5600L +#----------------------------------------------------------------------- +ENCODER_NUMBER = 0 +ENCODER_SDA_PIN = 8 +ENCODER_SCL_PIN = 9 +ENCODER_I2C_FREQUENCE = 400000 +ENCODER_HYST = 1 + diff --git a/BM/smart_motor.py b/BM/smart_motor.py new file mode 100644 index 0000000..f84f6d4 --- /dev/null +++ b/BM/smart_motor.py @@ -0,0 +1,325 @@ +import time +from as5600l import AS5600L +from tmc_2209 import TMC2209 +import setenv +from machine import Pin +import gc +#----------------------------------------------------------------------- +# sets the register bit "VACTUAL" to to a given value +# VACTUAL allows moving the motor by UART control. +# It gives the motor velocity in +-(2^23)-1 [μsteps / t] +# 0: Normal operation. Driver reacts to STEP input +#----------------------------------------------------------------------- +class SmartMotor(TMC2209): + status = False + + position = 0 + if setenv.MOTOR_SENSOR_END_PIN != -1 : + init_home_end =setenv.MOTOR_SENSOR_END_VALUE + pin_home_end = Pin(setenv.MOTOR_SENSOR_END_PIN, Pin.IN) + if setenv.MOTOR_SENSOR_BEGIN_PIN != -1 : + init_home_begin =setenv.MOTOR_SENSOR_BEGIN_VALUE + pin_home_begin = Pin(setenv.MOTOR_SENSOR_BEGIN_PIN, Pin.IN) + + def get_encoder_position(self,encoder): + if self.encoder is not None: + self.actual = self.encoder.get_angle_degrees() + if self.actual != None and self.actual != self.last: + self.calc = self.actual-self.last + if self.actual < self.last : + if self.calc<-3800: + self.calc = abs((4096 - self.last + self.actual)) + self.posreal+=self.calc + elif self.actual > self.last : + if self.calc>3800: + self.calc = abs((4096 - self.actual + self.last)) + self.posreal+=self.calc + self.last = self.actual + return(self.posreal) + + def init_encoder(self): + self.encoder = AS5600L() + self.actual = 0 + self.last = 0 + print(self.encoder.get_status()) + self.posbegin = self.encoder.get_angle_degrees_fast() + print("posbegin",self.posbegin) + self.posreal = 0 + self.last=self.posbegin + + def reset_position(self): + self.position = 0 + + # def set_home_pins(self, start = -1, end = -1): + + def set_encoder(self, encoder): + self.encoder = encoder + + def init_vactual(self): + self.clear_general_stat() + time.sleep_us(10) + self.set_voltage_sense(False)#ok + self.set_current_flow(setenv.MOTOR_AMP) + self.set_iscale_analog(False)#ok + self.set_interpolation(True) + self.set_internal_resistor_sense(False) + self.set_spread_cycle(True) + self.set_microstepping_resolution(setenv.MOTOR_MICROSTEP) + self.set_microstep_resolution_regselect(True) + self.set_pin_enable(True) + return True + + def rotate(self, + vactual, + degrees = 0, + acceleration = 0, + deceleration = 0, + KP = 1.0, + KI = 0, + KD = 0, + counter = False, + show_stallguard_result = False, + show_tstep = False, + absrel = True): + self.init_vactual() + liste_vitesse = [0] + liste_time = [0] + liste_distance = [0] + if(absrel): + if degrees - self.position < 0: + print(degrees - self.position) + self.set_direction_shart(False) + degrees = abs(degrees - self.position) + sense = False + else: + degrees = degrees - self.position + sense = True + self.set_direction_shart(True) + + vactual = int(round((vactual/0.715)*self.get_steps_per_resolution())) # not tested! + self._stop = False + current_vactual = 0 + last_error = 0 + integral = 0 + + + if self.debugmode == True: + if(degrees != 0): + print("vactual: "+str(vactual)+" for "+str(degrees)+" degrees") + + + if (degrees != 0): + start_time = time.ticks_ms() + end_time = start_time + current_degrees = 0 + timespan = 0 + error= 0 + self.set_pin_enable(True) + while((current_degrees <= degrees)): + print(current_degrees) + error = degrees - current_degrees + integral = integral + error + derivative = error - last_error + speed_adjustment = KP * error + KI * integral + KD * derivative + last_error = error + + start_time= time.ticks_ms() + gap_time = (start_time-end_time)/1000 + rps = current_vactual/self.get_steps_per_resolution()*0.715 + angle = rps*gap_time*360 + current_degrees = current_degrees+angle + timespan +=gap_time + if(sense): + self.position += angle + else: + self.position -= angle + if ((current_vactual==0) or (error/current_vactual > current_vactual/deceleration)): + if(acceleration != 0 and abs(current_vactual)vactual: + current_vactual=vactual + else: + current_vactual -= deceleration*gap_time +# liste_vitesse.append(current_vactual*setenv.MOTOR_MICROSTEP) +# liste_time.append(liste_time[len(liste_time)-1] + gap_time) +# liste_distance.append(current_degrees) + print(current_vactual*setenv.MOTOR_MICROSTEP) + self.set_vactual(current_vactual*setenv.MOTOR_MICROSTEP) + gc.collect() + end_time=start_time + self.set_pin_enable(False) + self.set_vactual(0) +# print("============vitesse==========") +# print(liste_vitesse) +# print("============temps============") +# print(liste_time) +# print("============distance============") +# print(liste_distance) +# print("=============================") + + return ('fin de position a : ' + str(self.position) + ' degres') + + def rotate_Closed_Loop(self, + vactual, + degrees = 0, + acceleration = 0, + deceleration = 0, + KP = 1.0, + KI = 0, + KD = 0, + counter = False, + show_stallguard_result = False, + show_tstep = False, + absrel = True): + self.init_vactual() + print(self.get_encoder_position(self.encoder)) + if(absrel): + print(self.get_encoder_position(self.encoder)) + if (degrees - self.get_encoder_position(self.encoder)) < 0: + self.set_direction_shart(False) + sense = False + else: + self.set_direction_shart(True) + sense = True + + vactual = int(round((vactual/0.715)*self.get_steps_per_resolution())) # not tested! + self._stop = False + current_vactual = 0 + last_error = 0 + integral = 0 + + if (vactual<0): + acceleration = -acceleration + + if self.debugmode == True: + if(degrees != 0): + print("vactual: "+str(vactual)+" for "+str(degrees)+" degrees") + + + if (degrees != 0): + current_degrees = self.get_encoder_position(0) + self.set_pin_enable(True) + start_time = time.ticks_ms() + end_time = start_time + current_degrees = 0 + timespan = 0 + + if(degrees - current_degrees < 0): + self.set_set_direction_shart_shart(False) + while((not self._stop) and (current_degrees <= degrees)): + current_degrees = self.get_encoder_position(0) + + error = degrees - current_degrees + integral = integral + error + derivative = error - last_error + speed_adjustment = KP * error + KI * integral + KD * derivative + last_error = error + + start_time= time.ticks_ms() + gap_time = (start_time-end_time)/1000 + rps = current_vactual/self.get_steps_per_resolution()*0.715 + angle = rps*gap_time*360 + current_degrees = current_degrees+angle + timespan +=gap_time + if(sense): + self.position += angle + else: + self.position -= angle + + if ((current_vactual==0) or (error/current_vactual > current_vactual/deceleration)): + if(acceleration != 0 and abs(current_vactual)vactual: + current_vactual=vactual + self.set_vactual(current_vactual) + else: + current_vactual -= deceleration*gap_time + self.set_vactual(current_vactual) + self.set_pin_enable(False) + self.set_vactual(0) + return ('fin de position a : ' + str(self.position) + ' degres') + + def stop(self): + self.set_vactual(0) + time.sleep(1) + self.set_pin_enable(False) + self.p_pin_enable.off() +#----------------------------------------------------------------------- +# This function is for doing Home +# Setup "mode" to 'begin' for Home 0 and 'end' for go to max range +#For uses absolute position +#----------------------------------------------------------------------- + + def go_home(self,mode=False): + self.run_vactual() + if(mode!=False): + if(mode == "begin"): + current_vactual = 0 + if self.pin_home_begin != -1: + self.set_pin_enable(True) + self.set_direction_shart(False) + vactual = int(round((1/0.715)*self.get_steps_per_resolution())) + while self.pin_home_begin.value() == self.init_home_begin: + if(abs(current_vactual)vactual: + current_vactual=vactual + self.set_vactual(current_vactual) + self.set_vactual(0) + time.sleep(0.2) + self.set_direction_shart(True) + current_vactual = 0 + while self.pin_home_begin.value() != self.init_home_begin: + if(abs(current_vactual)vactual: + current_vactual=vactual + self.set_vactual(current_vactual) + else : + print("Any begin sensor setup") + return False + if(mode == "end"): + if self.pin_home_end != -1: + self.set_pin_enable(True) + self.set_direction_shart(True) + vactual = int(round((1.5/0.715)*self.get_steps_per_resolution())) + while self.pin_home_end.value() == self.init_home_end: + if(abs(current_vactual)vactual: + current_vactual=vactual + self.set_vactual(current_vactual) + self.set_vactual(0) + time.sleep(0.2) + self.set_direction_shart(False) + current_vactual = 0 + while self.pin_home_end.value() != self.init_home_end: + if(abs(current_vactual)vactual: + current_vactual=vactual + self.set_vactual(int(round(current_vactual))) + else : + print("Any end sensor setup") + return False + + else: + self.set_voltage_sense(True) + self.set_current_flow(1800) + self.set_iscale_analog(True) + self.set_interpolation(True) + self.set_spread_cycle(True) + self.set_microstepping_resolution(setenv.MOTOR_MICROSTEP) + self.set_internal_resistor_sense(False) + self.set_microstep_resolution_regselect(True) + print(self.rotation(500,degrees=-self.position,acceleration=1000,deceleration=1000)) + self.set_vactual(0) + self.position = 0 + return True + +#----------------------------------------------------------------------- +# return the current position result +#----------------------------------------------------------------------- + + def get_position_degrees(self): + return self.position diff --git a/BM/softuart.py b/BM/softuart.py new file mode 100644 index 0000000..1677765 --- /dev/null +++ b/BM/softuart.py @@ -0,0 +1,56 @@ +from machine import Pin +from rp2 import PIO, StateMachine, asm_pio + + +## ASM +@asm_pio(autopush=True, push_thresh=8, in_shiftdir=PIO.SHIFT_RIGHT, fifo_join=PIO.JOIN_RX) +def uart_rx_mini(): + wait(0, pin, 0) + set(x, 7) [10] + label("bitloop") + in_(pins, 1) + jmp(x_dec, "bitloop") [6] + + +@asm_pio(sideset_init=PIO.OUT_HIGH, out_init=PIO.OUT_HIGH, out_shiftdir=PIO.SHIFT_RIGHT) +def uart_tx(): + pull() + set(x, 7) .side(0) [7] + label("bitloop") + out(pins, 1) [6] + jmp(x_dec, "bitloop") + nop() .side(1) [6] + + + +class UART: + + def __init__(self, rx, tx, baudrate, id): + self.UART_BAUD = baudrate + self.PIO_RX_PIN = Pin(rx, Pin.IN, Pin.PULL_UP) + self.PIO_TX_PIN = Pin(tx, Pin.OUT, value=1) + self.smrx = StateMachine(id, uart_rx_mini, freq=8*self.UART_BAUD, in_base=self.PIO_RX_PIN, jmp_pin=self.PIO_RX_PIN) + self.smrx.active(1) + self.smtx = StateMachine(id + 1, uart_tx, freq=8*self.UART_BAUD, sideset_base=self.PIO_TX_PIN, out_base=self.PIO_TX_PIN) + self.smtx.active(1) + + def deinit(self): + self.smrx.active(0) + self.smtx.active(0) + + def write(self,s): + #self.smtx.put(bytes(s)) + self.smtx.put(s) + return len(s) + + def read(self): + z = [] + + for i in range(100): + buflen = self.smrx.rx_fifo() + + if buflen: + for c in range(buflen): + z.append(self.smrx.get() >> 24) + + return bytes(z) diff --git a/BM/tmc_2209.py b/BM/tmc_2209.py new file mode 100644 index 0000000..09f18a8 --- /dev/null +++ b/BM/tmc_2209.py @@ -0,0 +1,952 @@ +import sys +import time +import math +import setenv + +from machine import Pin +if setenv.MOTOR_SOFT_UART == True: + from softuart import UART +else: + from machine import UART +#----------------------------------------------------------------------- +# this file contains: +# 1. hexadecimal address of the different registers +# 2. bitposition and bitmasks of the different values of each register +# +# Example: +# the register IOIN has the address 0x06 and the first bit shows +# whether the ENABLE (EN/ENN) Pin is currently HIGH or LOW +#----------------------------------------------------------------------- + +#addresses +GCONF = 0x00 +GSTAT = 0x01 +IFCNT = 0x02 +IOIN = 0x06 +IHOLD_IRUN = 0x10 +TSTEP = 0x12 +TCOOLTHRS = 0x14 +SGTHRS = 0x40 +SG_RESULT = 0x41 +MSCNT = 0x6A +CHOPCONF = 0x6C +DRVSTATUS = 0x6F +VACTUAL = 0x22 + +#GCONF +i_scale_analog = 1<<0 +internal_rsense = 1<<1 +en_spreadcycle = 1<<2 +shaft = 1<<3 +index_otpw = 1<<4 +index_step = 1<<5 +mstep_reg_select = 1<<7 + +#GSTAT +reset = 1<<0 +drv_err = 1<<1 +uv_cp = 1<<2 + +#CHOPCONF +vsense = 1<<17 +msres0 = 1<<24 +msres1 = 1<<25 +msres2 = 1<<26 +msres3 = 1<<27 +intpol = 1<<28 + +#IOIN +io_enn = 1<<0 +io_step = 1<<7 +io_spread = 1<<8 +io_dir = 1<<9 + +#DRVSTATUS +stst = 1<<31 +stealth = 1<<30 +cs_actual = 31<<16 +t157 = 1<<11 +t150 = 1<<10 +t143 = 1<<9 +t120 = 1<<8 +olb = 1<<7 +ola = 1<<6 +s2vsb = 1<<5 +s2vsa = 1<<4 +s2gb = 1<<3 +s2ga = 1<<2 +ot = 1<<1 +otpw = 1<<0 + +#IHOLD_IRUN +ihold = 31<<0 +irun = 31<<8 +iholddelay = 15<<16 + +#SGTHRS +sgthrs = 255<<0 + +#others +mres_256 = 0 +mres_128 = 1 +mres_64 = 2 +mres_32 = 3 +mres_16 = 4 +mres_8 = 5 +mres_4 = 6 +mres_2 = 7 +mres_1 = 8 + + +#----------------------------------------------------------------------- +# TMC_UART LogLevl +#----------------------------------------------------------------------- +class Loglevel(): + none = 0 + error = 10 + info = 20 + debug = 30 + all = 100 + + +#----------------------------------------------------------------------- +# TMC_UART +# +# this class is used to communicate with the TMC via UART +# it can be used to change the settings of the TMC. +# like the current or the microsteppingmode +#----------------------------------------------------------------------- +class TMC_UART: + mtr_id = 0 + ser = None + rFrame = [0x55, 0, 0, 0] + wFrame = [0x55, 0, 0, 0 , 0, 0, 0, 0] + communication_pause = 0 + +#----------------------------------------------------------------------- +# constructor +#----------------------------------------------------------------------- + def __init__(self, rx, tx, serialport, baudrate): + if setenv.MOTOR_SOFT_UART == True: + self.ser = UART(rx=rx, tx=tx, baudrate=baudrate, id=serialport) + print("soft_tmc") + else: + self.ser = UART(serialport,baudrate,rx=Pin(rx), tx=Pin(tx)) + print("hard_tmc",serialport,baudrate,rx ,tx) + + self.mtr_id = 0 + #self.ser.timeout = 20000/baudrate # adjust per baud and hardware. Sequential reads without some delay fail. + self.communication_pause = 500 / baudrate # adjust per baud and hardware. Sequential reads without some delay fail. + +#----------------------------------------------------------------------- +# destructor +#----------------------------------------------------------------------- + def deinit(self): + self.ser.deinit() + +#----------------------------------------------------------------------- +# this function calculates the crc8 parity bit +#----------------------------------------------------------------------- + def compute_crc8_atm(self, datagram, initial_value=0): + crc = initial_value + + for byte in datagram: # Iterate bytes in data + for _ in range(0, 8): # Iterate bits in byte + if (crc >> 7) ^ (byte & 0x01): + crc = ((crc << 1) ^ 0x07) & 0xFF + else: + crc = (crc << 1) & 0xFF + + byte = byte >> 1 # Shift to next bit + + return crc + +#----------------------------------------------------------------------- +# reads the registry on the TMC with a given address. +# returns the binary value of that register +#----------------------------------------------------------------------- + def read_reg(self, reg): + self.rFrame[1] = self.mtr_id + self.rFrame[2] = reg + self.rFrame[3] = self.compute_crc8_atm(self.rFrame[:-1]) + rt = self.ser.write(bytes(self.rFrame)) + + if rt != len(self.rFrame): +# print(f"TMC2209: Err in write", file=sys.stderr) + return False + + # time.sleep(self.communication_pause) # adjust per baud and hardware. Sequential reads without some delay fail. + rtn = self.ser.read() #read what it self + + if rtn == None: +# print("TMC2209: Err in read") + return "" + + print("rtn[7:11] :",rtn[7:11] , rtn[7] ,rtn[8] , rtn[9] , rtn[10] , " , reg : ",reg) + return rtn[7:11] +#----------------------------------------------------------------------- +# this function tries to read the registry of the TMC 10 times +# if a valid answer is returned, this function returns it as an integer +#----------------------------------------------------------------------- + def read_int(self, reg): + tries = 0 + + while True: + rtn = self.read_reg(reg) + tries += 1 + + if len(rtn) >= 4: + break + else: + pass + print(f"TMC2209: did not get the expected 4 data bytes. Instead got {str(len(rtn))} Bytes") + + if tries >= 10: + print("TMC2209: after 10 tries not valid answer. exiting") + print("TMC2209: is Stepper Powersupply switched on ?") + raise SystemExit + + return int.from_bytes(rtn, 'big', False) + +#----------------------------------------------------------------------- +# this function can write a value to the register of the tmc +# 1. use read_int to get the current setting of the TMC +# 2. then modify the settings as wished +# 3. write them back to the driver with this function +#----------------------------------------------------------------------- + def write_reg(self, reg, val): + #self.ser.reset_output_buffer() + #self.ser.reset_input_buffer() + + self.wFrame[1] = self.mtr_id + self.wFrame[2] = reg | 0x80; # set write bit + self.wFrame[3] = 0xFF & (val>>24) + self.wFrame[4] = 0xFF & (val>>16) + self.wFrame[5] = 0xFF & (val>>8) + self.wFrame[6] = 0xFF & val + self.wFrame[7] = self.compute_crc8_atm(self.wFrame[:-1]) + print("x" ,bytes(self.wFrame),self.wFrame) + + rtn = self.ser.write(bytes(self.wFrame)) + + if rtn != len(self.wFrame): +# print(f"TMC2209: Err in write", file=sys.stderr) + return False + + time.sleep(self.communication_pause) + return True + +#----------------------------------------------------------------------- +# this function als writes a value to the register of the TMC +# but it also checks if the writing process was successfully by checking +# the InterfaceTransmissionCounter before and after writing +#----------------------------------------------------------------------- + def write_reg_check(self, reg, val): + ifcnt1 = self.read_int(IFCNT) + self.write_reg(reg, val) + ifcnt2 = self.read_int(IFCNT) + + if ifcnt1 >= ifcnt2: + print("TMC2209: writing not successful!") + print(f"reg: {reg} val: {val}") + print(f"ifcnt: {ifcnt1} {ifcnt2}") + return False + + return True + + +#----------------------------------------------------------------------- +# this sets a specific bit to 1 +#----------------------------------------------------------------------- + def set_bit(self, value, bit): + return value | (bit) + +#----------------------------------------------------------------------- +# this sets a specific bit to 0 +#----------------------------------------------------------------------- + def clear_bit(self, value, bit): + return value & ~(bit) + + +#----------------------------------------------------------------------- +# TMC_2209 +# +# this class has two different functions: +# 1. change setting in the TMC-driver via UART +# 2. move the motor via STEP/DIR pins +#----------------------------------------------------------------------- +class TMC2209: + + tmc_uart = None + pin_step = 1 + p_pin_step = -1 + p_pin_direction = -1 + p_pin_enable = -1 + debugmode = False + _micro_stepping_resolution = -1 + _loglevel = Loglevel.info + +#----------------------------------------------------------------------- +# constructor +#----------------------------------------------------------------------- + def __init__(self, + rx=setenv.MOTOR_RX_PIN, + tx=setenv.MOTOR_TX_PIN, + pin_step=setenv.MOTOR_STEP_PIN, + pin_direction=setenv.MOTOR_DIR_PIN, + pin_enable=setenv.MOTOR_EN_PIN, + baudrate=setenv.MOTOR_BAUDRATE, + serialport=setenv.MOTOR_NUMBER, + ms_resolution=setenv.MOTOR_MICROSTEP): + self.tmc_uart = TMC_UART(rx, tx, serialport, baudrate) + self.pin_step = pin_step + self.p_pin_step = Pin(pin_step, Pin.OUT) + self.p_pin_direction = Pin(pin_direction, Pin.OUT) + self.p_pin_enable = Pin(pin_enable, Pin.OUT) + #self.set_microstepping_resolution(setenv.MOTOR_MICROSTEP) + #self.clear_general_stat() + +#----------------------------------------------------------------------- +# destructor +#----------------------------------------------------------------------- + def __del__(self): + if(self.debugmode == True): + print("TMC2209: Deinit") + + self.set_pin_enable(False) + self.tmc_uart.deinit() + + +#----------------------------------------------------------------------- +# read the register Adress "DRVSTATUS" and prints all current setting +#----------------------------------------------------------------------- + def driver_status(self): + print("TMC2209: ---") + print("TMC2209: DRIVER STATUS:") + drvstatus = self.tmc_uart.read_int(DRVSTATUS) + + if self.debugmode == True: + print("TMC2209:", bin(drvstatus)) + + if drvstatus & stst: + print("TMC2209: Info: motor is standing still") + else: + print("TMC2209: Info: motor is running") + + if drvstatus & stealth: + print("TMC2209: Info: motor is running on StealthChop") + else: + print("TMC2209: Info: motor is running on SpreadCycle") + + cs_act = drvstatus & cs_actual + cs_act = cs_act >> 16 + print(f"TMC2209: CS actual: {str(cs_act)}") + + if drvstatus & olb: + print("TMC2209: Warning: Open load detected on phase B") + + if drvstatus & ola: + print("TMC2209: Warning: Open load detected on phase A") + + if drvstatus & s2vsb: + print("TMC2209: Error: Short on low-side MOSFET detected on phase B. The driver becomes disabled") + + if drvstatus & s2vsa: + print("TMC2209: Error: Short on low-side MOSFET detected on phase A. The driver becomes disabled") + + if drvstatus & s2gb: + print("TMC2209: Error: Short to GND detected on phase B. The driver becomes disabled. ") + + if drvstatus & s2ga: + print("TMC2209: Error: Short to GND detected on phase A. The driver becomes disabled. ") + + if drvstatus & ot: + print("TMC2209: Error: Driver Overheating!") + + if drvstatus & otpw: + print("TMC2209: Warning: Driver Overheating Prewarning!") + +#----------------------------------------------------------------------- +# read the register Adress "GCONF" and prints all current setting +#----------------------------------------------------------------------- + def general_config(self): + print("TMC2209: ---") + print("TMC2209: GENERAL CONFIG") + gconf = self.tmc_uart.read_int(GCONF) + + if self.debugmode == True: + print("TMC2209:", bin(gconf)) + + if gconf & i_scale_analog: + print("TMC2209: Driver is using voltage supplied to VREF as current reference") + else: + print("TMC2209: Driver is using internal reference derived from 5VOUT") + + if gconf & internal_rsense: + print("TMC2209: Internal sense resistors. Use current supplied into VREF as reference.") + print("TMC2209: VREF pin internally is driven to GND in this mode.") + print("TMC2209: This will most likely destroy your driver!!!") + raise SystemExit + else: + print("TMC2209: Operation with external sense resistors") + + if gconf & en_spreadcycle: + print("TMC2209: SpreadCycle mode enabled") + else: + print("TMC2209: StealthChop PWM mode enabled") + + if gconf & shaft: + print("TMC2209: Inverse motor direction") + else: + print("TMC2209: normal motor direction") + + if gconf & index_otpw: + print("TMC2209: INDEX pin outputs overtemperature prewarning flag") + else: + print("TMC2209: INDEX shows the first microstep position of sequencer") + + if gconf & index_step: + print("TMC2209: INDEX output shows step pulses from internal pulse generator") + else: + print("TMC2209: INDEX output as selected by index_otpw") + + if gconf & mstep_reg_select: + print("TMC2209: Microstep resolution selected by MSTEP register") + else: + print("TMC2209: Microstep resolution selected by pins MS1, MS2") + +#----------------------------------------------------------------------- +# read the register Adress "GSTAT" and prints all current setting +#----------------------------------------------------------------------- + def general_stat(self): + print("TMC2209: ---") + print("TMC2209: GENERAL STAT") + gstat = self.tmc_uart.read_int(GSTAT) + + if self.debugmode == True: + print("TMC2209:", bin(gstat)) + + if gstat & reset: + print("TMC2209: The Driver has been reset since the last read access to GSTAT") + + if gstat & drv_err: + print("TMC2209: The driver has been shut down due to overtemperature or short circuit detection since the last read access") + + if gstat & uv_cp: + print("TMC2209: Undervoltage on the charge pump. The driver is disabled in this case") + +#----------------------------------------------------------------------- +# read the register Adress "GSTAT" and prints all current setting +#----------------------------------------------------------------------- + def clear_general_stat(self): + gstat = self.tmc_uart.read_int(GSTAT) + gstat = self.tmc_uart.set_bit(gstat, reset) + gstat = self.tmc_uart.set_bit(gstat, drv_err) + self.tmc_uart.write_reg_check(GSTAT, gstat) + +#----------------------------------------------------------------------- +# read the register Adress "IOIN" and prints all current setting +#----------------------------------------------------------------------- + def ioin(self): + print("TMC2209: ---") + print("TMC2209: INPUTS") + ioin = self.tmc_uart.read_int(IOIN) + + if self.debugmode == True: + print("TMC2209:", bin(ioin)) + + if ioin & io_spread: + print("TMC2209: spread is high") + else: + print("TMC2209: spread is low") + + if ioin & io_dir: + print("TMC2209: dir is high") + else: + print("TMC2209: dir is low") + + if ioin & io_step: + print("TMC2209: step is high") + else: + print("TMC2209: step is low") + + if ioin & io_enn: + print("TMC2209: en is high") + else: + print("TMC2209: en is low") + +#----------------------------------------------------------------------- +# read the register Adress "CHOPCONF" and prints all current setting +#----------------------------------------------------------------------- + def chopper_control(self): + print("TMC2209: ---") + print("TMC2209: CHOPPER CONTROL") + chopconf = self.tmc_uart.read_int(CHOPCONF) + + if self.debugmode == True: + print("TMC2209:", bin(chopconf)) + + print(f"TMC2209: native {str(self.get_microstepping_resolution())} microstep setting") + + if chopconf & intpol: + print("TMC2209: interpolation to 256 microsteps") + + if chopconf & vsense: + print("TMC2209: 1: High sensitivity, low sense resistor voltage") + else: + print("TMC2209: 0: Low sensitivity, high sense resistor voltage") + +#----------------------------------------------------------------------- +# enables or disables the motor current output +#----------------------------------------------------------------------- + def set_pin_enable(self, enabled): + if enabled: + self.p_pin_enable.off() +# print(f"TMC2209: Motor output active = {enabled}") + else: + self.p_pin_enable.on() + # print("en",self.p_pin_enable.value(),enabled) +# print(f"TMC2209: Motor output active = {enabled}") + +#----------------------------------------------------------------------- +# sets the motor shaft direction to the given value: 0 = CCW; 1 = CW +#----------------------------------------------------------------------- + def set_pin_direction(self, direction): + if (self.p_pin_direction.value() != direction): +# print("change",self.p_pin_direction.value() , direction) + + if direction: + self.p_pin_direction.on() + else: + self.p_pin_direction.off() +# print("value",self.p_pin_direction.value() ) + + +#----------------------------------------------------------------------- +# enables or disables the motor step output +#----------------------------------------------------------------------- + def set_pin_step(self, enabled): + if enabled: + self.p_pin_step.on() + else: + self.p_pin_step.off() + +#----------------------------------------------------------------------- +# returns the motor shaft direction: 0 = CCW; 1 = CW +#----------------------------------------------------------------------- + def get_direction_shart(self): + + return self.tmc_uart.read_int(GCONF) & shaft + + +#----------------------------------------------------------------------- +# sets the motor shaft direction to the given value: 0 = CCW; 1 = CW +#----------------------------------------------------------------------- + def set_direction_shart(self, direction): + gconf = self.tmc_uart.read_int(GCONF) + if (self.get_direction_shart()/8!=direction): + + if direction: + if self.debugmode == True: + print("TMC2209: write inverse motor direction") + + gconf = self.tmc_uart.set_bit(gconf, shaft) + else: + if self.debugmode == True: + print("TMC2209: write normal motor direction") + + gconf = self.tmc_uart.clear_bit(gconf, shaft) +# print(direction) + self.tmc_uart.write_reg_check(GCONF, gconf) + time.sleep_us(100) + +#----------------------------------------------------------------------- +# return whether the tmc inbuilt interpolation is active +#----------------------------------------------------------------------- + def get_interpolation(self): + return self.tmc_uart.read_int(CHOPCONF) & intpol + +#----------------------------------------------------------------------- +# enables the tmc inbuilt interpolation of the steps to 256 microsteps +#----------------------------------------------------------------------- + def set_interpolation(self, enabled): + chopconf = self.tmc_uart.read_int(CHOPCONF) + + if enabled: + chopconf = self.tmc_uart.set_bit(chopconf, intpol) + else: + chopconf = self.tmc_uart.clear_bit(chopconf, intpol) + + if self.debugmode == True: + print(f"TMC2209: writing microstep interpolation setting =", enabled) + + self.tmc_uart.write_reg_check(CHOPCONF, chopconf) + +#----------------------------------------------------------------------- +# return whether spreadcycle (1) is active or stealthchop (0) +#----------------------------------------------------------------------- + def get_spread_cycle(self): + return self.tmc_uart.read_int(GCONF) & en_spreadcycle + +#----------------------------------------------------------------------- +# enables spreadcycle (1) or stealthchop (0) +#----------------------------------------------------------------------- + def set_spread_cycle(self, enabled): + gconf = self.tmc_uart.read_int(GCONF) + + if enabled: + if self.debugmode == True: + print("TMC2209: Spreadcycle = activated") + + gconf = self.tmc_uart.set_bit(gconf, en_spreadcycle) + else: + if self.debugmode == True: + print("TMC2209: Stealthchop = deactivated") + + gconf = self.tmc_uart.clear_bit(gconf, en_spreadcycle) + + self.tmc_uart.write_reg_check(GCONF, gconf) + +#----------------------------------------------------------------------- +# returns the current native microstep resolution (1-256) +#----------------------------------------------------------------------- + def get_microstepping_resolution(self): + chopconf = self.tmc_uart.read_int(CHOPCONF) + print("chopconf : ", chopconf) + msresdezimal = chopconf & (msres0 | msres1 | msres2 | msres3) + msresdezimal = msresdezimal >> 24 + msresdezimal = 8 - msresdezimal + self._micro_stepping_resolution = int(math.pow(2, msresdezimal)) + + return self._micro_stepping_resolution + +#----------------------------------------------------------------------- +# sets the current native microstep resolution (1,2,4,8,16,32,64,128,256) +#----------------------------------------------------------------------- + def set_microstepping_resolution(self, msres): + chopconf = self.tmc_uart.read_int(CHOPCONF) + chopconf = chopconf & (~msres0 | ~msres1 | ~msres2 | ~msres3) #setting all bits to zero + print("chopconf 1 :",chopconf) + + msresdezimal = int(math.log(msres, 2)) + msresdezimal = 8 - msresdezimal + print("msresdezimal 2 :",msresdezimal) + + chopconf = int(chopconf) & int(4043309055) + print("chopconf 2 :",chopconf) + + chopconf = chopconf | msresdezimal << 24 + print("chopconf 3 :",chopconf) + + if self.debugmode == True: + print(f"TMC2209: writing {str(msres)} microstep setting") + + self.tmc_uart.write_reg_check(CHOPCONF, chopconf) + self.set_microstep_resolution_regselect(True) + + +#----------------------------------------------------------------------- +# sets the register bit "mstep_reg_select" to 1 or 0 depending to the given value. +# this is needed to set the microstep resolution via UART +# this method is called by "setMicrosteppingResolution" +#----------------------------------------------------------------------- + def set_microstep_resolution_regselect(self, enabled): + gconf = self.tmc_uart.read_int(GCONF) + print("gconf1 :",gconf) + + if enabled: + gconf = self.tmc_uart.set_bit(gconf, mstep_reg_select) + else: + gconf = self.tmc_uart.clear_bit(gconf, mstep_reg_select) + + if self.debugmode == True: + print(f"TMC2209: writing MStep Reg Select = {enabled}") + print("gconf2 :",gconf) + + self.tmc_uart.write_reg_check(GCONF, gconf) + +#----------------------------------------------------------------------- +# returns how many steps are needed for one revolution +#----------------------------------------------------------------------- + def get_steps_per_resolution(self): + return 200 * self.get_microstepping_resolution() + +#----------------------------------------------------------------------- +# returns the current Microstep counter. +# Indicates actual position in the microstep table for CUR_A +#----------------------------------------------------------------------- + def get_microstep_counter(self, in_steps = False, offset = 0): + mscnt = self.tmc_uart.read_int(MSCNT) + + if not in_steps: + return mscnt + + return round((4 * self._micro_stepping_resolution) - ((mscnt - 64) * (self._micro_stepping_resolution * 4) / 1024) - 1) + offset + +#----------------------------------------------------------------------- +# returns how many steps are needed for one rotation +#----------------------------------------------------------------------- + def get_steps_per_rotation(self): + return self.get_steps_per_resolution() * 21 + +#----------------------------------------------------------------------- +# return the current stallguard result +# its will be calculated with every fullstep +# higher values means a lower motor load +#----------------------------------------------------------------------- + def get_tstep(self): + return self.tmc_uart.read_int(TSTEP) +ehyfbzeyfeunz,ujefz +#----------------------------------------------------------------------- +# sets the register bit "VACTUAL" to to a given value +# VACTUAL allows moving the motor by UART control. +# It gives the motor velocity in +-(2^23)-1 [μsteps / t] +# 0: Normal operation. Driver reacts to STEP input +#----------------------------------------------------------------------- + def set_vactual(self, value): + self.tmc_uart.write_reg_check(VACTUAL, int(round(value))) + +#----------------------------------------------------------------------- +# return the current stallguard result +# its will be calculated with every fullstep +# higher values means a lower motor load +#----------------------------------------------------------------------- + def get_stallguard(self): + return self.tmc_uart.read_int(SG_RESULT) + +#----------------------------------------------------------------------- +# sets the register bit "SGTHRS" to to a given value +# this is needed for the stallguard interrupt callback +# SG_RESULT becomes compared to the double of this threshold. +# SG_RESULT ≤ SGTHRS*2 +#----------------------------------------------------------------------- + def set_stallguard_threshold(self, threshold): + if self.debugmode == True: + print("TMC2209: sgthrs =", bin(threshold)) + + self.tmc_uart.write_reg_check(SGTHRS, threshold) + +#----------------------------------------------------------------------- +# This is the lower threshold velocity for switching +# on smart energy CoolStep and StallGuard to DIAG output. (unsigned) +#----------------------------------------------------------------------- + def set_coolstep_threshold(self, threshold): + if self.debugmode == True: + print("TMC2209: tcoolthrs =", bin(threshold)) + + self.tmc_uart.write_reg_check(TCOOLTHRS, threshold) + +#----------------------------------------------------------------------- +# set a function to call back, when the driver detects a stall +# via stallguard +# high value on the diag pin can also mean a driver error +#----------------------------------------------------------------------- + def set_stallguard_callback(self, stallguard_pin, threshold, callback, min_speed = 2000): + self.set_stallguard_threshold(threshold) + self.set_coolstep_threshold(min_speed) + + if self.debugmode == True: + print("TMC2209: setup stallguard callback") + + p25 = Pin(stallguard_pin, Pin.IN, Pin.PULL_DOWN) + p25.irq(trigger=Pin.IRQ_RISING, handler=callback) + + +#----------------------------------------------------------------------- +# return whether Vref (1) or 5V (0) is used for current scale +#----------------------------------------------------------------------- + def get_iscale_analog(self): + return self.tmc_uart.read_int(GCONF) & i_scale_analog + +#----------------------------------------------------------------------- +# sets Vref (1) or 5V (0) for current scale +#----------------------------------------------------------------------- + def set_iscale_analog(self, enabled): + gconf = self.tmc_uart.read_int(GCONF) + + if enabled: + if self.debugmode == True: + print("TMC2209: activated Vref for current scale") + + gconf = self.tmc_uart.set_bit(gconf, i_scale_analog) + else: + if self.debugmode == True: + print("TMC2209: activated 5V-out for current scale") + + gconf = self.tmc_uart.clear_bit(gconf, i_scale_analog) + + self.tmc_uart.write_reg_check(GCONF, gconf) + +#----------------------------------------------------------------------- +# returns which sense resistor voltage is used for current scaling +# 0: Low sensitivity, high sense resistor voltage +# 1: High sensitivity, low sense resistor voltage +#----------------------------------------------------------------------- + def get_voltage_sense(self): + return self.tmc_uart.read_int(CHOPCONF) & vsense + +#----------------------------------------------------------------------- +# sets which sense resistor voltage is used for current scaling +# 0: Low sensitivity, high sense resistor voltage +# 1: High sensitivity, low sense resistor voltage +#----------------------------------------------------------------------- + def set_voltage_sense(self, enabled): + chopconf = self.tmc_uart.read_int(CHOPCONF) + + if enabled: + if self.debugmode == True: + print("TMC2209: activated High sensitivity, low sense resistor voltage") + + chopconf = self.tmc_uart.set_bit(chopconf, vsense) + else: + if self.debugmode == True: + print("TMC2209: activated Low sensitivity, high sense resistor voltage") + + chopconf = self.tmc_uart.clear_bit(chopconf, vsense) + + self.tmc_uart.write_reg_check(CHOPCONF, chopconf) + +#----------------------------------------------------------------------- +# returns which sense resistor voltage is used for current scaling +# 0: Low sensitivity, high sense resistor voltage +# 1: High sensitivity, low sense resistor voltage +#----------------------------------------------------------------------- + def get_internal_resistor_sense(self): + return self.tmc_uart.read_int(GCONF) & internal_rsense + +#----------------------------------------------------------------------- +# sets which sense resistor voltage is used for current scaling +# 0: Low sensitivity, high sense resistor voltage +# 1: High sensitivity, low sense resistor voltage +#----------------------------------------------------------------------- + def set_internal_resistor_sense(self, enabled): + gconf = self.tmc_uart.read_int(GCONF) + + if enabled: + if self.debugmode == True: + print("TMC2209: activated internal sense resistors.") + + gconf = self.tmc_uart.set_bit(gconf, internal_rsense) + else: + if self.debugmode == True: + print("TMC2209: activated operation with external sense resistors") + + gconf = self.tmc_uart.clear_bit(gconf, internal_rsense) + + self.tmc_uart.write_reg_check(GCONF, gconf) + +#----------------------------------------------------------------------- +# sets the current scale (CS) for Running and Holding +# and the delay, when to be switched to Holding current +# IHold = 0-31; IRun = 0-31; IHoldDelay = 0-15 +#----------------------------------------------------------------------- + def set_irun_ihold(self, IHold, IRun, IHoldDelay): + ihold_irun = 0 + ihold_irun = ihold_irun | IHold << 0 + ihold_irun = ihold_irun | IRun << 8 + ihold_irun = ihold_irun | IHoldDelay << 16 + + if self.debugmode == True: + print("TMC2209: ihold_irun =", bin(ihold_irun)) + + self.tmc_uart.write_reg_check(IHOLD_IRUN, ihold_irun) + +#----------------------------------------------------------------------- +# sets the current flow for the motor +# run_current in mA +# check whether Vref is actually 1.2V +#----------------------------------------------------------------------- + def set_current_flow(self, run_current, hold_current_multiplier = 0.5, hold_current_delay = 10, Vref = setenv.MOTOR_VREF): + CS_IRun = 0 + Rsense = 0.11 + Vfs = 0 + + if self.get_voltage_sense(): + if self.debugmode == True: + print("TMC2209: Vsense: 1") + + Vfs = 0.180 * Vref / 2.5 + else: + if self.debugmode == True: + print("TMC2209: Vsense: 0") + + Vfs = 0.325 * Vref / 2.5 + + CS_IRun = 32.0 * 1.41421 * run_current / 1000.0 * (Rsense + 0.02) / Vfs - 1 + CS_IRun = min(CS_IRun, 31) + CS_IRun = max(CS_IRun, 0) + CS_IHold = hold_current_multiplier * CS_IRun + CS_IRun = round(CS_IRun) + CS_IHold = round(CS_IHold) + hold_current_delay = round(hold_current_delay) + + if self.debugmode == True: + print("TMC2209: CS_IRun =", CS_IRun) + print("TMC2209: CS_IHold =", CS_IHold) + print("TMC2209: Delay =", hold_current_delay) + + self.set_irun_ihold(CS_IHold, CS_IRun, hold_current_delay) + +#----------------------------------------------------------------------- +# tests the EN, DIR and STEP pin +# this sets the EN, DIR and STEP pin to HIGH, LOW and HIGH +# and checks the IOIN Register of the TMC meanwhile +#----------------------------------------------------------------------- + def test_pins(self): + pin_dir_ok = pin_step_ok = pin_en_ok = True + + self.p_pin_step.on() + self.p_pin_direction.on() + self.p_pin_enable.on() + + time.sleep(0.1) + ioin = self.tmc_uart.read_int(IOIN) + + if not(ioin & io_dir): + pin_dir_ok = False + + if not(ioin & io_step): + pin_step_ok = False + + if not(ioin & io_enn): + pin_en_ok = False + + self.p_pin_step.off() + self.p_pin_direction.off() + self.p_pin_enable.off() + + time.sleep(0.1) + ioin = self.tmc_uart.read_int(IOIN) + + if ioin & io_dir: + pin_dir_ok = False + + if ioin & io_step: + pin_step_ok = False + + if ioin & io_enn: + pin_en_ok = False + + self.p_pin_step.on() + self.p_pin_direction.on() + self.p_pin_enable.on() + + time.sleep(0.1) + ioin = self.tmc_uart.read_int(IOIN) + + if not(ioin & io_dir): + pin_dir_ok = False + + if not(ioin & io_step): + pin_step_ok = False + + if not(ioin & io_enn): + pin_en_ok = False + + self.set_pin_enable(False) + + print("---") + print(f"Pin STEP: \t{pin_step_ok}") + print(f"Pin DIRECTION: \t{pin_dir_ok}") + print(f"Pin ENABLE: \t{pin_en_ok}") + print("---") diff --git a/Clean_TMC2209/CMakeLists.txt b/Clean_TMC2209/CMakeLists.txt new file mode 100644 index 0000000..ddc6b17 --- /dev/null +++ b/Clean_TMC2209/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.12) + +set(PROJECT_NAME "Uart_TMC2209_test") +set(PICO_SDK_PATH "E:/Beyon_Motion/pico-sdk") +set(PICO_TOOLCHAIN_PATH "C:/Users/spide/scoop/apps/gcc-arm-none-eabi/current/bin") +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +include(${PICO_SDK_PATH}/external/pico_sdk_import.cmake) + +project(${PROJECT_NAME} C CXX ASM) # Ajout de CXX ici + +pico_sdk_init() + +add_executable(${PROJECT_NAME} + main.c + Tmc2209.c + Tmc_uart.c +) + + +target_link_libraries(${PROJECT_NAME} + pico_stdlib + hardware_i2c + hardware_uart + hardware_dma + # TMC2209 +) + +pico_enable_stdio_usb(${PROJECT_NAME} 1) +pico_enable_stdio_uart(${PROJECT_NAME} 0) + +pico_add_extra_outputs(${PROJECT_NAME}) diff --git a/Clean_TMC2209/Tmc2209.c b/Clean_TMC2209/Tmc2209.c new file mode 100644 index 0000000..754750f --- /dev/null +++ b/Clean_TMC2209/Tmc2209.c @@ -0,0 +1,830 @@ +// Tmc2209.c +#include "Tmc2209.h" + + +#define portMAX_DELAY 10 +#define UART_BUFFER_SIZE 64 // Taille du tampon UART, à ajuster selon vos besoins + +// Adresses des registres +#define GCONF 0x00 +#define GSTAT 0x01 +#define IFCNT 0x02 +#define IOIN 0x06 +#define IHOLD_IRUN 0x10 +#define TSTEP 0x12 +#define TCOOLTHRS 0x14 +#define SGTHRS 0x40 +#define SG_RESULT 0x41 +#define MSCNT 0x6A +#define CHOPCONF 0x6C +#define DRVSTATUS 0x6F +#define VACTUAL 0x22 + +// Bits associés à GCONF +#define I_SCALE_ANALOG (1 << 0) +#define INTERNAL_RSENSE (1 << 1) +#define EN_SPREADCYCLE (1 << 2) +#define SHAFT (1 << 3) +#define INDEX_OTPW (1 << 4) +#define INDEX_STEP (1 << 5) +#define MSTEP_REG_SELECT (1 << 7) + +// Bits associés à GSTAT +#define RESET (1 << 0) +#define DRV_ERR (1 << 1) +#define UV_CP (1 << 2) + +// Bits associés à CHOPCONF +#define VSENSE (1 << 17) +#define MSRES0 (1 << 24) +#define MSRES1 (1 << 25) +#define MSRES2 (1 << 26) +#define MSRES3 (1 << 27) +#define INTPOL (1 << 28) + +// Bits associés à IOIN +#define IO_ENN (1 << 0) +#define IO_STEP (1 << 7) +#define IO_SPREAD (1 << 8) +#define IO_DIR (1 << 9) + +// Bits associés à DRVSTATUS +#define STST (1U << 31) +#define STEALTH (1U << 30) +#define CS_ACTUAL (31U << 16) +#define T157 (1 << 11) +#define T150 (1 << 10) +#define T143 (1 << 9) +#define T120 (1 << 8) +#define OLB (1 << 7) +#define OLA (1 << 6) +#define S2VSB (1 << 5) +#define S2VSA (1 << 4) +#define S2GB (1 << 3) +#define S2GA (1 << 2) +#define OT (1 << 1) +#define OTPW (1 << 0) + +// Bits associés à IHOLD_IRUN +#define IHOLD (31 << 0) +#define IRUN (31 << 8) +#define IHOLDDELAY (15 << 16) + +// Bits associés à SGTHRS +#define SGTHRS_VAL (255 << 0) + +// Autres constantes +#define MRES_256 0 +#define MRES_128 1 +#define MRES_64 2 +#define MRES_32 3 +#define MRES_16 4 +#define MRES_8 5 +#define MRES_4 6 +#define MRES_2 7 +#define MRES_1 8 + + + + +void TMC2209_Init(TMC2209* tmc2209,TMC_UART* serial_instance) { + + tmc2209->serial_instance = serial_instance; + tmc2209->mtr_id = 0x00; + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = 0x00; + tmc2209->rFrame[2] = 0x00; + tmc2209->rFrame[3] = 0x00; + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = 0x00; + tmc2209->wFrame[2] = 0x00; + tmc2209->wFrame[3] = 0x00; + tmc2209->wFrame[4] = 0x00; + tmc2209->wFrame[5] = 0x00; + tmc2209->wFrame[6] = 0x00; + tmc2209->wFrame[7] = 0x00; + tmc2209->result[0] = 0x00; + tmc2209->result[1] = 0x00; + tmc2209->result[2] = 0x00; + tmc2209->result[3] = 0x00; + + // return true; +} + +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value) { + uint8_t crc = initial_value; + + size_t i; + int j; + for (i = 0; i < length; i++) { + uint8_t byte = datagram[i]; + for (j = 0; j < 8; j++) { + if ((crc >> 7) ^ (byte & 0x01)) { + crc = ((crc << 1) ^ 0x07) & 0xFF; + } else { + crc = (crc << 1) & 0xFF; + } + byte >>= 1; + } + } + return crc; +} + + + +uint64_t *read_reg(TMC2209* tmc2209, int reg) { + + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = tmc2209->mtr_id; + tmc2209->rFrame[2] = reg; + tmc2209->rFrame[3] = compute_crc8_atm(tmc2209->rFrame, 3, 0); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[3]); + + uint64_t temp_result[12] = {0x00}; + + int i = 0; + uint32_t start_time = time_us_32(); // Temps de départ en microsecondes + while (time_us_32() - start_time < 2000 && i < 12) { // Lire pendant 2 ms + if (uart_is_readable(tmc2209->serial_instance->UART_ID)) { + uint64_t tempchar = uart_getc(tmc2209->serial_instance->UART_ID); + temp_result[i] = tempchar; + i++; + } + } + + if (temp_result[11] == 0 ){ + tmc2209->result[0] = temp_result[6]; + tmc2209->result[1] = temp_result[7]; + tmc2209->result[2] = temp_result[8]; + tmc2209->result[3] = temp_result[9]; + }else{ + tmc2209->result[0] = temp_result[7]; + tmc2209->result[1] = temp_result[8]; + tmc2209->result[2] = temp_result[9]; + tmc2209->result[3] = temp_result[10]; + } + + sleep_ms(3); + return tmc2209->result; +} + + +uint32_t read_int(TMC2209* tmc2209, int reg) { + uint8_t data[4]; // Array to store the 4-byte response + + for (int tries = 0; tries < 10; tries++) { + uint64_t* rtn = read_reg(tmc2209, reg); + + if (rtn == NULL) { + printf("TMC2209: read_reg failed to return data\n"); + continue; + } + + if (sizeof(*rtn) >= sizeof(data)) { + for (int i = 0; i < sizeof(data); i++) { + data[i] = (uint8_t)(*rtn >> (8 * (sizeof(*rtn) - i - 1))); + } + } else { + printf("TMC2209: expected at least 4 bytes, got %zu Bytes\n", sizeof(*rtn)); + continue; + } + + uint32_t result_int = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; + + if (!(result_int & 0x80000000)) { + return result_int; + } else { + printf("TMC2209: error in register response: 0x%08X\n", result_int); + } + } + + printf("TMC2209: failed to read register after 10 tries\n"); + printf("TMC2209: is Stepper Powersupply switched on?\n"); + exit(EXIT_FAILURE); +} + + +bool write_reg(TMC2209* tmc2209, int reg, int val) { + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = tmc2209->mtr_id; + tmc2209->wFrame[2] = reg | 0x80; + tmc2209->wFrame[3] = (val >> 24) & 0xFF; + tmc2209->wFrame[4] = (val >> 16) & 0xFF; + tmc2209->wFrame[5] = (val >> 8) & 0xFF; + tmc2209->wFrame[6] = val & 0xFF; + tmc2209->wFrame[7] = compute_crc8_atm(tmc2209->wFrame, sizeof(tmc2209->wFrame) - 1, 0); + + // printf("val : %d\n",val); + + // printf("Frames :"); + // for (int i = 0; i < 8; i++) { + // printf("%X ", tmc2209->wFrame[i]); + // } + // printf("\n"); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[3]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[4]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[5]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[6]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[7]); + + sleep_ms(3); + + return true; +} + +bool write_reg_check(TMC2209* tmc2209, int reg, int val) { + + int ifcnt12 = read_int(tmc2209, IFCNT); + unsigned int ifcnt1 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + write_reg(tmc2209, reg, val); + + int ifcnt22 = read_int(tmc2209, IFCNT); + unsigned int ifcnt2 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (ifcnt1 >= ifcnt2) { + printf("TMC2209: writing not successful!\n"); + printf("reg: %X val: %d\n", reg, val); + printf("ifcnt: %d %d\n", ifcnt1, ifcnt2); + return false; + } + + return true; +} + +void TMC2209_destroy(TMC2209* tmc2209) { + // free(tmc2209); +} + + + + + +void driver_status(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: DRIVER STATUS:\n"); + read_int(tmc2209, DRVSTATUS); + unsigned int drvstatus = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Drvstatus : %d \n",drvstatus); + + if (drvstatus & STST) { + printf("TMC2209: Info: motor is standing still\n"); + } else { + printf("TMC2209: Info: motor is running\n"); + } + + if (drvstatus & STEALTH) { + printf("TMC2209: Info: motor is running on StealthChop\n"); + } else { + printf("TMC2209: Info: motor is running on SpreadCycle\n"); + } + + int cs_act = drvstatus & CS_ACTUAL; + cs_act >>= 16; + printf("TMC2209: CS actual: %d\n", cs_act); + + if (drvstatus & OLB) { + printf("TMC2209: Warning: Open load detected on phase B\n"); + } + if (drvstatus & OLA) { + printf("TMC2209: Warning: Open load detected on phase A\n"); + } + if (drvstatus & S2VSB) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase B. The driver becomes disabled\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase A. The driver becomes disabled\n"); + } + if (drvstatus & S2GB) { + printf("TMC2209: Error: Short to GND detected on phase B. The driver becomes disabled.\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short to GND detected on phase A. The driver becomes disabled.\n"); + } + if (drvstatus & OT) { + printf("TMC2209: Error: Driver Overheating!\n"); + } + if (drvstatus & OTPW) { + printf("TMC2209: Warning: Driver Overheating Prewarning!\n"); + } +} + +// Fonction general_config +void general_config(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL CONFIG\n"); + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Gconf : %d \n",gconf); + + if (gconf & I_SCALE_ANALOG) { + printf("TMC2209: Driver is using voltage supplied to VREF as current reference\n"); + } else { + printf("TMC2209: Driver is using internal reference derived from 5VOUT\n"); + } + + if (gconf & INTERNAL_RSENSE) { + printf("TMC2209: Internal sense resistors. Use current supplied into VREF as reference.\n"); + printf("TMC2209: VREF pin internally is driven to GND in this mode.\n"); + printf("TMC2209: This will most likely destroy your driver!!!\n"); + exit(EXIT_FAILURE); + } else { + printf("TMC2209: Operation with external sense resistors\n"); + } + + if (gconf & EN_SPREADCYCLE) { + printf("TMC2209: SpreadCycle mode enabled\n"); + } else { + printf("TMC2209: StealthChop PWM mode enabled\n"); + } + + if (gconf & SHAFT) { + printf("TMC2209: Inverse motor direction\n"); + } else { + printf("TMC2209: normal motor direction\n"); + } + + if (gconf & INDEX_OTPW) { + printf("TMC2209: INDEX pin outputs overtemperature prewarning flag\n"); + } else { + printf("TMC2209: INDEX shows the first microstep position of sequencer\n"); + } + + if (gconf & INDEX_STEP) { + printf("TMC2209: INDEX output shows step pulses from internal pulse generator\n"); + } else { + printf("TMC2209: INDEX output as selected by index_otpw\n"); + } +} + +// Fonction general_stat +void general_stat(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL STAT\n"); + read_int(tmc2209, GSTAT); + unsigned int gstat = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Gstat : %d \n",gstat); + if (gstat & RESET) { + printf("TMC2209: The driver has been reset since the last read access to GSTAT\n"); + } else { + printf("TMC2209: The driver has not been reset since the last read access to GSTAT\n"); + } + + if (gstat & DRV_ERR) { + printf("TMC2209: The driver has been shut down due to overtemperature or short circuit detection since the last read access\n"); + } else { + printf("TMC2209: The driver has not been shut down due to overtemperature or short circuit detection since the last read access\n"); + } + + if (gstat & UV_CP) { + printf("TMC2209: Undervoltage detected on the charge pump. The driver is disabled in this case\n"); + } else { + printf("TMC2209: No undervoltage detected on the charge pump. The driver is not disabled in this case\n"); + } + + + printf("end Gstat\n"); +} + + +bool set_vactual(TMC2209* tmc2209, int value) { + return write_reg_check(tmc2209, VACTUAL, value); +} + + + +unsigned int set_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value | bit; + // printf("value %d ,set_bit temp : %d\n" ,value,temp); + return temp; +} + + +// Fonction pour définir un bit spécifique à 0 +unsigned int clear_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value & ~(bit); + // printf("value %d ,clear_bit temp : %d\n" ,value,temp); + return temp; +} + + +void clear_general_stat(TMC2209* tmc2209) { + read_int(tmc2209, GSTAT); + unsigned int gstat= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + gstat = set_bit(gstat, RESET); + gstat = set_bit(gstat, DRV_ERR); + write_reg_check(tmc2209, GSTAT, gstat); +} + + + +void set_voltage_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); // Lire la valeur actuelle du registre CHOPCONF + unsigned int chopconf= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf |= VSENSE; + } else { + chopconf &= ~VSENSE; + } + + if (!write_reg_check(tmc2209, CHOPCONF, chopconf)) { + printf("Erreur lors de l'écriture de la valeur dans le registre CHOPCONF\n"); + } +} + +bool get_voltage_sense(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + return (chopconf & VSENSE) != 0; +} + + +void set_current_flow(TMC2209* tmc2209,double run_current, double hold_current_multiplier, int hold_current_delay, double Vref) { + double CS_IRun = 0.0; + double Rsense = 0.11; + double Vfs = 0.0; + Vref = 5.4; + hold_current_multiplier = 0.5; + hold_current_delay = 10; + run_current = 1800; + + int voltage_sense = get_voltage_sense(tmc2209); + + if (voltage_sense) { + Vfs = 0.180 * Vref / 2.5; + } else { + Vfs = 0.325 * Vref / 2.5; + } + + CS_IRun = 32.0 * 1.41421 * run_current / 1000.0 * (Rsense + 0.02) / Vfs - 1; + CS_IRun = fmin(CS_IRun, 31); + CS_IRun = fmax(CS_IRun, 0); + double CS_IHold = hold_current_multiplier * CS_IRun; + CS_IRun = round(CS_IRun); + CS_IHold = round(CS_IHold); + + // printf("CS_IHold_rounded %.3f, CS_IRun_rounded %.3f, hold_current_delay %d\n" , CS_IHold, CS_IRun, hold_current_delay); + + set_irun_ihold(tmc2209,CS_IHold, CS_IRun, hold_current_delay); +} + +int get_iscale_analog(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & I_SCALE_ANALOG) ; +} + +void set_iscale_analog(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (enabled) { + gconf = set_bit(gconf, I_SCALE_ANALOG); + } else { + + gconf = clear_bit(gconf, I_SCALE_ANALOG); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +int get_interpolation(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (chopconf & INTPOL) ; +} + +void set_interpolation(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf = set_bit(chopconf, INTPOL); + } else { + chopconf = clear_bit(chopconf, INTPOL); + } + + write_reg_check(tmc2209, CHOPCONF, chopconf); +} + +int get_internal_resistor_sense(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & INTERNAL_RSENSE) ; +} + + +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, INTERNAL_RSENSE); + } else { + + gconf = clear_bit(gconf, INTERNAL_RSENSE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +int get_spread_cycle(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & EN_SPREADCYCLE) ; +} + + +void set_spread_cycle(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, EN_SPREADCYCLE); + } else { + + gconf = clear_bit(gconf, EN_SPREADCYCLE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +void set_microstepping_resolution(TMC2209* tmc2209, int msres) { + + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + // printf("chopconf %d \n",chopconf); + + int msresdezimal = 8 - (int)log2(msres); + chopconf &= 4043309055; + chopconf |= msresdezimal << 24; + write_reg_check(tmc2209, CHOPCONF, chopconf); + set_microstep_resolution_regselect(tmc2209, true); +} + +int get_microstepping_resolution(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + + // printf("chopconf : %d\n", chopconf); + int msresdezimal = chopconf & (MSRES0 | MSRES1 | MSRES2 | MSRES3); + msresdezimal = msresdezimal >> 24; + msresdezimal = 8 - msresdezimal; + int micro_stepping_resolution = (int)pow(2, msresdezimal); + + return micro_stepping_resolution; +} + +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + gconf = set_bit(gconf, MSTEP_REG_SELECT); + } else { + gconf = clear_bit(gconf, MSTEP_REG_SELECT); + } + // printf("gconf : %d \n",gconf); + + write_reg_check(tmc2209, GCONF, gconf); +} + + +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay) { + // Convertir les valeurs doubles en entiers + int ihold_irun = 0; + int ih = (int)IHold; + int ir = (int)IRun; + + ihold_irun |= ih << 0; + // printf("ihold_irun1 : %d\n",ihold_irun); + + ihold_irun |= ir << 8; + // printf("ihold_irun2 : %d\n",ihold_irun); + + ihold_irun |= IHoldDelay << 16; + + // printf("ihold_irun3 : %d\n",ihold_irun); + + write_reg_check(tmc2209, IHOLD_IRUN, ihold_irun); +} + +int get_direction_shart(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & SHAFT) ; +} + + + + +void ioin(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: INPUTS\n"); + read_int(tmc2209, IOIN); + unsigned int ioin = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + + if (ioin & IO_SPREAD) { + printf("TMC2209: spread is high\n"); + } else { + printf("TMC2209: spread is low\n"); + } + + if (ioin & IO_DIR) { + printf("TMC2209: dir is high\n"); + } else { + printf("TMC2209: dir is low\n"); + } + + if (ioin & IO_STEP) { + printf("TMC2209: step is high\n"); + } else { + printf("TMC2209: step is low\n"); + } + + if (ioin & IO_ENN) { + printf("TMC2209: en is high\n"); + } else { + printf("TMC2209: en is low\n"); + } +} + + + +void chopper_control(TMC2209* tmc2209, int direction) { + printf("TMC2209: ---\n"); + printf("TMC2209: CHOPPER CONTROL\n"); + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (chopconf & INTPOL) { + printf("TMC2209: interpolation to 256 microsteps\n"); + } + + if (chopconf & VSENSE) { + printf("TMC2209: 1: High sensitivity, low sense resistor voltage\n"); + } else { + printf("TMC2209: 0: Low sensitivity, high sense resistor voltage\n"); + } +} + +void set_direction_shart(TMC2209* tmc2209, int direction) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + int dir = get_direction_shart(tmc2209); + // printf("dir : %d , dir 8 : %d\n",dir,dir / 8); + if ((dir / 8) != direction) { + if (direction) { + gconf = set_bit(gconf, SHAFT); + } else { + gconf = clear_bit(gconf, SHAFT); + } + // printf("gconf : %d \n",gconf); + + write_reg_check(tmc2209, GCONF, gconf); + sleep_us(100); + } +} + + +int get_stallguard(TMC2209* tmc2209) { + read_int(tmc2209, SG_RESULT); + unsigned int stg = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return stg ; +} + + +void set_stallguard_threshold(TMC2209* tmc2209, int threshold){ + write_reg_check(tmc2209,SGTHRS, threshold); +} + +void set_coolstep_threshold(TMC2209* tmc2209, int threshold){ + write_reg_check(tmc2209,TCOOLTHRS, threshold); +} + + +void set_stallguard_callback(TMC2209* tmc2209, int stallguard_pin, int threshold, int callback, int min_speed){ + set_stallguard_threshold(tmc2209,threshold); + set_coolstep_threshold(tmc2209,min_speed); + + gpio_set_function(stallguard_pin, GPIO_FUNC_SIO); + gpio_pull_up(stallguard_pin); + + gpio_set_irq_enabled_with_callback(stallguard_pin, GPIO_IRQ_EDGE_RISE, true, callback); + +} + +int get_tstep(TMC2209* tmc2209) { + read_int(tmc2209, TSTEP); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return gconf ; +} + + +int get_microstep_counter(TMC2209* tmc2209, bool in_steps, int offset) { + read_int(tmc2209, MSCNT); + unsigned int mscnt = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (!in_steps) { + return mscnt; + } + + int micro_stepping_resolution = get_microstepping_resolution(tmc2209); // Remplacez par la résolution réelle du micro-pas + return round((4 * micro_stepping_resolution) - ((mscnt - 64) * (micro_stepping_resolution * 4) / 1024) - 1) + offset; +} diff --git a/Clean_TMC2209/Tmc2209.h b/Clean_TMC2209/Tmc2209.h new file mode 100644 index 0000000..4d29078 --- /dev/null +++ b/Clean_TMC2209/Tmc2209.h @@ -0,0 +1,66 @@ +// Tmc2209.h +#ifndef TMC2209_H +#define TMC2209_H + +#include "pico/stdlib.h" +#include "Tmc_uart.h" +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + TMC_UART* serial_instance; + int mtr_id; + uint8_t rFrame[4]; + uint8_t wFrame[8]; + uint64_t result[4]; +} TMC2209; + +void TMC2209_Init(TMC2209* tmc2209, TMC_UART* serial_instance); //ok +void TMC2209_destroy(TMC2209* tmc2209); //TODO +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value); //ok +uint64_t* read_reg(TMC2209* tmc2209, int reg) ; //ok +uint32_t read_int(TMC2209* tmc2209, int reg); //ok +bool write_reg(TMC2209* tmc2209, int reg, int val); //ok +bool write_reg_check(TMC2209* tmc2209, int reg, int val) ; //ok + +void driver_status(TMC2209* tmc2209); //NotWork +void general_config(TMC2209* tmc2209); //NotWork +void general_stat(TMC2209* tmc2209); //NotWork + +bool set_vactual(TMC2209* tmc2209, int value); //ok +void set_voltage_sense(TMC2209* tmc2209, bool enabled); //ok +bool get_voltage_sense(TMC2209* tmc2209); //ok +void set_current_flow(TMC2209* tmc2209, double run_current, double hold_current_multiplier, int hold_current_delay, double Vref);//averif NotWork + +int get_iscale_analog(TMC2209* tmc2209); //ok +void set_iscale_analog(TMC2209* tmc2209, bool enabled); //ok +int get_interpolation(TMC2209* tmc2209); //ok +void set_interpolation(TMC2209* tmc2209, bool enabled); //ok +int get_internal_resistor_sense(TMC2209* tmc2209); //ok +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled); //ok +int get_spread_cycle(TMC2209* tmc2209); //NotWork +void set_spread_cycle(TMC2209* tmc2209, bool enabled); //NotWork + +void set_microstepping_resolution(TMC2209* tmc2209, int msres); //ok +int get_microstepping_resolution(TMC2209* tmc2209); //ok +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled); //ok +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay); //ok + +int get_direction_shart(TMC2209* tmc2209); //ok +void ioin(TMC2209* tmc2209); +void clear_general_stat(TMC2209* tmc2209); //ok +void set_direction_shart(TMC2209* tmc2209, int direction); //ok + +int get_stallguard(TMC2209* tmc2209); +void set_stallguard_threshold(TMC2209* tmc2209, int threshold); +void set_coolstep_threshold(TMC2209* tmc2209, int threshold); +void set_stallguard_callback(TMC2209* tmc2209, int stallguard_pin, int threshold, int callback, int min_speed); +int get_tstep(TMC2209* tmc2209); +int get_microstep_counter(TMC2209* tmc2209, bool in_steps, int offset); + +#endif diff --git a/Clean_TMC2209/Tmc_uart.c b/Clean_TMC2209/Tmc_uart.c new file mode 100644 index 0000000..6b1f142 --- /dev/null +++ b/Clean_TMC2209/Tmc_uart.c @@ -0,0 +1,36 @@ +// TMC_UART.c +#include "TMC_uart.h" + + +#define DEFAULT_UART_ID uart1 +#define DEFAULT_BAUD_RATE 115200 +#define DEFAULT_MOTOR_TX_PIN 4 +#define DEFAULT_MOTOR_RX_PIN 5 + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN) { + + if (BAUD_RATE == -1) BAUD_RATE = DEFAULT_BAUD_RATE; + if (MOTOR_TX_PIN == -1) MOTOR_TX_PIN = DEFAULT_MOTOR_TX_PIN; + if (MOTOR_RX_PIN == -1) MOTOR_RX_PIN = DEFAULT_MOTOR_RX_PIN; + + uart_init(UART_ID, BAUD_RATE); + gpio_set_function(MOTOR_TX_PIN, GPIO_FUNC_UART); + gpio_set_function(MOTOR_RX_PIN, GPIO_FUNC_UART); + uart_set_hw_flow(UART_ID, false, false); + uart_set_format(UART_ID, 8, 1, UART_PARITY_NONE); + uart_set_fifo_enabled(UART_ID, false); + + tmc_uart->UART_ID = UART_ID; + tmc_uart->BAUD_RATE = BAUD_RATE; + tmc_uart->MOTOR_TX_PIN = MOTOR_TX_PIN; + tmc_uart->MOTOR_RX_PIN = MOTOR_RX_PIN; + return tmc_uart; +} + +void TMC_UART_Write(TMC_UART* tmc_uart, int data) { + uart_putc(tmc_uart->UART_ID, data); +} + +void TMC_UART_Destroy(TMC_UART* tmc_uart) { + // Aucune opération nécessaire +} diff --git a/Clean_TMC2209/Tmc_uart.h b/Clean_TMC2209/Tmc_uart.h new file mode 100644 index 0000000..b7d2d5d --- /dev/null +++ b/Clean_TMC2209/Tmc_uart.h @@ -0,0 +1,18 @@ +// TMC_UART.h +#ifndef TMC_UART_H +#define TMC_UART_H + +#include +#include "pico/stdlib.h" + +typedef struct { + uart_inst_t *UART_ID; + int BAUD_RATE; + int MOTOR_TX_PIN; + int MOTOR_RX_PIN; +} TMC_UART; + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN); +void tmc_Uart_Destroy(TMC_UART* TMC_UART); + +#endif diff --git a/Clean_TMC2209/lib/tmc/boards/Board.c b/Clean_TMC2209/lib/tmc/boards/Board.c new file mode 100644 index 0000000..a80f290 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/Board.c @@ -0,0 +1,172 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Board.h" + +MotionControllerBoards motionControllerBoards; +DriverBoards driverBoards; + +static void deInit(void) {} + +// Evalboard channel function dummies +static uint32_t dummy_Motor(uint8_t motor) +{ + UNUSED(motor); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_MotorValue(uint8_t motor, int32_t value) +{ + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static void dummy_AddressRef(uint8_t motor, uint16_t address, int32_t *value) +{ + UNUSED(motor); + UNUSED(address); + UNUSED(value); +} + +static void dummy_AddressValue(uint8_t motor, uint16_t address, int32_t value) +{ + UNUSED(motor); + UNUSED(address); + UNUSED(value); +} + +static uint32_t dummy_MotorRef(uint8_t motor, int32_t *value) +{ + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_TypeMotorValue(uint8_t type, uint8_t motor, int32_t value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_TypeMotorRef(uint8_t type, uint8_t motor, int32_t *value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_getLimit(uint8_t type, uint8_t motor, int32_t *value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint8_t dummy_onPinChange(IOPinTypeDef *pin, IO_States state) +{ + UNUSED(pin); + UNUSED(state); + return 1; +} + +static void dummy_OTP_init(void) +{ + return; +} + +static void dummy_OTP_address(uint32_t address) +{ + UNUSED(address); + return; +} + +static void dummy_OTP_value(uint32_t value) +{ + UNUSED(value); + return; +} + +static void dummy_OTP_program(void) +{ + return; +} + +static void dummy_OTP_lock(void) +{ + return; +} + +static OTP_Status dummy_OTP_status(void) +{ + return OTP_STATUS_IDLE; +} + +static uint8_t delegationReturn(void) +{ + return 1; +} + +static void enableDriver(DriverState state) +{ + UNUSED(state); +} + +static void periodicJob(uint32_t tick) +{ + UNUSED(tick); +} + +void board_setDummyFunctions(EvalboardFunctionsTypeDef *channel) +{ + channel->config->reset = delegationReturn; + channel->config->restore = delegationReturn; + + channel->deInit = deInit; + channel->periodicJob = periodicJob; + channel->left = dummy_MotorValue; + channel->stop = dummy_Motor; + channel->moveTo = dummy_MotorValue; + channel->moveBy = dummy_MotorRef; + channel->moveProfile = dummy_MotorValue; + channel->right = dummy_MotorValue; + channel->GAP = dummy_TypeMotorRef; + channel->readRegister = dummy_AddressRef; + channel->writeRegister = dummy_AddressValue; + channel->SAP = dummy_TypeMotorValue; + channel->SIO = dummy_TypeMotorValue; + channel->GIO = dummy_TypeMotorRef; + channel->STAP = dummy_TypeMotorValue; + channel->RSAP = dummy_TypeMotorValue; + channel->userFunction = dummy_TypeMotorRef; + channel->getMeasuredSpeed = dummy_MotorRef; + channel->checkErrors = periodicJob; + channel->enableDriver = enableDriver; + + channel->fullCover = NULL; + channel->getMin = dummy_getLimit; + channel->getMax = dummy_getLimit; + channel->onPinChange = dummy_onPinChange; + + channel->OTP_init = dummy_OTP_init; + channel->OTP_address = dummy_OTP_address; + channel->OTP_value = dummy_OTP_value; + channel->OTP_program = dummy_OTP_program; + channel->OTP_status = dummy_OTP_status; + channel->OTP_lock = dummy_OTP_lock; +} + +void periodicJobDummy(uint32_t tick) +{ + UNUSED(tick); +} diff --git a/Clean_TMC2209/lib/tmc/boards/Board.h b/Clean_TMC2209/lib/tmc/boards/Board.h new file mode 100644 index 0000000..79ddfaf --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/Board.h @@ -0,0 +1,197 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef BOARD_H +#define BOARD_H + +#include "tmc/helpers/API_Header.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "tmc/VitalSignsMonitor.h" + +#include "tmc/ic/TMC2130/TMC2130.h" +#include "tmc/ic/TMC2160/TMC2160.h" +#include "tmc/ic/TMC2208/TMC2208.h" +#include "tmc/ic/TMC2224/TMC2224.h" +#include "tmc/ic/TMC2590/TMC2590.h" +#include "tmc/ic/TMC2660/TMC2660.h" +#include "tmc/ic/TMC6100/TMC6100.h" +#include "tmc/ic/TMC6200/TMC6200.h" +#include "tmc/ic/TMC7300/TMC7300.h" + + +#include "tmc/ic/TMC2209/TMC2209.h" +#include "tmc/ic/TMC2225/TMC2225.h" +#include "tmc/ic/TMC2226/TMC2226.h" +#include "tmc/ic/TMC2300/TMC2300.h" +#include "tmc/ic/MAX22216/MAX22216.h" +#include "tmc/ic/TMC4361A/TMC4361A.h" +#include "tmc/ic/TMC5031/TMC5031.h" +#include "tmc/ic/TMC5041/TMC5041.h" +#include "tmc/ic/TMC5062/TMC5062.h" +#include "tmc/ic/TMC5072/TMC5072.h" +#include "tmc/ic/TMC5130/TMC5130.h" +#include "tmc/ic/TMC5160/TMC5160.h" +#include "tmc/ic/TMC8461/TMC8461.h" +#include "tmc/ic/TMC8462/TMC8462.h" + +// parameter access (for axis parameters) +#define READ 0 +#define WRITE 1 + +typedef enum { + LIMIT_MIN, + LIMIT_MAX +} AxisParameterLimit; + +typedef enum { + DRIVER_DISABLE, + DRIVER_ENABLE, + DRIVER_USE_GLOBAL_ENABLE +} DriverState; + +typedef enum { + OTP_STATUS_IDLE = 0, + OTP_STATUS_PROGRAMMING = 1, + OTP_STATUS_DONE = 2, + OTP_STATUS_FAILED = 3 +} OTP_Status; + +// Evalboard channel struct +typedef struct +{ + void *type; + uint8_t id; + uint32_t errors; + int32_t VMMax; + int32_t VMMin; + unsigned char numberOfMotors; + ConfigurationTypeDef *config; + uint32_t (*left) (uint8_t motor, int32_t velocity); // move left with velocity + uint32_t (*right) (uint8_t motor, int32_t velocity); // move right with velocity + uint32_t (*rotate) (uint8_t motor, int32_t velocity); // move right with velocity + uint32_t (*stop) (uint8_t motor); // stop motor + uint32_t (*moveTo) (uint8_t motor, int32_t position); // move to position + uint32_t (*moveBy) (uint8_t motor, int32_t *ticks); // move by , changes ticks to absolute target + uint32_t (*moveProfile) (uint8_t motor, int32_t position); // move profile + uint32_t (*SAP) (uint8_t type, uint8_t motor, int32_t value); // set axis parameter -> TMCL conformance + uint32_t (*GAP) (uint8_t type, uint8_t motor, int32_t *value); // get axis parameter -> TMCL conformance + uint32_t (*STAP) (uint8_t type, uint8_t motor, int32_t value); // store axis parameter -> TMCL conformance + uint32_t (*RSAP) (uint8_t type, uint8_t motor, int32_t value); // restore axis parameter -> TMCL conformance + uint32_t (*SIO) (uint8_t type, uint8_t motor, int32_t value); + uint32_t (*GIO) (uint8_t type, uint8_t motor, int32_t *value); + void (*readRegister) (uint8_t motor, uint16_t address, int32_t *value); // Motor needed since some chips utilize it as a switch between low and high values + void (*writeRegister) (uint8_t motor, uint16_t address, int32_t value); // Motor needed since some chips utilize it as a switch between low and high values + uint32_t (*getMeasuredSpeed) (uint8_t motor, int32_t *value); + uint32_t (*userFunction) (uint8_t type, uint8_t motor, int32_t *value); + + void (*periodicJob) (uint32_t tick); + void (*deInit) (void); + + void (*checkErrors) (uint32_t tick); + void (*enableDriver) (DriverState state); + + uint8_t (*cover) (uint8_t data, uint8_t lastTransfer); + void (*fullCover) (uint8_t *data, size_t length); + + uint32_t (*getMin) (uint8_t type, uint8_t motor, int32_t *value); + uint32_t (*getMax) (uint8_t type, uint8_t motor, int32_t *value); + + uint8_t (*onPinChange)(IOPinTypeDef *pin, IO_States state); + + void (*OTP_init)(void); + void (*OTP_address)(uint32_t address); + void (*OTP_value)(uint32_t value); + void (*OTP_program)(void); + void (*OTP_lock)(void); + OTP_Status (*OTP_status)(void); +} EvalboardFunctionsTypeDef; + + +// "hash" function to resolve API error <=> Map index +inline uint8_t error_index(uint8_t error) +{ + uint8_t i = 0; + for(; error != 1; i++) + error >>= 1; + return i; +} + +// Evalboard errors +// TODO: Extends API Error bits. For more information, see comment in TMCError typedef. +typedef enum { + TMC_ERROR_TYPE = 0x04, + TMC_ERROR_ADDRESS = 0x04, + TMC_ERROR_NOT_DONE = 0x20 +} EvalboardErrorBit; + +// Channel identifiers required to switch between channels in readWrite +typedef enum { + CHANNEL_1, + CHANNEL_2 +} EvalboardChannels; + +// struct for our Evalsystem, with two available Evalboard channels +typedef struct +{ + EvalboardFunctionsTypeDef ch1; + EvalboardFunctionsTypeDef ch2; + DriverState driverEnable; // global driver status +} EvalboardsTypeDef; + +extern EvalboardsTypeDef Evalboards; + +typedef enum { + TMC_BOARD_COMM_DEFAULT, + TMC_BOARD_COMM_SPI, + TMC_BOARD_COMM_UART, + TMC_BOARD_COMM_WLAN +} TMC_Board_Comm_Mode; + +// Group all the motion controller chip objects into a single union to save memory, +// since we will only ever use one driver at a time +typedef union { + TMC4361ATypeDef tmc4361A; + TMC5031TypeDef tmc5031; + TMC5041TypeDef tmc5041; + TMC5062TypeDef tmc5062; + TMC5072TypeDef tmc5072; + TMC5130TypeDef tmc5130; + TMC5160TypeDef tmc5160; + TMC8461TypeDef tmc8461; + TMC8462TypeDef tmc8462; +} MotionControllerBoards; +extern MotionControllerBoards motionControllerBoards; + +// Group all the driver chip objects into a single union to save memory, +// since we will only ever use one motion controller at a time +typedef union { + TMC2130TypeDef tmc2130; + TMC2160TypeDef tmc2160; + TMC2208TypeDef tmc2208; + TMC2224TypeDef tmc2224; + TMC2590TypeDef tmc2590; + TMC2660TypeDef tmc2660; + TMC7300TypeDef tmc7300; + TMC2209TypeDef tmc2209; + TMC2225TypeDef tmc2225; + TMC2226TypeDef tmc2226; + TMC2300TypeDef tmc2300; + MAX22216TypeDef max22216; +} DriverBoards; +extern DriverBoards driverBoards; + +void periodicJobDummy(uint32_t tick); +void board_setDummyFunctions(EvalboardFunctionsTypeDef *channel); + +#include "TMCDriver.h" +#include "TMCMotionController.h" + +#endif /* BOARD_H */ diff --git a/Clean_TMC2209/lib/tmc/boards/SelfTest.h b/Clean_TMC2209/lib/tmc/boards/SelfTest.h new file mode 100644 index 0000000..9d0447a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/SelfTest.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SELF_TEST_H +#define SELF_TEST_H + + #define SELF_TEST_PINS_PER_GROUP 17 + #define SELF_TEST_LEAVE 1 + #define SELF_TEST_A_OUT_B_IN 2 + #define SELF_TEST_A_IN_B_OUT 3 + #define SELF_TEST_READ_AN 4 + #define SELF_TEST_SET_AN 5 + #define SELF_TEST_SET_AN_2 6 + #define SELF_TEST_SET_MIXED 7 + #define SELF_TEST_SET_EXTIO 8 + +#endif /* SELF_TEST_H */ diff --git a/Clean_TMC2209/lib/tmc/boards/TMC2209_eval.c b/Clean_TMC2209/lib/tmc/boards/TMC2209_eval.c new file mode 100644 index 0000000..2dea26e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/TMC2209_eval.c @@ -0,0 +1,790 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Board.h" +#include "tmc/ic/TMC2209/TMC2209.h" +#include "tmc/StepDir.h" + +#undef TMC2209_MAX_VELOCITY +#define TMC2209_MAX_VELOCITY STEPDIR_MAX_VELOCITY + +// Stepdir precision: 2^17 -> 17 digits of precision +#define STEPDIR_PRECISION 131072 + +#define ERRORS_VM (1<<0) +#define ERRORS_VM_UNDER (1<<1) +#define ERRORS_VM_OVER (1<<2) + +#define VM_MIN 50 // VM[V/10] min +#define VM_MAX 390 // VM[V/10] max + +#define MOTORS 1 + +#define VREF_FULLSCALE 2100 // mV // with R308 achievable Vref_max is ~2100mV +//#define VREF_FULLSCALE 3300 // mV // without R308 achievable Vref_max is ~2500mV + + +static uint32_t right(uint8_t motor, int32_t velocity); +static uint32_t left(uint8_t motor, int32_t velocity); +static uint32_t rotate(uint8_t motor, int32_t velocity); +static uint32_t stop(uint8_t motor); +static uint32_t moveTo(uint8_t motor, int32_t position); +static uint32_t moveBy(uint8_t motor, int32_t *ticks); +static uint32_t GAP(uint8_t type, uint8_t motor, int32_t *value); +static uint32_t SAP(uint8_t type, uint8_t motor, int32_t value); + +static void checkErrors (uint32_t tick); +static void deInit(void); +static uint32_t userFunction(uint8_t type, uint8_t motor, int32_t *value); + +static void periodicJob(uint32_t tick); +static uint8_t reset(void); +static uint8_t restore(void); +static void enableDriver(DriverState state); + +static UART_Config *TMC2209_UARTChannel; +static ConfigurationTypeDef *TMC2209_config; + +static uint16_t vref; // mV +static int32_t thigh; + +static timer_channel timerChannel; +// Helper macro - Access the chip object in the driver boards union +#define TMC2209 (driverBoards.tmc2209) + +// Helper macro - index is always 1 here (channel 1 <-> index 0, channel 2 <-> index 1) +#define TMC2209_CRC(data, length) tmc_CRC8(data, length, 1) + +typedef struct +{ + IOPinTypeDef *ENN; + IOPinTypeDef *SPREAD; + IOPinTypeDef *STEP; + IOPinTypeDef *DIR; + IOPinTypeDef *MS1_AD0; + IOPinTypeDef *MS2_AD1; + IOPinTypeDef *DIAG; + IOPinTypeDef *INDEX; + IOPinTypeDef *UC_PWM; + IOPinTypeDef *STDBY; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static inline TMC2209TypeDef *motorToIC(uint8_t motor) +{ + UNUSED(motor); + + return &TMC2209; +} + +static inline UART_Config *channelToUART(uint8_t channel) +{ + UNUSED(channel); + + return TMC2209_UARTChannel; +} + +// => UART wrapper +// Write [writeLength] bytes from the [data] array. +// If [readLength] is greater than zero, read [readLength] bytes from the +// [data] array. +void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength) +{ + UART_readWrite(channelToUART(channel), data, writeLength, readLength); +} +// <= UART wrapper + +// => CRC wrapper +// Return the CRC8 of [length] bytes of data stored in the [data] array. +uint8_t tmc2209_CRC8(uint8_t *data, size_t length) +{ + return TMC2209_CRC(data, length); +} +// <= CRC wrapper + +void tmc2209_writeRegister(uint8_t motor, uint16_t address, int32_t value) +{ + tmc2209_writeInt(motorToIC(motor), (uint8_t) address, value); + +} + +void tmc2209_readRegister(uint8_t motor, uint16_t address, int32_t *value) +{ + *value = tmc2209_readInt(motorToIC(motor), (uint8_t) address); +} + +static uint32_t rotate(uint8_t motor, int32_t velocity) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + StepDir_rotate(motor, velocity); + + return TMC_ERROR_NONE; +} + +static uint32_t right(uint8_t motor, int32_t velocity) +{ + return rotate(motor, velocity); +} + +static uint32_t left(uint8_t motor, int32_t velocity) +{ + return rotate(motor, -velocity); +} + +static uint32_t stop(uint8_t motor) +{ + return rotate(motor, 0); +} + +static uint32_t moveTo(uint8_t motor, int32_t position) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + StepDir_moveTo(motor, position); + + return TMC_ERROR_NONE; +} + +static uint32_t moveBy(uint8_t motor, int32_t *ticks) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + // determine actual position and add numbers of ticks to move + *ticks += StepDir_getActualPosition(motor); + + return moveTo(motor, *ticks); +} + +static uint32_t handleParameter(uint8_t readWrite, uint8_t motor, uint8_t type, int32_t *value) +{ + uint32_t errors = TMC_ERROR_NONE; + int32_t buffer = 0; + + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + switch(type) + { + case 0: + // Target position + if(readWrite == READ) { + *value = StepDir_getTargetPosition(motor); + } else if(readWrite == WRITE) { + StepDir_moveTo(motor, *value); + } + break; + case 1: + // Actual position + if(readWrite == READ) { + *value = StepDir_getActualPosition(motor); + } else if(readWrite == WRITE) { + StepDir_setActualPosition(motor, *value); + } + break; + case 2: + // Target speed + if(readWrite == READ) { + *value = StepDir_getTargetVelocity(motor); + } else if(readWrite == WRITE) { + StepDir_rotate(motor, *value); + } + break; + case 3: + // Actual speed + if(readWrite == READ) { + *value = StepDir_getActualVelocity(motor); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 4: + // Maximum speed + if(readWrite == READ) { + *value = StepDir_getVelocityMax(motor); + } else if(readWrite == WRITE) { + StepDir_setVelocityMax(motor, abs(*value)); + } + break; + case 5: + // Maximum acceleration + if(readWrite == READ) { + *value = StepDir_getAcceleration(motor); + } else if(readWrite == WRITE) { + StepDir_setAcceleration(motor, *value); + } + break; + case 6: + // Maximum current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IRUN_MASK, TMC2209_IRUN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IRUN_MASK, TMC2209_IRUN_SHIFT, *value); + } + break; + case 7: + // Standby current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IHOLD_MASK, TMC2209_IHOLD_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IHOLD_MASK, TMC2209_IHOLD_SHIFT, *value); + } + break; + case 8: + // Position reached flag + if(readWrite == READ) { + *value = (StepDir_getStatus(motor) & STATUS_TARGET_REACHED)? 1:0; + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 9: + // VREF + if (readWrite == READ) { + *value = vref; + } else { + if ((uint32_t) *value < VREF_FULLSCALE) { + vref = *value; + Timer.setDuty(timerChannel, ((float)vref) / VREF_FULLSCALE); + } else { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 23: + // Speed threshold for high speed mode + if(readWrite == READ) { + buffer = thigh; + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + thigh = *value; + } + break; + case 28: + // Internal RSense + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_GCONF, TMC2209_INTERNAL_RSENSE_MASK, TMC2209_INTERNAL_RSENSE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_GCONF, TMC2209_INTERNAL_RSENSE_MASK, TMC2209_INTERNAL_RSENSE_SHIFT, *value); + } + break; + case 29: + // Measured Speed + if(readWrite == READ) { + buffer = (int32_t)(((int64_t)StepDir_getFrequency(motor) * (int64_t)122) / (int64_t)TMC2209_FIELD_READ(motorToIC(motor), TMC2209_TSTEP, TMC2209_TSTEP_MASK, TMC2209_TSTEP_SHIFT)); + *value = (abs(buffer) < 20) ? 0 : buffer; + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 50: // StepDir internal(0)/external(1) + if(readWrite == READ) { + *value = StepDir_getMode(motor); + } else if(readWrite == WRITE) { + StepDir_setMode(motor, *value); + } + break; + case 51: // StepDir interrupt frequency + if(readWrite == READ) { + *value = StepDir_getFrequency(motor); + } else if(readWrite == WRITE) { + StepDir_setFrequency(motor, *value); + } + break; + case 140: + // Microstep Resolution + if(readWrite == READ) { + *value = 256 >> TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_MRES_MASK, TMC2209_MRES_SHIFT); + } else if(readWrite == WRITE) { + switch(*value) + { + case 1: *value = 8; break; + case 2: *value = 7; break; + case 4: *value = 6; break; + case 8: *value = 5; break; + case 16: *value = 4; break; + case 32: *value = 3; break; + case 64: *value = 2; break; + case 128: *value = 1; break; + case 256: *value = 0; break; + default: *value = -1; break; + } + + if(*value != -1) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_MRES_MASK, TMC2209_MRES_SHIFT, *value); + } + else + { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 162: + // Chopper blank time + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TBL_MASK, TMC2209_TBL_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TBL_MASK, TMC2209_TBL_SHIFT, *value); + } + break; + case 165: + // Chopper hysteresis end / fast decay time + if(readWrite == READ) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HEND_MASK, TMC2209_HEND_SHIFT); + } + else + { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF); + *value = (tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) >> 4) & 0x07; + if(buffer & (1<<11)) + *value |= 1<<3; + } + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 166: + // Chopper hysteresis start / sine wave offset + if(readWrite == READ) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HSTRT_MASK, TMC2209_HSTRT_SHIFT); + } + else + { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF); + *value = (tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) >> 7) & 0x0F; + if(buffer & (1<<11)) + *value |= 1<<3; + } + } else if(readWrite == WRITE) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HSTRT_MASK, TMC2209_HSTRT_SHIFT, *value); + } + else + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HEND_MASK, TMC2209_HEND_SHIFT, *value); + } + } + break; + case 167: + // Chopper off time + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TOFF_MASK, TMC2209_TOFF_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TOFF_MASK, TMC2209_TOFF_SHIFT, *value); + } + break; + case 168: + // smartEnergy current minimum (SEIMIN) + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEIMIN_MASK, TMC2209_SEIMIN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEIMIN_MASK, TMC2209_SEIMIN_SHIFT, *value); + } + break; + case 169: + // smartEnergy current down step + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEDN_MASK, TMC2209_SEDN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEDN_MASK, TMC2209_SEDN_SHIFT, *value); + } + break; + case 170: + // smartEnergy hysteresis + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMAX_MASK, TMC2209_SEMAX_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMAX_MASK, TMC2209_SEMAX_SHIFT, *value); + } + break; + case 171: + // smartEnergy current up step + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEUP_MASK, TMC2209_SEUP_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEUP_MASK, TMC2209_SEUP_SHIFT, *value); + } + break; + case 172: + // smartEnergy hysteresis start + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMIN_MASK, TMC2209_SEMIN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMIN_MASK, TMC2209_SEMIN_SHIFT, *value); + } + break; + case 174: + // stallGuard2 threshold + if(readWrite == READ) { + *value = tmc2209_readInt(motorToIC(motor), TMC2209_SGTHRS); + } else if(readWrite == WRITE) { + tmc2209_writeInt(motorToIC(motor), TMC2209_SGTHRS, *value); + } + break; + case 179: + // VSense + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_VSENSE_MASK, TMC2209_VSENSE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_VSENSE_MASK, TMC2209_VSENSE_SHIFT, *value); + } + break; + case 180: + // smartEnergy actual current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_DRVSTATUS, TMC2209_CS_ACTUAL_MASK, TMC2209_CS_ACTUAL_SHIFT); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 181: + // smartEnergy stall velocity + if(readWrite == READ) { + *value = StepDir_getStallGuardThreshold(motor); + } else if(readWrite == WRITE) { + // Store the threshold value in the internal StepDir generator + StepDir_setStallGuardThreshold(motor, *value); + + // Convert the value for the TCOOLTHRS register + // The IC only sends out Stallguard errors while TCOOLTHRS >= TSTEP >= TPWMTHRS + // The TSTEP value is measured. To prevent measurement inaccuracies hiding + // a stall signal, we decrease the needed velocity by roughly 12% before converting it. + *value -= (*value) >> 3; + if (*value) + { + *value = MIN(0x000FFFFF, (1<<24) / (*value)); + } + else + { + *value = 0x000FFFFF; + } + tmc2209_writeInt(motorToIC(motor), TMC2209_TCOOLTHRS, *value); + } + break; + case 182: + // smartEnergy threshold speed + if(readWrite == READ) { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_TCOOLTHRS); + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + tmc2209_writeInt(motorToIC(motor), TMC2209_TCOOLTHRS, *value); + } + break; + case 186: + // PWM threshold speed + if(readWrite == READ) { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_TPWMTHRS); + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + tmc2209_writeInt(motorToIC(motor), TMC2209_TPWMTHRS, *value); + } + break; + case 187: + // PWM gradient + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_GRAD_MASK, TMC2209_PWM_GRAD_SHIFT); + } else if(readWrite == WRITE) { + // Set gradient + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_GRAD_MASK, TMC2209_PWM_GRAD_SHIFT, *value); + + // Enable/disable stealthChop accordingly + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_GCONF, TMC2209_EN_SPREADCYCLE_MASK, TMC2209_EN_SPREADCYCLE_SHIFT, (*value > 0) ? 0 : 1); + } + break; + case 191: + // PWM frequency + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_FREQ_MASK, TMC2209_PWM_FREQ_SHIFT); + } else if(readWrite == WRITE) { + if(*value >= 0 && *value < 4) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_FREQ_MASK, TMC2209_PWM_FREQ_SHIFT, *value); + } + else + { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 192: + // PWM autoscale + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_AUTOSCALE_MASK, TMC2209_PWM_AUTOSCALE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_AUTOSCALE_MASK, TMC2209_PWM_AUTOSCALE_SHIFT, (*value)? 1:0); + } + break; + case 204: + // Freewheeling mode + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_FREEWHEEL_MASK, TMC2209_FREEWHEEL_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_FREEWHEEL_MASK, TMC2209_FREEWHEEL_SHIFT, *value); + } + break; + case 206: + // Load value + if(readWrite == READ) { + *value = tmc2209_readInt(motorToIC(motor), TMC2209_SG_RESULT); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + default: + errors |= TMC_ERROR_TYPE; + break; + } + + return errors; +} + +static uint32_t SAP(uint8_t type, uint8_t motor, int32_t value) +{ + return handleParameter(WRITE, motor, type, &value); +} + +static uint32_t GAP(uint8_t type, uint8_t motor, int32_t *value) +{ + return handleParameter(READ, motor, type, value); +} + +static void checkErrors(uint32_t tick) +{ + UNUSED(tick); + Evalboards.ch2.errors = 0; +} + +static uint32_t userFunction(uint8_t type, uint8_t motor, int32_t *value) +{ + uint32_t errors = 0; + uint8_t state; + IOPinTypeDef *pin; + + switch(type) + { + case 0: // Read StepDir status bits + *value = StepDir_getStatus(motor); + break; + case 1: + tmc2209_set_slave(motorToIC(motor), (*value) & 0xFF); + break; + case 2: + *value = tmc2209_get_slave(motorToIC(motor)); + break; + case 3: + *value = Timer.getDuty(timerChannel) * 100 / TIMER_MAX; + break; + case 4: + Timer.setDuty(timerChannel, ((float)*value) / 100); + break; + case 5: // Set pin state + state = (*value) & 0x03; + pin = Pins.ENN; + switch(motor) { + case 0: + pin = Pins.ENN; + break; + case 1: + pin = Pins.SPREAD; + break; + case 2: + pin = Pins.MS1_AD0; + break; + case 3: + pin = Pins.MS2_AD1; + break; + case 4: + pin = Pins.UC_PWM; + break; + case 5: + pin = Pins.STDBY; + break; + } + HAL.IOs->config->setToState(pin, state); + break; + case 6: // Get pin state + pin = Pins.ENN; + switch(motor) { + case 0: + pin = Pins.ENN; + break; + case 1: + pin = Pins.SPREAD; + break; + case 2: + pin = Pins.MS1_AD0; + break; + case 3: + pin = Pins.MS2_AD1; + break; + case 4: + pin = Pins.UC_PWM; + break; + case 5: + pin = Pins.STDBY; + break; + } + *value = (uint32_t) HAL.IOs->config->getState(pin); + break; + default: + errors |= TMC_ERROR_TYPE; + break; + } + + return errors; +} + +static void deInit(void) +{ + enableDriver(DRIVER_DISABLE); + HAL.IOs->config->reset(Pins.ENN); + HAL.IOs->config->reset(Pins.SPREAD); + HAL.IOs->config->reset(Pins.STEP); + HAL.IOs->config->reset(Pins.DIR); + HAL.IOs->config->reset(Pins.MS1_AD0); + HAL.IOs->config->reset(Pins.MS2_AD1); + HAL.IOs->config->reset(Pins.DIAG); + HAL.IOs->config->reset(Pins.INDEX); + HAL.IOs->config->reset(Pins.STDBY); + HAL.IOs->config->reset(Pins.UC_PWM); + + StepDir_deInit(); + Timer.deInit(); +} + +static uint8_t reset() +{ + StepDir_init(STEPDIR_PRECISION); + StepDir_setPins(0, Pins.STEP, Pins.DIR, Pins.DIAG); + + return tmc2209_reset(&TMC2209); +} + +static uint8_t restore() +{ + return tmc2209_restore(&TMC2209); +} + +static void enableDriver(DriverState state) +{ + if(state == DRIVER_USE_GLOBAL_ENABLE) + state = Evalboards.driverEnable; + + if(state == DRIVER_DISABLE) + HAL.IOs->config->setHigh(Pins.ENN); + else if((state == DRIVER_ENABLE) && (Evalboards.driverEnable == DRIVER_ENABLE)) + HAL.IOs->config->setLow(Pins.ENN); +} + +static void periodicJob(uint32_t tick) +{ + tmc2209_periodicJob(&TMC2209, tick); + StepDir_periodicJob(0); +} + +void TMC2209_init(void) +{ + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + timerChannel = TIMER_CHANNEL_3; + +#elif defined(LandungsbrueckeV3) + timerChannel = TIMER_CHANNEL_4; +#endif + tmc_fillCRC8Table(0x07, true, 1); + thigh = 0; + + Pins.ENN = &HAL.IOs->pins->DIO0; + Pins.SPREAD = &HAL.IOs->pins->DIO8; + Pins.STEP = &HAL.IOs->pins->DIO6; + Pins.DIR = &HAL.IOs->pins->DIO7; + Pins.MS1_AD0 = &HAL.IOs->pins->DIO3; + Pins.MS2_AD1 = &HAL.IOs->pins->DIO4; + Pins.DIAG = &HAL.IOs->pins->DIO1; + Pins.INDEX = &HAL.IOs->pins->DIO2; + Pins.UC_PWM = &HAL.IOs->pins->DIO9; + Pins.STDBY = &HAL.IOs->pins->DIO0; + + HAL.IOs->config->toOutput(Pins.ENN); + HAL.IOs->config->toOutput(Pins.SPREAD); + HAL.IOs->config->toOutput(Pins.STEP); + HAL.IOs->config->toOutput(Pins.DIR); + HAL.IOs->config->toOutput(Pins.MS1_AD0); + HAL.IOs->config->toOutput(Pins.MS2_AD1); + HAL.IOs->config->toInput(Pins.DIAG); + HAL.IOs->config->toInput(Pins.INDEX); + + HAL.IOs->config->setLow(Pins.MS1_AD0); + HAL.IOs->config->setLow(Pins.MS2_AD1); + + TMC2209_UARTChannel = HAL.UART; + TMC2209_UARTChannel->pinout = UART_PINS_2; + TMC2209_UARTChannel->rxtx.init(); + + TMC2209_config = Evalboards.ch2.config; + + Evalboards.ch2.config->reset = reset; + Evalboards.ch2.config->restore = restore; + + Evalboards.ch2.rotate = rotate; + Evalboards.ch2.right = right; + Evalboards.ch2.left = left; + Evalboards.ch2.stop = stop; + Evalboards.ch2.GAP = GAP; + Evalboards.ch2.SAP = SAP; + Evalboards.ch2.moveTo = moveTo; + Evalboards.ch2.moveBy = moveBy; + Evalboards.ch2.writeRegister = tmc2209_writeRegister; + Evalboards.ch2.readRegister = tmc2209_readRegister; + Evalboards.ch2.userFunction = userFunction; + Evalboards.ch2.enableDriver = enableDriver; + Evalboards.ch2.checkErrors = checkErrors; + Evalboards.ch2.numberOfMotors = MOTORS; + Evalboards.ch2.VMMin = VM_MIN; + Evalboards.ch2.VMMax = VM_MAX; + Evalboards.ch2.deInit = deInit; + Evalboards.ch2.periodicJob = periodicJob; + + tmc2209_init(&TMC2209, 0, 0, TMC2209_config, &tmc2209_defaultRegisterResetState[0]); + + StepDir_init(STEPDIR_PRECISION); + StepDir_setPins(0, Pins.STEP, Pins.DIR, Pins.DIAG); + StepDir_setVelocityMax(0, 51200); + StepDir_setAcceleration(0, 51200); + + HAL.IOs->config->toOutput(Pins.UC_PWM); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + Pins.UC_PWM->configuration.GPIO_Mode = GPIO_Mode_AF4; +#elif defined(LandungsbrueckeV3) + Pins.UC_PWM->configuration.GPIO_Mode = GPIO_MODE_AF; + gpio_af_set(Pins.UC_PWM->port, GPIO_AF_1, Pins.UC_PWM->bitWeight); + +#endif + + vref = 2000; + HAL.IOs->config->set(Pins.UC_PWM); + Timer.init(); + Timer.setDuty(timerChannel, ((float)vref) / VREF_FULLSCALE); + + enableDriver(DRIVER_ENABLE); +}; diff --git a/Clean_TMC2209/lib/tmc/boards/TMCDriver.c b/Clean_TMC2209/lib/tmc/boards/TMCDriver.c new file mode 100644 index 0000000..d46ac91 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/TMCDriver.c @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCDriver.h" + +EvalBoardDriverTypeDef TMCDriver = +{ + .config = + { + .state = CONFIG_READY, + .configIndex = 0, + .shadowRegister = { 0 } + } +}; + +void tmcdriver_init() +{ + Evalboards.ch2.config = &TMCDriver.config; + Evalboards.ch2.config->state = CONFIG_READY; + Evalboards.ch2.config->configIndex = 0; + + // A value of 0 indicates the Evalboard not connecting the VM line, + // resulting in skipped global minimum voltage checks. + // A negative value indicates no board being connected, which skips the + // minimum voltage check for that channel + Evalboards.ch2.VMMin = -1; + Evalboards.ch2.VMMax = s32_MAX; + + Evalboards.ch2.numberOfMotors = 0; + Evalboards.ch2.errors = 0; + + Evalboards.ch2.config->channel = CHANNEL_2; + + board_setDummyFunctions(&Evalboards.ch2); +} diff --git a/Clean_TMC2209/lib/tmc/boards/TMCDriver.h b/Clean_TMC2209/lib/tmc/boards/TMCDriver.h new file mode 100644 index 0000000..b837ea4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/TMCDriver.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCDRIVER_H_ +#define TMCDRIVER_H_ + + #include "Board.h" + + typedef struct + { + ConfigurationTypeDef config; + } EvalBoardDriverTypeDef; + + extern EvalBoardDriverTypeDef TMCDriver; + + void tmcdriver_init(); + +#endif /* TMCDRIVER_H_ */ diff --git a/Clean_TMC2209/lib/tmc/boards/TMCMotionController.c b/Clean_TMC2209/lib/tmc/boards/TMCMotionController.c new file mode 100644 index 0000000..fca7bce --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/TMCMotionController.c @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCMotionController.h" + +EvalBoardMotionControllerTypeDef TMCMotionController = +{ + .config = + { + .state = CONFIG_READY, + .configIndex = 0, + .shadowRegister = { 0 } + } +}; + +void tmcmotioncontroller_init() +{ + Evalboards.ch1.config = &TMCMotionController.config; + Evalboards.ch1.config->state = CONFIG_READY; + Evalboards.ch1.config->configIndex = 0; + + // A value of 0 indicates the Evalboard not connecting the VM line, + // resulting in skipped global minimum voltage checks. + // A negative value indicates no board being connected, which skips the + // minimum voltage check for that channel + Evalboards.ch1.VMMin = -1; + Evalboards.ch1.VMMax = s32_MAX; + + Evalboards.ch1.numberOfMotors = 0; + Evalboards.ch1.errors = 0; + + Evalboards.ch1.config->channel = CHANNEL_1; + + board_setDummyFunctions(&Evalboards.ch1); +} diff --git a/Clean_TMC2209/lib/tmc/boards/TMCMotionController.h b/Clean_TMC2209/lib/tmc/boards/TMCMotionController.h new file mode 100644 index 0000000..a6df4d2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/boards/TMCMotionController.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCMOTIONCONTROLLER_H_ +#define TMCMOTIONCONTROLLER_H_ + + #include "Board.h" + + typedef struct + { + ConfigurationTypeDef config; + } EvalBoardMotionControllerTypeDef; + + extern EvalBoardMotionControllerTypeDef TMCMotionController; + + void tmcmotioncontroller_init(); + +#endif /* TMCMOTIONCONTROLLER_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/ADCs.h b/Clean_TMC2209/lib/tmc/hal/ADCs.h new file mode 100644 index 0000000..3feb9c4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/ADCs.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef ADC_H +#define ADC_H + +#include + +#define N_O_ADC_CHANNELS 7 + +static volatile uint16_t ADCValue[N_O_ADC_CHANNELS]; + +typedef struct +{ + volatile uint16_t *AIN0; + volatile uint16_t *AIN1; + volatile uint16_t *AIN2; + volatile uint16_t *DIO4; + volatile uint16_t *DIO5; + volatile uint16_t *VM; + volatile uint16_t *AIN_EXT; // Only LB_V3 + void (*init)(); + void (*deInit)(); +} ADCTypeDef; + +extern ADCTypeDef ADCs; + +#endif /* ADC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/HAL.h b/Clean_TMC2209/lib/tmc/hal/HAL.h new file mode 100644 index 0000000..d7e7100 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/HAL.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _HAL_H_ +#define _HAL_H_ + +#include "derivative.h" +#include "IOs.h" +#include "IOMap.h" +#include "SPI.h" +#include "ADCs.h" +#include "USB.h" +#include "LEDs.h" +#include "RS232.h" +#include "WLAN.h" +#include "Timer.h" +#include "SysTick.h" +#include "UART.h" + +typedef struct +{ + IOsTypeDef *config; + IOPinMapTypeDef *pins; +} IOsFunctionsTypeDef; + +typedef struct +{ + void (*init) (void); + void (*reset) (uint8_t ResetPeripherals); + void (*NVIC_DeInit)(void); + const IOsFunctionsTypeDef *IOs; + SPITypeDef *SPI; + RXTXTypeDef *USB; + LEDsTypeDef *LEDs; + ADCTypeDef *ADCs; + RXTXTypeDef *RS232; + RXTXTypeDef *WLAN; + TimerTypeDef *Timer; + UART_Config *UART; +} HALTypeDef; + +extern const HALTypeDef HAL; + +extern uint8_t hwid; + +#endif /* _HAL_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/IOMap.h b/Clean_TMC2209/lib/tmc/hal/IOMap.h new file mode 100644 index 0000000..d5c806b --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/IOMap.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _IO_PIN_MAP_H_ +#define _IO_PIN_MAP_H_ + +#include "IOs.h" + +typedef struct +{ + void (*init) (void); + + IOPinTypeDef **pins; // Map Pin ID <=> Pin + + IOPinTypeDef ID_CLK; + IOPinTypeDef ID_CH0; + IOPinTypeDef ID_CH1; + + IOPinTypeDef DIO0; + IOPinTypeDef DIO1; + IOPinTypeDef DIO2; + IOPinTypeDef DIO3; + IOPinTypeDef DIO4; + IOPinTypeDef DIO5; + IOPinTypeDef DIO6; + IOPinTypeDef DIO7; + IOPinTypeDef DIO8; + IOPinTypeDef DIO9; + IOPinTypeDef DIO10; + IOPinTypeDef DIO11; + IOPinTypeDef CLK16; + IOPinTypeDef SPI2_CSN0; + IOPinTypeDef SPI2_CSN1; + IOPinTypeDef SPI2_CSN2; + IOPinTypeDef SPI2_SCK; + IOPinTypeDef SPI2_SDO; + IOPinTypeDef SPI2_SDI; + + IOPinTypeDef SPI1_CSN; + IOPinTypeDef SPI1_SCK; + IOPinTypeDef SPI1_SDI; + IOPinTypeDef SPI1_SDO; + + IOPinTypeDef DIO12; + IOPinTypeDef DIO13; + IOPinTypeDef DIO14; + IOPinTypeDef DIO15; + IOPinTypeDef DIO16; + IOPinTypeDef DIO17; + IOPinTypeDef DIO18; + IOPinTypeDef DIO19; + + IOPinTypeDef RS232_TX; + IOPinTypeDef RS232_RX; + + IOPinTypeDef USB_V_BUS; + IOPinTypeDef USB_V_DM; + IOPinTypeDef USB_V_DP; + + IOPinTypeDef LED_STAT; + IOPinTypeDef LED_ERROR; + + IOPinTypeDef EEPROM_SCK; + IOPinTypeDef EEPROM_SI; + IOPinTypeDef EEPROM_SO; + IOPinTypeDef EEPROM_NCS; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + IOPinTypeDef WIRELESS_TX; + IOPinTypeDef WIRELESS_RX; + IOPinTypeDef WIRELESS_NRST; + IOPinTypeDef MIXED0; + IOPinTypeDef MIXED1; + IOPinTypeDef MIXED2; + IOPinTypeDef MIXED3; + IOPinTypeDef MIXED4; + IOPinTypeDef MIXED5; + IOPinTypeDef MIXED6; + IOPinTypeDef ID_HW_0; + IOPinTypeDef ID_HW_1; + IOPinTypeDef ID_HW_2; + IOPinTypeDef EXTIO_2; + IOPinTypeDef EXTIO_3; + IOPinTypeDef EXTIO_4; + IOPinTypeDef EXTIO_5; + IOPinTypeDef EXTIO_6; + IOPinTypeDef EXTIO_7; +#endif + +#if defined(LandungsbrueckeV3) + IOPinTypeDef DIO10_PWM_WL; + IOPinTypeDef DIO10_UART_TX; + IOPinTypeDef DIO11_PWM_WH; + IOPinTypeDef DIO11_UART_RX; + IOPinTypeDef SW_UART_PWM; + IOPinTypeDef EXT0; + IOPinTypeDef EXT1; + IOPinTypeDef EXT2; + IOPinTypeDef EXT3; + IOPinTypeDef EXT4; + IOPinTypeDef ADC_VM; + IOPinTypeDef AIN0; + IOPinTypeDef AIN1; + IOPinTypeDef AIN2; + IOPinTypeDef AIN_EXT; + IOPinTypeDef WIFI_EN; + IOPinTypeDef WIFI_RST; + IOPinTypeDef WIFI_TX; + IOPinTypeDef WIFI_RX; + IOPinTypeDef BUTTON; +#endif + + IOPinTypeDef DUMMY; +} IOPinMapTypeDef; + +extern IOPinMapTypeDef IOMap; + +#endif /* _IO_PIN_MAP_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/IOs.h b/Clean_TMC2209/lib/tmc/hal/IOs.h new file mode 100644 index 0000000..00d6e58 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/IOs.h @@ -0,0 +1,164 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _IO_H_ +#define _IO_H_ + +// #include "derivative.h" + +typedef enum { // Give bits explicitly, because IDE relies on it. + IOS_LOW = 0b00, + IOS_HIGH = 0b01, + IOS_OPEN = 0b10, + IOS_NOCHANGE = 0b11 +} IO_States; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // use ST like configuration structures also for Landungsbruecke + + typedef enum + { + GPIO_Mode_AN = 0x00, /*!< GPIO Analog Mode, Pin disabled */ + GPIO_Mode_AF1 = 0x01, /*!< GPIO Alternate function Mode GPIO*/ + GPIO_Mode_AF2 = 0x02, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF3 = 0x03, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF4 = 0x04, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF5 = 0x05, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF6 = 0x06, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF7 = 0x07, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_IN = 0x08, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x09 /*!< GPIO Output Mode */ + } GPIOMode_TypeDef; + + typedef enum + { + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 + } GPIOOType_TypeDef; + + typedef enum + { + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 + } GPIOPuPd_TypeDef; + + typedef enum + { + GPIO_Speed_2MHz = 0x00, /*!< Low speed */ + GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ + GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ + GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + } GPIOSpeed_TypeDef; + + #include "hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h" +#elif defined(LandungsbrueckeV3) +// typedef enum +// { +// GPIO_MODE_INPUT = 0x00, /*!< GPIO Input Mode */ +// GPIO_MODE_OUTPUT = 0x01, /*!< GPIO Output Mode */ +// GPIO_MODE_AF = 0x02, /*!< GPIO Alternate function Mode*/ +// GPIO_MODE_ANALOG = 0x03, /*!< GPIO Analog Mode*/ +// } GPIOMode_TypeDef; +// +// typedef enum +// { +// GPIO_OTYPE_PP = 0x00, +// GPIO_OTYPE_OD = 0x01 +// } GPIOOType_TypeDef; +// +// typedef enum +// { +// GPIO_PUPD_NONE = 0x00, +// GPIO_PUPD_PULLUP = 0x01, +// GPIO_PUPD_PULLDOWN = 0x02 +// } GPIOPuPd_TypeDef; +// +// typedef enum +// { +// GPIO_OSPEED_2MHZ = 0x00, /*!< Low speed */ +// GPIO_OSPEED_25MHZ = 0x01, /*!< Medium speed */ +// GPIO_OSPEED_50MHZ = 0x02, /*!< Fast speed */ +// GPIO_OSPEED_MAX = 0x03 /*!< GPIO very high output speed, max speed more than 50MHz */ +// } GPIOSpeed_TypeDef; + typedef uint32_t GPIOMode_TypeDef; + typedef uint32_t GPIOOType_TypeDef; + typedef uint32_t GPIOPuPd_TypeDef; + typedef uint32_t GPIOSpeed_TypeDef; + + +#endif + + +enum IOsHighLevelFunctions { IO_DEFAULT, IO_DI, IO_AI, IO_DO, IO_PWM, IO_SD, IO_CLK16, IO_SPI }; + +typedef struct +{ + const uint8_t DEFAULT; + const uint8_t DI; + const uint8_t AI; + const uint8_t DO; + const uint8_t PWM; + const uint8_t SD; + const uint8_t CLK16; + const uint8_t SPI; +} IOsHighLevelFunctionTypeDef; + +typedef struct +{ + GPIOMode_TypeDef GPIO_Mode; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOOType_TypeDef GPIO_OType; + GPIOPuPd_TypeDef GPIO_PuPd; +} IOPinInitTypeDef; + +typedef struct +{ + #if defined(LandungsbrueckeV3) + uint32_t port; + volatile uint32_t *setBitRegister; + volatile uint32_t *resetBitRegister; + #elif defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + PORT_MemMapPtr portBase; + GPIO_MemMapPtr GPIOBase; + volatile uint32_t *setBitRegister; + volatile uint32_t *resetBitRegister; + #endif + uint32_t bitWeight; + unsigned char bit; + IOPinInitTypeDef configuration; + IOPinInitTypeDef resetConfiguration; + enum IOsHighLevelFunctions highLevelFunction; + IO_States state; +} IOPinTypeDef; + +typedef struct +{ + void (*set)(IOPinTypeDef *pin); + void (*copy)(IOPinInitTypeDef *from, IOPinTypeDef*to); + void (*reset)(IOPinTypeDef *pin); + void (*toOutput)(IOPinTypeDef *pin); + void (*toInput)(IOPinTypeDef *pin); + + void (*setHigh)(IOPinTypeDef *pin); + void (*setLow)(IOPinTypeDef *pin); + void (*setToState)(IOPinTypeDef *pin, IO_States state); + IO_States (*getState)(IOPinTypeDef *pin); + unsigned char (*isHigh)(IOPinTypeDef *pin); + void (*init)(void); + IOsHighLevelFunctionTypeDef HIGH_LEVEL_FUNCTIONS; +} IOsTypeDef; + +extern IOsTypeDef IOs; + +// A bit weight of 0 is used to indicate a nonexistent pin +#define DUMMY_BITWEIGHT 0 +#define IS_DUMMY_PIN(pin) (pin->bitWeight == DUMMY_BITWEIGHT) + +#endif /* _IO_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/LEDs.h b/Clean_TMC2209/lib/tmc/hal/LEDs.h new file mode 100644 index 0000000..87dc536 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/LEDs.h @@ -0,0 +1,49 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef LEDS_H_ +#define LEDS_H_ + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define LED_ON() *HAL.IOs->pins->LED_STAT.resetBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_OFF() *HAL.IOs->pins->LED_STAT.setBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_TOGGLE() HAL.IOs->pins->LED_STAT.GPIOBase->PTOR ^= GPIO_PTOR_PTTO(HAL.IOs->pins->LED_STAT.bitWeight) + + #define LED_ERROR_ON() *HAL.IOs->pins->LED_ERROR.resetBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_OFF() *HAL.IOs->pins->LED_ERROR.setBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_TOGGLE() HAL.IOs->pins->LED_ERROR.GPIOBase->PTOR ^= GPIO_PTOR_PTTO(HAL.IOs->pins->LED_ERROR.bitWeight) +#elif defined(LandungsbrueckeV3) + #define LED_ON() *HAL.IOs->pins->LED_STAT.resetBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_OFF() *HAL.IOs->pins->LED_STAT.setBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_TOGGLE() GPIO_TG(HAL.IOs->pins->LED_STAT.port) = HAL.IOs->pins->LED_STAT.bitWeight + + #define LED_ERROR_ON() *HAL.IOs->pins->LED_ERROR.resetBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_OFF() *HAL.IOs->pins->LED_ERROR.setBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_TOGGLE() GPIO_TG(HAL.IOs->pins->LED_ERROR.port) = HAL.IOs->pins->LED_ERROR.bitWeight +#endif + + #include "IOs.h" + + typedef struct + { + void (*on)(void); + void (*off)(void); + void (*toggle)(void); + } LEDTypeDef; + + typedef struct + { + void (*init)(void); + LEDTypeDef stat; + LEDTypeDef error; + } LEDsTypeDef; + + extern LEDsTypeDef LEDs; + +#endif /* LEDS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c new file mode 100644 index 0000000..52a35ee --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c @@ -0,0 +1,295 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.c +** Project : FS_TC_Test +** Processor : MK20DN512VLL10 +** Component : MK20DN512LL10 +** Version : Component 01.000, Driver 01.04, CPU db: 3.00.000 +** Datasheet : K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Compiler : GNU C Compiler +** Date/Time : 2014-12-22, 13:39, # CodeGen: 7 +** Abstract : +** +** Settings : +** +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file Cpu.c +** @version 01.04 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +/* MODULE Cpu. */ + +/* {Default RTOS Adapter} No RTOS includes */ + +#include "hal/derivative.h" +#include "Cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Global variables */ +volatile uint8 SR_reg; /* Current value of the FAULTMASK register */ +volatile uint8 SR_lock = 0x00U; /* Lock */ + +void LowLevelInit(void); +void InitClocks(void); + + +CpuTypeDef Cpu = +{ + .initClocks = InitClocks, + .initLowLevel = LowLevelInit, +}; + +/* +** =================================================================== +** Method : Cpu_SetBASEPRI (component MK20DN512LL10) +** +** Description : +** This method sets the BASEPRI core register. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void Cpu_SetBASEPRI(uint32 Level); + +/* +** =================================================================== +** Method : Cpu_INT_NMIInterrupt (component MK20DN512LL10) +** +** Description : +** This ISR services the Non Maskable Interrupt interrupt. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void __attribute__ ((interrupt)) Cpu_INT_NMIInterrupt(void) +{ + +} + +/* +** =================================================================== +** Method : Cpu_Cpu_Interrupt (component MK20DN512LL10) +** +** Description : +** This ISR services an unused interrupt/exception vector. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void __attribute__ ((interrupt)) Cpu_Interrupt(void) +{ + /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */ + PE_DEBUGHALT(); +} + + +/***************************************************************//** + \fn InitClocks(void) + \brief Initialize the clock PLL + + This function inializes the PLL to 96MHz (with 16MHz crystal + freqeuncy) and then switches to PLL clock. + So the following frequencies are used: + Core: 96MHz + Bus: 48MHz + FlexBus: 48MHz + Flash: 24MHz + + This routine has been generated by ProcessorExpert and cleaned + up manually. +********************************************************************/ +void InitClocks(void) +{ + //Turn on clocking for all ports to enable pin routing + SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK + | SIM_SCGC5_PORTB_MASK + | SIM_SCGC5_PORTC_MASK + | SIM_SCGC5_PORTD_MASK + | SIM_SCGC5_PORTE_MASK ); + + //PLL already selected by bootloader? => exit + if((MCG_S & 0x0C)==0x0C) return; + + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | + SIM_CLKDIV1_OUTDIV2(0x01) | + SIM_CLKDIV1_OUTDIV3(0x03) | + SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ + + if((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) + { + /* PMC_REGSC: ACKISO=1 */ + PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ + } + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | + SIM_CLKDIV1_OUTDIV2(0x01) | + SIM_CLKDIV1_OUTDIV3(0x01) | + SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */ + /* SIM_SOPT2: PLLFLLSEL=1 */ + SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK|SIM_SOPT2_CLKOUTSEL(6); /* Select PLL as a clock source for various peripherals */ + /* SIM_SOPT1: OSC32KSEL=3 */ + SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ + /* Switch to FBE Mode */ + /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ + MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK); + /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC_CR = OSC_CR_ERCLKEN_MASK; + /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); + /* MCG_C4: DMX32=0,DRST_DRS=0 */ + MCG_C4 &= (uint8)~(uint8)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); + /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ + MCG_C5 = MCG_C5_PRDIV0(0x03); + /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ + MCG_C6 = MCG_C6_VDIV0(0x00); + while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U); /* Check that the oscillator is running */ + while((MCG_S & MCG_S_IREFST_MASK) != 0x00U); /* Check that the source of the FLL reference clock is the external reference clock. */ + while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */ + /* Switch to PBE Mode */ + /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ + MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); + while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */ + while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ + /* Switch to PEE Mode */ + /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); + while((MCG_S & 0x0CU) != 0x0CU); /* Wait until output of the PLL is selected */ +} + +/* +** =================================================================== +** Method : Cpu_SetBASEPRI (component MK20DN512LL10) +** +** Description : +** This method sets the BASEPRI core register. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +/*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */ +#ifdef _lint + #define Cpu_SetBASEPRI(Level) /* empty */ +#else +void Cpu_SetBASEPRI(uint32 Level) { + __asm ("msr basepri, %[input]"::[input] "r" (Level):); +} +#endif +/*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + + + +/***************************************************************//** + \fn LowLevelInit(void) + \brief Low level initialization of the MCU + + This function does some low level initialization of the MCU. + Generated by ProcessorExpert and then cleaned up manually. +********************************************************************/ +void LowLevelInit(void) +{ + /* Initialization of the RCM module */ //***TEST_OK: Kann je nach Beschaltung des Reset-Pins zum Absturz führen + /* RCM_RPFW: RSTFLTSEL=0 */ + RCM_RPFW &= (uint8)~(uint8)(RCM_RPFW_RSTFLTSEL(0x1F)); + /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */ + RCM_RPFC &= (uint8)~(uint8)( + RCM_RPFC_RSTFLTSS_MASK | + RCM_RPFC_RSTFLTSRW(0x03) + ); + /* Initialization of the FTFL_FlashConfig module */ + /* SIM_SCGC7: MPU=1 */ + SIM_SCGC7 |= SIM_SCGC7_MPU_MASK; + /* Initialization of the MPU module */ + + //Turn off MPU (important e.g. for the USB stack to work properly) + /* MPU_CESR: SPERR=0,VLD=0 */ + MPU_CESR &= (uint32)~(uint32)((MPU_CESR_SPERR(0x1F) | MPU_CESR_VLD_MASK)); + + /* Initialization of the PMC module */ + /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */ + PMC_LVDSC1 = (uint8)((PMC_LVDSC1 & (uint8)~(uint8)( + PMC_LVDSC1_LVDIE_MASK | + PMC_LVDSC1_LVDV(0x03) + )) | (uint8)( + PMC_LVDSC1_LVDACK_MASK | + PMC_LVDSC1_LVDRE_MASK + )); + /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */ + PMC_LVDSC2 = (uint8)((PMC_LVDSC2 & (uint8)~(uint8)( + PMC_LVDSC2_LVWIE_MASK | + PMC_LVDSC2_LVWV(0x03) + )) | (uint8)( + PMC_LVDSC2_LVWACK_MASK + )); + /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */ + PMC_REGSC &= (uint8)~(uint8)( + PMC_REGSC_BGEN_MASK | + PMC_REGSC_ACKISO_MASK | + PMC_REGSC_BGBE_MASK + ); + /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */ + SMC_PMPROT = 0x00U; /* Setup Power mode protection register */ + + //Interrupt priority base setting + Cpu_SetBASEPRI(0); +} + + + + +/* END Cpu. */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h new file mode 100644 index 0000000..0331eb2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.h +** Project : FS_TC_Test +** Processor : MK20DN512VLL10 +** Component : MK20DN512LL10 +** Version : Component 01.000, Driver 01.04, CPU db: 3.00.000 +** Datasheet : K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Compiler : GNU C Compiler +** Date/Time : 2014-12-17, 14:57, # CodeGen: 6 +** Abstract : +** +** Settings : +** +** Contents : +** No public methods +** +** (c) Freescale Semiconductor, Inc. +** 2004 All Rights Reserved +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file Cpu.h +** @version 01.04 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +#ifndef __Cpu_H +#define __Cpu_H + +/* MODULE Cpu. */ +/*Include shared modules, which are used for whole project*/ +#include "USB_CDC/PE_Types.h" +#include "USB_CDC/PE_Error.h" +#include "USB_CDC/PE_Const.h" +#include "hal/derivative.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Active configuration define symbol */ +#define PEcfg_FLASH 1U + +/* Methods configuration constants - generated for all enabled component's methods */ + +/* Events configuration constants - generated for all enabled component's events */ +#define Cpu_OnNMIINT_EVENT_ENABLED + +#define CPU_BUS_CLK_HZ 48000000U /* Initial value of the bus clock frequency in Hz */ +#define CPU_CORE_CLK_HZ 96000000U /* Initial value of the core/system clock frequency in Hz. */ + +#define CPU_CLOCK_CONFIG_NUMBER 0x01U /* Specifies number of defined clock configurations. */ + +#define CPU_BUS_CLK_HZ_CLOCK_CONFIG0 48000000U /* Value of the bus clock frequency in the clock configuration 0 in Hz. */ +#define CPU_CORE_CLK_HZ_CLOCK_CONFIG0 96000000U /* Value of the core/system clock frequency in the clock configuration 0 in Hz. */ + + +#define CPU_XTAL_CLK_HZ 16000000U /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ + +#define CPU_FAMILY_Kinetis /* Specification of the core type of the selected cpu */ +#define CPU_DERIVATIVE_MK20DN512LL10 /* Name of the selected cpu derivative */ +#define CPU_PARTNUM_MK20DN512VLL10 /* Part number of the selected cpu */ +#define CPU_LITTLE_ENDIAN /* The selected cpu uses little endian */ + + +/* CPU frequencies in clock configuration 0 */ +#define CPU_CLOCK_CONFIG_0 0x00U /* Clock configuration 0 identifier */ +#define CPU_CORE_CLK_HZ_CONFIG_0 96000000UL /* Core clock frequency in clock configuration 0 */ +#define CPU_BUS_CLK_HZ_CONFIG_0 48000000UL /* Bus clock frequency in clock configuration 0 */ +#define CPU_FLEXBUS_CLK_HZ_CONFIG_0 48000000UL /* Flexbus clock frequency in clock configuration 0 */ +#define CPU_FLASH_CLK_HZ_CONFIG_0 24000000UL /* FLASH clock frequency in clock configuration 0 */ +#define CPU_USB_CLK_HZ_CONFIG_0 0UL /* USB clock frequency in clock configuration 0 */ +#define CPU_PLL_FLL_CLK_HZ_CONFIG_0 96000000UL /* PLL/FLL clock frequency in clock configuration 0 */ +#define CPU_MCGIR_CLK_HZ_CONFIG_0 32768UL /* MCG internal reference clock frequency in clock configuration 0 */ +#define CPU_OSCER_CLK_HZ_CONFIG_0 16000000UL /* System OSC external reference clock frequency in clock configuration 0 */ +#define CPU_ERCLK32K_CLK_HZ_CONFIG_0 1000UL /* External reference clock 32k frequency in clock configuration 0 */ +#define CPU_MCGFF_CLK_HZ_CONFIG_0 31250UL /* MCG fixed frequency clock */ + + +typedef struct { + uint32 cpu_core_clk_hz; /* Core clock frequency in clock configuration */ + uint32 cpu_bus_clk_hz; /* Bus clock frequency in clock configuration */ + uint32 cpu_flexbus_clk_hz; /* Flexbus clock frequency in clock configuration */ + uint32 cpu_flash_clk_hz; /* FLASH clock frequency in clock configuration */ + uint32 cpu_usb_clk_hz; /* USB clock frequency in clock configuration */ + uint32 cpu_pll_fll_clk_hz; /* PLL/FLL clock frequency in clock configuration */ + uint32 cpu_mcgir_clk_hz; /* MCG internal reference clock frequency in clock configuration */ + uint32 cpu_oscer_clk_hz; /* System OSC external reference clock frequency in clock configuration */ + uint32 cpu_erclk32k_clk_hz; /* External reference clock 32k frequency in clock configuration */ + uint32 cpu_mcgff_clk_hz; /* MCG fixed frequency clock */ +} TCpuClockConfiguration; + +/* The array of clock frequencies in configured clock configurations */ +extern const TCpuClockConfiguration PE_CpuClockConfigurations[CPU_CLOCK_CONFIG_NUMBER]; + + /* Interrupt vector table type definition */ + typedef void (*const tIsrFunc)(void); + typedef struct { + void * __ptr; + tIsrFunc __fun[0x77]; + } tVectorTable; + + extern const tVectorTable __vect_table; + +/* Global variables */ +/*lint -esym(765,SR_reg) Disable MISRA rule (8.10) checking for symbols (SR_reg). The SR_reg is used in inline assembler. */ +extern volatile uint8 SR_reg; /* Current FAULTMASK register */ +/*lint -esym(765,SR_lock) Disable MISRA rule (8.10) checking for symbols (SR_lock). The SR_reg is used in inline assembler. */ +extern volatile uint8 SR_lock; + + +typedef struct +{ + void (*initClocks)(void); + void (*initLowLevel)(void); +} CpuTypeDef; + + +extern CpuTypeDef Cpu; + + +/* {Default RTOS Adapter} ISR function prototype */ +void __attribute__ ((interrupt)) Cpu_INT_NMIInterrupt(void); +/* +** =================================================================== +** Method : Cpu_INT_NMIInterrupt (component MK20DN512LL10) +** +** Description : +** This ISR services the Non Maskable Interrupt interrupt. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void __attribute__ ((interrupt)) Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Cpu_Interrupt (component MK20DN512LL10) +** +** Description : +** This ISR services an unused interrupt/exception vector. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END Cpu. */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif +/* __Cpu_H */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h new file mode 100644 index 0000000..2887b0d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h @@ -0,0 +1,14458 @@ +//#include "typedefs.h" +/* +** ################################################################### +** Processors: MK20DN512VLK10 +** MK20DX256VLK10 +** MK20DN512VLL10 +** MK20DX256VLL10 +** MK20DN512VLQ10 +** MK20DX128VLQ10 +** MK20DX256VLQ10 +** MK20DN512VMB10 +** MK20DX256VMB10 +** MK20DN512VMC10 +** MK20DX256VMC10 +** MK20DN512VMD10 +** MK20DX256VMD10 +** MK20DX128VMD10 +** +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K20P144M100SF2V2RM Rev. 1, Jan 2012 +** Version: rev. 1.1, 2012-01-10 +** +** Abstract: +** This header file implements peripheral memory map for MK20D10 +** processor. +** +** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-09-15) +** Initial version +** - rev. 1.1 (2012-01-10) +** Registers updated according to the new reference manual revision - Rev. 1, Jan 2012 +** +** ################################################################### +*/ + +/** + * @file MK20D10.h + * @version 1.1 + * @date 2012-01-10 + * @brief Peripheral memory map for MK20D10 + * + * This header file implements peripheral memory map for MK20D10 processor. + */ + + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCU_MK20D10) /* Check if memory map has not been already included */ +#define MCU_MK20D10 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MK20D10 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001u + +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG(Reg,Bit) (*((uint32 volatile*)(0x42000000u + (32u*((uint32)&(Reg) - (uint32)0x40000000u)) + (4u*((uint32)(Bit)))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +typedef enum { + INT_Initial_Stack_Pointer = 0, /**< Initial Stack Pointer */ + INT_Initial_Program_Counter = 1, /**< Initial Program Counter */ + INT_NMI = 2, /**< Non-maskable Interrupt (NMI) */ + INT_Hard_Fault = 3, /**< Hard Fault */ + INT_Mem_Manage_Fault = 4, /**< MemManage Fault */ + INT_Bus_Fault = 5, /**< Bus Fault */ + INT_Usage_Fault = 6, /**< Usage Fault */ + INT_Reserved7 = 7, /**< Reserved interrupt 7 */ + INT_Reserved8 = 8, /**< Reserved interrupt 8 */ + INT_Reserved9 = 9, /**< Reserved interrupt 9 */ + INT_Reserved10 = 10, /**< Reserved interrupt 10 */ + INT_SVCall = 11, /**< Supervisor call (SVCall) */ + INT_DebugMonitor = 12, /**< Debug Monitor */ + INT_Reserved13 = 13, /**< Reserved interrupt 13 */ + INT_PendableSrvReq = 14, /**< Pendable request for system service (PendableSrvReq) */ + INT_SysTick = 15, /**< SysTick Interrupt */ + INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */ + INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */ + INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */ + INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */ + INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */ + INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */ + INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */ + INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */ + INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */ + INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */ + INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */ + INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */ + INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */ + INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */ + INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */ + INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */ + INT_DMA_Error = 32, /**< DMA Error Interrupt */ + INT_MCM = 33, /**< Normal Interrupt */ + INT_FTFL = 34, /**< FTFL Interrupt */ + INT_Read_Collision = 35, /**< Read Collision Interrupt */ + INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */ + INT_LLW = 37, /**< Low Leakage Wakeup */ + INT_Watchdog = 38, /**< WDOG Interrupt */ + INT_Reserved39 = 39, /**< Reserved Interrupt 39 */ + INT_I2C0 = 40, /**< I2C0 interrupt */ + INT_I2C1 = 41, /**< I2C1 interrupt */ + INT_SPI0 = 42, /**< SPI0 Interrupt */ + INT_SPI1 = 43, /**< SPI1 Interrupt */ + INT_SPI2 = 44, /**< SPI2 Interrupt */ + INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd message buffers interrupt */ + INT_CAN0_Bus_Off = 46, /**< CAN0 bus off interrupt */ + INT_CAN0_Error = 47, /**< CAN0 error interrupt */ + INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx warning interrupt */ + INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx warning interrupt */ + INT_CAN0_Wake_Up = 50, /**< CAN0 wake up interrupt */ + INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */ + INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */ + INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd message buffers interrupt */ + INT_CAN1_Bus_Off = 54, /**< CAN1 bus off interrupt */ + INT_CAN1_Error = 55, /**< CAN1 error interrupt */ + INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx warning interrupt */ + INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx warning interrupt */ + INT_CAN1_Wake_Up = 58, /**< CAN1 wake up interrupt */ + INT_Reserved59 = 59, /**< Reserved interrupt 59 */ + INT_UART0_LON = 60, /**< UART0 LON interrupt */ + INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */ + INT_UART0_ERR = 62, /**< UART0 Error interrupt */ + INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */ + INT_UART1_ERR = 64, /**< UART1 Error interrupt */ + INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */ + INT_UART2_ERR = 66, /**< UART2 Error interrupt */ + INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */ + INT_UART3_ERR = 68, /**< UART3 Error interrupt */ + INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */ + INT_UART4_ERR = 70, /**< UART4 Error interrupt */ + INT_UART5_RX_TX = 71, /**< UART5 Receive/Transmit interrupt */ + INT_UART5_ERR = 72, /**< UART5 Error interrupt */ + INT_ADC0 = 73, /**< ADC0 interrupt */ + INT_ADC1 = 74, /**< ADC1 interrupt */ + INT_CMP0 = 75, /**< CMP0 interrupt */ + INT_CMP1 = 76, /**< CMP1 interrupt */ + INT_CMP2 = 77, /**< CMP2 interrupt */ + INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */ + INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */ + INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */ + INT_CMT = 81, /**< CMT interrupt */ + INT_RTC = 82, /**< RTC interrupt */ + INT_RTC_Seconds = 83, /**< RTC seconds interrupt */ + INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */ + INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */ + INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */ + INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */ + INT_PDB0 = 88, /**< PDB0 Interrupt */ + INT_USB0 = 89, /**< USB0 interrupt */ + INT_USBDCD = 90, /**< USBDCD Interrupt */ + INT_Reserved91 = 91, /**< Reserved interrupt 91 */ + INT_Reserved92 = 92, /**< Reserved interrupt 92 */ + INT_Reserved93 = 93, /**< Reserved interrupt 93 */ + INT_Reserved94 = 94, /**< Reserved interrupt 94 */ + INT_Reserved95 = 95, /**< Reserved interrupt 95 */ + INT_SDHC = 96, /**< SDHC Interrupt */ + INT_DAC0 = 97, /**< DAC0 interrupt */ + INT_DAC1 = 98, /**< DAC1 interrupt */ + INT_TSI0 = 99, /**< TSI0 Interrupt */ + INT_MCG = 100, /**< MCG Interrupt */ + INT_LPTimer = 101, /**< LPTimer interrupt */ + INT_Reserved102 = 102, /**< Reserved interrupt 102 */ + INT_PORTA = 103, /**< Port A interrupt */ + INT_PORTB = 104, /**< Port B interrupt */ + INT_PORTC = 105, /**< Port C interrupt */ + INT_PORTD = 106, /**< Port D interrupt */ + INT_PORTE = 107, /**< Port E interrupt */ + INT_Reserved108 = 108, /**< Reserved interrupt 108 */ + INT_Reserved109 = 109, /**< Reserved interrupt 109 */ + INT_SWI = 110, /**< Software interrupt */ + INT_Reserved111 = 111, /**< Reserved interrupt 111 */ + INT_Reserved112 = 112, /**< Reserved interrupt 112 */ + INT_Reserved113 = 113, /**< Reserved interrupt 113 */ + INT_Reserved114 = 114, /**< Reserved interrupt 114 */ + INT_Reserved115 = 115, /**< Reserved interrupt 115 */ + INT_Reserved116 = 116, /**< Reserved interrupt 116 */ + INT_Reserved117 = 117, /**< Reserved interrupt 117 */ + INT_Reserved118 = 118, /**< Reserved interrupt 118 */ + INT_Reserved119 = 119 /**< Reserved interrupt 119 */ +} IRQInterruptIndex; + +/** + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Peripheral type defines + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Peripheral_defines Peripheral type defines + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Peripheral ADC + * @{ + */ + +/** ADC - Peripheral register structure */ +typedef struct ADC_MemMap { + uint32 SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + uint32 CFG1; /**< ADC configuration register 1, offset: 0x8 */ + uint32 CFG2; /**< Configuration register 2, offset: 0xC */ + uint32 R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + uint32 CV1; /**< Compare value registers, offset: 0x18 */ + uint32 CV2; /**< Compare value registers, offset: 0x1C */ + uint32 SC2; /**< Status and control register 2, offset: 0x20 */ + uint32 SC3; /**< Status and control register 3, offset: 0x24 */ + uint32 OFS; /**< ADC offset correction register, offset: 0x28 */ + uint32 PG; /**< ADC plus-side gain register, offset: 0x2C */ + uint32 MG; /**< ADC minus-side gain register, offset: 0x30 */ + uint32 CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + uint32 CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + uint32 CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + uint32 CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + uint32 CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + uint32 CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + uint32 CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + uint32 PGA; /**< ADC PGA register, offset: 0x50 */ + uint32 CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + uint32 CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + uint32 CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + uint32 CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + uint32 CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + uint32 CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + uint32 CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} volatile *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_SC1_REG(base,index) ((base)->SC1[index]) +#define ADC_CFG1_REG(base) ((base)->CFG1) +#define ADC_CFG2_REG(base) ((base)->CFG2) +#define ADC_R_REG(base,index) ((base)->R[index]) +#define ADC_CV1_REG(base) ((base)->CV1) +#define ADC_CV2_REG(base) ((base)->CV2) +#define ADC_SC2_REG(base) ((base)->SC2) +#define ADC_SC3_REG(base) ((base)->SC3) +#define ADC_OFS_REG(base) ((base)->OFS) +#define ADC_PG_REG(base) ((base)->PG) +#define ADC_MG_REG(base) ((base)->MG) +#define ADC_CLPD_REG(base) ((base)->CLPD) +#define ADC_CLPS_REG(base) ((base)->CLPS) +#define ADC_CLP4_REG(base) ((base)->CLP4) +#define ADC_CLP3_REG(base) ((base)->CLP3) +#define ADC_CLP2_REG(base) ((base)->CLP2) +#define ADC_CLP1_REG(base) ((base)->CLP1) +#define ADC_CLP0_REG(base) ((base)->CLP0) +#define ADC_PGA_REG(base) ((base)->PGA) +#define ADC_CLMD_REG(base) ((base)->CLMD) +#define ADC_CLMS_REG(base) ((base)->CLMS) +#define ADC_CLM4_REG(base) ((base)->CLM4) +#define ADC_CLM3_REG(base) ((base)->CLM3) +#define ADC_CLM2_REG(base) ((base)->CLM2) +#define ADC_CLM1_REG(base) ((base)->CLM1) +#define ADC_CLM0_REG(base) ((base)->CLM0) + +/** + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32)(((uint32)(x))<MPRA) +#define AIPS_PACRA_REG(base) ((base)->PACRA) +#define AIPS_PACRB_REG(base) ((base)->PACRB) +#define AIPS_PACRC_REG(base) ((base)->PACRC) +#define AIPS_PACRD_REG(base) ((base)->PACRD) +#define AIPS_PACRE_REG(base) ((base)->PACRE) +#define AIPS_PACRF_REG(base) ((base)->PACRF) +#define AIPS_PACRG_REG(base) ((base)->PACRG) +#define AIPS_PACRH_REG(base) ((base)->PACRH) +#define AIPS_PACRI_REG(base) ((base)->PACRI) +#define AIPS_PACRJ_REG(base) ((base)->PACRJ) +#define AIPS_PACRK_REG(base) ((base)->PACRK) +#define AIPS_PACRL_REG(base) ((base)->PACRL) +#define AIPS_PACRM_REG(base) ((base)->PACRM) +#define AIPS_PACRN_REG(base) ((base)->PACRN) +#define AIPS_PACRO_REG(base) ((base)->PACRO) +#define AIPS_PACRP_REG(base) ((base)->PACRP) + +/** + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AIPS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AIPS_Register_Masks AIPS Register Masks + * @{ + */ + +/* MPRA Bit Fields */ +#define AIPS_MPRA_MPL5_MASK 0x100u +#define AIPS_MPRA_MPL5_SHIFT 8 +#define AIPS_MPRA_MTW5_MASK 0x200u +#define AIPS_MPRA_MTW5_SHIFT 9 +#define AIPS_MPRA_MTR5_MASK 0x400u +#define AIPS_MPRA_MTR5_SHIFT 10 +#define AIPS_MPRA_MPL4_MASK 0x1000u +#define AIPS_MPRA_MPL4_SHIFT 12 +#define AIPS_MPRA_MTW4_MASK 0x2000u +#define AIPS_MPRA_MTW4_SHIFT 13 +#define AIPS_MPRA_MTR4_MASK 0x4000u +#define AIPS_MPRA_MTR4_SHIFT 14 +#define AIPS_MPRA_MPL3_MASK 0x10000u +#define AIPS_MPRA_MPL3_SHIFT 16 +#define AIPS_MPRA_MTW3_MASK 0x20000u +#define AIPS_MPRA_MTW3_SHIFT 17 +#define AIPS_MPRA_MTR3_MASK 0x40000u +#define AIPS_MPRA_MTR3_SHIFT 18 +#define AIPS_MPRA_MPL2_MASK 0x100000u +#define AIPS_MPRA_MPL2_SHIFT 20 +#define AIPS_MPRA_MTW2_MASK 0x200000u +#define AIPS_MPRA_MTW2_SHIFT 21 +#define AIPS_MPRA_MTR2_MASK 0x400000u +#define AIPS_MPRA_MTR2_SHIFT 22 +#define AIPS_MPRA_MPL1_MASK 0x1000000u +#define AIPS_MPRA_MPL1_SHIFT 24 +#define AIPS_MPRA_MTW1_MASK 0x2000000u +#define AIPS_MPRA_MTW1_SHIFT 25 +#define AIPS_MPRA_MTR1_MASK 0x4000000u +#define AIPS_MPRA_MTR1_SHIFT 26 +#define AIPS_MPRA_MPL0_MASK 0x10000000u +#define AIPS_MPRA_MPL0_SHIFT 28 +#define AIPS_MPRA_MTW0_MASK 0x20000000u +#define AIPS_MPRA_MTW0_SHIFT 29 +#define AIPS_MPRA_MTR0_MASK 0x40000000u +#define AIPS_MPRA_MTR0_SHIFT 30 +/* PACRA Bit Fields */ +#define AIPS_PACRA_TP7_MASK 0x1u +#define AIPS_PACRA_TP7_SHIFT 0 +#define AIPS_PACRA_WP7_MASK 0x2u +#define AIPS_PACRA_WP7_SHIFT 1 +#define AIPS_PACRA_SP7_MASK 0x4u +#define AIPS_PACRA_SP7_SHIFT 2 +#define AIPS_PACRA_TP6_MASK 0x10u +#define AIPS_PACRA_TP6_SHIFT 4 +#define AIPS_PACRA_WP6_MASK 0x20u +#define AIPS_PACRA_WP6_SHIFT 5 +#define AIPS_PACRA_SP6_MASK 0x40u +#define AIPS_PACRA_SP6_SHIFT 6 +#define AIPS_PACRA_TP5_MASK 0x100u +#define AIPS_PACRA_TP5_SHIFT 8 +#define AIPS_PACRA_WP5_MASK 0x200u +#define AIPS_PACRA_WP5_SHIFT 9 +#define AIPS_PACRA_SP5_MASK 0x400u +#define AIPS_PACRA_SP5_SHIFT 10 +#define AIPS_PACRA_TP4_MASK 0x1000u +#define AIPS_PACRA_TP4_SHIFT 12 +#define AIPS_PACRA_WP4_MASK 0x2000u +#define AIPS_PACRA_WP4_SHIFT 13 +#define AIPS_PACRA_SP4_MASK 0x4000u +#define AIPS_PACRA_SP4_SHIFT 14 +#define AIPS_PACRA_TP3_MASK 0x10000u +#define AIPS_PACRA_TP3_SHIFT 16 +#define AIPS_PACRA_WP3_MASK 0x20000u +#define AIPS_PACRA_WP3_SHIFT 17 +#define AIPS_PACRA_SP3_MASK 0x40000u +#define AIPS_PACRA_SP3_SHIFT 18 +#define AIPS_PACRA_TP2_MASK 0x100000u +#define AIPS_PACRA_TP2_SHIFT 20 +#define AIPS_PACRA_WP2_MASK 0x200000u +#define AIPS_PACRA_WP2_SHIFT 21 +#define AIPS_PACRA_SP2_MASK 0x400000u +#define AIPS_PACRA_SP2_SHIFT 22 +#define AIPS_PACRA_TP1_MASK 0x1000000u +#define AIPS_PACRA_TP1_SHIFT 24 +#define AIPS_PACRA_WP1_MASK 0x2000000u +#define AIPS_PACRA_WP1_SHIFT 25 +#define AIPS_PACRA_SP1_MASK 0x4000000u +#define AIPS_PACRA_SP1_SHIFT 26 +#define AIPS_PACRA_TP0_MASK 0x10000000u +#define AIPS_PACRA_TP0_SHIFT 28 +#define AIPS_PACRA_WP0_MASK 0x20000000u +#define AIPS_PACRA_WP0_SHIFT 29 +#define AIPS_PACRA_SP0_MASK 0x40000000u +#define AIPS_PACRA_SP0_SHIFT 30 +/* PACRB Bit Fields */ +#define AIPS_PACRB_TP7_MASK 0x1u +#define AIPS_PACRB_TP7_SHIFT 0 +#define AIPS_PACRB_WP7_MASK 0x2u +#define AIPS_PACRB_WP7_SHIFT 1 +#define AIPS_PACRB_SP7_MASK 0x4u +#define AIPS_PACRB_SP7_SHIFT 2 +#define AIPS_PACRB_TP6_MASK 0x10u +#define AIPS_PACRB_TP6_SHIFT 4 +#define AIPS_PACRB_WP6_MASK 0x20u +#define AIPS_PACRB_WP6_SHIFT 5 +#define AIPS_PACRB_SP6_MASK 0x40u +#define AIPS_PACRB_SP6_SHIFT 6 +#define AIPS_PACRB_TP5_MASK 0x100u +#define AIPS_PACRB_TP5_SHIFT 8 +#define AIPS_PACRB_WP5_MASK 0x200u +#define AIPS_PACRB_WP5_SHIFT 9 +#define AIPS_PACRB_SP5_MASK 0x400u +#define AIPS_PACRB_SP5_SHIFT 10 +#define AIPS_PACRB_TP4_MASK 0x1000u +#define AIPS_PACRB_TP4_SHIFT 12 +#define AIPS_PACRB_WP4_MASK 0x2000u +#define AIPS_PACRB_WP4_SHIFT 13 +#define AIPS_PACRB_SP4_MASK 0x4000u +#define AIPS_PACRB_SP4_SHIFT 14 +#define AIPS_PACRB_TP3_MASK 0x10000u +#define AIPS_PACRB_TP3_SHIFT 16 +#define AIPS_PACRB_WP3_MASK 0x20000u +#define AIPS_PACRB_WP3_SHIFT 17 +#define AIPS_PACRB_SP3_MASK 0x40000u +#define AIPS_PACRB_SP3_SHIFT 18 +#define AIPS_PACRB_TP2_MASK 0x100000u +#define AIPS_PACRB_TP2_SHIFT 20 +#define AIPS_PACRB_WP2_MASK 0x200000u +#define AIPS_PACRB_WP2_SHIFT 21 +#define AIPS_PACRB_SP2_MASK 0x400000u +#define AIPS_PACRB_SP2_SHIFT 22 +#define AIPS_PACRB_TP1_MASK 0x1000000u +#define AIPS_PACRB_TP1_SHIFT 24 +#define AIPS_PACRB_WP1_MASK 0x2000000u +#define AIPS_PACRB_WP1_SHIFT 25 +#define AIPS_PACRB_SP1_MASK 0x4000000u +#define AIPS_PACRB_SP1_SHIFT 26 +#define AIPS_PACRB_TP0_MASK 0x10000000u +#define AIPS_PACRB_TP0_SHIFT 28 +#define AIPS_PACRB_WP0_MASK 0x20000000u +#define AIPS_PACRB_WP0_SHIFT 29 +#define AIPS_PACRB_SP0_MASK 0x40000000u +#define AIPS_PACRB_SP0_SHIFT 30 +/* PACRC Bit Fields */ +#define AIPS_PACRC_TP7_MASK 0x1u +#define AIPS_PACRC_TP7_SHIFT 0 +#define AIPS_PACRC_WP7_MASK 0x2u +#define AIPS_PACRC_WP7_SHIFT 1 +#define AIPS_PACRC_SP7_MASK 0x4u +#define AIPS_PACRC_SP7_SHIFT 2 +#define AIPS_PACRC_TP6_MASK 0x10u +#define AIPS_PACRC_TP6_SHIFT 4 +#define AIPS_PACRC_WP6_MASK 0x20u +#define AIPS_PACRC_WP6_SHIFT 5 +#define AIPS_PACRC_SP6_MASK 0x40u +#define AIPS_PACRC_SP6_SHIFT 6 +#define AIPS_PACRC_TP5_MASK 0x100u +#define AIPS_PACRC_TP5_SHIFT 8 +#define AIPS_PACRC_WP5_MASK 0x200u +#define AIPS_PACRC_WP5_SHIFT 9 +#define AIPS_PACRC_SP5_MASK 0x400u +#define AIPS_PACRC_SP5_SHIFT 10 +#define AIPS_PACRC_TP4_MASK 0x1000u +#define AIPS_PACRC_TP4_SHIFT 12 +#define AIPS_PACRC_WP4_MASK 0x2000u +#define AIPS_PACRC_WP4_SHIFT 13 +#define AIPS_PACRC_SP4_MASK 0x4000u +#define AIPS_PACRC_SP4_SHIFT 14 +#define AIPS_PACRC_TP3_MASK 0x10000u +#define AIPS_PACRC_TP3_SHIFT 16 +#define AIPS_PACRC_WP3_MASK 0x20000u +#define AIPS_PACRC_WP3_SHIFT 17 +#define AIPS_PACRC_SP3_MASK 0x40000u +#define AIPS_PACRC_SP3_SHIFT 18 +#define AIPS_PACRC_TP2_MASK 0x100000u +#define AIPS_PACRC_TP2_SHIFT 20 +#define AIPS_PACRC_WP2_MASK 0x200000u +#define AIPS_PACRC_WP2_SHIFT 21 +#define AIPS_PACRC_SP2_MASK 0x400000u +#define AIPS_PACRC_SP2_SHIFT 22 +#define AIPS_PACRC_TP1_MASK 0x1000000u +#define AIPS_PACRC_TP1_SHIFT 24 +#define AIPS_PACRC_WP1_MASK 0x2000000u +#define AIPS_PACRC_WP1_SHIFT 25 +#define AIPS_PACRC_SP1_MASK 0x4000000u +#define AIPS_PACRC_SP1_SHIFT 26 +#define AIPS_PACRC_TP0_MASK 0x10000000u +#define AIPS_PACRC_TP0_SHIFT 28 +#define AIPS_PACRC_WP0_MASK 0x20000000u +#define AIPS_PACRC_WP0_SHIFT 29 +#define AIPS_PACRC_SP0_MASK 0x40000000u +#define AIPS_PACRC_SP0_SHIFT 30 +/* PACRD Bit Fields */ +#define AIPS_PACRD_TP7_MASK 0x1u +#define AIPS_PACRD_TP7_SHIFT 0 +#define AIPS_PACRD_WP7_MASK 0x2u +#define AIPS_PACRD_WP7_SHIFT 1 +#define AIPS_PACRD_SP7_MASK 0x4u +#define AIPS_PACRD_SP7_SHIFT 2 +#define AIPS_PACRD_TP6_MASK 0x10u +#define AIPS_PACRD_TP6_SHIFT 4 +#define AIPS_PACRD_WP6_MASK 0x20u +#define AIPS_PACRD_WP6_SHIFT 5 +#define AIPS_PACRD_SP6_MASK 0x40u +#define AIPS_PACRD_SP6_SHIFT 6 +#define AIPS_PACRD_TP5_MASK 0x100u +#define AIPS_PACRD_TP5_SHIFT 8 +#define AIPS_PACRD_WP5_MASK 0x200u +#define AIPS_PACRD_WP5_SHIFT 9 +#define AIPS_PACRD_SP5_MASK 0x400u +#define AIPS_PACRD_SP5_SHIFT 10 +#define AIPS_PACRD_TP4_MASK 0x1000u +#define AIPS_PACRD_TP4_SHIFT 12 +#define AIPS_PACRD_WP4_MASK 0x2000u +#define AIPS_PACRD_WP4_SHIFT 13 +#define AIPS_PACRD_SP4_MASK 0x4000u +#define AIPS_PACRD_SP4_SHIFT 14 +#define AIPS_PACRD_TP3_MASK 0x10000u +#define AIPS_PACRD_TP3_SHIFT 16 +#define AIPS_PACRD_WP3_MASK 0x20000u +#define AIPS_PACRD_WP3_SHIFT 17 +#define AIPS_PACRD_SP3_MASK 0x40000u +#define AIPS_PACRD_SP3_SHIFT 18 +#define AIPS_PACRD_TP2_MASK 0x100000u +#define AIPS_PACRD_TP2_SHIFT 20 +#define AIPS_PACRD_WP2_MASK 0x200000u +#define AIPS_PACRD_WP2_SHIFT 21 +#define AIPS_PACRD_SP2_MASK 0x400000u +#define AIPS_PACRD_SP2_SHIFT 22 +#define AIPS_PACRD_TP1_MASK 0x1000000u +#define AIPS_PACRD_TP1_SHIFT 24 +#define AIPS_PACRD_WP1_MASK 0x2000000u +#define AIPS_PACRD_WP1_SHIFT 25 +#define AIPS_PACRD_SP1_MASK 0x4000000u +#define AIPS_PACRD_SP1_SHIFT 26 +#define AIPS_PACRD_TP0_MASK 0x10000000u +#define AIPS_PACRD_TP0_SHIFT 28 +#define AIPS_PACRD_WP0_MASK 0x20000000u +#define AIPS_PACRD_WP0_SHIFT 29 +#define AIPS_PACRD_SP0_MASK 0x40000000u +#define AIPS_PACRD_SP0_SHIFT 30 +/* PACRE Bit Fields */ +#define AIPS_PACRE_TP7_MASK 0x1u +#define AIPS_PACRE_TP7_SHIFT 0 +#define AIPS_PACRE_WP7_MASK 0x2u +#define AIPS_PACRE_WP7_SHIFT 1 +#define AIPS_PACRE_SP7_MASK 0x4u +#define AIPS_PACRE_SP7_SHIFT 2 +#define AIPS_PACRE_TP6_MASK 0x10u +#define AIPS_PACRE_TP6_SHIFT 4 +#define AIPS_PACRE_WP6_MASK 0x20u +#define AIPS_PACRE_WP6_SHIFT 5 +#define AIPS_PACRE_SP6_MASK 0x40u +#define AIPS_PACRE_SP6_SHIFT 6 +#define AIPS_PACRE_TP5_MASK 0x100u +#define AIPS_PACRE_TP5_SHIFT 8 +#define AIPS_PACRE_WP5_MASK 0x200u +#define AIPS_PACRE_WP5_SHIFT 9 +#define AIPS_PACRE_SP5_MASK 0x400u +#define AIPS_PACRE_SP5_SHIFT 10 +#define AIPS_PACRE_TP4_MASK 0x1000u +#define AIPS_PACRE_TP4_SHIFT 12 +#define AIPS_PACRE_WP4_MASK 0x2000u +#define AIPS_PACRE_WP4_SHIFT 13 +#define AIPS_PACRE_SP4_MASK 0x4000u +#define AIPS_PACRE_SP4_SHIFT 14 +#define AIPS_PACRE_TP3_MASK 0x10000u +#define AIPS_PACRE_TP3_SHIFT 16 +#define AIPS_PACRE_WP3_MASK 0x20000u +#define AIPS_PACRE_WP3_SHIFT 17 +#define AIPS_PACRE_SP3_MASK 0x40000u +#define AIPS_PACRE_SP3_SHIFT 18 +#define AIPS_PACRE_TP2_MASK 0x100000u +#define AIPS_PACRE_TP2_SHIFT 20 +#define AIPS_PACRE_WP2_MASK 0x200000u +#define AIPS_PACRE_WP2_SHIFT 21 +#define AIPS_PACRE_SP2_MASK 0x400000u +#define AIPS_PACRE_SP2_SHIFT 22 +#define AIPS_PACRE_TP1_MASK 0x1000000u +#define AIPS_PACRE_TP1_SHIFT 24 +#define AIPS_PACRE_WP1_MASK 0x2000000u +#define AIPS_PACRE_WP1_SHIFT 25 +#define AIPS_PACRE_SP1_MASK 0x4000000u +#define AIPS_PACRE_SP1_SHIFT 26 +#define AIPS_PACRE_TP0_MASK 0x10000000u +#define AIPS_PACRE_TP0_SHIFT 28 +#define AIPS_PACRE_WP0_MASK 0x20000000u +#define AIPS_PACRE_WP0_SHIFT 29 +#define AIPS_PACRE_SP0_MASK 0x40000000u +#define AIPS_PACRE_SP0_SHIFT 30 +/* PACRF Bit Fields */ +#define AIPS_PACRF_TP7_MASK 0x1u +#define AIPS_PACRF_TP7_SHIFT 0 +#define AIPS_PACRF_WP7_MASK 0x2u +#define AIPS_PACRF_WP7_SHIFT 1 +#define AIPS_PACRF_SP7_MASK 0x4u +#define AIPS_PACRF_SP7_SHIFT 2 +#define AIPS_PACRF_TP6_MASK 0x10u +#define AIPS_PACRF_TP6_SHIFT 4 +#define AIPS_PACRF_WP6_MASK 0x20u +#define AIPS_PACRF_WP6_SHIFT 5 +#define AIPS_PACRF_SP6_MASK 0x40u +#define AIPS_PACRF_SP6_SHIFT 6 +#define AIPS_PACRF_TP5_MASK 0x100u +#define AIPS_PACRF_TP5_SHIFT 8 +#define AIPS_PACRF_WP5_MASK 0x200u +#define AIPS_PACRF_WP5_SHIFT 9 +#define AIPS_PACRF_SP5_MASK 0x400u +#define AIPS_PACRF_SP5_SHIFT 10 +#define AIPS_PACRF_TP4_MASK 0x1000u +#define AIPS_PACRF_TP4_SHIFT 12 +#define AIPS_PACRF_WP4_MASK 0x2000u +#define AIPS_PACRF_WP4_SHIFT 13 +#define AIPS_PACRF_SP4_MASK 0x4000u +#define AIPS_PACRF_SP4_SHIFT 14 +#define AIPS_PACRF_TP3_MASK 0x10000u +#define AIPS_PACRF_TP3_SHIFT 16 +#define AIPS_PACRF_WP3_MASK 0x20000u +#define AIPS_PACRF_WP3_SHIFT 17 +#define AIPS_PACRF_SP3_MASK 0x40000u +#define AIPS_PACRF_SP3_SHIFT 18 +#define AIPS_PACRF_TP2_MASK 0x100000u +#define AIPS_PACRF_TP2_SHIFT 20 +#define AIPS_PACRF_WP2_MASK 0x200000u +#define AIPS_PACRF_WP2_SHIFT 21 +#define AIPS_PACRF_SP2_MASK 0x400000u +#define AIPS_PACRF_SP2_SHIFT 22 +#define AIPS_PACRF_TP1_MASK 0x1000000u +#define AIPS_PACRF_TP1_SHIFT 24 +#define AIPS_PACRF_WP1_MASK 0x2000000u +#define AIPS_PACRF_WP1_SHIFT 25 +#define AIPS_PACRF_SP1_MASK 0x4000000u +#define AIPS_PACRF_SP1_SHIFT 26 +#define AIPS_PACRF_TP0_MASK 0x10000000u +#define AIPS_PACRF_TP0_SHIFT 28 +#define AIPS_PACRF_WP0_MASK 0x20000000u +#define AIPS_PACRF_WP0_SHIFT 29 +#define AIPS_PACRF_SP0_MASK 0x40000000u +#define AIPS_PACRF_SP0_SHIFT 30 +/* PACRG Bit Fields */ +#define AIPS_PACRG_TP7_MASK 0x1u +#define AIPS_PACRG_TP7_SHIFT 0 +#define AIPS_PACRG_WP7_MASK 0x2u +#define AIPS_PACRG_WP7_SHIFT 1 +#define AIPS_PACRG_SP7_MASK 0x4u +#define AIPS_PACRG_SP7_SHIFT 2 +#define AIPS_PACRG_TP6_MASK 0x10u +#define AIPS_PACRG_TP6_SHIFT 4 +#define AIPS_PACRG_WP6_MASK 0x20u +#define AIPS_PACRG_WP6_SHIFT 5 +#define AIPS_PACRG_SP6_MASK 0x40u +#define AIPS_PACRG_SP6_SHIFT 6 +#define AIPS_PACRG_TP5_MASK 0x100u +#define AIPS_PACRG_TP5_SHIFT 8 +#define AIPS_PACRG_WP5_MASK 0x200u +#define AIPS_PACRG_WP5_SHIFT 9 +#define AIPS_PACRG_SP5_MASK 0x400u +#define AIPS_PACRG_SP5_SHIFT 10 +#define AIPS_PACRG_TP4_MASK 0x1000u +#define AIPS_PACRG_TP4_SHIFT 12 +#define AIPS_PACRG_WP4_MASK 0x2000u +#define AIPS_PACRG_WP4_SHIFT 13 +#define AIPS_PACRG_SP4_MASK 0x4000u +#define AIPS_PACRG_SP4_SHIFT 14 +#define AIPS_PACRG_TP3_MASK 0x10000u +#define AIPS_PACRG_TP3_SHIFT 16 +#define AIPS_PACRG_WP3_MASK 0x20000u +#define AIPS_PACRG_WP3_SHIFT 17 +#define AIPS_PACRG_SP3_MASK 0x40000u +#define AIPS_PACRG_SP3_SHIFT 18 +#define AIPS_PACRG_TP2_MASK 0x100000u +#define AIPS_PACRG_TP2_SHIFT 20 +#define AIPS_PACRG_WP2_MASK 0x200000u +#define AIPS_PACRG_WP2_SHIFT 21 +#define AIPS_PACRG_SP2_MASK 0x400000u +#define AIPS_PACRG_SP2_SHIFT 22 +#define AIPS_PACRG_TP1_MASK 0x1000000u +#define AIPS_PACRG_TP1_SHIFT 24 +#define AIPS_PACRG_WP1_MASK 0x2000000u +#define AIPS_PACRG_WP1_SHIFT 25 +#define AIPS_PACRG_SP1_MASK 0x4000000u +#define AIPS_PACRG_SP1_SHIFT 26 +#define AIPS_PACRG_TP0_MASK 0x10000000u +#define AIPS_PACRG_TP0_SHIFT 28 +#define AIPS_PACRG_WP0_MASK 0x20000000u +#define AIPS_PACRG_WP0_SHIFT 29 +#define AIPS_PACRG_SP0_MASK 0x40000000u +#define AIPS_PACRG_SP0_SHIFT 30 +/* PACRH Bit Fields */ +#define AIPS_PACRH_TP7_MASK 0x1u +#define AIPS_PACRH_TP7_SHIFT 0 +#define AIPS_PACRH_WP7_MASK 0x2u +#define AIPS_PACRH_WP7_SHIFT 1 +#define AIPS_PACRH_SP7_MASK 0x4u +#define AIPS_PACRH_SP7_SHIFT 2 +#define AIPS_PACRH_TP6_MASK 0x10u +#define AIPS_PACRH_TP6_SHIFT 4 +#define AIPS_PACRH_WP6_MASK 0x20u +#define AIPS_PACRH_WP6_SHIFT 5 +#define AIPS_PACRH_SP6_MASK 0x40u +#define AIPS_PACRH_SP6_SHIFT 6 +#define AIPS_PACRH_TP5_MASK 0x100u +#define AIPS_PACRH_TP5_SHIFT 8 +#define AIPS_PACRH_WP5_MASK 0x200u +#define AIPS_PACRH_WP5_SHIFT 9 +#define AIPS_PACRH_SP5_MASK 0x400u +#define AIPS_PACRH_SP5_SHIFT 10 +#define AIPS_PACRH_TP4_MASK 0x1000u +#define AIPS_PACRH_TP4_SHIFT 12 +#define AIPS_PACRH_WP4_MASK 0x2000u +#define AIPS_PACRH_WP4_SHIFT 13 +#define AIPS_PACRH_SP4_MASK 0x4000u +#define AIPS_PACRH_SP4_SHIFT 14 +#define AIPS_PACRH_TP3_MASK 0x10000u +#define AIPS_PACRH_TP3_SHIFT 16 +#define AIPS_PACRH_WP3_MASK 0x20000u +#define AIPS_PACRH_WP3_SHIFT 17 +#define AIPS_PACRH_SP3_MASK 0x40000u +#define AIPS_PACRH_SP3_SHIFT 18 +#define AIPS_PACRH_TP2_MASK 0x100000u +#define AIPS_PACRH_TP2_SHIFT 20 +#define AIPS_PACRH_WP2_MASK 0x200000u +#define AIPS_PACRH_WP2_SHIFT 21 +#define AIPS_PACRH_SP2_MASK 0x400000u +#define AIPS_PACRH_SP2_SHIFT 22 +#define AIPS_PACRH_TP1_MASK 0x1000000u +#define AIPS_PACRH_TP1_SHIFT 24 +#define AIPS_PACRH_WP1_MASK 0x2000000u +#define AIPS_PACRH_WP1_SHIFT 25 +#define AIPS_PACRH_SP1_MASK 0x4000000u +#define AIPS_PACRH_SP1_SHIFT 26 +#define AIPS_PACRH_TP0_MASK 0x10000000u +#define AIPS_PACRH_TP0_SHIFT 28 +#define AIPS_PACRH_WP0_MASK 0x20000000u +#define AIPS_PACRH_WP0_SHIFT 29 +#define AIPS_PACRH_SP0_MASK 0x40000000u +#define AIPS_PACRH_SP0_SHIFT 30 +/* PACRI Bit Fields */ +#define AIPS_PACRI_TP7_MASK 0x1u +#define AIPS_PACRI_TP7_SHIFT 0 +#define AIPS_PACRI_WP7_MASK 0x2u +#define AIPS_PACRI_WP7_SHIFT 1 +#define AIPS_PACRI_SP7_MASK 0x4u +#define AIPS_PACRI_SP7_SHIFT 2 +#define AIPS_PACRI_TP6_MASK 0x10u +#define AIPS_PACRI_TP6_SHIFT 4 +#define AIPS_PACRI_WP6_MASK 0x20u +#define AIPS_PACRI_WP6_SHIFT 5 +#define AIPS_PACRI_SP6_MASK 0x40u +#define AIPS_PACRI_SP6_SHIFT 6 +#define AIPS_PACRI_TP5_MASK 0x100u +#define AIPS_PACRI_TP5_SHIFT 8 +#define AIPS_PACRI_WP5_MASK 0x200u +#define AIPS_PACRI_WP5_SHIFT 9 +#define AIPS_PACRI_SP5_MASK 0x400u +#define AIPS_PACRI_SP5_SHIFT 10 +#define AIPS_PACRI_TP4_MASK 0x1000u +#define AIPS_PACRI_TP4_SHIFT 12 +#define AIPS_PACRI_WP4_MASK 0x2000u +#define AIPS_PACRI_WP4_SHIFT 13 +#define AIPS_PACRI_SP4_MASK 0x4000u +#define AIPS_PACRI_SP4_SHIFT 14 +#define AIPS_PACRI_TP3_MASK 0x10000u +#define AIPS_PACRI_TP3_SHIFT 16 +#define AIPS_PACRI_WP3_MASK 0x20000u +#define AIPS_PACRI_WP3_SHIFT 17 +#define AIPS_PACRI_SP3_MASK 0x40000u +#define AIPS_PACRI_SP3_SHIFT 18 +#define AIPS_PACRI_TP2_MASK 0x100000u +#define AIPS_PACRI_TP2_SHIFT 20 +#define AIPS_PACRI_WP2_MASK 0x200000u +#define AIPS_PACRI_WP2_SHIFT 21 +#define AIPS_PACRI_SP2_MASK 0x400000u +#define AIPS_PACRI_SP2_SHIFT 22 +#define AIPS_PACRI_TP1_MASK 0x1000000u +#define AIPS_PACRI_TP1_SHIFT 24 +#define AIPS_PACRI_WP1_MASK 0x2000000u +#define AIPS_PACRI_WP1_SHIFT 25 +#define AIPS_PACRI_SP1_MASK 0x4000000u +#define AIPS_PACRI_SP1_SHIFT 26 +#define AIPS_PACRI_TP0_MASK 0x10000000u +#define AIPS_PACRI_TP0_SHIFT 28 +#define AIPS_PACRI_WP0_MASK 0x20000000u +#define AIPS_PACRI_WP0_SHIFT 29 +#define AIPS_PACRI_SP0_MASK 0x40000000u +#define AIPS_PACRI_SP0_SHIFT 30 +/* PACRJ Bit Fields */ +#define AIPS_PACRJ_TP7_MASK 0x1u +#define AIPS_PACRJ_TP7_SHIFT 0 +#define AIPS_PACRJ_WP7_MASK 0x2u +#define AIPS_PACRJ_WP7_SHIFT 1 +#define AIPS_PACRJ_SP7_MASK 0x4u +#define AIPS_PACRJ_SP7_SHIFT 2 +#define AIPS_PACRJ_TP6_MASK 0x10u +#define AIPS_PACRJ_TP6_SHIFT 4 +#define AIPS_PACRJ_WP6_MASK 0x20u +#define AIPS_PACRJ_WP6_SHIFT 5 +#define AIPS_PACRJ_SP6_MASK 0x40u +#define AIPS_PACRJ_SP6_SHIFT 6 +#define AIPS_PACRJ_TP5_MASK 0x100u +#define AIPS_PACRJ_TP5_SHIFT 8 +#define AIPS_PACRJ_WP5_MASK 0x200u +#define AIPS_PACRJ_WP5_SHIFT 9 +#define AIPS_PACRJ_SP5_MASK 0x400u +#define AIPS_PACRJ_SP5_SHIFT 10 +#define AIPS_PACRJ_TP4_MASK 0x1000u +#define AIPS_PACRJ_TP4_SHIFT 12 +#define AIPS_PACRJ_WP4_MASK 0x2000u +#define AIPS_PACRJ_WP4_SHIFT 13 +#define AIPS_PACRJ_SP4_MASK 0x4000u +#define AIPS_PACRJ_SP4_SHIFT 14 +#define AIPS_PACRJ_TP3_MASK 0x10000u +#define AIPS_PACRJ_TP3_SHIFT 16 +#define AIPS_PACRJ_WP3_MASK 0x20000u +#define AIPS_PACRJ_WP3_SHIFT 17 +#define AIPS_PACRJ_SP3_MASK 0x40000u +#define AIPS_PACRJ_SP3_SHIFT 18 +#define AIPS_PACRJ_TP2_MASK 0x100000u +#define AIPS_PACRJ_TP2_SHIFT 20 +#define AIPS_PACRJ_WP2_MASK 0x200000u +#define AIPS_PACRJ_WP2_SHIFT 21 +#define AIPS_PACRJ_SP2_MASK 0x400000u +#define AIPS_PACRJ_SP2_SHIFT 22 +#define AIPS_PACRJ_TP1_MASK 0x1000000u +#define AIPS_PACRJ_TP1_SHIFT 24 +#define AIPS_PACRJ_WP1_MASK 0x2000000u +#define AIPS_PACRJ_WP1_SHIFT 25 +#define AIPS_PACRJ_SP1_MASK 0x4000000u +#define AIPS_PACRJ_SP1_SHIFT 26 +#define AIPS_PACRJ_TP0_MASK 0x10000000u +#define AIPS_PACRJ_TP0_SHIFT 28 +#define AIPS_PACRJ_WP0_MASK 0x20000000u +#define AIPS_PACRJ_WP0_SHIFT 29 +#define AIPS_PACRJ_SP0_MASK 0x40000000u +#define AIPS_PACRJ_SP0_SHIFT 30 +/* PACRK Bit Fields */ +#define AIPS_PACRK_TP7_MASK 0x1u +#define AIPS_PACRK_TP7_SHIFT 0 +#define AIPS_PACRK_WP7_MASK 0x2u +#define AIPS_PACRK_WP7_SHIFT 1 +#define AIPS_PACRK_SP7_MASK 0x4u +#define AIPS_PACRK_SP7_SHIFT 2 +#define AIPS_PACRK_TP6_MASK 0x10u +#define AIPS_PACRK_TP6_SHIFT 4 +#define AIPS_PACRK_WP6_MASK 0x20u +#define AIPS_PACRK_WP6_SHIFT 5 +#define AIPS_PACRK_SP6_MASK 0x40u +#define AIPS_PACRK_SP6_SHIFT 6 +#define AIPS_PACRK_TP5_MASK 0x100u +#define AIPS_PACRK_TP5_SHIFT 8 +#define AIPS_PACRK_WP5_MASK 0x200u +#define AIPS_PACRK_WP5_SHIFT 9 +#define AIPS_PACRK_SP5_MASK 0x400u +#define AIPS_PACRK_SP5_SHIFT 10 +#define AIPS_PACRK_TP4_MASK 0x1000u +#define AIPS_PACRK_TP4_SHIFT 12 +#define AIPS_PACRK_WP4_MASK 0x2000u +#define AIPS_PACRK_WP4_SHIFT 13 +#define AIPS_PACRK_SP4_MASK 0x4000u +#define AIPS_PACRK_SP4_SHIFT 14 +#define AIPS_PACRK_TP3_MASK 0x10000u +#define AIPS_PACRK_TP3_SHIFT 16 +#define AIPS_PACRK_WP3_MASK 0x20000u +#define AIPS_PACRK_WP3_SHIFT 17 +#define AIPS_PACRK_SP3_MASK 0x40000u +#define AIPS_PACRK_SP3_SHIFT 18 +#define AIPS_PACRK_TP2_MASK 0x100000u +#define AIPS_PACRK_TP2_SHIFT 20 +#define AIPS_PACRK_WP2_MASK 0x200000u +#define AIPS_PACRK_WP2_SHIFT 21 +#define AIPS_PACRK_SP2_MASK 0x400000u +#define AIPS_PACRK_SP2_SHIFT 22 +#define AIPS_PACRK_TP1_MASK 0x1000000u +#define AIPS_PACRK_TP1_SHIFT 24 +#define AIPS_PACRK_WP1_MASK 0x2000000u +#define AIPS_PACRK_WP1_SHIFT 25 +#define AIPS_PACRK_SP1_MASK 0x4000000u +#define AIPS_PACRK_SP1_SHIFT 26 +#define AIPS_PACRK_TP0_MASK 0x10000000u +#define AIPS_PACRK_TP0_SHIFT 28 +#define AIPS_PACRK_WP0_MASK 0x20000000u +#define AIPS_PACRK_WP0_SHIFT 29 +#define AIPS_PACRK_SP0_MASK 0x40000000u +#define AIPS_PACRK_SP0_SHIFT 30 +/* PACRL Bit Fields */ +#define AIPS_PACRL_TP7_MASK 0x1u +#define AIPS_PACRL_TP7_SHIFT 0 +#define AIPS_PACRL_WP7_MASK 0x2u +#define AIPS_PACRL_WP7_SHIFT 1 +#define AIPS_PACRL_SP7_MASK 0x4u +#define AIPS_PACRL_SP7_SHIFT 2 +#define AIPS_PACRL_TP6_MASK 0x10u +#define AIPS_PACRL_TP6_SHIFT 4 +#define AIPS_PACRL_WP6_MASK 0x20u +#define AIPS_PACRL_WP6_SHIFT 5 +#define AIPS_PACRL_SP6_MASK 0x40u +#define AIPS_PACRL_SP6_SHIFT 6 +#define AIPS_PACRL_TP5_MASK 0x100u +#define AIPS_PACRL_TP5_SHIFT 8 +#define AIPS_PACRL_WP5_MASK 0x200u +#define AIPS_PACRL_WP5_SHIFT 9 +#define AIPS_PACRL_SP5_MASK 0x400u +#define AIPS_PACRL_SP5_SHIFT 10 +#define AIPS_PACRL_TP4_MASK 0x1000u +#define AIPS_PACRL_TP4_SHIFT 12 +#define AIPS_PACRL_WP4_MASK 0x2000u +#define AIPS_PACRL_WP4_SHIFT 13 +#define AIPS_PACRL_SP4_MASK 0x4000u +#define AIPS_PACRL_SP4_SHIFT 14 +#define AIPS_PACRL_TP3_MASK 0x10000u +#define AIPS_PACRL_TP3_SHIFT 16 +#define AIPS_PACRL_WP3_MASK 0x20000u +#define AIPS_PACRL_WP3_SHIFT 17 +#define AIPS_PACRL_SP3_MASK 0x40000u +#define AIPS_PACRL_SP3_SHIFT 18 +#define AIPS_PACRL_TP2_MASK 0x100000u +#define AIPS_PACRL_TP2_SHIFT 20 +#define AIPS_PACRL_WP2_MASK 0x200000u +#define AIPS_PACRL_WP2_SHIFT 21 +#define AIPS_PACRL_SP2_MASK 0x400000u +#define AIPS_PACRL_SP2_SHIFT 22 +#define AIPS_PACRL_TP1_MASK 0x1000000u +#define AIPS_PACRL_TP1_SHIFT 24 +#define AIPS_PACRL_WP1_MASK 0x2000000u +#define AIPS_PACRL_WP1_SHIFT 25 +#define AIPS_PACRL_SP1_MASK 0x4000000u +#define AIPS_PACRL_SP1_SHIFT 26 +#define AIPS_PACRL_TP0_MASK 0x10000000u +#define AIPS_PACRL_TP0_SHIFT 28 +#define AIPS_PACRL_WP0_MASK 0x20000000u +#define AIPS_PACRL_WP0_SHIFT 29 +#define AIPS_PACRL_SP0_MASK 0x40000000u +#define AIPS_PACRL_SP0_SHIFT 30 +/* PACRM Bit Fields */ +#define AIPS_PACRM_TP7_MASK 0x1u +#define AIPS_PACRM_TP7_SHIFT 0 +#define AIPS_PACRM_WP7_MASK 0x2u +#define AIPS_PACRM_WP7_SHIFT 1 +#define AIPS_PACRM_SP7_MASK 0x4u +#define AIPS_PACRM_SP7_SHIFT 2 +#define AIPS_PACRM_TP6_MASK 0x10u +#define AIPS_PACRM_TP6_SHIFT 4 +#define AIPS_PACRM_WP6_MASK 0x20u +#define AIPS_PACRM_WP6_SHIFT 5 +#define AIPS_PACRM_SP6_MASK 0x40u +#define AIPS_PACRM_SP6_SHIFT 6 +#define AIPS_PACRM_TP5_MASK 0x100u +#define AIPS_PACRM_TP5_SHIFT 8 +#define AIPS_PACRM_WP5_MASK 0x200u +#define AIPS_PACRM_WP5_SHIFT 9 +#define AIPS_PACRM_SP5_MASK 0x400u +#define AIPS_PACRM_SP5_SHIFT 10 +#define AIPS_PACRM_TP4_MASK 0x1000u +#define AIPS_PACRM_TP4_SHIFT 12 +#define AIPS_PACRM_WP4_MASK 0x2000u +#define AIPS_PACRM_WP4_SHIFT 13 +#define AIPS_PACRM_SP4_MASK 0x4000u +#define AIPS_PACRM_SP4_SHIFT 14 +#define AIPS_PACRM_TP3_MASK 0x10000u +#define AIPS_PACRM_TP3_SHIFT 16 +#define AIPS_PACRM_WP3_MASK 0x20000u +#define AIPS_PACRM_WP3_SHIFT 17 +#define AIPS_PACRM_SP3_MASK 0x40000u +#define AIPS_PACRM_SP3_SHIFT 18 +#define AIPS_PACRM_TP2_MASK 0x100000u +#define AIPS_PACRM_TP2_SHIFT 20 +#define AIPS_PACRM_WP2_MASK 0x200000u +#define AIPS_PACRM_WP2_SHIFT 21 +#define AIPS_PACRM_SP2_MASK 0x400000u +#define AIPS_PACRM_SP2_SHIFT 22 +#define AIPS_PACRM_TP1_MASK 0x1000000u +#define AIPS_PACRM_TP1_SHIFT 24 +#define AIPS_PACRM_WP1_MASK 0x2000000u +#define AIPS_PACRM_WP1_SHIFT 25 +#define AIPS_PACRM_SP1_MASK 0x4000000u +#define AIPS_PACRM_SP1_SHIFT 26 +#define AIPS_PACRM_TP0_MASK 0x10000000u +#define AIPS_PACRM_TP0_SHIFT 28 +#define AIPS_PACRM_WP0_MASK 0x20000000u +#define AIPS_PACRM_WP0_SHIFT 29 +#define AIPS_PACRM_SP0_MASK 0x40000000u +#define AIPS_PACRM_SP0_SHIFT 30 +/* PACRN Bit Fields */ +#define AIPS_PACRN_TP7_MASK 0x1u +#define AIPS_PACRN_TP7_SHIFT 0 +#define AIPS_PACRN_WP7_MASK 0x2u +#define AIPS_PACRN_WP7_SHIFT 1 +#define AIPS_PACRN_SP7_MASK 0x4u +#define AIPS_PACRN_SP7_SHIFT 2 +#define AIPS_PACRN_TP6_MASK 0x10u +#define AIPS_PACRN_TP6_SHIFT 4 +#define AIPS_PACRN_WP6_MASK 0x20u +#define AIPS_PACRN_WP6_SHIFT 5 +#define AIPS_PACRN_SP6_MASK 0x40u +#define AIPS_PACRN_SP6_SHIFT 6 +#define AIPS_PACRN_TP5_MASK 0x100u +#define AIPS_PACRN_TP5_SHIFT 8 +#define AIPS_PACRN_WP5_MASK 0x200u +#define AIPS_PACRN_WP5_SHIFT 9 +#define AIPS_PACRN_SP5_MASK 0x400u +#define AIPS_PACRN_SP5_SHIFT 10 +#define AIPS_PACRN_TP4_MASK 0x1000u +#define AIPS_PACRN_TP4_SHIFT 12 +#define AIPS_PACRN_WP4_MASK 0x2000u +#define AIPS_PACRN_WP4_SHIFT 13 +#define AIPS_PACRN_SP4_MASK 0x4000u +#define AIPS_PACRN_SP4_SHIFT 14 +#define AIPS_PACRN_TP3_MASK 0x10000u +#define AIPS_PACRN_TP3_SHIFT 16 +#define AIPS_PACRN_WP3_MASK 0x20000u +#define AIPS_PACRN_WP3_SHIFT 17 +#define AIPS_PACRN_SP3_MASK 0x40000u +#define AIPS_PACRN_SP3_SHIFT 18 +#define AIPS_PACRN_TP2_MASK 0x100000u +#define AIPS_PACRN_TP2_SHIFT 20 +#define AIPS_PACRN_WP2_MASK 0x200000u +#define AIPS_PACRN_WP2_SHIFT 21 +#define AIPS_PACRN_SP2_MASK 0x400000u +#define AIPS_PACRN_SP2_SHIFT 22 +#define AIPS_PACRN_TP1_MASK 0x1000000u +#define AIPS_PACRN_TP1_SHIFT 24 +#define AIPS_PACRN_WP1_MASK 0x2000000u +#define AIPS_PACRN_WP1_SHIFT 25 +#define AIPS_PACRN_SP1_MASK 0x4000000u +#define AIPS_PACRN_SP1_SHIFT 26 +#define AIPS_PACRN_TP0_MASK 0x10000000u +#define AIPS_PACRN_TP0_SHIFT 28 +#define AIPS_PACRN_WP0_MASK 0x20000000u +#define AIPS_PACRN_WP0_SHIFT 29 +#define AIPS_PACRN_SP0_MASK 0x40000000u +#define AIPS_PACRN_SP0_SHIFT 30 +/* PACRO Bit Fields */ +#define AIPS_PACRO_TP7_MASK 0x1u +#define AIPS_PACRO_TP7_SHIFT 0 +#define AIPS_PACRO_WP7_MASK 0x2u +#define AIPS_PACRO_WP7_SHIFT 1 +#define AIPS_PACRO_SP7_MASK 0x4u +#define AIPS_PACRO_SP7_SHIFT 2 +#define AIPS_PACRO_TP6_MASK 0x10u +#define AIPS_PACRO_TP6_SHIFT 4 +#define AIPS_PACRO_WP6_MASK 0x20u +#define AIPS_PACRO_WP6_SHIFT 5 +#define AIPS_PACRO_SP6_MASK 0x40u +#define AIPS_PACRO_SP6_SHIFT 6 +#define AIPS_PACRO_TP5_MASK 0x100u +#define AIPS_PACRO_TP5_SHIFT 8 +#define AIPS_PACRO_WP5_MASK 0x200u +#define AIPS_PACRO_WP5_SHIFT 9 +#define AIPS_PACRO_SP5_MASK 0x400u +#define AIPS_PACRO_SP5_SHIFT 10 +#define AIPS_PACRO_TP4_MASK 0x1000u +#define AIPS_PACRO_TP4_SHIFT 12 +#define AIPS_PACRO_WP4_MASK 0x2000u +#define AIPS_PACRO_WP4_SHIFT 13 +#define AIPS_PACRO_SP4_MASK 0x4000u +#define AIPS_PACRO_SP4_SHIFT 14 +#define AIPS_PACRO_TP3_MASK 0x10000u +#define AIPS_PACRO_TP3_SHIFT 16 +#define AIPS_PACRO_WP3_MASK 0x20000u +#define AIPS_PACRO_WP3_SHIFT 17 +#define AIPS_PACRO_SP3_MASK 0x40000u +#define AIPS_PACRO_SP3_SHIFT 18 +#define AIPS_PACRO_TP2_MASK 0x100000u +#define AIPS_PACRO_TP2_SHIFT 20 +#define AIPS_PACRO_WP2_MASK 0x200000u +#define AIPS_PACRO_WP2_SHIFT 21 +#define AIPS_PACRO_SP2_MASK 0x400000u +#define AIPS_PACRO_SP2_SHIFT 22 +#define AIPS_PACRO_TP1_MASK 0x1000000u +#define AIPS_PACRO_TP1_SHIFT 24 +#define AIPS_PACRO_WP1_MASK 0x2000000u +#define AIPS_PACRO_WP1_SHIFT 25 +#define AIPS_PACRO_SP1_MASK 0x4000000u +#define AIPS_PACRO_SP1_SHIFT 26 +#define AIPS_PACRO_TP0_MASK 0x10000000u +#define AIPS_PACRO_TP0_SHIFT 28 +#define AIPS_PACRO_WP0_MASK 0x20000000u +#define AIPS_PACRO_WP0_SHIFT 29 +#define AIPS_PACRO_SP0_MASK 0x40000000u +#define AIPS_PACRO_SP0_SHIFT 30 +/* PACRP Bit Fields */ +#define AIPS_PACRP_TP7_MASK 0x1u +#define AIPS_PACRP_TP7_SHIFT 0 +#define AIPS_PACRP_WP7_MASK 0x2u +#define AIPS_PACRP_WP7_SHIFT 1 +#define AIPS_PACRP_SP7_MASK 0x4u +#define AIPS_PACRP_SP7_SHIFT 2 +#define AIPS_PACRP_TP6_MASK 0x10u +#define AIPS_PACRP_TP6_SHIFT 4 +#define AIPS_PACRP_WP6_MASK 0x20u +#define AIPS_PACRP_WP6_SHIFT 5 +#define AIPS_PACRP_SP6_MASK 0x40u +#define AIPS_PACRP_SP6_SHIFT 6 +#define AIPS_PACRP_TP5_MASK 0x100u +#define AIPS_PACRP_TP5_SHIFT 8 +#define AIPS_PACRP_WP5_MASK 0x200u +#define AIPS_PACRP_WP5_SHIFT 9 +#define AIPS_PACRP_SP5_MASK 0x400u +#define AIPS_PACRP_SP5_SHIFT 10 +#define AIPS_PACRP_TP4_MASK 0x1000u +#define AIPS_PACRP_TP4_SHIFT 12 +#define AIPS_PACRP_WP4_MASK 0x2000u +#define AIPS_PACRP_WP4_SHIFT 13 +#define AIPS_PACRP_SP4_MASK 0x4000u +#define AIPS_PACRP_SP4_SHIFT 14 +#define AIPS_PACRP_TP3_MASK 0x10000u +#define AIPS_PACRP_TP3_SHIFT 16 +#define AIPS_PACRP_WP3_MASK 0x20000u +#define AIPS_PACRP_WP3_SHIFT 17 +#define AIPS_PACRP_SP3_MASK 0x40000u +#define AIPS_PACRP_SP3_SHIFT 18 +#define AIPS_PACRP_TP2_MASK 0x100000u +#define AIPS_PACRP_TP2_SHIFT 20 +#define AIPS_PACRP_WP2_MASK 0x200000u +#define AIPS_PACRP_WP2_SHIFT 21 +#define AIPS_PACRP_SP2_MASK 0x400000u +#define AIPS_PACRP_SP2_SHIFT 22 +#define AIPS_PACRP_TP1_MASK 0x1000000u +#define AIPS_PACRP_TP1_SHIFT 24 +#define AIPS_PACRP_WP1_MASK 0x2000000u +#define AIPS_PACRP_WP1_SHIFT 25 +#define AIPS_PACRP_SP1_MASK 0x4000000u +#define AIPS_PACRP_SP1_SHIFT 26 +#define AIPS_PACRP_TP0_MASK 0x10000000u +#define AIPS_PACRP_TP0_SHIFT 28 +#define AIPS_PACRP_WP0_MASK 0x20000000u +#define AIPS_PACRP_WP0_SHIFT 29 +#define AIPS_PACRP_SP0_MASK 0x40000000u +#define AIPS_PACRP_SP0_SHIFT 30 + +/** + * @} + */ /* end of group AIPS_Register_Masks */ + + +/* AIPS - Peripheral instance base addresses */ +/** Peripheral AIPS0 base pointer */ +#define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u) +/** Peripheral AIPS1 base pointer */ +#define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u) + +/* ---------------------------------------------------------------------------- + -- AIPS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros + * @{ + */ + + +/* AIPS - Register instance definitions */ +/* AIPS0 */ +#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR) +/* AIPS1 */ +#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR) + +/** + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group AIPS_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- AXBS + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Peripheral AXBS + * @{ + */ + +/** AXBS - Peripheral register structure */ +typedef struct AXBS_MemMap { + struct { /* offset: 0x0, array step: 0x100 */ + uint32 PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ + uint8 RESERVED_0[12]; + uint32 CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ + uint8 RESERVED_1[236]; + } SLAVE[5]; + uint8 RESERVED_0[768]; + uint32 MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8 RESERVED_1[252]; + uint32 MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8 RESERVED_2[252]; + uint32 MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8 RESERVED_3[508]; + uint32 MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8 RESERVED_4[252]; + uint32 MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ +} volatile *AXBS_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- AXBS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros + * @{ + */ + + +/* AXBS - Register accessors */ +#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) +#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) +#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) +#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) +#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) +#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) +#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) + +/** + * @} + */ /* end of group AXBS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/* PRS Bit Fields */ +#define AXBS_PRS_M0_MASK 0x7u +#define AXBS_PRS_M0_SHIFT 0 +#define AXBS_PRS_M0(x) (((uint32)(((uint32)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) + +/** + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32)(((uint32)(x))<CR0) +#define CMP_CR1_REG(base) ((base)->CR1) +#define CMP_FPR_REG(base) ((base)->FPR) +#define CMP_SCR_REG(base) ((base)->SCR) +#define CMP_DACCR_REG(base) ((base)->DACCR) +#define CMP_MUXCR_REG(base) ((base)->MUXCR) + +/** + * @} + */ /* end of group CMP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/* CR0 Bit Fields */ +#define CMP_CR0_HYSTCTR_MASK 0x3u +#define CMP_CR0_HYSTCTR_SHIFT 0 +#define CMP_CR0_HYSTCTR(x) (((uint8)(((uint8)(x))<CGH1) +#define CMT_CGL1_REG(base) ((base)->CGL1) +#define CMT_CGH2_REG(base) ((base)->CGH2) +#define CMT_CGL2_REG(base) ((base)->CGL2) +#define CMT_OC_REG(base) ((base)->OC) +#define CMT_MSC_REG(base) ((base)->MSC) +#define CMT_CMD1_REG(base) ((base)->CMD1) +#define CMT_CMD2_REG(base) ((base)->CMD2) +#define CMT_CMD3_REG(base) ((base)->CMD3) +#define CMT_CMD4_REG(base) ((base)->CMD4) +#define CMT_PPS_REG(base) ((base)->PPS) +#define CMT_DMA_REG(base) ((base)->DMA) + +/** + * @} + */ /* end of group CMT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/* CGH1 Bit Fields */ +#define CMT_CGH1_PH_MASK 0xFFu +#define CMT_CGH1_PH_SHIFT 0 +#define CMT_CGH1_PH(x) (((uint8)(((uint8)(x))<ACCESS16BIT.CRCL) +#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) +#define CRC_CRC_REG(base) ((base)->CRC) +#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) +#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) +#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) +#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) +#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) +#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) +#define CRC_GPOLY_REG(base) ((base)->GPOLY) +#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) +#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) +#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) +#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) +#define CRC_CTRL_REG(base) ((base)->CTRL) +#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) + +/** + * @} + */ /* end of group CRC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/* CRCL Bit Fields */ +#define CRC_CRCL_CRCL_MASK 0xFFFFu +#define CRC_CRCL_CRCL_SHIFT 0 +#define CRC_CRCL_CRCL(x) (((uint16)(((uint16)(x))<base_DHCSR_Read) +#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write) +#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR) +#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR) +#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR) + +/** + * @} + */ /* end of group CoreDebug_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CoreDebug Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group CoreDebug_Register_Masks */ + + +/* CoreDebug - Peripheral instance base addresses */ +/** Peripheral CoreDebug base pointer */ +#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u) + +/* ---------------------------------------------------------------------------- + -- CoreDebug - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros + * @{ + */ + + +/* CoreDebug - Register instance definitions */ +/* CoreDebug */ +#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR) +#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR) +#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR) +#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR) +#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR) + +/** + * @} + */ /* end of group CoreDebug_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group CoreDebug_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- DAC + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Peripheral DAC + * @{ + */ + +/** DAC - Peripheral register structure */ +typedef struct DAC_MemMap { + struct { /* offset: 0x0, array step: 0x2 */ + uint8 DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + uint8 DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + uint8 SR; /**< DAC Status Register, offset: 0x20 */ + uint8 C0; /**< DAC Control Register, offset: 0x21 */ + uint8 C1; /**< DAC Control Register 1, offset: 0x22 */ + uint8 C2; /**< DAC Control Register 2, offset: 0x23 */ +} volatile *DAC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DAC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros + * @{ + */ + + +/* DAC - Register accessors */ +#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) +#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) +#define DAC_SR_REG(base) ((base)->SR) +#define DAC_C0_REG(base) ((base)->C0) +#define DAC_C1_REG(base) ((base)->C1) +#define DAC_C2_REG(base) ((base)->C2) + +/** + * @} + */ /* end of group DAC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/* DATL Bit Fields */ +#define DAC_DATL_DATA_MASK 0xFFu +#define DAC_DATL_DATA_SHIFT 0 +#define DAC_DATL_DATA(x) (((uint8)(((uint8)(x))<CR) +#define DMA_ES_REG(base) ((base)->ES) +#define DMA_ERQ_REG(base) ((base)->ERQ) +#define DMA_EEI_REG(base) ((base)->EEI) +#define DMA_CEEI_REG(base) ((base)->CEEI) +#define DMA_SEEI_REG(base) ((base)->SEEI) +#define DMA_CERQ_REG(base) ((base)->CERQ) +#define DMA_SERQ_REG(base) ((base)->SERQ) +#define DMA_CDNE_REG(base) ((base)->CDNE) +#define DMA_SSRT_REG(base) ((base)->SSRT) +#define DMA_CERR_REG(base) ((base)->CERR) +#define DMA_CINT_REG(base) ((base)->CINT) +#define DMA_INT_REG(base) ((base)->INT) +#define DMA_ERR_REG(base) ((base)->ERR) +#define DMA_HRS_REG(base) ((base)->HRS) +#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) +#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) +#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) +#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) +#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) +#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) +#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) +#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) +#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) +#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) +#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) +#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) +#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) +#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) +#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) +#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) +#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) +#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) +#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) +#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) +#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) +#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) +#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) +#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) +#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) +#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) +#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) +#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) +#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) +#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) + +/** + * @} + */ /* end of group DMA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32)(((uint32)(x))<CHCFG[index]) + +/** + * @} + */ /* end of group DMAMUX_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/* CHCFG Bit Fields */ +#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu +#define DMAMUX_CHCFG_SOURCE_SHIFT 0 +#define DMAMUX_CHCFG_SOURCE(x) (((uint8)(((uint8)(x))<CTRL) +#define DWT_CYCCNT_REG(base) ((base)->CYCCNT) +#define DWT_CPICNT_REG(base) ((base)->CPICNT) +#define DWT_EXCCNT_REG(base) ((base)->EXCCNT) +#define DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT) +#define DWT_LSUCNT_REG(base) ((base)->LSUCNT) +#define DWT_FOLDCNT_REG(base) ((base)->FOLDCNT) +#define DWT_PCSR_REG(base) ((base)->PCSR) +#define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) +#define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) +#define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION) +#define DWT_PID4_REG(base) ((base)->PID4) +#define DWT_PID5_REG(base) ((base)->PID5) +#define DWT_PID6_REG(base) ((base)->PID6) +#define DWT_PID7_REG(base) ((base)->PID7) +#define DWT_PID0_REG(base) ((base)->PID0) +#define DWT_PID1_REG(base) ((base)->PID1) +#define DWT_PID2_REG(base) ((base)->PID2) +#define DWT_PID3_REG(base) ((base)->PID3) +#define DWT_CID0_REG(base) ((base)->CID0) +#define DWT_CID1_REG(base) ((base)->CID1) +#define DWT_CID2_REG(base) ((base)->CID2) +#define DWT_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group DWT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DWT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DWT_Register_Masks DWT Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group DWT_Register_Masks */ + + +/* DWT - Peripheral instance base addresses */ +/** Peripheral DWT base pointer */ +#define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u) + +/* ---------------------------------------------------------------------------- + -- DWT - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros + * @{ + */ + + +/* DWT - Register instance definitions */ +/* DWT */ +#define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR) +#define DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR) +#define DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR) +#define DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR) +#define DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR) +#define DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR) +#define DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR) +#define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR) +#define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0) +#define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0) +#define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0) +#define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1) +#define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1) +#define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1) +#define DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2) +#define DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2) +#define DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2) +#define DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3) +#define DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3) +#define DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3) +#define DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR) +#define DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR) +#define DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR) +#define DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR) +#define DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR) +#define DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR) +#define DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR) +#define DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR) +#define DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR) +#define DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR) +#define DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR) +#define DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR) + +/* DWT - Register array accessors */ +#define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index) +#define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index) +#define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index) + +/** + * @} + */ /* end of group DWT_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group DWT_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETB + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Peripheral ETB + * @{ + */ + +/** ETB - Peripheral register structure */ +typedef struct ETB_MemMap { + uint8 RESERVED_0[4]; + uint32 RDP; /**< RAM Depth Register, offset: 0x4 */ + uint8 RESERVED_1[4]; + uint32 STS; /**< Status Register, offset: 0xC */ + uint32 RRD; /**< RAM Read Data Register, offset: 0x10 */ + uint32 RRP; /**< RAM Read Pointer Register, offset: 0x14 */ + uint32 RWP; /**< RAM Write Pointer Register, offset: 0x18 */ + uint32 TRG; /**< Trigger Counter Register, offset: 0x1C */ + uint32 CTL; /**< Control Register, offset: 0x20 */ + uint32 RWD; /**< RAM Write Data Register, offset: 0x24 */ + uint8 RESERVED_2[728]; + uint32 FFSR; /**< Formatter and Flush Status Register, offset: 0x300 */ + uint32 FFCR; /**< Formatter and Flush Control Register, offset: 0x304 */ + uint8 RESERVED_3[3032]; + uint32 ITMISCOP0; /**< Integration Register, ITMISCOP0, offset: 0xEE0 */ + uint32 ITTRFLINACK; /**< Integration Register, ITTRFLINACK, offset: 0xEE4 */ + uint32 ITTRFLIN; /**< Integration Register, ITTRFLIN, offset: 0xEE8 */ + uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ + uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ + uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ + uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ + uint8 RESERVED_4[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_5[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_6[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_7[12]; + uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ + uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros + * @{ + */ + + +/* ETB - Register accessors */ +#define ETB_RDP_REG(base) ((base)->RDP) +#define ETB_STS_REG(base) ((base)->STS) +#define ETB_RRD_REG(base) ((base)->RRD) +#define ETB_RRP_REG(base) ((base)->RRP) +#define ETB_RWP_REG(base) ((base)->RWP) +#define ETB_TRG_REG(base) ((base)->TRG) +#define ETB_CTL_REG(base) ((base)->CTL) +#define ETB_RWD_REG(base) ((base)->RWD) +#define ETB_FFSR_REG(base) ((base)->FFSR) +#define ETB_FFCR_REG(base) ((base)->FFCR) +#define ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0) +#define ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK) +#define ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN) +#define ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0) +#define ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1) +#define ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETB_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETB_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETB_LAR_REG(base) ((base)->LAR) +#define ETB_LSR_REG(base) ((base)->LSR) +#define ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETB_DEVID_REG(base) ((base)->DEVID) +#define ETB_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETB_PIDR4_REG(base) ((base)->PIDR4) +#define ETB_PIDR5_REG(base) ((base)->PIDR5) +#define ETB_PIDR6_REG(base) ((base)->PIDR6) +#define ETB_PIDR7_REG(base) ((base)->PIDR7) +#define ETB_PIDR0_REG(base) ((base)->PIDR0) +#define ETB_PIDR1_REG(base) ((base)->PIDR1) +#define ETB_PIDR2_REG(base) ((base)->PIDR2) +#define ETB_PIDR3_REG(base) ((base)->PIDR3) +#define ETB_CIDR0_REG(base) ((base)->CIDR0) +#define ETB_CIDR1_REG(base) ((base)->CIDR1) +#define ETB_CIDR2_REG(base) ((base)->CIDR2) +#define ETB_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Masks ETB Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETB_Register_Masks */ + + +/* ETB - Peripheral instance base addresses */ +/** Peripheral ETB base pointer */ +#define ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u) + +/* ---------------------------------------------------------------------------- + -- ETB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros + * @{ + */ + + +/* ETB - Register instance definitions */ +/* ETB */ +#define ETB_RDP ETB_RDP_REG(ETB_BASE_PTR) +#define ETB_STS ETB_STS_REG(ETB_BASE_PTR) +#define ETB_RRD ETB_RRD_REG(ETB_BASE_PTR) +#define ETB_RRP ETB_RRP_REG(ETB_BASE_PTR) +#define ETB_RWP ETB_RWP_REG(ETB_BASE_PTR) +#define ETB_TRG ETB_TRG_REG(ETB_BASE_PTR) +#define ETB_CTL ETB_CTL_REG(ETB_BASE_PTR) +#define ETB_RWD ETB_RWD_REG(ETB_BASE_PTR) +#define ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR) +#define ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR) +#define ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR) +#define ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR) +#define ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR) +#define ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR) +#define ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR) +#define ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR) +#define ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR) +#define ETB_LAR ETB_LAR_REG(ETB_BASE_PTR) +#define ETB_LSR ETB_LSR_REG(ETB_BASE_PTR) +#define ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR) +#define ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR) +#define ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR) +#define ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR) +#define ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR) +#define ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR) +#define ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR) +#define ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR) +#define ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR) +#define ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR) +#define ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR) +#define ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR) +#define ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR) +#define ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR) +#define ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR) + +/** + * @} + */ /* end of group ETB_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETB_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETF + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Peripheral ETF + * @{ + */ + +/** ETF - Peripheral register structure */ +typedef struct ETF_MemMap { + uint32 FCR; /**< Funnel Control Register, offset: 0x0 */ + uint32 PCR; /**< Priority Control Register, offset: 0x4 */ + uint8 RESERVED_0[3812]; + uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ + uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ + uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ + uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ + uint8 RESERVED_1[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_2[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_3[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_4[12]; + uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ + uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETF_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros + * @{ + */ + + +/* ETF - Register accessors */ +#define ETF_FCR_REG(base) ((base)->FCR) +#define ETF_PCR_REG(base) ((base)->PCR) +#define ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0) +#define ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1) +#define ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETF_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETF_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETF_LAR_REG(base) ((base)->LAR) +#define ETF_LSR_REG(base) ((base)->LSR) +#define ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETF_DEVID_REG(base) ((base)->DEVID) +#define ETF_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETF_PIDR4_REG(base) ((base)->PIDR4) +#define ETF_PIDR5_REG(base) ((base)->PIDR5) +#define ETF_PIDR6_REG(base) ((base)->PIDR6) +#define ETF_PIDR7_REG(base) ((base)->PIDR7) +#define ETF_PIDR0_REG(base) ((base)->PIDR0) +#define ETF_PIDR1_REG(base) ((base)->PIDR1) +#define ETF_PIDR2_REG(base) ((base)->PIDR2) +#define ETF_PIDR3_REG(base) ((base)->PIDR3) +#define ETF_CIDR0_REG(base) ((base)->CIDR0) +#define ETF_CIDR1_REG(base) ((base)->CIDR1) +#define ETF_CIDR2_REG(base) ((base)->CIDR2) +#define ETF_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Masks ETF Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETF_Register_Masks */ + + +/* ETF - Peripheral instance base addresses */ +/** Peripheral ETF base pointer */ +#define ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u) + +/* ---------------------------------------------------------------------------- + -- ETF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros + * @{ + */ + + +/* ETF - Register instance definitions */ +/* ETF */ +#define ETF_FCR ETF_FCR_REG(ETF_BASE_PTR) +#define ETF_PCR ETF_PCR_REG(ETF_BASE_PTR) +#define ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR) +#define ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR) +#define ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR) +#define ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR) +#define ETF_LAR ETF_LAR_REG(ETF_BASE_PTR) +#define ETF_LSR ETF_LSR_REG(ETF_BASE_PTR) +#define ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR) +#define ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR) +#define ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR) +#define ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR) +#define ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR) +#define ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR) +#define ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR) +#define ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR) +#define ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR) +#define ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR) +#define ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR) +#define ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR) +#define ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR) +#define ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR) +#define ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR) + +/** + * @} + */ /* end of group ETF_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETF_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETM + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Peripheral ETM + * @{ + */ + +/** ETM - Peripheral register structure */ +typedef struct ETM_MemMap { + uint32 CR; /**< Main Control Register, offset: 0x0 */ + uint32 CCR; /**< Configuration Code Register, offset: 0x4 */ + uint32 TRIGGER; /**< Trigger Event Register, offset: 0x8 */ + uint8 RESERVED_0[4]; + uint32 SR; /**< ETM Status Register, offset: 0x10 */ + uint32 SCR; /**< System Configuration Register, offset: 0x14 */ + uint8 RESERVED_1[8]; + uint32 EEVR; /**< Trace Enable Event Register, offset: 0x20 */ + uint32 TECR1; /**< Trace Enable Control 1 Register, offset: 0x24 */ + uint32 FFLR; /**< FIFOFULL Level Register, offset: 0x28 */ + uint8 RESERVED_2[276]; + uint32 CNTRLDVR1; /**< Free-running counter reload value, offset: 0x140 */ + uint8 RESERVED_3[156]; + uint32 SYNCFR; /**< Synchronization Frequency Register, offset: 0x1E0 */ + uint32 IDR; /**< ID Register, offset: 0x1E4 */ + uint32 CCER; /**< Configuration Code Extension Register, offset: 0x1E8 */ + uint8 RESERVED_4[4]; + uint32 TESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register, offset: 0x1F0 */ + uint8 RESERVED_5[4]; + uint32 TSEVR; /**< Timestamp Event Register, offset: 0x1F8 */ + uint8 RESERVED_6[4]; + uint32 TRACEIDR; /**< CoreSight Trace ID Register, offset: 0x200 */ + uint8 RESERVED_7[4]; + uint32 IDR2; /**< ETM ID Register 2, offset: 0x208 */ + uint8 RESERVED_8[264]; + uint32 PDSR; /**< Device Power-Down Status Register, offset: 0x314 */ + uint8 RESERVED_9[3016]; + uint32 ITMISCIN; /**< Integration Test Miscelaneous Inputs Register, offset: 0xEE0 */ + uint8 RESERVED_10[4]; + uint32 ITTRIGOUT; /**< Integration Test Trigger Out Register, offset: 0xEE8 */ + uint8 RESERVED_11[4]; + uint32 ITATBCTR2; /**< ETM Integration Test ATB Control 2 Register, offset: 0xEF0 */ + uint8 RESERVED_12[4]; + uint32 ITATBCTR0; /**< ETM Integration Test ATB Control 0 Register, offset: 0xEF8 */ + uint8 RESERVED_13[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_14[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_15[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_16[16]; + uint32 DEVTYPE; /**< CoreSight Device Type Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros + * @{ + */ + + +/* ETM - Register accessors */ +#define ETM_CR_REG(base) ((base)->CR) +#define ETM_CCR_REG(base) ((base)->CCR) +#define ETM_TRIGGER_REG(base) ((base)->TRIGGER) +#define ETM_SR_REG(base) ((base)->SR) +#define ETM_SCR_REG(base) ((base)->SCR) +#define ETM_EEVR_REG(base) ((base)->EEVR) +#define ETM_TECR1_REG(base) ((base)->TECR1) +#define ETM_FFLR_REG(base) ((base)->FFLR) +#define ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1) +#define ETM_SYNCFR_REG(base) ((base)->SYNCFR) +#define ETM_IDR_REG(base) ((base)->IDR) +#define ETM_CCER_REG(base) ((base)->CCER) +#define ETM_TESSEICR_REG(base) ((base)->TESSEICR) +#define ETM_TSEVR_REG(base) ((base)->TSEVR) +#define ETM_TRACEIDR_REG(base) ((base)->TRACEIDR) +#define ETM_IDR2_REG(base) ((base)->IDR2) +#define ETM_PDSR_REG(base) ((base)->PDSR) +#define ETM_ITMISCIN_REG(base) ((base)->ITMISCIN) +#define ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT) +#define ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETM_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETM_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETM_LAR_REG(base) ((base)->LAR) +#define ETM_LSR_REG(base) ((base)->LSR) +#define ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETM_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETM_PIDR4_REG(base) ((base)->PIDR4) +#define ETM_PIDR5_REG(base) ((base)->PIDR5) +#define ETM_PIDR6_REG(base) ((base)->PIDR6) +#define ETM_PIDR7_REG(base) ((base)->PIDR7) +#define ETM_PIDR0_REG(base) ((base)->PIDR0) +#define ETM_PIDR1_REG(base) ((base)->PIDR1) +#define ETM_PIDR2_REG(base) ((base)->PIDR2) +#define ETM_PIDR3_REG(base) ((base)->PIDR3) +#define ETM_CIDR0_REG(base) ((base)->CIDR0) +#define ETM_CIDR1_REG(base) ((base)->CIDR1) +#define ETM_CIDR2_REG(base) ((base)->CIDR2) +#define ETM_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Masks ETM Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETM_Register_Masks */ + + +/* ETM - Peripheral instance base addresses */ +/** Peripheral ETM base pointer */ +#define ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u) + +/* ---------------------------------------------------------------------------- + -- ETM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros + * @{ + */ + + +/* ETM - Register instance definitions */ +/* ETM */ +#define ETMCR ETM_CR_REG(ETM_BASE_PTR) +#define ETMCCR ETM_CCR_REG(ETM_BASE_PTR) +#define ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR) +#define ETMSR ETM_SR_REG(ETM_BASE_PTR) +#define ETMSCR ETM_SCR_REG(ETM_BASE_PTR) +#define ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR) +#define ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR) +#define ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR) +#define ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR) +#define ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR) +#define ETMIDR ETM_IDR_REG(ETM_BASE_PTR) +#define ETMCCER ETM_CCER_REG(ETM_BASE_PTR) +#define ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR) +#define ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR) +#define ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR) +#define ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR) +#define ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR) +#define ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR) +#define ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR) +#define ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR) +#define ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR) +#define ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR) +#define ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR) +#define ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR) +#define ETMLAR ETM_LAR_REG(ETM_BASE_PTR) +#define ETMLSR ETM_LSR_REG(ETM_BASE_PTR) +#define ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR) +#define ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR) +#define ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR) +#define ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR) +#define ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR) +#define ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR) +#define ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR) +#define ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR) +#define ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR) +#define ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR) +#define ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR) +#define ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR) +#define ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR) +#define ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR) + +/** + * @} + */ /* end of group ETM_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- EWM + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Peripheral EWM + * @{ + */ + +/** EWM - Peripheral register structure */ +typedef struct EWM_MemMap { + uint8 CTRL; /**< Control Register, offset: 0x0 */ + uint8 SERV; /**< Service Register, offset: 0x1 */ + uint8 CMPL; /**< Compare Low Register, offset: 0x2 */ + uint8 CMPH; /**< Compare High Register, offset: 0x3 */ +} volatile *EWM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- EWM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros + * @{ + */ + + +/* EWM - Register accessors */ +#define EWM_CTRL_REG(base) ((base)->CTRL) +#define EWM_SERV_REG(base) ((base)->SERV) +#define EWM_CMPL_REG(base) ((base)->CMPL) +#define EWM_CMPH_REG(base) ((base)->CMPH) + +/** + * @} + */ /* end of group EWM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EWM_CTRL_EWMEN_MASK 0x1u +#define EWM_CTRL_EWMEN_SHIFT 0 +#define EWM_CTRL_ASSIN_MASK 0x2u +#define EWM_CTRL_ASSIN_SHIFT 1 +#define EWM_CTRL_INEN_MASK 0x4u +#define EWM_CTRL_INEN_SHIFT 2 +#define EWM_CTRL_INTEN_MASK 0x8u +#define EWM_CTRL_INTEN_SHIFT 3 +/* SERV Bit Fields */ +#define EWM_SERV_SERVICE_MASK 0xFFu +#define EWM_SERV_SERVICE_SHIFT 0 +#define EWM_SERV_SERVICE(x) (((uint8)(((uint8)(x))<CS[index].CSAR) +#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) +#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) +#define FB_CSPMCR_REG(base) ((base)->CSPMCR) + +/** + * @} + */ /* end of group FB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/* CSAR Bit Fields */ +#define FB_CSAR_BA_MASK 0xFFFF0000u +#define FB_CSAR_BA_SHIFT 16 +#define FB_CSAR_BA(x) (((uint32)(((uint32)(x))<PFAPR) +#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) +#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) +#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) +#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) +#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) + +/** + * @} + */ /* end of group FMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/* PFAPR Bit Fields */ +#define FMC_PFAPR_M0AP_MASK 0x3u +#define FMC_PFAPR_M0AP_SHIFT 0 +#define FMC_PFAPR_M0AP(x) (((uint32)(((uint32)(x))<CTRL) +#define FPB_REMAP_REG(base) ((base)->REMAP) +#define FPB_COMP_REG(base,index) ((base)->COMP[index]) +#define FPB_PID4_REG(base) ((base)->PID4) +#define FPB_PID5_REG(base) ((base)->PID5) +#define FPB_PID6_REG(base) ((base)->PID6) +#define FPB_PID7_REG(base) ((base)->PID7) +#define FPB_PID0_REG(base) ((base)->PID0) +#define FPB_PID1_REG(base) ((base)->PID1) +#define FPB_PID2_REG(base) ((base)->PID2) +#define FPB_PID3_REG(base) ((base)->PID3) +#define FPB_CID0_REG(base) ((base)->CID0) +#define FPB_CID1_REG(base) ((base)->CID1) +#define FPB_CID2_REG(base) ((base)->CID2) +#define FPB_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group FPB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FPB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FPB_Register_Masks FPB Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group FPB_Register_Masks */ + + +/* FPB - Peripheral instance base addresses */ +/** Peripheral FPB base pointer */ +#define FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u) + +/* ---------------------------------------------------------------------------- + -- FPB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros + * @{ + */ + + +/* FPB - Register instance definitions */ +/* FPB */ +#define FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR) +#define FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR) +#define FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0) +#define FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1) +#define FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2) +#define FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3) +#define FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4) +#define FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5) +#define FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6) +#define FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7) +#define FP_PID4 FPB_PID4_REG(FPB_BASE_PTR) +#define FP_PID5 FPB_PID5_REG(FPB_BASE_PTR) +#define FP_PID6 FPB_PID6_REG(FPB_BASE_PTR) +#define FP_PID7 FPB_PID7_REG(FPB_BASE_PTR) +#define FP_PID0 FPB_PID0_REG(FPB_BASE_PTR) +#define FP_PID1 FPB_PID1_REG(FPB_BASE_PTR) +#define FP_PID2 FPB_PID2_REG(FPB_BASE_PTR) +#define FP_PID3 FPB_PID3_REG(FPB_BASE_PTR) +#define FP_CID0 FPB_CID0_REG(FPB_BASE_PTR) +#define FP_CID1 FPB_CID1_REG(FPB_BASE_PTR) +#define FP_CID2 FPB_CID2_REG(FPB_BASE_PTR) +#define FP_CID3 FPB_CID3_REG(FPB_BASE_PTR) + +/* FPB - Register array accessors */ +#define FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index) + +/** + * @} + */ /* end of group FPB_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group FPB_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- FTFL + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Peripheral FTFL + * @{ + */ + +/** FTFL - Peripheral register structure */ +typedef struct FTFL_MemMap { + uint8 FSTAT; /**< Flash Status Register, offset: 0x0 */ + uint8 FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + uint8 FSEC; /**< Flash Security Register, offset: 0x2 */ + uint8 FOPT; /**< Flash Option Register, offset: 0x3 */ + uint8 FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + uint8 FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + uint8 FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + uint8 FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + uint8 FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + uint8 FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + uint8 FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + uint8 FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + uint8 FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + uint8 FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + uint8 FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + uint8 FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + uint8 FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + uint8 FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + uint8 FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + uint8 FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8 RESERVED_0[2]; + uint8 FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ + uint8 FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ +} volatile *FTFL_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- FTFL - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros + * @{ + */ + + +/* FTFL - Register accessors */ +#define FTFL_FSTAT_REG(base) ((base)->FSTAT) +#define FTFL_FCNFG_REG(base) ((base)->FCNFG) +#define FTFL_FSEC_REG(base) ((base)->FSEC) +#define FTFL_FOPT_REG(base) ((base)->FOPT) +#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) +#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) +#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) +#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) +#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) +#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) +#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) +#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) +#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) +#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) +#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) +#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) +#define FTFL_FPROT3_REG(base) ((base)->FPROT3) +#define FTFL_FPROT2_REG(base) ((base)->FPROT2) +#define FTFL_FPROT1_REG(base) ((base)->FPROT1) +#define FTFL_FPROT0_REG(base) ((base)->FPROT0) +#define FTFL_FEPROT_REG(base) ((base)->FEPROT) +#define FTFL_FDPROT_REG(base) ((base)->FDPROT) + +/** + * @} + */ /* end of group FTFL_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTFL Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Masks FTFL Register Masks + * @{ + */ + +/* FSTAT Bit Fields */ +#define FTFL_FSTAT_MGSTAT0_MASK 0x1u +#define FTFL_FSTAT_MGSTAT0_SHIFT 0 +#define FTFL_FSTAT_FPVIOL_MASK 0x10u +#define FTFL_FSTAT_FPVIOL_SHIFT 4 +#define FTFL_FSTAT_ACCERR_MASK 0x20u +#define FTFL_FSTAT_ACCERR_SHIFT 5 +#define FTFL_FSTAT_RDCOLERR_MASK 0x40u +#define FTFL_FSTAT_RDCOLERR_SHIFT 6 +#define FTFL_FSTAT_CCIF_MASK 0x80u +#define FTFL_FSTAT_CCIF_SHIFT 7 +/* FCNFG Bit Fields */ +#define FTFL_FCNFG_EEERDY_MASK 0x1u +#define FTFL_FCNFG_EEERDY_SHIFT 0 +#define FTFL_FCNFG_RAMRDY_MASK 0x2u +#define FTFL_FCNFG_RAMRDY_SHIFT 1 +#define FTFL_FCNFG_PFLSH_MASK 0x4u +#define FTFL_FCNFG_PFLSH_SHIFT 2 +#define FTFL_FCNFG_SWAP_MASK 0x8u +#define FTFL_FCNFG_SWAP_SHIFT 3 +#define FTFL_FCNFG_ERSSUSP_MASK 0x10u +#define FTFL_FCNFG_ERSSUSP_SHIFT 4 +#define FTFL_FCNFG_ERSAREQ_MASK 0x20u +#define FTFL_FCNFG_ERSAREQ_SHIFT 5 +#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u +#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 +#define FTFL_FCNFG_CCIE_MASK 0x80u +#define FTFL_FCNFG_CCIE_SHIFT 7 +/* FSEC Bit Fields */ +#define FTFL_FSEC_SEC_MASK 0x3u +#define FTFL_FSEC_SEC_SHIFT 0 +#define FTFL_FSEC_SEC(x) (((uint8)(((uint8)(x))<SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) +#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FMS_REG(base) ((base)->FMS) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/** + * @} + */ /* end of group FTM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32)(((uint32)(x))<PDOR) +#define GPIO_PSOR_REG(base) ((base)->PSOR) +#define GPIO_PCOR_REG(base) ((base)->PCOR) +#define GPIO_PTOR_REG(base) ((base)->PTOR) +#define GPIO_PDIR_REG(base) ((base)->PDIR) +#define GPIO_PDDR_REG(base) ((base)->PDDR) + +/** + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* PDOR Bit Fields */ +#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu +#define GPIO_PDOR_PDO_SHIFT 0 +#define GPIO_PDOR_PDO(x) (((uint32)(((uint32)(x))<A1) +#define I2C_F_REG(base) ((base)->F) +#define I2C_C1_REG(base) ((base)->C1) +#define I2C_S_REG(base) ((base)->S) +#define I2C_D_REG(base) ((base)->D) +#define I2C_C2_REG(base) ((base)->C2) +#define I2C_FLT_REG(base) ((base)->FLT) +#define I2C_RA_REG(base) ((base)->RA) +#define I2C_SMB_REG(base) ((base)->SMB) +#define I2C_A2_REG(base) ((base)->A2) +#define I2C_SLTH_REG(base) ((base)->SLTH) +#define I2C_SLTL_REG(base) ((base)->SLTL) + +/** + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* A1 Bit Fields */ +#define I2C_A1_AD_MASK 0xFEu +#define I2C_A1_AD_SHIFT 1 +#define I2C_A1_AD(x) (((uint8)(((uint8)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) +#define I2S_MCR_REG(base) ((base)->MCR) +#define I2S_MDR_REG(base) ((base)->MDR) + +/** + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x7u +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32)(((uint32)(x))<STIM_READ[index2]) +#define ITM_STIM_WRITE_REG(base,index2) ((base)->STIM_WRITE[index2]) +#define ITM_TER_REG(base) ((base)->TER) +#define ITM_TPR_REG(base) ((base)->TPR) +#define ITM_TCR_REG(base) ((base)->TCR) +#define ITM_LAR_REG(base) ((base)->LAR) +#define ITM_LSR_REG(base) ((base)->LSR) +#define ITM_PID4_REG(base) ((base)->PID4) +#define ITM_PID5_REG(base) ((base)->PID5) +#define ITM_PID6_REG(base) ((base)->PID6) +#define ITM_PID7_REG(base) ((base)->PID7) +#define ITM_PID0_REG(base) ((base)->PID0) +#define ITM_PID1_REG(base) ((base)->PID1) +#define ITM_PID2_REG(base) ((base)->PID2) +#define ITM_PID3_REG(base) ((base)->PID3) +#define ITM_CID0_REG(base) ((base)->CID0) +#define ITM_CID1_REG(base) ((base)->CID1) +#define ITM_CID2_REG(base) ((base)->CID2) +#define ITM_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group ITM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ITM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ITM_Register_Masks ITM Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ITM_Register_Masks */ + + +/* ITM - Peripheral instance base addresses */ +/** Peripheral ITM base pointer */ +#define ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u) + +/* ---------------------------------------------------------------------------- + -- ITM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros + * @{ + */ + + +/* ITM - Register instance definitions */ +/* ITM */ +#define ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0) +#define ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0) +#define ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1) +#define ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1) +#define ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2) +#define ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2) +#define ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3) +#define ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3) +#define ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4) +#define ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4) +#define ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5) +#define ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5) +#define ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6) +#define ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6) +#define ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7) +#define ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7) +#define ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8) +#define ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8) +#define ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9) +#define ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9) +#define ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10) +#define ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10) +#define ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11) +#define ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11) +#define ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12) +#define ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12) +#define ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13) +#define ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13) +#define ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14) +#define ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14) +#define ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15) +#define ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15) +#define ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16) +#define ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16) +#define ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17) +#define ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17) +#define ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18) +#define ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18) +#define ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19) +#define ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19) +#define ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20) +#define ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20) +#define ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21) +#define ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21) +#define ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22) +#define ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22) +#define ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23) +#define ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23) +#define ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24) +#define ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24) +#define ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25) +#define ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25) +#define ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26) +#define ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26) +#define ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27) +#define ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27) +#define ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28) +#define ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28) +#define ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29) +#define ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29) +#define ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30) +#define ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30) +#define ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31) +#define ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31) +#define ITM_TER ITM_TER_REG(ITM_BASE_PTR) +#define ITM_TPR ITM_TPR_REG(ITM_BASE_PTR) +#define ITM_TCR ITM_TCR_REG(ITM_BASE_PTR) +#define ITM_LAR ITM_LAR_REG(ITM_BASE_PTR) +#define ITM_LSR ITM_LSR_REG(ITM_BASE_PTR) +#define ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR) +#define ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR) +#define ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR) +#define ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR) +#define ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR) +#define ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR) +#define ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR) +#define ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR) +#define ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR) +#define ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR) +#define ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR) +#define ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR) + +/* ITM - Register array accessors */ +#define ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2) +#define ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2) + +/** + * @} + */ /* end of group ITM_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ITM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- LLWU + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Peripheral LLWU + * @{ + */ + +/** LLWU - Peripheral register structure */ +typedef struct LLWU_MemMap { + uint8 PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ + uint8 PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ + uint8 PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ + uint8 PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ + uint8 ME; /**< LLWU Module Enable Register, offset: 0x4 */ + uint8 F1; /**< LLWU Flag 1 Register, offset: 0x5 */ + uint8 F2; /**< LLWU Flag 2 Register, offset: 0x6 */ + uint8 F3; /**< LLWU Flag 3 Register, offset: 0x7 */ + uint8 FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ + uint8 FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ + uint8 RST; /**< LLWU Reset Enable Register, offset: 0xA */ +} volatile *LLWU_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- LLWU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros + * @{ + */ + + +/* LLWU - Register accessors */ +#define LLWU_PE1_REG(base) ((base)->PE1) +#define LLWU_PE2_REG(base) ((base)->PE2) +#define LLWU_PE3_REG(base) ((base)->PE3) +#define LLWU_PE4_REG(base) ((base)->PE4) +#define LLWU_ME_REG(base) ((base)->ME) +#define LLWU_F1_REG(base) ((base)->F1) +#define LLWU_F2_REG(base) ((base)->F2) +#define LLWU_F3_REG(base) ((base)->F3) +#define LLWU_FILT1_REG(base) ((base)->FILT1) +#define LLWU_FILT2_REG(base) ((base)->FILT2) +#define LLWU_RST_REG(base) ((base)->RST) + +/** + * @} + */ /* end of group LLWU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/* PE1 Bit Fields */ +#define LLWU_PE1_WUPE0_MASK 0x3u +#define LLWU_PE1_WUPE0_SHIFT 0 +#define LLWU_PE1_WUPE0(x) (((uint8)(((uint8)(x))<CSR) +#define LPTMR_PSR_REG(base) ((base)->PSR) +#define LPTMR_CMR_REG(base) ((base)->CMR) +#define LPTMR_CNR_REG(base) ((base)->CNR) + +/** + * @} + */ /* end of group LPTMR_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define LPTMR_CSR_TEN_MASK 0x1u +#define LPTMR_CSR_TEN_SHIFT 0 +#define LPTMR_CSR_TMS_MASK 0x2u +#define LPTMR_CSR_TMS_SHIFT 1 +#define LPTMR_CSR_TFC_MASK 0x4u +#define LPTMR_CSR_TFC_SHIFT 2 +#define LPTMR_CSR_TPP_MASK 0x8u +#define LPTMR_CSR_TPP_SHIFT 3 +#define LPTMR_CSR_TPS_MASK 0x30u +#define LPTMR_CSR_TPS_SHIFT 4 +#define LPTMR_CSR_TPS(x) (((uint32)(((uint32)(x))<C1) +#define MCG_C2_REG(base) ((base)->C2) +#define MCG_C3_REG(base) ((base)->C3) +#define MCG_C4_REG(base) ((base)->C4) +#define MCG_C5_REG(base) ((base)->C5) +#define MCG_C6_REG(base) ((base)->C6) +#define MCG_S_REG(base) ((base)->S) +#define MCG_SC_REG(base) ((base)->SC) +#define MCG_ATCVH_REG(base) ((base)->ATCVH) +#define MCG_ATCVL_REG(base) ((base)->ATCVL) +#define MCG_C7_REG(base) ((base)->C7) +#define MCG_C8_REG(base) ((base)->C8) + +/** + * @} + */ /* end of group MCG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/* C1 Bit Fields */ +#define MCG_C1_IREFSTEN_MASK 0x1u +#define MCG_C1_IREFSTEN_SHIFT 0 +#define MCG_C1_IRCLKEN_MASK 0x2u +#define MCG_C1_IRCLKEN_SHIFT 1 +#define MCG_C1_IREFS_MASK 0x4u +#define MCG_C1_IREFS_SHIFT 2 +#define MCG_C1_FRDIV_MASK 0x38u +#define MCG_C1_FRDIV_SHIFT 3 +#define MCG_C1_FRDIV(x) (((uint8)(((uint8)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_CR_REG(base) ((base)->CR) +#define MCM_ISR_REG(base) ((base)->ISR) +#define MCM_ETBCC_REG(base) ((base)->ETBCC) +#define MCM_ETBRL_REG(base) ((base)->ETBRL) +#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) +#define MCM_PID_REG(base) ((base)->PID) + +/** + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16)(((uint16)(x))<CESR) +#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) +#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) +#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) +#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) + +/** + * @} + */ /* end of group MPU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MPU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MPU_Register_Masks MPU Register Masks + * @{ + */ + +/* CESR Bit Fields */ +#define MPU_CESR_VLD_MASK 0x1u +#define MPU_CESR_VLD_SHIFT 0 +#define MPU_CESR_NRGD_MASK 0xF00u +#define MPU_CESR_NRGD_SHIFT 8 +#define MPU_CESR_NRGD(x) (((uint32)(((uint32)(x))<BACKKEY3) +#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) +#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) +#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) +#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) +#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) +#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) +#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) +#define NV_FPROT3_REG(base) ((base)->FPROT3) +#define NV_FPROT2_REG(base) ((base)->FPROT2) +#define NV_FPROT1_REG(base) ((base)->FPROT1) +#define NV_FPROT0_REG(base) ((base)->FPROT0) +#define NV_FSEC_REG(base) ((base)->FSEC) +#define NV_FOPT_REG(base) ((base)->FOPT) +#define NV_FEPROT_REG(base) ((base)->FEPROT) +#define NV_FDPROT_REG(base) ((base)->FDPROT) + +/** + * @} + */ /* end of group NV_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/* BACKKEY3 Bit Fields */ +#define NV_BACKKEY3_KEY_MASK 0xFFu +#define NV_BACKKEY3_KEY_SHIFT 0 +#define NV_BACKKEY3_KEY(x) (((uint8)(((uint8)(x))<ISER[index]) +#define NVIC_ICER_REG(base,index) ((base)->ICER[index]) +#define NVIC_ISPR_REG(base,index) ((base)->ISPR[index]) +#define NVIC_ICPR_REG(base,index) ((base)->ICPR[index]) +#define NVIC_IABR_REG(base,index) ((base)->IABR[index]) +#define NVIC_IP_REG(base,index) ((base)->IP[index]) +#define NVIC_STIR_REG(base,index) ((base)->STIR[index]) + +/** + * @} + */ /* end of group NVIC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- NVIC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NVIC_Register_Masks NVIC Register Masks + * @{ + */ + +/* ISER Bit Fields */ +#define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu +#define NVIC_ISER_SETENA_SHIFT 0 +#define NVIC_ISER_SETENA(x) (((uint32)(((uint32)(x))<CR) + +/** + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define OSC_CR_SC16P_MASK 0x1u +#define OSC_CR_SC16P_SHIFT 0 +#define OSC_CR_SC8P_MASK 0x2u +#define OSC_CR_SC8P_SHIFT 1 +#define OSC_CR_SC4P_MASK 0x4u +#define OSC_CR_SC4P_SHIFT 2 +#define OSC_CR_SC2P_MASK 0x8u +#define OSC_CR_SC2P_SHIFT 3 +#define OSC_CR_EREFSTEN_MASK 0x20u +#define OSC_CR_EREFSTEN_SHIFT 5 +#define OSC_CR_ERCLKEN_MASK 0x80u +#define OSC_CR_ERCLKEN_SHIFT 7 + +/** + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base pointer */ +#define OSC_BASE_PTR ((OSC_MemMapPtr)0x40065000u) + +/* ---------------------------------------------------------------------------- + -- OSC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros + * @{ + */ + + +/* OSC - Register instance definitions */ +/* OSC */ +#define OSC_CR OSC_CR_REG(OSC_BASE_PTR) + +/** + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group OSC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PDB + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Peripheral PDB + * @{ + */ + +/** PDB - Peripheral register structure */ +typedef struct PDB_MemMap { + uint32 SC; /**< Status and Control Register, offset: 0x0 */ + uint32 MOD; /**< Modulus Register, offset: 0x4 */ + uint32 CNT; /**< Counter Register, offset: 0x8 */ + uint32 IDLY; /**< Interrupt Delay Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + uint32 C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */ + uint32 S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */ + uint32 DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8 RESERVED_0[24]; + } CH[2]; + uint8 RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + uint32 INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */ + uint32 INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8 RESERVED_1[48]; + uint32 POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ + uint32 PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ +} volatile *PDB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PDB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros + * @{ + */ + + +/* PDB - Register accessors */ +#define PDB_SC_REG(base) ((base)->SC) +#define PDB_MOD_REG(base) ((base)->MOD) +#define PDB_CNT_REG(base) ((base)->CNT) +#define PDB_IDLY_REG(base) ((base)->IDLY) +#define PDB_C1_REG(base,index) ((base)->CH[index].C1) +#define PDB_S_REG(base,index) ((base)->CH[index].S) +#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) +#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) +#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) +#define PDB_POEN_REG(base) ((base)->POEN) +#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) + +/** + * @} + */ /* end of group PDB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define PDB_SC_LDOK_MASK 0x1u +#define PDB_SC_LDOK_SHIFT 0 +#define PDB_SC_CONT_MASK 0x2u +#define PDB_SC_CONT_SHIFT 1 +#define PDB_SC_MULT_MASK 0xCu +#define PDB_SC_MULT_SHIFT 2 +#define PDB_SC_MULT(x) (((uint32)(((uint32)(x))<MCR) +#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) +#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) +#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) +#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) + +/** + * @} + */ /* end of group PIT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define PIT_MCR_FRZ_MASK 0x1u +#define PIT_MCR_FRZ_SHIFT 0 +#define PIT_MCR_MDIS_MASK 0x2u +#define PIT_MCR_MDIS_SHIFT 1 +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32)(((uint32)(x))<LVDSC1) +#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) +#define PMC_REGSC_REG(base) ((base)->REGSC) + +/** + * @} + */ /* end of group PMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/* LVDSC1 Bit Fields */ +#define PMC_LVDSC1_LVDV_MASK 0x3u +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8)(((uint8)(x))<PCR[index]) +#define PORT_GPCLR_REG(base) ((base)->GPCLR) +#define PORT_GPCHR_REG(base) ((base)->GPCHR) +#define PORT_ISFR_REG(base) ((base)->ISFR) +#define PORT_DFER_REG(base) ((base)->DFER) +#define PORT_DFCR_REG(base) ((base)->DFCR) +#define PORT_DFWR_REG(base) ((base)->DFWR) + +/** + * @} + */ /* end of group PORT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/* PCR Bit Fields */ +#define PORT_PCR_PS_MASK 0x1u +#define PORT_PCR_PS_SHIFT 0 +#define PORT_PCR_PE_MASK 0x2u +#define PORT_PCR_PE_SHIFT 1 +#define PORT_PCR_SRE_MASK 0x4u +#define PORT_PCR_SRE_SHIFT 2 +#define PORT_PCR_PFE_MASK 0x10u +#define PORT_PCR_PFE_SHIFT 4 +#define PORT_PCR_ODE_MASK 0x20u +#define PORT_PCR_ODE_SHIFT 5 +#define PORT_PCR_DSE_MASK 0x40u +#define PORT_PCR_DSE_SHIFT 6 +#define PORT_PCR_MUX_MASK 0x700u +#define PORT_PCR_MUX_SHIFT 8 +#define PORT_PCR_MUX(x) (((uint32)(((uint32)(x))<SRS0) +#define RCM_SRS1_REG(base) ((base)->SRS1) +#define RCM_RPFC_REG(base) ((base)->RPFC) +#define RCM_RPFW_REG(base) ((base)->RPFW) +#define RCM_MR_REG(base) ((base)->MR) + +/** + * @} + */ /* end of group RCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/* SRS0 Bit Fields */ +#define RCM_SRS0_WAKEUP_MASK 0x1u +#define RCM_SRS0_WAKEUP_SHIFT 0 +#define RCM_SRS0_LVD_MASK 0x2u +#define RCM_SRS0_LVD_SHIFT 1 +#define RCM_SRS0_LOC_MASK 0x4u +#define RCM_SRS0_LOC_SHIFT 2 +#define RCM_SRS0_LOL_MASK 0x8u +#define RCM_SRS0_LOL_SHIFT 3 +#define RCM_SRS0_WDOG_MASK 0x20u +#define RCM_SRS0_WDOG_SHIFT 5 +#define RCM_SRS0_PIN_MASK 0x40u +#define RCM_SRS0_PIN_SHIFT 6 +#define RCM_SRS0_POR_MASK 0x80u +#define RCM_SRS0_POR_SHIFT 7 +/* SRS1 Bit Fields */ +#define RCM_SRS1_JTAG_MASK 0x1u +#define RCM_SRS1_JTAG_SHIFT 0 +#define RCM_SRS1_LOCKUP_MASK 0x2u +#define RCM_SRS1_LOCKUP_SHIFT 1 +#define RCM_SRS1_SW_MASK 0x4u +#define RCM_SRS1_SW_SHIFT 2 +#define RCM_SRS1_MDM_AP_MASK 0x8u +#define RCM_SRS1_MDM_AP_SHIFT 3 +#define RCM_SRS1_EZPT_MASK 0x10u +#define RCM_SRS1_EZPT_SHIFT 4 +#define RCM_SRS1_SACKERR_MASK 0x20u +#define RCM_SRS1_SACKERR_SHIFT 5 +/* RPFC Bit Fields */ +#define RCM_RPFC_RSTFLTSRW_MASK 0x3u +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 +#define RCM_RPFC_RSTFLTSRW(x) (((uint8)(((uint8)(x))<REG[index]) + +/** + * @} + */ /* end of group RFSYS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFSYS_REG_LL_MASK 0xFFu +#define RFSYS_REG_LL_SHIFT 0 +#define RFSYS_REG_LL(x) (((uint32)(((uint32)(x))<REG[index]) + +/** + * @} + */ /* end of group RFVBAT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFVBAT_REG_LL_MASK 0xFFu +#define RFVBAT_REG_LL_SHIFT 0 +#define RFVBAT_REG_LL(x) (((uint32)(((uint32)(x))<TSR) +#define RTC_TPR_REG(base) ((base)->TPR) +#define RTC_TAR_REG(base) ((base)->TAR) +#define RTC_TCR_REG(base) ((base)->TCR) +#define RTC_CR_REG(base) ((base)->CR) +#define RTC_SR_REG(base) ((base)->SR) +#define RTC_LR_REG(base) ((base)->LR) +#define RTC_IER_REG(base) ((base)->IER) +#define RTC_WAR_REG(base) ((base)->WAR) +#define RTC_RAR_REG(base) ((base)->RAR) + +/** + * @} + */ /* end of group RTC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/* TSR Bit Fields */ +#define RTC_TSR_TSR_MASK 0xFFFFFFFFu +#define RTC_TSR_TSR_SHIFT 0 +#define RTC_TSR_TSR(x) (((uint32)(((uint32)(x))<ACTLR) +#define SCB_CPUID_REG(base) ((base)->CPUID) +#define SCB_ICSR_REG(base) ((base)->ICSR) +#define SCB_VTOR_REG(base) ((base)->VTOR) +#define SCB_AIRCR_REG(base) ((base)->AIRCR) +#define SCB_SCR_REG(base) ((base)->SCR) +#define SCB_CCR_REG(base) ((base)->CCR) +#define SCB_SHPR1_REG(base) ((base)->SHPR1) +#define SCB_SHPR2_REG(base) ((base)->SHPR2) +#define SCB_SHPR3_REG(base) ((base)->SHPR3) +#define SCB_SHCSR_REG(base) ((base)->SHCSR) +#define SCB_CFSR_REG(base) ((base)->CFSR) +#define SCB_HFSR_REG(base) ((base)->HFSR) +#define SCB_DFSR_REG(base) ((base)->DFSR) +#define SCB_MMFAR_REG(base) ((base)->MMFAR) +#define SCB_BFAR_REG(base) ((base)->BFAR) +#define SCB_AFSR_REG(base) ((base)->AFSR) + +/** + * @} + */ /* end of group SCB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SCB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SCB_Register_Masks SCB Register Masks + * @{ + */ + +/* ACTLR Bit Fields */ +#define SCB_ACTLR_DISMCYCINT_MASK 0x1u +#define SCB_ACTLR_DISMCYCINT_SHIFT 0 +#define SCB_ACTLR_DISDEFWBUF_MASK 0x2u +#define SCB_ACTLR_DISDEFWBUF_SHIFT 1 +#define SCB_ACTLR_DISFOLD_MASK 0x4u +#define SCB_ACTLR_DISFOLD_SHIFT 2 +/* CPUID Bit Fields */ +#define SCB_CPUID_REVISION_MASK 0xFu +#define SCB_CPUID_REVISION_SHIFT 0 +#define SCB_CPUID_REVISION(x) (((uint32)(((uint32)(x))<DSADDR) +#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) +#define SDHC_CMDARG_REG(base) ((base)->CMDARG) +#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) +#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) +#define SDHC_DATPORT_REG(base) ((base)->DATPORT) +#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) +#define SDHC_PROCTL_REG(base) ((base)->PROCTL) +#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) +#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) +#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) +#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) +#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) +#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) +#define SDHC_WML_REG(base) ((base)->WML) +#define SDHC_FEVT_REG(base) ((base)->FEVT) +#define SDHC_ADMAES_REG(base) ((base)->ADMAES) +#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) +#define SDHC_VENDOR_REG(base) ((base)->VENDOR) +#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) +#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) + +/** + * @} + */ /* end of group SDHC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDHC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SDHC_Register_Masks SDHC Register Masks + * @{ + */ + +/* DSADDR Bit Fields */ +#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu +#define SDHC_DSADDR_DSADDR_SHIFT 2 +#define SDHC_DSADDR_DSADDR(x) (((uint32)(((uint32)(x))<SOPT1) +#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) +#define SIM_SOPT2_REG(base) ((base)->SOPT2) +#define SIM_SOPT4_REG(base) ((base)->SOPT4) +#define SIM_SOPT5_REG(base) ((base)->SOPT5) +#define SIM_SOPT7_REG(base) ((base)->SOPT7) +#define SIM_SDID_REG(base) ((base)->SDID) +#define SIM_SCGC1_REG(base) ((base)->SCGC1) +#define SIM_SCGC2_REG(base) ((base)->SCGC2) +#define SIM_SCGC3_REG(base) ((base)->SCGC3) +#define SIM_SCGC4_REG(base) ((base)->SCGC4) +#define SIM_SCGC5_REG(base) ((base)->SCGC5) +#define SIM_SCGC6_REG(base) ((base)->SCGC6) +#define SIM_SCGC7_REG(base) ((base)->SCGC7) +#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) +#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) +#define SIM_FCFG1_REG(base) ((base)->FCFG1) +#define SIM_FCFG2_REG(base) ((base)->FCFG2) +#define SIM_UIDH_REG(base) ((base)->UIDH) +#define SIM_UIDMH_REG(base) ((base)->UIDMH) +#define SIM_UIDML_REG(base) ((base)->UIDML) +#define SIM_UIDL_REG(base) ((base)->UIDL) + +/** + * @} + */ /* end of group SIM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* SOPT1 Bit Fields */ +#define SIM_SOPT1_RAMSIZE_MASK 0xF000u +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE(x) (((uint32)(((uint32)(x))<PMPROT) +#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) +#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) +#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) + +/** + * @} + */ /* end of group SMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/* PMPROT Bit Fields */ +#define SMC_PMPROT_AVLLS_MASK 0x2u +#define SMC_PMPROT_AVLLS_SHIFT 1 +#define SMC_PMPROT_ALLS_MASK 0x8u +#define SMC_PMPROT_ALLS_SHIFT 3 +#define SMC_PMPROT_AVLP_MASK 0x20u +#define SMC_PMPROT_AVLP_SHIFT 5 +/* PMCTRL Bit Fields */ +#define SMC_PMCTRL_STOPM_MASK 0x7u +#define SMC_PMCTRL_STOPM_SHIFT 0 +#define SMC_PMCTRL_STOPM(x) (((uint8)(((uint8)(x))<MCR) +#define SPI_TCR_REG(base) ((base)->TCR) +#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) +#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) +#define SPI_SR_REG(base) ((base)->SR) +#define SPI_RSER_REG(base) ((base)->RSER) +#define SPI_PUSHR_REG(base) ((base)->PUSHR) +#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) +#define SPI_POPR_REG(base) ((base)->POPR) +#define SPI_TXFR0_REG(base) ((base)->TXFR0) +#define SPI_TXFR1_REG(base) ((base)->TXFR1) +#define SPI_TXFR2_REG(base) ((base)->TXFR2) +#define SPI_TXFR3_REG(base) ((base)->TXFR3) +#define SPI_RXFR0_REG(base) ((base)->RXFR0) +#define SPI_RXFR1_REG(base) ((base)->RXFR1) +#define SPI_RXFR2_REG(base) ((base)->RXFR2) +#define SPI_RXFR3_REG(base) ((base)->RXFR3) + +/** + * @} + */ /* end of group SPI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define SPI_MCR_HALT_MASK 0x1u +#define SPI_MCR_HALT_SHIFT 0 +#define SPI_MCR_SMPL_PT_MASK 0x300u +#define SPI_MCR_SMPL_PT_SHIFT 8 +#define SPI_MCR_SMPL_PT(x) (((uint32)(((uint32)(x))<CSR) +#define SysTick_RVR_REG(base) ((base)->RVR) +#define SysTick_CVR_REG(base) ((base)->CVR) +#define SysTick_CALIB_REG(base) ((base)->CALIB) + +/** + * @} + */ /* end of group SysTick_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SysTick Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SysTick_Register_Masks SysTick Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define SysTick_CSR_ENABLE_MASK 0x1u +#define SysTick_CSR_ENABLE_SHIFT 0 +#define SysTick_CSR_TICKINT_MASK 0x2u +#define SysTick_CSR_TICKINT_SHIFT 1 +#define SysTick_CSR_CLKSOURCE_MASK 0x4u +#define SysTick_CSR_CLKSOURCE_SHIFT 2 +#define SysTick_CSR_COUNTFLAG_MASK 0x10000u +#define SysTick_CSR_COUNTFLAG_SHIFT 16 +/* RVR Bit Fields */ +#define SysTick_RVR_RELOAD_MASK 0xFFFFFFu +#define SysTick_RVR_RELOAD_SHIFT 0 +#define SysTick_RVR_RELOAD(x) (((uint32)(((uint32)(x))<SSPSR) +#define TPIU_CSPSR_REG(base) ((base)->CSPSR) +#define TPIU_ACPR_REG(base) ((base)->ACPR) +#define TPIU_SPPR_REG(base) ((base)->SPPR) +#define TPIU_FFSR_REG(base) ((base)->FFSR) +#define TPIU_FFCR_REG(base) ((base)->FFCR) +#define TPIU_FSCR_REG(base) ((base)->FSCR) +#define TPIU_TRIGGER_REG(base) ((base)->TRIGGER) +#define TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0) +#define TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1) +#define TPIU_ITCTRL_REG(base) ((base)->ITCTRL) +#define TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define TPIU_DEVID_REG(base) ((base)->DEVID) +#define TPIU_PID4_REG(base) ((base)->PID4) +#define TPIU_PID5_REG(base) ((base)->PID5) +#define TPIU_PID6_REG(base) ((base)->PID6) +#define TPIU_PID7_REG(base) ((base)->PID7) +#define TPIU_PID0_REG(base) ((base)->PID0) +#define TPIU_PID1_REG(base) ((base)->PID1) +#define TPIU_PID2_REG(base) ((base)->PID2) +#define TPIU_PID3_REG(base) ((base)->PID3) +#define TPIU_CID0_REG(base) ((base)->CID0) +#define TPIU_CID1_REG(base) ((base)->CID1) +#define TPIU_CID2_REG(base) ((base)->CID2) +#define TPIU_CID4_REG(base) ((base)->CID4) + +/** + * @} + */ /* end of group TPIU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TPIU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TPIU_Register_Masks TPIU Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group TPIU_Register_Masks */ + + +/* TPIU - Peripheral instance base addresses */ +/** Peripheral TPIU base pointer */ +#define TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u) + +/* ---------------------------------------------------------------------------- + -- TPIU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros + * @{ + */ + + +/* TPIU - Register instance definitions */ +/* TPIU */ +#define TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR) +#define TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR) +#define TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR) +#define TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR) +#define TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR) +#define TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR) +#define TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR) +#define TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR) +#define TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR) +#define TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR) +#define TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR) +#define TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR) +#define TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR) +#define TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR) +#define TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR) +#define TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR) +#define TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR) +#define TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR) +#define TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR) +#define TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR) +#define TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR) +#define TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR) +#define TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR) +#define TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR) +#define TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR) +#define TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR) +#define TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR) +#define TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR) + +/** + * @} + */ /* end of group TPIU_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group TPIU_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- TSI + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Peripheral TSI + * @{ + */ + +/** TSI - Peripheral register structure */ +typedef struct TSI_MemMap { + uint32 GENCS; /**< General Control and Status Register, offset: 0x0 */ + uint32 SCANC; /**< SCAN Control Register, offset: 0x4 */ + uint32 PEN; /**< Pin Enable Register, offset: 0x8 */ + uint32 WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ + uint8 RESERVED_0[240]; + uint32 CNTR1; /**< Counter Register, offset: 0x100 */ + uint32 CNTR3; /**< Counter Register, offset: 0x104 */ + uint32 CNTR5; /**< Counter Register, offset: 0x108 */ + uint32 CNTR7; /**< Counter Register, offset: 0x10C */ + uint32 CNTR9; /**< Counter Register, offset: 0x110 */ + uint32 CNTR11; /**< Counter Register, offset: 0x114 */ + uint32 CNTR13; /**< Counter Register, offset: 0x118 */ + uint32 CNTR15; /**< Counter Register, offset: 0x11C */ + uint32 THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ +} volatile *TSI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- TSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros + * @{ + */ + + +/* TSI - Register accessors */ +#define TSI_GENCS_REG(base) ((base)->GENCS) +#define TSI_SCANC_REG(base) ((base)->SCANC) +#define TSI_PEN_REG(base) ((base)->PEN) +#define TSI_WUCNTR_REG(base) ((base)->WUCNTR) +#define TSI_CNTR1_REG(base) ((base)->CNTR1) +#define TSI_CNTR3_REG(base) ((base)->CNTR3) +#define TSI_CNTR5_REG(base) ((base)->CNTR5) +#define TSI_CNTR7_REG(base) ((base)->CNTR7) +#define TSI_CNTR9_REG(base) ((base)->CNTR9) +#define TSI_CNTR11_REG(base) ((base)->CNTR11) +#define TSI_CNTR13_REG(base) ((base)->CNTR13) +#define TSI_CNTR15_REG(base) ((base)->CNTR15) +#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) + +/** + * @} + */ /* end of group TSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TSI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Masks TSI Register Masks + * @{ + */ + +/* GENCS Bit Fields */ +#define TSI_GENCS_STPE_MASK 0x1u +#define TSI_GENCS_STPE_SHIFT 0 +#define TSI_GENCS_STM_MASK 0x2u +#define TSI_GENCS_STM_SHIFT 1 +#define TSI_GENCS_ESOR_MASK 0x10u +#define TSI_GENCS_ESOR_SHIFT 4 +#define TSI_GENCS_ERIE_MASK 0x20u +#define TSI_GENCS_ERIE_SHIFT 5 +#define TSI_GENCS_TSIIE_MASK 0x40u +#define TSI_GENCS_TSIIE_SHIFT 6 +#define TSI_GENCS_TSIEN_MASK 0x80u +#define TSI_GENCS_TSIEN_SHIFT 7 +#define TSI_GENCS_SWTS_MASK 0x100u +#define TSI_GENCS_SWTS_SHIFT 8 +#define TSI_GENCS_SCNIP_MASK 0x200u +#define TSI_GENCS_SCNIP_SHIFT 9 +#define TSI_GENCS_OVRF_MASK 0x1000u +#define TSI_GENCS_OVRF_SHIFT 12 +#define TSI_GENCS_EXTERF_MASK 0x2000u +#define TSI_GENCS_EXTERF_SHIFT 13 +#define TSI_GENCS_OUTRGF_MASK 0x4000u +#define TSI_GENCS_OUTRGF_SHIFT 14 +#define TSI_GENCS_EOSF_MASK 0x8000u +#define TSI_GENCS_EOSF_SHIFT 15 +#define TSI_GENCS_PS_MASK 0x70000u +#define TSI_GENCS_PS_SHIFT 16 +#define TSI_GENCS_PS(x) (((uint32)(((uint32)(x))<BDH) +#define UART_BDL_REG(base) ((base)->BDL) +#define UART_C1_REG(base) ((base)->C1) +#define UART_C2_REG(base) ((base)->C2) +#define UART_S1_REG(base) ((base)->S1) +#define UART_S2_REG(base) ((base)->S2) +#define UART_C3_REG(base) ((base)->C3) +#define UART_D_REG(base) ((base)->D) +#define UART_MA1_REG(base) ((base)->MA1) +#define UART_MA2_REG(base) ((base)->MA2) +#define UART_C4_REG(base) ((base)->C4) +#define UART_C5_REG(base) ((base)->C5) +#define UART_ED_REG(base) ((base)->ED) +#define UART_MODEM_REG(base) ((base)->MODEM) +#define UART_IR_REG(base) ((base)->IR) +#define UART_PFIFO_REG(base) ((base)->PFIFO) +#define UART_CFIFO_REG(base) ((base)->CFIFO) +#define UART_SFIFO_REG(base) ((base)->SFIFO) +#define UART_TWFIFO_REG(base) ((base)->TWFIFO) +#define UART_TCFIFO_REG(base) ((base)->TCFIFO) +#define UART_RWFIFO_REG(base) ((base)->RWFIFO) +#define UART_RCFIFO_REG(base) ((base)->RCFIFO) +#define UART_C7816_REG(base) ((base)->C7816) +#define UART_IE7816_REG(base) ((base)->IE7816) +#define UART_IS7816_REG(base) ((base)->IS7816) +#define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0) +#define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1) +#define UART_WN7816_REG(base) ((base)->WN7816) +#define UART_WF7816_REG(base) ((base)->WF7816) +#define UART_ET7816_REG(base) ((base)->ET7816) +#define UART_TL7816_REG(base) ((base)->TL7816) + +/** + * @} + */ /* end of group UART_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* BDH Bit Fields */ +#define UART_BDH_SBR_MASK 0x1Fu +#define UART_BDH_SBR_SHIFT 0 +#define UART_BDH_SBR(x) (((uint8)(((uint8)(x))<PERID) +#define USB_IDCOMP_REG(base) ((base)->IDCOMP) +#define USB_REV_REG(base) ((base)->REV) +#define USB_ADDINFO_REG(base) ((base)->ADDINFO) +#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) +#define USB_OTGICR_REG(base) ((base)->OTGICR) +#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) +#define USB_OTGCTL_REG(base) ((base)->OTGCTL) +#define USB_ISTAT_REG(base) ((base)->ISTAT) +#define USB_INTEN_REG(base) ((base)->INTEN) +#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) +#define USB_ERREN_REG(base) ((base)->ERREN) +#define USB_STAT_REG(base) ((base)->STAT) +#define USB_CTL_REG(base) ((base)->CTL) +#define USB_ADDR_REG(base) ((base)->ADDR) +#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) +#define USB_FRMNUML_REG(base) ((base)->FRMNUML) +#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) +#define USB_TOKEN_REG(base) ((base)->TOKEN) +#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) +#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) +#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) +#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) +#define USB_USBCTRL_REG(base) ((base)->USBCTRL) +#define USB_OBSERVE_REG(base) ((base)->OBSERVE) +#define USB_CONTROL_REG(base) ((base)->CONTROL) +#define USB_USBTRC0_REG(base) ((base)->USBTRC0) +#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) + +/** + * @} + */ /* end of group USB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* PERID Bit Fields */ +#define USB_PERID_ID_MASK 0x3Fu +#define USB_PERID_ID_SHIFT 0 +#define USB_PERID_ID(x) (((uint8)(((uint8)(x))<CONTROL) +#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) +#define USBDCD_STATUS_REG(base) ((base)->STATUS) +#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) +#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) +#define USBDCD_TIMER2_REG(base) ((base)->TIMER2) + +/** + * @} + */ /* end of group USBDCD_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/* CONTROL Bit Fields */ +#define USBDCD_CONTROL_IACK_MASK 0x1u +#define USBDCD_CONTROL_IACK_SHIFT 0 +#define USBDCD_CONTROL_IF_MASK 0x100u +#define USBDCD_CONTROL_IF_SHIFT 8 +#define USBDCD_CONTROL_IE_MASK 0x10000u +#define USBDCD_CONTROL_IE_SHIFT 16 +#define USBDCD_CONTROL_START_MASK 0x1000000u +#define USBDCD_CONTROL_START_SHIFT 24 +#define USBDCD_CONTROL_SR_MASK 0x2000000u +#define USBDCD_CONTROL_SR_SHIFT 25 +/* CLOCK Bit Fields */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 +#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32)(((uint32)(x))<TRM) +#define VREF_SC_REG(base) ((base)->SC) + +/** + * @} + */ /* end of group VREF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/* TRM Bit Fields */ +#define VREF_TRM_TRIM_MASK 0x3Fu +#define VREF_TRM_TRIM_SHIFT 0 +#define VREF_TRM_TRIM(x) (((uint8)(((uint8)(x))<STCTRLH) +#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) +#define WDOG_TOVALH_REG(base) ((base)->TOVALH) +#define WDOG_TOVALL_REG(base) ((base)->TOVALL) +#define WDOG_WINH_REG(base) ((base)->WINH) +#define WDOG_WINL_REG(base) ((base)->WINL) +#define WDOG_REFRESH_REG(base) ((base)->REFRESH) +#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) +#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) +#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) +#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) +#define WDOG_PRESC_REG(base) ((base)->PRESC) + +/** + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* STCTRLH Bit Fields */ +#define WDOG_STCTRLH_WDOGEN_MASK 0x1u +#define WDOG_STCTRLH_WDOGEN_SHIFT 0 +#define WDOG_STCTRLH_CLKSRC_MASK 0x2u +#define WDOG_STCTRLH_CLKSRC_SHIFT 1 +#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u +#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 +#define WDOG_STCTRLH_WINEN_MASK 0x8u +#define WDOG_STCTRLH_WINEN_SHIFT 3 +#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 +#define WDOG_STCTRLH_DBGEN_MASK 0x20u +#define WDOG_STCTRLH_DBGEN_SHIFT 5 +#define WDOG_STCTRLH_STOPEN_MASK 0x40u +#define WDOG_STCTRLH_STOPEN_SHIFT 6 +#define WDOG_STCTRLH_WAITEN_MASK 0x80u +#define WDOG_STCTRLH_WAITEN_SHIFT 7 +#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u +#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 +#define WDOG_STCTRLH_TESTSEL_MASK 0x800u +#define WDOG_STCTRLH_TESTSEL_SHIFT 11 +#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u +#define WDOG_STCTRLH_BYTESEL_SHIFT 12 +#define WDOG_STCTRLH_BYTESEL(x) (((uint16)(((uint16)(x))< m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld new file mode 100644 index 0000000..d6a2f70 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DN512.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00000410, LENGTH = 512K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 128K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.ramcode) /* .ramcode section for code to be executed in SRAM */ + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld new file mode 100644 index 0000000..389690d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DX256-TMCM.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00008000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00008400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00008410, LENGTH = 512K-32K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld new file mode 100644 index 0000000..0e16652 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DN512.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00000410, LENGTH = 512K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.ramcode) /* .ramcode section for code to be executed in SRAM */ + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h new file mode 100644 index 0000000..5977c17 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h @@ -0,0 +1,3727 @@ +/* + PDD layer implementation for peripheral type ADC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(ADC_PDD_H_) +#define ADC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error ADC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK10D5) /* ADC0 */ && \ + !defined(MCU_MK10D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK10F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK10DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK11D5) /* ADC0 */ && \ + !defined(MCU_MK11D5WS) /* ADC0 */ && \ + !defined(MCU_MK12D5) /* ADC0 */ && \ + !defined(MCU_MK20D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK20D5) /* ADC0 */ && \ + !defined(MCU_MK20D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK20F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK20DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK21D5) /* ADC0 */ && \ + !defined(MCU_MK21D5WS) /* ADC0 */ && \ + !defined(MCU_MK21F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK21F12WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22D5) /* ADC0 */ && \ + !defined(MCU_MK22F12810) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F25612) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F51212) /* ADC0, ADC1 */ && \ + !defined(MCU_MK24F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40X256VMD100) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK52D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK52DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK53D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK53DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK60F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK60DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60N512VMD100) /* ADC0, ADC1 */ && \ + !defined(MCU_MK61F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F12WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F15WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK63F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK63F12WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK64F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK65F18) /* ADC0, ADC1 */ && \ + !defined(MCU_MK65F18WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK66F18) /* ADC0, ADC1 */ && \ + !defined(MCU_MK70F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F12WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F15WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MKE02Z2) /* ADC */ && \ + !defined(MCU_MKE02Z4) /* ADC */ && \ + !defined(MCU_SKEAZN642) /* ADC */ && \ + !defined(MCU_MKE04Z1284) /* ADC */ && \ + !defined(MCU_MKE04Z4) /* ADC */ && \ + !defined(MCU_SKEAZN84) /* ADC */ && \ + !defined(MCU_MKE06Z4) /* ADC */ && \ + !defined(MCU_MKL02Z4) /* ADC0 */ && \ + !defined(MCU_MKL03Z4) /* ADC0 */ && \ + !defined(MCU_MKL04Z4) /* ADC0 */ && \ + !defined(MCU_MKL05Z4) /* ADC0 */ && \ + !defined(MCU_MKL14Z4) /* ADC0 */ && \ + !defined(MCU_MKL15Z4) /* ADC0 */ && \ + !defined(MCU_MKL16Z4) /* ADC0 */ && \ + !defined(MCU_MKL24Z4) /* ADC0 */ && \ + !defined(MCU_MKL25Z4) /* ADC0 */ && \ + !defined(MCU_MKL26Z4) /* ADC0 */ && \ + !defined(MCU_MKL34Z4) /* ADC0 */ && \ + !defined(MCU_MKL36Z4) /* ADC0 */ && \ + !defined(MCU_MKL46Z4) /* ADC0 */ && \ + !defined(MCU_MKV10Z7) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F12810) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F25612) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F51212) /* ADC0, ADC1 */ && \ + !defined(MCU_MKW01Z4) /* ADC0 */ && \ + !defined(MCU_MKW21D5) /* ADC0 */ && \ + !defined(MCU_MKW21D5WS) /* ADC0 */ && \ + !defined(MCU_MKW22D5) /* ADC0 */ && \ + !defined(MCU_MKW22D5WS) /* ADC0 */ && \ + !defined(MCU_MKW24D5) /* ADC0 */ && \ + !defined(MCU_MKW24D5WS) /* ADC0 */ && \ + !defined(MCU_PCK20L4) /* ADC0 */ && \ + !defined(MCU_SKEAZ1284) /* ADC */ + // Unsupported MCU is active + #error ADC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL24Z4))) +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x1AU /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x1BU /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x16U /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x17U /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_DIFFERENTIAL_DADP0_DADM0 0x20U /**< Differential mode, positive and negative channel 0 */ + #define ADC_PDD_DIFFERENTIAL_DADP1_DADM1 0x21U /**< Differential mode, positive and negative channel 1 */ + #define ADC_PDD_DIFFERENTIAL_DADP2_DADM2 0x22U /**< Differential mode, positive and negative channel 2 */ + #define ADC_PDD_DIFFERENTIAL_DADP3_DADM3 0x23U /**< Differential mode, positive and negative channel 3 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_DIFFERENTIAL_BANDGAP 0x3BU /**< Differential mode, positive and negative bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_DIFFERENTIAL_VREFSH 0x3DU /**< Differential mode, positive and negative VREFS. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x1AU /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x1BU /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for trigger type selection */ +#define ADC_PDD_SW_TRIGGER 0U /**< SW trigger */ +#define ADC_PDD_HW_TRIGGER 0x40U /**< HW trigger */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for compare function selection */ + #define ADC_PDD_COMPARE_DISABLED 0U /**< Compare function disabled */ + #define ADC_PDD_LESS_THAN 0x20U /**< Compare function enabled to 'less than' */ + #define ADC_PDD_GREATER_THAN_OR_EQUAL 0x30U /**< Compare function enabled to 'greater than or equal' */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for compare function selection */ + #define ADC_PDD_COMPARE_DISABLED 0U /**< Compare function disabled */ + #define ADC_PDD_LESS_THAN 0x20U /**< Compare function enabled to 'less than' */ + #define ADC_PDD_GREATER_THAN_OR_EQUAL 0x30U /**< Compare function enabled to 'greater than or equal' */ + #define ADC_PDD_RANGE_NOT_INCLUSIVE 0x28U /**< Compare function enabled to 'range, not inclusive' */ + #define ADC_PDD_RANGE_INCLUSIVE 0x38U /**< Compare function enabled to 'range, inclusive' */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock input constants */ +#define ADC_PDD_BUS_CLOCK 0U /**< Bus clock as clock input */ +#define ADC_PDD_BUS_CLOCK_DIV_2 0x1U /**< Bus clock divided 2 as clock input */ +#define ADC_PDD_ALTERNATE_CLOCK 0x2U /**< Alternate clock as clock input */ +#define ADC_PDD_ASYNCHRONOUS_CLOCK 0x3U /**< Asynchronous clock as clock input */ + +/* Resolution mode constants */ +#define ADC_PDD_RESOLUTION_8_BITS 0U /**< 8-bit conversion in single-ended mode, 9-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_12_BITS 0x4U /**< 12-bit conversion in single-ended mode, 13-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_10_BITS 0x8U /**< 10-bit conversion in single-ended mode, 11-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_16_BITS 0xCU /**< 16-bit conversion in single-ended mode, 16-bit conversion in differential mode */ + +/* Clock division constants */ +#define ADC_PDD_DIVIDE_1 0U /**< The divide ration is 1 */ +#define ADC_PDD_DIVIDE_2 0x20U /**< The divide ration is 2 */ +#define ADC_PDD_DIVIDE_4 0x40U /**< The divide ration is 4 */ +#define ADC_PDD_DIVIDE_8 0x60U /**< The divide ration is 8 */ + +/* Long sample time constants */ +#define ADC_PDD_LONG_SAMPLE_TIME_20_CLOCKS 0U /**< 20 extra ADC clock cycles; 24 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_12_CLOCKS 0x1U /**< 12 extra ADC clock cycles; 16 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_6_CLOCKS 0x2U /**< 6 extra ADC clock cycles; 10 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_2_CLOCKS 0x3U /**< 2 extra ADC clock cycles; 6 ADC clock cycles total */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for conversion speed selection */ + #define ADC_PDD_SHORT 0U /**< Short sample time - less precise conversion. */ + #define ADC_PDD_LONG 0x1U /**< Long sample time - more precise conversion. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Total sample time constants */ + #define ADC_PDD_SAMPLE_TIME_24_CLOCKS 0U /**< 24 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_16_CLOCKS 0x1U /**< 16 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_10_CLOCKS 0x2U /**< 10 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_6_CLOCKS 0x3U /**< 6 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_4_CLOCKS 0x4U /**< 4 ADC clock cycles total */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Channel set constants */ +#define ADC_PDD_CHANNEL_SET_A 0U /**< ADxxa channel set */ +#define ADC_PDD_CHANNEL_SET_B 0x10U /**< ADxxb channel set */ + +/* Voltage reference constants */ +#define ADC_PDD_VOLTAGE_REFERENCE_DEFAULT 0U /**< Default voltage reference Vrefh and Vrefl */ +#define ADC_PDD_VOLTAGE_REFERENCE_ALTERNATE 0x1U /**< Alternate voltage reference */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for one conversion or continuous selection */ + #define ADC_PDD_ONE_CONVERSION 0U /**< One conversion mode */ + #define ADC_PDD_CONTINUOUS_CONVERSIONS 0x20U /**< Continuous conversion mode */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for one conversion or continuous selection */ + #define ADC_PDD_ONE_CONVERSION 0U /**< One conversion mode */ + #define ADC_PDD_CONTINUOUS_CONVERSIONS 0x8U /**< Continuous conversion mode */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for average type selection */ +#define ADC_PDD_AVERAGE_DISABLED 0U /**< Average function disabled */ +#define ADC_PDD_4_SAMPLES_AVERAGED 0x4U /**< Average function with 4 samples */ +#define ADC_PDD_8_SAMPLES_AVERAGED 0x5U /**< Average function with 8 samples */ +#define ADC_PDD_16_SAMPLES_AVERAGED 0x6U /**< Average function with 16 samples */ +#define ADC_PDD_32_SAMPLES_AVERAGED 0x7U /**< Average function with 32 samples */ + +/* Constants for voltage reference selection */ +#define ADC_PDD_VREF 0U /**< VREFH and VREFL signals are used as voltage reference. */ +#define ADC_PDD_VANALOG 0x1U /**< VDDA and VSSA (analog supply) signals are used as voltage reference. */ + +/* Constants for power mode selection */ +#define ADC_PDD_NORMAL 0U /**< Normal power mode - faster ADC clock. */ +#define ADC_PDD_LOW 0x80U /**< Low power mode - slower ADC clock. */ + +/* Constants for divider */ +#define ADC_PDD_DIV_1 0U /**< Input clock divided by 1. */ +#define ADC_PDD_DIV_2 0x20U /**< Input clock divided by 2. */ +#define ADC_PDD_DIV_4 0x40U /**< Input clock divided by 4. */ +#define ADC_PDD_DIV_8 0x60U /**< Input clock divided by 8. */ + +/* Constants for resolution settings */ +#define ADC_PDD_RES_8 0U /**< 8-bit conversion. */ +#define ADC_PDD_RES_10 0x4U /**< 10-bit conversion. */ +#define ADC_PDD_RES_12 0x8U /**< 12-bit conversion. */ + +/* Constants for clock source settings */ +#define ADC_PDD_PERIPH_CLK 0U /**< Peripheral clock (BUS_CLOCK) selected as clock source. */ +#define ADC_PDD_PERIPH_CLK_DIV_2 0x1U /**< Half of peripheral clock (BUS_CLOCK) selected as clock source. */ +#define ADC_PDD_ALT_CLK 0x2U /**< Alternate clock selected as clock source. */ +#define ADC_PDD_ASYNC_CLK 0x3U /**< Asynchro clock selected as clock source. */ + +/* Constants for FIFO scan mode settings */ +#define ADC_PDD_NORMAL 0U /**< Selects normal mode of the FIFO. */ +#define ADC_PDD_SCAN 0x40U /**< Selects scan mode of the FIFO. */ + +/* Constants for FIFO compare mode settings */ +#define ADC_PDD_OR 0U /**< Selects logic or between the compare trigger inside the FIFO. */ +#define ADC_PDD_AND 0x20U /**< Selects logic and between the compare trigger inside the FIFO. */ + +/* Constants for FIFO state */ +#define ADC_PDD_EMPTY 0x8U /**< FIFO is empty. */ +#define ADC_PDD_NOT_EMPTY 0U /**< FIFO contains some data - measurement in progress. */ +#define ADC_PDD_FULL 0x4U /**< FIFO is full, next measurements will rewrite previous results. */ + +/* Constants for HW trigger masking mode */ +#define ADC_PDD_HAND 0U /**< Selects hand mode: Hardware trigger masking depended on HTRGMASKE bit, see the EnableFIFO_HW_TriggerMasking macro. */ +#define ADC_PDD_AUTOMATIC 0x1U /**< Selects automatic mode: Hardware trigger masked automatically when data FIFO is not empty. */ + + +/* ---------------------------------------------------------------------------- + -- SetChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @param Value Parameter specifying new channel. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_SetChannel(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC1_ADCH_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new channel. Use constants from group + * "Channel constants for channel selection". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetChannel(_BASE_PTR, periphID, + * ADC_PDD_SINGLE_ENDED_DAD0); + * @endcode + */ + #define ADC_PDD_SetChannel(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)0x3FU))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableConversionCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_EnableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) |= \ + ADC_SC1_AIEN_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_EnableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) |= \ + ADC_SC1_AIEN_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableConversionCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_DisableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_DisableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC1_AIEN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_DisableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_DisableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)ADC_SC1_AIEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetConversionCompleteFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns conversion complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionCompleteFlag(_BASE_PTR, periphID); + * @endcode + */ + #define ADC_PDD_GetConversionCompleteFlag(PeripheralBase, Index) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & ADC_SC1_COCO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns conversion complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionCompleteFlag(_BASE_PTR, periphID); + * @endcode + */ + #define ADC_PDD_GetConversionCompleteFlag(PeripheralBase, Index) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase,(Index)) & ADC_SC1_COCO_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl1Reg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_WriteStatusControl1Reg(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl1Reg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_WriteStatusControl1Reg(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the content of the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl1Reg(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_ReadStatusControl1Reg(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl1Reg(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_ReadStatusControl1Reg(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectInputClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects input clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Input Clock input. This parameter is of "Clock input constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectInputClock(_BASE_PTR, ADC_PDD_BUS_CLOCK); + * @endcode + */ +#define ADC_PDD_SelectInputClock(PeripheralBase, Input) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADICLK_MASK))) | ( \ + (uint32)(Input))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC resolution mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Resolution mode. This parameter is of "Resolution mode constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectResolution(_BASE_PTR, + * ADC_PDD_RESOLUTION_8_BITS); + * @endcode + */ +#define ADC_PDD_SelectResolution(PeripheralBase, Mode) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_MODE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLongSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables long sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if long sample time will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableLongSampleTime(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableLongSampleTime(PeripheralBase, State) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADLSMP_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG1_ADLSMP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClockDivision + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC clock division. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divide Clock division. This parameter is of "Clock division constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectClockDivision(_BASE_PTR, ADC_PDD_DIVIDE_1); + * @endcode + */ +#define ADC_PDD_SelectClockDivision(PeripheralBase, Divide) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADIV_MASK))) | ( \ + (uint32)(Divide))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables low power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if low power mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableLowPowerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableLowPowerMode(PeripheralBase, State) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADLPC_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG1_ADLPC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfiguration1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_WriteConfiguration1Reg(PeripheralBase, Value) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_WriteConfiguration1Reg(PeripheralBase, Value) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadConfiguration1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the content of the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration1Reg(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_ReadConfiguration1Reg(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration1Reg(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_ReadConfiguration1Reg(PeripheralBase) ( \ + ADC_CFG1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectLongSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects sample time effective if long sample time is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time Long sample time. This parameter is of "Long sample time + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectLongSampleTime(_BASE_PTR, + * ADC_PDD_LONG_SAMPLE_TIME_20_CLOCKS); + * @endcode + */ +#define ADC_PDD_SelectLongSampleTime(PeripheralBase, Time) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)(Time))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects sample time effective if long sample time is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time Long sample time. This parameter is of "Total sample time + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC0_CFG2, + * ADC1_CFG1, ADC1_CFG2, ADC2_CFG1, ADC2_CFG2, ADC3_CFG1, ADC3_CFG2 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectSampleTime(_BASE_PTR, + * ADC_PDD_SAMPLE_TIME_24_CLOCKS); + * @endcode + */ +#define ADC_PDD_SelectSampleTime(PeripheralBase, Time) ( \ + ( \ + ((Time) == ADC_PDD_SAMPLE_TIME_24_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_16_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_10_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_6_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : ( \ + ADC_CFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG1_ADLSMP_MASK)) \ + )))), \ + ( \ + ((Time) == ADC_PDD_SAMPLE_TIME_24_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK)) : (((Time) == ADC_PDD_SAMPLE_TIME_16_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)0x1U))) : (((Time) == ADC_PDD_SAMPLE_TIME_10_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)0x2U))) : (((Time) == ADC_PDD_SAMPLE_TIME_6_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) |= \ + ADC_CFG2_ADLSTS_MASK) : ( \ + ADC_CFG2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK)) \ + )))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHighSpeedMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables high speed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if high speed mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableHighSpeedMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableHighSpeedMode(PeripheralBase, State) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADHSC_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG2_ADHSC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsynchronousClockOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables asynchronous clock output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if asynchronous clock output will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableAsynchronousClockOutput(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableAsynchronousClockOutput(PeripheralBase, State) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADACKEN_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG2_ADACKEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelSet + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects between alternate sets of ADC channels. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Set ADC channel set. This parameter is of "Channel set constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectChannelSet(_BASE_PTR, ADC_PDD_CHANNEL_SET_A); + * @endcode + */ +#define ADC_PDD_SelectChannelSet(PeripheralBase, Set) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_MUXSEL_MASK))) | ( \ + (uint32)(Set))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteConfiguration2Reg(PeripheralBase, Value) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadConfiguration2Reg(PeripheralBase) ( \ + ADC_CFG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetConversionActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns conversion active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionActiveFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetConversionActiveFlag(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_ADACT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCompareValue1Raw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 1. This parameter is a + * 12-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue1Raw(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_SetCompareValue1Raw(PeripheralBase, Value) ( \ + ADC_CV_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 1. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue1Raw(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_SetCompareValue1Raw(PeripheralBase, Value) ( \ + ADC_CV1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCompareValue1Raw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue1Raw(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetCompareValue1Raw(PeripheralBase) ( \ + ADC_CV_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue1Raw(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetCompareValue1Raw(PeripheralBase) ( \ + ADC_CV1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCompareValue2Raw + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets compare value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 2. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV2, ADC1_CV2, + * ADC2_CV2, ADC3_CV2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue2Raw(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetCompareValue2Raw(PeripheralBase, Value) ( \ + ADC_CV2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCompareValue2Raw + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns compare value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV2, ADC1_CV2, + * ADC2_CV2, ADC3_CV2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue2Raw(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCompareValue2Raw(PeripheralBase) ( \ + ADC_CV2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetConversionTriggerType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets conversion trigger type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Trigger mode. This parameter is of "Constants for trigger type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetConversionTriggerType(_BASE_PTR, + * ADC_PDD_SW_TRIGGER); + * @endcode + */ +#define ADC_PDD_SetConversionTriggerType(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_ADTRG_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetConversionTriggerType + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns conversion trigger type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for trigger type selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionTriggerType(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetConversionTriggerType(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_ADTRG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCompareFunction + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets compare type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Compare mode. This parameter is of "Constants for compare + * function selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareFunction(_BASE_PTR, + * ADC_PDD_COMPARE_DISABLED); + * @endcode + */ + #define ADC_PDD_SetCompareFunction(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)((uint32)0x3U << 4U)))) | ( \ + (uint32)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets compare type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Compare mode. This parameter is of "Constants for compare + * function selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareFunction(_BASE_PTR, + * ADC_PDD_COMPARE_DISABLED); + * @endcode + */ + #define ADC_PDD_SetCompareFunction(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)((uint32)0x7U << 3U)))) | ( \ + (uint32)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_DMAEN_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_SC2_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the voltage reference source used for conversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Voltage reference. This parameter is of "Voltage reference + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectVoltageReference(_BASE_PTR, + * ADC_PDD_VOLTAGE_REFERENCE_DEFAULT); + * @endcode + */ +#define ADC_PDD_SelectVoltageReference(PeripheralBase, Reference) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_REFSEL_MASK))) | ( \ + (uint32)(Reference))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteStatusControl2Reg(PeripheralBase, Value) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadStatusControl2Reg(PeripheralBase) ( \ + ADC_SC2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartCalibration + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts calibration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_StartCalibration(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_StartCalibration(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) |= \ + ADC_SC3_CAL_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCalibrationActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns calibration active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetCalibrationActiveFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCalibrationActiveFlag(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_CAL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCalibrationFailedStatusFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns calibration failed status flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetCalibrationFailedStatusFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCalibrationFailedStatusFlag(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_CALF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetContinuousMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode One conversion or continuous mode. This parameter is of + * "Constants for one conversion or continuous selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetContinuousMode(_BASE_PTR, + * ADC_PDD_ONE_CONVERSION); + * @endcode + */ + #define ADC_PDD_SetContinuousMode(PeripheralBase, Mode) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC1_ADCO_MASK))) | ( \ + (uint32)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode One conversion or continuous mode. This parameter is of + * "Constants for one conversion or continuous selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetContinuousMode(_BASE_PTR, + * ADC_PDD_ONE_CONVERSION); + * @endcode + */ + #define ADC_PDD_SetContinuousMode(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADCO_MASK))) | ( \ + (uint32)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetContinuousMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for one conversion or continuous + * selection" type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetContinuousMode(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetContinuousMode(PeripheralBase) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & ADC_SC1_ADCO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for one conversion or continuous + * selection" type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetContinuousMode(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetContinuousMode(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADCO_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetAverageFunction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets average function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Average mode. This parameter is of "Constants for average type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetAverageFunction(_BASE_PTR, + * ADC_PDD_AVERAGE_DISABLED); + * @endcode + */ +#define ADC_PDD_SetAverageFunction(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)0x7U))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteStatusControl3Reg(PeripheralBase, Value) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadStatusControl3Reg(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResultValueRaw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns raw data from result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index], ADC_R + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResultValueRaw(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_GetResultValueRaw(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns raw data from result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index], ADC_R + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResultValueRaw(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_GetResultValueRaw(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadDataResultReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index]. + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadDataResultReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define ADC_PDD_ReadDataResultReg(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOffsetCorrectionValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets offset error correction value in 2's complement and left + * justified format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new offset correction value. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetOffsetCorrectionValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetOffsetCorrectionValue(PeripheralBase, Value) ( \ + ADC_OFS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOffsetCorrectionValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns offset error correction value in 2's complement and left + * justified format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetOffsetCorrectionValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetOffsetCorrectionValue(PeripheralBase) ( \ + ADC_OFS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOffsetCorrectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Offset correction register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteOffsetCorrectionReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteOffsetCorrectionReg(PeripheralBase, Value) ( \ + ADC_OFS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOffsetCorrectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Offset correction register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadOffsetCorrectionReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadOffsetCorrectionReg(PeripheralBase) ( \ + ADC_OFS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPlusGainValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets plus-side gain value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetPlusGainValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetPlusGainValue(PeripheralBase, Value) ( \ + ADC_PG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideGainReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideGainReg(PeripheralBase, Value) ( \ + ADC_PG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadPlusSideGainReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideGainReg(PeripheralBase) ( \ + ADC_PG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinusGainValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets minus-side gain value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetMinusGainValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetMinusGainValue(PeripheralBase, Value) ( \ + ADC_MG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideGainReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideGainReg(PeripheralBase, Value) ( \ + ADC_MG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadMinusSideGainReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideGainReg(PeripheralBase) ( \ + ADC_MG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus0CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus0CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus0CalibrationValue(PeripheralBase) ( \ + ADC_CLP0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration0Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration0Reg(PeripheralBase, Value) ( \ + ADC_CLP0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration0Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration0Reg(PeripheralBase) ( \ + ADC_CLP0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus1CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus1CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus1CalibrationValue(PeripheralBase) ( \ + ADC_CLP1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration1Reg(PeripheralBase, Value) ( \ + ADC_CLP1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration1Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration1Reg(PeripheralBase) ( \ + ADC_CLP1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus2CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus2CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus2CalibrationValue(PeripheralBase) ( \ + ADC_CLP2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration2Reg(PeripheralBase, Value) ( \ + ADC_CLP2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration2Reg(PeripheralBase) ( \ + ADC_CLP2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus3CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus3CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus3CalibrationValue(PeripheralBase) ( \ + ADC_CLP3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration3Reg(PeripheralBase, Value) ( \ + ADC_CLP3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration3Reg(PeripheralBase) ( \ + ADC_CLP3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus4CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus4CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus4CalibrationValue(PeripheralBase) ( \ + ADC_CLP4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration4Reg(PeripheralBase, Value) ( \ + ADC_CLP4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration4Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration4Reg(PeripheralBase) ( \ + ADC_CLP4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlusSCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value S. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlusSCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlusSCalibrationValue(PeripheralBase) ( \ + ADC_CLPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibrationSReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibrationSReg(PeripheralBase, Value) ( \ + ADC_CLPS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibrationSReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibrationSReg(PeripheralBase) ( \ + ADC_CLPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlusDCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value D. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlusDCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlusDCalibrationValue(PeripheralBase) ( \ + ADC_CLPD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibrationDReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibrationDReg(PeripheralBase, Value) ( \ + ADC_CLPD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibrationDReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibrationDReg(PeripheralBase) ( \ + ADC_CLPD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus0CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus0CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus0CalibrationValue(PeripheralBase) ( \ + ADC_CLM0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration0Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration0Reg(PeripheralBase, Value) ( \ + ADC_CLM0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration0Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration0Reg(PeripheralBase) ( \ + ADC_CLM0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus1CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus1CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus1CalibrationValue(PeripheralBase) ( \ + ADC_CLM1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration1Reg(PeripheralBase, Value) ( \ + ADC_CLM1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration1Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration1Reg(PeripheralBase) ( \ + ADC_CLM1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus2CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus2CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus2CalibrationValue(PeripheralBase) ( \ + ADC_CLM2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration2Reg(PeripheralBase, Value) ( \ + ADC_CLM2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration2Reg(PeripheralBase) ( \ + ADC_CLM2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus3CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus3CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus3CalibrationValue(PeripheralBase) ( \ + ADC_CLM3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration3Reg(PeripheralBase, Value) ( \ + ADC_CLM3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration3Reg(PeripheralBase) ( \ + ADC_CLM3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus4CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus4CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus4CalibrationValue(PeripheralBase) ( \ + ADC_CLM4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration4Reg(PeripheralBase, Value) ( \ + ADC_CLM4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration4Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration4Reg(PeripheralBase) ( \ + ADC_CLM4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinusSCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value S. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinusSCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinusSCalibrationValue(PeripheralBase) ( \ + ADC_CLMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibrationSReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibrationSReg(PeripheralBase, Value) ( \ + ADC_CLMS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibrationSReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibrationSReg(PeripheralBase) ( \ + ADC_CLMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinusDCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value D. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinusDCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinusDCalibrationValue(PeripheralBase) ( \ + ADC_CLMD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibrationDReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibrationDReg(PeripheralBase, Value) ( \ + ADC_CLMD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibrationDReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibrationDReg(PeripheralBase) ( \ + ADC_CLMD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the voltage reference source used for conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param RefSel Reference selection. This parameter is of "Constants for + * voltage reference selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * ADC_PDD_SetVoltageReference(_BASE_PTR, ADC_PDD_VREF); + * @endcode + */ +#define ADC_PDD_SetVoltageReference(PeripheralBase, RefSel) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_REFSEL_MASK))) | ( \ + (uint32)(RefSel))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the voltage reference source used for conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for voltage reference selection" type. + * The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetVoltageReference(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetVoltageReference(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_REFSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SampleTime Selects short/long sample time. This parameter is of + * "Constants for conversion speed selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetSampleTime(_BASE_PTR, ADC_PDD_SHORT); + * @endcode + */ +#define ADC_PDD_SetSampleTime(PeripheralBase, SampleTime) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADLSMP_MASK))) | ( \ + (uint32)((uint32)(SampleTime) << ADC_SC3_ADLSMP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns short/long sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for conversion speed selection" type. + * The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetSampleTime(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetSampleTime(PeripheralBase) ( \ + ((uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADLPC_MASK) == 0U) ? ( \ + ADC_PDD_SHORT) : ( \ + ADC_PDD_LONG) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Conversion speed. This parameter is of "Constants for power mode + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetPowerMode(_BASE_PTR, ADC_PDD_NORMAL); + * @endcode + */ +#define ADC_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADLPC_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for power mode selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetPowerMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPowerMode(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADLPC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param DivVal Divider value. This parameter is of "Constants for divider" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetDivider(_BASE_PTR, ADC_PDD_DIV_1); + * @endcode + */ +#define ADC_PDD_SetDivider(PeripheralBase, DivVal) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADIV_MASK))) | ( \ + (uint32)(DivVal))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for divider" type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetDivider(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetDivider(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADIV_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets resolution of the conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Resolution Resolution value. This parameter is of "Constants for + * resolution settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetResolution(_BASE_PTR, ADC_PDD_RES_8); + * @endcode + */ +#define ADC_PDD_SetResolution(PeripheralBase, Resolution) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_MODE_MASK))) | ( \ + (uint32)(Resolution))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns resolution of the conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for resolution settings" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResolution(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetResolution(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_MODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Resolution value. This parameter is of "Constants for clock + * source settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetClockSource(_BASE_PTR, ADC_PDD_PERIPH_CLK); + * @endcode + */ +#define ADC_PDD_SetClockSource(PeripheralBase, Source) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADICLK_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for clock source settings" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetClockSource(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetClockSource(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADICLK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_ScanMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets normal or scan mode for FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Normal or scan mode for FIFO. This parameter is of "Constants for + * FIFO scan mode settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_ScanMode(_BASE_PTR, ADC_PDD_NORMAL); + * @endcode + */ +#define ADC_PDD_SetFIFO_ScanMode(PeripheralBase, Mode) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_ASCANE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_ScanMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns normal or scan mode for FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO scan mode settings" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_ScanMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_ScanMode(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_ASCANE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_CompareMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets logic mode of the compared result inside FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Mode of comparing result inside FIFO. This parameter is of + * "Constants for FIFO compare mode settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_CompareMode(_BASE_PTR, ADC_PDD_OR); + * @endcode + */ +#define ADC_PDD_SetFIFO_CompareMode(PeripheralBase, Mode) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_ACFSEL_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_CompareMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns logic mode of the compared result inside FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO compare mode settings" type. + * The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_CompareMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_CompareMode(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_ACFSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_Depth + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects between FIFO disabled and FIFO level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Depth Parameter specifying the requested FIFO depth. Value should be + * in range from 1 to 8. Value equal to one means that FIFO is disabled and + * just one channel can be measured. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_Depth(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetFIFO_Depth(PeripheralBase, Depth) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_AFDEP_MASK))) | ( \ + (uint32)(uint8)(Depth) - 1U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_Depth + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns depth of the FIFO. Value equal to one means that FIFO is + * disabled and just one channel can be measured. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetFIFO_Depth(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_Depth(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_AFDEP_MASK) + 1U \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_State + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO state" type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_State(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_State(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)((uint32)0x3U << 2U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFIFO_HW_TriggerMultipleConversions + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable/disable HW trigger multiple conversions in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_EnableFIFO_HW_TriggerMultipleConversions(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableFIFO_HW_TriggerMultipleConversions(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + ADC_SC4_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC4_HTRGME_MASK)) : ( \ + ADC_SC4_REG(PeripheralBase) |= \ + ADC_SC4_HTRGME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFIFO_HW_TriggerMasking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable/disable HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * ADC_PDD_EnableFIFO_HW_TriggerMasking(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableFIFO_HW_TriggerMasking(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + ADC_SC5_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC5_HTRGMASKE_MASK)) : ( \ + ADC_SC5_REG(PeripheralBase) |= \ + ADC_SC5_HTRGMASKE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_HW_TriggerMaskingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mode of the HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Mode of comparing result inside FIFO. This parameter is of + * "Constants for HW trigger masking mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * ADC_PDD_SetFIFO_HW_TriggerMaskingMode(_BASE_PTR, + * ADC_PDD_HAND); + * @endcode + */ +#define ADC_PDD_SetFIFO_HW_TriggerMaskingMode(PeripheralBase, Mode) ( \ + ADC_SC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC5_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC5_HTRGMASKSEL_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_HW_TriggerMaskingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mode of the HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for HW trigger masking mode" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * uint8 result = + * ADC_PDD_GetFIFO_HW_TriggerMaskingMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_HW_TriggerMaskingMode(PeripheralBase) ( \ + (uint32)(ADC_SC5_REG(PeripheralBase) & ADC_SC5_HTRGMASKSEL_MASK) \ + ) +#endif /* #if defined(ADC_PDD_H_) */ + +/* ADC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h new file mode 100644 index 0000000..aae4e10 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h @@ -0,0 +1,2898 @@ +/* + PDD layer implementation for peripheral type CAN + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CAN_PDD_H_) +#define CAN_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CAN PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK10D7) /* CAN0 */ && \ + !defined(MCU_MK10F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK10DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20D7) /* CAN0 */ && \ + !defined(MCU_MK20F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK21F12) /* CAN0 */ && \ + !defined(MCU_MK21F12WS) /* CAN0 */ && \ + !defined(MCU_MK22F12) /* CAN0 */ && \ + !defined(MCU_MK24F12) /* CAN0 */ && \ + !defined(MCU_MK30D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK30D7) /* CAN0 */ && \ + !defined(MCU_MK30DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40D7) /* CAN0 */ && \ + !defined(MCU_MK40DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40X256VMD100) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60N512VMD100) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F12WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F15WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK63F12) /* CAN0 */ && \ + !defined(MCU_MK63F12WS) /* CAN0 */ && \ + !defined(MCU_MK64F12) /* CAN0 */ && \ + !defined(MCU_MK65F18) /* CAN0, CAN1 */ && \ + !defined(MCU_MK65F18WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK66F18) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F12WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F15WS) /* CAN0, CAN1 */ + // Unsupported MCU is active + #error CAN PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Warning interrupt mask (for EnableWarningInterruptsMask, + DisableWarningInterruptsMask macros). */ +#define CAN_PDD_TX_WARNING_INT_MASK CAN_CTRL1_TWRNMSK_MASK /**< Tx warning interrupt mask. */ +#define CAN_PDD_RX_WARNING_INT_MASK CAN_CTRL1_RWRNMSK_MASK /**< Rx warning interrupt mask. */ + +/* Status flags constants (for GetStatusInterruptFlags1, + ClearStatusInterruptFlags1 macros). */ +#define CAN_PDD_SYNCHRONIZED_TO_CAN_BUS CAN_ESR1_SYNCH_MASK /**< CAN synchronization status flag */ +#define CAN_PDD_TX_WARNING_INT CAN_ESR1_TWRNINT_MASK /**< Tx warning interrupt Flag */ +#define CAN_PDD_RX_WARNING_INT CAN_ESR1_RWRNINT_MASK /**< Rx warning interrupt Flag */ +#define CAN_PDD_BIT1_ERROR CAN_ESR1_BIT1ERR_MASK /**< Bit1 error flag */ +#define CAN_PDD_BIT0_ERROR CAN_ESR1_BIT0ERR_MASK /**< Bit0 error flag */ +#define CAN_PDD_ACKNOWLEDGE_ERROR CAN_ESR1_ACKERR_MASK /**< Acknowledge error flag */ +#define CAN_PDD_CRC_ERROR CAN_ESR1_CRCERR_MASK /**< Cyclic redundancy check error flag */ +#define CAN_PDD_FORM_ERROR CAN_ESR1_FRMERR_MASK /**< Form error detected */ +#define CAN_PDD_SUFFTING_ERROR CAN_ESR1_STFERR_MASK /**< Stuffing error flag */ +#define CAN_PDD_TX_ERROR_WARNING CAN_ESR1_TXWRN_MASK /**< Tx error warning - repetitive errors are occurring during message transmission */ +#define CAN_PDD_RX_ERROR_WARNING CAN_ESR1_RXWRN_MASK /**< Rx error warning - repetitive errors are occurring during message reception */ +#define CAN_PDD_CAN_BUS_IDLE CAN_ESR1_IDLE_MASK /**< CAN bus IDLE state. */ +#define CAN_PDD_TRANSMITTING_MESSAGE CAN_ESR1_TX_MASK /**< FlexCAN in transmission */ +#define CAN_PDD_RECEIVING_MESSAGE CAN_ESR1_RX_MASK /**< FlexCAN in reception */ +#define CAN_PDD_BUS_OFF_INT CAN_ESR1_BOFFINT_MASK /**< FlexCAN enters Bus Off state */ +#define CAN_PDD_ERROR_INT CAN_ESR1_ERRINT_MASK /**< Error interrupt */ +#define CAN_PDD_WAKEUP_INT CAN_ESR1_WAKINT_MASK /**< Wake-Up interrupt */ + +/* CAN device state mode constants (for GetReadyStatus macro). */ +#define CAN_PDD_IS_READY 0x8000000U /**< CAN module is either in Disable Mode, Doze Mode, Stop Mode or Freeze Mode. */ +#define CAN_PDD_NOT_READY 0U /**< CAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. */ + +/* CAN device soft reset state constants (for GetSoftReset macro). */ +#define CAN_PDD_IS_RESET 0U /**< No reset request */ +#define CAN_PDD_NOT_RESET 0x2000000U /**< Resets the registers affected by soft reset. */ + +/* CAN device freeze state constants (for GetFreezeAck macro). */ +#define CAN_PDD_IS_FREEZE 0x1000000U /**< CAN in Freeze Mode, prescaler stopped */ +#define CAN_PDD_NOT_FREEZE 0U /**< CAN not in Freeze Mode, prescaler running */ + +/* CAN device low power mode constants (for GetLowPowerAcknowledge macro). */ +#define CAN_PDD_IS_LOW_POWER_MODE 0x100000U /**< CAN is either in Disable Mode, Doze Mode or Stop mode */ +#define CAN_PDD_NOT_LOW_POWER_MODE 0U /**< CAN is not in any of the low power modes */ + +/* Rx FIFO Acceptance ID Mode constants (for SetRxFIFOAcceptanceIDMode macro). */ +#define CAN_PDD_FORMAT_A 0U /**< One full ID (standard and extended) per ID Filter Table element */ +#define CAN_PDD_FORMAT_B 0x1U /**< Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Tableelement */ +#define CAN_PDD_FORMAT_C 0x2U /**< Four partial 8-bit Standard IDs per ID Filter Table element */ +#define CAN_PDD_FORMAT_D 0x3U /**< All frames rejected */ + +/* CAN Engine Clock Source constants (for SetClockSource macro). */ +#define CAN_PDD_XTAL_CLOCK 0U /**< The CAN engine clock source is the oscillator clock */ +#define CAN_PDD_BUS_CLOCK 0x2000U /**< The CAN engine clock source is the peripheral clock */ + +/* Rx sampling mode constants (for SetBitSampling macro). */ +#define CAN_PDD_ONE_SAMPLE 0U /**< Just one sample is used to determine the bit value */ +#define CAN_PDD_THREE_SAMPLES 0x80U /**< Three samples are used to determine the value of the received bit */ + +/* Message buffer interrupt and flag mask constant constants (for + EnableMessageBufferInterruptMask1, DisableMessageBufferInterruptMask1 macros). */ +#define CAN_PDD_MESSAGE_BUFFER_0 0x1U /**< Buffer MB0 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_1 0x2U /**< Buffer MB1 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_2 0x4U /**< Buffer MB2 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_3 0x8U /**< Buffer MB3 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_4 0x10U /**< Buffer MB4 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_5 0x20U /**< Buffer MB5 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_6 0x40U /**< Buffer MB6 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_7 0x80U /**< Buffer MB7 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_8 0x100U /**< Buffer MB8 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_9 0x200U /**< Buffer MB9 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_10 0x400U /**< Buffer MB10 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_11 0x800U /**< Buffer MB11 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_12 0x1000U /**< Buffer MB12 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_13 0x2000U /**< Buffer MB13 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_14 0x4000U /**< Buffer MB14 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_15 0x8000U /**< Buffer MB15 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_16 0x10000U /**< Buffer MB16 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_17 0x20000U /**< Buffer MB17 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_18 0x40000U /**< Buffer MB18 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_19 0x80000U /**< Buffer MB19 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_20 0x100000U /**< Buffer MB20 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_21 0x200000U /**< Buffer MB21 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_22 0x400000U /**< Buffer MB22 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_23 0x800000U /**< Buffer MB23 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_24 0x1000000U /**< Buffer MB24 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_25 0x2000000U /**< Buffer MB25 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_26 0x4000000U /**< Buffer MB26 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_27 0x8000000U /**< Buffer MB27 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_28 0x10000000U /**< Buffer MB28 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_29 0x20000000U /**< Buffer MB29 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_30 0x40000000U /**< Buffer MB30 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_31 0x80000000U /**< Buffer MB31 interrupt mask */ + +/* Number Rx FIFO filter constants (for SetNumberRxFIFOFilter macro). */ +#define CAN_PDD_RX_FIFO_FILTERS_8 0U /**< 8 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_16 0x1U /**< 16 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_24 0x2U /**< 24 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_32 0x3U /**< 32 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_40 0x4U /**< 40 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_48 0x5U /**< 48 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_56 0x6U /**< 56 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_64 0x7U /**< 64 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_72 0x8U /**< 72 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_80 0x9U /**< 80 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_88 0xAU /**< 88 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_96 0xBU /**< 96 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_104 0xCU /**< 104 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_112 0xDU /**< 112 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_120 0xEU /**< 120 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_128 0xFU /**< 128 Rx FIFO Filters */ + +/* Mailboxes reception priority constants (for SetReceptionPriority macro). */ +#define CAN_PDD_START_FIFO_THEN_MAILBOXES 0U /**< Matching starts from Rx FIFO and continues on Mailboxes */ +#define CAN_PDD_START_MAILBOXES_THEN_FIFO 0x40000U /**< Matching starts from Mailboxes and continues on Rx FIFO */ + +/* Remote request priority constants (for SetRemoteRequestPriority macro). */ +#define CAN_PDD_GENERATE_REMOTE_RESPONSE_FRAME 0U /**< Remote Response Frame is generated */ +#define CAN_PDD_STORE_REMOTE_REQUEST_FRANE 0x20000U /**< Remote Request Frame is stored */ + +/* Rx message buffer codes constants (for SetMessageBufferCode, + GetMessageBufferCode macros) */ +#define CAN_PDD_MB_RX_NOT_ACTIVE 0U /**< MB is not active */ +#define CAN_PDD_MB_RX_FULL 0x2U /**< MB is full */ +#define CAN_PDD_MB_RX_EMPTY 0x4U /**< MB is active and empty */ +#define CAN_PDD_MB_RX_OVERRUN 0x6U /**< MB is being overwritten into a full buffer */ +#define CAN_PDD_MB_RX_BUSY 0x1U /**< FlexCAN is updating the contents of the MB */ +#define CAN_PDD_MB_RX_RANSWER 0xAU /**< A frame was configured to recognize a Remote Request Frame and transmit a ResponseFrame in return */ + +/* Tx message buffer codes constants (for SetMessageBufferCode, + GetMessageBufferCode macros) */ +#define CAN_PDD_MB_TX_NOT_ACTIVE 0x8U /**< MB is not active */ +#define CAN_PDD_MB_TX_ABORT 0x9U /**< MB is aborted */ +#define CAN_PDD_MB_TX_DATA_FRAME 0xCU /**< MB is a Tx Data Frame */ +#define CAN_PDD_MB_TX_REMOTE_FRAME 0xCU /**< MB is a Tx Remote Request Frame */ +#define CAN_PDD_MB_TX_RESPONSE_FRAME 0xAU /**< MB is a Tx Response Frame from an incoming Remote Request Frame */ + +/* Type of message buffer ID constants (for SetMessageBufferID, + GetMessageBufferID macros). */ +#define CAN_PDD_BUFFER_ID_EXT 0U /**< Extended frame format */ +#define CAN_PDD_BUFFER_ID_STD 0x1U /**< Standard frame format */ + +/* Message buffer interrupt and flag mask constant constants (for + EnableMessageBufferInterruptMask2, DisableMessageBufferInterruptMask2 macros). */ +#define CAN_PDD_MESSAGE_BUFFER_32 0x1U /**< Buffer MB32 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_33 0x2U /**< Buffer MB33 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_34 0x4U /**< Buffer MB34 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_35 0x8U /**< Buffer MB35 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_36 0x10U /**< Buffer MB36 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_37 0x20U /**< Buffer MB37 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_38 0x40U /**< Buffer MB38 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_39 0x80U /**< Buffer MB39 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_40 0x100U /**< Buffer MB40 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_41 0x200U /**< Buffer MB41 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_42 0x400U /**< Buffer MB42 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_43 0x800U /**< Buffer MB43 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_44 0x1000U /**< Buffer MB44 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_45 0x2000U /**< Buffer MB45 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_46 0x4000U /**< Buffer MB46 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_47 0x8000U /**< Buffer MB47 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_48 0x10000U /**< Buffer MB48 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_49 0x20000U /**< Buffer MB49 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_50 0x40000U /**< Buffer MB50 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_51 0x80000U /**< Buffer MB51 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_52 0x100000U /**< Buffer MB52 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_53 0x200000U /**< Buffer MB53 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_54 0x400000U /**< Buffer MB54 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_55 0x800000U /**< Buffer MB55 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_56 0x1000000U /**< Buffer MB56 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_57 0x2000000U /**< Buffer MB57 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_58 0x4000000U /**< Buffer MB58 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_59 0x8000000U /**< Buffer MB59 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_60 0x10000000U /**< Buffer MB60 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_61 0x20000000U /**< Buffer MB61 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_62 0x40000000U /**< Buffer MB62 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_63 0x80000000U /**< Buffer MB63 interrupt mask */ + + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_MDIS_MASK) : ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_MDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnterFreezeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enter CAN device to freeze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnterFreezeMode(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnterFreezeMode(PeripheralBase) ( \ + (CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_FRZ_MASK), \ + (CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_HALT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ExitFreezeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Return CAN device from freeze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ExitFreezeMode(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_ExitFreezeMode(PeripheralBase) ( \ + (CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_HALT_MASK)), \ + (CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_FRZ_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receive FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Rx FIFO will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableRxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableRxFIFO(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_RFEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_RFEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadyStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ready state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device state mode constants (for + * GetReadyStatus macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetReadyStatus(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetReadyStatus(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_NOTRDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the WakeUp interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWakeUpInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableWakeUpInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_WAKMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWakeUpInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the WakeUp interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWakeUpInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableWakeUpInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_WAKMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSoftReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enters to the soft reset mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetSoftReset(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_SetSoftReset(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_SOFTRST_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSoftResetState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the soft reset operation state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device soft reset state constants (for + * GetSoftReset macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetSoftResetState(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetSoftResetState(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_SOFTRST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFreezeAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the acknowledge of freeze operation state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device freeze state constants (for + * GetFreezeAck macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetFreezeAck(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetFreezeAck(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_FRZACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSupervizorMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables supervisor mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if supervisor mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSupervizorMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSupervizorMode(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_SUPV_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_SUPV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSelfWakeUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables self wake up feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if self wake up will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSelfWakeUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSelfWakeUp(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_SLFWAK_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_SLFWAK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWarningInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the warning interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWarningInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableWarningInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_WRNEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWarningInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the warning interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWarningInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableWarningInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_WRNEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLowPowerAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the low power state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device low power mode constants (for + * GetLowPowerAcknowledge macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetLowPowerAcknowledge(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetLowPowerAcknowledge(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_LPMACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSelfReception + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables self reception. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if self reception will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSelfReception(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSelfReception(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_SRXDIS_MASK) : ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_SRXDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInvidualRxMasking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables invidual Rx masking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if invidual Rx masking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableInvidualRxMasking(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableInvidualRxMasking(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_IRMQ_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_IRMQ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLocalPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables local priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if local priority will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLocalPriority(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLocalPriority(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_LPRIOEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_LPRIOEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAbort + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables abort a pending transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if abort a pending transmission will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableAbort(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableAbort(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_AEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_AEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFIFOAcceptanceIDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Rx FIFO acceptance ID mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Rx FIFO acceptance ID mode value[0..3]. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRxFIFOAcceptanceIDMode(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetRxFIFOAcceptanceIDMode(PeripheralBase, Mode) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_IDAM_MASK))) | ( \ + (uint32)((uint32)(Mode) << CAN_MCR_IDAM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNumberOfLastMessageBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the number of the last Message Buffer that will take part in the + * matching and arbitration processes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Number of the last Message Buffer value[0..127]. This parameter + * is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetNumberOfLastMessageBuffer(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetNumberOfLastMessageBuffer(PeripheralBase, Value) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_MAXMB_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescalerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the prescaler division factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Prescaler division factor value[0..255]. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPrescalerValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPrescalerValue(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PRESDIV_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PRESDIV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetResyncJumpWidthValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the resync jump width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Resync jump width value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetResyncJumpWidthValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetResyncJumpWidthValue(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_RJW_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_RJW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseSegment1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of phase segment 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Phase segment 1 value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPhaseSegment1Value(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPhaseSegment1Value(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PSEG1_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PSEG1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseSegment2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of phase segment 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Phase segment 2 value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPhaseSegment2Value(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPhaseSegment2Value(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PSEG2_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PSEG2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusOffInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Bus Off interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableBusOffInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableBusOffInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_BOFFMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusOffInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Bus Off interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableBusOffInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableBusOffInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_BOFFMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableErrorInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_ERRMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableErrorInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_ERRMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CAN Engine Clock Source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Parameter specifying clock source of CAN Engine. This + * parameter is of "CAN Engine Clock Source constants (for SetClockSource + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetClockSource(_BASE_PTR, CAN_PDD_XTAL_CLOCK); + * @endcode + */ +#define CAN_PDD_SetClockSource(PeripheralBase, ClkSource) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_CLKSRC_MASK))) | ( \ + (uint32)(ClkSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLoopBack + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Loop Back mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Loop Back will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLoopBack(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLoopBack(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LPB_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LPB_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWarningInterruptsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Warning Interrupts Mask defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Warning + * interrupt mask (for EnableWarningInterruptsMask, + * DisableWarningInterruptsMask macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWarningInterruptsMask(_BASE_PTR, + * CAN_PDD_TX_WARNING_INT_MASK); + * @endcode + */ +#define CAN_PDD_EnableWarningInterruptsMask(PeripheralBase, Mask) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWarningInterruptsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Warning Interrupts Mask defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Warning + * interrupt mask (for EnableWarningInterruptsMask, + * DisableWarningInterruptsMask macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWarningInterruptsMask(_BASE_PTR, + * CAN_PDD_TX_WARNING_INT_MASK); + * @endcode + */ +#define CAN_PDD_DisableWarningInterruptsMask(PeripheralBase, Mask) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBitSampling + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CAN bit sampling at the Rx input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Sampling Parameter specifying bit sampling at the Rx input. This + * parameter is of "Rx sampling mode constants (for SetBitSampling macro)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetBitSampling(_BASE_PTR, CAN_PDD_ONE_SAMPLE); + * @endcode + */ +#define CAN_PDD_SetBitSampling(PeripheralBase, Sampling) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_SMP_MASK))) | ( \ + (uint32)(Sampling))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusOffRecovery + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Bus Off Recovery. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Bus Off Recovery will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableBusOffRecovery(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableBusOffRecovery(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_BOFFREC_MASK) : ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_BOFFREC_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimerSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Timer Synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Timer Synchronization will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableTimerSynchronization(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableTimerSynchronization(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_TSYN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_TSYN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowestBufferTransmitFirst + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Lowest Buffer Transmit First. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Lowest Buffer Transmit First will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLowestBufferTransmitFirst(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLowestBufferTransmitFirst(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LBUF_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableListenOnlyMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Listen Only Mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Listen Only Mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableListenOnlyMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableListenOnlyMode(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LOM_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPropagationSegment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Propagation Segment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Propagation Segment value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPropagationSegment(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPropagationSegment(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PROPSEG_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value of the Timer, value[0..65535]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_TIMER, CAN1_TIMER + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTimerValue(PeripheralBase, Value) ( \ + CAN_TIMER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_TIMER_REG(PeripheralBase) & (uint32)(~(uint32)CAN_TIMER_TIMER_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CAN0_TIMER, CAN1_TIMER + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CAN_PDD_GetTimerValue(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetTimerValue(PeripheralBase) ( \ + (uint16)(CAN_TIMER_REG(PeripheralBase) & CAN_TIMER_TIMER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Global Acceptance Mask for mailboxes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Global Acceptance Mask value[0..0x1FFFFFFF]. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RXMGMASK, + * CAN1_RXMGMASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetGlobalAcceptanceMask(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetGlobalAcceptanceMask(PeripheralBase, AccMask) ( \ + CAN_RXMGMASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetGlobalAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Global Acceptance Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RXMGMASK, + * CAN1_RXMGMASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetGlobalAcceptanceMask(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetGlobalAcceptanceMask(PeripheralBase) ( \ + CAN_RXMGMASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAcceptanceMask14 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Acceptance Mask for message buffer 14. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Acceptance Mask for message bugger 14 value[0..0x1FFFFFFF]. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RX14MASK, + * CAN1_RX14MASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetAcceptanceMask14(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetAcceptanceMask14(PeripheralBase, AccMask) ( \ + CAN_RX14MASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAcceptanceMask14 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Acceptance Mask for message buffer 14. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RX14MASK, + * CAN1_RX14MASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetAcceptanceMask14(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetAcceptanceMask14(PeripheralBase) ( \ + CAN_RX14MASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAcceptanceMask15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Acceptance Mask for message buffer 15. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Acceptance Mask for message bugger 15 value[0..0x1FFFFFFF]. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RX15MASK, + * CAN1_RX15MASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetAcceptanceMask15(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetAcceptanceMask15(PeripheralBase, AccMask) ( \ + CAN_RX15MASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAcceptanceMask15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Acceptance Mask for message buffer 15. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RX15MASK, + * CAN1_RX15MASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetAcceptanceMask15(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetAcceptanceMask15(PeripheralBase) ( \ + CAN_RX15MASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the transmit error counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmit error counter value[0..255]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTxErrorCounter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTxErrorCounter(PeripheralBase, Value) ( \ + CAN_ECR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_ECR_TXERRCNT_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the transmit error counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetTxErrorCounter(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetTxErrorCounter(PeripheralBase) ( \ + (uint8)(CAN_ECR_REG(PeripheralBase) & CAN_ECR_TXERRCNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the receive error counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receive error counter value[0..255]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRxErrorCounter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetRxErrorCounter(PeripheralBase, Value) ( \ + CAN_ECR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_ECR_RXERRCNT_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ECR_RXERRCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the receive error counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetRxErrorCounter(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetRxErrorCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & CAN_ECR_RXERRCNT_MASK)) >> ( \ + CAN_ECR_RXERRCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for + * GetStatusInterruptFlags1, ClearStatusInterruptFlags1 macros)." for processing return + * value. + * @remarks The macro accesses the following registers: CAN0_ESR1, CAN1_ESR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetStatusInterruptFlags1(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetStatusInterruptFlags1(PeripheralBase) ( \ + CAN_ESR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStatusInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants (for GetStatusInterruptFlags1, + * ClearStatusInterruptFlags1 macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ESR1, CAN1_ESR1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearStatusInterruptFlags1(_BASE_PTR, + * CAN_PDD_SYNCHRONIZED_TO_CAN_BUS); + * @endcode + */ +#define CAN_PDD_ClearStatusInterruptFlags1(PeripheralBase, Mask) ( \ + CAN_ESR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CAN_ESR1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(( \ + CAN_ESR1_WAKINT_MASK) | (( \ + CAN_ESR1_ERRINT_MASK) | (( \ + CAN_ESR1_BOFFINT_MASK) | (( \ + CAN_ESR1_RWRNINT_MASK) | ( \ + CAN_ESR1_TWRNINT_MASK))))))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferInterruptMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables message buffer[0..31] interrupt requests defined by mask + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK1, CAN1_IMASK1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferInterruptMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferInterruptMask1(PeripheralBase, Mask) ( \ + CAN_IMASK1_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMessageBufferInterruptMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables message buffer interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK1, CAN1_IMASK1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableMessageBufferInterruptMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_DisableMessageBufferInterruptMask1(PeripheralBase, Mask) ( \ + CAN_IMASK1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferInterruptFlag1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Message Buffer Interrupt flag register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_IFLAG1, CAN1_IFLAG1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetMessageBufferInterruptFlag1(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetMessageBufferInterruptFlag1(PeripheralBase) ( \ + CAN_IFLAG1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearMessageBufferInterruptFlagMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear Message Buffer Interrupt Flag defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IFLAG1, CAN1_IFLAG1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearMessageBufferInterruptFlagMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_ClearMessageBufferInterruptFlagMask1(PeripheralBase, Mask) ( \ + CAN_IFLAG1_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWriteAccessToMemory + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Write Access To Memory In Freeze Mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Write Access To Memory In Freeze Mode + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWriteAccessToMemory(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableWriteAccessToMemory(PeripheralBase, State) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_WRMFRZ_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL2_WRMFRZ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNumberRxFIFOFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Number Rx FIFO filter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Number of Rx FIFO filter[0..3]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetNumberRxFIFOFilter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetNumberRxFIFOFilter(PeripheralBase, Value) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_RFFN_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL2_RFFN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxArbitrationStartDelay + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Tx Arbitration Start Delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value[0..31] of Tx Arbitration Start Delay. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTxArbitrationStartDelay(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTxArbitrationStartDelay(PeripheralBase, Value) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_TASD_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL2_TASD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReceptionPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mailboxes reception priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying mailboxes reception priority. This + * parameter is of "Mailboxes reception priority constants (for + * SetReceptionPriority macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetReceptionPriority(_BASE_PTR, + * CAN_PDD_START_FIFO_THEN_MAILBOXES); + * @endcode + */ +#define CAN_PDD_SetReceptionPriority(PeripheralBase, Priority) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_MRP_MASK))) | ( \ + (uint32)(Priority))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRemoteRequestPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets remote request priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying remote request priority. This parameter + * is of "Remote request priority constants (for SetRemoteRequestPriority + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRemoteRequestPriority(_BASE_PTR, + * CAN_PDD_GENERATE_REMOTE_RESPONSE_FRAME); + * @endcode + */ +#define CAN_PDD_SetRemoteRequestPriority(PeripheralBase, Priority) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_RRS_MASK))) | ( \ + (uint32)(Priority))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRTRComparison + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the comparison of both Rx Mailbox filter's IDE and + * RTR bit with their corresponding bitswithin the incoming frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Rx mailbox filter's. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableRTRComparison(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableRTRComparison(PeripheralBase, State) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_EACEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL2_EACEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusRegister2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Error Status Register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_ESR2, CAN1_ESR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetErrorStatusRegister2(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetErrorStatusRegister2(PeripheralBase) ( \ + CAN_ESR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCRCRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CRC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_CRCR, CAN1_CRCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetCRCRegister(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetCRCRegister(PeripheralBase) ( \ + CAN_CRCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalRxFIFOMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets Global Rx FIFO Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Global Rx FIFO mask value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RXFGMASK, + * CAN1_RXFGMASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetGlobalRxFIFOMask(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetGlobalRxFIFOMask(PeripheralBase, Mask) ( \ + CAN_RXFGMASK_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOInfoRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Rx FIFO Information Register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RXFIR, CAN1_RXFIR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetRxFIFOInfoRegister(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetRxFIFOInfoRegister(PeripheralBase) ( \ + CAN_RXFIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInvidualAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets value of invidual acceptance mask defined by Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param AccMask Acceptance mask value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RXIMR[Index]. + * @par Example: + * @code + * CAN_PDD_SetInvidualAcceptanceMask(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetInvidualAcceptanceMask(PeripheralBase, Index, AccMask) ( \ + CAN_RXIMR_REG(PeripheralBase,(Index)) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInvidualAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value Invidual Acceptance Mask Register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RXIMR[Index]. + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetInvidualAcceptanceMask(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetInvidualAcceptanceMask(PeripheralBase, Index) ( \ + CAN_RXIMR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer code. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferCode(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferCode(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_CODE_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CS_CODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer code. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferCode(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferCode(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_CODE_MASK)) >> ( \ + CAN_CS_CODE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferDataLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer data length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..8]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferDataLength(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferDataLength(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_DLC_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CS_DLC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferDataLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = + * CAN_PDD_GetMessageBufferDataLength(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferDataLength(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_DLC_MASK)) >> ( \ + CAN_CS_DLC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferTimeStamp + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer TimeStamp. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..8]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferTimeStamp(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferTimeStamp(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_CS_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)CAN_CS_TIME_STAMP_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferTimeStamp + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer TimeStamp. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint16 result = + * CAN_PDD_GetMessageBufferTimeStamp(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferTimeStamp(PeripheralBase, Index) ( \ + (uint16)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_TIME_STAMP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferRTR + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables RTR of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested state of Remote Transmission Request bit. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferRTR(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferRTR(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_RTR_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_RTR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferRTR + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of RTR bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferRTR(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferRTR(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_RTR_MASK)) >> ( \ + CAN_CS_RTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferSRR + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SRR of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested state of Substitute Remote Request bit. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferSRR(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferSRR(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_SRR_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_SRR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferSRR + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of SRR bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferSRR(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferSRR(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_SRR_MASK)) >> ( \ + CAN_CS_SRR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferIDExt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables extended ID of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested frame format. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferIDExt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferIDExt(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_IDE_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_IDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferIDExt + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of ID extended bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferIDExt(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferIDExt(PeripheralBase, Index) ( \ + ((uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_IDE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferID + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of message buffer ID. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param TypeID Requested ID format. This parameter is of "Type of message + * buffer ID constants (for SetMessageBufferID, GetMessageBufferID macros)." + * type. + * @param Value ID value. This parameter is a 29-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferID(_BASE_PTR, periphID, + * CAN_PDD_BUFFER_ID_EXT, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferID(PeripheralBase, Index, TypeID, Value) ( \ + ((TypeID) == CAN_PDD_BUFFER_ID_STD) ? ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_ID_STD_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ID_STD_SHIFT)))) : ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_ID_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(CAN_ID_STD_MASK | CAN_ID_EXT_MASK))))) | ( \ + (uint32)(Value)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferID + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value ID of message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param TypeID Requested ID format. This parameter is of "Type of message + * buffer ID constants (for SetMessageBufferID, GetMessageBufferID macros)." + * type. + * @return Returns a 29-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferID(_BASE_PTR, + * periphID, CAN_PDD_BUFFER_ID_EXT); + * @endcode + */ +#define CAN_PDD_GetMessageBufferID(PeripheralBase, Index, TypeID) ( \ + ((TypeID) == CAN_PDD_BUFFER_ID_STD) ? ( \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & CAN_ID_STD_MASK)) >> ( \ + CAN_ID_STD_SHIFT))) : ( \ + (uint32)(( \ + CAN_ID_REG(PeripheralBase,(Index))) & ( \ + (uint32)(CAN_ID_STD_MASK | CAN_ID_EXT_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferWORD0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer data WORD0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer data value[0..0xFFFFFFFF]. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD0[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferWORD0(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferWORD0(PeripheralBase, Index, Value) ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferWORD0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data WORD0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: WORD0[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferWORD0(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferWORD0(PeripheralBase, Index) ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferWORD1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer data WORD1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer data value[0..0xFFFFFFFF]. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD1[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferWORD1(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferWORD1(PeripheralBase, Index, Value) ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferWORD1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data WORD1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: WORD1[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferWORD1(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferWORD1(PeripheralBase, Index) ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field in the message buffer denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param ByteIndex Data byte index. This parameter is of index type. + * @param Value Data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD0[Index], + * WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetMessageBufferData(_BASE_PTR, periphID, periphID, + * 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferData(PeripheralBase, Index, ByteIndex, Value) ( \ + ((uint8)((uint8)(ByteIndex) & 0xFCU) == 0U) ? ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_WORD0_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(( \ + (uint32)0xFFU) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U))))))) | ( \ + (uint32)(( \ + (uint32)(Value)) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))))) : ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_WORD1_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(( \ + (uint32)0xFFU) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U))))))) | ( \ + (uint32)(( \ + (uint32)(Value)) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the data field in the message buffer denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param ByteIndex Data byte index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WORD0[Index], + * WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferData(_BASE_PTR, + * periphID, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferData(PeripheralBase, Index, ByteIndex) ( \ + ((uint8)((uint8)(ByteIndex) & 0xFCU) == 0U) ? ( \ + (uint8)(( \ + CAN_WORD0_REG(PeripheralBase,(Index))) >> ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))) : ( \ + (uint8)(( \ + CAN_WORD1_REG(PeripheralBase,(Index))) >> ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferLocalPrio + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Local Priority Field within the message ID buffer + * denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Local priority value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferLocalPrio(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferLocalPrio(PeripheralBase, Index, Value) ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_ID_PRIO_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ID_PRIO_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferLocalPrio + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Local priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * uint8 result = + * CAN_PDD_GetMessageBufferLocalPrio(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferLocalPrio(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & CAN_ID_PRIO_MASK)) >> ( \ + CAN_ID_PRIO_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFOFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the filters for FIFO table, this table is located on unavailable + * MB memory space. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param CS Value of CS register. This parameter is a 32-bit value. + * @param ID Value of ID register. This parameter is a 32-bit value. + * @param WORD0 Value of WORD0 register. This parameter is a 32-bit value. + * @param WORD1 Value of WORD1 register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index], ID[Index], + * WORD0[Index], WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetFIFOFilter(_BASE_PTR, periphID, 1, 1, 1, 1); + * @endcode + */ +#define CAN_PDD_SetFIFOFilter(PeripheralBase, Index, CS, ID, WORD0, WORD1) ( \ + (CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(CS)), \ + ((CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(ID)), \ + ((CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(WORD0)), \ + (CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(WORD1)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferInterruptMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables message buffer[32..63] interrupt requests defined by mask + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK2, CAN1_IMASK2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferInterruptMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferInterruptMask2(PeripheralBase, Mask) ( \ + CAN_IMASK2_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMessageBufferInterruptMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables message buffer interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK2, CAN1_IMASK2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableMessageBufferInterruptMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_DisableMessageBufferInterruptMask2(PeripheralBase, Mask) ( \ + CAN_IMASK2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferInterruptFlag2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Message Buffer Interrupt flag register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_IFLAG2, CAN1_IFLAG2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetMessageBufferInterruptFlag2(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetMessageBufferInterruptFlag2(PeripheralBase) ( \ + CAN_IFLAG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearMessageBufferInterruptFlagMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear Message Buffer Interrupt Flag defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IFLAG2, CAN1_IFLAG2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearMessageBufferInterruptFlagMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_ClearMessageBufferInterruptFlagMask2(PeripheralBase, Mask) ( \ + CAN_IFLAG2_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if doze mode will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableDozeMode(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_DOZE_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_DOZE_SHIFT))) \ + ) +#endif /* #if defined(CAN_PDD_H_) */ + +/* CAN_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h new file mode 100644 index 0000000..f3a871b --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h @@ -0,0 +1,2501 @@ +/* + PDD layer implementation for peripheral type CMP + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CMP_PDD_H_) +#define CMP_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CMP PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK10D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK10D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK10F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK10DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK11D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK11D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MK12D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK20D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK20D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK20D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK20F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK20DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK21D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK21D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MK21F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK21F12WS) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK22D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F12810) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK22F25612) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F51212) /* CMP0, CMP1 */ && \ + !defined(MCU_MK24F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40X256VMD100) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK52D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK52DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK53D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK53DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK60F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK60DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60N512VMD100) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK61F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F12WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F15WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK63F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK63F12WS) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK64F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK65F18) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK65F18WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK66F18) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F12WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F15WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MKE02Z2) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE02Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_SKEAZN642) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE04Z1284) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE04Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_SKEAZN84) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE06Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKL02Z4) /* CMP0 */ && \ + !defined(MCU_MKL03Z4) /* CMP0 */ && \ + !defined(MCU_MKL04Z4) /* CMP0 */ && \ + !defined(MCU_MKL05Z4) /* CMP0 */ && \ + !defined(MCU_MKL14Z4) /* CMP0 */ && \ + !defined(MCU_MKL15Z4) /* CMP0 */ && \ + !defined(MCU_MKL16Z4) /* CMP0 */ && \ + !defined(MCU_MKL24Z4) /* CMP0 */ && \ + !defined(MCU_MKL25Z4) /* CMP0 */ && \ + !defined(MCU_MKL26Z4) /* CMP0 */ && \ + !defined(MCU_MKL34Z4) /* CMP0 */ && \ + !defined(MCU_MKL36Z4) /* CMP0 */ && \ + !defined(MCU_MKL46Z4) /* CMP0 */ && \ + !defined(MCU_MKV10Z7) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F12810) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F25612) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F51212) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW01Z4) /* CMP0 */ && \ + !defined(MCU_MKW21D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW21D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW22D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW22D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW24D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW24D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_PCK20L4) /* CMP0, CMP1 */ && \ + !defined(MCU_SKEAZ1284) /* ACMP0, ACMP1 */ + // Unsupported MCU is active + #error CMP PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Interrupts' mask */ + #define CMP_PDD_EDGE_INTERRUPT ACMP_CS_ACIE_MASK /**< Falling edge interrupt enable mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Interrupts' mask */ + #define CMP_PDD_FALLING_EDGE_INTERRUPT CMP_SCR_IEF_MASK /**< Falling edge interrupt enable mask. */ + #define CMP_PDD_RISING_EDGE_INTERRUPT CMP_SCR_IER_MASK /**< Rising edge interrupt enable mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Interrupts' flags */ + #define CMP_PDD_EDGE_FLAG ACMP_CS_ACF_MASK /**< Edge flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Interrupts' flags */ + #define CMP_PDD_FALLING_EDGE_FLAG CMP_SCR_CFF_MASK /**< Falling edge flag. */ + #define CMP_PDD_RISING_EDGE_FLAG CMP_SCR_CFR_MASK /**< Rising edge flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Comparator modes */ + #define CMP_PDD_FALLING_EDGE_MODE 0U /**< Falling edge detection mode. */ + #define CMP_PDD_RISING_EDGE_MODE 0x1U /**< Rising edge detection mode. */ + #define CMP_PDD_BOTH_EDGES_MODE 0x3U /**< Both falling and rising edge detection mode. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Comparator modes */ + #define CMP_PDD_FALLING_EDGE_MODE CMP_SCR_IEF_MASK /**< Falling edge detection mode. */ + #define CMP_PDD_RISING_EDGE_MODE CMP_SCR_IER_MASK /**< Rising edge detection mode. */ + #define CMP_PDD_BOTH_EDGES_MODE 0x18U /**< Both falling and rising edge detection mode. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* External input mask */ +#define CMP_PDD_EXTERNAL_INPUT_0 0x1U /**< External input 0 */ +#define CMP_PDD_EXTERNAL_INPUT_1 0x2U /**< External input 1 */ +#define CMP_PDD_EXTERNAL_INPUT_2 0x4U /**< External input 2 */ + +/* Deprecated: Hysteresis constants. Please use HYSTERESIS_LEVEL_X constants. */ +#define CMP_PDD_HYSTERESIS_DISABLE 0U /**< Hysteresis not used. */ +#define CMP_PDD_HYSTERESIS_20MV 0x1U /**< 20 mV hysteresis used. */ +#define CMP_PDD_HYSTERESIS_40MV 0x2U /**< 40 mV hysteresis used. */ +#define CMP_PDD_HYSTERESIS_60MV 0x3U /**< 60 mV hysteresis used. */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Hysteresis constants. For exact value representation see peripheral device + documentation. */ + #define CMP_PDD_HYSTERESIS_LEVEL_0 0U /**< Level 0 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_1 0x40U /**< Level 1 hysteresis used. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Hysteresis constants. For exact value representation see peripheral device + documentation. */ + #define CMP_PDD_HYSTERESIS_LEVEL_0 0U /**< Level 0 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_1 0x1U /**< Level 1 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_2 0x2U /**< Level 2 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_3 0x3U /**< Level 3 hysteresis used. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Filter sample count constants. */ +#define CMP_PDD_FILTER_DISABLED 0U /**< Filter disabled. */ +#define CMP_PDD_FILTER_1_SAMPLE 0x10U /**< 1 consecutive sample must agree. */ +#define CMP_PDD_FILTER_2_SAMPLES 0x20U /**< 2 consecutive samples must agree. */ +#define CMP_PDD_FILTER_3_SAMPLES 0x30U /**< 3 consecutive samples must agree. */ +#define CMP_PDD_FILTER_4_SAMPLES 0x40U /**< 4 consecutive samples must agree. */ +#define CMP_PDD_FILTER_5_SAMPLES 0x50U /**< 5 consecutive samples must agree. */ +#define CMP_PDD_FILTER_6_SAMPLES 0x60U /**< 6 consecutive samples must agree. */ +#define CMP_PDD_FILTER_7_SAMPLES 0x70U /**< 7 consecutive samples must agree. */ + +/* Comparator output filtration constant */ +#define CMP_PDD_FILTERED_OUTPUT 0U /**< Filtered comparator output. */ +#define CMP_PDD_UNFILTERED_OUTPUT CMP_CR1_COS_MASK /**< Filter on comparator output is bypassed. */ + +/* Comparator output inversion constant. */ +#define CMP_PDD_NOT_INVERTED_OUTPUT 0U /**< Comparator output is not inverted. */ +#define CMP_PDD_INVERTED_OUTPUT CMP_CR1_INV_MASK /**< Comparator output is inverted. */ + +/* Comparator power mode constant. */ +#define CMP_PDD_LOW_POWER_MODE 0U /**< Low power/low speed mode. */ +#define CMP_PDD_HIGH_SPEED_MODE CMP_CR1_PMODE_MASK /**< High power/high speed mode. */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100))) +/* Comparator's interrupt stop mode constant. */ + #define CMP_PDD_LEVEL_SENSITIVE_MODE 0U /**< Comparator is level sensitive in stop mode */ + #define CMP_PDD_EDGE_SENSITIVE_MODE CMP_SCR_SMELB_MASK /**< Comparator is edge sensitive in stop mode */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Comparator's interrupt stop mode constant. */ + #define CMP_PDD_LEVEL_SENSITIVE_MODE 0U /**< Comparator is level sensitive in stop mode */ + #define CMP_PDD_EDGE_SENSITIVE_MODE 0x1U /**< Comparator is edge sensitive in stop mode */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Analog comparator 6-bit DAC supply voltage reference source constant. For + exact connection see peripheral device documentation. */ + #define CMP_PDD_V_REF_INPUT_1 0U /**< Vin1 reference. */ + #define CMP_PDD_V_REF_INPUT_2 ACMP_C1_DACREF_MASK /**< Vin2 reference */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Analog comparator 6-bit DAC supply voltage reference source constant. */ + #define CMP_PDD_V_REF_INPUT_1 0U /**< Vin1 reference. */ + #define CMP_PDD_V_REF_INPUT_2 CMP_DACCR_VRSEL_MASK /**< Vin2 reference */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Negative input constant. */ + #define CMP_PDD_NEGATIVE_INPUT_0 0U /**< Negative input 0. */ + #define CMP_PDD_NEGATIVE_INPUT_1 0x1U /**< Negative input 1. */ + #define CMP_PDD_NEGATIVE_INPUT_2 0x2U /**< Negative input 2. */ + #define CMP_PDD_NEGATIVE_INPUT_3 0x3U /**< Negative input 3. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Negative input constant. */ + #define CMP_PDD_NEGATIVE_INPUT_0 0U /**< Negative input 0. */ + #define CMP_PDD_NEGATIVE_INPUT_1 0x1U /**< Negative input 1. */ + #define CMP_PDD_NEGATIVE_INPUT_2 0x2U /**< Negative input 2. */ + #define CMP_PDD_NEGATIVE_INPUT_3 0x3U /**< Negative input 3. */ + #define CMP_PDD_NEGATIVE_INPUT_4 0x4U /**< Negative input 4. */ + #define CMP_PDD_NEGATIVE_INPUT_5 0x5U /**< Negative input 5. */ + #define CMP_PDD_NEGATIVE_INPUT_6 0x6U /**< Negative input 6. */ + #define CMP_PDD_NEGATIVE_INPUT_7 0x7U /**< Negative input 7. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Positive input constant. */ + #define CMP_PDD_POSITIVE_INPUT_0 0U /**< Positive input 0. */ + #define CMP_PDD_POSITIVE_INPUT_1 0x10U /**< Positive input 1. */ + #define CMP_PDD_POSITIVE_INPUT_2 0x20U /**< Positive input 2. */ + #define CMP_PDD_POSITIVE_INPUT_3 0x30U /**< Positive input 3. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Positive input constant. */ + #define CMP_PDD_POSITIVE_INPUT_0 0U /**< Positive input 0. */ + #define CMP_PDD_POSITIVE_INPUT_1 0x8U /**< Positive input 1. */ + #define CMP_PDD_POSITIVE_INPUT_2 0x10U /**< Positive input 2. */ + #define CMP_PDD_POSITIVE_INPUT_3 0x18U /**< Positive input 3. */ + #define CMP_PDD_POSITIVE_INPUT_4 0x20U /**< Positive input 4. */ + #define CMP_PDD_POSITIVE_INPUT_5 0x28U /**< Positive input 5. */ + #define CMP_PDD_POSITIVE_INPUT_6 0x30U /**< Positive input 6. */ + #define CMP_PDD_POSITIVE_INPUT_7 0x38U /**< Positive input 7. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the comparator's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of comparator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDevice(PeripheralBase, State) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACE_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_CS_ACE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the comparator's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of comparator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDevice(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_EN_MASK))) | ( \ + (uint8)(State))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetDeviceEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of comparator's enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of comparator's enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_EN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableInterrupts(_BASE_PTR, CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableInterrupts(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_SCR_REG(PeripheralBase) | (uint8)(Mask))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_DisableInterrupts(_BASE_PTR, + * CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_DisableInterrupts(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetInterruptMask(_BASE_PTR, CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACIE_MASK))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetInterruptMask(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)(CMP_SCR_IEF_MASK | CMP_SCR_IER_MASK))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACIE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & (uint8)(CMP_SCR_IEF_MASK | CMP_SCR_IER_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACF_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & (uint8)(CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_ClearInterruptFlags(_BASE_PTR, CMP_PDD_EDGE_FLAG); + * @endcode + */ + #define CMP_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACF_MASK))) | ( \ + (uint8)((uint8)(~(uint8)(Mask)) & ACMP_CS_ACF_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_ClearInterruptFlags(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetHysteresis + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets comparator hard block hysteresis control bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Hysteresis Hysteresis value. This parameter is of "Hysteresis + * constants. For exact value representation see peripheral device documentation." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetHysteresis(_BASE_PTR, + * CMP_PDD_HYSTERESIS_LEVEL_0); + * @endcode + */ + #define CMP_PDD_SetHysteresis(PeripheralBase, Hysteresis) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_HYST_MASK))) | ( \ + (uint8)(Hysteresis))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets comparator hard block hysteresis control bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Hysteresis Hysteresis value. This parameter is of "Hysteresis + * constants. For exact value representation see peripheral device documentation." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetHysteresis(_BASE_PTR, + * CMP_PDD_HYSTERESIS_LEVEL_0); + * @endcode + */ + #define CMP_PDD_SetHysteresis(PeripheralBase, Hysteresis) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR0_HYSTCTR_MASK))) | ( \ + (uint8)(Hysteresis))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetHysteresis + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Hysteresis constants. For exact value + * representation see peripheral device documentation." type. The value is cast to + * "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetHysteresis(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetHysteresis(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_HYST_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Hysteresis constants. For exact value + * representation see peripheral device documentation." type. The value is cast to + * "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetHysteresis(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetHysteresis(PeripheralBase) ( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & CMP_CR0_HYSTCTR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter sample count bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Filter sample count. This parameter is of "Filter sample count + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetFilterCount(_BASE_PTR, CMP_PDD_FILTER_DISABLED); + * @endcode + */ +#define CMP_PDD_SetFilterCount(PeripheralBase, Count) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR0_FILTER_CNT_MASK))) | ( \ + (uint8)(Count))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Filter sample count constants." type. The value + * is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetFilterCount(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetFilterCount(PeripheralBase) ( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & CMP_CR0_FILTER_CNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOutputPin + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Comparator output pin enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if output pin will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableOutputPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableOutputPin(PeripheralBase, State) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACOPE_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_CS_ACOPE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Comparator output pin enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if output pin will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableOutputPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableOutputPin(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_OPE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_OPE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetOutputPinEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns whether is the output pin enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetOutputPinEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetOutputPinEnabled(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACOPE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns whether is the output pin enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetOutputPinEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetOutputPinEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_OPE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetComparatorOutputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator output filtration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Output Parameter specifying if output will be filtered or not. This + * parameter is of "Comparator output filtration constant" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorOutputFilter(_BASE_PTR, + * CMP_PDD_FILTERED_OUTPUT); + * @endcode + */ +#define CMP_PDD_SetComparatorOutputFilter(PeripheralBase, Output) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_COS_MASK))) | ( \ + (uint8)(Output))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of comparator output filtration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator output filtration constant" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetComparatorOutputFilter(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorOutputFilter(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_COS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComparatorOutputInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator output inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Output Parameter specifying if output will be inverted or not. This + * parameter is of "Comparator output inversion constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorOutputInversion(_BASE_PTR, + * CMP_PDD_NOT_INVERTED_OUTPUT); + * @endcode + */ +#define CMP_PDD_SetComparatorOutputInversion(PeripheralBase, Output) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_INV_MASK))) | ( \ + (uint8)(Output))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutputInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the comparator output is inverted. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator output inversion constant." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetComparatorOutputInversion(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorOutputInversion(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_INV_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Power mode. This parameter is of "Comparator power mode + * constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetPowerMode(_BASE_PTR, CMP_PDD_LOW_POWER_MODE); + * @endcode + */ +#define CMP_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_PMODE_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current comparator power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator power mode constant." type. The value + * is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPowerMode(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetPowerMode(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_PMODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWindowing + ---------------------------------------------------------------------------- */ + +/** + * @brief Windowing enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if windowing will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableWindowing(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableWindowing(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_WE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_WE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetWindowingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the windowing is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetWindowingEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetWindowingEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_WE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSampling + ---------------------------------------------------------------------------- */ + +/** + * @brief Sampling enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if sampling will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableSampling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableSampling(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_SE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_SE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSamplingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the sampling is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetSamplingEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetSamplingEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_SE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterPeriod + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter sample period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Filter sample period value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetFilterPeriod(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_SetFilterPeriod(PeripheralBase, Period) ( \ + CMP_FPR_REG(PeripheralBase) = \ + (uint8)(Period) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterPeriod + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current filter sample period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetFilterPeriod(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetFilterPeriod(PeripheralBase) ( \ + CMP_FPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current comparator output state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorOutput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetComparatorOutput(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current comparator output state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorOutput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetComparatorOutput(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & CMP_SCR_COUT_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)CMP_SCR_DMAEN_MASK)) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)((uint8)(State) << CMP_SCR_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComparatorMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets comparator's interrupt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Comparator interrupt mode. Use constants from group "Comparator + * modes". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorMode(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_MODE); + * @endcode + */ + #define CMP_PDD_SetComparatorMode(PeripheralBase, Mode) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACMOD_MASK))) | ( \ + (uint8)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets comparator's interrupt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Comparator interrupt mode. Use constants from group "Comparator + * modes". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorMode(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_MODE); + * @endcode + */ + #define CMP_PDD_SetComparatorMode(PeripheralBase, Mode) ( \ + CMP_PDD_SetInterruptMask(PeripheralBase, (uint8)(Mode)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCompareStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns last detected edge on comparator's output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @par Example: + * @code + * uint8 result = CMP_PDD_GetCompareStatus(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetCompareStatus(PeripheralBase) ( \ + CMP_PDD_GetInterruptFlags(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetVoltage + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Output voltage value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetVoltage(_BASE_PTR, 1); + * @endcode + */ + #define CMP_PDD_SetVoltage(PeripheralBase, Value) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACVAL_MASK))) | ( \ + (uint8)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Output voltage value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetVoltage(_BASE_PTR, 1); + * @endcode + */ + #define CMP_PDD_SetVoltage(PeripheralBase, Value) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_VOSEL_MASK))) | ( \ + (uint8)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetVoltage + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetVoltage(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetVoltage(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACVAL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetVoltage(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetVoltage(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_VOSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetReference + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects analog comparator 6-bit DAC supply voltage reference source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Supply voltage source. This parameter is of "Analog + * comparator 6-bit DAC supply voltage reference source constant. For exact + * connection see peripheral device documentation." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetReference(_BASE_PTR, CMP_PDD_V_REF_INPUT_1); + * @endcode + */ + #define CMP_PDD_SetReference(PeripheralBase, Reference) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACREF_MASK))) | ( \ + (uint8)(Reference))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects analog comparator 6-bit DAC supply voltage reference source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Supply voltage source. This parameter is of "Analog + * comparator 6-bit DAC supply voltage reference source constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetReference(_BASE_PTR, CMP_PDD_V_REF_INPUT_1); + * @endcode + */ + #define CMP_PDD_SetReference(PeripheralBase, Reference) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_VRSEL_MASK))) | ( \ + (uint8)(Reference))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetReference + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected reference input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Analog comparator 6-bit DAC supply voltage + * reference source constant. For exact connection see peripheral device + * documentation." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetReference(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetReference(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACREF_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected reference input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Analog comparator 6-bit DAC supply voltage + * reference source constant." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetReference(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetReference(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_VRSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDac + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Analog comparator 6-bit DAC enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DAC will be enabled or disabled. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDac(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDac(PeripheralBase, State) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_C1_DACEN_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Analog comparator 6-bit DAC enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DAC will be enabled or disabled. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDac(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDac(PeripheralBase, State) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_DACCR_DACEN_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetDacEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of analog comparator 6-bit DAC enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDacEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDacEnabled(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACEN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of analog comparator 6-bit DAC enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDacEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDacEnabled(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_DACEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetNegativeInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets negative comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param NegativeInput Negative input number. This parameter is of "Negative + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetNegativeInput(_BASE_PTR, + * CMP_PDD_NEGATIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetNegativeInput(PeripheralBase, NegativeInput) ( \ + ACMP_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C0_ACNSEL_MASK))) | ( \ + (uint8)(NegativeInput))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets negative comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param NegativeInput Negative input number. This parameter is of "Negative + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetNegativeInput(_BASE_PTR, + * CMP_PDD_NEGATIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetNegativeInput(PeripheralBase, NegativeInput) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_MSEL_MASK))) | ( \ + (uint8)(NegativeInput))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetNegativeInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected negative input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Negative input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetNegativeInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetNegativeInput(PeripheralBase) ( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & ACMP_C0_ACNSEL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected negative input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Negative input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetNegativeInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetNegativeInput(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_MSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPositiveInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets positive comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PositiveInput Positive input number. This parameter is of "Positive + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetPositiveInput(_BASE_PTR, + * CMP_PDD_POSITIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetPositiveInput(PeripheralBase, PositiveInput) ( \ + ACMP_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C0_ACPSEL_MASK))) | ( \ + (uint8)(PositiveInput))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets positive comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PositiveInput Positive input number. This parameter is of "Positive + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetPositiveInput(_BASE_PTR, + * CMP_PDD_POSITIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetPositiveInput(PeripheralBase, PositiveInput) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PSEL_MASK))) | ( \ + (uint8)(PositiveInput))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetPositiveInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected positive input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Positive input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPositiveInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetPositiveInput(PeripheralBase) ( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & ACMP_C0_ACPSEL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected positive input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Positive input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPositiveInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetPositiveInput(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_PSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePassThroughMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Used to enable to MUX pass through mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables/Disables pass through mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnablePassThroughMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnablePassThroughMode(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PSTM_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_PSTM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPassThroughModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the pass through mode is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetPassThroughModeEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetPassThroughModeEnabled(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_PSTM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteControl0Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteControl0Reg(PeripheralBase, Value) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadControl0Reg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadControl0Reg(PeripheralBase) ( \ + CMP_CR0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadControl1Reg(PeripheralBase) ( \ + CMP_CR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFilterPeriodReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Filter period register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteFilterPeriodReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteFilterPeriodReg(PeripheralBase, Value) ( \ + CMP_FPR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFilterPeriodReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Filter period register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadFilterPeriodReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadFilterPeriodReg(PeripheralBase) ( \ + CMP_FPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadStatusControlReg(PeripheralBase) ( \ + CMP_SCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DAC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteDacControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteDacControlReg(PeripheralBase, Value) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Dac control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadDacControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadDacControlReg(PeripheralBase) ( \ + CMP_DACCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMuxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the MUX control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteMuxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteMuxControlReg(PeripheralBase, Value) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMuxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the MUX control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadMuxControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadMuxControlReg(PeripheralBase) ( \ + CMP_MUXCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects stop mode edge/level interrupt control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying if edge or level stop mode will be used. + * This parameter is of "Comparator's interrupt stop mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetStopMode(_BASE_PTR, + * CMP_PDD_LEVEL_SENSITIVE_MODE); + * @endcode + */ +#define CMP_PDD_SetStopMode(PeripheralBase, Mode) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)CMP_SCR_SMELB_MASK)) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableNegativeInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Negative MUX enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if negative input will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableNegativeInput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableNegativeInput(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_MEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_MEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePositiveInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Postive MUX enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if positive input will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnablePositiveInput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnablePositiveInput(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_PEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTriggerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Trigger mode enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if trigger mode for DAC will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableTriggerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableTriggerMode(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_TRIGM_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_TRIGM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the trigger mode is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetTriggerModeEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetTriggerModeEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_TRIGM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current edge detection mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Comparator modes" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorMode(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorMode(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACMOD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExternalInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable specified external inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EnExtInput Mask of enabled external inputs. Use constants from group + * "External input mask". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_C2, ACMP1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableExternalInput(_BASE_PTR, + * CMP_PDD_EXTERNAL_INPUT_0); + * @endcode + */ +#define CMP_PDD_EnableExternalInput(PeripheralBase, EnExtInput) ( \ + ACMP_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C2_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C2_ACIPE_MASK))) | ( \ + (uint8)(EnExtInput))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnabledExternalInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the mask of enabled external inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "External input mask" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ACMP0_C2, ACMP1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetEnabledExternalInput(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetEnabledExternalInput(PeripheralBase) ( \ + (uint8)(ACMP_C2_REG(PeripheralBase) & ACMP_C2_ACIPE_MASK) \ + ) +#endif /* #if defined(CMP_PDD_H_) */ + +/* CMP_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h new file mode 100644 index 0000000..01dcec7 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h @@ -0,0 +1,1110 @@ +/* + PDD layer implementation for peripheral type CMT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CMT_PDD_H_) +#define CMT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CMT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CMT */ && \ + !defined(MCU_MK10D5) /* CMT */ && \ + !defined(MCU_MK10D7) /* CMT */ && \ + !defined(MCU_MK10F12) /* CMT */ && \ + !defined(MCU_MK10DZ10) /* CMT */ && \ + !defined(MCU_MK11D5) /* CMT */ && \ + !defined(MCU_MK11D5WS) /* CMT */ && \ + !defined(MCU_MK12D5) /* CMT */ && \ + !defined(MCU_MK20D10) /* CMT */ && \ + !defined(MCU_MK20D5) /* CMT */ && \ + !defined(MCU_MK20D7) /* CMT */ && \ + !defined(MCU_MK20F12) /* CMT */ && \ + !defined(MCU_MK20DZ10) /* CMT */ && \ + !defined(MCU_MK21D5) /* CMT */ && \ + !defined(MCU_MK21D5WS) /* CMT */ && \ + !defined(MCU_MK21F12) /* CMT */ && \ + !defined(MCU_MK21F12WS) /* CMT */ && \ + !defined(MCU_MK22D5) /* CMT */ && \ + !defined(MCU_MK22F12) /* CMT */ && \ + !defined(MCU_MK24F12) /* CMT */ && \ + !defined(MCU_MK30D10) /* CMT */ && \ + !defined(MCU_MK30D7) /* CMT */ && \ + !defined(MCU_MK30DZ10) /* CMT */ && \ + !defined(MCU_MK40D10) /* CMT */ && \ + !defined(MCU_MK40D7) /* CMT */ && \ + !defined(MCU_MK40DZ10) /* CMT */ && \ + !defined(MCU_MK40X256VMD100) /* CMT */ && \ + !defined(MCU_MK50D10) /* CMT */ && \ + !defined(MCU_MK50D7) /* CMT */ && \ + !defined(MCU_MK50DZ10) /* CMT */ && \ + !defined(MCU_MK51D10) /* CMT */ && \ + !defined(MCU_MK51D7) /* CMT */ && \ + !defined(MCU_MK51DZ10) /* CMT */ && \ + !defined(MCU_MK52D10) /* CMT */ && \ + !defined(MCU_MK52DZ10) /* CMT */ && \ + !defined(MCU_MK53D10) /* CMT */ && \ + !defined(MCU_MK53DZ10) /* CMT */ && \ + !defined(MCU_MK60D10) /* CMT */ && \ + !defined(MCU_MK60F12) /* CMT */ && \ + !defined(MCU_MK60F15) /* CMT */ && \ + !defined(MCU_MK60DZ10) /* CMT */ && \ + !defined(MCU_MK60N512VMD100) /* CMT */ && \ + !defined(MCU_MK61F12) /* CMT */ && \ + !defined(MCU_MK61F15) /* CMT */ && \ + !defined(MCU_MK61F12WS) /* CMT */ && \ + !defined(MCU_MK61F15WS) /* CMT */ && \ + !defined(MCU_MK63F12) /* CMT */ && \ + !defined(MCU_MK63F12WS) /* CMT */ && \ + !defined(MCU_MK64F12) /* CMT */ && \ + !defined(MCU_MK65F18) /* CMT */ && \ + !defined(MCU_MK65F18WS) /* CMT */ && \ + !defined(MCU_MK66F18) /* CMT */ && \ + !defined(MCU_MK70F12) /* CMT */ && \ + !defined(MCU_MK70F15) /* CMT */ && \ + !defined(MCU_MK70F12WS) /* CMT */ && \ + !defined(MCU_MK70F15WS) /* CMT */ && \ + !defined(MCU_MKW21D5) /* CMT */ && \ + !defined(MCU_MKW21D5WS) /* CMT */ && \ + !defined(MCU_MKW22D5) /* CMT */ && \ + !defined(MCU_MKW22D5WS) /* CMT */ && \ + !defined(MCU_MKW24D5) /* CMT */ && \ + !defined(MCU_MKW24D5WS) /* CMT */ && \ + !defined(MCU_PCK20L4) /* CMT */ + // Unsupported MCU is active + #error CMT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Enable baseband constants */ +#define CMT_PDD_BASEBAND_DISABLED 0U /**< Disabled */ +#define CMT_PDD_BASEBAND_ENABLED CMT_MSC_BASE_MASK /**< Enabled */ + +/* Enable FSK constants */ +#define CMT_PDD_MODE_TIME_BASEBAND 0U /**< Time baseband */ +#define CMT_PDD_MODE_FSK CMT_MSC_FSK_MASK /**< FSK */ + +/* Divider constants */ +#define CMT_PDD_DIVIDER_1 0U /**< 1 */ +#define CMT_PDD_DIVIDER_2 0x1U /**< 2 */ +#define CMT_PDD_DIVIDER_4 0x2U /**< 4 */ +#define CMT_PDD_DIVIDER_8 0x3U /**< 8 */ + +/* Prescaler constants */ +#define CMT_PDD_PRESCALER_1 0U /**< 1 */ +#define CMT_PDD_PRESCALER_2 0x1U /**< 2 */ +#define CMT_PDD_PRESCALER_3 0x2U /**< 3 */ +#define CMT_PDD_PRESCALER_4 0x3U /**< 4 */ +#define CMT_PDD_PRESCALER_5 0x4U /**< 5 */ +#define CMT_PDD_PRESCALER_6 0x5U /**< 6 */ +#define CMT_PDD_PRESCALER_7 0x6U /**< 7 */ +#define CMT_PDD_PRESCALER_8 0x7U /**< 8 */ +#define CMT_PDD_PRESCALER_9 0x8U /**< 9 */ +#define CMT_PDD_PRESCALER_10 0x9U /**< 10 */ +#define CMT_PDD_PRESCALER_11 0xAU /**< 11 */ +#define CMT_PDD_PRESCALER_12 0xBU /**< 12 */ +#define CMT_PDD_PRESCALER_13 0xCU /**< 13 */ +#define CMT_PDD_PRESCALER_14 0xDU /**< 14 */ +#define CMT_PDD_PRESCALER_15 0xEU /**< 15 */ +#define CMT_PDD_PRESCALER_16 0xFU /**< 16 */ + +/* IRO pin constants */ +#define CMT_PDD_PIN_DISABLED 0U /**< Disabled */ +#define CMT_PDD_PIN_ENABLED CMT_OC_IROPEN_MASK /**< Enabled */ + +/* CMT output polarity constants */ +#define CMT_PDD_POLARITY_LOW 0U /**< Low */ +#define CMT_PDD_POLARITY_HIGH CMT_OC_CMTPOL_MASK /**< High */ + +/* IRO latch constants */ +#define CMT_PDD_LATCH_LOW 0U /**< Low */ +#define CMT_PDD_LATCH_HIGH CMT_OC_IROL_MASK /**< High */ + +/* Enable DMA constants */ +#define CMT_PDD_DMA_DISABLED 0U /**< Disabled */ +#define CMT_PDD_DMA_ENABLED CMT_DMA_DMA_MASK /**< Enabled */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_EOCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_EOCF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CMT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_EnableInterrupt(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) |= \ + CMT_MSC_EOCIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CMT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_DisableInterrupt(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) &= \ + (uint8)(~(uint8)CMT_MSC_EOCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CMT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC, CMT_CMD2 + * (depending on the peripheral). + * @par Example: + * @code + * CMT_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ClearInterruptFlag(PeripheralBase) ( \ + (void)CMT_MSC_REG(PeripheralBase), \ + (void)CMT_CMD2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBaseband + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the freerun mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Baseband New value of the baseband. Use constants from group "Enable + * baseband constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableBaseband(_BASE_PTR, + * CMT_PDD_BASEBAND_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableBaseband(PeripheralBase, Baseband) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_BASE_MASK))) | ( \ + (uint8)(Baseband))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFskMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Enable FSK + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_SelectFskMode(_BASE_PTR, + * CMT_PDD_MODE_TIME_BASEBAND); + * @endcode + */ +#define CMT_PDD_SelectFskMode(PeripheralBase, Mode) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_FSK_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExtendedSpace + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures extended space. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Extended Extended space enabled/disabled. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableExtendedSpace(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMT_PDD_EnableExtendedSpace(PeripheralBase, Extended) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_EXSPC_MASK))) | ( \ + (uint8)((uint8)(Extended) << CMT_MSC_EXSPC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CMT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of CMT device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMT_PDD_EnableDevice(PeripheralBase, State) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_MCGEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of CMT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_MCGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock divide prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the divider. Use constants from group "Divider + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_SetDivider(_BASE_PTR, CMT_PDD_DIVIDER_1); + * @endcode + */ +#define CMT_PDD_SetDivider(PeripheralBase, Divider) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_CMTDIV_MASK))) | ( \ + (uint8)((uint8)(Divider) << CMT_MSC_CMTDIV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets primary prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * CMT_PDD_SetPrescaler(_BASE_PTR, CMT_PDD_PRESCALER_1); + * @endcode + */ +#define CMT_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + CMT_PPS_REG(PeripheralBase) = \ + (uint8)(Prescaler) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIroPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables IRO signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pin New value of the IROpin. Use constants from group "IRO pin + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_EnableIroPin(_BASE_PTR, CMT_PDD_PIN_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableIroPin(PeripheralBase, Pin) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_IROPEN_MASK))) | ( \ + (uint8)(Pin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures CMT output polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity New value of the polarity. Use constants from group "CMT + * output polarity constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_SetPolarity(_BASE_PTR, CMT_PDD_POLARITY_LOW); + * @endcode + */ +#define CMT_PDD_SetPolarity(PeripheralBase, Polarity) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_CMTPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLatch + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures IRO latch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State New value of the latch. Use constants from group "IRO latch + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_SetLatch(_BASE_PTR, CMT_PDD_LATCH_LOW); + * @endcode + */ +#define CMT_PDD_SetLatch(PeripheralBase, State) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_IROL_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDMA + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the dma mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the DMA. Use constants from group "Enable DMA + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * CMT_PDD_EnableDMA(_BASE_PTR, CMT_PDD_DMA_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableDMA(PeripheralBase, Value) ( \ + CMT_DMA_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_DMA_REG(PeripheralBase) & (uint8)(~(uint8)CMT_DMA_DMA_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteHighData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGH1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGH1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGH1. + * @par Example: + * @code + * CMT_PDD_WriteHighData1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteHighData1Reg(PeripheralBase, Value) ( \ + CMT_CGH1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGH1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGH1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadHighData1Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadHighData1Reg(PeripheralBase) ( \ + CMT_CGH1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLowData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGL1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGL1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGL1. + * @par Example: + * @code + * CMT_PDD_WriteLowData1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteLowData1Reg(PeripheralBase, Value) ( \ + CMT_CGL1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLowData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGL1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGL1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadLowData1Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadLowData1Reg(PeripheralBase) ( \ + CMT_CGL1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteHighData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGH2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGH2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGH2. + * @par Example: + * @code + * CMT_PDD_WriteHighData2Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteHighData2Reg(PeripheralBase, Value) ( \ + CMT_CGH2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGH2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGH2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadHighData2Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadHighData2Reg(PeripheralBase) ( \ + CMT_CGH2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLowData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGL2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGL2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGL2. + * @par Example: + * @code + * CMT_PDD_WriteLowData2Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteLowData2Reg(PeripheralBase, Value) ( \ + CMT_CGL2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLowData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGL2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGL2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadLowData2Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadLowData2Reg(PeripheralBase) ( \ + CMT_CGL2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOutputControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the OC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the OC register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_WriteOutputControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteOutputControlReg(PeripheralBase, Value) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOutputControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the OC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadOutputControlReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadOutputControlReg(PeripheralBase) ( \ + CMT_OC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the MSC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the MSC register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the MSC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadStatusControlReg(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMarkHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD1. + * @par Example: + * @code + * CMT_PDD_WriteMarkHighReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteMarkHighReg(PeripheralBase, Value) ( \ + CMT_CMD1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMarkHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadMarkHighReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadMarkHighReg(PeripheralBase) ( \ + CMT_CMD1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMarkLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD2. + * @par Example: + * @code + * CMT_PDD_WriteMarkLowReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteMarkLowReg(PeripheralBase, Value) ( \ + CMT_CMD2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMarkLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadMarkLowReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadMarkLowReg(PeripheralBase) ( \ + CMT_CMD2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSpaceHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD3 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD3. + * @par Example: + * @code + * CMT_PDD_WriteSpaceHighReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteSpaceHighReg(PeripheralBase, Value) ( \ + CMT_CMD3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSpaceHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD3. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadSpaceHighReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadSpaceHighReg(PeripheralBase) ( \ + CMT_CMD3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSpaceLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD4 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD4. + * @par Example: + * @code + * CMT_PDD_WriteSpaceLowReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteSpaceLowReg(PeripheralBase, Value) ( \ + CMT_CMD4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSpaceLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD4. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadSpaceLowReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadSpaceLowReg(PeripheralBase) ( \ + CMT_CMD4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePrimaryPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the PPS register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the PPS register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * CMT_PDD_WritePrimaryPrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WritePrimaryPrescalerReg(PeripheralBase, Value) ( \ + CMT_PPS_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrimaryPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the PPS register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadPrimaryPrescalerReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadPrimaryPrescalerReg(PeripheralBase) ( \ + CMT_PPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDMAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DMA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the DMA register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * CMT_PDD_WriteDMAReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteDMAReg(PeripheralBase, Value) ( \ + CMT_DMA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDMAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DMA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadDMAReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadDMAReg(PeripheralBase) ( \ + CMT_DMA_REG(PeripheralBase) \ + ) +#endif /* #if defined(CMT_PDD_H_) */ + +/* CMT_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h new file mode 100644 index 0000000..6e165ab --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h @@ -0,0 +1,1134 @@ +/* + PDD layer implementation for peripheral type CRC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CRC_PDD_H_) +#define CRC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CRC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CRC */ && \ + !defined(MCU_MK10D5) /* CRC */ && \ + !defined(MCU_MK10D7) /* CRC */ && \ + !defined(MCU_MK10F12) /* CRC */ && \ + !defined(MCU_MK10DZ10) /* CRC */ && \ + !defined(MCU_MK11D5) /* CRC */ && \ + !defined(MCU_MK11D5WS) /* CRC */ && \ + !defined(MCU_MK12D5) /* CRC */ && \ + !defined(MCU_MK20D10) /* CRC */ && \ + !defined(MCU_MK20D5) /* CRC */ && \ + !defined(MCU_MK20D7) /* CRC */ && \ + !defined(MCU_MK20F12) /* CRC */ && \ + !defined(MCU_MK20DZ10) /* CRC */ && \ + !defined(MCU_MK21D5) /* CRC */ && \ + !defined(MCU_MK21D5WS) /* CRC */ && \ + !defined(MCU_MK21F12) /* CRC */ && \ + !defined(MCU_MK21F12WS) /* CRC */ && \ + !defined(MCU_MK22D5) /* CRC */ && \ + !defined(MCU_MK22F12810) /* CRC */ && \ + !defined(MCU_MK22F12) /* CRC */ && \ + !defined(MCU_MK22F25612) /* CRC */ && \ + !defined(MCU_MK22F51212) /* CRC */ && \ + !defined(MCU_MK24F12) /* CRC */ && \ + !defined(MCU_MK30D10) /* CRC */ && \ + !defined(MCU_MK30D7) /* CRC */ && \ + !defined(MCU_MK30DZ10) /* CRC */ && \ + !defined(MCU_MK40D10) /* CRC */ && \ + !defined(MCU_MK40D7) /* CRC */ && \ + !defined(MCU_MK40DZ10) /* CRC */ && \ + !defined(MCU_MK40X256VMD100) /* CRC */ && \ + !defined(MCU_MK50D10) /* CRC */ && \ + !defined(MCU_MK50D7) /* CRC */ && \ + !defined(MCU_MK50DZ10) /* CRC */ && \ + !defined(MCU_MK51D10) /* CRC */ && \ + !defined(MCU_MK51D7) /* CRC */ && \ + !defined(MCU_MK51DZ10) /* CRC */ && \ + !defined(MCU_MK52D10) /* CRC */ && \ + !defined(MCU_MK52DZ10) /* CRC */ && \ + !defined(MCU_MK53D10) /* CRC */ && \ + !defined(MCU_MK53DZ10) /* CRC */ && \ + !defined(MCU_MK60D10) /* CRC */ && \ + !defined(MCU_MK60F12) /* CRC */ && \ + !defined(MCU_MK60F15) /* CRC */ && \ + !defined(MCU_MK60DZ10) /* CRC */ && \ + !defined(MCU_MK60N512VMD100) /* CRC */ && \ + !defined(MCU_MK61F12) /* CRC */ && \ + !defined(MCU_MK61F15) /* CRC */ && \ + !defined(MCU_MK61F12WS) /* CRC */ && \ + !defined(MCU_MK61F15WS) /* CRC */ && \ + !defined(MCU_MK63F12) /* CRC */ && \ + !defined(MCU_MK63F12WS) /* CRC */ && \ + !defined(MCU_MK64F12) /* CRC */ && \ + !defined(MCU_MK65F18) /* CRC */ && \ + !defined(MCU_MK65F18WS) /* CRC */ && \ + !defined(MCU_MK66F18) /* CRC */ && \ + !defined(MCU_MK70F12) /* CRC */ && \ + !defined(MCU_MK70F15) /* CRC */ && \ + !defined(MCU_MK70F12WS) /* CRC */ && \ + !defined(MCU_MK70F15WS) /* CRC */ && \ + !defined(MCU_MKE02Z2) /* CRC */ && \ + !defined(MCU_MKE02Z4) /* CRC */ && \ + !defined(MCU_SKEAZN642) /* CRC */ && \ + !defined(MCU_MKE04Z1284) /* CRC */ && \ + !defined(MCU_MKE04Z4) /* CRC */ && \ + !defined(MCU_SKEAZN84) /* CRC */ && \ + !defined(MCU_MKE06Z4) /* CRC */ && \ + !defined(MCU_MKV10Z7) /* CRC */ && \ + !defined(MCU_MKV31F12810) /* CRC */ && \ + !defined(MCU_MKV31F25612) /* CRC */ && \ + !defined(MCU_MKV31F51212) /* CRC */ && \ + !defined(MCU_MKW21D5) /* CRC */ && \ + !defined(MCU_MKW21D5WS) /* CRC */ && \ + !defined(MCU_MKW22D5) /* CRC */ && \ + !defined(MCU_MKW22D5WS) /* CRC */ && \ + !defined(MCU_MKW24D5) /* CRC */ && \ + !defined(MCU_MKW24D5WS) /* CRC */ && \ + !defined(MCU_PCK20L4) /* CRC */ && \ + !defined(MCU_SKEAZ1284) /* CRC */ + // Unsupported MCU is active + #error CRC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Computation parameters of CRC standards. */ +#define CRC_PDD_NO_TRANSPOSE 0U /**< No transpose of data. */ +#define CRC_PDD_BITS 0x1U /**< Bits are swapped. */ +#define CRC_PDD_BITS_AND_BYTES 0x2U /**< Bytes and bits are swapped. */ +#define CRC_PDD_BYTES 0x3U /**< Bytes are swapped. */ + + +/* ---------------------------------------------------------------------------- + -- GetCRCDataRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CRC_PDD_GetCRCDataRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataRegister(PeripheralBase) ( \ + CRC_DATA_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CRC_PDD_GetCRCDataRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataRegister(PeripheralBase) ( \ + CRC_CRC_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCRCDataHRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns upper 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataHRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataHRegister(PeripheralBase) ( \ + CRC_DATAH_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns upper 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataHRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataHRegister(PeripheralBase) ( \ + CRC_CRCH_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCRCDataLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns lower 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataLRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataLRegister(PeripheralBase) ( \ + CRC_DATAL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns lower 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataLRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataLRegister(PeripheralBase) ( \ + CRC_CRCL_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (4 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataRegister(PeripheralBase, Data) ( \ + CRC_DATA_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (4 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataRegister(PeripheralBase, Data) ( \ + CRC_CRC_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (2 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLRegister(PeripheralBase, Data) ( \ + CRC_DATAL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (2 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLRegister(PeripheralBase, Data) ( \ + CRC_CRCL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataLLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (1 byte). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCLL, CRC_DATALL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLLRegister(PeripheralBase, Data) ( \ + CRC_DATALL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (1 byte). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCLL, CRC_DATALL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLLRegister(PeripheralBase, Data) ( \ + CRC_CRCLL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetSeedHigh + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set upper 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedHigh(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedHigh(PeripheralBase, Data) ( \ + CRC_DATAH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set upper 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedHigh(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedHigh(PeripheralBase, Data) ( \ + CRC_CRCH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetSeedLow + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set lower 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedLow(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedLow(PeripheralBase, Data) ( \ + CRC_DATAL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set lower 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedLow(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedLow(PeripheralBase, Data) ( \ + CRC_CRCL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPolyHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Set upper 16 bits of polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Polynomial value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLYH. + * @par Example: + * @code + * CRC_PDD_SetPolyHigh(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetPolyHigh(PeripheralBase, Data) ( \ + CRC_GPOLYH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPolyLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Set lower 16 bits of polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Polynomial value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLYL. + * @par Example: + * @code + * CRC_PDD_SetPolyLow(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetPolyLow(PeripheralBase, Data) ( \ + CRC_GPOLYL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRCControlRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Control register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRCControlRegister(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetCRCControlRegister(PeripheralBase, Data) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSeedBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetSeedBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetSeedBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_WAS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSeedBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_ClearSeedBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ClearSeedBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_WAS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetXorBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable result XORing with 0xFFFF or 0xFFFFFFFF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetXorBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetXorBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_FXOR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearXorBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable result XORing with 0xFFFF or 0xFFFFFFFF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_ClearXorBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ClearXorBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC32bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC module for 32bit computation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC32bit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC32bit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_TCRC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC16bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC module for 16bit computation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC16bit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC16bit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Set input data transposition type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Input data transposition type. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetInputTranspose(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetInputTranspose(PeripheralBase, Type) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & (uint32)(~(uint32)CRC_CTRL_TOT_MASK))) | ( \ + (uint32)((uint32)(Type) << CRC_CTRL_TOT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOutputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Set output data transposition type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Output data transposition type. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetOutputTranspose(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetOutputTranspose(PeripheralBase, Type) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))) | ( \ + (uint32)((uint32)(Type) << CRC_CTRL_TOTR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOutputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Get output transpose settings. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint8 result = CRC_PDD_GetOutputTranspose(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_GetOutputTranspose(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & CRC_CTRL_TOTR_MASK)) >> ( \ + CRC_CTRL_TOTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Get input transpose settings. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint8 result = CRC_PDD_GetInputTranspose(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_GetInputTranspose(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & CRC_CTRL_TOT_MASK)) >> ( \ + CRC_CTRL_TOT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_16 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CRC16 standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_16(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_16(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CRC32 standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_32(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_32(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) | (( \ + CRC_CTRL_TCRC_MASK) | (( \ + CRC_CTRL_WAS_MASK) | ( \ + CRC_CTRL_FXOR_MASK))))) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_CCITT + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CCITT standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_CCITT(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_CCITT(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | ( \ + CRC_CTRL_WAS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_KERMIT + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for KERMIT standard operation and starts seed + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_KERMIT(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_KERMIT(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_DNP + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for DNP standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_DNP(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_DNP(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK)))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + CRC_CTRL_FXOR_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_MODBUS16 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for MODBUS16 standard operation and starts seed + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_MODBUS16(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_MODBUS16(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_DATA. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadDataReg(PeripheralBase) ( \ + CRC_DATA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC data + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC data register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_DATA. + * @par Example: + * @code + * CRC_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WriteDataReg(PeripheralBase, Value) ( \ + CRC_DATA_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPolynomialReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_GPOLY. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadPolynomialReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadPolynomialReg(PeripheralBase) ( \ + CRC_GPOLY_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePolynomialReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC polynomial + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC polynomial register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLY. + * @par Example: + * @code + * CRC_PDD_WritePolynomialReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WritePolynomialReg(PeripheralBase, Value) ( \ + CRC_GPOLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadControlReg(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WriteControlReg(PeripheralBase, Value) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(CRC_PDD_H_) */ + +/* CRC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h new file mode 100644 index 0000000..ff56063 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h @@ -0,0 +1,1353 @@ +/* + PDD layer implementation for peripheral type DAC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DAC_PDD_H_) +#define DAC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DAC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK10D7) /* DAC0 */ && \ + !defined(MCU_MK10F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK10DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK11D5) /* DAC0 */ && \ + !defined(MCU_MK11D5WS) /* DAC0 */ && \ + !defined(MCU_MK12D5) /* DAC0 */ && \ + !defined(MCU_MK20D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK20D7) /* DAC0 */ && \ + !defined(MCU_MK20F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK20DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK21D5) /* DAC0 */ && \ + !defined(MCU_MK21D5WS) /* DAC0 */ && \ + !defined(MCU_MK21F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK21F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK22D5) /* DAC0 */ && \ + !defined(MCU_MK22F12810) /* DAC0 */ && \ + !defined(MCU_MK22F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK22F25612) /* DAC0 */ && \ + !defined(MCU_MK22F51212) /* DAC0, DAC1 */ && \ + !defined(MCU_MK24F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK30D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK30D7) /* DAC0 */ && \ + !defined(MCU_MK30DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40D7) /* DAC0 */ && \ + !defined(MCU_MK40DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40X256VMD100) /* DAC0, DAC1 */ && \ + !defined(MCU_MK50D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK50D7) /* DAC0 */ && \ + !defined(MCU_MK50DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK51D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK51D7) /* DAC0 */ && \ + !defined(MCU_MK51DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK52D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK52DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK53D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK53DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60N512VMD100) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F15WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK63F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK63F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK64F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK65F18) /* DAC0, DAC1 */ && \ + !defined(MCU_MK65F18WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK66F18) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F15WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MKL05Z4) /* DAC0 */ && \ + !defined(MCU_MKL15Z4) /* DAC0 */ && \ + !defined(MCU_MKL16Z4) /* DAC0 */ && \ + !defined(MCU_MKL25Z4) /* DAC0 */ && \ + !defined(MCU_MKL26Z4) /* DAC0 */ && \ + !defined(MCU_MKL36Z4) /* DAC0 */ && \ + !defined(MCU_MKL46Z4) /* DAC0 */ && \ + !defined(MCU_MKV10Z7) /* DAC0 */ && \ + !defined(MCU_MKV31F12810) /* DAC0 */ && \ + !defined(MCU_MKV31F25612) /* DAC0 */ && \ + !defined(MCU_MKV31F51212) /* DAC0, DAC1 */ && \ + !defined(MCU_MKW01Z4) /* DAC0 */ && \ + !defined(MCU_MKW21D5) /* DAC0 */ && \ + !defined(MCU_MKW21D5WS) /* DAC0 */ && \ + !defined(MCU_MKW22D5) /* DAC0 */ && \ + !defined(MCU_MKW22D5WS) /* DAC0 */ && \ + !defined(MCU_MKW24D5) /* DAC0 */ && \ + !defined(MCU_MKW24D5WS) /* DAC0 */ + // Unsupported MCU is active + #error DAC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Interrupts' masks. */ + #define DAC_PDD_BUFFER_START_INTERRUPT DAC_C0_DACBTIEN_MASK /**< Buffer start (top position) interrupt mask. */ + #define DAC_PDD_BUFFER_END_INTERRUPT DAC_C0_DACBBIEN_MASK /**< Buffer end (bottom position) interrupt mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' masks. */ + #define DAC_PDD_BUFFER_START_INTERRUPT DAC_C0_DACBTIEN_MASK /**< Buffer start (top position) interrupt mask. */ + #define DAC_PDD_BUFFER_END_INTERRUPT DAC_C0_DACBBIEN_MASK /**< Buffer end (bottom position) interrupt mask. */ + #define DAC_PDD_BUFFER_WATERMARK_INTERRUPT DAC_C0_DACBWIEN_MASK /**< Buffer watermark interrupt mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Interrupts' flags. */ + #define DAC_PDD_BUFFER_START_FLAG DAC_SR_DACBFRPTF_MASK /**< Buffer start (top position) flag. */ + #define DAC_PDD_BUFFER_END_FLAG DAC_SR_DACBFRPBF_MASK /**< Buffer end (bottom position) flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' flags. */ + #define DAC_PDD_BUFFER_START_FLAG DAC_SR_DACBFRPTF_MASK /**< Buffer start (top position) flag. */ + #define DAC_PDD_BUFFER_END_FLAG DAC_SR_DACBFRPBF_MASK /**< Buffer end (bottom position) flag. */ + #define DAC_PDD_BUFFER_WATERMARK_FLAG DAC_SR_DACBFWMF_MASK /**< Buffer watermark flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's trigger source constant. */ +#define DAC_PDD_HW_TRIGGER 0U /**< HW trigger. */ +#define DAC_PDD_SW_TRIGGER DAC_C0_DACTRGSEL_MASK /**< SW trigger. */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* D/A converter's buffer work mode constant. */ + #define DAC_PDD_BUFFER_NORMAL_MODE 0U /**< Normal mode. */ + #define DAC_PDD_BUFFER_OTSCAN_MODE 0x2U /**< One-time mode. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's buffer work mode constant. */ + #define DAC_PDD_BUFFER_NORMAL_MODE 0U /**< Normal mode. */ + #define DAC_PDD_BUFFER_SWING_MODE 0x1U /**< Swing mode. */ + #define DAC_PDD_BUFFER_OTSCAN_MODE 0x2U /**< One-time mode. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's buffer watermark constant. For exact value representation see + peripheral device documentation. */ +#define DAC_PDD_BUFFER_WATERMARK_L1 0U /**< Level 1 watermark (1 word). */ +#define DAC_PDD_BUFFER_WATERMARK_L2 0x1U /**< Level 2 watermark (2 words). */ +#define DAC_PDD_BUFFER_WATERMARK_L3 0x2U /**< Level 3 watermark (3 words). */ +#define DAC_PDD_BUFFER_WATERMARK_L4 0x3U /**< Level 4 watermark (4 words). */ + +/* D/A converter's buffer reference constant. */ +#define DAC_PDD_V_REF_INTERNAL 0U /**< Internal reference source. */ +#define DAC_PDD_V_REF_EXTERNAL DAC_C0_DACRFS_MASK /**< External reference source. */ + +/* D/A converter's buffer low power mode constant. */ +#define DAC_PDD_HIGH_POWER 0U /**< High power mode. */ +#define DAC_PDD_LOW_POWER DAC_C0_LPEN_MASK /**< Low power mode. */ + + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the D/A converter's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of D/A converter. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableDevice(PeripheralBase, State) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << DAC_C0_DACEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of D/A converter enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(DAC_C0_REG(PeripheralBase) & DAC_C0_DACEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableInterrupts(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ +#define DAC_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_DisableInterrupts(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ +#define DAC_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetInterruptMask(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ + #define DAC_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_C0_DACBBIEN_MASK | DAC_C0_DACBTIEN_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetInterruptMask(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ + #define DAC_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_C0_DACBBIEN_MASK | (DAC_C0_DACBTIEN_MASK | DAC_C0_DACBWIEN_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' masks." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(DAC_C0_DACBBIEN_MASK | DAC_C0_DACBTIEN_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' masks." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(DAC_C0_DACBBIEN_MASK | (DAC_C0_DACBTIEN_MASK | DAC_C0_DACBWIEN_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ClearInterruptFlags(_BASE_PTR, + * DAC_PDD_BUFFER_START_FLAG); + * @endcode + */ + #define DAC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))))) | ( \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ClearInterruptFlags(_BASE_PTR, + * DAC_PDD_BUFFER_START_FLAG); + * @endcode + */ + #define DAC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))))) | ( \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetData + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets value of D/A converter's data buffer word defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data word value. This parameter is a 12-bit value. + * @param RegIndex Buffer word index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[RegIndex], + * DATH[RegIndex] (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetData(_BASE_PTR, 1, periphID); + * @endcode + */ + #define DAC_PDD_SetData(PeripheralBase, Data, RegIndex) ( \ + (DAC_DATL_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(Data)), \ + (DAC_DATH_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(( \ + (uint8)(( \ + DAC_DATH_REG(PeripheralBase,(RegIndex))) & ( \ + (uint8)(~(uint8)DAC_DATH_DATA_MASK)))) | ( \ + (uint8)((uint16)(Data) >> 8U)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets value of D/A converter's data buffer word defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data word value. This parameter is a 12-bit value. + * @param RegIndex Buffer word index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[RegIndex], + * DATH[RegIndex] (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetData(_BASE_PTR, 1, periphID); + * @endcode + */ + #define DAC_PDD_SetData(PeripheralBase, Data, RegIndex) ( \ + (DAC_DATL_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(Data)), \ + (DAC_DATH_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(( \ + (uint8)(( \ + DAC_DATH_REG(PeripheralBase,(RegIndex))) & ( \ + (uint8)(~(uint8)DAC_DATH_DATA1_MASK)))) | ( \ + (uint8)((uint16)(Data) >> 8U)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief D/A converter's buffer enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if D/A converter's buffer will be enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableBuffer(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableBuffer(PeripheralBase, State) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBufferEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current data buffer state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferEnabled(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetBufferEnabled(PeripheralBase) ( \ + (uint8)(DAC_C1_REG(PeripheralBase) & DAC_C1_DACBFEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Trigger Parameter specifying which trigger source will be used. This + * parameter is of "D/A converter's trigger source constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetTrigger(_BASE_PTR, DAC_PDD_HW_TRIGGER); + * @endcode + */ +#define DAC_PDD_SetTrigger(PeripheralBase, Trigger) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACTRGSEL_MASK))) | ( \ + (uint8)(Trigger))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current trigger source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetTriggerSource(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetTriggerSource(PeripheralBase) ( \ + (uint8)(DAC_C0_REG(PeripheralBase) & DAC_C0_DACTRGSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceSwTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces D/A converter's software trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ForceSwTrigger(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ForceSwTrigger(PeripheralBase) ( \ + DAC_C0_REG(PeripheralBase) |= \ + DAC_C0_DACSWTRG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Selects D/A converter's buffer work mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying which data buffer work mode will be used. + * This parameter is of "D/A converter's buffer work mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferMode(_BASE_PTR, + * DAC_PDD_BUFFER_NORMAL_MODE); + * @endcode + */ + #define DAC_PDD_SetBufferMode(PeripheralBase, Mode) ( \ + ((Mode) == DAC_PDD_BUFFER_NORMAL_MODE) ? ( \ + DAC_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)DAC_C1_DACBFMD_MASK)) : ( \ + DAC_C1_REG(PeripheralBase) |= \ + DAC_C1_DACBFMD_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects D/A converter's buffer work mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying which data buffer work mode will be used. + * This parameter is of "D/A converter's buffer work mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferMode(_BASE_PTR, + * DAC_PDD_BUFFER_NORMAL_MODE); + * @endcode + */ + #define DAC_PDD_SetBufferMode(PeripheralBase, Mode) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFMD_MASK))) | ( \ + (uint8)((uint8)(Mode) << DAC_C1_DACBFMD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetBufferWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets D/A converter's buffer watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Parameter specifying data buffer watermark level. This + * parameter is of "D/A converter's buffer watermark constant. For exact value + * representation see peripheral device documentation." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferWatermark(_BASE_PTR, + * DAC_PDD_BUFFER_WATERMARK_L1); + * @endcode + */ +#define DAC_PDD_SetBufferWatermark(PeripheralBase, Watermark) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFWM_MASK))) | ( \ + (uint8)((uint8)(Watermark) << DAC_C1_DACBFWM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferReadPointer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets D/A converter's buffer read pointer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pointer Parameter specifying new data buffer read pointer value. This + * parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferReadPointer(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferReadPointer(PeripheralBase, Pointer) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFRP_MASK))) | ( \ + (uint8)((uint8)(Pointer) << DAC_C2_DACBFRP_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets D/A converter's buffer read pointer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pointer Parameter specifying new data buffer read pointer value. This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferReadPointer(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferReadPointer(PeripheralBase, Pointer) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFRP_MASK))) | ( \ + (uint8)((uint8)(Pointer) << DAC_C2_DACBFRP_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBufferReadPointer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns current data buffer read pointer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferReadPointer(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferReadPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFRP_MASK)) >> ( \ + DAC_C2_DACBFRP_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns current data buffer read pointer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferReadPointer(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferReadPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFRP_MASK)) >> ( \ + DAC_C2_DACBFRP_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetBufferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets D/A converter's buffer upper limit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Buffer upper limit (buffer register maximal index). This + * parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferSize(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferSize(PeripheralBase, Size) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFUP_MASK))) | ( \ + (uint8)(Size))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets D/A converter's buffer upper limit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Buffer upper limit (buffer register maximal index). This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferSize(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferSize(PeripheralBase, Size) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFUP_MASK))) | ( \ + (uint8)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBufferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns current data buffer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferSize(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferSize(PeripheralBase) ( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFUP_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns current data buffer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferSize(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferSize(PeripheralBase) ( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFUP_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Parameter specifying if internal or external voltage + * reference source will be used. This parameter is of "D/A converter's buffer + * reference constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetReference(_BASE_PTR, DAC_PDD_V_REF_INTERNAL); + * @endcode + */ +#define DAC_PDD_SetReference(PeripheralBase, Reference) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACRFS_MASK))) | ( \ + (uint8)(Reference))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's low power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying if high or low power mode will be used. This + * parameter is of "D/A converter's buffer low power mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetPowerMode(_BASE_PTR, DAC_PDD_HIGH_POWER); + * @endcode + */ +#define DAC_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_LPEN_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DMAEN_MASK))) | ( \ + (uint8)((uint8)(State) << DAC_C1_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[Index]. + * @par Example: + * @code + * DAC_PDD_WriteDataLowReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DAC_PDD_WriteDataLowReg(PeripheralBase, Index, Value) ( \ + DAC_DATL_REG(PeripheralBase,(Index)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DATL[Index]. + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadDataLowReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DAC_PDD_ReadDataLowReg(PeripheralBase, Index) ( \ + DAC_DATL_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATH[Index]. + * @par Example: + * @code + * DAC_PDD_WriteDataHighReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DAC_PDD_WriteDataHighReg(PeripheralBase, Index, Value) ( \ + DAC_DATH_REG(PeripheralBase,(Index)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DATH[Index]. + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadDataHighReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DAC_PDD_ReadDataHighReg(PeripheralBase, Index) ( \ + DAC_DATH_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadStatusReg(PeripheralBase) ( \ + DAC_SR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl0Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl0Reg(PeripheralBase, Value) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl0Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl0Reg(PeripheralBase) ( \ + DAC_C0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl1Reg(PeripheralBase) ( \ + DAC_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl2Reg(PeripheralBase) ( \ + DAC_C2_REG(PeripheralBase) \ + ) +#endif /* #if defined(DAC_PDD_H_) */ + +/* DAC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h new file mode 100644 index 0000000..4c794da --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h @@ -0,0 +1,402 @@ +/* + PDD layer implementation for peripheral type DMAMUX + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DMAMUX_PDD_H_) +#define DMAMUX_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DMAMUX PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DMAMUX */ && \ + !defined(MCU_MK10D5) /* DMAMUX */ && \ + !defined(MCU_MK10D7) /* DMAMUX */ && \ + !defined(MCU_MK10F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK10DZ10) /* DMAMUX */ && \ + !defined(MCU_MK11D5) /* DMAMUX */ && \ + !defined(MCU_MK11D5WS) /* DMAMUX */ && \ + !defined(MCU_MK12D5) /* DMAMUX */ && \ + !defined(MCU_MK20D10) /* DMAMUX */ && \ + !defined(MCU_MK20D5) /* DMAMUX */ && \ + !defined(MCU_MK20D7) /* DMAMUX */ && \ + !defined(MCU_MK20F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK20DZ10) /* DMAMUX */ && \ + !defined(MCU_MK21D5) /* DMAMUX */ && \ + !defined(MCU_MK21D5WS) /* DMAMUX */ && \ + !defined(MCU_MK21F12) /* DMAMUX */ && \ + !defined(MCU_MK21F12WS) /* DMAMUX */ && \ + !defined(MCU_MK22D5) /* DMAMUX */ && \ + !defined(MCU_MK22F12810) /* DMAMUX */ && \ + !defined(MCU_MK22F12) /* DMAMUX */ && \ + !defined(MCU_MK22F25612) /* DMAMUX */ && \ + !defined(MCU_MK22F51212) /* DMAMUX */ && \ + !defined(MCU_MK24F12) /* DMAMUX */ && \ + !defined(MCU_MK30D10) /* DMAMUX */ && \ + !defined(MCU_MK30D7) /* DMAMUX */ && \ + !defined(MCU_MK30DZ10) /* DMAMUX */ && \ + !defined(MCU_MK40D10) /* DMAMUX */ && \ + !defined(MCU_MK40D7) /* DMAMUX */ && \ + !defined(MCU_MK40DZ10) /* DMAMUX */ && \ + !defined(MCU_MK40X256VMD100) /* DMAMUX */ && \ + !defined(MCU_MK50D10) /* DMAMUX */ && \ + !defined(MCU_MK50D7) /* DMAMUX */ && \ + !defined(MCU_MK50DZ10) /* DMAMUX */ && \ + !defined(MCU_MK51D10) /* DMAMUX */ && \ + !defined(MCU_MK51D7) /* DMAMUX */ && \ + !defined(MCU_MK51DZ10) /* DMAMUX */ && \ + !defined(MCU_MK52D10) /* DMAMUX */ && \ + !defined(MCU_MK52DZ10) /* DMAMUX */ && \ + !defined(MCU_MK53D10) /* DMAMUX */ && \ + !defined(MCU_MK53DZ10) /* DMAMUX */ && \ + !defined(MCU_MK60D10) /* DMAMUX */ && \ + !defined(MCU_MK60F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK60F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK60DZ10) /* DMAMUX */ && \ + !defined(MCU_MK60N512VMD100) /* DMAMUX */ && \ + !defined(MCU_MK61F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F12WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F15WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK63F12) /* DMAMUX */ && \ + !defined(MCU_MK63F12WS) /* DMAMUX */ && \ + !defined(MCU_MK64F12) /* DMAMUX */ && \ + !defined(MCU_MK65F18) /* DMAMUX */ && \ + !defined(MCU_MK65F18WS) /* DMAMUX */ && \ + !defined(MCU_MK66F18) /* DMAMUX */ && \ + !defined(MCU_MK70F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F12WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F15WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MKL04Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL05Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL14Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL15Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL16Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL24Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL25Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL26Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL34Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL36Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL46Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKV10Z7) /* DMAMUX */ && \ + !defined(MCU_MKV31F12810) /* DMAMUX */ && \ + !defined(MCU_MKV31F25612) /* DMAMUX */ && \ + !defined(MCU_MKV31F51212) /* DMAMUX */ && \ + !defined(MCU_MKW01Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKW21D5) /* DMAMUX */ && \ + !defined(MCU_MKW21D5WS) /* DMAMUX */ && \ + !defined(MCU_MKW22D5) /* DMAMUX */ && \ + !defined(MCU_MKW22D5WS) /* DMAMUX */ && \ + !defined(MCU_MKW24D5) /* DMAMUX */ && \ + !defined(MCU_MKW24D5WS) /* DMAMUX */ && \ + !defined(MCU_PCK20L4) /* DMAMUX */ + // Unsupported MCU is active + #error DMAMUX PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Channel request source constants. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_0 0U /**< Channel request source 0. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_1 0x1U /**< Channel request source 1. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_2 0x2U /**< Channel request source 2. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_3 0x3U /**< Channel request source 3. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_4 0x4U /**< Channel request source 4. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_5 0x5U /**< Channel request source 5. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_6 0x6U /**< Channel request source 6. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_7 0x7U /**< Channel request source 7. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_8 0x8U /**< Channel request source 8. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_9 0x9U /**< Channel request source 9. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_10 0xAU /**< Channel request source 10. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_11 0xBU /**< Channel request source 11. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_12 0xCU /**< Channel request source 12. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_13 0xDU /**< Channel request source 13. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_14 0xEU /**< Channel request source 14. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_15 0xFU /**< Channel request source 15. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_16 0x10U /**< Channel request source 16. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_17 0x11U /**< Channel request source 17. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_18 0x12U /**< Channel request source 18. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_19 0x13U /**< Channel request source 19. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_20 0x14U /**< Channel request source 20. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_21 0x15U /**< Channel request source 21. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_22 0x16U /**< Channel request source 22. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_23 0x17U /**< Channel request source 23. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_24 0x18U /**< Channel request source 24. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_25 0x19U /**< Channel request source 25. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_26 0x1AU /**< Channel request source 26. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_27 0x1BU /**< Channel request source 27. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_28 0x1CU /**< Channel request source 28. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_29 0x1DU /**< Channel request source 29. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_30 0x1EU /**< Channel request source 30. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_31 0x1FU /**< Channel request source 31. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_32 0x20U /**< Channel request source 32. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_33 0x21U /**< Channel request source 33. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_34 0x22U /**< Channel request source 34. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_35 0x23U /**< Channel request source 35. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_36 0x24U /**< Channel request source 36. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_37 0x25U /**< Channel request source 37. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_38 0x26U /**< Channel request source 38. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_39 0x27U /**< Channel request source 39. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_40 0x28U /**< Channel request source 40. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_41 0x29U /**< Channel request source 41. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_42 0x2AU /**< Channel request source 42. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_43 0x2BU /**< Channel request source 43. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_44 0x2CU /**< Channel request source 44. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_45 0x2DU /**< Channel request source 45. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_46 0x2EU /**< Channel request source 46. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_47 0x2FU /**< Channel request source 47. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_48 0x30U /**< Channel request source 48. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_49 0x31U /**< Channel request source 49. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_50 0x32U /**< Channel request source 50. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_51 0x33U /**< Channel request source 51. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_52 0x34U /**< Channel request source 52. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_53 0x35U /**< Channel request source 53. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_54 0x36U /**< Channel request source 54. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_55 0x37U /**< Channel request source 55. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_56 0x38U /**< Channel request source 56. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_57 0x39U /**< Channel request source 57. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_58 0x3AU /**< Channel request source 58. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_59 0x3BU /**< Channel request source 59. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_60 0x3CU /**< Channel request source 60. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_61 0x3DU /**< Channel request source 61. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_62 0x3EU /**< Channel request source 62. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_63 0x3FU /**< Channel request source 63. */ + +/* Channel enabled bit mask */ +#define DMAMUX_PDD_CHANNEL_ENABLED DMAMUX_CHCFG_ENBL_MASK /**< Channel enabled bit mask */ + +/* Trigger enabled bit mask */ +#define DMAMUX_PDD_TRIGGER_ENABLED DMAMUX_CHCFG_TRIG_MASK /**< Trigger enabled bit mask */ + + +/* ---------------------------------------------------------------------------- + -- WriteChannelConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA MUX channel configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA MUX channel configuration register value. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_WriteChannelConfigurationReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMAMUX_PDD_WriteChannelConfigurationReg(PeripheralBase, Channel, Value) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = + * DMAMUX_PDD_ReadChannelConfigurationReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMAMUX_PDD_ReadChannelConfigurationReg(PeripheralBase, Channel) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA MUX channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA MUX channel will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_EnableChannel(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define DMAMUX_PDD_EnableChannel(PeripheralBase, Channel, State) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_ENBL_MASK)))) | ( \ + (uint8)((uint8)(State) << DMAMUX_CHCFG_ENBL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetChannelEnabled(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetChannelEnabled(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_ENBL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA MUX channel triggering. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA MUX channel triggering will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_EnableTrigger(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define DMAMUX_PDD_EnableTrigger(PeripheralBase, Channel, State) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_TRIG_MASK)))) | ( \ + (uint8)((uint8)(State) << DMAMUX_CHCFG_TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel triggering state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetTriggerEnabled(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetTriggerEnabled(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_TRIG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelSource DMA channel source number. This parameter is a 6-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_SetChannelSource(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMAMUX_PDD_SetChannelSource(PeripheralBase, Channel, ChannelSource) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_SOURCE_MASK)))) | ( \ + (uint8)(ChannelSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of enabled DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetChannelSource(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetChannelSource(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_SOURCE_MASK) \ + ) +#endif /* #if defined(DMAMUX_PDD_H_) */ + +/* DMAMUX_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h new file mode 100644 index 0000000..912199b --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h @@ -0,0 +1,7966 @@ +/* + PDD layer implementation for peripheral type DMA + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DMA_PDD_H_) +#define DMA_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DMA PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DMA */ && \ + !defined(MCU_MK10D5) /* DMA */ && \ + !defined(MCU_MK10D7) /* DMA */ && \ + !defined(MCU_MK10F12) /* DMA */ && \ + !defined(MCU_MK10DZ10) /* DMA */ && \ + !defined(MCU_MK11D5) /* DMA */ && \ + !defined(MCU_MK11D5WS) /* DMA */ && \ + !defined(MCU_MK12D5) /* DMA */ && \ + !defined(MCU_MK20D10) /* DMA */ && \ + !defined(MCU_MK20D5) /* DMA */ && \ + !defined(MCU_MK20D7) /* DMA */ && \ + !defined(MCU_MK20F12) /* DMA */ && \ + !defined(MCU_MK20DZ10) /* DMA */ && \ + !defined(MCU_MK21D5) /* DMA */ && \ + !defined(MCU_MK21D5WS) /* DMA */ && \ + !defined(MCU_MK21F12) /* DMA */ && \ + !defined(MCU_MK21F12WS) /* DMA */ && \ + !defined(MCU_MK22D5) /* DMA */ && \ + !defined(MCU_MK22F12810) /* DMA */ && \ + !defined(MCU_MK22F12) /* DMA */ && \ + !defined(MCU_MK22F25612) /* DMA */ && \ + !defined(MCU_MK22F51212) /* DMA */ && \ + !defined(MCU_MK24F12) /* DMA */ && \ + !defined(MCU_MK30D10) /* DMA */ && \ + !defined(MCU_MK30D7) /* DMA */ && \ + !defined(MCU_MK30DZ10) /* DMA */ && \ + !defined(MCU_MK40D10) /* DMA */ && \ + !defined(MCU_MK40D7) /* DMA */ && \ + !defined(MCU_MK40DZ10) /* DMA */ && \ + !defined(MCU_MK40X256VMD100) /* DMA */ && \ + !defined(MCU_MK50D10) /* DMA */ && \ + !defined(MCU_MK50D7) /* DMA */ && \ + !defined(MCU_MK50DZ10) /* DMA */ && \ + !defined(MCU_MK51D10) /* DMA */ && \ + !defined(MCU_MK51D7) /* DMA */ && \ + !defined(MCU_MK51DZ10) /* DMA */ && \ + !defined(MCU_MK52D10) /* DMA */ && \ + !defined(MCU_MK52DZ10) /* DMA */ && \ + !defined(MCU_MK53D10) /* DMA */ && \ + !defined(MCU_MK53DZ10) /* DMA */ && \ + !defined(MCU_MK60D10) /* DMA */ && \ + !defined(MCU_MK60F12) /* DMA */ && \ + !defined(MCU_MK60F15) /* DMA */ && \ + !defined(MCU_MK60DZ10) /* DMA */ && \ + !defined(MCU_MK60N512VMD100) /* DMA */ && \ + !defined(MCU_MK61F12) /* DMA */ && \ + !defined(MCU_MK61F15) /* DMA */ && \ + !defined(MCU_MK61F12WS) /* DMA */ && \ + !defined(MCU_MK61F15WS) /* DMA */ && \ + !defined(MCU_MK63F12) /* DMA */ && \ + !defined(MCU_MK63F12WS) /* DMA */ && \ + !defined(MCU_MK64F12) /* DMA */ && \ + !defined(MCU_MK65F18) /* DMA */ && \ + !defined(MCU_MK65F18WS) /* DMA */ && \ + !defined(MCU_MK66F18) /* DMA */ && \ + !defined(MCU_MK70F12) /* DMA */ && \ + !defined(MCU_MK70F15) /* DMA */ && \ + !defined(MCU_MK70F12WS) /* DMA */ && \ + !defined(MCU_MK70F15WS) /* DMA */ && \ + !defined(MCU_MKL04Z4) /* DMA */ && \ + !defined(MCU_MKL05Z4) /* DMA */ && \ + !defined(MCU_MKL14Z4) /* DMA */ && \ + !defined(MCU_MKL15Z4) /* DMA */ && \ + !defined(MCU_MKL16Z4) /* DMA */ && \ + !defined(MCU_MKL24Z4) /* DMA */ && \ + !defined(MCU_MKL25Z4) /* DMA */ && \ + !defined(MCU_MKL26Z4) /* DMA */ && \ + !defined(MCU_MKL34Z4) /* DMA */ && \ + !defined(MCU_MKL36Z4) /* DMA */ && \ + !defined(MCU_MKL46Z4) /* DMA */ && \ + !defined(MCU_MKV10Z7) /* DMA */ && \ + !defined(MCU_MKV31F12810) /* DMA */ && \ + !defined(MCU_MKV31F25612) /* DMA */ && \ + !defined(MCU_MKV31F51212) /* DMA */ && \ + !defined(MCU_MKW01Z4) /* DMA */ && \ + !defined(MCU_MKW21D5) /* DMA */ && \ + !defined(MCU_MKW21D5WS) /* DMA */ && \ + !defined(MCU_MKW22D5) /* DMA */ && \ + !defined(MCU_MKW22D5WS) /* DMA */ && \ + !defined(MCU_MKW24D5) /* DMA */ && \ + !defined(MCU_MKW24D5WS) /* DMA */ && \ + !defined(MCU_PCK20L4) /* DMA */ + // Unsupported MCU is active + #error DMA PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* DMA channel constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_4 0x4U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_5 0x5U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_6 0x6U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_7 0x7U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_8 0x8U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_9 0x9U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_10 0xAU /**< Channel 10. */ + #define DMA_PDD_CHANNEL_11 0xBU /**< Channel 11. */ + #define DMA_PDD_CHANNEL_12 0xCU /**< Channel 12. */ + #define DMA_PDD_CHANNEL_13 0xDU /**< Channel 13. */ + #define DMA_PDD_CHANNEL_14 0xEU /**< Channel 14. */ + #define DMA_PDD_CHANNEL_15 0xFU /**< Channel 15. */ + #define DMA_PDD_CHANNEL_16 0x10U /**< Channel 16. */ + #define DMA_PDD_CHANNEL_17 0x11U /**< Channel 17. */ + #define DMA_PDD_CHANNEL_18 0x12U /**< Channel 18. */ + #define DMA_PDD_CHANNEL_19 0x13U /**< Channel 19. */ + #define DMA_PDD_CHANNEL_20 0x14U /**< Channel 20. */ + #define DMA_PDD_CHANNEL_21 0x15U /**< Channel 21. */ + #define DMA_PDD_CHANNEL_22 0x16U /**< Channel 22. */ + #define DMA_PDD_CHANNEL_23 0x17U /**< Channel 23. */ + #define DMA_PDD_CHANNEL_24 0x18U /**< Channel 24. */ + #define DMA_PDD_CHANNEL_25 0x19U /**< Channel 25. */ + #define DMA_PDD_CHANNEL_26 0x1AU /**< Channel 26. */ + #define DMA_PDD_CHANNEL_27 0x1BU /**< Channel 27. */ + #define DMA_PDD_CHANNEL_28 0x1CU /**< Channel 28. */ + #define DMA_PDD_CHANNEL_29 0x1DU /**< Channel 29. */ + #define DMA_PDD_CHANNEL_30 0x1EU /**< Channel 30. */ + #define DMA_PDD_CHANNEL_31 0x1FU /**< Channel 31. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_4 0x4U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_5 0x5U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_6 0x6U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_7 0x7U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_8 0x8U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_9 0x9U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_10 0xAU /**< Channel 10. */ + #define DMA_PDD_CHANNEL_11 0xBU /**< Channel 11. */ + #define DMA_PDD_CHANNEL_12 0xCU /**< Channel 12. */ + #define DMA_PDD_CHANNEL_13 0xDU /**< Channel 13. */ + #define DMA_PDD_CHANNEL_14 0xEU /**< Channel 14. */ + #define DMA_PDD_CHANNEL_15 0xFU /**< Channel 15. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_MASK_4 0x10U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_MASK_5 0x20U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_MASK_6 0x40U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_MASK_7 0x80U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_MASK_8 0x100U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_MASK_9 0x200U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_MASK_10 0x400U /**< Channel 10. */ + #define DMA_PDD_CHANNEL_MASK_11 0x800U /**< Channel 11. */ + #define DMA_PDD_CHANNEL_MASK_12 0x1000U /**< Channel 12. */ + #define DMA_PDD_CHANNEL_MASK_13 0x2000U /**< Channel 13. */ + #define DMA_PDD_CHANNEL_MASK_14 0x4000U /**< Channel 14. */ + #define DMA_PDD_CHANNEL_MASK_15 0x8000U /**< Channel 15. */ + #define DMA_PDD_CHANNEL_MASK_16 0x10000U /**< Channel 16. */ + #define DMA_PDD_CHANNEL_MASK_17 0x20000U /**< Channel 17. */ + #define DMA_PDD_CHANNEL_MASK_18 0x40000U /**< Channel 18. */ + #define DMA_PDD_CHANNEL_MASK_19 0x80000U /**< Channel 19. */ + #define DMA_PDD_CHANNEL_MASK_20 0x100000U /**< Channel 20. */ + #define DMA_PDD_CHANNEL_MASK_21 0x200000U /**< Channel 21. */ + #define DMA_PDD_CHANNEL_MASK_22 0x400000U /**< Channel 22. */ + #define DMA_PDD_CHANNEL_MASK_23 0x800000U /**< Channel 23. */ + #define DMA_PDD_CHANNEL_MASK_24 0x1000000U /**< Channel 24. */ + #define DMA_PDD_CHANNEL_MASK_25 0x2000000U /**< Channel 25. */ + #define DMA_PDD_CHANNEL_MASK_26 0x4000000U /**< Channel 26. */ + #define DMA_PDD_CHANNEL_MASK_27 0x8000000U /**< Channel 27. */ + #define DMA_PDD_CHANNEL_MASK_28 0x10000000U /**< Channel 28. */ + #define DMA_PDD_CHANNEL_MASK_29 0x20000000U /**< Channel 29. */ + #define DMA_PDD_CHANNEL_MASK_30 0x40000000U /**< Channel 30. */ + #define DMA_PDD_CHANNEL_MASK_31 0x80000000U /**< Channel 31. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_MASK_4 0x10U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_MASK_5 0x20U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_MASK_6 0x40U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_MASK_7 0x80U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_MASK_8 0x100U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_MASK_9 0x200U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_MASK_10 0x400U /**< Channel 10. */ + #define DMA_PDD_CHANNEL_MASK_11 0x800U /**< Channel 11. */ + #define DMA_PDD_CHANNEL_MASK_12 0x1000U /**< Channel 12. */ + #define DMA_PDD_CHANNEL_MASK_13 0x2000U /**< Channel 13. */ + #define DMA_PDD_CHANNEL_MASK_14 0x4000U /**< Channel 14. */ + #define DMA_PDD_CHANNEL_MASK_15 0x8000U /**< Channel 15. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel major loop linking disabled bit mask */ +#define DMA_PDD_MAJOR_LINK_DISABLED 0U /**< Channel major loop linking disabled */ + +/* Channel major loop linking enabled bit mask */ +#define DMA_PDD_MAJOR_LINK_ENABLED DMA_CSR_MAJORELINK_MASK /**< Channel major loop linking enabled */ + +/* Channel scatter/gather disabled bit mask */ +#define DMA_PDD_SCATTER_GATHER_DISABLED 0U /**< Channel scatter/gather disabled */ + +/* Channel scatter/gather enabled bit mask */ +#define DMA_PDD_SCATTER_GATHER_ENABLED DMA_CSR_ESG_MASK /**< Channel scatter/gather enabled */ + +/* Enable channel after request bit mask */ +#define DMA_PDD_ENABLE_AFTER_REQUEST 0U /**< Enable channel after request */ + +/* Disable channel after request bit mask */ +#define DMA_PDD_DISABLE_AFTER_REQUEST DMA_CSR_DREQ_MASK /**< Disable channel after request */ + +/* Minor loop offset bit position value */ +#define DMA_PDD_MINOR_LOOP_OFFSET_SHIFT 0U /**< Minor loop offset bit position value. */ + +/* Minor loop enable bit position value */ +#define DMA_PDD_MINOR_LOOP_ENABLE_SHIFT 0x1EU /**< Minor loop enable bit position value. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Channel error status constants */ + #define DMA_PDD_CONFIGURATION_ERROR_FLAG DMA_DSR_BCR_CE_MASK /**< Configuration error flag. */ + #define DMA_PDD_ERROR_ON_SOURCE_FLAG DMA_DSR_BCR_BES_MASK /**< Error on source side flag. */ + #define DMA_PDD_ERROR_ON_DESTINATION_FLAG DMA_DSR_BCR_BED_MASK /**< Error on destination side flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel-related error flags. Bit mask of flags associated with specific + channel (use GetErrorStatusChannel to obtain associated channel number). */ + #define DMA_PDD_CHANNEL_ERROR_FLAGS 0x100FFU /**< All channel-related error flags mask. */ + #define DMA_PDD_ERROR_TRANSFER_CANCELED_FLAG DMA_ES_ECX_MASK /**< Canceled transfer by the error cancel transfer input. */ + #define DMA_PDD_ERROR_SOURCE_ADDRESS_FLAG DMA_ES_SAE_MASK /**< Source address error. */ + #define DMA_PDD_ERROR_SOURCE_OFFSET_FLAG DMA_ES_SOE_MASK /**< Source offset error. */ + #define DMA_PDD_ERROR_DESTINATION_ADDRESS_FLAG DMA_ES_DAE_MASK /**< Destination address error. */ + #define DMA_PDD_ERROR_DESTINATION_OFFSET_FLAG DMA_ES_DOE_MASK /**< Source offset error. */ + #define DMA_PDD_ERROR_COUNT_FLAG DMA_ES_NCE_MASK /**< Error detected in minor loop byte count or major loop iteration count. */ + #define DMA_PDD_ERROR_SCATTER_GATHER_FLAG DMA_ES_SGE_MASK /**< Scatter/gather configuration error. */ + #define DMA_PDD_ERROR_ON_SOURCE_FLAG DMA_ES_SBE_MASK /**< Error on source side flag. */ + #define DMA_PDD_ERROR_ON_DESTINATION_FLAG DMA_ES_DBE_MASK /**< Error on destination side flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* Device-related error flags. Bit mask of flags associated with whole DMA + device or multiple channels. */ + #define DMA_PDD_DEVICE_ERROR_FLAGS 0xC000U /**< All device-related error flags mask. */ + #define DMA_PDD_ERROR_CHANNEL_PRIORITY_FLAG DMA_ES_CPE_MASK /**< Configuration error in the channel priorities (channel priorities are not unique). */ + #define DMA_PDD_ERROR_GROUP_PRIORITY_FLAG DMA_ES_GPE_MASK /**< Configuration error in the group priorities (group priorities are not unique). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Device-related error flags. Bit mask of flags associated with whole DMA + device or multiple channels. */ + #define DMA_PDD_DEVICE_ERROR_FLAGS 0x4000U /**< All device-related error flags mask. */ + #define DMA_PDD_ERROR_CHANNEL_PRIORITY_FLAG DMA_ES_CPE_MASK /**< Configuration error in the channel priorities (channel priorities are not unique). */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Constants used in SetChannelPriority */ +#define DMA_PDD_DCHPRI_DPA_MASK DMA_DCHPRI3_DPA_MASK /**< Disable preempt ability bit mask. */ +#define DMA_PDD_DCHPRI_CHPRI_MASK DMA_DCHPRI3_CHPRI_MASK /**< Channel arbitration priority bit group mask. */ +#define DMA_PDD_DCHPRI_ECP_SHIFT 0x7U /**< Enable channel preemption bit position. */ +#define DMA_PDD_DCHPRI_CHPRI_SHIFT 0U /**< Channel arbitration priority bit group position. */ + +/* Constant specifying if DMA channel can be temporarily suspended by the + service request of a higher priority channel */ +#define DMA_PDD_CHANNEL_CAN_BE_PREEMPTED 0U /**< Channel can be preempted. */ +#define DMA_PDD_CHANNEL_CANNOT_BE_PREEMPTED DMA_DCHPRI3_ECP_MASK /**< Channel can't be preempted. */ + +/* Constant specifying if DMA channel can suspend a lower priority channel */ +#define DMA_PDD_CHANNEL_CAN_PREEMPT_OTHER 0U /**< Channel can suspend other channels. */ +#define DMA_PDD_CHANNEL_CANNOT_PREEMPT_OTHER DMA_DCHPRI3_DPA_MASK /**< Channel can't suspend other channels. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Circular buffer size constants */ + #define DMA_PDD_CIRCULAR_BUFFER_DISABLED 0U /**< Circular buffer disabled. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_BYTES 0x1U /**< 16 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_BYTES 0x2U /**< 32 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_BYTES 0x3U /**< 64 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_BYTES 0x4U /**< 128 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_BYTES 0x5U /**< 256 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_BYTES 0x6U /**< 512 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_KBYTE 0x7U /**< 1 Kbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_KBYTES 0x8U /**< 2 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_KBYTES 0x9U /**< 4 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_KBYTES 0xAU /**< 8 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_KBYTES 0xBU /**< 16 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_KBYTES 0xCU /**< 32 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_KBYTES 0xDU /**< 64 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_KBYTES 0xEU /**< 128 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_KBYTES 0xFU /**< 256 Kbytes circular buffer. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Circular buffer size constants */ + #define DMA_PDD_CIRCULAR_BUFFER_DISABLED 0U /**< Circular buffer disabled. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_BYTES 0x1U /**< 2 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_BYTES 0x2U /**< 4 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_BYTES 0x3U /**< 8 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_BYTES 0x4U /**< 16 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_BYTES 0x5U /**< 32 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_BYTES 0x6U /**< 64 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_BYTES 0x7U /**< 128 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_BYTES 0x8U /**< 256 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_BYTES 0x9U /**< 512 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_KBYTE 0xAU /**< 1 Kbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_KBYTES 0xBU /**< 2 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_KBYTES 0xCU /**< 4 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_KBYTES 0xDU /**< 8 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_KBYTES 0xEU /**< 16 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_KBYTES 0xFU /**< 32 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_KBYTES 0x10U /**< 64 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_KBYTES 0x11U /**< 128 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_KBYTES 0x12U /**< 256 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_KBYTES 0x13U /**< 512 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_MBYTE 0x14U /**< 1 Mbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_MBYTES 0x15U /**< 2 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_MBYTES 0x16U /**< 4 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_MBYTES 0x17U /**< 8 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_MBYTES 0x18U /**< 16 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_MBYTES 0x19U /**< 32 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_MBYTES 0x1AU /**< 64 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_MBYTES 0x1BU /**< 128 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_MBYTES 0x1CU /**< 256 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_MBYTES 0x1DU /**< 512 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_GBYTE 0x1EU /**< 1 Gbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_GBYTES 0x1FU /**< 2 Gbytes circular buffer. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Channel activity status constants */ + #define DMA_PDD_TRANSFER_DONE_FLAG DMA_DSR_BCR_DONE_MASK /**< Transfer done flag. */ + #define DMA_PDD_TRANSFER_BUSY_FLAG DMA_DSR_BCR_BSY_MASK /**< Transfer in progress flag. */ + #define DMA_PDD_TRANSFER_REQUEST_PENDING_FLAG DMA_DSR_BCR_REQ_MASK /**< Transfer request pending flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel activity status constants */ + #define DMA_PDD_TRANSFER_DONE_FLAG DMA_CSR_DONE_MASK /**< Transfer done flag. */ + #define DMA_PDD_TRANSFER_ACTIVE_FLAG DMA_CSR_ACTIVE_MASK /**< Transfer in progress flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Transfer complete interrupt enable/disable constants */ + #define DMA_PDD_TRANSFER_COMPLETE_ENABLE DMA_DCR_EINT_MASK /**< Transfer complete interrupt enabled. */ + #define DMA_PDD_TRANSFER_COMPLETE_DISABLE 0U /**< Transfer complete interrupt disabled. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Transfer complete interrupt enable/disable constants */ + #define DMA_PDD_TRANSFER_COMPLETE_ENABLE DMA_CSR_INTMAJOR_MASK /**< Transfer complete interrupt enabled. */ + #define DMA_PDD_TRANSFER_COMPLETE_DISABLE 0U /**< Transfer complete interrupt disabled. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' mask */ +#define DMA_PDD_TRANSFER_COMPLETE_INTERRUPT DMA_DCR_EINT_MASK /**< Transfer complete interrupt mask. */ + +/* Interrupts' flags */ +#define DMA_PDD_TRANSFER_COMPLETE_FLAG DMA_DSR_BCR_DONE_MASK /**< Transfer complete flag. */ + +/* Channel request source constants */ +#define DMA_PDD_CHANNEL_SOURCE_0 0U /**< Channel request source 0. */ +#define DMA_PDD_CHANNEL_SOURCE_1 0x1U /**< Channel request source 1. */ +#define DMA_PDD_CHANNEL_SOURCE_2 0x2U /**< Channel request source 2. */ +#define DMA_PDD_CHANNEL_SOURCE_3 0x3U /**< Channel request source 3. */ +#define DMA_PDD_CHANNEL_SOURCE_4 0x4U /**< Channel request source 4. */ +#define DMA_PDD_CHANNEL_SOURCE_5 0x5U /**< Channel request source 5. */ +#define DMA_PDD_CHANNEL_SOURCE_6 0x6U /**< Channel request source 6. */ +#define DMA_PDD_CHANNEL_SOURCE_7 0x7U /**< Channel request source 7. */ +#define DMA_PDD_CHANNEL_SOURCE_8 0x8U /**< Channel request source 8. */ +#define DMA_PDD_CHANNEL_SOURCE_9 0x9U /**< Channel request source 9. */ +#define DMA_PDD_CHANNEL_SOURCE_10 0xAU /**< Channel request source 10. */ +#define DMA_PDD_CHANNEL_SOURCE_11 0xBU /**< Channel request source 11. */ +#define DMA_PDD_CHANNEL_SOURCE_12 0xCU /**< Channel request source 12. */ +#define DMA_PDD_CHANNEL_SOURCE_13 0xDU /**< Channel request source 13. */ +#define DMA_PDD_CHANNEL_SOURCE_14 0xEU /**< Channel request source 14. */ +#define DMA_PDD_CHANNEL_SOURCE_15 0xFU /**< Channel request source 15. */ + +/* Set all or only one DMA channel. Used in Set/Clear macros to distinct between + setting/clearing attribute of one specified channel or of all channels. */ +#define DMA_PDD_ONE_CHANNEL 0U /**< Set only one DMA channel. */ +#define DMA_PDD_ALL_CHANNELS DMA_SERQ_SAER_MASK /**< Set all DMA channels. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0x1U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x2U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0U /**< 32-bit transfer size. */ + +#elif ((defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x1U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0x2U /**< 32-bit transfer size. */ + #define DMA_PDD_16_BYTE 0x4U /**< 16-byte transfer size. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x1U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0x2U /**< 32-bit transfer size. */ + #define DMA_PDD_16_BYTE 0x4U /**< 16-byte transfer size. */ + #define DMA_PDD_32_BYTE 0x5U /**< 32-byte transfer size. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA stall time value. */ +#define DMA_PDD_NO_STALL 0U /**< No stall. */ +#define DMA_PDD_STALL_4_CYCLES 0x8000U /**< Stall 4 cycles. */ +#define DMA_PDD_STALL_8_CYCLES 0xC000U /**< Stall 8 cycles. */ + +/* DMA data transfer size. */ +#define DMA_PDD_LINKING_DISABLED 0U /**< Channel linking disabled. */ +#define DMA_PDD_CYCLE_STEAL_AND_TRANSFER_COMPLETE_LINKING 0x10U /**< Channel linked after each cycle-steal transfer and after transfer complete. */ +#define DMA_PDD_CYCLE_STEAL_LINKING 0x20U /**< Channel linked only after each cycle-steal transfer. */ +#define DMA_PDD_TRANSFER_COMPLETE_LINKING 0x30U /**< Channel linked only after transfer complete. */ + + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Writes to DMA channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel control register value. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_WriteControlReg(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ + #define DMA_PDD_WriteControlReg(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Writes to DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA control register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_WriteControlReg(PeripheralBase, Value) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadControlReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_ReadControlReg(PeripheralBase, Channel) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_ReadControlReg(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- CancelTransfer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Cancels remaining data transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DSR_BCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_CancelTransfer(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_CancelTransfer(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DSR_BCR_DONE_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Cancels remaining data transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DSR_BCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_CancelTransfer(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_CancelTransfer(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_CX_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ErrorCancelTransfer + ---------------------------------------------------------------------------- */ + +/** + * @brief Cancels remaining data transfer with error generation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_ErrorCancelTransfer(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ErrorCancelTransfer(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_ECX_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMinorLoopMapping + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables minor loop mapping. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if minor loop mapping will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableMinorLoopMapping(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableMinorLoopMapping(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_EMLM_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_EMLM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopMappingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minor loop mapping state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetMinorLoopMappingEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetMinorLoopMappingEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_EMLM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousLinkMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables minor loop continuous link mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if minor loop continuous link mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableContinuousLinkMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableContinuousLinkMode(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_CLM_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_CLM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetContinuousLinkModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minor loop continuous link mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetContinuousLinkModeEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetContinuousLinkModeEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_CLM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- HaltOperations + ---------------------------------------------------------------------------- */ + +/** + * @brief Halts DMA operations. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_HaltOperations(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_HaltOperations(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_HALT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResumeOperations + ---------------------------------------------------------------------------- */ + +/** + * @brief Resumes halted DMA operations. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_ResumeOperations(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ResumeOperations(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)DMA_CR_HALT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHaltOnError + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables stalling of DMA operations after error occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if error occurance halts DMA operations. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableHaltOnError(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableHaltOnError(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_HOE_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_HOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetHaltOnErrorEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA operations halt on error state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetHaltOnErrorEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetHaltOnErrorEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_HOE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRoundRobinArbitration + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables round robin channel arbitration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if round robin channel arbitration is + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableRoundRobinArbitration(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableRoundRobinArbitration(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_ERCA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_ERCA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRoundRobinArbitrationEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns round robin channel arbitration state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRoundRobinArbitrationEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRoundRobinArbitrationEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_ERCA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDebug + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA operations in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA operations in debug mode are enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableDebug(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDebug(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_EDBG_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_EDBG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDebugEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA operations in debug mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDebugEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetDebugEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_EDBG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadErrorStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel error status register provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadErrorStatusReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadErrorStatusReg(PeripheralBase) ( \ + DMA_ES_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use ReadErrorStatusReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusRegister(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorStatusRegister(PeripheralBase) ( \ + DMA_ES_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel error status flags provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusFlags(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusFlags(PeripheralBase) ( \ + (uint32)(( \ + DMA_ES_REG(PeripheralBase)) & ( \ + (uint32)(( \ + DMA_ES_ECX_MASK) | (( \ + DMA_ES_GPE_MASK) | (( \ + DMA_ES_CPE_MASK) | (( \ + DMA_ES_SAE_MASK) | (( \ + DMA_ES_SOE_MASK) | (( \ + DMA_ES_DAE_MASK) | (( \ + DMA_ES_DOE_MASK) | (( \ + DMA_ES_NCE_MASK) | (( \ + DMA_ES_SGE_MASK) | (( \ + DMA_ES_SBE_MASK) | ( \ + DMA_ES_DBE_MASK))))))))))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel error status flags provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusFlags(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusFlags(PeripheralBase) ( \ + (uint32)(( \ + DMA_ES_REG(PeripheralBase)) & ( \ + (uint32)(( \ + DMA_ES_ECX_MASK) | (( \ + DMA_ES_CPE_MASK) | (( \ + DMA_ES_SAE_MASK) | (( \ + DMA_ES_SOE_MASK) | (( \ + DMA_ES_DAE_MASK) | (( \ + DMA_ES_DOE_MASK) | (( \ + DMA_ES_NCE_MASK) | (( \ + DMA_ES_SGE_MASK) | (( \ + DMA_ES_SBE_MASK) | ( \ + DMA_ES_DBE_MASK)))))))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteChannelPriorityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteChannelPriorityReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteChannelPriorityReg(PeripheralBase, Channel, Value) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) = (uint8)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelPriorityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = DMA_PDD_ReadChannelPriorityReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadChannelPriorityReg(PeripheralBase, Channel) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- DCHPRI_REG + ---------------------------------------------------------------------------- */ + +/** + * @brief SetChannelPriority channel parameter conversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_DCHPRI_REG(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) ( \ + (&DMA_DCHPRI3_REG(PeripheralBase))[Channel^3U] \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @param EnablePreemption Parameter specifying if DMA channel can be + * temporarily suspended by the service request of a higher priority channel. This + * parameter is a 8-bit value. + * @param EnablePreemptAbility Parameter specifying if DMA channel can suspend a + * lower priority channel. This parameter is a 8-bit value. + * @param Priority Data word value. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_SetChannelPriority(_BASE_PTR, periphID, 1, 1, 1); + * @endcode + */ +#define DMA_PDD_SetChannelPriority(PeripheralBase, Channel, EnablePreemption, EnablePreemptAbility, Priority) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) = ( \ + (EnablePreemptAbility) ? ( \ + (uint8)((uint8)(EnablePreemption) << DMA_DCHPRI3_ECP_SHIFT) | \ + (uint8)((((uint8)(Priority) & DMA_DCHPRI3_CHPRI_MASK) << DMA_DCHPRI3_CHPRI_SHIFT)) \ + ) : ( \ + (uint8)((uint8)(EnablePreemption) << DMA_DCHPRI3_ECP_SHIFT) | \ + (uint8)((((uint8)(Priority) & DMA_DCHPRI3_CHPRI_MASK) << DMA_DCHPRI3_CHPRI_SHIFT)) | \ + (DMA_DCHPRI3_DPA_MASK) \ + ) \ + )) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableRegs + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set/clear error interrupts and channel requests enable + * registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA control registers value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteEnableRegs(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableRegs(PeripheralBase, Value) ( \ + DMA_CEEI_REG(PeripheralBase) = (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlagRegs + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear done status, clear error and interrupt flags and + * set start channel request registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA flag registers value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteFlagRegs(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteFlagRegs(PeripheralBase, Value) ( \ + DMA_CDNE_REG(PeripheralBase) = (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_WriteEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableRequestReg(PeripheralBase, Value) ( \ + DMA_ERQ_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadEnableRequestReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableRequestReg(PeripheralBase) ( \ + DMA_ERQ_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRequestMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels requests specified by Mask parameter, rest is not + * changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_EnableRequestMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableRequestMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRequestMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels requests specified by Mask parameter, rest is + * not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be disabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_DisableRequestMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableRequestMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRequestEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnableMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetRequestEnableMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of enabled DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestEnableMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRequestEnableMask(PeripheralBase) ( \ + DMA_ERQ_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_WriteSetEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetEnableRequestReg(PeripheralBase, Value) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRequestEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channel peripheral request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_EnableRequest(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableRequest(PeripheralBase, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_WriteClearEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearEnableRequestReg(PeripheralBase, Value) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channel peripheral request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_DisableRequest(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableRequest(PeripheralBase, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearRequestEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePeripheralRequest + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables peripheral requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel peripheral requests will be + * enabled or ignored. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ, DMA_SERQ, + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnablePeripheralRequest(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnablePeripheralRequest(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_ERQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_ERQ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables peripheral requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @param State Parameter specifying if DMA channel peripheral requests will be + * enabled or ignored. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ, DMA_SERQ, + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnablePeripheralRequest(_BASE_PTR, 1, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnablePeripheralRequest(PeripheralBase, Channel, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Channel)) : ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_WriteEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_EEI_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadEnableErrorInterruptReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableErrorInterruptReg(PeripheralBase) ( \ + DMA_EEI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels error interrupts specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be enabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_EnableErrorInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableErrorInterruptMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels error interrupts specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be disabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_DisableErrorInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableErrorInterruptMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be enabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnableMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetErrorInterruptEnableMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetErrorInterruptEnableMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorInterruptEnableMask(PeripheralBase) ( \ + DMA_EEI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_WriteSetEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channel error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_EnableErrorInterrupt(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableErrorInterrupt(PeripheralBase, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_WriteClearEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorInterruptEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channel error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_DisableErrorInterrupt(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableErrorInterrupt(PeripheralBase, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT. + * @par Example: + * @code + * DMA_PDD_WriteClearInterruptRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearInterruptRequestReg(PeripheralBase, Value) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_FLAG); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, Channel, Mask) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + (uint32)(Mask) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT. + * @par Example: + * @code + * DMA_PDD_ClearChannelInterruptFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearChannelInterruptFlag(PeripheralBase, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * DMA_PDD_WriteInterruptRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteInterruptRequestReg(PeripheralBase, Value) ( \ + DMA_INT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadInterruptRequestReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadInterruptRequestReg(PeripheralBase) ( \ + DMA_INT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channels interrupt requests specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA interrupt requests to be cleared. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlagsMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearInterruptFlagsMask(PeripheralBase, Mask) ( \ + DMA_INT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels interrupt requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetInterruptFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetInterruptFlagsMask(PeripheralBase) ( \ + DMA_INT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear error register register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_WriteClearErrorReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearErrorReg(PeripheralBase, Value) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channel error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearChannelErrorFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearChannelErrorFlag(PeripheralBase, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA error register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * DMA_PDD_WriteErrorReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteErrorReg(PeripheralBase, Value) ( \ + DMA_ERR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA error register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadErrorReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadErrorReg(PeripheralBase) ( \ + DMA_ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channels error flags specified by Mask parameter, rest is + * not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA errors to be cleared. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlagsMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearErrorFlagsMask(PeripheralBase, Mask) ( \ + DMA_ERR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channel error flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorFlagsMask(PeripheralBase) ( \ + DMA_ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetChannelErrorFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_GetChannelErrorFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_ERR_REG(PeripheralBase) & (uint32)((uint32)0x1U << (uint8)(Channel))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetStartBitReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set START bit register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT. + * @par Example: + * @code + * DMA_PDD_WriteSetStartBitReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetStartBitReg(PeripheralBase, Value) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartTransfer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, Channel) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DCR_START_MASK \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteClearDoneBitReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear DONE status bit register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_WriteClearDoneBitReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearDoneBitReg(PeripheralBase, Value) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDoneFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearDoneFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Clears channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CDNE, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ClearDoneFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_ClearDoneFlag(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DSR_BCR_DONE_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearDoneFlag(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlag(PeripheralBase, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteHwRequestStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA hardware request status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * DMA_PDD_WriteHwRequestStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteHwRequestStatusReg(PeripheralBase, Value) ( \ + DMA_HRS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHwRequestStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA hardware request status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadHwRequestStatusReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadHwRequestStatusReg(PeripheralBase) ( \ + DMA_HRS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels requests status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRequestFlagsMask(PeripheralBase) ( \ + DMA_HRS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSourceAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD source address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteSourceAddressReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteSourceAddressReg(PeripheralBase, Channel, Value) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSourceAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD source address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadSourceAddressReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadSourceAddressReg(PeripheralBase, Channel) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Address DMA channel source address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddress(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddress(PeripheralBase, Channel, Address) ( \ + DMA_SAR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Address DMA channel source address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddress(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddress(PeripheralBase, Channel, Address) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetSourceAddress(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceAddress(PeripheralBase, Channel) ( \ + DMA_SAR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetSourceAddress(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetSourceAddress(PeripheralBase, Channel) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteDestinationAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD destination address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteDestinationAddressReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteDestinationAddressReg(PeripheralBase, Channel, Value) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDestinationAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD destination address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadDestinationAddressReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadDestinationAddressReg(PeripheralBase, Channel) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Address DMA channel destination address. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddress(_BASE_PTR, DMA_PDD_CHANNEL_0, + * 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddress(PeripheralBase, Channel, Address) ( \ + DMA_DAR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Address DMA channel destination address. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddress(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddress(PeripheralBase, Channel, Address) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDestinationAddress(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationAddress(PeripheralBase, Channel) ( \ + DMA_DAR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDestinationAddress(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationAddress(PeripheralBase, Channel) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteSourceAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD source address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteSourceAddressOffsetReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteSourceAddressOffsetReg(PeripheralBase, Channel, Value) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSourceAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD source address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadSourceAddressOffsetReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadSourceAddressOffsetReg(PeripheralBase, Channel) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel source address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Offset DMA channel source address offset. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_SetSourceAddressOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetSourceAddressOffset(PeripheralBase, Channel, Offset) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Offset) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel source address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_GetSourceAddressOffset(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetSourceAddressOffset(PeripheralBase, Channel) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDestinationAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD destination address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteDestinationAddressOffsetReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteDestinationAddressOffsetReg(PeripheralBase, Channel, Value) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDestinationAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD destination address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadDestinationAddressOffsetReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadDestinationAddressOffsetReg(PeripheralBase, Channel) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel destination address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Offset DMA channel destination address offset. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetDestinationAddressOffset(PeripheralBase, Channel, Offset) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Offset) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel destination address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetDestinationAddressOffset(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetDestinationAddressOffset(PeripheralBase, Channel) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransferAttributesReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel transfer attributes register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Transfer attributes register value. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteTransferAttributesReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteTransferAttributesReg(PeripheralBase, Channel, Value) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransferAttributesReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel transfer attributes register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: ATTR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadTransferAttributesReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadTransferAttributesReg(PeripheralBase, Channel) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Modulo DMA channel source address modulo. Use constants from group + * "Circular buffer size constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_CIRCULAR_BUFFER_DISABLED); + * @endcode + */ + #define DMA_PDD_SetSourceAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SMOD_MASK)))) | ( \ + (uint32)((uint32)(Modulo) << DMA_DCR_SMOD_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Modulo DMA channel source address modulo. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddressModulo(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_SMOD_MASK)))) | ( \ + (uint16)((uint16)(Modulo) << DMA_ATTR_SMOD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Circular buffer size constants" for + * processing return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DMA_PDD_GetSourceAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SMOD_MASK)) >> ( \ + DMA_DCR_SMOD_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DMA_PDD_GetSourceAddressModulo(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetSourceAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_SMOD_MASK)) >> ( \ + DMA_ATTR_SMOD_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetSourceDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Size DMA channel source data tranfer block size. This parameter is of + * "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceDataTransferSize(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetSourceDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SSIZE_MASK)))) | ( \ + (uint32)((uint32)(Size) << DMA_DCR_SSIZE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Size DMA channel source data tranfer block size. This parameter is of + * "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceDataTransferSize(_BASE_PTR, periphID, + * DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetSourceDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_SSIZE_MASK)))) | ( \ + (uint16)((uint16)(Size) << DMA_ATTR_SSIZE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetSourceDataTransferSize(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SSIZE_MASK)) >> ( \ + DMA_DCR_SSIZE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetSourceDataTransferSize(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetSourceDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_SSIZE_MASK)) >> ( \ + DMA_ATTR_SSIZE_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Modulo DMA channel destination address modulo. Use constants from + * group "Circular buffer size constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_CIRCULAR_BUFFER_DISABLED); + * @endcode + */ + #define DMA_PDD_SetDestinationAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DMOD_MASK)))) | ( \ + (uint32)((uint32)(Modulo) << DMA_DCR_DMOD_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Modulo DMA channel destination address modulo. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressModulo(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_DMOD_MASK)))) | ( \ + (uint16)((uint16)(Modulo) << DMA_ATTR_DMOD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Circular buffer size constants" for + * processing return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationAddressModulo(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DMOD_MASK)) >> ( \ + DMA_DCR_DMOD_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationAddressModulo(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_DMOD_MASK)) >> ( \ + DMA_ATTR_DMOD_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetDestinationDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Size DMA channel destination data tranfer block size. This parameter + * is of "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationDataTransferSize(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetDestinationDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DSIZE_MASK)))) | ( \ + (uint32)((uint32)(Size) << DMA_DCR_DSIZE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Size DMA channel destination data tranfer block size. This parameter + * is of "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationDataTransferSize(_BASE_PTR, periphID, + * DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetDestinationDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_DSIZE_MASK)))) | ( \ + (uint16)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationDataTransferSize(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DSIZE_MASK)) >> ( \ + DMA_DCR_DSIZE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationDataTransferSize(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_DSIZE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteMinorLoopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel minor loop register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteMinorLoopReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteMinorLoopReg(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinorLoopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor loop register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadMinorLoopReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadMinorLoopReg(PeripheralBase, Channel) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 32-bit DMA channel byte count. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount32(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount32(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount32(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount32(PeripheralBase, Channel) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount30 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 30-bit DMA channel byte count. This parameter is a 30-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount30(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount30(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFNO_NBYTES_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount30 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 30-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: NBYTES_MLOFFNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount30(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount30(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFNO_NBYTES_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount10 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 10-bit DMA channel byte count. This parameter is a 10-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount10(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount10(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_NBYTES_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount10 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount10(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount10(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFYES_NBYTES_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSourceMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel source minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel source minor loop offset + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableSourceMinorLoopOffset(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableSourceMinorLoopOffset(PeripheralBase, Channel, State) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_SMLOE_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDestinationMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel destination minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel source minor loop offset + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableDestinationMinorLoopOffset(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDestinationMinorLoopOffset(PeripheralBase, Channel, State) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_DMLOE_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopOffsetEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns source and destination minor loop offset enable bits state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetMinorLoopOffsetEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetMinorLoopOffsetEnabled(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param AddressOffset Address offset added to source and/or destination + * address. This parameter is a 20-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMinorLoopOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetMinorLoopOffset(PeripheralBase, Channel, AddressOffset) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_MLOFF_MASK)))) | ( \ + (uint32)((uint32)(AddressOffset) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 20-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetMinorLoopOffset(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetMinorLoopOffset(PeripheralBase, Channel) ( \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFYES_MLOFF_MASK))) >> ( \ + DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCurrentMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel current minor loop link major loop count + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteCurrentMajorLoopCountReg(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_WriteCurrentMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCurrentMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel current minor loop link major loop count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadCurrentMajorLoopCountReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_ReadCurrentMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCurrentMinorLoopLinking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel current minor loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableCurrentMinorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableCurrentMinorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKNO_ELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CITER_ELINKNO_ELINK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCurrentMinorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current minor loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMinorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMinorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_CITER_ELINKNO_ELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel current major loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 15-bit DMA channel major loop count. This parameter is a 15-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount15(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetCurrentMajorLoopCount15(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKNO_CITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)(Value))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetCurrentMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel current major loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 15-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMajorLoopCount15(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMajorLoopCount15(PeripheralBase, Channel) ( \ + (uint16)(DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_CITER_ELINKNO_CITER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCurrentMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMajorLoopCount9(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMajorLoopCount9(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_CITER_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetCurrentMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteBeginningMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel beginning minor loop link major loop count + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteBeginningMajorLoopCountReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteBeginningMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBeginningMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel beginning minor loop link major loop count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadBeginningMajorLoopCountReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_ReadBeginningMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBeginningMinorLoopLinking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel beginning minor loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableBeginningMinorLoopLinking(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableBeginningMinorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKNO_ELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_BITER_ELINKNO_ELINK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBeginningMinorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns beginning minor loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMinorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMinorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_BITER_ELINKNO_ELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 15-bit DMA channel major loop count. This parameter is a 15-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount15(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_SetBeginningMajorLoopCount15(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKNO_BITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBeginningMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 15-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMajorLoopCount15(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMajorLoopCount15(PeripheralBase, Channel) ( \ + (uint16)(DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_BITER_ELINKNO_BITER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)(Value))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBeginningMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMajorLoopCount9(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMajorLoopCount9(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_BITER_ELINKYES_BITER_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteLastSourceAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD last source address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteLastSourceAddressAdjustmentReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteLastSourceAddressAdjustmentReg(PeripheralBase, Channel, Value) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLastSourceAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA TCD last source address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadLastSourceAddressAdjustmentReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadLastSourceAddressAdjustmentReg(PeripheralBase, Channel) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLastSourceAddressAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel last source address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel last source address adjustment. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLastSourceAddressAdjustment(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_SetLastSourceAddressAdjustment(PeripheralBase, Channel, Value) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLastSourceAddressAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel last source address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetLastSourceAddressAdjustment(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetLastSourceAddressAdjustment(PeripheralBase, Channel) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLastDestinationAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD last destination address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteLastDestinationAddressAdjustmentReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteLastDestinationAddressAdjustmentReg(PeripheralBase, Channel, Value) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLastDestinationAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA TCD last destination address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadLastDestinationAddressAdjustmentReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadLastDestinationAddressAdjustmentReg(PeripheralBase, Channel) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLastDestinationAddressAdjustment_ScatterGather + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel last destination address adjustment or address for + * next TCD to be loaded into this channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel last destination address adjustment or TCD address. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLastDestinationAddressAdjustment_ScatterGather(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_SetLastDestinationAddressAdjustment_ScatterGather(PeripheralBase, Channel, Value) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLastDestinationAddressAdjustment_ScatterGather + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel last destination address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetLastDestinationAddressAdjustment_ScatterGather(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetLastDestinationAddressAdjustment_ScatterGather(PeripheralBase, Channel) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Channel control status register value. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteControlStatusReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteControlStatusReg(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_ReadControlStatusReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadControlStatusReg(PeripheralBase, Channel) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStallTime + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)(StallTime))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)(StallTime))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)))) | ( \ + (uint16)(StallTime))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetStallTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns bandwidth control stall time value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetStallTime(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetStallTime(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_BWC_MASK)) >> ( \ + DMA_CSR_BWC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMajorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetMajorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetChannelActivityFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel request pending, busy and done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Channel activity status constants" for + * processing return value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetChannelActivityFlags(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetChannelActivityFlags(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_DSR_BCR_REQ_MASK | (DMA_DSR_BCR_BSY_MASK | DMA_DSR_BCR_DONE_MASK)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns channel done and channel active status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetChannelActivityFlags(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetChannelActivityFlags(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(DMA_CSR_DONE_MASK | DMA_CSR_ACTIVE_MASK))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearChannelActivityFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)((uint16)(~(uint16)(ChannelActivityFlags)) & (uint16)(~(uint16)0x3C00U)) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)((uint16)(~(uint16)(ChannelActivityFlags)) & (uint16)(~(uint16)0x2000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)(~(uint16)(ChannelActivityFlags)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDoneFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDoneFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDoneFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_DONE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = DMA_PDD_GetDoneFlag(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDoneFlag(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_DONE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel active status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_GetActiveFlag(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetActiveFlag(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_ACTIVE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMajorLoopLinking + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetMajorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns major loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetMajorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetMajorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableScatterGather + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetScatterGatherEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns scatter/gather processing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetScatterGatherEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetScatterGatherEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_ESG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRequestAutoDisable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_D_REQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_D_REQ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetRequestAutoDisableEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns automaticall request clearing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRequestAutoDisableEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetRequestAutoDisableEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_D_REQ_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns automaticall request clearing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetRequestAutoDisableEnabled(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetRequestAutoDisableEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_DREQ_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransferCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_EINT_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_EINT_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetTransferCompleteInterruptEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns transfer complete enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetTransferCompleteInterruptEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetTransferCompleteInterruptEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_EINT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns transfer complete enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetTransferCompleteInterruptEnabled(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetTransferCompleteInterruptEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_INTMAJOR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransferHalfInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetTransferHalfInterruptEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transfer half enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetTransferHalfInterruptEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetTransferHalfInterruptEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_INTHALF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelGroup1Priority + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets group 1 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup1Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup1Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP1PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP1PRI_SHIFT))) \ + ) +#else /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Sets group 1 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup1Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup1Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP1PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP1PRI_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetChannelGroup0Priority + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets group 0 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup0Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup0Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP0PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP0PRI_SHIFT))) \ + ) +#else /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Sets group 0 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup0Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup0Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP0PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP0PRI_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableRoundRobinGroupArbitration + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables round robin group arbitration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if round robin group arbitration is enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableRoundRobinGroupArbitration(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableRoundRobinGroupArbitration(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_ERGA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_ERGA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRoundRobinGroupArbitrationEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns round robin group arbitration state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRoundRobinGroupArbitrationEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRoundRobinGroupArbitrationEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_ERGA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelGroupPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns group priority assigned to specified DMA channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @par Example: + * @code + * uint8 result = DMA_PDD_GetChannelGroupPriority(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetChannelGroupPriority(PeripheralBase, Channel) ( \ + (uint8)( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) & DMA_DCHPRI3_GRPPRI_MASK) >> DMA_DCHPRI3_GRPPRI_SHIFT \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels asynchrounous requests in stop mode specified by + * Mask parameter, rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_EnableAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels asynchrounous requests in stop mode specified by + * Mask parameter, rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be disabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_DisableAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mask of DMA channels enabled for asynchronous requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_SetAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels enabled for asynchronous request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetAsyncRequestInStopMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetAsyncRequestInStopMask(PeripheralBase) ( \ + DMA_EARS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableAsyncRequestInStopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable asynchronous request in STOP register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_WriteEnableAsyncRequestInStopReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableAsyncRequestInStopReg(PeripheralBase, Value) ( \ + DMA_EARS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableAsyncRequestInStopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable asynchronous request in STOP register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadEnableAsyncRequestInStopReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableAsyncRequestInStopReg(PeripheralBase) ( \ + DMA_EARS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableInterrupts(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_INTERRUPT); + * @endcode + */ +#define DMA_PDD_EnableInterrupts(PeripheralBase, Channel, Mask) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_DisableInterrupts(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_INTERRUPT); + * @endcode + */ +#define DMA_PDD_DisableInterrupts(PeripheralBase, Channel, Mask) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Interrupts' flags" for processing return + * value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetInterruptFlags(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetInterruptFlags(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_DONE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusByteCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel status and byte count control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteStatusByteCountReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_WriteStatusByteCountReg(PeripheralBase, Channel, Value) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusByteCountRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use WriteStatusByteCountReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteStatusByteCountRegister(_BASE_PTR, + * DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_WriteStatusByteCountRegister(PeripheralBase, Channel, Value) ( \ + DMA_PDD_WriteStatusByteCountReg(PeripheralBase, (Channel), (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusByteCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel status and byte count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadStatusByteCountReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_ReadStatusByteCountReg(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusByteCountRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use ReadStatusByteCountReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetStatusByteCountRegister(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetStatusByteCountRegister(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteStatusRegister(_BASE_PTR, DMA_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define DMA_PDD_WriteStatusRegister(PeripheralBase, Channel, Value) ( \ + DMA_DSR_REG(PeripheralBase,(Channel)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel status register provading information about last + * recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetStatusRegister(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetStatusRegister(PeripheralBase, Channel) ( \ + DMA_DSR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel busy status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetBusyFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetBusyFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_BSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestPendingFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel request pending status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestPendingFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetRequestPendingFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_REQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel configuration error, bus error on source and bus + * error on destination status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Channel error status constants" for + * processing return value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetChannelErrorFlags(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetChannelErrorFlags(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_DSR_BCR_CE_MASK | (DMA_DSR_BCR_BES_MASK | DMA_DSR_BCR_BED_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value 24-bit DMA channel byte count. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount(PeripheralBase, Channel, Value) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & (( \ + (uint32)(~(uint32)DMA_DSR_BCR_BCR_MASK)) & ( \ + (uint32)(~(uint32)DMA_DSR_BCR_DONE_MASK))))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetByteCount(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_BCR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPeripheralRequestEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns peripheral requests enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetPeripheralRequestEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetPeripheralRequestEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_ERQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCycleSteal + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables cycle steal mode (single read/write transfer per + * request). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel cycle-steal mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableCycleSteal(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableCycleSteal(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & (uint32)(~(uint32)DMA_DCR_CS_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_CS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCycleStealEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns cycle steal mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetCycleStealEnabled(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetCycleStealEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_CS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables continuous mode (whole transfer per request). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel continuous mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableContinuousMode(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableContinuousMode(PeripheralBase, Channel, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DCR_CS_MASK) : ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) &= \ + (uint32)(~(uint32)DMA_DCR_CS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetContinuousModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns continuous mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetContinuousModeEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetContinuousModeEnabled(PeripheralBase, Channel) ( \ + ((uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_CS_MASK) == 0U) ? ( \ + PDD_ENABLE) : ( \ + PDD_DISABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAutoAlign + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables auto-align mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfers will be transfers + * are optimized based on the address and size or not. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableAutoAlign(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableAutoAlign(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & (uint32)(~(uint32)DMA_DCR_AA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_AA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAutoAlignEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns auto-align mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetAutoAlignEnabled(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetAutoAlignEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_AA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsynchronousRequests + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables asynchronous requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfers will be transfers + * are optimized based on the address and size or not. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableAsynchronousRequests(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableAsynchronousRequests(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_EADREQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_EADREQ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAsynchronousRequestsEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns auto-align mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetAsynchronousRequestsEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetAsynchronousRequestsEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_EADREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSourceAddressIncrement + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables source address incrementation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel source address increments + * after each successful transfer (according to transfer size) or not. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableSourceAddressIncrement(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableSourceAddressIncrement(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SINC_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_SINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressIncrementEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns source address incrementation enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetSourceAddressIncrementEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetSourceAddressIncrementEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SINC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDestinationAddressIncrement + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables destination address incrementation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel destination address + * increments after each successful transfer (according to transfer size) or not. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableDestinationAddressIncrement(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDestinationAddressIncrement(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DINC_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_DINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressIncrementEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns destination address incrementation enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetDestinationAddressIncrementEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetDestinationAddressIncrementEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DINC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelLinkingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel linking mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mode DMA channel linking mode. This parameter is of "DMA data transfer + * size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetChannelLinkingMode(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_LINKING_DISABLED); + * @endcode + */ +#define DMA_PDD_SetChannelLinkingMode(PeripheralBase, Channel, Mode) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LINKCC_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelLinkingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel linking mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetChannelLinkingMode(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetChannelLinkingMode(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LINKCC_MASK)) >> ( \ + DMA_DCR_LINKCC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLinkChannel1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel link 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value Linked DMA channel number. Use constants from group "DMA channel + * constants". This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLinkChannel1(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetLinkChannel1(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LCH1_MASK)))) | ( \ + (uint32)((uint32)(Value) << DMA_DCR_LCH1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLinkChannel1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel link 1 channel number. Use constants from group + * "DMA channel constants" for processing return value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetLinkChannel1(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetLinkChannel1(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LCH1_MASK)) >> ( \ + DMA_DCR_LCH1_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLinkChannel2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel link 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value Linked DMA channel number. Use constants from group "DMA channel + * constants". This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLinkChannel2(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetLinkChannel2(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LCH2_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLinkChannel2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel link 2 channel number. Use constants from group + * "DMA channel constants" for processing return value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetLinkChannel2(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetLinkChannel2(PeripheralBase, Channel) ( \ + (uint8)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LCH2_MASK) \ + ) +#endif /* #if defined(DMA_PDD_H_) */ + +/* DMA_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h new file mode 100644 index 0000000..2f524a0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h @@ -0,0 +1,490 @@ +/* + PDD layer implementation for peripheral type EWM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(EWM_PDD_H_) +#define EWM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error EWM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* EWM */ && \ + !defined(MCU_MK10D5) /* EWM */ && \ + !defined(MCU_MK10D7) /* EWM */ && \ + !defined(MCU_MK10F12) /* EWM */ && \ + !defined(MCU_MK10DZ10) /* EWM */ && \ + !defined(MCU_MK11D5) /* EWM */ && \ + !defined(MCU_MK11D5WS) /* EWM */ && \ + !defined(MCU_MK12D5) /* EWM */ && \ + !defined(MCU_MK20D10) /* EWM */ && \ + !defined(MCU_MK20D5) /* EWM */ && \ + !defined(MCU_MK20D7) /* EWM */ && \ + !defined(MCU_MK20F12) /* EWM */ && \ + !defined(MCU_MK20DZ10) /* EWM */ && \ + !defined(MCU_MK21D5) /* EWM */ && \ + !defined(MCU_MK21D5WS) /* EWM */ && \ + !defined(MCU_MK21F12) /* EWM */ && \ + !defined(MCU_MK21F12WS) /* EWM */ && \ + !defined(MCU_MK22D5) /* EWM */ && \ + !defined(MCU_MK22F12810) /* EWM */ && \ + !defined(MCU_MK22F12) /* EWM */ && \ + !defined(MCU_MK22F25612) /* EWM */ && \ + !defined(MCU_MK22F51212) /* EWM */ && \ + !defined(MCU_MK24F12) /* EWM */ && \ + !defined(MCU_MK30D10) /* EWM */ && \ + !defined(MCU_MK30D7) /* EWM */ && \ + !defined(MCU_MK30DZ10) /* EWM */ && \ + !defined(MCU_MK40D10) /* EWM */ && \ + !defined(MCU_MK40D7) /* EWM */ && \ + !defined(MCU_MK40DZ10) /* EWM */ && \ + !defined(MCU_MK40X256VMD100) /* EWM */ && \ + !defined(MCU_MK50D10) /* EWM */ && \ + !defined(MCU_MK50D7) /* EWM */ && \ + !defined(MCU_MK50DZ10) /* EWM */ && \ + !defined(MCU_MK51D10) /* EWM */ && \ + !defined(MCU_MK51D7) /* EWM */ && \ + !defined(MCU_MK51DZ10) /* EWM */ && \ + !defined(MCU_MK52D10) /* EWM */ && \ + !defined(MCU_MK52DZ10) /* EWM */ && \ + !defined(MCU_MK53D10) /* EWM */ && \ + !defined(MCU_MK53DZ10) /* EWM */ && \ + !defined(MCU_MK60D10) /* EWM */ && \ + !defined(MCU_MK60F12) /* EWM */ && \ + !defined(MCU_MK60F15) /* EWM */ && \ + !defined(MCU_MK60DZ10) /* EWM */ && \ + !defined(MCU_MK60N512VMD100) /* EWM */ && \ + !defined(MCU_MK61F12) /* EWM */ && \ + !defined(MCU_MK61F15) /* EWM */ && \ + !defined(MCU_MK61F12WS) /* EWM */ && \ + !defined(MCU_MK61F15WS) /* EWM */ && \ + !defined(MCU_MK63F12) /* EWM */ && \ + !defined(MCU_MK63F12WS) /* EWM */ && \ + !defined(MCU_MK64F12) /* EWM */ && \ + !defined(MCU_MK65F18) /* EWM */ && \ + !defined(MCU_MK65F18WS) /* EWM */ && \ + !defined(MCU_MK66F18) /* EWM */ && \ + !defined(MCU_MK70F12) /* EWM */ && \ + !defined(MCU_MK70F15) /* EWM */ && \ + !defined(MCU_MK70F12WS) /* EWM */ && \ + !defined(MCU_MK70F15WS) /* EWM */ && \ + !defined(MCU_MKV10Z7) /* EWM */ && \ + !defined(MCU_MKV31F12810) /* EWM */ && \ + !defined(MCU_MKV31F25612) /* EWM */ && \ + !defined(MCU_MKV31F51212) /* EWM */ && \ + !defined(MCU_MKW21D5) /* EWM */ && \ + !defined(MCU_MKW21D5WS) /* EWM */ && \ + !defined(MCU_MKW22D5) /* EWM */ && \ + !defined(MCU_MKW22D5WS) /* EWM */ && \ + !defined(MCU_MKW24D5) /* EWM */ && \ + !defined(MCU_MKW24D5WS) /* EWM */ && \ + !defined(MCU_PCK20L4) /* EWM */ + // Unsupported MCU is active + #error EWM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Service constants */ +#define EWM_PDD_KEY_1 0xB4U /**< First key */ +#define EWM_PDD_KEY_2 0x2CU /**< Second key */ + +/* Clock source constants. */ +#define EWM_PDD_SOURCE_ROSC_8M 0U /**< Relaxation oscillator clock */ +#define EWM_PDD_SOURCE_XTAL_OSC 0x1U /**< Crystal oscillator clock */ +#define EWM_PDD_SOURCE_BUS_CLK 0x2U /**< IP bus clock */ +#define EWM_PDD_SOURCE_ROSC_200K 0x3U /**< Low speed oscillator clock */ + + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteControlReg(PeripheralBase, Value) ( \ + EWM_CTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of EWM device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(EWM_CTRL_REG(PeripheralBase) & EWM_CTRL_EWMEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare low register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CMPL. + * @par Example: + * @code + * EWM_PDD_WriteCompareLowReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteCompareLowReg(PeripheralBase, Value) ( \ + EWM_CMPL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CMPL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadCompareLowReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadCompareLowReg(PeripheralBase) ( \ + EWM_CMPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare high register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CMPH. + * @par Example: + * @code + * EWM_PDD_WriteCompareHighReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteCompareHighReg(PeripheralBase, Value) ( \ + EWM_CMPH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CMPH. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadCompareHighReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadCompareHighReg(PeripheralBase) ( \ + EWM_CMPH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteServiceReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the service register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_SERV. + * @par Example: + * @code + * EWM_PDD_WriteServiceReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteServiceReg(PeripheralBase, Value) ( \ + EWM_SERV_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the EWM interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_DisableInterrupt(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)EWM_CTRL_INTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the EWM interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_EnableInterrupt(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) |= \ + EWM_CTRL_INTEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * EWM_PDD_SelectClockSource(_BASE_PTR, + * EWM_PDD_SOURCE_ROSC_8M); + * @endcode + */ +#define EWM_PDD_SelectClockSource(PeripheralBase, Source) ( \ + EWM_CLKCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(EWM_CLKCTRL_REG(PeripheralBase) & (uint8)(~(uint8)EWM_CLKCTRL_CLKSEL_MASK))) | ( \ + (uint8)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the prescaler. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * EWM_PDD_SetPrescaler(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_SetPrescaler(PeripheralBase, Value) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadControlReg(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the clock control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * EWM_PDD_WriteClockControlReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteClockControlReg(PeripheralBase, Value) ( \ + EWM_CLKCTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadClockControlReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadClockControlReg(PeripheralBase) ( \ + EWM_CLKCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the clock prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the clock prescaler register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * EWM_PDD_WriteClockPrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteClockPrescalerReg(PeripheralBase, Value) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the clock prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadClockPrescalerReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadClockPrescalerReg(PeripheralBase) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) \ + ) +#endif /* #if defined(EWM_PDD_H_) */ + +/* EWM_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h new file mode 100644 index 0000000..5410393 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h @@ -0,0 +1,1244 @@ +/* + PDD layer implementation for peripheral type FMC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FMC_PDD_H_) +#define FMC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FMC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FMC */ && \ + !defined(MCU_MK10D5) /* FMC */ && \ + !defined(MCU_MK10D7) /* FMC */ && \ + !defined(MCU_MK10F12) /* FMC */ && \ + !defined(MCU_MK10DZ10) /* FMC */ && \ + !defined(MCU_MK11D5) /* FMC */ && \ + !defined(MCU_MK11D5WS) /* FMC */ && \ + !defined(MCU_MK12D5) /* FMC */ && \ + !defined(MCU_MK20D10) /* FMC */ && \ + !defined(MCU_MK20D5) /* FMC */ && \ + !defined(MCU_MK20D7) /* FMC */ && \ + !defined(MCU_MK20F12) /* FMC */ && \ + !defined(MCU_MK20DZ10) /* FMC */ && \ + !defined(MCU_MK21D5) /* FMC */ && \ + !defined(MCU_MK21D5WS) /* FMC */ && \ + !defined(MCU_MK21F12) /* FMC */ && \ + !defined(MCU_MK21F12WS) /* FMC */ && \ + !defined(MCU_MK22D5) /* FMC */ && \ + !defined(MCU_MK22F12810) /* FMC */ && \ + !defined(MCU_MK22F12) /* FMC */ && \ + !defined(MCU_MK22F25612) /* FMC */ && \ + !defined(MCU_MK22F51212) /* FMC */ && \ + !defined(MCU_MK24F12) /* FMC */ && \ + !defined(MCU_MK30D10) /* FMC */ && \ + !defined(MCU_MK30D7) /* FMC */ && \ + !defined(MCU_MK30DZ10) /* FMC */ && \ + !defined(MCU_MK40D10) /* FMC */ && \ + !defined(MCU_MK40D7) /* FMC */ && \ + !defined(MCU_MK40DZ10) /* FMC */ && \ + !defined(MCU_MK40X256VMD100) /* FMC */ && \ + !defined(MCU_MK50D10) /* FMC */ && \ + !defined(MCU_MK50D7) /* FMC */ && \ + !defined(MCU_MK50DZ10) /* FMC */ && \ + !defined(MCU_MK51D10) /* FMC */ && \ + !defined(MCU_MK51D7) /* FMC */ && \ + !defined(MCU_MK51DZ10) /* FMC */ && \ + !defined(MCU_MK52D10) /* FMC */ && \ + !defined(MCU_MK52DZ10) /* FMC */ && \ + !defined(MCU_MK53D10) /* FMC */ && \ + !defined(MCU_MK53DZ10) /* FMC */ && \ + !defined(MCU_MK60D10) /* FMC */ && \ + !defined(MCU_MK60F12) /* FMC */ && \ + !defined(MCU_MK60F15) /* FMC */ && \ + !defined(MCU_MK60DZ10) /* FMC */ && \ + !defined(MCU_MK60N512VMD100) /* FMC */ && \ + !defined(MCU_MK61F12) /* FMC */ && \ + !defined(MCU_MK61F15) /* FMC */ && \ + !defined(MCU_MK61F12WS) /* FMC */ && \ + !defined(MCU_MK61F15WS) /* FMC */ && \ + !defined(MCU_MK63F12) /* FMC */ && \ + !defined(MCU_MK63F12WS) /* FMC */ && \ + !defined(MCU_MK64F12) /* FMC */ && \ + !defined(MCU_MK65F18) /* FMC */ && \ + !defined(MCU_MK65F18WS) /* FMC */ && \ + !defined(MCU_MK66F18) /* FMC */ && \ + !defined(MCU_MK70F12) /* FMC */ && \ + !defined(MCU_MK70F15) /* FMC */ && \ + !defined(MCU_MK70F12WS) /* FMC */ && \ + !defined(MCU_MK70F15WS) /* FMC */ && \ + !defined(MCU_MKV31F12810) /* FMC */ && \ + !defined(MCU_MKV31F25612) /* FMC */ && \ + !defined(MCU_MKV31F51212) /* FMC */ && \ + !defined(MCU_MKW21D5) /* FMC */ && \ + !defined(MCU_MKW21D5WS) /* FMC */ && \ + !defined(MCU_MKW22D5) /* FMC */ && \ + !defined(MCU_MKW22D5WS) /* FMC */ && \ + !defined(MCU_MKW24D5) /* FMC */ && \ + !defined(MCU_MKW24D5WS) /* FMC */ && \ + !defined(MCU_PCK20L4) /* FMC */ + // Unsupported MCU is active + #error FMC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Master acces protection constants. */ +#define FMC_PDD_NO_ACCESS 0U /**< No access may be performed by master */ +#define FMC_PDD_READ_ONLY_ACCESS 0x1U /**< Only read accesses may be performed by master */ +#define FMC_PDD_WRITE_ONLY_ACCESS 0x2U /**< Only write accesses may be performed by master */ +#define FMC_PDD_READ_AND_WRITE_ACCESS 0x3U /**< Read and write accesses may be performed by master */ + +/* Wait state required to access the flash memory constants. */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_1 0U /**< 1 wait state required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_2 0x1U /**< 2 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_3 0x2U /**< 3 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_4 0x3U /**< 4 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_5 0x4U /**< 5 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_6 0x5U /**< 6 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_7 0x6U /**< 7 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_8 0x7U /**< 8 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_9 0x8U /**< 9 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_10 0x9U /**< 10 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_11 0xAU /**< 11 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_12 0xBU /**< 12 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_13 0xCU /**< 13 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_14 0xDU /**< 14 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_15 0xEU /**< 15 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_16 0xFU /**< 16 wait states required to access the flash memory */ + +/* Cache lock way constants. */ +#define FMC_PDD_CACHE_LOCK_WAY_0 0x1U /**< Cache lock way 0 */ +#define FMC_PDD_CACHE_LOCK_WAY_1 0x2U /**< Cache lock way 1 */ +#define FMC_PDD_CACHE_LOCK_WAY_2 0x4U /**< Cache lock way 2 */ +#define FMC_PDD_CACHE_LOCK_WAY_3 0x8U /**< Cache lock way 3 */ +#define FMC_PDD_CACHE_LOCK_WAY_ALL 0xFU /**< Cache lock all ways */ + +/* Invalide flash cache way mask constants. */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_0 0x100000U /**< Cache invalidate way 0 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_1 0x200000U /**< Cache invalidate way 1 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_2 0x400000U /**< Cache invalidate way 2 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_3 0x800000U /**< Cache invalidate way 3 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_ALL 0xF00000U /**< Cache invalidate all ways mask */ + +/* Memory width constants. */ +#define FMC_PDD_MEMORY_WIDTH_32BITS 0U /**< Memory width 32 bits constant */ +#define FMC_PDD_MEMORY_WIDTH_64BITS 0x20000U /**< Memory width 64 bits constant */ + +/* Cache replacement control constants */ +#define FMC_PDD_LRU_REPLACEMENT_FOR_ALL_4_WAYS 0U /**< LRU replacement algorithm per set across all four ways */ +#define FMC_PDD_LRU_WITH_01_IFETCHES_23_DATA_WAYS 0x40U /**< Independent LRU with ways [0-1] for ifetches, [2-3] for data */ +#define FMC_PDD_LRU_WITH_02_IFETCHES_3_DATA_WAYS 0x60U /**< Independent LRU with ways [0-2] for ifetches, [3] for data */ + + +/* ---------------------------------------------------------------------------- + -- InvalidateFlashCache + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR, FMC_PFB01CR + * (depending on the peripheral). + * @par Example: + * @code + * FMC_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ + #define FMC_PDD_InvalidateFlashCache(PeripheralBase) ( \ + FMC_PFB01CR_REG(PeripheralBase) |= \ + (uint32)(FMC_PFB01CR_CINV_WAY_MASK | FMC_PFB01CR_S_B_INV_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR, FMC_PFB01CR + * (depending on the peripheral). + * @par Example: + * @code + * FMC_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ + #define FMC_PDD_InvalidateFlashCache(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) |= \ + (uint32)(FMC_PFB0CR_CINV_WAY_MASK | FMC_PFB0CR_S_B_INV_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableMaster7Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 7 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 7 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster7Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster7Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M7PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M7PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster6Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 6 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 6 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster6Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster6Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M6PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M6PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster5Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 5 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 5 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster5Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster5Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M5PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M5PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster4Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 4 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 4 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster4Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster4Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M4PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M4PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster3Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 3 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 3 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster3Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster3Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M3PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M3PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster2Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 2 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 2 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster2Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster2Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M2PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M2PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster1Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 1 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 1 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster1Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster1Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M1PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M1PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster0Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 0 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 0 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster0Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster0Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M0PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M0PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster7AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 7 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster7AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster7AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M7AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M7AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster6AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 6 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster6AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster6AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M6AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M6AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster5AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 5 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster5AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster5AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M5AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M5AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster4AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 4 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster4AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster4AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M4AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M4AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster3AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 3 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster3AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster3AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M3AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M3AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster2AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 2 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster2AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster2AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M2AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M2AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster1AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 1 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster1AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster1AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M1AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M1AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster0AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 0 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster0AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster0AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M0AP_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashAccessProtectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash access protection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadFlashAccessProtectionReg(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_ReadFlashAccessProtectionReg(PeripheralBase) ( \ + FMC_PFAPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashAccessProtectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash access + * protection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash access protection register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_WriteFlashAccessProtectionReg(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_WriteFlashAccessProtectionReg(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadWaitStateControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the wait state control value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint8 result = FMC_PDD_GetReadWaitStateControl(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetReadWaitStateControl(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_B0RWSC_MASK)) >> ( \ + FMC_PFB0CR_B0RWSC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCacheLockWayMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the cache lock way defined by mas parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Cache lock way mask. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_SetCacheLockWayMask(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_SetCacheLockWayMask(PeripheralBase, Mask) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FMC_PFB0CR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FMC_PFB0CR_CLCK_WAY_MASK)))) | ( \ + (uint32)((uint32)(Mask) << FMC_PFB0CR_CLCK_WAY_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCacheLockWay + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the cache lock way mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint8 result = FMC_PDD_GetCacheLockWay(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetCacheLockWay(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_CLCK_WAY_MASK)) >> ( \ + FMC_PFB0CR_CLCK_WAY_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalideFlashCacheWay + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalide flash cache way requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of invalide flash cache way. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_InvalideFlashCacheWay(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_InvalideFlashCacheWay(PeripheralBase, Mask) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FMC_PFB0CR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FMC_PFB0CR_CINV_WAY_MASK)))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalidePrefetchSpeculationBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalidate (clear) speculation buffer and single entry buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_InvalidePrefetchSpeculationBuffer(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_InvalidePrefetchSpeculationBuffer(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) |= \ + FMC_PFB0CR_S_B_INV_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMemoryWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the memory width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Memory width constants." type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint32 result = FMC_PDD_GetMemoryWidth(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetMemoryWidth(PeripheralBase) ( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_B0MW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCacheReplacementControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the cache replacement control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Control Cache replacement control value. The user should use one from + * the enumerated values. This parameter is of "Cache replacement control + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_SetCacheReplacementControl(_BASE_PTR, + * FMC_PDD_LRU_REPLACEMENT_FOR_ALL_4_WAYS); + * @endcode + */ +#define FMC_PDD_SetCacheReplacementControl(PeripheralBase, Control) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_CRC_MASK))) | ( \ + (uint32)(Control))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDataCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a data cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of data cache request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableDataCache(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableDataCache(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0DCE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0DCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInstructionCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a instruction cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of instruction cache request. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableInstructionCache(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableInstructionCache(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0ICE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0ICE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDataPrefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a data prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of data prefetch request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableDataPrefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableDataPrefetch(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0DPE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0DPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInstructionPrefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a instruction prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of instruction prefetch request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableInstructionPrefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableInstructionPrefetch(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0IPE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0IPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSingleEntryBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a single entry buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of single entry buffer request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableSingleEntryBuffer(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableSingleEntryBuffer(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0SEBE_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint32 result = FMC_PDD_ReadFlashControlReg(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_ReadFlashControlReg(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_WriteFlashControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_WriteFlashControlReg(PeripheralBase, Value) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheTagStorageWaySetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache tag way and set storage register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache tag storage way index. This parameter is of index type. + * @param SetIdx Cache tag storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TAGVD[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheTagStorageWaySetReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheTagStorageWaySetReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_TAGVD_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheTagStorageWaySetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache tag way + * and set storage register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache tag storage way index. This parameter is of index type. + * @param SetIdx Cache tag storage set index. This parameter is of index type. + * @param Value Value to be written to the cache tag way and set storage + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TAGVD[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheTagStorageWaySetReg(_BASE_PTR, periphID, + * periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheTagStorageWaySetReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_TAGVD_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheDataStorageWaySetUpperWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache data way and set storage upper word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DATA_U[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheDataStorageWaySetUpperWordReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheDataStorageWaySetUpperWordReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_DATA_U_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheDataStorageWaySetUpperWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache data way + * and set storage upper word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @param Value Value to be written to the cache data way and set storage upper + * word register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATA_U[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheDataStorageWaySetUpperWordReg(_BASE_PTR, + * periphID, periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheDataStorageWaySetUpperWordReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_DATA_U_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheDataStorageWaySetLowerWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache data way and set storage lower word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DATA_L[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheDataStorageWaySetLowerWordReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheDataStorageWaySetLowerWordReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_DATA_L_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheDataStorageWaySetLowerWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache data way + * and set storage lower word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @param Value Value to be written to the cache data way and set storage lower + * word register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATA_L[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheDataStorageWaySetLowerWordReg(_BASE_PTR, + * periphID, periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheDataStorageWaySetLowerWordReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_DATA_L_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(FMC_PDD_H_) */ + +/* FMC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h new file mode 100644 index 0000000..029c053 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h @@ -0,0 +1,3215 @@ +/* + PDD layer implementation for peripheral type FTFL + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FTFL_PDD_H_) +#define FTFL_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FTFL PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FTFL */ && \ + !defined(MCU_MK10D5) /* FTFL */ && \ + !defined(MCU_MK10D7) /* FTFL */ && \ + !defined(MCU_MK10DZ10) /* FTFL */ && \ + !defined(MCU_MK11D5) /* FTFL */ && \ + !defined(MCU_MK11D5WS) /* FTFL */ && \ + !defined(MCU_MK12D5) /* FTFL */ && \ + !defined(MCU_MK20D10) /* FTFL */ && \ + !defined(MCU_MK20D5) /* FTFL */ && \ + !defined(MCU_MK20D7) /* FTFL */ && \ + !defined(MCU_MK20DZ10) /* FTFL */ && \ + !defined(MCU_MK21D5) /* FTFL */ && \ + !defined(MCU_MK21D5WS) /* FTFL */ && \ + !defined(MCU_MK22D5) /* FTFL */ && \ + !defined(MCU_MK30D10) /* FTFL */ && \ + !defined(MCU_MK30D7) /* FTFL */ && \ + !defined(MCU_MK30DZ10) /* FTFL */ && \ + !defined(MCU_MK40D10) /* FTFL */ && \ + !defined(MCU_MK40D7) /* FTFL */ && \ + !defined(MCU_MK40DZ10) /* FTFL */ && \ + !defined(MCU_MK40X256VMD100) /* FTFL */ && \ + !defined(MCU_MK50D10) /* FTFL */ && \ + !defined(MCU_MK50D7) /* FTFL */ && \ + !defined(MCU_MK50DZ10) /* FTFL */ && \ + !defined(MCU_MK51D10) /* FTFL */ && \ + !defined(MCU_MK51D7) /* FTFL */ && \ + !defined(MCU_MK51DZ10) /* FTFL */ && \ + !defined(MCU_MK52D10) /* FTFL */ && \ + !defined(MCU_MK52DZ10) /* FTFL */ && \ + !defined(MCU_MK53D10) /* FTFL */ && \ + !defined(MCU_MK53DZ10) /* FTFL */ && \ + !defined(MCU_MK60D10) /* FTFL */ && \ + !defined(MCU_MK60DZ10) /* FTFL */ && \ + !defined(MCU_MK60N512VMD100) /* FTFL */ && \ + !defined(MCU_MKW21D5) /* FTFL */ && \ + !defined(MCU_MKW21D5WS) /* FTFL */ && \ + !defined(MCU_MKW22D5) /* FTFL */ && \ + !defined(MCU_MKW22D5WS) /* FTFL */ && \ + !defined(MCU_MKW24D5) /* FTFL */ && \ + !defined(MCU_MKW24D5WS) /* FTFL */ && \ + !defined(MCU_PCK20L4) /* FTFL */ + // Unsupported MCU is active + #error FTFL PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* ClearFlags constants */ +#define FTFL_PDD_COMMAND_COMPLETE FTFL_FSTAT_CCIF_MASK /**< Command complete flag mask */ +#define FTFL_PDD_READ_COLLISION_ERROR FTFL_FSTAT_RDCOLERR_MASK /**< Read collision error flag mask */ +#define FTFL_PDD_ACCESS_ERROR FTFL_FSTAT_ACCERR_MASK /**< Access error flag mask */ +#define FTFL_PDD_PROTECTION_VIOLATION FTFL_FSTAT_FPVIOL_MASK /**< Protection violation flag mask */ +#define FTFL_PDD_COMMAND_COMPLETION_STATUS FTFL_FSTAT_MGSTAT0_MASK /**< Command completion ststus flag mask */ + +/* EnableInterrupts;, DisableInterrupts constants */ +#define FTFL_PDD_COMMAND_COMPLETE_INT FTFL_FCNFG_CCIE_MASK /**< Command complete interrupt mask */ +#define FTFL_PDD_READ_COLLISION_ERROR_INT FTFL_FCNFG_RDCOLLIE_MASK /**< Read collision error interrupt mask */ + +/* SetFCCOBCommand constants */ +#define FTFL_PDD_READ_1S_BLOCK 0U /**< Read 1s Block command value */ +#define FTFL_PDD_READ_1S_SECTION 0x1U /**< Read 1s Section command value */ +#define FTFL_PDD_PROGRAM_CHECK 0x2U /**< Program Check command value */ +#define FTFL_PDD_READ_RESOURCE 0x3U /**< Read Resource command value */ +#define FTFL_PDD_PROGRAM_LONGWORD 0x6U /**< Program Longword command value */ +#define FTFL_PDD_ERASE_FLASH_BLOCK 0x8U /**< Erase Flash Block command value */ +#define FTFL_PDD_ERASE_FLASH_SECTOR 0x9U /**< Erase Flash Sector command value */ +#define FTFL_PDD_PROGRAM_SECTION 0xBU /**< Program Section command value */ +#define FTFL_PDD_READ_1S_ALL_BLOCKS 0x40U /**< Read 1s All Blocks command value */ +#define FTFL_PDD_PDD_READ_ONCE 0x41U /**< Read Once command value */ +#define FTFL_PDD_PROGRAM_ONCE 0x43U /**< Program Once command value */ +#define FTFL_PDD_ERASE_ALL_BLOCKS 0x44U /**< Erase All Blocks command value */ +#define FTFL_PDD_VERIFY_BACKDOOR_ACCESS_KEY 0x45U /**< Verify Backdoor Access Key command value */ +#define FTFL_PDD_PROGRAM_PARTITION 0x80U /**< Program Partition command value */ +#define FTFL_PDD_SET_EERAM_FUCTION 0x81U /**< Set FlexRAM Function command value */ + +/* Margin level constants */ +#define FTFL_PDD_READ_MARGIN_LEVEL_NORMAL 0U /**< Normal read level constant */ +#define FTFL_PDD_READ_MARGIN_LEVEL_USER 0x1U /**< User read level constant */ +#define FTFL_PDD_READ_MARGIN_LEVEL_FACTORY 0x2U /**< Factory read level constant */ + +/* Read resource command resource code constants */ +#define FTFL_PDD_RESOURCE_IFR 0U /**< IFR */ +#define FTFL_PDD_RESOURCE_VERSION_ID 0x1U /**< Version ID */ + +/* EEPROM size constants */ +#define FTFL_PDD_EEPROM_DATA_SIZE_0_B 0xFU /**< No EEPROM */ +#define FTFL_PDD_EEPROM_DATA_SIZE_32_B 0x9U /**< 32 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_64_B 0x8U /**< 64 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_128_B 0x7U /**< 128 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_256_B 0x6U /**< 256 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_512_B 0x5U /**< 512 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_1024_B 0x4U /**< 1024 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_SIZE_2048_B 0x3U /**< 2048 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_4096_B 0x2U /**< 4096 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_8192_B 0x1U /**< 8192 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_16384_B 0U /**< 16384 bytes of EEPROM data */ + +/* EEPROM backup size constants */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_0_KB 0U /**< No EEPROM */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_8_KB 0x1U /**< 8 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_16_KB 0x2U /**< 16 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_32_KB 0x3U /**< 32 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_64_KB 0x4U /**< 64 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_128_KB 0x5U /**< 128 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_256_KB 0x6U /**< 256 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_512_KB 0x7U /**< 512 KB of EEPROM backup */ +#define FTFL_PDD_DATA_FLASH_SIZE_0_KB 0x8U /**< No data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_8_KB 0x9U /**< 8 KB of data falsh */ +#define FTFL_PDD_EDATA_FLASH_SIZE_16_KB 0xAU /**< 16 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_32_KB 0xBU /**< 32 KB of data falshp */ +#define FTFL_PDD_DATA_FLASH_SIZE_64_KB 0xCU /**< 64 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_128_KB 0xDU /**< 128 KB of data falsh */ +#define FTFL_PDD_EDATA_FLASH_SIZE_256_KB 0xEU /**< 256 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_512_KB 0xFU /**< 512 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_MAX 0xFU /**< No EEPROM backup data falsh only */ + +/* FlexRAM function constants */ +#define FTFL_PDD_FLEXRAM_AS_RAM 0xFFU /**< Make FlexRAM available as RAM */ +#define FTFL_PDD_FLEXRAM_AS_EEPROM 0U /**< Make FlexRAM available for EEPROM */ + +/* BackDoorKey constants */ +#define FTFL_PDD_BACKDOOR_KEY_ENABLED 0U /**< Backdoor key enable constant */ +#define FTFL_PDD_BACKDOOR_KEY_DISABLED 0x1U /**< Backdoor key disable constant */ + +/* Mass erase constants */ +#define FTFL_PDD_MASS_ERASE_ENABLED 0U /**< Mass erase enable constant */ +#define FTFL_PDD_MASS_ERASE_DISABLED 0x1U /**< Mass erase disable constant */ + +/* Factory access constants */ +#define FTFL_PDD_FACTORY_ACCESS_GRANTED 0U /**< Factory access granted constant */ +#define FTFL_PDD_FACTORY_ACCESS_DENIED 0x1U /**< Factory access denied constant */ + +/* Security state constants */ +#define FTFL_PDD_UNSECURED 0U /**< Unsecure constant */ +#define FTFL_PDD_SECURED 0x1U /**< Secure constant */ + +/* FlashProtection constants */ +#define FTFL_PDD_UNPROTECTED 0U /**< Unprotect constant */ +#define FTFL_PDD_PROTECTED 0x1U /**< Protect constant */ + + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "ClearFlags constants" for processing return + * value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadStatusReg(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Flash status register. Use constants from + * group "ClearFlags constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_WriteStatusReg(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE); + * @endcode + */ +#define FTFL_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCommandCompleteFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Command complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearCommandCompleteFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearCommandCompleteFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_CCIF_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearReadCollisionErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Read collision error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearReadCollisionErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearReadCollisionErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_RDCOLERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAccessErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Access error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearAccessErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearAccessErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_ACCERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearProtectionViolationErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Protection violation error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearProtectionViolationErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearProtectionViolationErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- LaunchCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts new command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_LaunchCommand(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_LaunchCommand(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + 0x80U \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Flags Interrupt mask. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearFlags(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_ClearFlags(PeripheralBase, Flags) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(Flags) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetFlags(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadConfigReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadConfigReg(PeripheralBase) ( \ + FTFL_FCNFG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Flash configuration register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_WriteConfigReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteConfigReg(PeripheralBase, Value) ( \ + FTFL_FCNFG_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Command commplete end Read collision error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "EnableInterrupts;, + * DisableInterrupts constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_EnableInterrupts(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define FTFL_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + FTFL_FCNFG_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + FTFL_FCNFG_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(FTFL_FCNFG_CCIE_MASK | FTFL_FCNFG_RDCOLLIE_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Command commplete end Read collision error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "EnableInterrupts;, + * DisableInterrupts constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_DisableInterrupts(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define FTFL_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + FTFL_FCNFG_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEraseAllRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the erase all request bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetEraseAllRequest(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEraseAllRequest(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_ERSAREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SuspendErasing + ---------------------------------------------------------------------------- */ + +/** + * @brief Suspends the current Erase Flash Sector command execution. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_SuspendErasing(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_SuspendErasing(PeripheralBase) ( \ + FTFL_FCNFG_REG(PeripheralBase) |= \ + FTFL_FCNFG_ERSSUSP_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRAMReady + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Ram ready bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetRAMReady(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetRAMReady(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_RAMRDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEEEReady + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the EEE ready bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetEEEReady(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEEEReady(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_EEERDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSecurityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Security register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadSecurityReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadSecurityReg(PeripheralBase) ( \ + FTFL_FSEC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBackdoorEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FTFL_PDD_BACKDOOR_KEY_ENABLED if backdoor key + * access is enabled else returns the FTFL_PDD_BACKDOOR_KEY_DISABLED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "BackDoorKey constants" type. The value is cast to + * "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetBackdoorEnable(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetBackdoorEnable(PeripheralBase) ( \ + (( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_KEYEN_MASK)) >> ( \ + FTFL_FSEC_KEYEN_SHIFT))) == ( \ + 0x2U)) ? ( \ + FTFL_PDD_BACKDOOR_KEY_ENABLED) : ( \ + FTFL_PDD_BACKDOOR_KEY_DISABLED) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMassEraseEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant MASS_ERASE_ENABLED if mass erase is enabled else + * returns the MASS_ERASE_DISABLED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Mass erase constants" type. The value is cast to + * "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetMassEraseEnable(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetMassEraseEnable(PeripheralBase) ( \ + (( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_MEEN_MASK)) >> ( \ + FTFL_FSEC_MEEN_SHIFT))) == ( \ + 0x2U)) ? ( \ + FTFL_PDD_MASS_ERASE_DISABLED) : ( \ + FTFL_PDD_MASS_ERASE_ENABLED) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFactoryAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FACTORY_ACCESS_GRANTED if access to the flash + * memory contents is enabled else returns the FACTORY_ACCESS_DENIED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Factory access constants" type. The value is cast + * to "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetFactoryAccess(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetFactoryAccess(PeripheralBase) ( \ + ((uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_FSLACC_MASK) == 0U) ? ( \ + FTFL_PDD_FACTORY_ACCESS_GRANTED) : ((( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_FSLACC_MASK)) >> ( \ + FTFL_FSEC_FSLACC_SHIFT))) == ( \ + 0x3U)) ? ( \ + FTFL_PDD_FACTORY_ACCESS_GRANTED) : ( \ + FTFL_PDD_FACTORY_ACCESS_DENIED) \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSecurityState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FTFL_PDD_SECURED if MCU is in secure state else + * returns the FTFL_PDD_UNSECURED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Security state constants" type. The value is cast + * to "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetSecurityState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetSecurityState(PeripheralBase) ( \ + ((uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_SEC_MASK) == 0x2U) ? ( \ + FTFL_PDD_UNSECURED) : ( \ + FTFL_PDD_SECURED) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOptionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Optional register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FOPT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadOptionReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadOptionReg(PeripheralBase) ( \ + FTFL_FOPT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB0Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB0Reg(PeripheralBase) ( \ + FTFL_FCCOB0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB1Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB1Reg(PeripheralBase) ( \ + FTFL_FCCOB1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB2. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB2Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB2Reg(PeripheralBase) ( \ + FTFL_FCCOB2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB3. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB3Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB3Reg(PeripheralBase) ( \ + FTFL_FCCOB3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB4Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB4Reg(PeripheralBase) ( \ + FTFL_FCCOB4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB5Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB5Reg(PeripheralBase) ( \ + FTFL_FCCOB5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB6Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB6Reg(PeripheralBase) ( \ + FTFL_FCCOB6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB7Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB7Reg(PeripheralBase) ( \ + FTFL_FCCOB7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 8. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB8Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB8Reg(PeripheralBase) ( \ + FTFL_FCCOB8_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB9Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 9. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB9Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB9Reg(PeripheralBase) ( \ + FTFL_FCCOB9_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOBAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register A. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOBAReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOBAReg(PeripheralBase) ( \ + FTFL_FCCOBA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOBBReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register B. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOBBReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOBBReg(PeripheralBase) ( \ + FTFL_FCCOBB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB0 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB0Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB0Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB1Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB1Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB2. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB2Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB2Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB3register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB3 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB3. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB3Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB3Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB4 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB4Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB4Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB5 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB5Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB5Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB6 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB6Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB6Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB7 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB7Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB7Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB8 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB8Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB8Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB9Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB9 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB9 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB9Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB9Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOBA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOBA register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBAReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBAReg(PeripheralBase, Value) ( \ + FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBBReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOBB register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOBB register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBBReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBBReg(PeripheralBase, Value) ( \ + FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFCCOBCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB Command register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Command Value written to the FCCOB Command register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * FTFL_PDD_SetFCCOBCommand(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_SetFCCOBCommand(PeripheralBase, Command) ( \ + FTFL_FCCOB0_REG(PeripheralBase) = \ + (uint8)(Command) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFCCOBAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Value written to the FCCOB Address register. This parameter is + * a 24-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB3, + * FTFL_FCCOB2, FTFL_FCCOB1 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_SetFCCOBAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_SetFCCOBAddress(PeripheralBase, Address) ( \ + (FTFL_FCCOB3_REG(PeripheralBase) = \ + (uint8)(Address)), \ + ((FTFL_FCCOB2_REG(PeripheralBase) = \ + (uint8)((uint32)(Address) >> 8U)), \ + (FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)((uint32)(Address) >> 16U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 0 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData0(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData0(PeripheralBase, Data) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 1 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData1(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData1(PeripheralBase, Data) ( \ + FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 2 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData2(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData2(PeripheralBase, Data) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 3 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData3(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData3(PeripheralBase, Data) ( \ + FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 4 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData4(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData4(PeripheralBase, Data) ( \ + FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData5 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 5 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData5(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData5(PeripheralBase, Data) ( \ + FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData6 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 6 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData6(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData6(PeripheralBase, Data) ( \ + FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData7 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 7 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData7(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData7(PeripheralBase, Data) ( \ + FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBFirstLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets first longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBFirstLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBFirstLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBSecondLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets second longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8, + * FTFL_FCCOB9, FTFL_FCCOBA, FTFL_FCCOBB (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBSecondLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBSecondLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets program Flash protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions Protected regions. This parameter is a 32-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * FTFL_PDD_SetPFlashProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetPFlashProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + *(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)) |= \ + (uint32)(Regions)) : ( \ + *(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)) &= \ + (uint32)(~(uint32)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns program falsh protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_GetPFlashProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetPFlashProtectionState(PeripheralBase) ( \ + (uint32)(~(*(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT0. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection0Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection0Reg(PeripheralBase) ( \ + FTFL_FPROT0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 0 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT0. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection0Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection0Reg(PeripheralBase, Value) ( \ + FTFL_FPROT0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT1. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection1Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection1Reg(PeripheralBase) ( \ + FTFL_FPROT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 1 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT1. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection1Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection1Reg(PeripheralBase, Value) ( \ + FTFL_FPROT1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT2. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection2Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection2Reg(PeripheralBase) ( \ + FTFL_FPROT2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 2 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT2. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection2Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection2Reg(PeripheralBase, Value) ( \ + FTFL_FPROT2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection3Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection3Reg(PeripheralBase) ( \ + FTFL_FPROT3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 3 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection3Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection3Reg(PeripheralBase, Value) ( \ + FTFL_FPROT3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns all error flags in the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetErrorFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetErrorFlags(PeripheralBase) ( \ + (uint8)(( \ + FTFL_FSTAT_REG(PeripheralBase)) & ( \ + (uint8)(( \ + FTFL_FSTAT_RDCOLERR_MASK) | (( \ + FTFL_FSTAT_ACCERR_MASK) | (( \ + FTFL_FSTAT_FPVIOL_MASK) | ( \ + FTFL_FSTAT_MGSTAT0_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear all error flags in the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearErrorFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearErrorFlags(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(FTFL_FSTAT_RDCOLERR_MASK | (FTFL_FSTAT_ACCERR_MASK | FTFL_FSTAT_FPVIOL_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCompleteFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Command complete" flag is set otherwise + * returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetCmdCompleteFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCompleteFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_CCIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadCollisionErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Read collision error" flag is set + * otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetReadCollisionErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetReadCollisionErrorFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_RDCOLERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAccessErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Access error" flag is set otherwise + * returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetAccessErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetAccessErrorFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_ACCERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetProtectionViolationFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Protection violationr" flag is set + * otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetProtectionViolationFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetProtectionViolationFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_FPVIOL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCompleteStatusFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Memory controller command completion + * status" flag is set otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetCmdCompleteStatusFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCompleteStatusFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_MGSTAT0_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartCmd + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts commad execution. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_StartCmd(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_StartCmd(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + FTFL_FSTAT_CCIF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current command (value of the FCCOB0 register). This macro + * is common for all commands. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetCmdCode(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCode(PeripheralBase) ( \ + FTFL_FCCOB0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s block command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_Init(_BASE_PTR, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_Init(PeripheralBase, Address, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_BLOCK << 24), \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_Read1sBlock_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_BLOCK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sBlock_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB4_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s section command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block to be verified. This + * parameter is a 24-bit value. + * @param SectionUnitCount Number of section units to be verified. This + * parameter is a 16-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_Init(_BASE_PTR, 1, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_Init(PeripheralBase, Address, SectionUnitCount, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_SECTION << 24), \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = (SectionUnitCount << 16) | (MarginLevel << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_Read1sSection_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_SECTION << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the size field of the command (value of the FCCOB4-FCC0B5 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @par Example: + * @code + * uint16 result = + * FTFL_PDD_Cmd_Read1sSection_GetSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetSize(PeripheralBase) ( \ + (uint16)((*(uint16 *)(void *)&(FTFL_FCCOB5_REG(PeripheralBase)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the size field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SectionUnitCount Number of section units to be verified. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetSize(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetSize(PeripheralBase, SectionUnitCount) ( \ + *(uint16*)&FTFL_FCCOB5_REG(PeripheralBase) = (SectionUnitCount) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sSection_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB6_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program check command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be longword aligned. + * This parameter is a 24-bit value. + * @param Data Expected data. This parameter is a 32-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_Init(_BASE_PTR, 1, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_Init(PeripheralBase, Address, Data, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_CHECK << 24), \ + ((FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel)), \ + *(uint32*)&FTFL_FCCOBB_REG(PeripheralBase) = Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramCheck_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be longword aligned. + * This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_CHECK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the data field of the command (FCCOB8-FCC0BB registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramCheck_GetData(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetData(PeripheralBase) ( \ + (uint32)(*(uint32 *)(void *)&FTFL_FCCOBB_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field of the command (FCCOB8-FCC0BB registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Expected data. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetData(PeripheralBase, Data) ( \ + *(uint32*)&FTFL_FCCOBB_REG(PeripheralBase) = Data \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ProgramCheck_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB4_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program longword command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be 32-bit aligned. This + * parameter is a 24-bit value. + * @param Data Longword to be written. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_Init(_BASE_PTR, 1, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_Init(PeripheralBase, Address, Data) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24), \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = Data \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_getAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramLongword_getAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_getAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_GetDWord + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the data field of the command (FCCOB4-FCC0B7 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramLongword_GetDWord(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_GetDWord(PeripheralBase) ( \ + (uint32)(*(uint32 *)(void *)&FTFL_FCCOB7_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_SetDWord + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field of the command (FCCOB4-FCC0B7 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param DWord Expected data. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_SetDWord(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_SetDWord(PeripheralBase, DWord) ( \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = DWord \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase flash block command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block to be erased. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseFlashBlock_Init(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_Init(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_ERASE_FLASH_BLOCK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_EraseFlashBlock_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseFlashBlock_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase flash sector command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash sector to be erased. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseSector_Init(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_Init(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_ERASE_FLASH_SECTOR << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_EraseSector_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash sector. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseSector_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s all blocks command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sAllBlocks_Init(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_Init(PeripheralBase, MarginLevel) ( \ + *(uint16*)&FTFL_FCCOB1_REG(PeripheralBase) = MarginLevel | (FTFL_PDD_READ_1S_ALL_BLOCKS << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB1 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sAllBlocks_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB1_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB1 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sAllBlocks_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseAllBlocks_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase all blocks command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseAllBlocks_Init(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseAllBlocks_Init(PeripheralBase) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_ERASE_ALL_BLOCKS \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramPartition_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program partition command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EepromDataSize EEPROM data size and split factor(if supported) code. + * Use constants from group "EEPROM size constants". This parameter is 8 + * bits wide. + * @param EepromBackupSize EEPROM backup size. Use constants from group "EEPROM + * backup size constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramPartition_Init(_BASE_PTR, + * FTFL_PDD_EEPROM_DATA_SIZE_0_B, FTFL_PDD_EEPROM_BACKUP_SIZE_0_KB); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramPartition_Init(PeripheralBase, EepromDataSize, EepromBackupSize) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_PROGRAM_PARTITION, \ + (*(uint8*)&FTFL_FCCOB4_REG(PeripheralBase) = EepromDataSize, \ + *(uint8*)&FTFL_FCCOB5_REG(PeripheralBase) = EepromBackupSize) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read Resource command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ReadPartition_Init(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_Init(PeripheralBase) ( \ + *(uint8*)&FTFL_FCCOB8_REG(PeripheralBase) = 0x00, \ + (*(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = 0x00800000 | 0xFC | (FTFL_PDD_READ_RESOURCE << 24), \ + *(uint8*)&FTFL_FCCOB8_REG(PeripheralBase) = FTFL_PDD_RESOURCE_IFR) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_GetEepromDataSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ReadPartition_GetEepromDataSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_GetEepromDataSize(PeripheralBase) ( \ + FTFL_FCCOB4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_GetEepromBackUpSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ReadPartition_GetEepromBackUpSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_GetEepromBackUpSize(PeripheralBase) ( \ + FTFL_FCCOB5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_SetFlexRAMFunction_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Set FlexRAM Function command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Function FrexRam function choice. Use constants from group "FlexRAM + * function constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_SetFlexRAMFunction_Init(_BASE_PTR, + * FTFL_PDD_FLEXRAM_AS_RAM); + * @endcode + */ +#define FTFL_PDD_Cmd_SetFlexRAMFunction_Init(PeripheralBase, Function) ( \ + *(uint16*)&FTFL_FCCOB1_REG(PeripheralBase) = Function | (FTFL_PDD_SET_EERAM_FUCTION << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_VerifyBackdoorAccessKey_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Verify Backdoor Access Key command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Key0 Key 0. This parameter is a 8-bit value. + * @param Key1 Key 0. This parameter is a 8-bit value. + * @param Key2 Key 0. This parameter is a 8-bit value. + * @param Key3 Key 0. This parameter is a 8-bit value. + * @param Key4 Key 0. This parameter is a 8-bit value. + * @param Key5 Key 0. This parameter is a 8-bit value. + * @param Key6 Key 0. This parameter is a 8-bit value. + * @param Key7 Key 0. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7, FTFL_FCCOB8, FTFL_FCCOB9, FTFL_FCCOBA, + * FTFL_FCCOBB (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_Cmd_VerifyBackdoorAccessKey_Init(_BASE_PTR, 1, 1, + * 1, 1, 1, 1, 1, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_VerifyBackdoorAccessKey_Init(PeripheralBase, Key0, Key1, Key2, Key3, Key4, Key5, Key6, Key7) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_VERIFY_BACKDOOR_ACCESS_KEY, \ + ((FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Key0)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Key1)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Key2)), \ + ((FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Key3)), \ + ((FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Key4)), \ + ((FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Key5)), \ + ((FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Key6)), \ + (FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Key7))))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data Flash protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions FTFL_PDD_PROTECTED or FTFL_PDD_UNPROTECTED. This parameter is + * a 8-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FDPROT. + * @par Example: + * @code + * FTFL_PDD_SetDFlashProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetDFlashProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + FTFL_FDPROT_REG(PeripheralBase) |= \ + (uint8)(Regions)) : ( \ + FTFL_FDPROT_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the returned value represent 1/8 of the Data FLASH memory. + * If the bit is set the region is protected else the region is unprotected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FDPROT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetDFlashProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetDFlashProtectionState(PeripheralBase) ( \ + (uint8)(~(uint8)FTFL_FDPROT_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetEERAMProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the Region parameter represent 1/8 of the EERPROM memory. + * To change the protection state of the region(s) select requested regions + * (Region param) and set new state (State param). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions Protected regions. This parameter is a 8-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FEPROT. + * @par Example: + * @code + * FTFL_PDD_SetEERAMProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetEERAMProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + FTFL_FEPROT_REG(PeripheralBase) |= \ + (uint8)(Regions)) : ( \ + FTFL_FEPROT_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEERAMProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the returned value represent 1/8 of the EERPROM memory. If + * the bit is set the region is protected else the region is unprotected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FEPROT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetEERAMProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEERAMProtectionState(PeripheralBase) ( \ + (uint8)(~(uint8)FTFL_FEPROT_REG(PeripheralBase)) \ + ) +#endif /* #if defined(FTFL_PDD_H_) */ + +/* FTFL_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h new file mode 100644 index 0000000..242a599 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h @@ -0,0 +1,5072 @@ +/* + PDD layer implementation for peripheral type FTM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FTM_PDD_H_) +#define FTM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FTM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK10D5) /* FTM0, FTM1 */ && \ + !defined(MCU_MK10D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK10F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK10DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK11D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK11D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK12D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20D5) /* FTM0, FTM1 */ && \ + !defined(MCU_MK20D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK20DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK21F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK22D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F12810) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK22F25612) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F51212) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK24F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK30D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK30D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK30DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40X256VMD100) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK52D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK52DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK53D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK53DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK60F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK60DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60N512VMD100) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK61F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F15WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK63F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK63F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK64F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK65F18) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK65F18WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK66F18) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F15WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MKE02Z2) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE02Z4) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_SKEAZN642) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE04Z1284) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE04Z4) /* FTM0, FTM2 */ && \ + !defined(MCU_SKEAZN84) /* FTM0, FTM2 */ && \ + !defined(MCU_MKE06Z4) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV10Z7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F12810) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F25612) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F51212) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MKW21D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW21D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW22D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW22D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW24D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW24D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_PCK20L4) /* FTM0, FTM1 */ && \ + !defined(MCU_SKEAZ1284) /* FTM0, FTM1, FTM2 */ + // Unsupported MCU is active + #error FTM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* FTM channel constants */ +#define FTM_PDD_CHANNEL_0 0U /**< 0 */ +#define FTM_PDD_CHANNEL_1 0x1U /**< 1 */ +#define FTM_PDD_CHANNEL_2 0x2U /**< 2 */ +#define FTM_PDD_CHANNEL_3 0x3U /**< 3 */ +#define FTM_PDD_CHANNEL_4 0x4U /**< 4 */ +#define FTM_PDD_CHANNEL_5 0x5U /**< 5 */ +#define FTM_PDD_CHANNEL_6 0x6U /**< 6 */ +#define FTM_PDD_CHANNEL_7 0x7U /**< 7 */ + +/* Prescaler constants */ +#define FTM_PDD_DIVIDE_1 0U /**< 1 */ +#define FTM_PDD_DIVIDE_2 0x1U /**< 2 */ +#define FTM_PDD_DIVIDE_4 0x2U /**< 4 */ +#define FTM_PDD_DIVIDE_8 0x3U /**< 8 */ +#define FTM_PDD_DIVIDE_16 0x4U /**< 16 */ +#define FTM_PDD_DIVIDE_32 0x5U /**< 32 */ +#define FTM_PDD_DIVIDE_64 0x6U /**< 64 */ +#define FTM_PDD_DIVIDE_128 0x7U /**< 128 */ + +/* PWM aligned mode constants */ +#define FTM_PDD_EDGE_ALIGNED 0U /**< Edge aligned */ +#define FTM_PDD_CENTER_ALIGNED FTM_SC_CPWMS_MASK /**< Center aligned */ + +/* Interrupt flag masks for ClearChannelFlag */ +#define FTM_PDD_FLAG_0 0x1U /**< 0 */ +#define FTM_PDD_FLAG_1 0x2U /**< 1 */ +#define FTM_PDD_FLAG_2 0x4U /**< 2 */ +#define FTM_PDD_FLAG_3 0x8U /**< 3 */ +#define FTM_PDD_FLAG_4 0x10U /**< 4 */ +#define FTM_PDD_FLAG_5 0x20U /**< 5 */ +#define FTM_PDD_FLAG_6 0x40U /**< 6 */ +#define FTM_PDD_FLAG_7 0x80U /**< 7 */ + +/* FTM channel masks. */ +#define FTM_PDD_CHANNEL_0_MASK 0x1U /**< Channel 0 mask */ +#define FTM_PDD_CHANNEL_1_MASK 0x2U /**< Channel 1 mask */ +#define FTM_PDD_CHANNEL_2_MASK 0x4U /**< Channel 2 mask */ +#define FTM_PDD_CHANNEL_3_MASK 0x8U /**< Channel 3 mask */ +#define FTM_PDD_CHANNEL_4_MASK 0x10U /**< Channel 4 mask */ +#define FTM_PDD_CHANNEL_5_MASK 0x20U /**< Channel 5 mask */ +#define FTM_PDD_CHANNEL_6_MASK 0x40U /**< Channel 6 mask */ +#define FTM_PDD_CHANNEL_7_MASK 0x80U /**< Channel 7 mask */ + +/* Deadtime prescaler constants */ +#define FTM_PDD_DT_DIVIDE_1 0U /**< 1 */ +#define FTM_PDD_DT_DIVIDE_4 0x2U /**< 4 */ +#define FTM_PDD_DT_DIVIDE_16 0x3U /**< 16 */ + +/* Clock source constants. */ +#define FTM_PDD_DISABLED 0U /**< Disabled */ +#define FTM_PDD_SYSTEM 0x8U /**< System clock */ +#define FTM_PDD_FIXED 0x10U /**< Fixed clock */ +#define FTM_PDD_EXTERNAL 0x18U /**< External clock */ + +/* Edge and level constants. */ +#define FTM_PDD_EDGE_NONE 0U /**< Disabled */ +#define FTM_PDD_EDGE_RISING 0x4U /**< Rising */ +#define FTM_PDD_EDGE_FALLING 0x8U /**< Falling */ +#define FTM_PDD_EDGE_BOTH 0xCU /**< Both */ + +/* Output action constants. */ +#define FTM_PDD_OUTPUT_NONE 0U /**< Disconnect */ +#define FTM_PDD_OUTPUT_TOGGLE 0x10U /**< Toggle */ +#define FTM_PDD_OUTPUT_CLEAR 0x20U /**< Clear */ +#define FTM_PDD_OUTPUT_SET 0x30U /**< Set */ + +/* Fault mode constants. */ +#define FTM_PDD_FAULT_DISABLED 0U /**< Fault control is disabled for all channels. */ +#define FTM_PDD_FAULT_EVEN_MANUAL 0x20U /**< Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. */ +#define FTM_PDD_FAULT_ALL_MANUAL 0x40U /**< Fault control is enabled for all channels, and the selected mode is the manual fault clearing. */ +#define FTM_PDD_FAULT_ALL_AUTOMATIC 0x60U /**< Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. */ + +/* PWM synchronization mode constants. */ +#define FTM_PDD_NO_RESTRICTIONS 0U /**< Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. */ +#define FTM_PDD_WITH_RESTRICTIONS 0x8U /**< Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. */ + +/* Output mask synchronization constants. */ +#define FTM_PDD_RISING_EDGES 0U /**< OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. */ +#define FTM_PDD_PWM_SYNCHRONIZATION 0x8U /**< OUTMASK register is updated with the value of its buffer only by the PWM synchronization. */ + +/* FTM counter synchronization constants. */ +#define FTM_PDD_COUNT_NORMALLY 0U /**< FTM counter continues to count normally. */ +#define FTM_PDD_UPDATE 0x4U /**< FTM counter is updated with its initial value when the selected trigger is detected. */ + +/* Phase input polarity constants. */ +#define FTM_PDD_QD_NORMAL_POLARITY 0U /**< Phase input signal is not inverted before identifying the rising and falling edges of this signal. */ +#define FTM_PDD_QD_INVERTED_POLARITY 0x1U /**< Phase input signal is inverted before identifying the rising and falling edges of this signal. */ + +/* Quadrature decoder encoding mode constants. */ +#define FTM_PDD_QD_PHASEA_AND_PHASEB 0U /**< Phase A and phase B encoding mode. */ +#define FTM_PDD_QD_COUNT_AND_DIRECTION 0x8U /**< Count and direction encoding mode. */ + +/* BDM mode constants. */ +#define FTM_PDD_BDM_00 0U /**< FTM counter: stopped. CH(n)F bit: can be set. FTM Channels Output: Functional mode. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_01 0x40U /**< FTM counter: stopped. CH(n)F bit: is not set. FTM Channels Output: The channels outputs are forced to their safe value according to POLn bit. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_10 0x80U /**< FTM counter: stopped. CH(n)F bit: is not set. FTM Channels Output: The channels outputs are frozen when the chip enters in BDM mode. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_11 0xC0U /**< FTM counter: Functional mode. CH(n)F bit: can be set. FTM Channels Output: Functional mode. Writes to MOD, CNTIN, and C(n)V registers: Functional mode. */ + +/* Fault input polarity constants. */ +#define FTM_PDD_FAULT_POLARITY_HIGH 0U /**< The fault input polarity is active high. A one at the fault input indicates a fault. */ +#define FTM_PDD_FAULT_POLARITY_LOW 0x1U /**< The fault input polarity is active low. A zero at the fault input indicates a fault. */ + +/* Synchronization mode constants. */ +#define FTM_PDD_SYNC_LEGACY 0U /**< Legacy PWM synchronization is selected. */ +#define FTM_PDD_SYNC_ENHANCED 0x80U /**< Enhanced PWM synchronization is selected. */ + +/* Register synchronization constants. */ +#define FTM_PDD_SYNC_BY_SYSTEM_CLOCK 0U /**< Register is updated with its buffer value at all rising edges of system clock. */ +#define FTM_PDD_SYNC_BY_PWM 0x1U /**< Register is updated with its buffer value by the PWM synchronization. */ + + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler constants". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPrescaler(_BASE_PTR, FTM_PDD_DIVIDE_1); + * @endcode + */ +#define FTM_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_PS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Prescaler))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Select clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPrescalerSource(_BASE_PTR, FTM_PDD_DISABLED); + * @endcode + */ +#define FTM_PDD_SelectPrescalerSource(PeripheralBase, Source) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_CLKS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of FTM device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_CLKS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPwmAlignMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures PWM aligned mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "PWM aligned mode + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPwmAlignMode(_BASE_PTR, FTM_PDD_EDGE_ALIGNED); + * @endcode + */ +#define FTM_PDD_SelectPwmAlignMode(PeripheralBase, Mode) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_CPWMS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOverflowInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns overflow interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetOverflowInterruptMask(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetOverflowInterruptMask(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_TOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_EnableOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_EnableOverflowInterrupt(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SC_REG(PeripheralBase) | FTM_SC_TOIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_DisableOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_DisableOverflowInterrupt(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_SC_TOIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOverflowInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns overflow interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetOverflowInterruptFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetOverflowInterruptFlag(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_TOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearOverflowInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears overflow interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_ClearOverflowInterruptFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ClearOverflowInterruptFlag(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_SC_TOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CNT, FTM1_CNT, + * FTM2_CNT, FTM3_CNT (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadCounterReg(PeripheralBase) ( \ + FTM_CNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- InitializeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value 0 to the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CNT, FTM1_CNT, + * FTM2_CNT, FTM3_CNT (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_InitializeCounter(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_InitializeCounter(PeripheralBase) ( \ + FTM_CNT_REG(PeripheralBase) = \ + 0U \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuloReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the modulo register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the modulo register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MOD, FTM1_MOD, + * FTM2_MOD, FTM3_MOD (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteModuloReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteModuloReg(PeripheralBase, Value) ( \ + FTM_MOD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuloReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the modulo register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_MOD, FTM1_MOD, + * FTM2_MOD, FTM3_MOD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadModuloReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadModuloReg(PeripheralBase) ( \ + FTM_MOD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannelDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM channel DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_EnableChannelDma(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_EnableChannelDma(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) | FTM_CnSC_DMA_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableChannelDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM channel DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_DisableChannelDma(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_DisableChannelDma(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_CnSC_DMA_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelEdgeLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the FTM channel edge and level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param ELSBA_val FTM channel ELSB:ELSA bits. This parameter is of "Edge and + * level constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SelectChannelEdgeLevel(_BASE_PTR, + * FTM_PDD_CHANNEL_0, FTM_PDD_EDGE_NONE); + * @endcode + */ +#define FTM_PDD_SelectChannelEdgeLevel(PeripheralBase, ChannelIdx, ELSBA_val) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)((uint32)0x3U << 2U))) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)(ELSBA_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the FTM channel mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param MSBA_val FTM channel MSB:MSA bits. This parameter is of "Output action + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SelectChannelMode(_BASE_PTR, FTM_PDD_CHANNEL_0, + * FTM_PDD_OUTPUT_NONE); + * @endcode + */ +#define FTM_PDD_SelectChannelMode(PeripheralBase, ChannelIdx, MSBA_val) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)((uint32)0x3U << 4U))) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)(MSBA_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetChannelInterruptMask(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_GetChannelInterruptMask(PeripheralBase, ChannelIdx) ( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) & FTM_CnSC_CHIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannelInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM channel interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_EnableChannelInterrupt(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_EnableChannelInterrupt(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) | FTM_CnSC_CHIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableChannelInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM channel interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_DisableChannelInterrupt(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_DisableChannelInterrupt(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_CnSC_CHIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetChannelInterruptFlag(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_GetChannelInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) & FTM_CnSC_CHF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_ClearChannelInterruptFlag(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ClearChannelInterruptFlag(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadChannelControlReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ReadChannelControlReg(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the channel status and control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_WriteChannelControlReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0, 1); + * @endcode + */ +#define FTM_PDD_WriteChannelControlReg(PeripheralBase, ChannelIdx, Value) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnV[ChannelIdx]. + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadChannelValueReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ReadChannelValueReg(PeripheralBase, ChannelIdx) ( \ + FTM_CnV_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the channel value register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnV[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_WriteChannelValueReg(_BASE_PTR, FTM_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define FTM_PDD_WriteChannelValueReg(PeripheralBase, ChannelIdx, Value) ( \ + FTM_CnV_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInitialValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the counter initial value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the counter initial value register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CNTIN, FTM1_CNTIN, + * FTM2_CNTIN, FTM3_CNTIN (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInitialValueReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInitialValueReg(PeripheralBase, Value) ( \ + FTM_CNTIN_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInitialValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter initial value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CNTIN, FTM1_CNTIN, + * FTM2_CNTIN, FTM3_CNTIN (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInitialValueReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInitialValueReg(PeripheralBase) ( \ + FTM_CNTIN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the capture and compare status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_STATUS, + * FTM1_STATUS, FTM2_STATUS, FTM3_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetChannelFlags(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetChannelFlags(PeripheralBase) ( \ + FTM_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt flag + * masks for ClearChannelFlag". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_STATUS, + * FTM1_STATUS, FTM2_STATUS, FTM3_STATUS (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_ClearChannelFlags(_BASE_PTR, FTM_PDD_FLAG_0); + * @endcode + */ +#define FTM_PDD_ClearChannelFlags(PeripheralBase, Mask) ( \ + FTM_STATUS_REG(PeripheralBase) = \ + (uint32)((uint32)(~(uint32)(Mask)) & (uint32)0xFFU) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFaultInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM fault interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_EnableFaultInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_EnableFaultInterrupt(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_FAULTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFaultInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM fault interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_DisableFaultInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_DisableFaultInterrupt(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_MODE_FAULTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProtectionDisable + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the write protection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteProtectionDisable(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_WriteProtectionDisable(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_WPDIS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InitializeOutputs + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialize the channel outputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_InitializeOutputs(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_InitializeOutputs(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_INIT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFeaturesModeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the feature mode selection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the feature mode selection register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFeaturesModeReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFeaturesModeReg(PeripheralBase, Value) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFeaturesModeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the features mode selection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFeaturesModeReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFeaturesModeReg(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSynchronizationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the synchronization register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the synchronization register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSynchronizationReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSynchronizationReg(PeripheralBase, Value) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSynchronizationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the synchronization register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadSynchronizationReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSynchronizationReg(PeripheralBase) ( \ + FTM_SYNC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInitialOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the initial state for channels output register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the initial state for channel output register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_OUTINIT, + * FTM1_OUTINIT, FTM2_OUTINIT, FTM3_OUTINIT (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInitialOutputReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInitialOutputReg(PeripheralBase, Value) ( \ + FTM_OUTINIT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInitialOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the initial state for channels output register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_OUTINIT, + * FTM1_OUTINIT, FTM2_OUTINIT, FTM3_OUTINIT (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInitialOutputReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInitialOutputReg(PeripheralBase) ( \ + FTM_OUTINIT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOutputMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the output mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the output mask register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_OUTMASK, + * FTM1_OUTMASK, FTM2_OUTMASK, FTM3_OUTMASK (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteOutputMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteOutputMaskReg(PeripheralBase, Value) ( \ + FTM_OUTMASK_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOutputMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the output mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_OUTMASK, + * FTM1_OUTMASK, FTM2_OUTMASK, FTM3_OUTMASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadOutputMaskReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadOutputMaskReg(PeripheralBase) ( \ + FTM_OUTMASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCombineReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the function for linked channels register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the function for linked channels register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteCombineReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteCombineReg(PeripheralBase, Value) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCombineReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the function for linked channels register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadCombineReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadCombineReg(PeripheralBase) ( \ + FTM_COMBINE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDeadtimeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the deadtime insertion control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the deadtime insertion control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteDeadtimeReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteDeadtimeReg(PeripheralBase, Value) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDeadtimeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the deadtime insertion control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadDeadtimeReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadDeadtimeReg(PeripheralBase) ( \ + FTM_DEADTIME_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteExternalTriggerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM external trigger register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM external trigger register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteExternalTriggerReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteExternalTriggerReg(PeripheralBase, Value) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExternalTriggerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM external trigger register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadExternalTriggerReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadExternalTriggerReg(PeripheralBase) ( \ + FTM_EXTTRIG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channels polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the channels polarity register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_POL, FTM1_POL, + * FTM2_POL, FTM3_POL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WritePolarityReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WritePolarityReg(PeripheralBase, Value) ( \ + FTM_POL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channels polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_POL, FTM1_POL, + * FTM2_POL, FTM3_POL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadPolarityReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadPolarityReg(PeripheralBase) ( \ + FTM_POL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the fault mode status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FMS, FTM1_FMS, + * FTM2_FMS, FTM3_FMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFaultStatusReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultStatusReg(PeripheralBase) ( \ + FTM_FMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProtectionEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the write protection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FMS, FTM1_FMS, + * FTM2_FMS, FTM3_FMS (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteProtectionEnable(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_WriteProtectionEnable(PeripheralBase) ( \ + FTM_FMS_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_FMS_REG(PeripheralBase) | FTM_FMS_WPEN_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF0_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF1_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF2_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF3_MASK)) & ( \ + (uint32)(~(uint32)FTM_FMS_FAULTF_MASK))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInputCaptureFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the input capture filter control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the input capture filter control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInputCaptureFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInputCaptureFilterReg(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInputCaptureFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the input capture filter control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadInputCaptureFilterReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInputCaptureFilterReg(PeripheralBase) ( \ + FTM_FILTER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFaultControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the fault control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the fault control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFaultControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFaultControlReg(PeripheralBase, Value) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the fault control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFaultControlReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultControlReg(PeripheralBase) ( \ + FTM_FLTCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteQuadratureDecoderReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the quadrature decoder control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the quadrature decoder control and status + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteQuadratureDecoderReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteQuadratureDecoderReg(PeripheralBase, Value) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadQuadratureDecoderReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the quadrature decoder control and status + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadQuadratureDecoderReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadQuadratureDecoderReg(PeripheralBase) ( \ + FTM_QDCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the configuration register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteConfigurationReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteConfigurationReg(PeripheralBase, Value) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadConfigurationReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadConfigurationReg(PeripheralBase) ( \ + FTM_CONF_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFaultInputPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM fault input polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM fault input polarity register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFaultInputPolarityReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFaultInputPolarityReg(PeripheralBase, Value) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultInputPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM fault input polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadFaultInputPolarityReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultInputPolarityReg(PeripheralBase) ( \ + FTM_FLTPOL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSynchronizationConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the synchronization configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the synchronization configuration register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSynchronizationConfigReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSynchronizationConfigReg(PeripheralBase, Value) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSynchronizationConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the synchronization configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadSynchronizationConfigReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSynchronizationConfigReg(PeripheralBase) ( \ + FTM_SYNCONF_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInvertingReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM inverting control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM inverting control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInvertingReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInvertingReg(PeripheralBase, Value) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInvertingReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM inverting control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInvertingReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInvertingReg(PeripheralBase) ( \ + FTM_INVCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSoftwareOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM software output control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM software output control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SWOCTRL, + * FTM1_SWOCTRL, FTM2_SWOCTRL, FTM3_SWOCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSoftwareOutputReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSoftwareOutputReg(PeripheralBase, Value) ( \ + FTM_SWOCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSoftwareOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM software output control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SWOCTRL, + * FTM1_SWOCTRL, FTM2_SWOCTRL, FTM3_SWOCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadSoftwareOutputReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSoftwareOutputReg(PeripheralBase) ( \ + FTM_SWOCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePwmLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM PWM load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM PWM load register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_PWMLOAD, + * FTM1_PWMLOAD, FTM2_PWMLOAD, FTM3_PWMLOAD (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WritePwmLoadReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WritePwmLoadReg(PeripheralBase, Value) ( \ + FTM_PWMLOAD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPwmLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM PWM load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_PWMLOAD, + * FTM1_PWMLOAD, FTM2_PWMLOAD, FTM3_PWMLOAD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadPwmLoadReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadPwmLoadReg(PeripheralBase) ( \ + FTM_PWMLOAD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the status and control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadStatusControlReg(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCounterResetByCapture + ---------------------------------------------------------------------------- */ + +/** + * @brief Counter reset is driven by the selected event of the channel (n) in + * the Input Capture mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param State Requested state of FTM counter reset when the selected channel + * (n) input event is detected. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SetCounterResetByCapture(_BASE_PTR, + * FTM_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCounterResetByCapture(PeripheralBase, ChannelIdx, State) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)FTM_CnSC_ICRST_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_CnSC_ICRST_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultControlMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Select the FTM fault control mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault control mode. This parameter is of "Fault + * mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultControlMode(_BASE_PTR, + * FTM_PDD_FAULT_DISABLED); + * @endcode + */ +#define FTM_PDD_SelectFaultControlMode(PeripheralBase, Mode) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_FAULTM_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCaptureTestMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture test mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the capture test mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCaptureTestMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCaptureTestMode(PeripheralBase, State) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_CAPTEST_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_MODE_CAPTEST_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPWMSynchronizationMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM + * counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the PWM synchronization mode. This parameter is of + * "PWM synchronization mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPWMSynchronizationMode(_BASE_PTR, + * FTM_PDD_NO_RESTRICTIONS); + * @endcode + */ +#define FTM_PDD_SelectPWMSynchronizationMode(PeripheralBase, Mode) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_PWMSYNC_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFTMEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables all registers including the FTM-specific registers (second set + * of registers) are available for use with no restrictions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the FTM enable. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFTMEnable(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFTMEnable(PeripheralBase, State) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_FTMEN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- PWMSoftwareTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the software trigger as the PWM synchronization trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_PWMSoftwareTrigger(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_PWMSoftwareTrigger(PeripheralBase) ( \ + FTM_SYNC_REG(PeripheralBase) |= \ + FTM_SYNC_SWSYNC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 2 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 2. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger2(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG2_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 1 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 1. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger1(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG1_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 0 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 0. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger0(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG0_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectOutputMaskSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects when the OUTMASK register is updated with the value of its + * buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the output mask synchronization. This parameter is + * of "Output mask synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectOutputMaskSynchronization(_BASE_PTR, + * FTM_PDD_RISING_EDGES); + * @endcode + */ +#define FTM_PDD_SelectOutputMaskSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_SYNCHOM_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFTMCounterSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Determines if the FTM counter is reinitialized when the selected + * trigger for the synchronization is detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the FTM counter synchronization. This parameter is + * of "FTM counter synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFTMCounterSynchronization(_BASE_PTR, + * FTM_PDD_COUNT_NORMALLY); + * @endcode + */ +#define FTM_PDD_SelectFTMCounterSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_REINIT_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaximumLoadingPoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the maximum loading point to PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the maximum loading point to PWM + * synchronization. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetMaximumLoadingPoint(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetMaximumLoadingPoint(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_CNTMAX_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_CNTMAX_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinimumLoadingPoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the minimum loading point to PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the maximum loading point to PWM + * synchronization. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetMinimumLoadingPoint(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetMinimumLoadingPoint(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_CNTMIN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C6V and C7V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C4V and C5V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C2V and C3V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C0V and C1V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures6 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 6 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 6. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures6(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures6(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 4 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 4. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures4(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures4(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 2 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 2. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures2(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 0 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 0. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures0(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 7 output is the inverse of the channel 6 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 5 output is the inverse of the channel 4 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 3 output is the inverse of the channel 2 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 1 output is the inverse of the channel 0 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE0_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadtimePrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets deadtime prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the deadtime prescaler. Use constants from + * group "Deadtime prescaler constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadtimePrescaler(_BASE_PTR, + * FTM_PDD_DT_DIVIDE_1); + * @endcode + */ +#define FTM_PDD_SetDeadtimePrescaler(PeripheralBase, Prescaler) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_DEADTIME_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_DEADTIME_DTPS_MASK)))) | ( \ + (uint32)((uint32)(Prescaler) << FTM_DEADTIME_DTPS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadtimeValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the deadtime insertion value for the deadtime counter. The + * deadtime counter is clocked by a scaled version of the system clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the deadtime. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadtimeValue(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetDeadtimeValue(PeripheralBase, Value) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_DEADTIME_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_DEADTIME_DTVAL_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelTriggerFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel trigger flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetChannelTriggerFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetChannelTriggerFlag(PeripheralBase) ( \ + (uint32)(FTM_EXTTRIG_REG(PeripheralBase) & FTM_EXTTRIG_TRIGF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInitializationTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the generation of the trigger when the FTM counter is equal to + * the CNTIN register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the generation of the trigger. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInitializationTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetInitializationTrigger(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_INITTRIGEN_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_INITTRIGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C0V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 0 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger0(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH0TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH0TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C1V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 1 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger1(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH1TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH1TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C2V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 2 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger2(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH2TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C3V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 3 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger3(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH3TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH3TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C4V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 4 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger4(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger4(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH4TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH4TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger5 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C5V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 5 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger5(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger5(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH5TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH5TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter3(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter3(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH3FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH3FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter2(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter2(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH2FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH2FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter1(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter1(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH1FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH1FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter0(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter0(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH0FVAL_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInpuFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the fault inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the fault input filter. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInpuFilter(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetFaultInpuFilter(PeripheralBase, Value) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FLTCTRL_FFVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter3(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter2(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter1(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter0(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR0EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR0EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput3(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput2(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput1(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput0(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT0EN_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseAInputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the quadrature decoder phase A input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the filter for quadrature decoder. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPhaseAInputFilter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPhaseAInputFilter(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_PHAFLTREN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_QDCTRL_PHAFLTREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseBInputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the quadrature decoder phase B input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the filter for quadrature decoder. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPhaseBInputFilter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPhaseBInputFilter(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_PHBFLTREN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_QDCTRL_PHBFLTREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPhaseAInputPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity for the quadrature decoder phase A input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the phase A input polarity. This parameter is of + * "Phase input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPhaseAInputPolarity(_BASE_PTR, + * FTM_PDD_QD_NORMAL_POLARITY); + * @endcode + */ +#define FTM_PDD_SelectPhaseAInputPolarity(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_PHAPOL_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_QDCTRL_PHAPOL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPhaseBInputPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity for the quadrature decoder phase B input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the phase B input polarity. This parameter is of + * "Phase input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPhaseBInputPolarity(_BASE_PTR, + * FTM_PDD_QD_NORMAL_POLARITY); + * @endcode + */ +#define FTM_PDD_SelectPhaseBInputPolarity(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_PHBPOL_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_QDCTRL_PHBPOL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectQDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the encoding mode used in the quadrature decoder mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the quadrature decoder encoding mode. This parameter + * is of "Quadrature decoder encoding mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectQDMode(_BASE_PTR, + * FTM_PDD_QD_PHASEA_AND_PHASEB); + * @endcode + */ +#define FTM_PDD_SelectQDMode(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_QUADMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetQDCounterDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates the counting direction in quadrature mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetQDCounterDirection(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetQDCounterDirection(PeripheralBase) ( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & FTM_QDCTRL_QUADIR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetQDTimerOverflowDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates if the TOF bit was set on the top or the bottom of counting + * in quadrature decoder mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetQDTimerOverflowDirection(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetQDTimerOverflowDirection(PeripheralBase) ( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & FTM_QDCTRL_TOFDIR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetQDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the quadrature decoder mode. In this mode, the phase A and B + * input signals control the FTM counter direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the quadrature decoder. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetQDMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetQDMode(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_QUADEN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalTimeBaseOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the global time base signal generation to other FTMs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the global time base output. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetGlobalTimeBaseOutput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetGlobalTimeBaseOutput(PeripheralBase, State) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_GTBEOUT_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_CONF_GTBEOUT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalTimeBase + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM to use an external global time base signal that is + * generated by another FTM. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the global time base output. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetGlobalTimeBase(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetGlobalTimeBase(PeripheralBase, State) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_GTBEEN_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_CONF_GTBEEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectBDMMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects Selects the FTM behavior in BDM mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the quadrature decoder encoding mode. This parameter + * is of "BDM mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectBDMMode(_BASE_PTR, FTM_PDD_BDM_00); + * @endcode + */ +#define FTM_PDD_SelectBDMMode(PeripheralBase, Mode) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_BDMMODE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTOFFrequency + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ratio between the number of counter overflows to the + * number of times the TOF bit is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the TOF frequency. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetTOFFrequency(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetTOFFrequency(PeripheralBase, Value) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_NUMTOF_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput3Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput3Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput3Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT3POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT3POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput2Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput2Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput2Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT2POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT2POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput1Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput1Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput1Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT1POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT1POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput0Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput0Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput0Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT0POL_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerSWOCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerSWOCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerSWOCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWSOC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWSOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerINVCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerINVCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerINVCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWINVC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWINVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerOUTMASK + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the OUTMASK register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerOUTMASK(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerOUTMASK(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_HWOM_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerWRBUF + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates MOD, CNTIN, and CV registers + * synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerWRBUF(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerWRBUF(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWWRBUF_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWWRBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerRSTCNT + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the FTM counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerRSTCNT(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerRSTCNT(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWRSTCNT_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWRSTCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerSWOCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerSWOCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerSWOCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWSOC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWSOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerINVCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerINVCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerINVCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWINVC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWINVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerOUTMASK + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the OUTMASK register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerOUTMASK(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerOUTMASK(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_SWOM_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerWRBUF + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates MOD, CNTIN, and CV registers + * synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerWRBUF(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerWRBUF(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWWRBUF_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWWRBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerRSTCNT + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the FTM counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerRSTCNT(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerRSTCNT(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWRSTCNT_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWRSTCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSynchronizationMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the PWM synchronization mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the synchronization mode. This parameter is of + * "Synchronization mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectSynchronizationMode(_BASE_PTR, + * FTM_PDD_SYNC_LEGACY); + * @endcode + */ +#define FTM_PDD_SelectSynchronizationMode(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SYNCMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSWOCTRLSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the SWOCTRL synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectSWOCTRLSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectSWOCTRLSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_SWOC_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_SWOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectINVCTRLSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the INVCTRL synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectINVCTRLSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectINVCTRLSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_INVC_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_INVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectCNTINSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects CNTIN register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the CNTIN synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectCNTINSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectCNTINSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_CNTINC_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_CNTINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHardwareTriggerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief The FTM clears the TRIGj bit when the hardware trigger j is detected, + * where j = 0, 1,2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the hardware trigger mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHardwareTriggerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHardwareTriggerMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FTM_SYNCONF_REG(PeripheralBase) |= \ + FTM_SYNCONF_HWTRIGMODE_MASK) : ( \ + FTM_SYNCONF_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_SYNCONF_HWTRIGMODE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels3Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 3 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 3 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels3Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels3Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels2Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 2 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 2 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels2Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels2Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels1Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 1 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 1 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels1Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels1Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels0Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 0 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 0 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels0Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels0Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV0EN_MASK)))) | ( \ + (uint32)(State))) \ + ) +#endif /* #if defined(FTM_PDD_H_) */ + +/* FTM_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h new file mode 100644 index 0000000..870ee69 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h @@ -0,0 +1,516 @@ +/* + PDD layer implementation for peripheral type GPIO + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(GPIO_PDD_H_) +#define GPIO_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error GPIO PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK10DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK11D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK11D5WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK12D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK20DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21D5WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21F12WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F12810) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F25612) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F51212) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK24F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40X256VMD100) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK52D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK52DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK53D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK53DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK60F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK60DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60N512VMD100) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK61F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F12WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F15WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK63F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK63F12WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK64F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK65F18) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK65F18WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK66F18) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK70F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F12WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F15WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MKE02Z2) /* GPIOA, GPIOB */ && \ + !defined(MCU_MKE02Z4) /* GPIOA, GPIOB */ && \ + !defined(MCU_SKEAZN642) /* GPIOA, GPIOB */ && \ + !defined(MCU_MKE04Z1284) /* GPIOA, GPIOB, GPIOC */ && \ + !defined(MCU_MKE04Z4) /* GPIOA */ && \ + !defined(MCU_SKEAZN84) /* GPIOA */ && \ + !defined(MCU_MKE06Z4) /* GPIOA, GPIOB, GPIOC */ && \ + !defined(MCU_MKL02Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL03Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL04Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL05Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL14Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL15Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL16Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL24Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL25Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL26Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL34Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL36Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL46Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV10Z7) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKV31F12810) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV31F25612) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV31F51212) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKW01Z4) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW21D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW21D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW22D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW22D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW24D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW24D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_PCK20L4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_SKEAZ1284) /* GPIOA, GPIOB, GPIOC */ + // Unsupported MCU is active + #error GPIO PDD library: Unsupported derivative is active. +#endif + +//#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Pin masks */ +#define GPIO_PDD_PIN_0 0x1U /**< Pin 0 mask */ +#define GPIO_PDD_PIN_1 0x2U /**< Pin 1 mask */ +#define GPIO_PDD_PIN_2 0x4U /**< Pin 2 mask */ +#define GPIO_PDD_PIN_3 0x8U /**< Pin 3 mask */ +#define GPIO_PDD_PIN_4 0x10U /**< Pin 4 mask */ +#define GPIO_PDD_PIN_5 0x20U /**< Pin 5 mask */ +#define GPIO_PDD_PIN_6 0x40U /**< Pin 6 mask */ +#define GPIO_PDD_PIN_7 0x80U /**< Pin 7 mask */ +#define GPIO_PDD_PIN_8 0x100U /**< Pin 8 mask */ +#define GPIO_PDD_PIN_9 0x200U /**< Pin 9 mask */ +#define GPIO_PDD_PIN_10 0x400U /**< Pin 10 mask */ +#define GPIO_PDD_PIN_11 0x800U /**< Pin 11 mask */ +#define GPIO_PDD_PIN_12 0x1000U /**< Pin 12 mask */ +#define GPIO_PDD_PIN_13 0x2000U /**< Pin 13 mask */ +#define GPIO_PDD_PIN_14 0x4000U /**< Pin 14 mask */ +#define GPIO_PDD_PIN_15 0x8000U /**< Pin 15 mask */ +#define GPIO_PDD_PIN_16 0x10000U /**< Pin 16 mask */ +#define GPIO_PDD_PIN_17 0x20000U /**< Pin 17 mask */ +#define GPIO_PDD_PIN_18 0x40000U /**< Pin 18 mask */ +#define GPIO_PDD_PIN_19 0x80000U /**< Pin 19 mask */ +#define GPIO_PDD_PIN_20 0x100000U /**< Pin 20 mask */ +#define GPIO_PDD_PIN_21 0x200000U /**< Pin 21 mask */ +#define GPIO_PDD_PIN_22 0x400000U /**< Pin 22 mask */ +#define GPIO_PDD_PIN_23 0x800000U /**< Pin 23 mask */ +#define GPIO_PDD_PIN_24 0x1000000U /**< Pin 24 mask */ +#define GPIO_PDD_PIN_25 0x2000000U /**< Pin 25 mask */ +#define GPIO_PDD_PIN_26 0x4000000U /**< Pin 26 mask */ +#define GPIO_PDD_PIN_27 0x8000000U /**< Pin 27 mask */ +#define GPIO_PDD_PIN_28 0x10000000U /**< Pin 28 mask */ +#define GPIO_PDD_PIN_29 0x20000000U /**< Pin 29 mask */ +#define GPIO_PDD_PIN_30 0x40000000U /**< Pin 30 mask */ +#define GPIO_PDD_PIN_31 0x80000000U /**< Pin 31 mask */ + + +/* ---------------------------------------------------------------------------- + -- GetPortDataInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets port data input independently of current direction setting nor + * pin usage. It returns zeros for pins which are not configured for a digital + * function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDIR, GPIOB_PDIR, + * GPIOC_PDIR, GPIOD_PDIR, GPIOE_PDIR, GPIOF_PDIR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDataInput(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDataInput(PeripheralBase) ( \ + (uint32)GPIO_PDIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDataOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets port data output. The value is driven out to the corresponding + * pin if direction of the pin is set to output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new data output value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDOR, GPIOB_PDOR, + * GPIOC_PDOR, GPIOD_PDOR, GPIOE_PDOR, GPIOF_PDOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDataOutput(_BASE_PTR, 1); + * @endcode + */ +#define GPIO_PDD_SetPortDataOutput(PeripheralBase, Value) ( \ + GPIO_PDOR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPortDataOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets port data output independently of current direction setting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDOR, GPIOB_PDOR, + * GPIOC_PDOR, GPIOD_PDOR, GPIOE_PDOR, GPIOF_PDOR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDataOutput(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDataOutput(PeripheralBase) ( \ + (uint32)GPIO_PDOR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be cleared. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PCOR, GPIOB_PCOR, + * GPIOC_PCOR, GPIOD_PCOR, GPIOE_PCOR, GPIOF_PCOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_ClearPortDataOutputMask(_BASE_PTR, GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_ClearPortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PCOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PSOR, GPIOB_PSOR, + * GPIOC_PSOR, GPIOD_PSOR, GPIOE_PSOR, GPIOF_PSOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDataOutputMask(_BASE_PTR, GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_SetPortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PSOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- TogglePortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Toggles required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be inverted. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PTOR, GPIOB_PTOR, + * GPIOC_PTOR, GPIOD_PTOR, GPIOE_PTOR, GPIOF_PTOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_TogglePortDataOutputMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_TogglePortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PTOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortInputDirectionMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets required pins as input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortInputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortInputDirectionMask(PeripheralBase, Mask) ( \ + (GPIO_PDDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask))), \ + (GPIO_PIDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets required pins as input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortInputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortInputDirectionMask(PeripheralBase, Mask) ( \ + GPIO_PDDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPortOutputDirectionMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pins as output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as output. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortOutputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_SetPortOutputDirectionMask(PeripheralBase, Mask) ( \ + GPIO_PDDR_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDirectionMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets direction on pins specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param InputMask Mask of port pins defining which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @param OutputMask Mask of port pins defining which should be set as output. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirectionMask(_BASE_PTR, GPIO_PDD_PIN_0, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortDirectionMask(PeripheralBase, InputMask, OutputMask) ( \ + (GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(GPIO_PDDR_REG(PeripheralBase) & (uint32)(~(uint32)(InputMask)))) | ( \ + (uint32)(OutputMask)))), \ + (GPIO_PIDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(InputMask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets direction on pins specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param InputMask Mask of port pins defining which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @param OutputMask Mask of port pins defining which should be set as output. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirectionMask(_BASE_PTR, GPIO_PDD_PIN_0, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortDirectionMask(PeripheralBase, InputMask, OutputMask) ( \ + GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(GPIO_PDDR_REG(PeripheralBase) & (uint32)(~(uint32)(InputMask)))) | ( \ + (uint32)(OutputMask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPortDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets direction of every pin in the port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new direction for port pins. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirection(_BASE_PTR, 1); + * @endcode + */ +#define GPIO_PDD_SetPortDirection(PeripheralBase, Value) ( \ + GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPortDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets direction of every pin in the port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDirection(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDirection(PeripheralBase) ( \ + (uint32)GPIO_PDDR_REG(PeripheralBase) \ + ) +#endif /* #if defined(GPIO_PDD_H_) */ + +/* GPIO_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h new file mode 100644 index 0000000..8e10db4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h @@ -0,0 +1,2150 @@ +/* + PDD layer implementation for peripheral type I2C + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(I2C_PDD_H_) +#define I2C_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error I2C PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10D5) /* I2C0 */ && \ + !defined(MCU_MK10D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK11D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK11D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK12D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20D5) /* I2C0 */ && \ + !defined(MCU_MK20D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK21F12WS) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK22D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F12810) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK22F25612) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F51212) /* I2C0, I2C1 */ && \ + !defined(MCU_MK24F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK30D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK30D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK30DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40X256VMD100) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK52D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK52DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK53D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK53DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60N512VMD100) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F12WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F15WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK63F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK63F12WS) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK64F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK65F18) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK65F18WS) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK66F18) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK70F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F12WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F15WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKE02Z2) /* I2C0 */ && \ + !defined(MCU_MKE02Z4) /* I2C0 */ && \ + !defined(MCU_SKEAZN642) /* I2C0 */ && \ + !defined(MCU_MKE04Z1284) /* I2C0, I2C1 */ && \ + !defined(MCU_MKE04Z4) /* I2C0 */ && \ + !defined(MCU_SKEAZN84) /* I2C0 */ && \ + !defined(MCU_MKE06Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL02Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL03Z4) /* I2C0 */ && \ + !defined(MCU_MKL04Z4) /* I2C0 */ && \ + !defined(MCU_MKL05Z4) /* I2C0 */ && \ + !defined(MCU_MKL14Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL15Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL16Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL24Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL25Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL26Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL34Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL36Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL46Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV10Z7) /* I2C0 */ && \ + !defined(MCU_MKV31F12810) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV31F25612) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV31F51212) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW01Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW21D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW21D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW22D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW22D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW24D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW24D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_PCK20L4) /* I2C0 */ && \ + !defined(MCU_SKEAZ1284) /* I2C0, I2C1 */ + // Unsupported MCU is active + #error I2C PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define I2C_PDD_RX_ACKNOWLEDGE I2C_S_RXAK_MASK /**< Receive acknowledge. */ +#define I2C_PDD_INTERRUPT_FLAG I2C_S_IICIF_MASK /**< Interrupt flag. */ +#define I2C_PDD_SLAVE_TRANSMIT I2C_S_SRW_MASK /**< Slave read/write request. */ +#define I2C_PDD_RANGE_ADDRESS_MATCH I2C_S_RAM_MASK /**< Range address match. */ +#define I2C_PDD_ARBIT_LOST I2C_S_ARBL_MASK /**< Arbitration lost. */ +#define I2C_PDD_BUS_IS_BUSY I2C_S_BUSY_MASK /**< Bus busy - set when a START signal is detected. */ +#define I2C_PDD_ADDRESSED_AS_SLAVE I2C_S_IAAS_MASK /**< Addressed as a slave. */ +#define I2C_PDD_TX_COMPLETE I2C_S_TCF_MASK /**< Transfer complete flag. */ + +/* SCL timeout flags constants (for GetSCLTimeoutInterruptFlags, + ClearSCLTimeoutInterruptFlags macros). */ +#define I2C_PDD_SCL_LOW_TIMEOUT I2C_SMB_SLTF_MASK /**< SCL low timeout flag. */ +#define I2C_PDD_SCL_HI_AND_SDA_HI_TIMEOUT I2C_SMB_SHTF1_MASK /**< SCL high timeout flag - sets when SCL and SDA are held high more than clock × LoValue / 512. */ +#define I2C_PDD_SCL_HI_AND_SDA_LOW_TIMEOUT I2C_SMB_SHTF2_MASK /**< SCL high timeout flag - sets when SCL is held high and SDA is held low more than clock × LoValue/512. */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/* Status flags constants. */ + #define I2C_PDD_BUS_STOP_FLAG I2C_FLT_STOPF_MASK /**< Stop detected on I2C bus */ + +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Status flags constants. */ + #define I2C_PDD_BUS_STOP_FLAG I2C_FLT_STOPF_MASK /**< Stop detected on I2C bus */ + #define I2C_PDD_BUS_START_FLAG I2C_FLT_STARTF_MASK /**< Start detected on I2C bus */ + +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Frequency multiplier constants (for SetFrequencyMultiplier macro). */ +#define I2C_PDD_FREQUENCY_MUL_1 0U /**< Multiplier factor = 1 */ +#define I2C_PDD_FREQUENCY_MUL_2 0x1U /**< Multiplier factor = 2 */ +#define I2C_PDD_FREQUENCY_MUL_4 0x2U /**< Multiplier factor = 4 */ + +/* Master mode constants (for MasterMode, GetMasterMode macros). */ +#define I2C_PDD_MASTER_MODE 0x20U /**< Master mode. */ +#define I2C_PDD_SLAVE_MODE 0U /**< Slave mode. */ + +/* Transmit mode constants (for SetTransmitMode, GetTransmitMode macros). */ +#define I2C_PDD_TX_DIRECTION 0x10U /**< SDA pin set as output. */ +#define I2C_PDD_RX_DIRECTION 0U /**< SDA pin set as input. */ + +/* BUS status constants (for GetBusStatus macro). */ +#define I2C_PDD_BUS_IDLE 0U /**< Bus is idle. */ +#define I2C_PDD_BUS_BUSY 0x20U /**< Bus is busy. */ + +/* Fast SMBus Acknowledge constants (for GetFastSmBusAcknowledge macro). */ +#define I2C_PDD_ACK_FOLLOWING_RX_DATA 0U /**< ACK or NACK is sent on the following receiving data byte. */ +#define I2C_PDD_ACK_AFTER_RX_DATA 0x80U /**< ACK or NACK is sent after receiving a data byte. */ + +/* Clock source constants (for SetSCLTimeoutBusClockSource macro). */ +#define I2C_PDD_BUS_CLOCK 0x10U /**< Bus clock frequency */ +#define I2C_PDD_BUS_CLOCK_DIV64 0U /**< Bus clock / 64 frequency */ + + +/* ---------------------------------------------------------------------------- + -- SetSlaveAddress7bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to the address register and set address length to 7 bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AddrValue Slave address value[0..127]. This parameter is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C0_C2, + * I2C1_A1, I2C1_C2, I2C2_A1, I2C2_C2, I2C3_A1, I2C3_C2 (depending on the + * peripheral). + * @par Example: + * @code + * I2C_PDD_SetSlaveAddress7bits(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSlaveAddress7bits(PeripheralBase, AddrValue) ( \ + (I2C_A1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A1_AD_MASK))) | ( \ + (uint8)((uint8)(AddrValue) << I2C_A1_AD_SHIFT)))), \ + (I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_ADEXT_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSlaveAddress10bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to the address register and set address length to 10 bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AddrValue Slave address value[0..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C0_C2, + * I2C1_A1, I2C1_C2, I2C2_A1, I2C2_C2, I2C3_A1, I2C3_C2 (depending on the + * peripheral). + * @par Example: + * @code + * I2C_PDD_SetSlaveAddress10bits(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSlaveAddress10bits(PeripheralBase, AddrValue) ( \ + (I2C_A1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A1_AD_MASK))) | ( \ + (uint8)((uint8)((uint16)(AddrValue) & 0x7FU) << I2C_A1_AD_SHIFT)))), \ + (I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_AD_MASK))) | (( \ + (uint8)((uint16)(AddrValue) >> 7U)) | ( \ + I2C_C2_ADEXT_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads address 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_A1, I2C1_A1, + * I2C2_A1, I2C3_A1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadAddress1Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadAddress1Reg(PeripheralBase) ( \ + I2C_A1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into address 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C1_A1, + * I2C2_A1, I2C3_A1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteAddress1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteAddress1Reg(PeripheralBase, Value) ( \ + I2C_A1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrequencyDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler to configure the I2C clock for the bit-rate + * selection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FreqDividerValue Frequency divider value[0..63]. This parameter is a + * 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetFrequencyDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetFrequencyDivider(PeripheralBase, FreqDividerValue) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_F_REG(PeripheralBase) & (uint8)(~(uint8)I2C_F_ICR_MASK))) | ( \ + (uint8)(FreqDividerValue))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrequencyMultiplier + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the factor, what is used along with frequency divider to generate + * the I2C baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FreqMultiplierValue Frequency multiplier value[0..2]. This parameter + * is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetFrequencyMultiplier(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetFrequencyMultiplier(PeripheralBase, FreqMultiplierValue) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_F_REG(PeripheralBase) & (uint8)(~(uint8)I2C_F_MULT_MASK))) | ( \ + (uint8)((uint8)(FreqMultiplierValue) << I2C_F_MULT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFrequencyDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads frequency divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadFrequencyDividerReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadFrequencyDividerReg(PeripheralBase) ( \ + I2C_F_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFrequencyDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into frequency + * divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the frequency divider register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteFrequencyDividerReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteFrequencyDividerReg(PeripheralBase, Value) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables I2C device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableDevice(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_IICEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C1_IICEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the I2C interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableInterrupt(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_IICIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the I2C interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableInterrupt(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C1_IICIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMasterMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts the I2C to the master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MasterMode I2C mode value. The user should use one from the enumerated + * values. This parameter is of "Master mode constants (for MasterMode, + * GetMasterMode macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetMasterMode(_BASE_PTR, I2C_PDD_MASTER_MODE); + * @endcode + */ +#define I2C_PDD_SetMasterMode(PeripheralBase, MasterMode) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_MST_MASK))) | ( \ + (uint8)(MasterMode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMasterMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current operating mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Master mode constants (for MasterMode, + * GetMasterMode macros)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetMasterMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetMasterMode(PeripheralBase) ( \ + (uint8)(I2C_C1_REG(PeripheralBase) & I2C_C1_MST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data pin to the output or input direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param TransmitMode Direction I2C pins. The user should use one from the + * enumerated values. This parameter is of "Transmit mode constants (for + * SetTransmitMode, GetTransmitMode macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetTransmitMode(_BASE_PTR, I2C_PDD_TX_DIRECTION); + * @endcode + */ +#define I2C_PDD_SetTransmitMode(PeripheralBase, TransmitMode) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_TX_MASK))) | ( \ + (uint8)(TransmitMode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransmitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current direction mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Transmit mode constants (for SetTransmitMode, + * GetTransmitMode macros)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetTransmitMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetTransmitMode(PeripheralBase) ( \ + (uint8)(I2C_C1_REG(PeripheralBase) & I2C_C1_TX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables an acknowledge signal to be sent to the bus at the + * ninth clock bit after receiving one byte of data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of acknowledge signal. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableTransmitAcknowledge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableTransmitAcknowledge(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_TXAK_MASK) : ( \ + I2C_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C1_TXAK_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- RepeatStart + ---------------------------------------------------------------------------- */ + +/** + * @brief Generates a repeated START condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_RepeatStart(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_RepeatStart(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_RSTA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the wakeup function in stop3 mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of wakeup function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableWakeUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableWakeUp(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_WUEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C1_WUEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of DMA function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_DMAEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadControl1Reg(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadStatusReg(PeripheralBase) ( \ + I2C_S_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns status of the BUS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "BUS status constants (for GetBusStatus macro)." + * type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetBusStatus(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetBusStatus(PeripheralBase) ( \ + (uint8)(I2C_S_REG(PeripheralBase) & I2C_S_BUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value that represents a mask of active (pending) interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + I2C_S_REG(PeripheralBase)) & ( \ + (uint8)(( \ + I2C_S_TCF_MASK) | (( \ + I2C_S_IICIF_MASK) | (( \ + I2C_S_RAM_MASK) | (( \ + I2C_S_ARBL_MASK) | ( \ + I2C_S_IAAS_MASK))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants (for ReadStatusReg, GetInterruptFlags, + * ClearInterruptFlags macros).". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearInterruptFlags(_BASE_PTR, + * I2C_PDD_RX_ACKNOWLEDGE); + * @endcode + */ +#define I2C_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + I2C_S_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_S_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_S_IICIF_MASK | I2C_S_ARBL_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + I2C_S_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_D, I2C1_D, I2C2_D, + * I2C3_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadDataReg(PeripheralBase) ( \ + I2C_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_D, I2C1_D, I2C2_D, + * I2C3_D (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteDataReg(PeripheralBase, Data) ( \ + I2C_D_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGeneralCallAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables general call address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of general call address function. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableGeneralCallAddress(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableGeneralCallAddress(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_GCAEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_GCAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAddressExtension + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables extension address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of extension address. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableAddressExtension(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableAddressExtension(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_ADEXT_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_ADEXT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPadsNormalDriveMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets control the drive capability of the I2C pads to normal drive mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetPadsNormalDriveMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_SetPadsNormalDriveMode(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_HDRS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPadsHighDriveMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets control the drive capability of the I2C pads to high drive mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetPadsHighDriveMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_SetPadsHighDriveMode(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) |= \ + I2C_C2_HDRS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSlaveBaudControlByMaster + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables slave baud rate control by master device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of slave baud rate control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSlaveBaudControlByMaster(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSlaveBaudControlByMaster(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2C_C2_REG(PeripheralBase) |= \ + I2C_C2_SBRC_MASK) : ( \ + I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_SBRC_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRangeAddressMatch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables range address matching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of range address matching function. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableRangeAddressMatch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableRangeAddressMatch(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_RMEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_RMEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadControl2Reg(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputGlitchFilter + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..31]. This parameter is + * a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_FLT_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#elif ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_FLT_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..31]. This parameter is + * a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) & (uint8)(~(uint8)I2C_FLT_FLT_MASK))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadInputGlitchFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads input glitch filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadInputGlitchFilterReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadInputGlitchFilterReg(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInputGlitchFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into input glitch + * filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the input glitch filter register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteInputGlitchFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteInputGlitchFilterReg(PeripheralBase, Value) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRangeAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the range slave address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param RangeAddressValue Range Address value[0..127]. This parameter is a + * 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetRangeAddress(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetRangeAddress(PeripheralBase, RangeAddressValue) ( \ + I2C_RA_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_RA_REG(PeripheralBase) & (uint8)(~(uint8)I2C_RA_RAD_MASK))) | ( \ + (uint8)((uint8)(RangeAddressValue) << I2C_RA_RAD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRangeAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads value of range address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadRangeAddressReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadRangeAddressReg(PeripheralBase) ( \ + I2C_RA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRangeAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into range address + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the range address register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteRangeAddressReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteRangeAddressReg(PeripheralBase, Value) ( \ + I2C_RA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFastSmBusNackAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables fast SMBus NACK/ACK. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus alert response will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableFastSmBusNackAck(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableFastSmBusNackAck(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_FACK_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_FACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFastSmBusAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Fast NACK/ACK enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Fast SMBus Acknowledge constants (for + * GetFastSmBusAcknowledge macro)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetFastSmBusAcknowledge(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetFastSmBusAcknowledge(PeripheralBase) ( \ + (uint8)(I2C_SMB_REG(PeripheralBase) & I2C_SMB_FACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSmBusAlertResponseAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SMBus alert response address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus alert response will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSmBusAlertResponseAddress(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSmBusAlertResponseAddress(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_ALERTEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_ALERTEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondI2CAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SMBus device default address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus device default address will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSecondI2CAddress(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSecondI2CAddress(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_SIICAEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_SIICAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSCLTimeoutBusClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source of the timeout counter to Bus clock or Bus clock/64 + * frequency. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClockSource SCL timeout BUS clock source value. The user should use + * one from the enumerated values. This parameter is of "Clock source + * constants (for SetSCLTimeoutBusClockSource macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSCLTimeoutBusClockSource(_BASE_PTR, + * I2C_PDD_BUS_CLOCK); + * @endcode + */ +#define I2C_PDD_SetSCLTimeoutBusClockSource(PeripheralBase, ClockSource) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_TCKSEL_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)(ClockSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSCLTimeoutInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value that represents a mask of active (pending) interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "SCL timeout flags constants (for + * GetSCLTimeoutInterruptFlags, ClearSCLTimeoutInterruptFlags macros)." for + * processing return value. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_GetSCLTimeoutInterruptFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetSCLTimeoutInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & ( \ + (uint8)(I2C_SMB_SLTF_MASK | (I2C_SMB_SHTF1_MASK | I2C_SMB_SHTF2_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSCLTimeoutInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group "SCL + * timeout flags constants (for GetSCLTimeoutInterruptFlags, + * ClearSCLTimeoutInterruptFlags macros).". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearSCLTimeoutInterruptFlags(_BASE_PTR, + * I2C_PDD_SCL_LOW_TIMEOUT); + * @endcode + */ +#define I2C_PDD_ClearSCLTimeoutInterruptFlags(PeripheralBase, Mask) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSCLTimeoutInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables SCL high and SDA low timeout interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSCLTimeoutInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableSCLTimeoutInterrupt(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_SMB_REG(PeripheralBase) | I2C_SMB_SHTF2IE_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSCLTimeoutInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables SCL high and SDA low timeout interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableSCLTimeoutInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableSCLTimeoutInterrupt(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_SMB_SHTF2IE_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSMBusControlAndStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SMBus control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadSMBusControlAndStatusReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSMBusControlAndStatusReg(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSMBusControlAndStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SMBus control + * and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SMBus control and status register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSMBusControlAndStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSMBusControlAndStatusReg(PeripheralBase, Value) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSMBusSlaveAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets SMBus address to the address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SMBusSlaveAddrValue SMBus slave address value[0..127]. This parameter + * is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSMBusSlaveAddress(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSMBusSlaveAddress(PeripheralBase, SMBusSlaveAddrValue) ( \ + I2C_A2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A2_SAD_MASK))) | ( \ + (uint8)((uint8)(SMBusSlaveAddrValue) << I2C_A2_SAD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads address 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadAddress2Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadAddress2Reg(PeripheralBase) ( \ + I2C_A2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into address 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the address 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteAddress2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteAddress2Reg(PeripheralBase, Value) ( \ + I2C_A2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSCLLowTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets SCL low timeout value that determines the timeout period of SCL + * low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SCLLowTimeoutValue SCL low timeout value[0..65535]. This parameter is + * a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C0_SLTH, + * I2C1_SLTL, I2C1_SLTH, I2C2_SLTL, I2C2_SLTH, I2C3_SLTL, I2C3_SLTH + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSCLLowTimeout(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSCLLowTimeout(PeripheralBase, SCLLowTimeoutValue) ( \ + (I2C_SLTL_REG(PeripheralBase) = \ + (uint8)(SCLLowTimeoutValue)), \ + (I2C_SLTH_REG(PeripheralBase) = \ + (uint8)((uint16)(SCLLowTimeoutValue) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSclLowTimeoutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SCL low timeout high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SLTH, I2C1_SLTH, + * I2C2_SLTH, I2C3_SLTH (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadSclLowTimeoutHighReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSclLowTimeoutHighReg(PeripheralBase) ( \ + I2C_SLTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSclLowTimeoutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SCL low timeout + * high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SCL low timeout high register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTH, I2C1_SLTH, + * I2C2_SLTH, I2C3_SLTH (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSclLowTimeoutHighReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSclLowTimeoutHighReg(PeripheralBase, Value) ( \ + I2C_SLTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSclLowTimeoutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SCL low timeout high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C1_SLTL, + * I2C2_SLTL, I2C3_SLTL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadSclLowTimeoutLowReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSclLowTimeoutLowReg(PeripheralBase) ( \ + I2C_SLTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSclLowTimeoutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SCL low timeout + * low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SCL low timeout low register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C1_SLTL, + * I2C2_SLTL, I2C3_SLTL (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSclLowTimeoutLowReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSclLowTimeoutLowReg(PeripheralBase, Value) ( \ + I2C_SLTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStopHoldOffMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables stop mode holdoff. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of stop mode holdoff. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableStopHoldOffMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define I2C_PDD_EnableStopHoldOffMode(PeripheralBase, State) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_SHEN_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))))) | ( \ + (uint8)((uint8)(State) << I2C_FLT_SHEN_SHIFT))) \ + ) +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables/disables stop mode holdoff. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of stop mode holdoff. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableStopHoldOffMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define I2C_PDD_EnableStopHoldOffMode(PeripheralBase, State) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_SHEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_FLT_SHEN_SHIFT))) \ + ) +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadBusStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the bus status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants." for processing + * return value. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadBusStatusFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadBusStatusFlags(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBusStatusInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Clears bus status interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearBusStatusInterruptFlags(_BASE_PTR, + * I2C_PDD_BUS_STOP_FLAG); + * @endcode + */ + #define I2C_PDD_ClearBusStatusInterruptFlags(PeripheralBase, Mask) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) & (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Clears bus status interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearBusStatusInterruptFlags(_BASE_PTR, + * I2C_PDD_BUS_STOP_FLAG); + * @endcode + */ + #define I2C_PDD_ClearBusStatusInterruptFlags(PeripheralBase, Mask) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableBusStopOrStartInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the bus stop or start interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableBusStopOrStartInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableBusStopOrStartInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) | I2C_FLT_SSIE_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusStopOrStartInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the bus stop or start interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableBusStopOrStartInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableBusStopOrStartInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_FLT_SSIE_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusStopInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the bus stop interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableBusStopInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableBusStopInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) | I2C_FLT_STOPIE_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusStopInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the bus stop interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableBusStopInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableBusStopInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_FLT_STOPIE_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) \ + ) +#endif /* #if defined(I2C_PDD_H_) */ + +/* I2C_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h new file mode 100644 index 0000000..49ae674 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h @@ -0,0 +1,788 @@ +/* + PDD layer implementation for peripheral type LPTMR + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(LPTMR_PDD_H_) +#define LPTMR_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error LPTMR PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* LPTMR0 */ && \ + !defined(MCU_MK10D5) /* LPTMR0 */ && \ + !defined(MCU_MK10D7) /* LPTMR0 */ && \ + !defined(MCU_MK10F12) /* LPTMR0 */ && \ + !defined(MCU_MK10DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK11D5) /* LPTMR0 */ && \ + !defined(MCU_MK11D5WS) /* LPTMR0 */ && \ + !defined(MCU_MK12D5) /* LPTMR0 */ && \ + !defined(MCU_MK20D10) /* LPTMR0 */ && \ + !defined(MCU_MK20D5) /* LPTMR0 */ && \ + !defined(MCU_MK20D7) /* LPTMR0 */ && \ + !defined(MCU_MK20F12) /* LPTMR0 */ && \ + !defined(MCU_MK20DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK21D5) /* LPTMR0 */ && \ + !defined(MCU_MK21D5WS) /* LPTMR0 */ && \ + !defined(MCU_MK21F12) /* LPTMR0 */ && \ + !defined(MCU_MK21F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK22D5) /* LPTMR0 */ && \ + !defined(MCU_MK22F12810) /* LPTMR0 */ && \ + !defined(MCU_MK22F12) /* LPTMR0 */ && \ + !defined(MCU_MK22F25612) /* LPTMR0 */ && \ + !defined(MCU_MK22F51212) /* LPTMR0 */ && \ + !defined(MCU_MK24F12) /* LPTMR0 */ && \ + !defined(MCU_MK30D10) /* LPTMR0 */ && \ + !defined(MCU_MK30D7) /* LPTMR0 */ && \ + !defined(MCU_MK30DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK40D10) /* LPTMR0 */ && \ + !defined(MCU_MK40D7) /* LPTMR0 */ && \ + !defined(MCU_MK40DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK40X256VMD100) /* LPTMR0 */ && \ + !defined(MCU_MK50D10) /* LPTMR0 */ && \ + !defined(MCU_MK50D7) /* LPTMR0 */ && \ + !defined(MCU_MK50DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK51D10) /* LPTMR0 */ && \ + !defined(MCU_MK51D7) /* LPTMR0 */ && \ + !defined(MCU_MK51DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK52D10) /* LPTMR0 */ && \ + !defined(MCU_MK52DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK53D10) /* LPTMR0 */ && \ + !defined(MCU_MK53DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK60D10) /* LPTMR0 */ && \ + !defined(MCU_MK60F12) /* LPTMR0 */ && \ + !defined(MCU_MK60F15) /* LPTMR0 */ && \ + !defined(MCU_MK60DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK60N512VMD100) /* LPTMR0 */ && \ + !defined(MCU_MK61F12) /* LPTMR0 */ && \ + !defined(MCU_MK61F15) /* LPTMR0 */ && \ + !defined(MCU_MK61F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK61F15WS) /* LPTMR0 */ && \ + !defined(MCU_MK63F12) /* LPTMR0 */ && \ + !defined(MCU_MK63F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK64F12) /* LPTMR0 */ && \ + !defined(MCU_MK65F18) /* LPTMR0 */ && \ + !defined(MCU_MK65F18WS) /* LPTMR0 */ && \ + !defined(MCU_MK66F18) /* LPTMR0 */ && \ + !defined(MCU_MK70F12) /* LPTMR0 */ && \ + !defined(MCU_MK70F15) /* LPTMR0 */ && \ + !defined(MCU_MK70F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK70F15WS) /* LPTMR0 */ && \ + !defined(MCU_MKL02Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL03Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL04Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL05Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL14Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL15Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL16Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL24Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL25Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL26Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL34Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL36Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL46Z4) /* LPTMR0 */ && \ + !defined(MCU_MKV10Z7) /* LPTMR0 */ && \ + !defined(MCU_MKV31F12810) /* LPTMR0 */ && \ + !defined(MCU_MKV31F25612) /* LPTMR0 */ && \ + !defined(MCU_MKV31F51212) /* LPTMR0 */ && \ + !defined(MCU_MKW01Z4) /* LPTMR0 */ && \ + !defined(MCU_MKW21D5) /* LPTMR0 */ && \ + !defined(MCU_MKW21D5WS) /* LPTMR0 */ && \ + !defined(MCU_MKW22D5) /* LPTMR0 */ && \ + !defined(MCU_MKW22D5WS) /* LPTMR0 */ && \ + !defined(MCU_MKW24D5) /* LPTMR0 */ && \ + !defined(MCU_MKW24D5WS) /* LPTMR0 */ && \ + !defined(MCU_PCK20L4) /* LPTMR0 */ + // Unsupported MCU is active + #error LPTMR PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Enable freerun constants */ +#define LPTMR_PDD_RESTART_ENABLED 0U /**< Enabled */ +#define LPTMR_PDD_RESTART_DISABLED LPTMR_CSR_TFC_MASK /**< Disabled */ + +/* Timer mode constants */ +#define LPTMR_PDD_SOURCE_INTERNAL 0U /**< Internal */ +#define LPTMR_PDD_SOURCE_EXTERNAL LPTMR_CSR_TMS_MASK /**< External */ + +/* Prescaler/Filter constants */ +#define LPTMR_PDD_PRESCALER_2 0U /**< 2 */ +#define LPTMR_PDD_PRESCALER_4 0x1U /**< 4 */ +#define LPTMR_PDD_PRESCALER_8 0x2U /**< 8 */ +#define LPTMR_PDD_PRESCALER_16 0x3U /**< 16 */ +#define LPTMR_PDD_PRESCALER_32 0x4U /**< 32 */ +#define LPTMR_PDD_PRESCALER_64 0x5U /**< 64 */ +#define LPTMR_PDD_PRESCALER_128 0x6U /**< 128 */ +#define LPTMR_PDD_PRESCALER_256 0x7U /**< 256 */ +#define LPTMR_PDD_PRESCALER_512 0x8U /**< 512 */ +#define LPTMR_PDD_PRESCALER_1024 0x9U /**< 1024 */ +#define LPTMR_PDD_PRESCALER_2048 0xAU /**< 2048 */ +#define LPTMR_PDD_PRESCALER_4096 0xBU /**< 4096 */ +#define LPTMR_PDD_PRESCALER_8192 0xCU /**< 8192 */ +#define LPTMR_PDD_PRESCALER_16384 0xDU /**< 16384 */ +#define LPTMR_PDD_PRESCALER_32768 0xEU /**< 32768 */ +#define LPTMR_PDD_PRESCALER_65536 0xFU /**< 65536 */ +#define LPTMR_PDD_FILTER_2 0x1U /**< 2 */ +#define LPTMR_PDD_FILTER_4 0x2U /**< 4 */ +#define LPTMR_PDD_FILTER_8 0x3U /**< 8 */ +#define LPTMR_PDD_FILTER_16 0x4U /**< 16 */ +#define LPTMR_PDD_FILTER_32 0x5U /**< 32 */ +#define LPTMR_PDD_FILTER_64 0x6U /**< 64 */ +#define LPTMR_PDD_FILTER_128 0x7U /**< 128 */ +#define LPTMR_PDD_FILTER_256 0x8U /**< 256 */ +#define LPTMR_PDD_FILTER_512 0x9U /**< 512 */ +#define LPTMR_PDD_FILTER_1024 0xAU /**< 1024 */ +#define LPTMR_PDD_FILTER_2048 0xBU /**< 2048 */ +#define LPTMR_PDD_FILTER_4096 0xCU /**< 4096 */ +#define LPTMR_PDD_FILTER_8192 0xDU /**< 8192 */ +#define LPTMR_PDD_FILTER_16384 0xEU /**< 16384 */ +#define LPTMR_PDD_FILTER_32768 0xFU /**< 32768 */ + +/* Divider constants */ +#define LPTMR_PDD_DIVIDER_1 0x1U /**< 1 */ +#define LPTMR_PDD_DIVIDER_2 0U /**< 2 */ +#define LPTMR_PDD_DIVIDER_4 0x2U /**< 4 */ +#define LPTMR_PDD_DIVIDER_8 0x4U /**< 8 */ +#define LPTMR_PDD_DIVIDER_16 0x6U /**< 16 */ +#define LPTMR_PDD_DIVIDER_32 0x8U /**< 32 */ +#define LPTMR_PDD_DIVIDER_64 0xAU /**< 64 */ +#define LPTMR_PDD_DIVIDER_128 0xCU /**< 128 */ +#define LPTMR_PDD_DIVIDER_256 0xEU /**< 256 */ +#define LPTMR_PDD_DIVIDER_512 0x10U /**< 512 */ +#define LPTMR_PDD_DIVIDER_1024 0x12U /**< 1024 */ +#define LPTMR_PDD_DIVIDER_2048 0x14U /**< 2048 */ +#define LPTMR_PDD_DIVIDER_4096 0x16U /**< 4096 */ +#define LPTMR_PDD_DIVIDER_8192 0x18U /**< 8192 */ +#define LPTMR_PDD_DIVIDER_16384 0x1AU /**< 16384 */ +#define LPTMR_PDD_DIVIDER_32768 0x1CU /**< 32768 */ +#define LPTMR_PDD_DIVIDER_65536 0x1EU /**< 65536 */ + +/* Timer Pin Select constants. */ +#define LPTMR_PDD_HSCMP 0U /**< Alt 0 */ +#define LPTMR_PDD_PIN_1 0x10U /**< Alt 1 */ +#define LPTMR_PDD_PIN_2 0x20U /**< Alt 2 */ +#define LPTMR_PDD_PIN_3 0x30U /**< Alt 3 */ + +/* Timer Pin Polarity constants. */ +#define LPTMR_PDD_POLARITY_RISING 0U /**< Rising */ +#define LPTMR_PDD_POLARITY_FALLING 0x8U /**< Falling */ + +/* Prescaler bypass constants. */ +#define LPTMR_PDD_BYPASS_DISABLED 0U /**< Disabled */ +#define LPTMR_PDD_BYPASS_ENABLED 0x4U /**< Enabled */ + +/* Clock source constants. */ +#define LPTMR_PDD_SOURCE_INTREF 0U /**< Internal reference clock */ +#define LPTMR_PDD_SOURCE_LPO1KHZ 0x1U /**< Low power oscillator clock */ +#define LPTMR_PDD_SOURCE_EXT32KHZ 0x2U /**< External 32 kHz clock */ +#define LPTMR_PDD_SOURCE_EXTREF 0x3U /**< External reference clock */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TCF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the LPT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_EnableInterrupt(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) | LPTMR_CSR_TIE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the LPT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_DisableInterrupt(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)LPTMR_CSR_TIE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears LPT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ClearInterruptFlag(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) |= \ + LPTMR_CSR_TCF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets Timer Pin Select bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param TPS_val New value of the TPS. This parameter is of "Timer Pin Select + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SelectPin(_BASE_PTR, LPTMR_PDD_HSCMP); + * @endcode + */ +#define LPTMR_PDD_SelectPin(PeripheralBase, TPS_val) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TPS_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(TPS_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the polarity of the input source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Edge New value of the polarity. This parameter is of "Timer Pin + * Polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SetPinPolarity(_BASE_PTR, + * LPTMR_PDD_POLARITY_RISING); + * @endcode + */ +#define LPTMR_PDD_SetPinPolarity(PeripheralBase, Edge) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TPP_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Edge))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFreerun + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the freerun mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Restart New value of the restart. Use constants from group "Enable + * freerun constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableFreerun(_BASE_PTR, + * LPTMR_PDD_RESTART_ENABLED); + * @endcode + */ +#define LPTMR_PDD_EnableFreerun(PeripheralBase, Restart) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TFC_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Restart))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects timer mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Timer mode + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SetTimerMode(_BASE_PTR, + * LPTMR_PDD_SOURCE_INTERNAL); + * @endcode + */ +#define LPTMR_PDD_SetTimerMode(PeripheralBase, Source) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TMS_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the LPT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of LPT device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define LPTMR_PDD_EnableDevice(PeripheralBase, State) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TEN_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of LPT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = + * LPTMR_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler/Filter constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SetPrescaler(_BASE_PTR, LPTMR_PDD_PRESCALER_2); + * @endcode + */ +#define LPTMR_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PRESCALE_MASK))) | ( \ + (uint32)((uint32)(Prescaler) << LPTMR_PSR_PRESCALE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePrescalerBypass + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescaler bypass. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Bypass New value of the bypass. This parameter is of "Prescaler bypass + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_EnablePrescalerBypass(_BASE_PTR, + * LPTMR_PDD_BYPASS_DISABLED); + * @endcode + */ +#define LPTMR_PDD_EnablePrescalerBypass(PeripheralBase, Bypass) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PBYP_MASK))) | ( \ + (uint32)(Bypass))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets both prescale value and bypass value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the divider. Use constants from group "Divider + * constants". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SetDivider(_BASE_PTR, LPTMR_PDD_DIVIDER_1); + * @endcode + */ +#define LPTMR_PDD_SetDivider(PeripheralBase, Divider) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_PSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_PSR_PRESCALE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_PSR_PBYP_MASK))))) | (( \ + (uint32)((uint32)((uint32)(Divider) >> 1U) << LPTMR_PSR_PRESCALE_SHIFT)) | ( \ + (uint32)((uint32)((uint32)(Divider) & 0x1U) << LPTMR_PSR_PBYP_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SelectPrescalerSource(_BASE_PTR, + * LPTMR_PDD_SOURCE_INTREF); + * @endcode + */ +#define LPTMR_PDD_SelectPrescalerSource(PeripheralBase, Source) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PCS_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CMR. + * @par Example: + * @code + * LPTMR_PDD_WriteCompareReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WriteCompareReg(PeripheralBase, Value) ( \ + LPTMR_CMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CMR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCompareReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadCompareReg(PeripheralBase) ( \ + LPTMR_CMR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100))) +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CNR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ + #define LPTMR_PDD_ReadCounterReg(PeripheralBase) ( \ + LPTMR_CNR_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CNR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ + #define LPTMR_PDD_ReadCounterReg(PeripheralBase) ( \ + (LPTMR_CNR_REG(PeripheralBase) = \ + 0U), \ + LPTMR_CNR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control status register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_WriteControlStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WriteControlStatusReg(PeripheralBase, Value) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadControlStatusReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadControlStatusReg(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePrescaleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the prescale register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the prescale register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_WritePrescaleReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WritePrescaleReg(PeripheralBase, Value) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrescaleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the prescale register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadPrescaleReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadPrescaleReg(PeripheralBase) ( \ + LPTMR_PSR_REG(PeripheralBase) \ + ) +#endif /* #if defined(LPTMR_PDD_H_) */ + +/* LPTMR_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h new file mode 100644 index 0000000..ebc7cf7 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h @@ -0,0 +1,787 @@ +/* + PDD layer implementation for peripheral type MCM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(MCM_PDD_H_) +#define MCM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error MCM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* MCM */ && \ + !defined(MCU_MK10D7) /* MCM */ && \ + !defined(MCU_MK10F12) /* MCM */ && \ + !defined(MCU_MK10DZ10) /* MCM */ && \ + !defined(MCU_MK11D5) /* MCM */ && \ + !defined(MCU_MK11D5WS) /* MCM */ && \ + !defined(MCU_MK12D5) /* MCM */ && \ + !defined(MCU_MK20D10) /* MCM */ && \ + !defined(MCU_MK20D7) /* MCM */ && \ + !defined(MCU_MK20F12) /* MCM */ && \ + !defined(MCU_MK20DZ10) /* MCM */ && \ + !defined(MCU_MK21D5) /* MCM */ && \ + !defined(MCU_MK21D5WS) /* MCM */ && \ + !defined(MCU_MK21F12) /* MCM */ && \ + !defined(MCU_MK21F12WS) /* MCM */ && \ + !defined(MCU_MK22D5) /* MCM */ && \ + !defined(MCU_MK22F12810) /* MCM */ && \ + !defined(MCU_MK22F12) /* MCM */ && \ + !defined(MCU_MK22F25612) /* MCM */ && \ + !defined(MCU_MK22F51212) /* MCM */ && \ + !defined(MCU_MK24F12) /* MCM */ && \ + !defined(MCU_MK30D10) /* MCM */ && \ + !defined(MCU_MK30D7) /* MCM */ && \ + !defined(MCU_MK30DZ10) /* MCM */ && \ + !defined(MCU_MK40D10) /* MCM */ && \ + !defined(MCU_MK40D7) /* MCM */ && \ + !defined(MCU_MK40DZ10) /* MCM */ && \ + !defined(MCU_MK40X256VMD100) /* MCM */ && \ + !defined(MCU_MK50D10) /* MCM */ && \ + !defined(MCU_MK50D7) /* MCM */ && \ + !defined(MCU_MK50DZ10) /* MCM */ && \ + !defined(MCU_MK51D10) /* MCM */ && \ + !defined(MCU_MK51D7) /* MCM */ && \ + !defined(MCU_MK51DZ10) /* MCM */ && \ + !defined(MCU_MK52D10) /* MCM */ && \ + !defined(MCU_MK52DZ10) /* MCM */ && \ + !defined(MCU_MK53D10) /* MCM */ && \ + !defined(MCU_MK53DZ10) /* MCM */ && \ + !defined(MCU_MK60D10) /* MCM */ && \ + !defined(MCU_MK60F12) /* MCM */ && \ + !defined(MCU_MK60F15) /* MCM */ && \ + !defined(MCU_MK60DZ10) /* MCM */ && \ + !defined(MCU_MK60N512VMD100) /* MCM */ && \ + !defined(MCU_MK61F12) /* MCM */ && \ + !defined(MCU_MK61F15) /* MCM */ && \ + !defined(MCU_MK61F12WS) /* MCM */ && \ + !defined(MCU_MK61F15WS) /* MCM */ && \ + !defined(MCU_MK63F12) /* MCM */ && \ + !defined(MCU_MK63F12WS) /* MCM */ && \ + !defined(MCU_MK64F12) /* MCM */ && \ + !defined(MCU_MK65F18) /* MCM */ && \ + !defined(MCU_MK65F18WS) /* MCM */ && \ + !defined(MCU_MK66F18) /* MCM */ && \ + !defined(MCU_MK70F12) /* MCM */ && \ + !defined(MCU_MK70F15) /* MCM */ && \ + !defined(MCU_MK70F12WS) /* MCM */ && \ + !defined(MCU_MK70F15WS) /* MCM */ && \ + !defined(MCU_MKE02Z2) /* MCM */ && \ + !defined(MCU_MKE02Z4) /* MCM */ && \ + !defined(MCU_SKEAZN642) /* MCM */ && \ + !defined(MCU_MKE04Z1284) /* MCM */ && \ + !defined(MCU_MKE04Z4) /* MCM */ && \ + !defined(MCU_SKEAZN84) /* MCM */ && \ + !defined(MCU_MKE06Z4) /* MCM */ && \ + !defined(MCU_MKL02Z4) /* MCM */ && \ + !defined(MCU_MKL03Z4) /* MCM */ && \ + !defined(MCU_MKL04Z4) /* MCM */ && \ + !defined(MCU_MKL05Z4) /* MCM */ && \ + !defined(MCU_MKL14Z4) /* MCM */ && \ + !defined(MCU_MKL15Z4) /* MCM */ && \ + !defined(MCU_MKL16Z4) /* MCM */ && \ + !defined(MCU_MKL24Z4) /* MCM */ && \ + !defined(MCU_MKL25Z4) /* MCM */ && \ + !defined(MCU_MKL26Z4) /* MCM */ && \ + !defined(MCU_MKL34Z4) /* MCM */ && \ + !defined(MCU_MKL36Z4) /* MCM */ && \ + !defined(MCU_MKL46Z4) /* MCM */ && \ + !defined(MCU_MKV10Z7) /* MCM */ && \ + !defined(MCU_MKV31F12810) /* MCM */ && \ + !defined(MCU_MKV31F25612) /* MCM */ && \ + !defined(MCU_MKV31F51212) /* MCM */ && \ + !defined(MCU_MKW01Z4) /* MCM */ && \ + !defined(MCU_MKW21D5) /* MCM */ && \ + !defined(MCU_MKW21D5WS) /* MCM */ && \ + !defined(MCU_MKW22D5) /* MCM */ && \ + !defined(MCU_MKW22D5WS) /* MCM */ && \ + !defined(MCU_MKW24D5) /* MCM */ && \ + !defined(MCU_MKW24D5WS) /* MCM */ && \ + !defined(MCU_SKEAZ1284) /* MCM */ + // Unsupported MCU is active + #error MCM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Slave bus connection to AXBS input port masks constants (for + GetSlaveBusConnectionToAxbsInputPort macro). */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_0 0x1U /**< A bus slave connection to AXBS input port 0 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_1 0x2U /**< A bus slave connection to AXBS input port 1 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_2 0x4U /**< A bus slave connection to AXBS input port 2 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_3 0x8U /**< A bus slave connection to AXBS input port 3 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_4 0x10U /**< A bus slave connection to AXBS input port 4 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_5 0x20U /**< A bus slave connection to AXBS input port 5 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_6 0x40U /**< A bus slave connection to AXBS input port 6 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_7 0x80U /**< A bus slave connection to AXBS input port 7 is present */ + +/* Master bus connection to AXBS input port masks constants (for + GetMasterBusConnectionToAxbsInputPortMask macro). */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_0 0x1U /**< A bus master connection to AXBS input port 0 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_1 0x2U /**< A bus master connection to AXBS input port 1 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_2 0x4U /**< A bus master connection to AXBS input port 2 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_3 0x8U /**< A bus master connection to AXBS input port 3 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_4 0x10U /**< A bus master connection to AXBS input port 4 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_5 0x20U /**< A bus master connection to AXBS input port 5 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_6 0x40U /**< A bus master connection to AXBS input port 6 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_7 0x80U /**< A bus master connection to AXBS input port 7 is present */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/* Crossbar master arbitration type */ + #define MCM_PDD_FIXED_PRIORITY 0U /**< Fixed-priority arbitration for the crossbar masters */ + #define MCM_PDD_ROUND_ROBIN 0x200U /**< Round-robin arbitration for the crossbar masters */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Crossbar master arbitration type */ + #define MCM_PDD_FIXED_PRIORITY 0U /**< Fixed-priority arbitration for the crossbar masters */ + #define MCM_PDD_ROUND_ROBIN 0x1U /**< Round-robin arbitration for the crossbar masters */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSlaveBusConnectionToAxbsInputPortMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns present mask value of a corresponding connection to the + * crossbar switch's slave input port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: MCM_PLASC. + * @par Example: + * @code + * uint8 result = + * MCM_PDD_GetSlaveBusConnectionToAxbsInputPortMask(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetSlaveBusConnectionToAxbsInputPortMask(PeripheralBase) ( \ + (uint8)(MCM_PLASC_REG(PeripheralBase) & MCM_PLASC_ASC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCrossbarSwitchSlaveConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads crossbar switch (AXBS) slave configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: MCM_PLASC. + * @par Example: + * @code + * uint16 result = + * MCM_PDD_ReadCrossbarSwitchSlaveConfigurationReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadCrossbarSwitchSlaveConfigurationReg(PeripheralBase) ( \ + MCM_PLASC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMasterBusConnectionToAxbsInputPortMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns present mask value of a corresponding connection to the + * crossbar switch's master input port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: MCM_PLAMC. + * @par Example: + * @code + * uint8 result = + * MCM_PDD_GetMasterBusConnectionToAxbsInputPortMask(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetMasterBusConnectionToAxbsInputPortMask(PeripheralBase) ( \ + (uint8)(MCM_PLAMC_REG(PeripheralBase) & MCM_PLAMC_AMC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCrossbarSwitchMasterConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads crossbar switch (AXBS) master configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: MCM_PLAMC. + * @par Example: + * @code + * uint16 result = + * MCM_PDD_ReadCrossbarSwitchMasterConfigurationReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadCrossbarSwitchMasterConfigurationReg(PeripheralBase) ( \ + MCM_PLAMC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCrossbarMastersArbitrationType + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects arbitration type for crossbar masters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Crossbar masters arbitration type. This parameter is of + * "Crossbar master arbitration type" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_SetCrossbarMastersArbitrationType(_BASE_PTR, + * MCM_PDD_FIXED_PRIORITY); + * @endcode + */ +#define MCM_PDD_SetCrossbarMastersArbitrationType(PeripheralBase, State) ( \ + MCM_PLACR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(MCM_PLACR_REG(PeripheralBase) & (uint32)(~(uint32)MCM_PLACR_ARB_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlatformControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads platform control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * uint32 result = MCM_PDD_ReadPlatformControlReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadPlatformControlReg(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlatformControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into platform control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the platform control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_WritePlatformControlReg(_BASE_PTR, 1); + * @endcode + */ +#define MCM_PDD_WritePlatformControlReg(PeripheralBase, Value) ( \ + MCM_PLACR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableStallingFlashController + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable stalling flash controller. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableStallingFlashController(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableStallingFlashController(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_ESFC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStallingFlashController + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable stalling flash controller. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableStallingFlashController(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableStallingFlashController(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_ESFC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashDataSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash data speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashDataSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashDataSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_EFDS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashDataSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash data speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashDataSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashDataSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_EFDS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controllerCache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controllerCache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerInstructionCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller instruction caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerInstructionCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerInstructionCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCIC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerInstructionCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller instruction caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerInstructionCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerInstructionCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCIC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerDataCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller data caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerDataCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerDataCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCDA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerDataCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller data caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerDataCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerDataCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCDA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalidateFlashCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_InvalidateFlashCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_CFCC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableComputeOperationWakeupOnInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable compute operation wakeup on interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_EnableComputeOperationWakeupOnInterrupt(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableComputeOperationWakeupOnInterrupt(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) |= \ + MCM_CPO_CPOWOI_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComputeOperationState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non zero value if compute operation entry has completed or + * compute operation exit has not completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_GetComputeOperationState(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetComputeOperationState(PeripheralBase) ( \ + (uint32)(MCM_CPO_REG(PeripheralBase) & MCM_CPO_CPOACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non zero value if compute operation request is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_GetComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetComputeOperationRequest(PeripheralBase) ( \ + (uint32)(MCM_CPO_REG(PeripheralBase) & MCM_CPO_CPOREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Set compute operation request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_SetComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_SetComputeOperationRequest(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) |= \ + MCM_CPO_CPOREQ_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear compute operation request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_ClearComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ClearComputeOperationRequest(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_CPO_CPOREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadComputeOperationControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads compute operation control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_ReadComputeOperationControlReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadComputeOperationControlReg(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteComputeOperationControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into compute operation + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the compute operation control register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_WriteComputeOperationControlReg(_BASE_PTR, 1); + * @endcode + */ +#define MCM_PDD_WriteComputeOperationControlReg(PeripheralBase, Value) ( \ + MCM_CPO_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(MCM_PDD_H_) */ + +/* MCM_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h new file mode 100644 index 0000000..3dd641a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h @@ -0,0 +1,1716 @@ +/* + PDD layer implementation for peripheral type PDB + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PDB_PDD_H_) +#define PDB_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PDB PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PDB0 */ && \ + !defined(MCU_MK10D5) /* PDB0 */ && \ + !defined(MCU_MK10D7) /* PDB0 */ && \ + !defined(MCU_MK10F12) /* PDB0 */ && \ + !defined(MCU_MK10DZ10) /* PDB0 */ && \ + !defined(MCU_MK11D5) /* PDB0 */ && \ + !defined(MCU_MK11D5WS) /* PDB0 */ && \ + !defined(MCU_MK12D5) /* PDB0 */ && \ + !defined(MCU_MK20D10) /* PDB0 */ && \ + !defined(MCU_MK20D5) /* PDB0 */ && \ + !defined(MCU_MK20D7) /* PDB0 */ && \ + !defined(MCU_MK20F12) /* PDB0 */ && \ + !defined(MCU_MK20DZ10) /* PDB0 */ && \ + !defined(MCU_MK21D5) /* PDB0 */ && \ + !defined(MCU_MK21D5WS) /* PDB0 */ && \ + !defined(MCU_MK21F12) /* PDB0 */ && \ + !defined(MCU_MK21F12WS) /* PDB0 */ && \ + !defined(MCU_MK22D5) /* PDB0 */ && \ + !defined(MCU_MK22F12810) /* PDB0 */ && \ + !defined(MCU_MK22F12) /* PDB0 */ && \ + !defined(MCU_MK22F25612) /* PDB0 */ && \ + !defined(MCU_MK22F51212) /* PDB0 */ && \ + !defined(MCU_MK24F12) /* PDB0 */ && \ + !defined(MCU_MK30D10) /* PDB0 */ && \ + !defined(MCU_MK30D7) /* PDB0 */ && \ + !defined(MCU_MK30DZ10) /* PDB0 */ && \ + !defined(MCU_MK40D10) /* PDB0 */ && \ + !defined(MCU_MK40D7) /* PDB0 */ && \ + !defined(MCU_MK40DZ10) /* PDB0 */ && \ + !defined(MCU_MK40X256VMD100) /* PDB0 */ && \ + !defined(MCU_MK50D10) /* PDB0 */ && \ + !defined(MCU_MK50D7) /* PDB0 */ && \ + !defined(MCU_MK50DZ10) /* PDB0 */ && \ + !defined(MCU_MK51D10) /* PDB0 */ && \ + !defined(MCU_MK51D7) /* PDB0 */ && \ + !defined(MCU_MK51DZ10) /* PDB0 */ && \ + !defined(MCU_MK52D10) /* PDB0 */ && \ + !defined(MCU_MK52DZ10) /* PDB0 */ && \ + !defined(MCU_MK53D10) /* PDB0 */ && \ + !defined(MCU_MK53DZ10) /* PDB0 */ && \ + !defined(MCU_MK60D10) /* PDB0 */ && \ + !defined(MCU_MK60F12) /* PDB0 */ && \ + !defined(MCU_MK60F15) /* PDB0 */ && \ + !defined(MCU_MK60DZ10) /* PDB0 */ && \ + !defined(MCU_MK60N512VMD100) /* PDB0 */ && \ + !defined(MCU_MK61F12) /* PDB0 */ && \ + !defined(MCU_MK61F15) /* PDB0 */ && \ + !defined(MCU_MK61F12WS) /* PDB0 */ && \ + !defined(MCU_MK61F15WS) /* PDB0 */ && \ + !defined(MCU_MK63F12) /* PDB0 */ && \ + !defined(MCU_MK63F12WS) /* PDB0 */ && \ + !defined(MCU_MK64F12) /* PDB0 */ && \ + !defined(MCU_MK65F18) /* PDB0 */ && \ + !defined(MCU_MK65F18WS) /* PDB0 */ && \ + !defined(MCU_MK66F18) /* PDB0 */ && \ + !defined(MCU_MK70F12) /* PDB0 */ && \ + !defined(MCU_MK70F15) /* PDB0 */ && \ + !defined(MCU_MK70F12WS) /* PDB0 */ && \ + !defined(MCU_MK70F15WS) /* PDB0 */ && \ + !defined(MCU_MKV10Z7) /* PDB0 */ && \ + !defined(MCU_MKV31F12810) /* PDB0 */ && \ + !defined(MCU_MKV31F25612) /* PDB0 */ && \ + !defined(MCU_MKV31F51212) /* PDB0 */ && \ + !defined(MCU_MKW21D5) /* PDB0 */ && \ + !defined(MCU_MKW21D5WS) /* PDB0 */ && \ + !defined(MCU_MKW22D5) /* PDB0 */ && \ + !defined(MCU_MKW22D5WS) /* PDB0 */ && \ + !defined(MCU_MKW24D5) /* PDB0 */ && \ + !defined(MCU_MKW24D5WS) /* PDB0 */ && \ + !defined(MCU_PCK20L4) /* PDB0 */ + // Unsupported MCU is active + #error PDB PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Interrupt masks. */ +#define PDB_PDD_SEQUENCE_ERROR_INT PDB_SC_PDBEIE_MASK /**< PDB sequence error interrupt mask */ +#define PDB_PDD_INTERRUPT_INT PDB_SC_PDBIE_MASK /**< PDB interrupt mask */ + +/* Trigger masks. */ +#define PDB_PDD_PRE_TRIGGER_0 0x1U /**< Trigger 0 mask. */ +#define PDB_PDD_PRE_TRIGGER_1 0x2U /**< Trigger 1 mask. */ +#define PDB_PDD_PRE_TRIGGER_2 0x4U /**< Trigger 2 mask. */ +#define PDB_PDD_PRE_TRIGGER_3 0x8U /**< Trigger 3 mask. */ +#define PDB_PDD_PRE_TRIGGER_4 0x10U /**< Trigger 4 mask. */ +#define PDB_PDD_PRE_TRIGGER_5 0x20U /**< Trigger 5 mask. */ +#define PDB_PDD_PRE_TRIGGER_6 0x40U /**< Trigger 6 mask. */ +#define PDB_PDD_PRE_TRIGGER_7 0x80U /**< Trigger 7 mask. */ + +/* Channel pre-trigger status constants. */ +#define PDB_PDD_PRE_TRIGGER_FLAG_0 0x10000U /**< Pre-Trigger channel flag 0 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_1 0x20000U /**< Pre-Trigger channel flag 1 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_2 0x40000U /**< Pre-Trigger channel flag 2 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_3 0x80000U /**< Pre-Trigger channel flag 3 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_4 0x100000U /**< Pre-Trigger channel flag 4 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_5 0x200000U /**< Pre-Trigger channel flag 5 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_6 0x400000U /**< Pre-Trigger channel flag 6 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_7 0x800000U /**< Pre-Trigger channel flag 7 mask */ +#define PDB_PDD_PRE_TRIGGER_ALL_FLAGS 0xFF0000U /**< Pre-Trigger channel all flags mask */ + +/* Pre-trigger sequence error constants. */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_0 0x1U /**< Pre-Trigger sequence error flag 0 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_1 0x2U /**< Pre-Trigger sequence error flag 1 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_2 0x4U /**< Pre-Trigger sequence error flag 2 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_3 0x8U /**< Pre-Trigger sequence error flag 3 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_4 0x10U /**< Pre-Trigger sequence error flag 4 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_5 0x20U /**< Pre-Trigger sequence error flag 5 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_6 0x40U /**< Pre-Trigger sequence error flag 6 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_7 0x80U /**< Pre-Trigger sequence error flag 7 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_ALL_FLAGS 0x80U /**< Pre-Trigger sequence all error flags mask */ + +/* Load mode constants */ +#define PDB_PDD_LOAD_IMMEDIATE 0U /**< The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED_WITH_COUNTER 0x40000U /**< The internal registers are loaded with the values from their buffers when the PDB counter reaches the PDB_MOD register value after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED_WITH_INPUT_TRIGGER 0x80000U /**< The internal registers are loaded with the values from their buffers when the PDB counter reaches the PDB_MOD register value after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED 0xC0000U /**< The internal registers are loaded with the values from their buffers when either the PDB counter reaches the PDB_MOD register value or a trigger input event is detected, after 1 is written to LDOK */ + +/* Prescaler divider constants */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_1 0U /**< Divide by 1 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_2 0x1000U /**< Divide by 2 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_4 0x2000U /**< Divide by 4 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_8 0x3000U /**< Divide by 8 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_16 0x4000U /**< Divide by 16 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_32 0x5000U /**< Divide by 32 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_64 0x6000U /**< Divide by 64 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_128 0x7000U /**< Divide by 128 */ + +/* Trigger input source constants */ +#define PDB_PDD_TRIGGER_INPUT_0 0U /**< Trigger-Input 0 */ +#define PDB_PDD_TRIGGER_INPUT_1 0x1U /**< Trigger-Input 1 */ +#define PDB_PDD_TRIGGER_INPUT_2 0x2U /**< Trigger-Input 2 */ +#define PDB_PDD_TRIGGER_INPUT_3 0x3U /**< Trigger-Input 3 */ +#define PDB_PDD_TRIGGER_INPUT_4 0x4U /**< Trigger-Input 4 */ +#define PDB_PDD_TRIGGER_INPUT_5 0x5U /**< Trigger-Input 5 */ +#define PDB_PDD_TRIGGER_INPUT_6 0x6U /**< Trigger-Input 6 */ +#define PDB_PDD_TRIGGER_INPUT_7 0x7U /**< Trigger-Input 7 */ +#define PDB_PDD_TRIGGER_INPUT_8 0x8U /**< Trigger-Input 8 */ +#define PDB_PDD_TRIGGER_INPUT_9 0x9U /**< Trigger-Input 9 */ +#define PDB_PDD_TRIGGER_INPUT_10 0xAU /**< Trigger-Input 10 */ +#define PDB_PDD_TRIGGER_INPUT_11 0xBU /**< Trigger-Input 11 */ +#define PDB_PDD_TRIGGER_INPUT_12 0xCU /**< Trigger-Input 12 */ +#define PDB_PDD_TRIGGER_INPUT_13 0xDU /**< Trigger-Input 13 */ +#define PDB_PDD_TRIGGER_INPUT_14 0xEU /**< Trigger-Input 14 */ +#define PDB_PDD_TRIGGER_INPUT_15 0xFU /**< Trigger-Input 15 */ +#define PDB_PDD_SOFTWARE_TRIGGER 0x10U /**< Software trigger */ + +/* Multiplication factor for prescalerconstants */ +#define PDB_PDD_MULTIPLICATION_FACTOR_1 0U /**< Multiplication factor is 1 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_10 0x4U /**< Multiplication factor is 10 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_20 0x8U /**< Multiplication factor is 20 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_40 0xCU /**< Multiplication factor is 40 */ + + +/* ---------------------------------------------------------------------------- + -- SelectLoadMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects load register mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Load register mode value. The user should use one from the + * enumerated values. This parameter is of "Load mode constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectLoadMode(_BASE_PTR, PDB_PDD_LOAD_IMMEDIATE); + * @endcode + */ +#define PDB_PDD_SelectLoadMode(PeripheralBase, Mode) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_LDMOD_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks.". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableInterrupt(_BASE_PTR, + * PDB_PDD_SEQUENCE_ERROR_INT); + * @endcode + */ +#define PDB_PDD_EnableInterrupt(PeripheralBase, Mask) ( \ + PDB_SC_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks.". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_DisableInterrupt(_BASE_PTR, + * PDB_PDD_SEQUENCE_ERROR_INT); + * @endcode + */ +#define PDB_PDD_DisableInterrupt(PeripheralBase, Mask) ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SoftwareTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets and restarts the counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SoftwareTrigger(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_SoftwareTrigger(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_SWTRIG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of DMA function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_DMAEN_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects prescaler divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider Prescaler divider value. The user should use one from the + * enumerated values. This parameter is of "Prescaler divider constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectPrescalerDivider(_BASE_PTR, + * PDB_PDD_PRESCALER_DIVIDE_BY_1); + * @endcode + */ +#define PDB_PDD_SelectPrescalerDivider(PeripheralBase, Divider) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_PRESCALER_MASK))) | ( \ + (uint32)(Divider))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectTriggerInputSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects trigger input source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Trigger input source. The user should use one from the + * enumerated values. This parameter is of "Trigger input source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectTriggerInputSource(_BASE_PTR, + * PDB_PDD_TRIGGER_INPUT_0); + * @endcode + */ +#define PDB_PDD_SelectTriggerInputSource(PeripheralBase, Source) ( \ + ((Source) == PDB_PDD_TRIGGER_INPUT_0) ? ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)PDB_SC_TRGSEL_MASK)) : (((Source) == PDB_PDD_TRIGGER_INPUT_1) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x1U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_2) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x2U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_3) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x3U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_4) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x4U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_5) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x5U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_6) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x6U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_7) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x7U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_8) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x8U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_9) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x9U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_10) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xAU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_11) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xBU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_12) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xCU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_13) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xDU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_14) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xEU << PDB_SC_TRGSEL_SHIFT)))) : ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_TRGSEL_MASK) \ + )))))))))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables PDB device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDevice(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_PDBEN_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_PDBEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value of the PDB interrupt flag. Flag is set when the + * counter value is equal to the IDLY register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * uint32 result = PDB_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(PDB_SC_REG(PeripheralBase) & PDB_SC_PDBIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ClearInterruptFlag(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)PDB_SC_PDBIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectMultiplicationFactor + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects multiplication factor for prescaler. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Factor Multiplication factor value. The user should use one from the + * enumerated values. This parameter is of "Multiplication factor for + * prescalerconstants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectMultiplicationFactor(_BASE_PTR, + * PDB_PDD_MULTIPLICATION_FACTOR_1); + * @endcode + */ +#define PDB_PDD_SelectMultiplicationFactor(PeripheralBase, Factor) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_MULT_MASK))) | ( \ + (uint32)(Factor))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the PDB operation in continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of continuous operation mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableContinuousMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableContinuousMode(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_CONT_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_CONT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- LoadInternalRegisters + ---------------------------------------------------------------------------- */ + +/** + * @brief Updates the internal registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_LoadInternalRegisters(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_LoadInternalRegisters(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_LDOK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusAndControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the status and control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_WriteStatusAndControlReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteStatusAndControlReg(PeripheralBase, Value) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusAndControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_ReadStatusAndControlReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadStatusAndControlReg(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetModulusValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the modulus value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Modulus value[0..65535]. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * PDB_PDD_SetModulusValue(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_SetModulusValue(PeripheralBase, Value) ( \ + PDB_MOD_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_MOD_REG(PeripheralBase) & (uint32)(~(uint32)PDB_MOD_MOD_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModulusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the modulus register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the modulus register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * PDB_PDD_WriteModulusReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteModulusReg(PeripheralBase, Value) ( \ + PDB_MOD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModulusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the modulus register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadModulusReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadModulusReg(PeripheralBase) ( \ + PDB_MOD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCounterValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: PDB0_CNT. + * @par Example: + * @code + * uint16 result = PDB_PDD_GetCounterValue(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetCounterValue(PeripheralBase) ( \ + (uint16)(PDB_CNT_REG(PeripheralBase) & PDB_CNT_CNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_CNT. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadCounterReg(PeripheralBase) ( \ + PDB_CNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInterruptDelayValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the interrupt delay value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Interrupt delay value[0..65535]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * PDB_PDD_SetInterruptDelayValue(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_SetInterruptDelayValue(PeripheralBase, Value) ( \ + PDB_IDLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_IDLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_IDLY_IDLY_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptDelayValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt delay value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * uint16 result = PDB_PDD_GetInterruptDelayValue(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetInterruptDelayValue(PeripheralBase) ( \ + (uint16)(PDB_IDLY_REG(PeripheralBase) & PDB_IDLY_IDLY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInterruptDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the interrupt delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the interrupt delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * PDB_PDD_WriteInterruptDelayReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteInterruptDelayReg(PeripheralBase, Value) ( \ + PDB_IDLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the interrupt delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadInterruptDelayReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadInterruptDelayReg(PeripheralBase) ( \ + PDB_IDLY_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPreTriggerBackToBackMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables (specified by mask parameters) the PDB pre-trigger + * operation as back-to-back mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Enable Trigger mask defining which pre-trigger back-to-back operation + * is disabled. Use constants from group "Trigger masks.". This parameter + * is 8 bits wide. + * @param Disable Trigger mask defining which pre-trigger back-to-back operation + * is enabled. Use constants from group "Trigger masks.". This parameter + * is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_SelectPreTriggerBackToBackMode(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_SelectPreTriggerBackToBackMode(PeripheralBase, Index, Enable, Disable) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_C1_REG(PeripheralBase,(Index))) | ( \ + (uint32)((uint32)(Enable) << PDB_C1_BB_SHIFT)))) & ( \ + (uint32)(~(uint32)((uint32)(Disable) << PDB_C1_BB_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPreTriggerOutputMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the PDB pre-trigger bypassed/delay output operation mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Bypass Trigger mask defining which pre-trigger output operation is + * bypassed. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @param Delay Trigger mask defining which pre-trigger output operation is + * delayed. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_SelectPreTriggerOutputMode(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_SelectPreTriggerOutputMode(PeripheralBase, Index, Bypass, Delay) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_C1_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)((uint32)(Bypass) << PDB_C1_TOS_SHIFT))))) | ( \ + (uint32)((uint32)(Delay) << PDB_C1_TOS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePreTriggerOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/Disables the PDB pre-trigger output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Enable Trigger mask defining which pre-trigger output is enabled. Use + * constants from group "Trigger masks.". This parameter is 8 bits wide. + * @param Disable Trigger mask defining which pre-trigger output is disabled. + * Use constants from group "Trigger masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_EnablePreTriggerOutput(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_EnablePreTriggerOutput(PeripheralBase, Index, Enable, Disable) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(PDB_C1_REG(PeripheralBase,(Index)) | (uint32)(Enable))) & ( \ + (uint32)(~(uint32)(Disable)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the channel control register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_WriteChannelControlReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteChannelControlReg(PeripheralBase, Index, Value) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelControlReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelControlReg(PeripheralBase, Index) ( \ + PDB_C1_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelPreTriggerFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PDB channel pre-trigger flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_GetChannelPreTriggerFlags(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_GetChannelPreTriggerFlags(PeripheralBase, Index) ( \ + (uint32)(PDB_S_REG(PeripheralBase,(Index)) & PDB_S_CF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelPreTriggerFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PDB channel pre-trigger flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Mask Pre-trigger flag mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_ClearChannelPreTriggerFlags(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_ClearChannelPreTriggerFlags(PeripheralBase, Index, Mask) ( \ + PDB_S_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelPreTriggerSequenceErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PDB channel pre-trigger sequence error flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_GetChannelPreTriggerSequenceErrorFlags(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_GetChannelPreTriggerSequenceErrorFlags(PeripheralBase, Index) ( \ + (uint32)(PDB_S_REG(PeripheralBase,(Index)) & PDB_S_ERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelPreTriggerSequenceErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PDB channel pre-trigger sequence error flags defined by + * mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Mask Pre-trigger sequence error flag mask. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_ClearChannelPreTriggerSequenceErrorFlags(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_ClearChannelPreTriggerSequenceErrorFlags(PeripheralBase, Index, Mask) ( \ + PDB_S_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the channel status register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_WriteChannelStatusReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteChannelStatusReg(PeripheralBase, Index, Value) ( \ + PDB_S_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelStatusReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelStatusReg(PeripheralBase, Index) ( \ + PDB_S_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelPreTriggerDelay + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets delay value for the PDB channel's corresponding pre-trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param PreTriggerIdx Pre-trigger index. This parameter is of index type. + * @param Value Pre-trigger channel delay value. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][PreTriggerIdx]. + * @par Example: + * @code + * PDB_PDD_SetChannelPreTriggerDelay(_BASE_PTR, periphID, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_SetChannelPreTriggerDelay(PeripheralBase, ChannelIdx, PreTriggerIdx, Value) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(PreTriggerIdx)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(PreTriggerIdx))) & ( \ + (uint32)(~(uint32)PDB_DLY_DLY_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param RegisterIdx Delay register index. This parameter is of index type. + * @param Value Value stored to the channel delay register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][RegisterIdx]. + * @par Example: + * @code + * PDB_PDD_WriteChannelDelayReg(_BASE_PTR, periphID, periphID, + * 1); + * @endcode + */ +#define PDB_PDD_WriteChannelDelayReg(PeripheralBase, ChannelIdx, RegisterIdx, Value) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(RegisterIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param RegisterIdx Delay register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][RegisterIdx]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelDelayReg(_BASE_PTR, + * periphID, periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelDelayReg(PeripheralBase, ChannelIdx, RegisterIdx) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(RegisterIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDacExternalTriggerInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DAC external trigger input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param State Parameter specifying if DAC external trigger input will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_EnableDacExternalTriggerInput(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDacExternalTriggerInput(PeripheralBase, Index, State) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_INTC_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_INTC_EXT_MASK)))) | ( \ + (uint32)((uint32)(State) << PDB_INTC_EXT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDacIntervalTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DAC interval trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param State Parameter specifying if DAC interval trigger will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_EnableDacIntervalTrigger(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDacIntervalTrigger(PeripheralBase, Index, State) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_INTC_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_INTC_TOE_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacIntervalTrigerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DACx interval trigger control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @param Value Value stored to the DACx interval trigger control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_WriteDacIntervalTrigerControlReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteDacIntervalTrigerControlReg(PeripheralBase, Index, Value) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacIntervalTrigerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DACx interval trigger control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_ReadDacIntervalTrigerControlReg(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_ReadDacIntervalTrigerControlReg(PeripheralBase, Index) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDacIntervalTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DAC interval trigger value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param Value DAC intervaltrigger value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * PDB_PDD_SetDacIntervalTrigger(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_SetDacIntervalTrigger(PeripheralBase, Index, Value) ( \ + PDB_INT_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(PDB_INT_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)PDB_INT_INT_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacIntervalReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DACx interval register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @param Value Value stored to the DACx interval register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * PDB_PDD_WriteDacIntervalReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteDacIntervalReg(PeripheralBase, Index, Value) ( \ + PDB_INT_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacIntervalReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DACx interval register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadDacIntervalReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadDacIntervalReg(PeripheralBase, Index) ( \ + PDB_INT_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePreTriggerPulseOut + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the PDB pre-trigger pulse output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Pre-trigger mask defining which pre-trigger pulse output is + * disabled. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @param Disable Pre-trigger mask defining which pre-trigger pulse output is + * enabled. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * PDB_PDD_EnablePreTriggerPulseOut(_BASE_PTR, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_EnablePreTriggerPulseOut(PeripheralBase, Enable, Disable) ( \ + PDB_POEN_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_POEN_REG(PeripheralBase) | (uint32)(Enable))) & ( \ + (uint32)(~(uint32)(Disable)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePulseOutEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the pulse-out enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out enable register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * PDB_PDD_WritePulseOutEnableReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WritePulseOutEnableReg(PeripheralBase, Index, Value) ( \ + PDB_POEN_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPulseOutEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the pulse-out enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutEnableReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadPulseOutEnableReg(PeripheralBase, Index) ( \ + PDB_POEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPulseOutDelay1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets the PDB pulse output delay 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 1 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay1(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay1(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_PODLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_PODLY_DLY1_MASK))) | ( \ + (uint32)((uint32)(Value) << PDB_PODLY_DLY1_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the PDB pulse output delay 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 1 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay1(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay1(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_PODLY_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_PODLY_DLY1_MASK)))) | ( \ + (uint32)((uint32)(Value) << PDB_PODLY_DLY1_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPulseOutDelay2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets the PDB pulse output delay 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 2 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay2(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay2(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_PODLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_PODLY_DLY2_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the PDB pulse output delay 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 2 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay2(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay2(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_PODLY_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_PODLY_DLY2_MASK)))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WritePulseOutDelayReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Writes value to the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_WritePulseOutDelayReg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_WritePulseOutDelayReg(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_WritePulseOutDelayReg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_WritePulseOutDelayReg(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPulseOutDelayReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Returns the content of the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutDelayReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define PDB_PDD_ReadPulseOutDelayReg(PeripheralBase, Index) ( \ + PDB_PODLY_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutDelayReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define PDB_PDD_ReadPulseOutDelayReg(PeripheralBase, Index) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#endif /* #if defined(PDB_PDD_H_) */ + +/* PDB_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h new file mode 100644 index 0000000..5860196 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h @@ -0,0 +1,69 @@ +/* Common type declarations for PDD layer */ +/* This file is static and it is generated from API-Factory */ + +#ifndef PDD_TYPES_H_ +#define PDD_TYPES_H_ + +/* --------------------------------------------------------------- */ +/* --------- PDD_TBool */ +/* --------------------------------------------------------------- */ + +/* Implementation note for boolean type: */ +/* Native "bool" type should be used for boolean values */ +/* because the compiler provides optimization and best type representation. */ +/* If the compiler does not support native "bool" type, common "Bool" */ +/* at each place there should be used the most suitable integer type */ +/* and no explicit conversion to 0 and 1 values should be used. */ +/* Common "TBool" typedef could have possible performance issue */ +/* (there is a problem how wide type to select). It is good to avoid using */ +/* explicit "!= 0" because of performance penalty, but without such */ +/* explicit conversion to 0/1 the resulting type may be too wide. */ +/* Every bool type (native or replaced by integer value) should be always */ +/* treated as zero-equal or non-zero (see below for examples). */ + +/* E.g.: This compiler supports boolean type only in C++ mode. */ +/* Out of the C++ mode the boolean type must be simulated. */ + +#ifndef __cplusplus +typedef uint16 PDD_TBool; +#else +typedef bool PDD_TBool; +#endif + +/* ============================================================================ + ================== General PDD macros ====================================== + ============================================================================ */ + +#define PDD_DISABLE 0u +#define PDD_ENABLE 1u + +/* ============================================================================ + ================== General register manipulating routines ================== + ============================================================================ */ + +#define setReg8(Reg, val) ((Reg) = (uint8)(val)) +#define getReg8(Reg) (Reg) +#define testReg8Bits(Reg, GetMask) ((Reg) & (uint8)(GetMask)) +#define clrReg8Bits(Reg, ClrMask) ((Reg) &= (uint8)((uint8)(~(uint8)(ClrMask)))) +#define setReg8Bits(Reg, SetMask) ((Reg) |= (uint8)(SetMask)) +#define invertReg8Bits(Reg, InvMask) ((Reg) ^= (uint8)(InvMask)) +#define clrSetReg8Bits(Reg, ClrMask, SetMask) ((Reg) = (uint8)(((Reg) & (uint8)(~(uint8)(ClrMask))) | (uint8)(SetMask))) + +#define setReg16(Reg, val) ((Reg) = (uint16)(val)) +#define getReg16(Reg) (Reg) +#define testReg16Bits(Reg, GetMask) ((Reg) & (uint16)(GetMask)) +#define clrReg16Bits(Reg, ClrMask) ((Reg) &= (uint16)(~(uint16)(ClrMask))) +#define setReg16Bits(Reg, SetMask) ((Reg) |= (uint16)(SetMask)) +#define invertReg16Bits(Reg, InvMask) ((Reg) ^= (uint16)(InvMask)) +#define clrSetReg16Bits(Reg, ClrMask, SetMask) ((Reg) = (uint16)(((Reg) & (uint16)(~(uint16)(ClrMask))) | (uint16)(SetMask))) + +#define setReg32(Reg, val) ((Reg) = (uint32)(val)) +#define getReg32(Reg) (Reg) +#define testReg32Bits(Reg, GetMask) ((Reg) & (uint32)(GetMask)) +#define clrReg32Bits(Reg, ClrMask) ((Reg) &= (uint32)(~(uint32)(ClrMask))) +#define setReg32Bits(Reg, SetMask) ((Reg) |= (uint32)(SetMask)) +#define invertReg32Bits(Reg, InvMask) ((Reg) ^= (uint32)(InvMask)) +#define clrSetReg32Bits(Reg, ClrMask, SetMask) ((Reg) = (uint32)(((Reg) & (uint32)(~(uint32)(ClrMask))) | (uint32)(SetMask))) + + +#endif /* #if !defined(PDD_TYPES_H_) */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h new file mode 100644 index 0000000..c8c5d69 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h @@ -0,0 +1,602 @@ +/* + PDD layer implementation for peripheral type PIT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PIT_PDD_H_) +#define PIT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PIT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PIT */ && \ + !defined(MCU_MK10D5) /* PIT */ && \ + !defined(MCU_MK10D7) /* PIT */ && \ + !defined(MCU_MK10F12) /* PIT */ && \ + !defined(MCU_MK10DZ10) /* PIT */ && \ + !defined(MCU_MK11D5) /* PIT */ && \ + !defined(MCU_MK11D5WS) /* PIT */ && \ + !defined(MCU_MK12D5) /* PIT */ && \ + !defined(MCU_MK20D10) /* PIT */ && \ + !defined(MCU_MK20D5) /* PIT */ && \ + !defined(MCU_MK20D7) /* PIT */ && \ + !defined(MCU_MK20F12) /* PIT */ && \ + !defined(MCU_MK20DZ10) /* PIT */ && \ + !defined(MCU_MK21D5) /* PIT */ && \ + !defined(MCU_MK21D5WS) /* PIT */ && \ + !defined(MCU_MK21F12) /* PIT */ && \ + !defined(MCU_MK21F12WS) /* PIT */ && \ + !defined(MCU_MK22D5) /* PIT */ && \ + !defined(MCU_MK22F12810) /* PIT */ && \ + !defined(MCU_MK22F12) /* PIT */ && \ + !defined(MCU_MK22F25612) /* PIT */ && \ + !defined(MCU_MK22F51212) /* PIT */ && \ + !defined(MCU_MK24F12) /* PIT */ && \ + !defined(MCU_MK30D10) /* PIT */ && \ + !defined(MCU_MK30D7) /* PIT */ && \ + !defined(MCU_MK30DZ10) /* PIT */ && \ + !defined(MCU_MK40D10) /* PIT */ && \ + !defined(MCU_MK40D7) /* PIT */ && \ + !defined(MCU_MK40DZ10) /* PIT */ && \ + !defined(MCU_MK40X256VMD100) /* PIT */ && \ + !defined(MCU_MK50D10) /* PIT */ && \ + !defined(MCU_MK50D7) /* PIT */ && \ + !defined(MCU_MK50DZ10) /* PIT */ && \ + !defined(MCU_MK51D10) /* PIT */ && \ + !defined(MCU_MK51D7) /* PIT */ && \ + !defined(MCU_MK51DZ10) /* PIT */ && \ + !defined(MCU_MK52D10) /* PIT */ && \ + !defined(MCU_MK52DZ10) /* PIT */ && \ + !defined(MCU_MK53D10) /* PIT */ && \ + !defined(MCU_MK53DZ10) /* PIT */ && \ + !defined(MCU_MK60D10) /* PIT */ && \ + !defined(MCU_MK60F12) /* PIT */ && \ + !defined(MCU_MK60F15) /* PIT */ && \ + !defined(MCU_MK60DZ10) /* PIT */ && \ + !defined(MCU_MK60N512VMD100) /* PIT */ && \ + !defined(MCU_MK61F12) /* PIT */ && \ + !defined(MCU_MK61F15) /* PIT */ && \ + !defined(MCU_MK61F12WS) /* PIT */ && \ + !defined(MCU_MK61F15WS) /* PIT */ && \ + !defined(MCU_MK63F12) /* PIT */ && \ + !defined(MCU_MK63F12WS) /* PIT */ && \ + !defined(MCU_MK64F12) /* PIT */ && \ + !defined(MCU_MK65F18) /* PIT */ && \ + !defined(MCU_MK65F18WS) /* PIT */ && \ + !defined(MCU_MK66F18) /* PIT */ && \ + !defined(MCU_MK70F12) /* PIT */ && \ + !defined(MCU_MK70F15) /* PIT */ && \ + !defined(MCU_MK70F12WS) /* PIT */ && \ + !defined(MCU_MK70F15WS) /* PIT */ && \ + !defined(MCU_MKE02Z2) /* PIT */ && \ + !defined(MCU_MKE02Z4) /* PIT */ && \ + !defined(MCU_SKEAZN642) /* PIT */ && \ + !defined(MCU_MKE04Z1284) /* PIT */ && \ + !defined(MCU_MKE04Z4) /* PIT */ && \ + !defined(MCU_SKEAZN84) /* PIT */ && \ + !defined(MCU_MKE06Z4) /* PIT */ && \ + !defined(MCU_MKL04Z4) /* PIT */ && \ + !defined(MCU_MKL05Z4) /* PIT */ && \ + !defined(MCU_MKL14Z4) /* PIT */ && \ + !defined(MCU_MKL15Z4) /* PIT */ && \ + !defined(MCU_MKL16Z4) /* PIT */ && \ + !defined(MCU_MKL24Z4) /* PIT */ && \ + !defined(MCU_MKL25Z4) /* PIT */ && \ + !defined(MCU_MKL26Z4) /* PIT */ && \ + !defined(MCU_MKL34Z4) /* PIT */ && \ + !defined(MCU_MKL36Z4) /* PIT */ && \ + !defined(MCU_MKL46Z4) /* PIT */ && \ + !defined(MCU_MKV31F12810) /* PIT */ && \ + !defined(MCU_MKV31F25612) /* PIT */ && \ + !defined(MCU_MKV31F51212) /* PIT */ && \ + !defined(MCU_MKW01Z4) /* PIT */ && \ + !defined(MCU_MKW21D5) /* PIT */ && \ + !defined(MCU_MKW21D5WS) /* PIT */ && \ + !defined(MCU_MKW22D5) /* PIT */ && \ + !defined(MCU_MKW22D5WS) /* PIT */ && \ + !defined(MCU_MKW24D5) /* PIT */ && \ + !defined(MCU_MKW24D5WS) /* PIT */ && \ + !defined(MCU_PCK20L4) /* PIT */ && \ + !defined(MCU_SKEAZ1284) /* PIT */ + // Unsupported MCU is active + #error PIT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* PIT channel constants */ +#define PIT_PDD_CHANNEL_0 0U /**< 0 */ +#define PIT_PDD_CHANNEL_1 0x1U /**< 1 */ +#define PIT_PDD_CHANNEL_2 0x2U /**< 2 */ +#define PIT_PDD_CHANNEL_3 0x3U /**< 3 */ + +/* Module clock constants */ +#define PIT_PDD_CLOCK_ENABLED 0U /**< Enabled */ +#define PIT_PDD_CLOCK_DISABLED PIT_MCR_MDIS_MASK /**< Disabled */ + +/* Freeze constants */ +#define PIT_PDD_TIMERS_RUN 0U /**< Run */ +#define PIT_PDD_TIMERS_STOPPED PIT_MCR_FRZ_MASK /**< Stopped */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetInterruptMask(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetInterruptMask(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) & PIT_TCTRL_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetInterruptFlag(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) & PIT_TFLG_TIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PIT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_EnableInterrupt(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_EnableInterrupt(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) |= \ + PIT_TCTRL_TIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the PIT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_DisableInterrupt(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_DisableInterrupt(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(~(uint32)PIT_TCTRL_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears PIT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx], + * LDVAL[ChannelIdx] (depending on the peripheral). + * @par Example: + * @code + * PIT_PDD_ClearInterruptFlag(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ClearInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) = \ + PIT_TFLG_TIF_MASK), \ + (void)PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ModuleClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables PIT module clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Clock New value of the clock. Use constants from group "Module clock + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_ModuleClock(_BASE_PTR, PIT_PDD_CLOCK_ENABLED); + * @endcode + */ +#define PIT_PDD_ModuleClock(PeripheralBase, Clock) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PIT_MCR_REG(PeripheralBase) & (uint32)(~(uint32)PIT_MCR_MDIS_MASK))) | ( \ + (uint32)(Clock))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ModuleFreeze + ---------------------------------------------------------------------------- */ + +/** + * @brief Allows the timers to be stopped when the device enters debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Freeze New value of the freeze. Use constants from group "Freeze + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_ModuleFreeze(_BASE_PTR, PIT_PDD_TIMERS_RUN); + * @endcode + */ +#define PIT_PDD_ModuleFreeze(PeripheralBase, Freeze) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PIT_MCR_REG(PeripheralBase) & (uint32)(~(uint32)PIT_MCR_FRZ_MASK))) | ( \ + (uint32)(Freeze))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the load register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LDVAL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteLoadReg(_BASE_PTR, PIT_PDD_CHANNEL_0, 1); + * @endcode + */ +#define PIT_PDD_WriteLoadReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LDVAL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadLoadReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadLoadReg(PeripheralBase, ChannelIdx) ( \ + PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the current timer value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CVAL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerValueReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerValueReg(PeripheralBase, ChannelIdx) ( \ + PIT_CVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PIT channel device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param State Requested state of PIT channel. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_EnableDevice(_BASE_PTR, PIT_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define PIT_PDD_EnableDevice(PeripheralBase, ChannelIdx, State) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx))) & ( \ + (uint32)(~(uint32)PIT_TCTRL_TEN_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of PIT channel device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetEnableDeviceStatus(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetEnableDeviceStatus(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) & PIT_TCTRL_TEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuleControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the module control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the module control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_WriteModuleControlReg(_BASE_PTR, 1); + * @endcode + */ +#define PIT_PDD_WriteModuleControlReg(PeripheralBase, Value) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuleControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the module control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadModuleControlReg(_BASE_PTR); + * @endcode + */ +#define PIT_PDD_ReadModuleControlReg(PeripheralBase) ( \ + PIT_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the timer control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the timer control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteTimerControlReg(_BASE_PTR, PIT_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define PIT_PDD_WriteTimerControlReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the timer control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerControlReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerControlReg(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerFlagReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the timer flag register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the timer flag register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteTimerFlagReg(_BASE_PTR, PIT_PDD_CHANNEL_0, 1); + * @endcode + */ +#define PIT_PDD_WriteTimerFlagReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerFlagReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the timer flag register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerFlagReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerFlagReg(PeripheralBase, ChannelIdx) ( \ + PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) \ + ) +#endif /* #if defined(PIT_PDD_H_) */ + +/* PIT_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h new file mode 100644 index 0000000..7f72e7c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h @@ -0,0 +1,2375 @@ +/* + PDD layer implementation for peripheral type PORT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PORT_PDD_H_) +#define PORT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PORT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK10DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK11D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK11D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK12D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK20DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F12810) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F25612) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F51212) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK24F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40X256VMD100) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK52D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK52DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK53D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK53DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK60F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK60DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60N512VMD100) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK61F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F15WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK63F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK63F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK64F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK65F18) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK65F18WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK66F18) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK70F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F15WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MKE02Z2) /* PORT */ && \ + !defined(MCU_MKE02Z4) /* PORT */ && \ + !defined(MCU_SKEAZN642) /* PORT */ && \ + !defined(MCU_MKE04Z1284) /* PORT */ && \ + !defined(MCU_MKE04Z4) /* PORT */ && \ + !defined(MCU_SKEAZN84) /* PORT */ && \ + !defined(MCU_MKE06Z4) /* PORT */ && \ + !defined(MCU_MKL02Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL03Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL04Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL05Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL14Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL15Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL16Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL24Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL25Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL26Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL34Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL36Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL46Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV10Z7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F12810) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F25612) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F51212) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW01Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW21D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW21D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW22D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW22D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW24D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW24D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_PCK20L4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_SKEAZ1284) /* PORT */ + // Unsupported MCU is active + #error PORT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Pin masks */ +#define PORT_PDD_PIN_0 0x1U /**< Pin 0 mask */ +#define PORT_PDD_PIN_1 0x2U /**< Pin 1 mask */ +#define PORT_PDD_PIN_2 0x4U /**< Pin 2 mask */ +#define PORT_PDD_PIN_3 0x8U /**< Pin 3 mask */ +#define PORT_PDD_PIN_4 0x10U /**< Pin 4 mask */ +#define PORT_PDD_PIN_5 0x20U /**< Pin 5 mask */ +#define PORT_PDD_PIN_6 0x40U /**< Pin 6 mask */ +#define PORT_PDD_PIN_7 0x80U /**< Pin 7 mask */ +#define PORT_PDD_PIN_8 0x100U /**< Pin 8 mask */ +#define PORT_PDD_PIN_9 0x200U /**< Pin 9 mask */ +#define PORT_PDD_PIN_10 0x400U /**< Pin 10 mask */ +#define PORT_PDD_PIN_11 0x800U /**< Pin 11 mask */ +#define PORT_PDD_PIN_12 0x1000U /**< Pin 12 mask */ +#define PORT_PDD_PIN_13 0x2000U /**< Pin 13 mask */ +#define PORT_PDD_PIN_14 0x4000U /**< Pin 14 mask */ +#define PORT_PDD_PIN_15 0x8000U /**< Pin 15 mask */ +#define PORT_PDD_PIN_16 0x10000U /**< Pin 16 mask */ +#define PORT_PDD_PIN_17 0x20000U /**< Pin 17 mask */ +#define PORT_PDD_PIN_18 0x40000U /**< Pin 18 mask */ +#define PORT_PDD_PIN_19 0x80000U /**< Pin 19 mask */ +#define PORT_PDD_PIN_20 0x100000U /**< Pin 20 mask */ +#define PORT_PDD_PIN_21 0x200000U /**< Pin 21 mask */ +#define PORT_PDD_PIN_22 0x400000U /**< Pin 22 mask */ +#define PORT_PDD_PIN_23 0x800000U /**< Pin 23 mask */ +#define PORT_PDD_PIN_24 0x1000000U /**< Pin 24 mask */ +#define PORT_PDD_PIN_25 0x2000000U /**< Pin 25 mask */ +#define PORT_PDD_PIN_26 0x4000000U /**< Pin 26 mask */ +#define PORT_PDD_PIN_27 0x8000000U /**< Pin 27 mask */ +#define PORT_PDD_PIN_28 0x10000000U /**< Pin 28 mask */ +#define PORT_PDD_PIN_29 0x20000000U /**< Pin 29 mask */ +#define PORT_PDD_PIN_30 0x40000000U /**< Pin 30 mask */ +#define PORT_PDD_PIN_31 0x80000000U /**< Pin 31 mask */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* List of pins offering high drive capability */ + #define PORT_PDD_PTB5 0x2U /**< PTB5 mask */ + #define PORT_PDD_PTC1 0x4U /**< PTC1 mask */ + #define PORT_PDD_PTC5 0x8U /**< PTC5 mask */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/* List of pins offering high drive capability */ + #define PORT_PDD_PTB4 0x1U /**< PTB4 mask */ + #define PORT_PDD_PTB5 0x2U /**< PTB5 mask */ + #define PORT_PDD_PTD0 0x4U /**< PTD0 mask */ + #define PORT_PDD_PTD1 0x8U /**< PTD1 mask */ + #define PORT_PDD_PTE0 0x10U /**< PTE0 mask */ + #define PORT_PDD_PTE1 0x20U /**< PTE1 mask */ + #define PORT_PDD_PTH0 0x40U /**< PTH0 mask */ + #define PORT_PDD_PTH1 0x80U /**< PTH1 mask */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/* Filter selection */ +#define PORT_PDD_NO_FILTER 0U /**< No filter */ +#define PORT_PDD_BUSCLK 0U /**< BUSCLK */ +#define PORT_PDD_FLTDIV1 0x1U /**< FLTDIV1 */ +#define PORT_PDD_FLTDIV2 0x2U /**< FLTDIV2 */ +#define PORT_PDD_FLTDIV3 0x3U /**< FLTDIV3 */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + #define PORT_PDD_IIC 0xAU /**< Selects filter for input from IIC */ + #define PORT_PDD_FTM0 0xCU /**< Selects filter for input from FTM0 */ + #define PORT_PDD_PWT 0xEU /**< Selects filter for input from PWT */ + +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_PTD 0x6U /**< Selects filter for input from PTD */ + #define PORT_PDD_PTE 0x8U /**< Selects filter for input from PTE */ + #define PORT_PDD_PTF 0xAU /**< Selects filter for input from PTF */ + #define PORT_PDD_PTG 0xCU /**< Selects filter for input from PTG */ + #define PORT_PDD_PTH 0xEU /**< Selects filter for input from PTH */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_PTD 0x6U /**< Selects filter for input from PTD */ + #define PORT_PDD_PTE 0x8U /**< Selects filter for input from PTE */ + #define PORT_PDD_PTF 0xAU /**< Selects filter for input from PTF */ + #define PORT_PDD_PTG 0xCU /**< Selects filter for input from PTG */ + #define PORT_PDD_PTH 0xEU /**< Selects filter for input from PTH */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + #define PORT_PDD_PTI 0U /**< Selects filter for input from PTI */ + #define PORT_PDD_IRQ 0x4U /**< Selects filter for input from IRQ */ + #define PORT_PDD_FTM0 0x6U /**< Selects filter for input from FTM0 */ + #define PORT_PDD_FTM1 0x8U /**< Selects filter for input from FTM1 */ + #define PORT_PDD_PWT 0xAU /**< Selects filter for input from PWT */ + #define PORT_PDD_I2C0 0xCU /**< Selects filter for input from I2C0 */ + #define PORT_PDD_I2C1 0xEU /**< Selects filter for input from I2C1 */ + +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/* Constants for pull type selection */ +#define PORT_PDD_PULL_DOWN 0U /**< Pull down */ +#define PORT_PDD_PULL_UP 0x1U /**< Pull up */ + +/* Constants for pull enabling/disabling */ +#define PORT_PDD_PULL_DISABLE 0U /**< Pull resistor disabled */ +#define PORT_PDD_PULL_ENABLE 0x2U /**< Pull resistor enabled */ + +/* Constants for slew rate setting */ +#define PORT_PDD_SLEW_RATE_FAST 0U /**< Fast slew rate */ +#define PORT_PDD_SLEW_RATE_SLOW 0x4U /**< Slow slew rate */ + +/* Constants for slew rate setting */ +#define PORT_PDD_PASSIVE_FILTER_DISABLE 0U /**< Passive filter disabled */ +#define PORT_PDD_PASSIVE_FILTER_ENABLE 0x10U /**< Passive filter enabled */ + +/* Constants for open drain setting */ +#define PORT_PDD_OPEN_DRAIN_DISABLE 0U /**< Open drain disabled */ +#define PORT_PDD_OPEN_DRAIN_ENABLE 0x20U /**< Open drain enabled */ + +/* Constants for drive strength setting */ +#define PORT_PDD_DRIVE_STRENGTH_LOW 0U /**< Low drive strength */ +#define PORT_PDD_DRIVE_STRENGTH_HIGH 0x40U /**< High drive strength */ + +/* Constants for mux control setting */ +#define PORT_PDD_MUX_CONTROL_DISABLE 0U /**< Mux control disabled */ +#define PORT_PDD_MUX_CONTROL_ALT1 0x100U /**< Pin used with alternate 1 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT2 0x200U /**< Pin used with alternate 2 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT3 0x300U /**< Pin used with alternate 3 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT4 0x400U /**< Pin used with alternate 4 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT5 0x500U /**< Pin used with alternate 5 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT6 0x600U /**< Pin used with alternate 6 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT7 0x700U /**< Pin used with alternate 7 functionality */ + +/* Constants for pin lock setting */ +#define PORT_PDD_PIN_CONTROL_UNLOCK 0U /**< Pin control unlocked */ +#define PORT_PDD_PIN_CONTROL_LOCK 0x8000U /**< Pin control locked */ + +/* Constants for interrupt configuration setting */ +#define PORT_PDD_INTERRUPT_DMA_DISABLED 0U /**< Interrupt and DMA disabled */ +#define PORT_PDD_DMA_ON_RISING 0x10000U /**< DMA enabled on rising edge */ +#define PORT_PDD_DMA_ON_FALLING 0x20000U /**< DMA enabled on falling edge */ +#define PORT_PDD_DMA_ON_RISING_FALLING 0x30000U /**< DMA enabled on rising and falling edges */ +#define PORT_PDD_INTERRUPT_ON_ZERO 0x80000U /**< Interrupt enabled on low level */ +#define PORT_PDD_INTERRUPT_ON_RISING 0x90000U /**< Interrupt enabled on rising edge */ +#define PORT_PDD_INTERRUPT_ON_FALLING 0xA0000U /**< Interrupt enabled on falling edge */ +#define PORT_PDD_INTERRUPT_ON_RISING_FALLING 0xB0000U /**< Interrupt enabled on rising and falling edges */ +#define PORT_PDD_INTERRUPT_ON_ONE 0xC0000U /**< Interrupt enabled on high level */ + +/* Constants for digital clock source setting */ +#define PORT_PDD_BUS_CLOCK 0U /**< Bus clock as filter clock source */ +#define PORT_PDD_LPO_CLOCK 0x1U /**< LPO clock as filter clock source */ + +/* Constants for Filter Division Set 1 */ +#define PORT_PDD_BUSCLK_DIV_2 0U /**< BUSCLK/2 */ +#define PORT_PDD_BUSCLK_DIV_4 0x1000000U /**< BUSCLK/4 */ +#define PORT_PDD_BUSCLK_DIV_8 0x2000000U /**< BUSCLK/8 */ +#define PORT_PDD_BUSCLK_DIV_16 0x3000000U /**< BUSCLK/16 */ + +/* Constants for Filter Division Set 2 */ +#define PORT_PDD_BUSCLK_DIV_32 0U /**< BUSCLK/32 */ +#define PORT_PDD_BUSCLK_DIV_64 0x4000000U /**< BUSCLK/64 */ +#define PORT_PDD_BUSCLK_DIV_128 0x8000000U /**< BUSCLK/128 */ +#define PORT_PDD_BUSCLK_DIV_256 0xC000000U /**< BUSCLK/256 */ +#define PORT_PDD_BUSCLK_DIV_512 0x10000000U /**< BUSCLK/512 */ +#define PORT_PDD_BUSCLK_DIV_1024 0x14000000U /**< BUSCLK/1024 */ +#define PORT_PDD_BUSCLK_DIV_2048 0x18000000U /**< BUSCLK/2048 */ +#define PORT_PDD_BUSCLK_DIV_4096 0x1C000000U /**< BUSCLK/4096 */ + +/* Constants for Filter Division Set 3 */ +#define PORT_PDD_LPOCLK 0U /**< LPOCLK */ +#define PORT_PDD_LPOCLK_DIV_2 0x20000000U /**< LPOCLK/2 */ +#define PORT_PDD_LPOCLK_DIV_4 0x40000000U /**< LPOCLK/4 */ +#define PORT_PDD_LPOCLK_DIV_8 0x60000000U /**< LPOCLK/8 */ +#define PORT_PDD_LPOCLK_DIV_16 0x80000000U /**< LPOCLK/16 */ +#define PORT_PDD_LPOCLK_DIV_32 0xA0000000U /**< LPOCLK/32 */ +#define PORT_PDD_LPOCLK_DIV_64 0xC0000000U /**< LPOCLK/64 */ +#define PORT_PDD_LPOCLK_DIV_128 0xE0000000U /**< LPOCLK/128 */ + + +/* ---------------------------------------------------------------------------- + -- GetPinPullSelect + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets which pull resistor is selected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pull type selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPullSelect(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPullSelect(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPullSelect + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets pull type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param Type Pull type. This parameter is of "Constants for pull type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPullSelect(_BASE_PTR, periphID, + * PORT_PDD_PULL_DOWN); + * @endcode + */ +#define PORT_PDD_SetPinPullSelect(PeripheralBase, PinIndex, Type) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PS_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinPullEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether pull resistor is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pull enabling/disabling" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPullEnable(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPullEnable(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPullEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets pull type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of pull enable. This parameter is of "Constants + * for pull enabling/disabling" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPullEnable(_BASE_PTR, periphID, + * PORT_PDD_PULL_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinPullEnable(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinSlewRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how slew rate is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for slew rate setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinSlewRate(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinSlewRate(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_SRE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinSlewRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets slew rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of slew rate. This parameter is of "Constants + * for slew rate setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinSlewRate(_BASE_PTR, periphID, + * PORT_PDD_SLEW_RATE_FAST); + * @endcode + */ +#define PORT_PDD_SetPinSlewRate(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_SRE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinPassiveFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether passive filter is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for slew rate setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPassiveFilter(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPassiveFilter(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PFE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPassiveFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets passive filter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of passive filter. This parameter is of + * "Constants for slew rate setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPassiveFilter(_BASE_PTR, periphID, + * PORT_PDD_PASSIVE_FILTER_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinPassiveFilter(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PFE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinOpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether open drain is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for open drain setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinOpenDrain(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinOpenDrain(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_ODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinOpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets open drain. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of open drain. This parameter is of "Constants + * for open drain setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinOpenDrain(_BASE_PTR, periphID, + * PORT_PDD_OPEN_DRAIN_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinOpenDrain(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_ODE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinDriverStrength + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how drive strength is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for drive strength setting" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinDriverStrength(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinDriverStrength(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_DSE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinDriveStrength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets drive strength. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of drive strength. This parameter is of + * "Constants for drive strength setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinDriveStrength(_BASE_PTR, periphID, + * PORT_PDD_DRIVE_STRENGTH_LOW); + * @endcode + */ +#define PORT_PDD_SetPinDriveStrength(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_DSE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinMuxControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how mux control is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for mux control setting" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinMuxControl(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinMuxControl(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_MUX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinMuxControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mux control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of Mux control. This parameter is of "Constants + * for mux control setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinMuxControl(_BASE_PTR, periphID, + * PORT_PDD_MUX_CONTROL_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinMuxControl(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_MUX_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinControlLock + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how pin lock is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pin lock setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinControlLock(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinControlLock(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_LK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockPinControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Locks pin control such as settings of pull, slew rate, passive filter, + * open drain, mux control and pin lock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of pin lock. This parameter is of "Constants for + * pin lock setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_LockPinControl(_BASE_PTR, periphID, + * PORT_PDD_PIN_CONTROL_UNLOCK); + * @endcode + */ +#define PORT_PDD_LockPinControl(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_LK_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinInterruptConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how interupt configuration is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for interrupt configuration setting" + * type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_GetPinInterruptConfiguration(_BASE_PTR, periphID); + * @endcode + */ +#define PORT_PDD_GetPinInterruptConfiguration(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_IRQC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinInterruptConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets interrupt configuration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of interrupt configuration. This parameter is of + * "Constants for interrupt configuration setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinInterruptConfiguration(_BASE_PTR, periphID, + * PORT_PDD_INTERRUPT_DMA_DISABLED); + * @endcode + */ +#define PORT_PDD_SetPinInterruptConfiguration(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_IRQC_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinInterruptFlag(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinInterruptFlag(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_ISF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_ISFR, PORTB_ISFR, + * PORTC_ISFR, PORTD_ISFR, PORTE_ISFR, PORTF_ISFR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetInterruptFlags(PeripheralBase) ( \ + PORT_ISFR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPinInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_ClearPinInterruptFlag(_BASE_PTR, periphID); + * @endcode + */ +#define PORT_PDD_ClearPinInterruptFlag(PeripheralBase, PinIndex) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) |= \ + PORT_PCR_ISF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins to clearing theirs interrupt flags. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_ISFR, PORTB_ISFR, + * PORTC_ISFR, PORTD_ISFR, PORTE_ISFR, PORTF_ISFR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_ClearInterruptFlags(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + PORT_ISFR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins of whole port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 0 within the port and the bit 31 corresponds with the pin + * which has index 31 within the port. This parameter is a 32-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCLR, + * PORTA_GPCHR, PORTB_GPCLR, PORTB_GPCHR, PORTC_GPCLR, PORTC_GPCHR, PORTD_GPCLR, + * PORTD_GPCHR, PORTE_GPCLR, PORTE_GPCHR, PORTF_GPCLR, PORTF_GPCHR + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControl(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControl(PeripheralBase, Mask, Value) ( \ + (PORT_GPCLR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)((uint32)((uint32)(Mask) & 0xFFFFU) << PORT_GPCLR_GPWE_SHIFT)) | ( \ + (uint32)(Value)))), \ + (PORT_GPCHR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)((uint32)(Mask) & (uint32)(~(uint32)0xFFFFU))) | ( \ + (uint32)(Value)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControlLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins from low part of port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 0 within the port and the bit 15 corresponds with the pin + * which has index 15 within the port. This parameter is a 16-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCLR, + * PORTB_GPCLR, PORTC_GPCLR, PORTD_GPCLR, PORTE_GPCLR, PORTF_GPCLR (depending on + * the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControlLow(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControlLow(PeripheralBase, Mask, Value) ( \ + PORT_GPCLR_REG(PeripheralBase) = \ + (uint32)((uint32)((uint32)(Mask) << PORT_GPCLR_GPWE_SHIFT) | (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControlHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins from high part of port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 16 within the port and the bit 15 corresponds with the pin + * which has index 31 within the port. This parameter is a 16-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCHR, + * PORTB_GPCHR, PORTC_GPCHR, PORTD_GPCHR, PORTE_GPCHR, PORTF_GPCHR (depending on + * the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControlHigh(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControlHigh(PeripheralBase, Mask, Value) ( \ + PORT_GPCHR_REG(PeripheralBase) = \ + (uint32)((uint32)((uint32)(Mask) << PORT_GPCHR_GPWE_SHIFT) | (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDigitalFilterStatusMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns enable status of digital filter for whole port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_GetEnableDigitalFilterStatusMask(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetEnableDigitalFilterStatusMask(PeripheralBase) ( \ + PORT_DFER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDigitalFilters + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables digital filters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins. Use constants from group "Pin masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_EnableDigitalFilters(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_EnableDigitalFilters(PeripheralBase, Mask) ( \ + PORT_DFER_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDigitalFilters + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables digital filters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins. Use constants from group "Pin masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_DisableDigitalFilters(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_DisableDigitalFilters(PeripheralBase, Mask) ( \ + PORT_DFER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how filter clock source is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for digital clock source setting" type. + * The value is cast to "uint32". + * @remarks The macro accesses the following registers: PORTA_DFCR, PORTB_DFCR, + * PORTC_DFCR, PORTD_DFCR, PORTE_DFCR, PORTF_DFCR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterClockSource(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetFilterClockSource(PeripheralBase) ( \ + (uint32)(PORT_DFCR_REG(PeripheralBase) & PORT_DFCR_CS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of filter clock source. This parameter is of + * "Constants for digital clock source setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFCR, PORTB_DFCR, + * PORTC_DFCR, PORTD_DFCR, PORTE_DFCR, PORTF_DFCR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterClockSource(_BASE_PTR, + * PORT_PDD_BUS_CLOCK); + * @endcode + */ +#define PORT_PDD_SetFilterClockSource(PeripheralBase, State) ( \ + PORT_DFCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_DFCR_REG(PeripheralBase) & (uint32)(~(uint32)PORT_DFCR_CS_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns filter length in clock cycles. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_DFWR, PORTB_DFWR, + * PORTC_DFWR, PORTD_DFWR, PORTE_DFWR, PORTF_DFWR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterLength(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetFilterLength(PeripheralBase) ( \ + PORT_DFWR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter length in clock cycles. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFWR, PORTB_DFWR, + * PORTC_DFWR, PORTD_DFWR, PORTE_DFWR, PORTF_DFWR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterLength(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_SetFilterLength(PeripheralBase, Value) ( \ + PORT_DFWR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 1" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet1(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet1(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV1_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 1" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet1(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet1(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV1_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 1. This parameter is of "Constants for + * Filter Division Set 1" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet1(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_2); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet1(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV1_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 1. This parameter is of "Constants for + * Filter Division Set 1" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet1(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_2); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet1(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV1_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 2" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet2(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet2(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV2_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 2" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet2(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet2(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV2_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 2. This parameter is of "Constants for + * Filter Division Set 2" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet2(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_32); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet2(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV2_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 2. This parameter is of "Constants for + * Filter Division Set 2" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet2(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_32); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet2(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV2_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet3 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 3" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet3(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet3(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV3_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 3" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet3(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet3(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV3_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet3 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 3. This parameter is of "Constants for + * Filter Division Set 3" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet3(_BASE_PTR, PORT_PDD_LPOCLK); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet3(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV3_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 3. This parameter is of "Constants for + * Filter Division Set 3" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet3(_BASE_PTR, PORT_PDD_LPOCLK); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet3(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV3_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter(PeripheralBase, Module) ( \ + (uint8)((uint8)(PORT_IOFLT_REG(PeripheralBase) >> (uint8)(Module)) & (uint8)0x3U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * PORT_PDD_SetFilter(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT0 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * PORT_PDD_WritePortFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilterReg(PeripheralBase, Value) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilterReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilterReg(PeripheralBase) ( \ + PORT_IOFLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePullupLowPortMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Enables/Disables pullup resistors on low port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of low port pins to be disabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of low port pins to be enabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupLowPortMask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupLowPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE0_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables/Disables pullup resistors on low port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of low port pins to be disabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of low port pins to be enabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupLowPortMask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupLowPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUEL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUEL_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WritePullupEnableLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Writes pullup enable low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * low port pins. Bit #0 of the mask controls pullup setting of the low + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 disables + * pullup for associated low port pin, bit value 1 enables pullup for + * associated low port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableLowReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableLowReg(PeripheralBase, Value) ( \ + PORT_PUE0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes pullup enable low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * low port pins. Bit #0 of the mask controls pullup setting of the low + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 disables + * pullup for associated low port pin, bit value 1 enables pullup for + * associated low port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableLowReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableLowReg(PeripheralBase, Value) ( \ + PORT_PUEL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPullupEnableLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Reads pullup enable configuration of the low port pins. Bit #0 of + * return value contains pullup setting of the low port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableLowReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableLowReg(PeripheralBase) ( \ + PORT_PUE0_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads pullup enable configuration of the low port pins. Bit #0 of + * return value contains pullup setting of the low port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableLowReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableLowReg(PeripheralBase) ( \ + PORT_PUEL_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePullupHighPortMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Enables/Disables pullup resistors on high port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupHighPortMask(_BASE_PTR, + * PORT_PDD_PIN_0, PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupHighPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUEH_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUEH_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Enables/Disables pullup resistors on high port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupHighPortMask(_BASE_PTR, + * PORT_PDD_PIN_0, PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupHighPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE1_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- WritePullupEnableHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Writes pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableHighReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableHighReg(PeripheralBase, Value) ( \ + PORT_PUEH_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Writes pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableHighReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableHighReg(PeripheralBase, Value) ( \ + PORT_PUE1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPullupEnableHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Reads pullup enable configuration of the high port pins. Bit #0 of + * return value contains pullup setting of the high port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableHighReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableHighReg(PeripheralBase) ( \ + PORT_PUEH_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Reads pullup enable configuration of the high port pins. Bit #0 of + * return value contains pullup setting of the high port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableHighReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableHighReg(PeripheralBase) ( \ + PORT_PUE1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- EnableHighDriveMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables/Disables high current drive capability on port pins specified + * by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighDriveDisableMask Mask of pins with high drive to be disabled. Use + * constants from group "List of pins offering high drive capability". + * This parameter is 32 bits wide. + * @param HighDriveEnableMask Mask of pins with high drive to be enabled. Use + * constants from group "List of pins offering high drive capability". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_EnableHighDriveMask(_BASE_PTR, PORT_PDD_PTB5, + * PORT_PDD_PTB5); + * @endcode + */ + #define PORT_PDD_EnableHighDriveMask(PeripheralBase, HighDriveDisableMask, HighDriveEnableMask) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_HDRVE_REG(PeripheralBase) & (uint32)(~(uint32)(HighDriveDisableMask)))) | ( \ + (uint32)(HighDriveEnableMask))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/** + * @brief Enables/Disables high current drive capability on port pins specified + * by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighDriveDisableMask Mask of pins with high drive to be disabled. Use + * constants from group "List of pins offering high drive capability". + * This parameter is 32 bits wide. + * @param HighDriveEnableMask Mask of pins with high drive to be enabled. Use + * constants from group "List of pins offering high drive capability". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_EnableHighDriveMask(_BASE_PTR, PORT_PDD_PTB4, + * PORT_PDD_PTB4); + * @endcode + */ + #define PORT_PDD_EnableHighDriveMask(PeripheralBase, HighDriveDisableMask, HighDriveEnableMask) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_HDRVE_REG(PeripheralBase) & (uint32)(~(uint32)(HighDriveDisableMask)))) | ( \ + (uint32)(HighDriveEnableMask))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ + +/* ---------------------------------------------------------------------------- + -- WriteHighDriveEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes high drive enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new high drive enable setting + * for associated pins. Pins supporting high drive capability are defined + * by High drive pin list. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_WriteHighDriveEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WriteHighDriveEnableReg(PeripheralBase, Value) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighDriveEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads high drive enable configuration of the associated pins. Pins + * supporting high drive capability are defined by High drive pin list. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadHighDriveEnableReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadHighDriveEnableReg(PeripheralBase) ( \ + PORT_HDRVE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter 0 configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter0(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter0(PeripheralBase, Module) ( \ + (uint8)(( \ + (uint8)(PORT_IOFLT0_REG(PeripheralBase) >> (uint8)(Module))) & ( \ + (uint8)0x3U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter 1 configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter1(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter1(PeripheralBase, Module) ( \ + (uint8)(( \ + (uint8)(PORT_IOFLT1_REG(PeripheralBase) >> (uint8)(Module))) & ( \ + (uint8)0x3U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter 0 for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * PORT_PDD_SetFilter0(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter0(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter 1 for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * PORT_PDD_SetFilter1(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter1(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilter0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT1 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * PORT_PDD_WritePortFilter0Reg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilter0Reg(PeripheralBase, Value) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilter1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * PORT_PDD_WritePortFilter1Reg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilter1Reg(PeripheralBase, Value) ( \ + PORT_IOFLT1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilter0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilter0Reg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilter0Reg(PeripheralBase) ( \ + PORT_IOFLT0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilter1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilter1Reg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilter1Reg(PeripheralBase) ( \ + PORT_IOFLT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePullupPort2Mask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/Disables pullup resistors on port 2 pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * PORT_PDD_EnablePullupPort2Mask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_EnablePullupPort2Mask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE2_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePort2PullupEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port 2 pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * PORT_PDD_WritePort2PullupEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePort2PullupEnableReg(PeripheralBase, Value) ( \ + PORT_PUE2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPort2PullupEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port 2 pullup enable configuration of the high port pins. Bit #0 + * of return value contains pullup setting of the high port pin #0, bit #31 + * contains setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPort2PullupEnableReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPort2PullupEnableReg(PeripheralBase) ( \ + PORT_PUE2_REG(PeripheralBase) \ + ) +#endif /* #if defined(PORT_PDD_H_) */ + +/* PORT_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h new file mode 100644 index 0000000..b9ab2c0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h @@ -0,0 +1,3576 @@ +/* + PDD layer implementation for peripheral type RTC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(RTC_PDD_H_) +#define RTC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error RTC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* RTC */ && \ + !defined(MCU_MK10D5) /* RTC */ && \ + !defined(MCU_MK10D7) /* RTC */ && \ + !defined(MCU_MK10F12) /* RTC */ && \ + !defined(MCU_MK10DZ10) /* RTC */ && \ + !defined(MCU_MK11D5) /* RTC */ && \ + !defined(MCU_MK11D5WS) /* RTC */ && \ + !defined(MCU_MK12D5) /* RTC */ && \ + !defined(MCU_MK20D10) /* RTC */ && \ + !defined(MCU_MK20D5) /* RTC */ && \ + !defined(MCU_MK20D7) /* RTC */ && \ + !defined(MCU_MK20F12) /* RTC */ && \ + !defined(MCU_MK20DZ10) /* RTC */ && \ + !defined(MCU_MK21D5) /* RTC */ && \ + !defined(MCU_MK21D5WS) /* RTC */ && \ + !defined(MCU_MK21F12) /* RTC */ && \ + !defined(MCU_MK21F12WS) /* RTC */ && \ + !defined(MCU_MK22D5) /* RTC */ && \ + !defined(MCU_MK22F12810) /* RTC */ && \ + !defined(MCU_MK22F12) /* RTC */ && \ + !defined(MCU_MK22F25612) /* RTC */ && \ + !defined(MCU_MK22F51212) /* RTC */ && \ + !defined(MCU_MK24F12) /* RTC */ && \ + !defined(MCU_MK30D10) /* RTC */ && \ + !defined(MCU_MK30D7) /* RTC */ && \ + !defined(MCU_MK30DZ10) /* RTC */ && \ + !defined(MCU_MK40D10) /* RTC */ && \ + !defined(MCU_MK40D7) /* RTC */ && \ + !defined(MCU_MK40DZ10) /* RTC */ && \ + !defined(MCU_MK40X256VMD100) /* RTC */ && \ + !defined(MCU_MK50D10) /* RTC */ && \ + !defined(MCU_MK50D7) /* RTC */ && \ + !defined(MCU_MK50DZ10) /* RTC */ && \ + !defined(MCU_MK51D10) /* RTC */ && \ + !defined(MCU_MK51D7) /* RTC */ && \ + !defined(MCU_MK51DZ10) /* RTC */ && \ + !defined(MCU_MK52D10) /* RTC */ && \ + !defined(MCU_MK52DZ10) /* RTC */ && \ + !defined(MCU_MK53D10) /* RTC */ && \ + !defined(MCU_MK53DZ10) /* RTC */ && \ + !defined(MCU_MK60D10) /* RTC */ && \ + !defined(MCU_MK60F12) /* RTC */ && \ + !defined(MCU_MK60F15) /* RTC */ && \ + !defined(MCU_MK60DZ10) /* RTC */ && \ + !defined(MCU_MK60N512VMD100) /* RTC */ && \ + !defined(MCU_MK61F12) /* RTC */ && \ + !defined(MCU_MK61F15) /* RTC */ && \ + !defined(MCU_MK61F12WS) /* RTC */ && \ + !defined(MCU_MK61F15WS) /* RTC */ && \ + !defined(MCU_MK63F12) /* RTC */ && \ + !defined(MCU_MK63F12WS) /* RTC */ && \ + !defined(MCU_MK64F12) /* RTC */ && \ + !defined(MCU_MK65F18) /* RTC */ && \ + !defined(MCU_MK65F18WS) /* RTC */ && \ + !defined(MCU_MK66F18) /* RTC */ && \ + !defined(MCU_MK70F12) /* RTC */ && \ + !defined(MCU_MK70F15) /* RTC */ && \ + !defined(MCU_MK70F12WS) /* RTC */ && \ + !defined(MCU_MK70F15WS) /* RTC */ && \ + !defined(MCU_MKL03Z4) /* RTC */ && \ + !defined(MCU_MKL04Z4) /* RTC */ && \ + !defined(MCU_MKL05Z4) /* RTC */ && \ + !defined(MCU_MKL14Z4) /* RTC */ && \ + !defined(MCU_MKL15Z4) /* RTC */ && \ + !defined(MCU_MKL16Z4) /* RTC */ && \ + !defined(MCU_MKL24Z4) /* RTC */ && \ + !defined(MCU_MKL25Z4) /* RTC */ && \ + !defined(MCU_MKL26Z4) /* RTC */ && \ + !defined(MCU_MKL34Z4) /* RTC */ && \ + !defined(MCU_MKL36Z4) /* RTC */ && \ + !defined(MCU_MKL46Z4) /* RTC */ && \ + !defined(MCU_MKW01Z4) /* RTC */ && \ + !defined(MCU_MKW21D5) /* RTC */ && \ + !defined(MCU_MKW21D5WS) /* RTC */ && \ + !defined(MCU_MKW22D5) /* RTC */ && \ + !defined(MCU_MKW22D5WS) /* RTC */ && \ + !defined(MCU_MKW24D5) /* RTC */ && \ + !defined(MCU_MKW24D5WS) /* RTC */ && \ + !defined(MCU_PCK20L4) /* RTC */ + // Unsupported MCU is active + #error RTC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/* Interrupt masks */ + #define RTC_PDD_MOF_INT RTC_SR_MOF_MASK /**< Monotonic overflow interrupt mask */ + #define RTC_PDD_TAF_INT RTC_SR_TAF_MASK /**< Alarm interrupt mask */ + #define RTC_PDD_TOF_INT RTC_SR_TOF_MASK /**< Timer overflow interrupt mask */ + #define RTC_PDD_TIF_INT RTC_SR_TIF_MASK /**< Time invalid interrupt mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +/* Interrupt masks */ + #define RTC_PDD_TAF_INT RTC_SR_TAF_MASK /**< Alarm interrupt mask */ + #define RTC_PDD_TOF_INT RTC_SR_TOF_MASK /**< Timer overflow interrupt mask */ + #define RTC_PDD_TIF_INT RTC_SR_TIF_MASK /**< Time invalid interrupt mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +#if (defined(MCU_MK65F18WS)) +/* Tamper interrupt masks */ + #define RTC_PDD_TMF_INT RTC_TDR_TMF_MASK /**< Test mode tamper interrupt mask */ + #define RTC_PDD_FSF_INT RTC_TDR_FSF_MASK /**< Flash security tamper interrupt mask */ + #define RTC_PDD_TTF_INT RTC_TDR_TTF_MASK /**< Temperature tamper interrupt mask */ + #define RTC_PDD_CTF_INT RTC_TDR_CTF_MASK /**< Clock tamper interrupt mask */ + #define RTC_PDD_VTF_INT RTC_TDR_VTF_MASK /**< Volatge tamper interrupt mask */ + +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS)) */ +/* Tamper interrupt masks */ + #define RTC_PDD_TMF_INT RTC_TDR_TMF_MASK /**< Test mode tamper interrupt mask */ + #define RTC_PDD_FSF_INT RTC_TDR_FSF_MASK /**< Flash security tamper interrupt mask */ + #define RTC_PDD_TTF_INT RTC_TDR_TTF_MASK /**< Temperature tamper interrupt mask */ + #define RTC_PDD_CTF_INT RTC_TDR_CTF_MASK /**< Clock tamper interrupt mask */ + #define RTC_PDD_VTF_INT RTC_TDR_VTF_MASK /**< Volatge tamper interrupt mask */ + #define RTC_PDD_DTF_INT RTC_TDR_DTF_MASK /**< DryIce tamper interrupt mask */ + +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS)) */ +/* WakeUpPinState constants */ +#define RTC_PDD_ASSERTED 0x8U /**< Pin is asserted */ +#define RTC_PDD_NOT_ASSERTED 0U /**< Pin is not asserted */ + + +/* ---------------------------------------------------------------------------- + -- ReadTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TSR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimeSecondsReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeSecondsReg(PeripheralBase) ( \ + RTC_TSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time seconds register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TSR. + * @par Example: + * @code + * RTC_PDD_WriteTimeSecondsReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeSecondsReg(PeripheralBase, Value) ( \ + RTC_TSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TPR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimePrescalerReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimePrescalerReg(PeripheralBase) ( \ + RTC_TPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time prescaler register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TPR. + * @par Example: + * @code + * RTC_PDD_WriteTimePrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimePrescalerReg(PeripheralBase, Value) ( \ + RTC_TPR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimeAlarmReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time alarm register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimeAlarmReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeAlarmReg(PeripheralBase) ( \ + RTC_TAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeAlarmReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time alarm register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time alarm register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TAR. + * @par Example: + * @code + * RTC_PDD_WriteTimeAlarmReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeAlarmReg(PeripheralBase, Value) ( \ + RTC_TAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimeCompensationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time compensation register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TCR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadTimeCompensationReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeCompensationReg(PeripheralBase) ( \ + RTC_TCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeCompensationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time compensation register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time compensation register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TCR. + * @par Example: + * @code + * RTC_PDD_WriteTimeCompensationReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeCompensationReg(PeripheralBase, Value) ( \ + RTC_TCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadControlReg(PeripheralBase) ( \ + RTC_CR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteControlReg(PeripheralBase, Value) ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUpdateMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables update mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableUpdateMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableUpdateMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_UM_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_UM_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSupervisorAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables supervisor accesss. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableSupervisorAccess(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableSupervisorAccess(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_SUP_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_SUP_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeupPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wakeup pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableWakeupPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableWakeupPin(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_WPE_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_WPE_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceSwReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces the equivalent of a VBAT POR to the rest of the RTC module, + * except the access control registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_ForceSwReset(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ForceSwReset(PeripheralBase) ( \ + (RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_SWR_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))), \ + (RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_SWR_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRtcInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the RTC interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetRtcInterruptMask(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetRtcInterruptMask(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRtcInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables RTC interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Imterrupt mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_SetRtcInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_SetRtcInterruptMask(PeripheralBase, Mask) ( \ + RTC_IER_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondsInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Seconds interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableSecondsInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableSecondsInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TSIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAlarmInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Alarm interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableAlarmInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableAlarmInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TAIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimeOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Time overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableTimeOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTimeOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TOIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimeInvalidInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Time invalid interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableTimeInvalidInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTimeInvalidInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TIIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSecondsInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Seconds interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableSecondsInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableSecondsInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TSIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAlarmInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Alarm interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableAlarmInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableAlarmInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TAIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTimeOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Time overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableTimeOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTimeOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTimeInvalidInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Time invalid interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableTimeInvalidInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTimeInvalidInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TIIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWakeUpPinState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets wake-up pin state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "WakeUpPinState constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_SetWakeUpPinState(_BASE_PTR, RTC_PDD_ASSERTED); + * @endcode + */ +#define RTC_PDD_SetWakeUpPinState(PeripheralBase, State) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(State) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadStatusReg(PeripheralBase) ( \ + RTC_SR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Status register. Use constants from group + * "Interrupt masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_WriteStatusReg(_BASE_PTR, RTC_PDD_MOF_INT); + * @endcode + */ + #define RTC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Status register. Use constants from group + * "Interrupt masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_WriteStatusReg(_BASE_PTR, RTC_PDD_TAF_INT); + * @endcode + */ + #define RTC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables seconds counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_EnableCounter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableCounter(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_SR_REG(PeripheralBase) = \ + 0U) : ( \ + RTC_SR_REG(PeripheralBase) = \ + 0x10U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableCounterStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns zero if the Time counter is disabled else return non-zero + * value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetEnableCounterStatus(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetEnableCounterStatus(PeripheralBase) ( \ + (uint32)(RTC_SR_REG(PeripheralBase) & RTC_SR_TCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Lock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadLockReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadLockReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Lock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Lock register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_WriteLockReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteLockReg(PeripheralBase, Value) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockStatusReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockStatusReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_SRL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockStatusReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockStatusReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_SRL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- LockControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockControlReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockControlReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_CRL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockControlReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockControlReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_CRL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- LockTimeComensationReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTimeComensationReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTimeComensationReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_TCL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTimeComensationReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTimeComensationReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TCL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWriteAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Write access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadWriteAccessReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadWriteAccessReg(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWriteAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Write access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Write access register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_WriteWriteAccessReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteWriteAccessReg(PeripheralBase, Value) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptEnableRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_IERW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_IERW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableLockRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_LRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_LRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableStatusRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_SRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_SRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableControlRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_CRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_CRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeCompensationRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TCRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TCRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeAlarmRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TARW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TARW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimePrescalerRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TPRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TPRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeSecondsRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TSRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TSRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadReadAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Read access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadReadAccessReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadReadAccessReg(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteReadAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Read access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Read access register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_WriteReadAccessReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteReadAccessReg(PeripheralBase, Value) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptEnableRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_IERR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_IERR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableLockRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_LRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_LRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableStatusRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_SRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_SRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableControlRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_CRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_CRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeCompensationRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TCRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TCRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeAlarmRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TARR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TARR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimePrescalerRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TPRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TPRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeSecondsRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TSRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TSRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableMonotonicOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Monotonic counter overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableMonotonicOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableMonotonicOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_MOIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Monotonic counter overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableMonotonicOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_MOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockMonotonicCounterHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MCHL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MCHL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockMonotonicCounterLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MCLL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MCLL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicEnableReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MEL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicEnableReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MEL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockTamperTimeSecondsReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_TTSL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TTSL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTamperTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTSR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_TTSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTamperTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper time in seconds. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTSR. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetTamperTime(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetTamperTime(PeripheralBase) ( \ + RTC_TTSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadMonotonicEnableReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicEnableReg(PeripheralBase) ( \ + RTC_MER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic enable register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicEnableReg(PeripheralBase, Value) ( \ + RTC_MER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMonotonicCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Monotonis counter counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * RTC_PDD_EnableMonotonicCounter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableMonotonicCounter(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_MER_REG(PeripheralBase) = \ + 0U) : ( \ + RTC_MER_REG(PeripheralBase) = \ + 0x10U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMonotonicCounterEnableStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns zero if the Monotonic counter is disabled else return non-zero + * value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_GetMonotonicCounterEnableStatus(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetMonotonicCounterEnableStatus(PeripheralBase) ( \ + (uint32)(RTC_MER_REG(PeripheralBase) & RTC_MER_MCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MCHR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_MCHR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicCounterHigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic counter high register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MCHR. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicCounterHigReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicCounterHigReg(PeripheralBase, Value) ( \ + RTC_MCHR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MCLR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_MCLR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicCounterLowgReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic counter low register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MCLR. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicCounterLowgReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicCounterLowgReg(PeripheralBase, Value) ( \ + RTC_MCLR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterHighRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MCHW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MCHW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterLowRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MCLW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MCLW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicEnableRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MERW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MERW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTamperTimeSecondsRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TTSW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TTSW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterHighRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MCHR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MCHR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterLowRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MCLR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MCLR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicEnableRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MERR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MERR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTamperTimeSecondsRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TTSR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TTSR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockTamperInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperInterruptReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperInterruptReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TIL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTrimReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperTrimReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperDetectReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperDetectReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TDL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperEnableReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRtcTamperInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the RTC tamper interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_GetRtcTamperInterruptMask(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetRtcTamperInterruptMask(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRtcTamperInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables RTC tamper interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Imterrupt mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_SetRtcTamperInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_SetRtcTamperInterruptMask(PeripheralBase, Mask) ( \ + RTC_TIR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTestModeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Test mode interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableTestModeInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTestModeInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_TMIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashSecurityInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Flash security interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableFlashSecurityInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableFlashSecurityInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_FSIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTemperatureTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Temperature tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableTemperatureTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTemperatureTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_TTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableClockTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Clock tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableClockTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableClockTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_CTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVolatgeTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Voltage tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableVolatgeTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableVolatgeTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_VTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDryIceTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DryIce tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableDryIceTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableDryIceTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_DTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTestModeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Test mode interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableTestModeInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTestModeInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_TMIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashSecurityInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Flash security interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableFlashSecurityInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableFlashSecurityInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_FSIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTemperatureTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Temperature tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableTemperatureTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTemperatureTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_TTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableClockTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Clock tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableClockTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableClockTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_CTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableVolatgeTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Voltage tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableVolatgeTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableVolatgeTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_VTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDryIceTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DryIce tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableDryIceTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableDryIceTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_DTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper detect register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TDR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTamperDetectReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperDetectReg(PeripheralBase) ( \ + RTC_TDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Tamper detect register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Tamper detect register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TDR. + * @par Example: + * @code + * RTC_PDD_WriteTamperDetectReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTamperDetectReg(PeripheralBase, Value) ( \ + RTC_TDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperInterruptRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperInterruptRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperInterruptRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TIRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperTrimRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTrimRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperTrimRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TTRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperDetectRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperDetectRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperDetectRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TDRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperEnableRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperEnableRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TERW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTamperTrimReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperTrimReg(PeripheralBase) ( \ + RTC_TTR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Tamper trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Tamper trim register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TTR. + * @par Example: + * @code + * RTC_PDD_WriteTamperTrimReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTamperTrimReg(PeripheralBase, Value) ( \ + RTC_TTR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperInterruptRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperInterruptRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperInterruptRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TIRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperTrimRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTrimRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperTrimRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TTRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperDetectRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperDetectRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperDetectRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TDRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperEnableRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperEnableRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TERR_MASK) \ + ) +#endif /* #if defined(RTC_PDD_H_) */ + +/* RTC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h new file mode 100644 index 0000000..7b65a78 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h @@ -0,0 +1,4409 @@ +/* + PDD layer implementation for peripheral type I2S + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SAI_PDD_H_) +#define SAI_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error I2S PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* I2S0 */ && \ + !defined(MCU_MK10D5) /* I2S0 */ && \ + !defined(MCU_MK10D7) /* I2S0 */ && \ + !defined(MCU_MK10F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK11D5) /* I2S0 */ && \ + !defined(MCU_MK11D5WS) /* I2S0 */ && \ + !defined(MCU_MK12D5) /* I2S0 */ && \ + !defined(MCU_MK20D10) /* I2S0 */ && \ + !defined(MCU_MK20D5) /* I2S0 */ && \ + !defined(MCU_MK20D7) /* I2S0 */ && \ + !defined(MCU_MK20F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK21D5) /* I2S0 */ && \ + !defined(MCU_MK21D5WS) /* I2S0 */ && \ + !defined(MCU_MK21F12) /* I2S0 */ && \ + !defined(MCU_MK21F12WS) /* I2S0 */ && \ + !defined(MCU_MK22D5) /* I2S0 */ && \ + !defined(MCU_MK22F12810) /* I2S0 */ && \ + !defined(MCU_MK22F12) /* I2S0 */ && \ + !defined(MCU_MK22F25612) /* I2S0 */ && \ + !defined(MCU_MK22F51212) /* I2S0 */ && \ + !defined(MCU_MK24F12) /* I2S0 */ && \ + !defined(MCU_MK30D10) /* I2S0 */ && \ + !defined(MCU_MK30D7) /* I2S0 */ && \ + !defined(MCU_MK40D10) /* I2S0 */ && \ + !defined(MCU_MK40D7) /* I2S0 */ && \ + !defined(MCU_MK50D10) /* I2S0 */ && \ + !defined(MCU_MK50D7) /* I2S0 */ && \ + !defined(MCU_MK51D10) /* I2S0 */ && \ + !defined(MCU_MK51D7) /* I2S0 */ && \ + !defined(MCU_MK52D10) /* I2S0 */ && \ + !defined(MCU_MK53D10) /* I2S0 */ && \ + !defined(MCU_MK60D10) /* I2S0 */ && \ + !defined(MCU_MK60F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK60F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F12WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F15WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK63F12) /* I2S0 */ && \ + !defined(MCU_MK63F12WS) /* I2S0 */ && \ + !defined(MCU_MK64F12) /* I2S0 */ && \ + !defined(MCU_MK65F18) /* I2S0 */ && \ + !defined(MCU_MK65F18WS) /* I2S0 */ && \ + !defined(MCU_MK66F18) /* I2S0 */ && \ + !defined(MCU_MK70F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F12WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F15WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MKL16Z4) /* I2S0 */ && \ + !defined(MCU_MKL26Z4) /* I2S0 */ && \ + !defined(MCU_MKL36Z4) /* I2S0 */ && \ + !defined(MCU_MKL46Z4) /* I2S0 */ && \ + !defined(MCU_MKW01Z4) /* I2S0 */ && \ + !defined(MCU_MKW21D5) /* I2S0 */ && \ + !defined(MCU_MKW21D5WS) /* I2S0 */ && \ + !defined(MCU_MKW22D5) /* I2S0 */ && \ + !defined(MCU_MKW22D5WS) /* I2S0 */ && \ + !defined(MCU_MKW24D5) /* I2S0 */ && \ + !defined(MCU_MKW24D5WS) /* I2S0 */ && \ + !defined(MCU_PCK20L4) /* I2S0 */ + // Unsupported MCU is active + #error I2S PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter/receiver status flags constants. */ + #define I2S_PDD_WORD_START_FLAG I2S_TCSR_WSF_MASK /**< Word start flag. */ + #define I2S_PDD_SYNC_ERROR_FLAG I2S_TCSR_SEF_MASK /**< Sync error flag. */ + #define I2S_PDD_FIFO_ERROR_FLAG I2S_TCSR_FEF_MASK /**< FIFO error flag. */ + #define I2S_PDD_FIFO_WARNING_FLAG I2S_TCSR_FWF_MASK /**< FIFO warning flag. */ + #define I2S_PDD_ALL_INT_FLAG 0x1C0000U /**< All interrupt flags. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter/receiver status flags constants. */ + #define I2S_PDD_WORD_START_FLAG I2S_TCSR_WSF_MASK /**< Word start flag. */ + #define I2S_PDD_SYNC_ERROR_FLAG I2S_TCSR_SEF_MASK /**< Sync error flag. */ + #define I2S_PDD_FIFO_ERROR_FLAG I2S_TCSR_FEF_MASK /**< FIFO error flag. */ + #define I2S_PDD_FIFO_WARNING_FLAG I2S_TCSR_FWF_MASK /**< FIFO warning flag. */ + #define I2S_PDD_FIFO_REQUEST_FLAG I2S_TCSR_FRF_MASK /**< FIFO request flag. */ + #define I2S_PDD_ALL_INT_FLAG 0x1C0000U /**< All interrupt flags. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter/receiver interrupt enable/disable constants (for + EnableTxInterrupt, DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros). */ + #define I2S_PDD_WORD_START_INT I2S_TCSR_WSIE_MASK /**< Word start interrupt mask. */ + #define I2S_PDD_SYNC_ERROR_INT I2S_TCSR_SEIE_MASK /**< Sync error interrupt mask. */ + #define I2S_PDD_FIFO_ERROR_INT I2S_TCSR_FEIE_MASK /**< FIFO error interrupt mask. */ + #define I2S_PDD_FIFO_WARNING_INT I2S_TCSR_FWIE_MASK /**< FIFO warning interrupt mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter/receiver interrupt enable/disable constants (for + EnableTxInterrupt, DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros). */ + #define I2S_PDD_WORD_START_INT I2S_TCSR_WSIE_MASK /**< Word start interrupt mask. */ + #define I2S_PDD_SYNC_ERROR_INT I2S_TCSR_SEIE_MASK /**< Sync error interrupt mask. */ + #define I2S_PDD_FIFO_ERROR_INT I2S_TCSR_FEIE_MASK /**< FIFO error interrupt mask. */ + #define I2S_PDD_FIFO_WARNING_INT I2S_TCSR_FWIE_MASK /**< FIFO warning interrupt mask. */ + #define I2S_PDD_FIFO_REQUEST_INT I2S_TCSR_FRIE_MASK /**< FIFO request interrupt mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter watermark constants (for SetTxFifoWatermark macro). */ +#define I2S_PDD_TX_WATERMARK_VALUE_0 0U /**< Transmitter FIFO watermark 0 */ +#define I2S_PDD_TX_WATERMARK_VALUE_1 0x1U /**< Transmitter FIFO watermark 1 */ +#define I2S_PDD_TX_WATERMARK_VALUE_2 0x2U /**< Transmitter FIFO watermark 2 */ +#define I2S_PDD_TX_WATERMARK_VALUE_3 0x3U /**< Transmitter FIFO watermark 3 */ +#define I2S_PDD_TX_WATERMARK_VALUE_4 0x4U /**< Transmitter FIFO watermark 4 */ +#define I2S_PDD_TX_WATERMARK_VALUE_5 0x5U /**< Transmitter FIFO watermark 5 */ +#define I2S_PDD_TX_WATERMARK_VALUE_6 0x6U /**< Transmitter FIFO watermark 6 */ +#define I2S_PDD_TX_WATERMARK_VALUE_7 0x7U /**< Transmitter FIFO watermark 7 */ + +/* Clocking transmitter mode constants (for SetTxSynchronousMode macro). */ +#define I2S_PDD_TX_ASYNCHRONOUS_MODE 0U /**< Asynchronous mode. */ +#define I2S_PDD_TX_SYNC_WITH_RECEIVER 0x1U /**< Synchronous with receiver. */ +#define I2S_PDD_TX_SYNC_WITH_ANOTHER_TRANSMITTER 0x2U /**< Synchronous with another SAI transmitter. */ +#define I2S_PDD_TX_SYNC_WITH_ANOTHER_RECEIVER 0x3U /**< Synchronous with another SAI receiver. */ + +#if (defined(MCU_MKW01Z4)) +/* Clocking transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + macro). */ + #define I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE 0U /**< Asynchronous mode (external bit clock) or Bus Clock selected (internal bit clock). */ + #define I2S_PDD_TX_SYNC_MODE_EXTERNAL_OR_SAI_MCLK_CLK_SOURCE 0x1U /**< Synchronous with another SAI transmitter (external bit clock) or Master Clock selected (internal bit clock). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clocking transmitter mode constants (for SetTxBitClockSource, + SetRxBitClockSource macro). */ + #define I2S_PDD_BUS_CLOCK_SOURCE 0U /**< Bus clock selected. */ + #define I2S_PDD_MASTER_CLOCK_1_SOURCE 0x1U /**< Mclk output 1 source */ + #define I2S_PDD_MASTER_CLOCK_2_SOURCE 0x2U /**< Mclk output 2 source */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter or receiver word flag configuration constants. */ + #define I2S_PDD_WORD_FLAG_1 0U /**< Word flag is set on 1st word. */ + #define I2S_PDD_WORD_FLAG_2 0x1U /**< Word flag is set on 2nd word. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver word flag configuration constants. */ + #define I2S_PDD_WORD_FLAG_1 0U /**< Word flag is set on 1st word. */ + #define I2S_PDD_WORD_FLAG_2 0x1U /**< Word flag is set on 2nd word. */ + #define I2S_PDD_WORD_FLAG_3 0x2U /**< Word flag is set on 3rd word. */ + #define I2S_PDD_WORD_FLAG_4 0x3U /**< Word flag is set on 4th word. */ + #define I2S_PDD_WORD_FLAG_5 0x4U /**< Word flag is set on 5th word. */ + #define I2S_PDD_WORD_FLAG_6 0x5U /**< Word flag is set on 6th word. */ + #define I2S_PDD_WORD_FLAG_7 0x6U /**< Word flag is set on 7th word. */ + #define I2S_PDD_WORD_FLAG_8 0x7U /**< Word flag is set on 8th word. */ + #define I2S_PDD_WORD_FLAG_9 0x8U /**< Word flag is set on 9th word. */ + #define I2S_PDD_WORD_FLAG_10 0x9U /**< Word flag is set on 10th word. */ + #define I2S_PDD_WORD_FLAG_11 0xAU /**< Word flag is set on 11th word. */ + #define I2S_PDD_WORD_FLAG_12 0xBU /**< Word flag is set on 12th word. */ + #define I2S_PDD_WORD_FLAG_13 0xCU /**< Word flag is set on 13th word. */ + #define I2S_PDD_WORD_FLAG_14 0xDU /**< Word flag is set on 14th word. */ + #define I2S_PDD_WORD_FLAG_15 0xEU /**< Word flag is set on 15th word. */ + #define I2S_PDD_WORD_FLAG_16 0xFU /**< Word flag is set on 16th word. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter or receiver frame size constants. */ + #define I2S_PDD_FRAME_SIZE_1 0U /**< 1 word per frame. */ + #define I2S_PDD_FRAME_SIZE_2 0x1U /**< 2 words per frame. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver frame size constants. */ + #define I2S_PDD_FRAME_SIZE_1 0U /**< 1 word per frame. */ + #define I2S_PDD_FRAME_SIZE_2 0x1U /**< 2 words per frame. */ + #define I2S_PDD_FRAME_SIZE_3 0x2U /**< 3 words per frame. */ + #define I2S_PDD_FRAME_SIZE_4 0x3U /**< 4 words per frame. */ + #define I2S_PDD_FRAME_SIZE_5 0x4U /**< 5 words per frame. */ + #define I2S_PDD_FRAME_SIZE_6 0x5U /**< 6 words per frame. */ + #define I2S_PDD_FRAME_SIZE_7 0x6U /**< 7 words per frame. */ + #define I2S_PDD_FRAME_SIZE_8 0x7U /**< 8 words per frame. */ + #define I2S_PDD_FRAME_SIZE_9 0x8U /**< 9 words per frame. */ + #define I2S_PDD_FRAME_SIZE_10 0x9U /**< 10 words per frame. */ + #define I2S_PDD_FRAME_SIZE_11 0xAU /**< 11 words per frame. */ + #define I2S_PDD_FRAME_SIZE_12 0xBU /**< 12 words per frame. */ + #define I2S_PDD_FRAME_SIZE_13 0xCU /**< 13 words per frame. */ + #define I2S_PDD_FRAME_SIZE_14 0xDU /**< 14 words per frame. */ + #define I2S_PDD_FRAME_SIZE_15 0xEU /**< 15 words per frame. */ + #define I2S_PDD_FRAME_SIZE_16 0xFU /**< 16 words per frame. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver sync width constants. */ +#define I2S_PDD_SYNC_WIDTH_1 0U /**< 1 bit clock. */ +#define I2S_PDD_SYNC_WIDTH_2 0x1U /**< 2 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_3 0x2U /**< 3 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_4 0x3U /**< 4 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_5 0x4U /**< 5 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_6 0x5U /**< 6 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_7 0x6U /**< 7 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_8 0x7U /**< 8 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_9 0x8U /**< 9 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_10 0x9U /**< 10 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_11 0xAU /**< 11 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_12 0xBU /**< 12 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_13 0xCU /**< 13 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_14 0xDU /**< 14 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_15 0xEU /**< 15 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_16 0xFU /**< 16 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_17 0x10U /**< 17 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_18 0x11U /**< 18 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_19 0x12U /**< 19 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_20 0x13U /**< 20 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_21 0x14U /**< 21 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_22 0x15U /**< 22 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_23 0x16U /**< 23 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_24 0x17U /**< 24 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_25 0x18U /**< 25 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_26 0x19U /**< 26 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_27 0x1AU /**< 27 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_28 0x1BU /**< 28 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_29 0x1CU /**< 29 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_30 0x1DU /**< 30 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_31 0x1EU /**< 31 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_32 0x1FU /**< 32 bits clock. */ + +/* Transmitter or receiver word width (in bits) constants. */ +#define I2S_PDD_WORD_WIDTH_1 0U /**< 1 bit. */ +#define I2S_PDD_WORD_WIDTH_2 0x1U /**< 2 bits. */ +#define I2S_PDD_WORD_WIDTH_3 0x2U /**< 3 bits. */ +#define I2S_PDD_WORD_WIDTH_4 0x3U /**< 4 bits. */ +#define I2S_PDD_WORD_WIDTH_5 0x4U /**< 5 bits. */ +#define I2S_PDD_WORD_WIDTH_6 0x5U /**< 6 bits. */ +#define I2S_PDD_WORD_WIDTH_7 0x6U /**< 7 bits. */ +#define I2S_PDD_WORD_WIDTH_8 0x7U /**< 8 bits. */ +#define I2S_PDD_WORD_WIDTH_9 0x8U /**< 9 bits. */ +#define I2S_PDD_WORD_WIDTH_10 0x9U /**< 10 bits. */ +#define I2S_PDD_WORD_WIDTH_11 0xAU /**< 11 bits. */ +#define I2S_PDD_WORD_WIDTH_12 0xBU /**< 12 bits. */ +#define I2S_PDD_WORD_WIDTH_13 0xCU /**< 13 bits. */ +#define I2S_PDD_WORD_WIDTH_14 0xDU /**< 14 bits. */ +#define I2S_PDD_WORD_WIDTH_15 0xEU /**< 15 bits. */ +#define I2S_PDD_WORD_WIDTH_16 0xFU /**< 16 bits. */ +#define I2S_PDD_WORD_WIDTH_17 0x10U /**< 17 bits. */ +#define I2S_PDD_WORD_WIDTH_18 0x11U /**< 18 bits. */ +#define I2S_PDD_WORD_WIDTH_19 0x12U /**< 19 bits. */ +#define I2S_PDD_WORD_WIDTH_20 0x13U /**< 20 bits. */ +#define I2S_PDD_WORD_WIDTH_21 0x14U /**< 21 bits. */ +#define I2S_PDD_WORD_WIDTH_22 0x15U /**< 22 bits. */ +#define I2S_PDD_WORD_WIDTH_23 0x16U /**< 23 bits. */ +#define I2S_PDD_WORD_WIDTH_24 0x17U /**< 24 bits. */ +#define I2S_PDD_WORD_WIDTH_25 0x18U /**< 25 bits. */ +#define I2S_PDD_WORD_WIDTH_26 0x19U /**< 26 bits. */ +#define I2S_PDD_WORD_WIDTH_27 0x1AU /**< 27 bits. */ +#define I2S_PDD_WORD_WIDTH_28 0x1BU /**< 28 bits. */ +#define I2S_PDD_WORD_WIDTH_29 0x1CU /**< 29 bits. */ +#define I2S_PDD_WORD_WIDTH_30 0x1DU /**< 30 bits. */ +#define I2S_PDD_WORD_WIDTH_31 0x1EU /**< 31 bits. */ +#define I2S_PDD_WORD_WIDTH_32 0x1FU /**< 32 bits. */ + +/* Receiver watermark constants (for SetRxFifoWatermark macro). */ +#define I2S_PDD_RX_WATERMARK_VALUE_1 0U /**< Receiver FIFO watermark 1 */ +#define I2S_PDD_RX_WATERMARK_VALUE_2 0x1U /**< Receiver FIFO watermark 2 */ +#define I2S_PDD_RX_WATERMARK_VALUE_3 0x2U /**< Receiver FIFO watermark 3 */ +#define I2S_PDD_RX_WATERMARK_VALUE_4 0x3U /**< Receiver FIFO watermark 4 */ +#define I2S_PDD_RX_WATERMARK_VALUE_5 0x4U /**< Receiver FIFO watermark 5 */ +#define I2S_PDD_RX_WATERMARK_VALUE_6 0x5U /**< Receiver FIFO watermark 6 */ +#define I2S_PDD_RX_WATERMARK_VALUE_7 0x6U /**< Receiver FIFO watermark 7 */ +#define I2S_PDD_RX_WATERMARK_VALUE_8 0x7U /**< Receiver FIFO watermark 8 */ + +/* Clocking transmitter mode constants (for SetRxSynchronousMode macro). */ +#define I2S_PDD_RX_ASYNCHRONOUS_MODE 0U /**< Asynchronous mode. */ +#define I2S_PDD_RX_SYNC_WITH_TRANSMITTER 0x1U /**< Synchronous with receiver. */ +#define I2S_PDD_RX_SYNC_WITH_ANOTHER_RECEIVER 0x2U /**< Synchronous with another SAI transmitter. */ +#define I2S_PDD_RX_SYNC_WITH_ANOTHER_TRANSMITTER 0x3U /**< Synchronous with another SAI transmitter. */ + +/* Divider update status flag constant (for GetDividerUpdateFlag macro). */ +#define I2S_PDD_MCLK_DIVIDER_RATIO_UPDATED I2S_MCR_DUF_MASK /**< MCLK Divider ratio is updating on-the-fly. */ + +/* Transmitter internal logic bit clock input constants (for SetTxBitClockInput + macros). */ +#define I2S_PDD_INTERNAL_BIT_CLOCK 0U /**< No effect. */ +#define I2S_PDD_EXTERNAL_BIT_CLOCK 0x10000000U /**< Internal logic is clocked as if bit clock was externally generated. */ + +/* Transmitter bit clock polarity constants (for SetTxBitClockPolarity, + SetRxBitClockPolarity macros). */ +#define I2S_PDD_BIT_CLOCK_ACTIVE_HIGH 0U /**< Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). */ +#define I2S_PDD_BIT_CLOCK_ACTIVE_LOW 0x2000000U /**< Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). */ + +/* Bit clock direction constants (for SetTxBitClockDirection, + SetRxBitClockDirection macros). */ +#define I2S_PDD_BIT_CLOCK_OUTPUT 0x1000000U /**< Bit clock is generated internally (master mode). */ +#define I2S_PDD_BIT_CLOCK_INPUT 0U /**< Bit clock is generated externally (slave mode). */ + +/* Data channel mask constant constants (for EnableRx/TxDataChannels, + DisableRx/TxDataChannels macros). */ +#define I2S_PDD_DATA_CHANNEL_0 0x1U /**< Data channel 0 mask */ +#define I2S_PDD_DATA_CHANNEL_1 0x2U /**< Data channel 1 mask */ + +/* Bit shift order constants (for SetTxShiftDirection, SetRxShiftDirection + macros). */ +#define I2S_PDD_MSB_FIRST 0U /**< MBS is transmitted/received first. */ +#define I2S_PDD_LSB_FIRST 0x10U /**< LBS is transmitted/received first. */ + +/* Frame sync position in stream constants (for SetTxFrameSyncEarly, + SetRxFrameSyncEarly macros). */ +#define I2S_PDD_FIRST_BIT_OF_DATA 0U /**< Asserts with the first bit of the frame. */ +#define I2S_PDD_ONE_BIT_BEFORE_DATA 0x8U /**< Asserts one bit before the first bit of the frame. */ + +/* Frame sync active polarity constants (for SetTxFrameSyncPolarity, + SetRxFrameSyncPolarity macros). */ +#define I2S_PDD_FRAME_SYNC_ACTIVE_HIGH 0U /**< Active high. */ +#define I2S_PDD_FRAME_SYNC_ACTIVE_LOW 0x2U /**< Active low. */ + +/* Frame sync PIN direction constants (for SetTxFrameSyncDirection, + SetRxFrameSyncDirection macros). */ +#define I2S_PDD_FRAME_SYNC_OUTPUT 0x1U /**< Generated internally (master mode). */ +#define I2S_PDD_FRAME_SYNC_INPUT 0U /**< Generated externally (slave mode). */ + +/* Receiver internal logic bit clock input constants (for SetRxBitClockInput + macros). */ +#define I2S_PDD_INTERNAL_BIT_CLOCK 0U /**< No effect. */ +#define I2S_PDD_EXTERNAL_BIT_CLOCK 0x10000000U /**< Internal logic is clocked as if bit clock was externally generated. */ + +#if (defined(MCU_MK22D5)) +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_PLL_FLL_CLK 0x3000000U /**< MCG PLL/FLL out. */ + #define I2S_PDD_PLL_CLK 0x3000000U /**< MCG PLL out. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_ER_OSC1 0x2000000U /**< ER OSC1 */ + #define I2S_PDD_PLL_CLK 0x3000000U /**< MCG PLL out. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_PLL_FLL_CLK 0x3000000U /**< MCG PLL/FLL out. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTxDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2S_TCSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)I2S_TCSR_TE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) : ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCSR_REG(PeripheralBase) | I2S_TCSR_TE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDeviceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transmitter enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxDeviceState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxDeviceState(PeripheralBase) ( \ + ((uint32)(I2S_TCSR_REG(PeripheralBase) & I2S_TCSR_TE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmitter operation in stop mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in stop mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInStopMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxInStopMode(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_STOPE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_STOPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmitter operation in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in debug mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxInDebugMode(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_DBGE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_DBGE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxBitClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmit bit clock, separately from the + * transmit enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Tx bit clock. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxBitClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxBitClock(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_BCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxBitClockState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transmitter bit clock enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxBitClockState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxBitClockState(PeripheralBase) ( \ + ((uint32)(I2S_TCSR_REG(PeripheralBase) & I2S_TCSR_BCE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- TxFifoReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the transmitter FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_TxFifoReset(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_TxFifoReset(PeripheralBase) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCSR_REG(PeripheralBase) | I2S_TCSR_FR_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the internal transmitter logic including the FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested transmitter reset state. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxSoftwareReset(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxSoftwareReset(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SR_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_SR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetTxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_TCSR_WSF_MASK) | (( \ + I2S_TCSR_SEF_MASK) | (( \ + I2S_TCSR_FEF_MASK) | ( \ + I2S_TCSR_FWF_MASK)))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetTxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_TCSR_WSF_MASK) | (( \ + I2S_TCSR_SEF_MASK) | (( \ + I2S_TCSR_FEF_MASK) | (( \ + I2S_TCSR_FWF_MASK) | ( \ + I2S_TCSR_FRF_MASK))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearTxInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears transmitter interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Transmitter/receiver status flags constants.". This parameter is 32 bits + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_ClearTxInterruptFlags(_BASE_PTR, + * I2S_PDD_WORD_START_FLAG); + * @endcode + */ +#define I2S_PDD_ClearTxInterruptFlags(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_TCSR_WSF_MASK | (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables transmitter interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_EnableTxInterrupt(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_TCSR_WSF_MASK | (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables transmitter interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableTxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_DisableTxInterrupt(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxFifoWarningDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter FIFO warning DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO warning DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxFifoWarningDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxFifoWarningDma(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FWDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_FWDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxFifoRequestDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter FIFO request DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO request DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxFifoRequestDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxFifoRequestDma(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FRDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxControlReg(PeripheralBase) ( \ + I2S_TCSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxControlReg(PeripheralBase, Value) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter FIFO watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmitter FIFO watermark. Use constants from group + * "Transmitter watermark constants (for SetTxFifoWatermark macro).". This parameter + * is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWatermark(_BASE_PTR, + * I2S_PDD_TX_WATERMARK_VALUE_0); + * @endcode + */ +#define I2S_PDD_SetTxFifoWatermark(PeripheralBase, Value) ( \ + I2S_TCR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR1_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR1_TFW_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration1Reg(PeripheralBase) ( \ + I2S_TCR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 1 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration1Reg(PeripheralBase, Value) ( \ + I2S_TCR1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxSynchronousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter asynchronous or synchronous modes of operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Transmit synchronous mode value. Use constants from group + * "Clocking transmitter mode constants (for SetTxSynchronousMode macro).". This + * parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxSynchronousMode(_BASE_PTR, + * I2S_PDD_TX_ASYNCHRONOUS_MODE); + * @endcode + */ +#define I2S_PDD_SetTxSynchronousMode(PeripheralBase, Mode) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_SYNC_MASK))) | ( \ + (uint32)((uint32)(Mode) << I2S_TCR2_SYNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxBitClockSwap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter swap bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of swap bit clock source. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxBitClockSwap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxBitClockSwap(PeripheralBase, State) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCS_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_TCR2_BCS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter internal logic bit clock input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Transmitter internal logic bit clock input value. The user + * should use one from the enumerated values. This parameter is of + * "Transmitter internal logic bit clock input constants (for SetTxBitClockInput + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockInput(_BASE_PTR, + * I2S_PDD_INTERNAL_BIT_CLOCK); + * @endcode + */ +#define I2S_PDD_SetTxBitClockInput(PeripheralBase, Source) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCI_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Transmit bit clock source value. Use constants from group + * "Clocking transmitter mode constants (for SetTxBitClockSource, + * SetRxBitClockSource macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockSource(_BASE_PTR, + * I2S_PDD_BUS_CLOCK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetTxBitClockSource(PeripheralBase, ClkSource) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_MSEL_MASK))) | ( \ + (uint32)((uint32)(ClkSource) << I2S_TCR2_MSEL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter bit clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Transmitter bit clock polarity value. The user should use one + * from the enumerated values. This parameter is of "Transmitter bit + * clock polarity constants (for SetTxBitClockPolarity, SetRxBitClockPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockPolarity(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetTxBitClockPolarity(PeripheralBase, Polarity) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter bit clock PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Transmitter bit clock direction value. The user should use + * one from the enumerated values. This parameter is of "Bit clock + * direction constants (for SetTxBitClockDirection, SetRxBitClockDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockDirection(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetTxBitClockDirection(PeripheralBase, Direction) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter bit clock divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Bit clock divider value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetTxBitClockDivider(PeripheralBase, Value) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_DIV_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration2Reg(PeripheralBase) ( \ + I2S_TCR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 2 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration2Reg(PeripheralBase, Value) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the transmitter data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Transmitter data channel mask value. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_EnableTxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_TCR3_REG(PeripheralBase) |= \ + (uint32)((uint32)(Mask) << I2S_TCR3_TCE_SHIFT) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the transmitter data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Transmitter data channel mask value. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableTxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_DisableTxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_TCR3_REG(PeripheralBase) &= \ + (uint32)(~(uint32)((uint32)(Mask) << I2S_TCR3_TCE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoWordFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 1 bit + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 4 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration3Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration3Reg(PeripheralBase) ( \ + I2S_TCR3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 3 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration3Reg(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetTxSyncWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the length of the frame sync in number of bit clocks. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Sync width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxSyncWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxSyncWidth(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_SYWD_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_SYWD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxShiftDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Specifies whether the LSB or the MSB is transmitted first. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Bit shift order value. The user should use one from the + * enumerated values. This parameter is of "Bit shift order constants (for + * SetTxShiftDirection, SetRxShiftDirection macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxShiftDirection(_BASE_PTR, I2S_PDD_MSB_FIRST); + * @endcode + */ +#define I2S_PDD_SetTxShiftDirection(PeripheralBase, Direction) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_MF_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncEarly + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync position in stream. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SyncEarly Frame sync position in stream value. The user should use one + * from the enumerated values. This parameter is of "Frame sync position + * in stream constants (for SetTxFrameSyncEarly, SetRxFrameSyncEarly + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncEarly(_BASE_PTR, + * I2S_PDD_FIRST_BIT_OF_DATA); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncEarly(PeripheralBase, SyncEarly) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSE_MASK))) | ( \ + (uint32)(SyncEarly))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync active polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Active frame sync polarity value. The user should use one + * from the enumerated values. This parameter is of "Frame sync active + * polarity constants (for SetTxFrameSyncPolarity, SetRxFrameSyncPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncPolarity(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncPolarity(PeripheralBase, Polarity) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Frame sync PIN direction value. The user should use one from + * the enumerated values. This parameter is of "Frame sync PIN direction + * constants (for SetTxFrameSyncDirection, SetRxFrameSyncDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncDirection(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncDirection(PeripheralBase, Direction) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration4Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration4Reg(PeripheralBase) ( \ + I2S_TCR4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 4 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration4Reg(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxWordNWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in each word, for each word except the + * first in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word N width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxWordNWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxWordNWidth(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_WNW_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_WNW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxWord0Width + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in the first word in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word 0 width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxWord0Width(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxWord0Width(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_W0W_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_W0W_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFirstBitShifted + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the bit index for the first bit transmitted for each word + * in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value First bit shifted index [0..31]. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFirstBitShifted(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetTxFirstBitShifted(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_FBT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_FBT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration5Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration5Reg(PeripheralBase) ( \ + I2S_TCR5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 5 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration5Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration5Reg(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxDataChannelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data channel register defined by Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @param Data Value stored to the data channel register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TDR[Index]. + * @par Example: + * @code + * I2S_PDD_WriteTxDataChannelReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define I2S_PDD_WriteTxDataChannelReg(PeripheralBase, Index, Data) ( \ + I2S_TDR_REG(PeripheralBase,(Index)) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDataChannelRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TDR[Index]. + * @par Example: + * @code + * uint32 result = + * I2S_PDD_GetTxDataChannelRegAddress(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxDataChannelRegAddress(PeripheralBase, Index) ( \ + (uint32)&I2S_TDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxChannelWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for transmit data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetTxChannelWriteFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxChannelWriteFifoPointer(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(I2S_TFR_REG(PeripheralBase,(Index)) & I2S_TFR_WFP_MASK)) >> ( \ + I2S_TFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxChannelReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for transmit data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetTxChannelReadFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxChannelReadFifoPointer(PeripheralBase, Index) ( \ + (uint8)(I2S_TFR_REG(PeripheralBase,(Index)) & I2S_TFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Reads transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFR[Index], TFR[] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxFifoReg(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_ReadTxFifoReg(PeripheralBase) ( \ + I2S_TFR_REG(PeripheralBase,0U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Reads transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFR[Index], TFR[] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxFifoReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define I2S_PDD_ReadTxFifoReg(PeripheralBase, Index) ( \ + I2S_TFR_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteTxTimeSlotMaskReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TMR_TWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TMR_TWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteTxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit mask + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit mask register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxMaskReg(PeripheralBase, Value) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2S_RCSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)I2S_RCSR_RE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) : ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCSR_REG(PeripheralBase) | I2S_RCSR_RE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDeviceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns receiver enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxDeviceState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxDeviceState(PeripheralBase) ( \ + ((uint32)(I2S_RCSR_REG(PeripheralBase) & I2S_RCSR_RE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxBitClockState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns receiver bit clock enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxBitClockState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxBitClockState(PeripheralBase) ( \ + ((uint32)(I2S_RCSR_REG(PeripheralBase) & I2S_RCSR_BCE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receiver operation in stop mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in stop mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInStopMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxInStopMode(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_STOPE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_STOPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receiver operation in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in debug mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxInDebugMode(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_DBGE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_DBGE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxBitClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receive bit clock, separately from the receive + * enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Rx bit clock. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxBitClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxBitClock(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_BCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- RxFifoReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the receiver FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_RxFifoReset(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_RxFifoReset(PeripheralBase) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCSR_REG(PeripheralBase) | I2S_RCSR_FR_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the internal receiver logic including the FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested receiver reset state. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxSoftwareReset(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxSoftwareReset(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SR_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_SR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetRxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_RCSR_WSF_MASK) | (( \ + I2S_RCSR_SEF_MASK) | (( \ + I2S_RCSR_FEF_MASK) | ( \ + I2S_RCSR_FWF_MASK)))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetRxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_RCSR_WSF_MASK) | (( \ + I2S_RCSR_SEF_MASK) | (( \ + I2S_RCSR_FEF_MASK) | (( \ + I2S_RCSR_FWF_MASK) | ( \ + I2S_RCSR_FRF_MASK))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearRxInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears receiver interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Transmitter/receiver status flags constants.". This parameter is 32 bits + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_ClearRxInterruptFlags(_BASE_PTR, + * I2S_PDD_WORD_START_FLAG); + * @endcode + */ +#define I2S_PDD_ClearRxInterruptFlags(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_RCSR_WSF_MASK | (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables receiver interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_EnableRxInterrupt(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_RCSR_WSF_MASK | (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables receiver interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableRxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_DisableRxInterrupt(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoWarningDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver FIFO warning DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO warning DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxFifoWarningDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxFifoWarningDma(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FWDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_FWDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoRequestDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver FIFO request DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO request DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxFifoRequestDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxFifoRequestDma(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FRDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxControlReg(PeripheralBase) ( \ + I2S_RCSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxControlReg(PeripheralBase, Value) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver FIFO watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receiver FIFO watermark. Use constants from group "Receiver + * watermark constants (for SetRxFifoWatermark macro).". This parameter is 3 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWatermark(_BASE_PTR, + * I2S_PDD_RX_WATERMARK_VALUE_1); + * @endcode + */ +#define I2S_PDD_SetRxFifoWatermark(PeripheralBase, Value) ( \ + I2S_RCR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR1_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR1_RFW_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration1Reg(PeripheralBase) ( \ + I2S_RCR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 1 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration1Reg(PeripheralBase, Value) ( \ + I2S_RCR1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxSynchronousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver asynchronous or synchronous modes of operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Receive synchronous mode value. Use constants from group + * "Clocking transmitter mode constants (for SetRxSynchronousMode macro).". This + * parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxSynchronousMode(_BASE_PTR, + * I2S_PDD_RX_ASYNCHRONOUS_MODE); + * @endcode + */ +#define I2S_PDD_SetRxSynchronousMode(PeripheralBase, Mode) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_SYNC_MASK))) | ( \ + (uint32)((uint32)(Mode) << I2S_RCR2_SYNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxBitClockSwap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver swap bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of swap bit clock source. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxBitClockSwap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxBitClockSwap(PeripheralBase, State) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCS_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_RCR2_BCS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver internal logic bit clock input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Receiver internal logic bit clock input value. The user should + * use one from the enumerated values. This parameter is of "Receiver + * internal logic bit clock input constants (for SetRxBitClockInput macros)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockInput(_BASE_PTR, + * I2S_PDD_INTERNAL_BIT_CLOCK); + * @endcode + */ +#define I2S_PDD_SetRxBitClockInput(PeripheralBase, Source) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCI_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Receive bit clock source value. Use constants from group + * "Clocking transmitter mode constants (for SetTxBitClockSource, + * SetRxBitClockSource macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockSource(_BASE_PTR, + * I2S_PDD_BUS_CLOCK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetRxBitClockSource(PeripheralBase, ClkSource) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_MSEL_MASK))) | ( \ + (uint32)((uint32)(ClkSource) << I2S_RCR2_MSEL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver bit clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Receiver bit clock polarity value. The user should use one + * from the enumerated values. This parameter is of "Transmitter bit clock + * polarity constants (for SetTxBitClockPolarity, SetRxBitClockPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockPolarity(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetRxBitClockPolarity(PeripheralBase, Polarity) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver bit clock PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Receiver bit clock direction value. The user should use one + * from the enumerated values. This parameter is of "Bit clock direction + * constants (for SetTxBitClockDirection, SetRxBitClockDirection macros)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockDirection(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetRxBitClockDirection(PeripheralBase, Direction) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver bit clock divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Bit clock divider value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetRxBitClockDivider(PeripheralBase, Value) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_DIV_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration2Reg(PeripheralBase) ( \ + I2S_RCR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 2 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration2Reg(PeripheralBase, Value) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the receiver data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Receiver data channel mask value. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_EnableRxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_RCR3_REG(PeripheralBase) |= \ + (uint32)((uint32)(Mask) << I2S_RCR3_RCE_SHIFT) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the receiver data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Receiver data channel mask value. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableRxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_DisableRxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_RCR3_REG(PeripheralBase) &= \ + (uint32)(~(uint32)((uint32)(Mask) << I2S_RCR3_RCE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoWordFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 1 bit + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 4 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration3Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration3Reg(PeripheralBase) ( \ + I2S_RCR3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 3 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration3Reg(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetRxSyncWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the length of the frame sync in number of bit clocks. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Sync width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxSyncWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxSyncWidth(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_SYWD_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_SYWD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxShiftDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Specifies whether the LSB or the MSB is received first. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Bit shift order value. The user should use one from the + * enumerated values. This parameter is of "Bit shift order constants (for + * SetTxShiftDirection, SetRxShiftDirection macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxShiftDirection(_BASE_PTR, I2S_PDD_MSB_FIRST); + * @endcode + */ +#define I2S_PDD_SetRxShiftDirection(PeripheralBase, Direction) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_MF_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncEarly + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync position in stream. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SyncEarly Frame sync position in stream value. The user should use one + * from the enumerated values. This parameter is of "Frame sync position + * in stream constants (for SetTxFrameSyncEarly, SetRxFrameSyncEarly + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncEarly(_BASE_PTR, + * I2S_PDD_FIRST_BIT_OF_DATA); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncEarly(PeripheralBase, SyncEarly) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSE_MASK))) | ( \ + (uint32)(SyncEarly))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync active polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Active frame sync polarity value. The user should use one + * from the enumerated values. This parameter is of "Frame sync active + * polarity constants (for SetTxFrameSyncPolarity, SetRxFrameSyncPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncPolarity(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncPolarity(PeripheralBase, Polarity) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Frame sync PIN direction value. The user should use one from + * the enumerated values. This parameter is of "Frame sync PIN direction + * constants (for SetTxFrameSyncDirection, SetRxFrameSyncDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncDirection(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncDirection(PeripheralBase, Direction) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration4Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration4Reg(PeripheralBase) ( \ + I2S_RCR4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 4 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration4Reg(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxWordNWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in each word, for each word except the + * first in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word N width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxWordNWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxWordNWidth(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_WNW_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_WNW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxWord0Width + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in the first word in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word 0 width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxWord0Width(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxWord0Width(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_W0W_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_W0W_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFirstBitShifted + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the bit index for the first bit received for each word in + * the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value First bit shifted index [0..31]. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFirstBitShifted(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetRxFirstBitShifted(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_FBT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_FBT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration5Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration5Reg(PeripheralBase) ( \ + I2S_RCR5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 5 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration5Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration5Reg(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxDataChannelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[Index]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxDataChannelReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define I2S_PDD_ReadRxDataChannelReg(PeripheralBase, Index) ( \ + I2S_RDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataChannelRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[Index]. + * @par Example: + * @code + * uint32 result = + * I2S_PDD_GetRxDataChannelRegAddress(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxDataChannelRegAddress(PeripheralBase, Index) ( \ + (uint32)&I2S_RDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxChannelWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for receive data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetRxChannelWriteFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxChannelWriteFifoPointer(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(I2S_RFR_REG(PeripheralBase,(Index)) & I2S_RFR_WFP_MASK)) >> ( \ + I2S_RFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxChannelReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for receive data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetRxChannelReadFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxChannelReadFifoPointer(PeripheralBase, Index) ( \ + (uint8)(I2S_RFR_REG(PeripheralBase,(Index)) & I2S_RFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxChannelFifoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxChannelFifoReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define I2S_PDD_ReadRxChannelFifoReg(PeripheralBase, Index) ( \ + I2S_RFR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxTimeSlotMaskReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RMR_RWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RMR_RWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxMaskReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxMaskReg(PeripheralBase) ( \ + I2S_RMR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive mask + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive mask register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxMaskReg(PeripheralBase, Value) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDividerUpdateFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns divider update status flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Divider update status flag constant (for + * GetDividerUpdateFlag macro)." for processing return value. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetDividerUpdateFlag(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetDividerUpdateFlag(PeripheralBase) ( \ + I2S_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMclkDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the MCLK divider and configures the SAI_MCLK pin as + * an output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master clock divider. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableMclkDivider(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableMclkDivider(PeripheralBase, State) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MCR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MCR_MOE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_MCR_MOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMclkDividerState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns Mclk divider enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetMclkDividerState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetMclkDividerState(PeripheralBase) ( \ + ((uint32)(I2S_MCR_REG(PeripheralBase) & I2S_MCR_MOE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock input to the MCLK Divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source value. The user should use one from the enumerated + * values. This parameter is of "Mclk clock input constants (for + * SetMclkClockSource macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkClockSource(_BASE_PTR, I2S_PDD_SYSTEM_CLK); + * @endcode + */ +#define I2S_PDD_SetMclkClockSource(PeripheralBase, Source) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MCR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MCR_MICS_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMclkControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads master clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadMclkControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadMclkControlReg(PeripheralBase) ( \ + I2S_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into master clock + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the master clock control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkControlReg(PeripheralBase, Value) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkFraction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Mclk fraction factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Fraction value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkFraction(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetMclkFraction(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MDR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MDR_FRACT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_MDR_FRACT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Mclk divider factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Divider value[0..4095]. This parameter is a 12-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetMclkDivider(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MDR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MDR_DIVIDE_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkDivideRatioReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the Mclk divide ratio register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the Mclk divide ration register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkDivideRatioReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkDivideRatioReg(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMclkDivideReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads master clock divide register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadMclkDivideReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadMclkDivideReg(PeripheralBase) ( \ + I2S_MDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkDivideReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into master clock + * divide register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the master clock divide register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkDivideReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkDivideReg(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxDataChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter data channel. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3. + * @par Example: + * @code + * I2S_PDD_EnableTxDataChannel(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxDataChannel(PeripheralBase, State) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_TCE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_TCR3_TCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value stored to the data register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TDR[]. + * @par Example: + * @code + * I2S_PDD_WriteTxDataReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxDataReg(PeripheralBase, Data) ( \ + I2S_TDR_REG(PeripheralBase,0U) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDataRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxDataRegAddress(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxDataRegAddress(PeripheralBase) ( \ + (uint32)&I2S_TDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for transmit data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxWriteFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxWriteFifoPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(I2S_TFR_REG(PeripheralBase,0U) & I2S_TFR_WFP_MASK)) >> ( \ + I2S_TFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for transmit data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxReadFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxReadFifoPointer(PeripheralBase) ( \ + (uint8)(I2S_TFR_REG(PeripheralBase,0U) & I2S_TFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDataChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver data channel. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3. + * @par Example: + * @code + * I2S_PDD_EnableRxDataChannel(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxDataChannel(PeripheralBase, State) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_RCE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_RCR3_RCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxDataReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxDataReg(PeripheralBase) ( \ + I2S_RDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxDataRegAddress(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxDataRegAddress(PeripheralBase) ( \ + (uint32)&I2S_RDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for receive data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxWriteFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxWriteFifoPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(I2S_RFR_REG(PeripheralBase,0U) & I2S_RFR_WFP_MASK)) >> ( \ + I2S_RFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for receive data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxReadFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxReadFifoPointer(PeripheralBase) ( \ + (uint8)(I2S_RFR_REG(PeripheralBase,0U) & I2S_RFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxFifoReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxFifoReg(PeripheralBase) ( \ + I2S_RFR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxClockingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock transmit clock mode and source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkMode Transmit clock mode value. Use constants from group "Clocking + * transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + * macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2. + * @par Example: + * @code + * I2S_PDD_SetTxClockingMode(_BASE_PTR, + * I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetTxClockingMode(PeripheralBase, ClkMode) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_CLKMODE_MASK))) | ( \ + (uint32)((uint32)(ClkMode) << I2S_TCR2_CLKMODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxClockingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock receive clock mode and source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkMode Transmit clock mode value. Use constants from group "Clocking + * transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + * macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2. + * @par Example: + * @code + * I2S_PDD_SetRxClockingMode(_BASE_PTR, + * I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetRxClockingMode(PeripheralBase, ClkMode) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_CLKMODE_MASK))) | ( \ + (uint32)((uint32)(ClkMode) << I2S_RCR2_CLKMODE_SHIFT))) \ + ) +#endif /* #if defined(SAI_PDD_H_) */ + +/* SAI_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h new file mode 100644 index 0000000..5050213 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h @@ -0,0 +1,2413 @@ +/* + PDD layer implementation for peripheral type SDHC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SDHC_PDD_H_) +#define SDHC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SDHC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SDHC */ && \ + !defined(MCU_MK10F12) /* SDHC */ && \ + !defined(MCU_MK10DZ10) /* SDHC */ && \ + !defined(MCU_MK20D10) /* SDHC */ && \ + !defined(MCU_MK20F12) /* SDHC */ && \ + !defined(MCU_MK20DZ10) /* SDHC */ && \ + !defined(MCU_MK21F12) /* SDHC */ && \ + !defined(MCU_MK21F12WS) /* SDHC */ && \ + !defined(MCU_MK22F12) /* SDHC */ && \ + !defined(MCU_MK24F12) /* SDHC */ && \ + !defined(MCU_MK30D10) /* SDHC */ && \ + !defined(MCU_MK30DZ10) /* SDHC */ && \ + !defined(MCU_MK40D10) /* SDHC */ && \ + !defined(MCU_MK40DZ10) /* SDHC */ && \ + !defined(MCU_MK40X256VMD100) /* SDHC */ && \ + !defined(MCU_MK50D10) /* SDHC */ && \ + !defined(MCU_MK50DZ10) /* SDHC */ && \ + !defined(MCU_MK51D10) /* SDHC */ && \ + !defined(MCU_MK51DZ10) /* SDHC */ && \ + !defined(MCU_MK52D10) /* SDHC */ && \ + !defined(MCU_MK52DZ10) /* SDHC */ && \ + !defined(MCU_MK53D10) /* SDHC */ && \ + !defined(MCU_MK53DZ10) /* SDHC */ && \ + !defined(MCU_MK60D10) /* SDHC */ && \ + !defined(MCU_MK60F12) /* SDHC */ && \ + !defined(MCU_MK60F15) /* SDHC */ && \ + !defined(MCU_MK60DZ10) /* SDHC */ && \ + !defined(MCU_MK60N512VMD100) /* SDHC */ && \ + !defined(MCU_MK61F12) /* SDHC */ && \ + !defined(MCU_MK61F15) /* SDHC */ && \ + !defined(MCU_MK61F12WS) /* SDHC */ && \ + !defined(MCU_MK61F15WS) /* SDHC */ && \ + !defined(MCU_MK63F12) /* SDHC */ && \ + !defined(MCU_MK63F12WS) /* SDHC */ && \ + !defined(MCU_MK64F12) /* SDHC */ && \ + !defined(MCU_MK65F18) /* SDHC */ && \ + !defined(MCU_MK65F18WS) /* SDHC */ && \ + !defined(MCU_MK66F18) /* SDHC */ && \ + !defined(MCU_MK70F12) /* SDHC */ && \ + !defined(MCU_MK70F15) /* SDHC */ && \ + !defined(MCU_MK70F12WS) /* SDHC */ && \ + !defined(MCU_MK70F15WS) /* SDHC */ + // Unsupported MCU is active + #error SDHC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Transfer DMA usage */ +#define SDHC_PDD_ENABLE_DMA SDHC_XFERTYP_DMAEN_MASK /**< Enable DMA. */ +#define SDHC_PDD_DISABLE_DMA 0U /**< Disable DMA. */ + +/* Transfer block count */ +#define SDHC_PDD_ENABLE_BLOCK_COUNT SDHC_XFERTYP_BCEN_MASK /**< Enable block count. */ +#define SDHC_PDD_DISABLE_BLOCK_COUNT 0U /**< Disable block count. */ + +/* Transfer auto CMD12 */ +#define SDHC_PDD_ENABLE_AUTO_CMD12 SDHC_XFERTYP_AC12EN_MASK /**< Enable auto CMD12. */ +#define SDHC_PDD_DISABLE_AUTO_CMD12 0U /**< Disable auto CMD12. */ + +/* Transfer data direction */ +#define SDHC_PDD_DATA_READ SDHC_XFERTYP_DTDSEL_MASK /**< Data read. */ +#define SDHC_PDD_DATA_WRITE 0U /**< Data write. */ + +/* Transfer multi/single block */ +#define SDHC_PDD_SINGLE_BLOCK 0U /**< Single block. */ +#define SDHC_PDD_MULTIPLE_BLOCK SDHC_XFERTYP_MSBSEL_MASK /**< Multiple block. */ + +/* Command response type */ +#define SDHC_PDD_NO_RESPONSE 0U /**< No response. */ +#define SDHC_PDD_RESPONSE_LENGTH_136 0x10000U /**< Response of length 136 bit. */ +#define SDHC_PDD_RESPONSE_LENGTH_48 0x20000U /**< Response of length 48 bit. */ +#define SDHC_PDD_RESPONSE_LENGTH_48_BUSY_CHECK 0x30000U /**< Response of length 48 bit with busy check. */ + +/* Command CRC check */ +#define SDHC_PDD_ENABLE_CRC_CHECK SDHC_XFERTYP_CCCEN_MASK /**< Enable CRC check. */ +#define SDHC_PDD_DISABLE_CRC_CHECK 0U /**< Disable CRC check. */ + +/* Command index check */ +#define SDHC_PDD_ENABLE_INDEX_CHECK SDHC_XFERTYP_CICEN_MASK /**< Enable index check. */ +#define SDHC_PDD_DISABLE_INDEX_CHECK 0U /**< Disable index check. */ + +/* Command data present */ +#define SDHC_PDD_DATA_PRESENT SDHC_XFERTYP_DPSEL_MASK /**< Data present. */ +#define SDHC_PDD_NO_DATA_PRESENT 0U /**< No data present. */ + +/* Command type */ +#define SDHC_PDD_NORMAL_CMD 0U /**< Normal command. */ +#define SDHC_PDD_SUSPEND_CMD 0x400000U /**< Suspend command. */ +#define SDHC_PDD_RESUME_CMD 0x800000U /**< Resume command. */ +#define SDHC_PDD_ABORT_CMD 0xC00000U /**< Abort command. */ + +/* Command class 0 - basic */ +#define SDHC_PDD_CMD0_GO_IDLE_STATE 0U /**< Go idle state. */ +#define SDHC_PDD_CMD1_SEND_OP_COND 0x1U /**< Send operation conditions. */ +#define SDHC_PDD_CMD2_ALL_SEND_CID 0x2U /**< All send CID (card identification register). */ +#define SDHC_PDD_CMD3_SET_RELATIVE_ADDR 0x3U /**< Set/send relative address. */ +#define SDHC_PDD_CMD4_SET_DSR 0x4U /**< Set DSR (driver stage register). */ +#define SDHC_PDD_CMD5_IO_SEND_OP_COND 0x5U /**< Send IO conditions. */ +#define SDHC_PDD_CMD6_SWITCH 0x6U /**< Switch function. */ +#define SDHC_PDD_CMD7_SELECT_CARD 0x7U /**< Select/deselect card. */ +#define SDHC_PDD_CMD8_SEND_EXT_CSD 0x8U /**< Send EXT_CSD (extended card specific data register). */ +#define SDHC_PDD_CMD9_SEND_CSD 0x9U /**< Send CSD (card specific data register). */ +#define SDHC_PDD_CMD10_SEND_CID 0xAU /**< Send CID (card identification register). */ +#define SDHC_PDD_CMD12_STOP_TRANSMISSION 0xCU /**< Stop transmission. */ +#define SDHC_PDD_CMD13_SEND_STATUS 0xDU /**< Send status. */ +#define SDHC_PDD_CMD14_BUS_TEST_READ 0xEU /**< Bus test pattern read. */ +#define SDHC_PDD_CMD15_GO_INACTIVE_STATE 0xFU /**< Go inactive state. */ +#define SDHC_PDD_CMD19_BUS_TEST_WRITE 0x13U /**< Bus test pattern write. */ + +/* Command class 1 - stream read */ +#define SDHC_PDD_CMD11_READ_DAT_UNTIL_STOP 0xBU /**< Read data until stop. */ + +/* Command class 2 - block read */ +#define SDHC_PDD_CMD16_SET_BLOCKLEN 0x10U /**< Set block length. */ +#define SDHC_PDD_CMD17_READ_SINGLE_BLOCK 0x11U /**< Read single block. */ +#define SDHC_PDD_CMD18_READ_MULTIPLE_BLOCK 0x12U /**< Read multiple block. */ + +/* Command class 3 - stream write */ +#define SDHC_PDD_CMD20_WRITE_DAT_UNTIL_STOP 0x14U /**< Write data until stop. */ + +/* Command class 4 - block write */ +#define SDHC_PDD_CMD24_WRITE_BLOCK 0x18U /**< Write block. */ +#define SDHC_PDD_CMD25_WRITE_MULTIPLE_BLOCK 0x19U /**< Write multiple block. */ +#define SDHC_PDD_CMD26_PROGRAM_CID 0x1AU /**< Program CID (card identification register). */ +#define SDHC_PDD_CMD27_PROGRAM_CSD 0x1BU /**< Program CSD (card specific data register). */ + +/* Command class 5 - erase */ +#define SDHC_PDD_CMD32_TAG_SECTOR_START 0x20U /**< Tag sector start [SD]. */ +#define SDHC_PDD_CMD33_TAG_SECTOR_END 0x21U /**< Tag sector end [SD]. */ +#define SDHC_PDD_CMD34_UNTAG_SECTOR 0x22U /**< Untag sector. */ +#define SDHC_PDD_CMD35_TAG_ERASE_GROUP_START 0x23U /**< Tag erase group start [MMC]. */ +#define SDHC_PDD_CMD36_TAG_ERASE_GROUP_END 0x24U /**< Tag erase group end [MMC]. */ +#define SDHC_PDD_CMD37_UNTAG_ERASE_GROUP 0x25U /**< Untag erase group. */ +#define SDHC_PDD_CMD38_ERASE 0x26U /**< Erase. */ + +/* Command class 6 - write protection */ +#define SDHC_PDD_CMD28_SET_WRITE_PROT 0x1CU /**< Set write protection. */ +#define SDHC_PDD_CMD29_CLR_WRITE_PROT 0x1DU /**< Clear write protection. */ +#define SDHC_PDD_CMD30_SEND_WRITE_PROT 0x1EU /**< Send write protection. */ + +/* Command class 7 - lock card */ +#define SDHC_PDD_CMD42_LOCK_UNLOCK 0x2AU /**< Lock/unlock card. */ + +/* Command class 8 - application specific */ +#define SDHC_PDD_CMD55_APP_CMD 0x37U /**< Application specific command. */ +#define SDHC_PDD_CMD56_GEN_CMD 0x38U /**< General purpose command. */ + +/* Command class 9 - IO mode */ +#define SDHC_PDD_CMD39_FAST_IO 0x27U /**< Fast IO [MMC]. */ +#define SDHC_PDD_CMD40_GO_IRQ_STATE 0x28U /**< Go IRQ state [MMC]. */ +#define SDHC_PDD_CMD52_IO_RW_DIRECT 0x34U /**< IO direct read/write [SD]. */ +#define SDHC_PDD_CMD53_IO_RW_EXTENDED 0x35U /**< IO extended read/write [SD]. */ + +/* Command class 10 - switch [SD] */ +#define SDHC_PDD_CMD60_RW_MULTIPLE_REG 0x3CU /**< Read/write multiple register. */ +#define SDHC_PDD_CMD61_RW_MULTIPLE_BLOCK 0x3DU /**< Read/write multiple block. */ + +/* Application specific commands [SD] */ +#define SDHC_PDD_ACMD6_SET_BUS_WIDTH 0x6U /**< Set bus width. */ +#define SDHC_PDD_ACMD13_SD_STATUS 0xDU /**< Send SD status. */ +#define SDHC_PDD_ACMD22_SEND_NUM_WR_SECTORS 0x16U /**< Send number of written sectors. */ +#define SDHC_PDD_ACMD23_SET_WR_BLK_ERASE_COUNT 0x17U /**< Set write block erase count. */ +#define SDHC_PDD_ACMD41_SD_APP_OP_COND 0x29U /**< Send operational conditions. */ +#define SDHC_PDD_ACMD42_SET_CLR_CARD_DETECT 0x2AU /**< Set/clear card detection. */ +#define SDHC_PDD_ACMD51_SEND_SCR 0x33U /**< Send SCR (SD configuration register). */ + +/* Clock divider values */ +#define SDHC_PDD_BASE_DIV_BY_2 0x1U /**< Base clock divided by 2. */ +#define SDHC_PDD_BASE_DIV_BY_4 0x2U /**< Base clock divided by 4. */ +#define SDHC_PDD_BASE_DIV_BY_8 0x4U /**< Base clock divided by 8. */ +#define SDHC_PDD_BASE_DIV_BY_16 0x8U /**< Base clock divided by 16. */ +#define SDHC_PDD_BASE_DIV_BY_32 0x10U /**< Base clock divided by 32. */ +#define SDHC_PDD_BASE_DIV_BY_64 0x20U /**< Base clock divided by 64. */ +#define SDHC_PDD_BASE_DIV_BY_128 0x40U /**< Base clock divided by 128. */ +#define SDHC_PDD_BASE_DIV_BY_256 0x80U /**< Base clock divided by 256. */ + +/* Interrupt masks */ +#define SDHC_PDD_COMMAND_COMPLETE_INT SDHC_IRQSTAT_CC_MASK /**< The end bit of the command response is received (except Auto CMD12). */ +#define SDHC_PDD_TRANSFER_COMPLETE_INT SDHC_IRQSTAT_TC_MASK /**< Read or write transfer is completed. */ +#define SDHC_PDD_BLOCK_GAP_EVENT_INT SDHC_IRQSTAT_BGE_MASK /**< Read or write transaction is stopped at a block gap. */ +#define SDHC_PDD_DMA_INT SDHC_IRQSTAT_DINT_MASK /**< The internal DMA (simple or advanced) finished the data transfer successfully. */ +#define SDHC_PDD_BUFFER_WRITE_READY_INT SDHC_IRQSTAT_BWR_MASK /**< Ready to write buffer. */ +#define SDHC_PDD_BUFFER_READ_READY_INT SDHC_IRQSTAT_BRR_MASK /**< Ready to read buffer. */ +#define SDHC_PDD_CARD_INSERTION_INT SDHC_IRQSTAT_CINS_MASK /**< Card inserted. */ +#define SDHC_PDD_CARD_REMOVAL_INT SDHC_IRQSTAT_CRM_MASK /**< Card removed. */ +#define SDHC_PDD_CARD_INT SDHC_IRQSTAT_CINT_MASK /**< Card interrupt. */ +#define SDHC_PDD_COMMAND_TIMEOUT_ERROR_INT SDHC_IRQSTAT_CTOE_MASK /**< No response is returned within 64 SDHC_CLK cycles from the end bit of the command or SDHC detects a SDHC_CMD line conflict. */ +#define SDHC_PDD_COMMAND_CRC_ERROR_INT SDHC_IRQSTAT_CCE_MASK /**< CRC error in the command response is detected or SDHC_CMD line conflict is detected when a command is issued. */ +#define SDHC_PDD_COMMAND_END_BIT_ERROR_INT SDHC_IRQSTAT_CEBE_MASK /**< The end bit of a command response is 0. */ +#define SDHC_PDD_COMMAND_INDEX_ERROR_INT SDHC_IRQSTAT_CIE_MASK /**< Command index error occured in the command response. */ +#define SDHC_PDD_DATA_TIMEOUT_ERROR_INT SDHC_IRQSTAT_DTOE_MASK /**< Data timeout error. */ +#define SDHC_PDD_DATA_CRC_ERROR_INT SDHC_IRQSTAT_DCE_MASK /**< CRC error detected when transferring read data on the SDHC_DAT line or the write CRC status having a value other than 0b010 detected. */ +#define SDHC_PDD_DATA_END_BIT_ERROR_INT SDHC_IRQSTAT_DEBE_MASK /**< Zero at the end bit position of read data on the SDHC_DAT line or at the end bit position of the CRC detected. */ +#define SDHC_PDD_AUTO_CMD12_ERROR_INT SDHC_IRQSTAT_AC12E_MASK /**< Auto CMD12 error. */ +#define SDHC_PDD_DMA_ERROR_INT SDHC_IRQSTAT_DMAE_MASK /**< Internal DMA (simple or advanced) transfer failed. */ + +/* Filter modes */ +#define SDHC_PDD_AUTO_CMD12_NOT_EXECUTED SDHC_AC12ERR_AC12NE_MASK /**< Auto CMD12 not executed. */ +#define SDHC_PDD_AUTO_CMD12_TIMEOUT_ERROR SDHC_AC12ERR_AC12TOE_MASK /**< Auto CMD12 timeout error. */ +#define SDHC_PDD_AUTO_CMD12_END_BIT_ERROR SDHC_AC12ERR_AC12EBE_MASK /**< Auto CMD12 end bit error. */ +#define SDHC_PDD_AUTO_CMD12_CRC_ERROR SDHC_AC12ERR_AC12CE_MASK /**< Auto CMD12 CRC error. */ +#define SDHC_PDD_AUTO_CMD12_INDEX_ERROR SDHC_AC12ERR_AC12IE_MASK /**< Auto CMD12 index error. */ +#define SDHC_PDD_CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR SDHC_AC12ERR_CNIBAC12E_MASK /**< Command not issued by Auto CMD12 error. */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/* Host capabilities flags */ + #define SDHC_PDD_ADMA_SUPPORT SDHC_HTCAPBLT_ADMAS_MASK /**< Advanced DMA support. */ + #define SDHC_PDD_HIGH_SPEED_SUPPORT SDHC_HTCAPBLT_HSS_MASK /**< High speed support. */ + #define SDHC_PDD_DMA_SUPPORT SDHC_HTCAPBLT_DMAS_MASK /**< DMA support. */ + #define SDHC_PDD_SUSPEND_RESUME_SUPPORT SDHC_HTCAPBLT_SRS_MASK /**< Suspend/resume support. */ + #define SDHC_PDD_3_3_V_SUPPORT SDHC_HTCAPBLT_VS33_MASK /**< Voltage support 3.3V. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Host capabilities flags */ + #define SDHC_PDD_ADMA_SUPPORT SDHC_HTCAPBLT_ADMAS_MASK /**< Advanced DMA support. */ + #define SDHC_PDD_HIGH_SPEED_SUPPORT SDHC_HTCAPBLT_HSS_MASK /**< High speed support. */ + #define SDHC_PDD_DMA_SUPPORT SDHC_HTCAPBLT_DMAS_MASK /**< DMA support. */ + #define SDHC_PDD_SUSPEND_RESUME_SUPPORT SDHC_HTCAPBLT_SRS_MASK /**< Suspend/resume support. */ + #define SDHC_PDD_3_3_V_SUPPORT SDHC_HTCAPBLT_VS33_MASK /**< Voltage support 3.3V. */ + #define SDHC_PDD_3_0_V_SUPPORT SDHC_HTCAPBLT_VS30_MASK /**< Voltage support 3.0V. */ + #define SDHC_PDD_1_8_V_SUPPORT SDHC_HTCAPBLT_VS18_MASK /**< Voltage support 1.8V. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Force event masks */ +#define SDHC_PDD_AUTO_CMD12_NOT_EXECUTED_EVENT SDHC_FEVT_AC12NE_MASK /**< Auto CMD12 not executed event. */ +#define SDHC_PDD_AUTO_CMD12_TIMEOUT_ERROR_EVENT SDHC_FEVT_AC12TOE_MASK /**< Auto CMD12 timeout error event. */ +#define SDHC_PDD_AUTO_CMD12_CRC_ERROR_EVENT SDHC_FEVT_AC12CE_MASK /**< Auto CMD12 CRC error event. */ +#define SDHC_PDD_AUTO_CMD12_END_BIT_ERROR_EVENT SDHC_FEVT_AC12EBE_MASK /**< Auto CMD12 end bit error event. */ +#define SDHC_PDD_AUTO_CMD12_INDEX_ERROR_EVENT SDHC_FEVT_AC12IE_MASK /**< Auto CMD12 index error event. */ +#define SDHC_PDD_CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR_EVENT SDHC_FEVT_CNIBAC12E_MASK /**< Command not executed by Auto CMD12 error event. */ +#define SDHC_PDD_COMMAND_TIMEOUT_ERROR_EVENT SDHC_FEVT_CTOE_MASK /**< Command time out error event. */ +#define SDHC_PDD_COMMAND_CRC_ERROR_EVENT SDHC_FEVT_CCE_MASK /**< Command CRC error event. */ +#define SDHC_PDD_COMMAND_END_BIT_ERROR_EVENT SDHC_FEVT_CEBE_MASK /**< Command end bit error event. */ +#define SDHC_PDD_COMMAND_INDEX_ERROR_EVENT SDHC_FEVT_CIE_MASK /**< Command index error event. */ +#define SDHC_PDD_DATA_TIMEOUT_ERROR_EVENT SDHC_FEVT_DTOE_MASK /**< Data time out error event. */ +#define SDHC_PDD_DATA_CRC_ERROR_EVENT SDHC_FEVT_DCE_MASK /**< Data CRC error event. */ +#define SDHC_PDD_DATA_END_BIT_ERROR_EVENT SDHC_FEVT_DEBE_MASK /**< Data end bit error event. */ +#define SDHC_PDD_AUTO_CMD12_ERROR_EVENT SDHC_FEVT_AC12E_MASK /**< Auto CMD12 error event. */ +#define SDHC_PDD_DMA_ERROR_EVENT SDHC_FEVT_DMAE_MASK /**< DMA error event. */ +#define SDHC_PDD_CARD_INTERRUPT_EVENT SDHC_FEVT_CINT_MASK /**< Card interrupt event. */ + +/* Clock sources */ +#define SDHC_PDD_CORE_SYSTEM_CLOCK 0U /**< Core/system clock. */ +#define SDHC_PDD_PLL_FLL_CLOCK 0x1U /**< PLL or FLL clock. */ +#define SDHC_PDD_EXTAL_CLOCK 0x2U /**< Extal clock. */ +#define SDHC_PDD_EXTERNAL_CLOCK 0x3U /**< External clock. */ + +/* LED states */ +#define SDHC_PDD_LED_ON 0x1U /**< LED on. */ +#define SDHC_PDD_LED_OFF 0U /**< LED off. */ + +/* Data transfer widths */ +#define SDHC_PDD_1_BIT_MODE 0U /**< 1 bit data width. */ +#define SDHC_PDD_4_BIT_MODE 0x2U /**< 4 bit data width. */ +#define SDHC_PDD_8_BIT_MODE 0x4U /**< 8 bit data width. */ + +/* Endian modes */ +#define SDHC_PDD_BIG_ENDIAN_MODE 0U /**< Big endian. */ +#define SDHC_PDD_HALF_WORD_BIG_ENDIAN_MODE 0x10U /**< Half word big endian. */ +#define SDHC_PDD_LITTLE_ENDIAN_MODE 0x20U /**< Little endian. */ + +/* DMA modes */ +#define SDHC_PDD_NO_OR_SIMPLE_DMA_MODE 0U /**< No DMA or simple DMA. */ +#define SDHC_PDD_ADVANCED_DMA_1_MODE 0x100U /**< Advanced DMA version 1. */ +#define SDHC_PDD_ADVANCED_DMA_2_MODE 0x200U /**< Advanced DMA version 2. */ + +/* ADMA error states */ +#define SDHC_PDD_ADMA_STOP 0U /**< Stop DMA. */ +#define SDHC_PDD_ADMA_FETCH_DESCRIPTOR 0x1U /**< Fetch descriptor. */ +#define SDHC_PDD_ADMA_CHANGE_ADDRESS 0x2U /**< Change address. */ +#define SDHC_PDD_ADMA_TRANSFER_DATA 0x3U /**< Transfer data. */ + +/* MMC boot modes */ +#define SDHC_PDD_NORMAL_BOOT 0U /**< Normal boot. */ +#define SDHC_PDD_ALTERNATIVE_BOOT 0x20U /**< Alternative boot. */ + +/* Specification version numbers */ +#define SDHC_PDD_SD_HOST_SPECIFICATION_V_2_0 0x1U /**< SD host specification version 2.0. */ + +/* Vendor version numbers */ +#define SDHC_PDD_FREESCALE_ESDHC_V_1_0 0U /**< Freescale eSDHC version 1.0. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_0 0x100U /**< Freescale eSDHC version 2.0. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_1 0x1100U /**< Freescale eSDHC version 2.1. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_2 0x1200U /**< Freescale eSDHC version 2.2. */ + + +/* ---------------------------------------------------------------------------- + -- SetDMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the DMA system address containing the physical system memory + * address used for DMA transfers. Should be called only when no transactions are + * executing (after transactions have stopped). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address DMA system address. Should be aligned to a 4 byte boundary. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_DSADDR. + * @par Example: + * @code + * SDHC_PDD_SetDMAAddress(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetDMAAddress(PeripheralBase, Address) ( \ + SDHC_DSADDR_REG(PeripheralBase) = \ + (uint32)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DMA system address containing the system address of the + * next contiguous data position after the last DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_DSADDR. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetDMAAddress(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetDMAAddress(PeripheralBase) ( \ + SDHC_DSADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBlockSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the block size for block data transfers. Should be called only + * when no transactions are executing (after transactions have stopped). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Transfer block size (from 0 to 4096). Should be aligned to a 4 + * byte boundary. This parameter is a 13-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * SDHC_PDD_SetBlockSize(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBlockSize(PeripheralBase, Size) ( \ + SDHC_BLKATTR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_BLKATTR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_BLKATTR_BLKSIZE_MASK)))) | ( \ + (uint32)(Size))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the block count for multiple block transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Block count for current transfer. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * SDHC_PDD_SetBlockCount(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBlockCount(PeripheralBase, Count) ( \ + SDHC_BLKATTR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_BLKATTR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_BLKATTR_BLKCNT_MASK)))) | ( \ + (uint32)((uint32)(Count) << SDHC_BLKATTR_BLKCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the block count left for the current transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * uint16 result = SDHC_PDD_GetBlockCount(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetBlockCount(PeripheralBase) ( \ + (uint16)(( \ + (uint32)(SDHC_BLKATTR_REG(PeripheralBase) & SDHC_BLKATTR_BLKCNT_MASK)) >> ( \ + SDHC_BLKATTR_BLKCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCommandArgument + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the command argument specified as bits 39-8 of the SD/MMC command + * format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Argument Command argument. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_CMDARG. + * @par Example: + * @code + * SDHC_PDD_SetCommandArgument(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetCommandArgument(PeripheralBase, Argument) ( \ + SDHC_CMDARG_REG(PeripheralBase) = \ + (uint32)(Argument) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Sends a command through the CMD bus line. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Command index. Use constants from the following groups: "Command + * class 0 - basic", "Command class 1 - stream read", "Command class 2 - + * block read", "Command class 3 - stream write", "Command class 4 - block + * write", "Command class 5 - erase", "Command class 6 - write + * protection", "Command class 7 - lock card", "Command class 8 - application + * specific", "Command class 9 - IO mode", "Command class 10 - switch [SD]", + * "Application specific commands [SD]". This parameter is 6 bits wide. + * @param Options Command options mask (one value from each constants group). + * Use constants from the following groups: "Transfer DMA usage", "Transfer + * block count", "Transfer auto CMD12", "Transfer data direction", + * "Transfer multi/single block", "Command response type", "Command CRC check", + * "Command index check", "Command data present", "Command type". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_XFERTYP. + * @par Example: + * @code + * SDHC_PDD_SendCommand(_BASE_PTR, 1, 1); + * @endcode + */ +#define SDHC_PDD_SendCommand(PeripheralBase, Index, Options) ( \ + SDHC_XFERTYP_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(Options)) | ( \ + (uint32)((uint32)(Index) << SDHC_XFERTYP_CMDINX_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandResponse + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the command response. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Response A four 32-bit values array variable, where to store the + * response. This parameter is of user-defined type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMDRSP[]. + * @par Example: + * @code + * SDHC_PDD_GetCommandResponse(_BASE_PTR, [Response]); + * @endcode + */ +#define SDHC_PDD_GetCommandResponse(PeripheralBase, Response) ( \ + Response[0] = SDHC_CMDRSP_REG(PeripheralBase,0U), \ + (Response[1] = SDHC_CMDRSP_REG(PeripheralBase,1U), \ + (Response[2] = SDHC_CMDRSP_REG(PeripheralBase,2U), \ + Response[3] = SDHC_CMDRSP_REG(PeripheralBase,3U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the internal buffer data content if the internal DMA is not + * used. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data content. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_DATPORT. + * @par Example: + * @code + * SDHC_PDD_SetBufferData(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBufferData(PeripheralBase, Data) ( \ + SDHC_DATPORT_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads the internal buffer data content if the internal DMA is not used. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_DATPORT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetBufferData(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetBufferData(PeripheralBase) ( \ + SDHC_DATPORT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCommandInhibited + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if a command is in progress (SDHC_CMD line is in use) + * until a command response is received. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCommandInhibited(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCommandInhibited(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CIHB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsDataCommandInhibited + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if a command with data transfer is in progress (SDHC_DAT + * line is in use) until data transfer is completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsDataCommandInhibited(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsDataCommandInhibited(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CDIHB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsDataLineActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if any of the data lines are in use. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsDataLineActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsDataLineActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_DLA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsSDClockStable + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the SD clock is stable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsSDClockStable(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsSDClockStable(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_SDSTB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsControllerClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the controller clock is gated off internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsControllerClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsControllerClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_IPGOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCrossbarClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the crossbar switch master clock is gated off + * internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsCrossbarClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCrossbarClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_HCKOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsPeripheralClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the crossbar switch master clock is gated off + * internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsPeripheralClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsPeripheralClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_PEROFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsSDHCClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the SDHC clock is gated off internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsSDHCClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsSDHCClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_SDOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsWriteTransferActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a write transfer is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsWriteTransferActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsWriteTransferActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_WTA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsReadTransferActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a read transfer is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsReadTransferActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsReadTransferActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_RTA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsBufferWriteEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether there is space for write data in the internal + * buffer. Used for non-DMA write transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsBufferWriteEnabled(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsBufferWriteEnabled(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_BWEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsBufferReadEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether there is space for read data in the internal buffer. + * Used for non-DMA read transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsBufferReadEnabled(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsBufferReadEnabled(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_BREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCardInserted + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a card is inserted. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCardInserted(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCardInserted(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CINS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCMDLineLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the SDHC_CMD line signal level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetCMDLineLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetCMDLineLevel(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CLSL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDATLineLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the SDHC_DAT line signal levels. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetDATLineLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetDATLineLevel(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_DLSL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLEDState + ---------------------------------------------------------------------------- */ + +/** + * @brief Controls the LED state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State LED state. This parameter is of "LED states" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetLEDState(_BASE_PTR, SDHC_PDD_LED_ON); + * @endcode + */ +#define SDHC_PDD_SetLEDState(PeripheralBase, State) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_LCTL_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataTransferWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data transfer width (data width of the SD bus). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data transfer width. This parameter is of "Data transfer widths" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetDataTransferWidth(_BASE_PTR, + * SDHC_PDD_1_BIT_MODE); + * @endcode + */ +#define SDHC_PDD_SetDataTransferWidth(PeripheralBase, Width) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_DTW_MASK))) | ( \ + (uint32)(Width))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDAT3AsCardDetectionPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables card detection on the DAT3 pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableDAT3AsCardDetectionPin(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableDAT3AsCardDetectionPin(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_D3CD_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_D3CD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetEndianMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the endian mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Endian mode. This parameter is of "Endian modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetEndianMode(_BASE_PTR, SDHC_PDD_BIG_ENDIAN_MODE); + * @endcode + */ +#define SDHC_PDD_SetEndianMode(PeripheralBase, Mode) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_PROCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_PROCTL_EMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCardDetectTestLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Determines card insertion status when card detection test level is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetCardDetectTestLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetCardDetectTestLevel(PeripheralBase) ( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & SDHC_PROCTL_CDTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCardDetectionTestLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables card detection test level (for test purpose). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableCardDetectionTestLevel(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableCardDetectionTestLevel(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_CDSS_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_CDSS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDMAMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the DMA mode when DMA is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode DMA mode. This parameter is of "DMA modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetDMAMode(_BASE_PTR, + * SDHC_PDD_NO_OR_SIMPLE_DMA_MODE); + * @endcode + */ +#define SDHC_PDD_SetDMAMode(PeripheralBase, Mode) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_DMAS_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStopAtBlockGapRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transaction execution stop at the next block gap for + * both DMA and non-DMA transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableStopAtBlockGapRequest(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableStopAtBlockGapRequest(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_SABGREQ_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_SABGREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ContinueRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Restarts a transaction which was stopped using the stop-at-block-gap + * request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_ContinueRequest(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ContinueRequest(PeripheralBase) ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_CREQ_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReadWaitControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables read wait control. Should be enabled only if the card + * supports this feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableReadWaitControl(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableReadWaitControl(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_RWCTL_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_RWCTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptAtBlockGap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables interrupt at block gap. Interrupt enable is valid + * only in 4-bit mode and the SD card should support this feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableInterruptAtBlockGap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableInterruptAtBlockGap(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_IABG_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_IABG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card interrupt. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardInterrupt(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardInterrupt(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECINT_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardInsertion + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card insertion. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardInsertion(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardInsertion(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECINS_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECINS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardRemoval + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card removal. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardRemoval(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardRemoval(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECRM_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECRM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableControllerClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables controller clock. If enabled, the controller clock is + * always active and no automatic gating is applied. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableControllerClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableControllerClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_IPGEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_IPGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrossbarClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables crossbar switch master clock. If enabled, the clock + * is always active and no automatic gating is applied. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableCrossbarClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableCrossbarClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_HCKEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_HCKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePeripheralClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables peripheral clock. If enabled, the peripheral clock is + * always active and no automatic gating is applied, thus SDHC_CLK is active + * only except auto gating-off during buffer danger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnablePeripheralClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnablePeripheralClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_PEREN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_PEREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSDHCClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SDHC clock. The SDHC_CLK frequency should be changed + * only if SDHC clock is disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableSDHCClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableSDHCClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_SDCLKEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_SDCLKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSDHCClockDivisor + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SDHC clock divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divisor SDHC clock divisor decreased by 1 (e.g. 2 means divisor by 3). + * This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetSDHCClockDivisor(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetSDHCClockDivisor(PeripheralBase, Divisor) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_SYSCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_SYSCTL_DVS_MASK))) | ( \ + (uint32)((uint32)(Divisor) << SDHC_SYSCTL_DVS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSDHCClockFrequency + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SDHC clock frequency. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Frequency SDHC clock frequency. Use constants from group "Clock + * divider values". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetSDHCClockFrequency(_BASE_PTR, + * SDHC_PDD_BASE_DIV_BY_2); + * @endcode + */ +#define SDHC_PDD_SetSDHCClockFrequency(PeripheralBase, Frequency) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_SYSCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_SYSCTL_SDCLKFS_MASK)))) | ( \ + (uint32)((uint32)(Frequency) << SDHC_SYSCTL_SDCLKFS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data timeout counter value. Determines the interval by which + * SDHC_DAT line timeouts are detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Timeout Data timeout counter value (from 0 to 14). Specifies the + * timeout value as 2^(13 + Timeout) SDHC clock cycles. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetDataTimeout(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetDataTimeout(PeripheralBase, Timeout) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_SYSCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_SYSCTL_DTOCV_MASK)))) | ( \ + (uint32)((uint32)(Timeout) << SDHC_SYSCTL_DTOCV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetDevice(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetDevice(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetCMDLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the SDHC_CMD line. Only part of the command circuit is reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetCMDLine(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetCMDLine(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetDATLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the SDHC_DAT line. The DMA and part of the data circuit are + * reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetDATLine(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetDATLine(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTD_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InitCard + ---------------------------------------------------------------------------- */ + +/** + * @brief Send 80 SD clocks to the card. Should be used during the card power-up + * period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_InitCard(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_InitCard(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_INITA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCardInitComplete + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether card initialization is completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCardInitComplete(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCardInitComplete(PeripheralBase) ( \ + (uint32)(( \ + (uint32)(SDHC_SYSCTL_REG(PeripheralBase) & SDHC_SYSCTL_INITA_MASK)) ^ ( \ + SDHC_SYSCTL_INITA_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the interrupt flags. The returned value can be masked with + * predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_IRQSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetInterruptFlags(PeripheralBase) ( \ + SDHC_IRQSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the specified interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTAT. + * @par Example: + * @code + * SDHC_PDD_ClearInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTAT_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSIGEN. + * @par Example: + * @code + * SDHC_PDD_EnableInterrupts(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + SDHC_IRQSIGEN_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSIGEN. + * @par Example: + * @code + * SDHC_PDD_DisableInterrupts(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + SDHC_IRQSIGEN_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt flags specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt masks". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTATEN. + * @par Example: + * @code + * SDHC_PDD_EnableInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_EnableInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTATEN_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt flags specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt masks". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTATEN. + * @par Example: + * @code + * SDHC_PDD_DisableInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_DisableInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTATEN_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAutoCMD12ErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the Auto CMD12 error flags. The return value can be mask with: + * AUTO_CMD12_NOT_EXECUTED, AUTO_CMD12_TIMEOUT_ERROR, AUTO_CMD12_END_BIT_ERROR, + * AUTO_CMD12_CRC_ERROR, AUTO_CMD12_INDEX_ERROR, + * CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_AC12ERR. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetAutoCMD12ErrorFlags(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetAutoCMD12ErrorFlags(PeripheralBase) ( \ + SDHC_AC12ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetHostCapabilities + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns host controller capabilities flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_HTCAPBLT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetHostCapabilities(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetHostCapabilities(PeripheralBase) ( \ + SDHC_HTCAPBLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMaxBlockLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates the maximum block size that the host driver can read and + * write to the buffer in the SDHC. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_HTCAPBLT. + * @par Example: + * @code + * SDHC_PDD_GetMaxBlockLength(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetMaxBlockLength(PeripheralBase) ( \ + 512 << (uint8)(( \ + (uint32)(SDHC_HTCAPBLT_REG(PeripheralBase) & SDHC_HTCAPBLT_MBL_MASK)) >> ( \ + SDHC_HTCAPBLT_MBL_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWriteWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the watermark level in DMA write operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Write watermark level (from 1 to 128). Number of 4-byte + * words of watermark level in DMA write operation. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_WML. + * @par Example: + * @code + * SDHC_PDD_SetWriteWatermark(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetWriteWatermark(PeripheralBase, Watermark) ( \ + SDHC_WML_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_WML_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_WML_WRWML_MASK))) | ( \ + (uint32)((uint32)(Watermark) << SDHC_WML_WRWML_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReadWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the watermark level in DMA read operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Read watermark level (from 1 to 128). Number of 4-byte words + * of watermark level in DMA read operation. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_WML. + * @par Example: + * @code + * SDHC_PDD_SetReadWatermark(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetReadWatermark(PeripheralBase, Watermark) ( \ + SDHC_WML_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_WML_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_WML_RDWML_MASK))) | ( \ + (uint32)(Watermark))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceEvents + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces events specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Event mask. Use constants from group "Force event masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_FEVT. + * @par Example: + * @code + * SDHC_PDD_ForceEvents(_BASE_PTR, + * SDHC_PDD_AUTO_CMD12_NOT_EXECUTED_EVENT); + * @endcode + */ +#define SDHC_PDD_ForceEvents(PeripheralBase, Mask) ( \ + SDHC_FEVT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_FEVT_REG(PeripheralBase) | (uint32)(Mask))) & (( \ + (uint32)(~(uint32)0x60U)) & (( \ + (uint32)(~(uint32)0xFF00U)) & (( \ + (uint32)(~(uint32)0x800000U)) & (( \ + (uint32)(~(uint32)0xE000000U)) & ( \ + (uint32)(~(uint32)0x60000000U))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMALengthMismatchErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA length mismatch error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetADMALengthMismatchErrorFlag(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMALengthMismatchErrorFlag(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMALME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMADescriptorErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA descriptor error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetADMADescriptorErrorFlag(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMADescriptorErrorFlag(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMADCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMAErrorState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA error state. The return value can be compared with + * predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "ADMA error states" type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetADMAErrorState(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMAErrorState(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMAES_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetADMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the ADMA system address containing the physical system memory + * address used for ADMA transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address ADMA system address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_ADSADDR. + * @par Example: + * @code + * SDHC_PDD_SetADMAAddress(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetADMAAddress(PeripheralBase, Address) ( \ + SDHC_ADSADDR_REG(PeripheralBase) = \ + (uint32)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA system address containing the address of the + * executing command of the descriptor table. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADSADDR. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetADMAAddress(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMAAddress(PeripheralBase) ( \ + SDHC_ADSADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExternalDMARequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the external DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_VENDOR. + * @par Example: + * @code + * SDHC_PDD_EnableExternalDMARequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableExternalDMARequest(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_VENDOR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_VENDOR_EXTDMAEN_MASK)) : ( \ + SDHC_VENDOR_REG(PeripheralBase) |= \ + SDHC_VENDOR_EXTDMAEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExactBlockNum + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables exact block number for SDIO CMD53. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_VENDOR. + * @par Example: + * @code + * SDHC_PDD_EnableExactBlockNum(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableExactBlockNum(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_VENDOR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_VENDOR_EXBLKNU_MASK)) : ( \ + SDHC_VENDOR_REG(PeripheralBase) |= \ + SDHC_VENDOR_EXBLKNU_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootAckTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the boot acknowled timeout counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Timeout Boot ack timeout counter value (from 0 to 14). Specifies the + * timeout value as 2^(8 + Timeout) SD clock cycles. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootAckTimeout(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBootAckTimeout(PeripheralBase, Timeout) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_DTOCVACK_MASK)))) | ( \ + (uint32)(Timeout))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBootAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables boot acknowledge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableBootAck(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableBootAck(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTACK_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_BOOTACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the boot mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Boot mode. This parameter is of "MMC boot modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootMode(_BASE_PTR, SDHC_PDD_NORMAL_BOOT); + * @endcode + */ +#define SDHC_PDD_SetBootMode(PeripheralBase, Mode) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBootMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the boot mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableBootMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableBootMode(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTEN_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_BOOTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAutoStopAtBlockGap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables auto stop at block gap function when boot. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableAutoStopAtBlockGap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableAutoStopAtBlockGap(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_AUTOSABGEN_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_AUTOSABGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the received boot block count after which 'stop at block gap' + * occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Boot block count. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootBlockCount(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBootBlockCount(PeripheralBase, Count) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTBLKCNT_MASK)))) | ( \ + (uint32)((uint32)(Count) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSpecificationVersion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the specification version number. The return value can be + * compared with predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Specification version numbers" type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SDHC_HOSTVER. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetSpecificationVersion(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetSpecificationVersion(PeripheralBase) ( \ + (uint32)(SDHC_HOSTVER_REG(PeripheralBase) & SDHC_HOSTVER_SVN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVendorVersion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the vendor version number. The return value can be compared + * with predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Vendor version numbers" type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: SDHC_HOSTVER. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetVendorVersion(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetVendorVersion(PeripheralBase) ( \ + (uint32)(SDHC_HOSTVER_REG(PeripheralBase) & SDHC_HOSTVER_VVN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Use constants from group "Clock sources". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * SDHC_PDD_SetClockSource(_BASE_PTR, + * SDHC_PDD_CORE_SYSTEM_CLOCK); + * @endcode + */ + #define SDHC_PDD_SetClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(SIM_BASE_PTR) = \ + (( \ + (uint32)(SIM_SOPT2_REG(SIM_BASE_PTR) & (uint32)(~(uint32)SIM_SOPT2_ESDHCSRC_MASK))) | ( \ + (uint32)((uint32)(Source) << SIM_SOPT2_ESDHCSRC_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) */ +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Use constants from group "Clock sources". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * SDHC_PDD_SetClockSource(_BASE_PTR, + * SDHC_PDD_CORE_SYSTEM_CLOCK); + * @endcode + */ + #define SDHC_PDD_SetClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(SIM_BASE_PTR) = \ + (( \ + (uint32)(SIM_SOPT2_REG(SIM_BASE_PTR) & (uint32)(~(uint32)SIM_SOPT2_SDHCSRC_MASK))) | ( \ + (uint32)((uint32)(Source) << SIM_SOPT2_SDHCSRC_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) */ +#endif /* #if defined(SDHC_PDD_H_) */ + +/* SDHC_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h new file mode 100644 index 0000000..d7365e3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h @@ -0,0 +1,6806 @@ +/* + PDD layer implementation for peripheral type SIM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SIM_PDD_H_) +#define SIM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SIM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SIM */ && \ + !defined(MCU_MK10D5) /* SIM */ && \ + !defined(MCU_MK10D7) /* SIM */ && \ + !defined(MCU_MK10F12) /* SIM */ && \ + !defined(MCU_MK10DZ10) /* SIM */ && \ + !defined(MCU_MK11D5) /* SIM */ && \ + !defined(MCU_MK11D5WS) /* SIM */ && \ + !defined(MCU_MK12D5) /* SIM */ && \ + !defined(MCU_MK20D10) /* SIM */ && \ + !defined(MCU_MK20D5) /* SIM */ && \ + !defined(MCU_MK20D7) /* SIM */ && \ + !defined(MCU_MK20F12) /* SIM */ && \ + !defined(MCU_MK20DZ10) /* SIM */ && \ + !defined(MCU_MK21D5) /* SIM */ && \ + !defined(MCU_MK21D5WS) /* SIM */ && \ + !defined(MCU_MK21F12) /* SIM */ && \ + !defined(MCU_MK21F12WS) /* SIM */ && \ + !defined(MCU_MK22D5) /* SIM */ && \ + !defined(MCU_MK22F12810) /* SIM */ && \ + !defined(MCU_MK22F12) /* SIM */ && \ + !defined(MCU_MK22F25612) /* SIM */ && \ + !defined(MCU_MK22F51212) /* SIM */ && \ + !defined(MCU_MK24F12) /* SIM */ && \ + !defined(MCU_MK30D10) /* SIM */ && \ + !defined(MCU_MK30D7) /* SIM */ && \ + !defined(MCU_MK30DZ10) /* SIM */ && \ + !defined(MCU_MK40D10) /* SIM */ && \ + !defined(MCU_MK40D7) /* SIM */ && \ + !defined(MCU_MK40DZ10) /* SIM */ && \ + !defined(MCU_MK40X256VMD100) /* SIM */ && \ + !defined(MCU_MK50D10) /* SIM */ && \ + !defined(MCU_MK50D7) /* SIM */ && \ + !defined(MCU_MK50DZ10) /* SIM */ && \ + !defined(MCU_MK51D10) /* SIM */ && \ + !defined(MCU_MK51D7) /* SIM */ && \ + !defined(MCU_MK51DZ10) /* SIM */ && \ + !defined(MCU_MK52D10) /* SIM */ && \ + !defined(MCU_MK52DZ10) /* SIM */ && \ + !defined(MCU_MK53D10) /* SIM */ && \ + !defined(MCU_MK53DZ10) /* SIM */ && \ + !defined(MCU_MK60D10) /* SIM */ && \ + !defined(MCU_MK60F12) /* SIM */ && \ + !defined(MCU_MK60F15) /* SIM */ && \ + !defined(MCU_MK60DZ10) /* SIM */ && \ + !defined(MCU_MK60N512VMD100) /* SIM */ && \ + !defined(MCU_MK61F12) /* SIM */ && \ + !defined(MCU_MK61F15) /* SIM */ && \ + !defined(MCU_MK61F12WS) /* SIM */ && \ + !defined(MCU_MK61F15WS) /* SIM */ && \ + !defined(MCU_MK63F12) /* SIM */ && \ + !defined(MCU_MK63F12WS) /* SIM */ && \ + !defined(MCU_MK64F12) /* SIM */ && \ + !defined(MCU_MK65F18) /* SIM */ && \ + !defined(MCU_MK65F18WS) /* SIM */ && \ + !defined(MCU_MK66F18) /* SIM */ && \ + !defined(MCU_MK70F12) /* SIM */ && \ + !defined(MCU_MK70F15) /* SIM */ && \ + !defined(MCU_MK70F12WS) /* SIM */ && \ + !defined(MCU_MK70F15WS) /* SIM */ && \ + !defined(MCU_MKE02Z2) /* SIM */ && \ + !defined(MCU_MKE02Z4) /* SIM */ && \ + !defined(MCU_SKEAZN642) /* SIM */ && \ + !defined(MCU_MKE04Z1284) /* SIM */ && \ + !defined(MCU_MKE04Z4) /* SIM */ && \ + !defined(MCU_SKEAZN84) /* SIM */ && \ + !defined(MCU_MKE06Z4) /* SIM */ && \ + !defined(MCU_MKL02Z4) /* SIM */ && \ + !defined(MCU_MKL03Z4) /* SIM */ && \ + !defined(MCU_MKL04Z4) /* SIM */ && \ + !defined(MCU_MKL05Z4) /* SIM */ && \ + !defined(MCU_MKL14Z4) /* SIM */ && \ + !defined(MCU_MKL15Z4) /* SIM */ && \ + !defined(MCU_MKL16Z4) /* SIM */ && \ + !defined(MCU_MKL24Z4) /* SIM */ && \ + !defined(MCU_MKL25Z4) /* SIM */ && \ + !defined(MCU_MKL26Z4) /* SIM */ && \ + !defined(MCU_MKL34Z4) /* SIM */ && \ + !defined(MCU_MKL36Z4) /* SIM */ && \ + !defined(MCU_MKL46Z4) /* SIM */ && \ + !defined(MCU_MKV10Z7) /* SIM */ && \ + !defined(MCU_MKV31F12810) /* SIM */ && \ + !defined(MCU_MKV31F25612) /* SIM */ && \ + !defined(MCU_MKV31F51212) /* SIM */ && \ + !defined(MCU_MKW21D5) /* SIM */ && \ + !defined(MCU_MKW21D5WS) /* SIM */ && \ + !defined(MCU_MKW22D5) /* SIM */ && \ + !defined(MCU_MKW22D5WS) /* SIM */ && \ + !defined(MCU_MKW24D5) /* SIM */ && \ + !defined(MCU_MKW24D5WS) /* SIM */ && \ + !defined(MCU_PCK20L4) /* SIM */ && \ + !defined(MCU_SKEAZ1284) /* SIM */ + // Unsupported MCU is active + #error SIM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MK10D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK10D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK10D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK10DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK10F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK11D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK11D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK12D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + +#elif (defined(MCU_MK20D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK20D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK20DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK20F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK21D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK21D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK21F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK21F12WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK22D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + +#elif (defined(MCU_MK22F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK22F12810)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK22F25612)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK22F51212)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0xA6U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0xA8U /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK24F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK30D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK30D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK30DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK40DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40X256VMD100)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK50D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + +#elif (defined(MCU_MK50D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK50DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + +#elif (defined(MCU_MK51D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK51D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK51DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK52D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK52DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK53D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK53DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK60D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK60DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK60N512VMD100)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK63F12WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK65F18WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_I2C3 0x7U /**< Clock gate identifier for I2C3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x24U /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0x29U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0x2AU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_USBHS 0x41U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBPHY 0x42U /**< Clock gate identifier for USBPHY */ + #define SIM_PDD_CLOCK_GATE_USBHSDCD 0x43U /**< Clock gate identifier for USBHSDCD */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDRAM 0xC3U /**< Clock gate identifier for Synchronous DRAM controller */ + +#elif (defined(MCU_MKE04Z1284)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x10U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C1) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif (defined(MCU_MKL02Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + +#elif (defined(MCU_MKL03Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x94U /**< Clock gate identifier for LPUART0 */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + +#elif (defined(MCU_MKL04Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL05Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL14Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL15Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL16Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL24Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL25Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL26Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL34Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL36Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL46Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV10Z7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xBCU /**< Clock gate identifier for Analog-to-Digital Converter 1 */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + +#elif (defined(MCU_MKV31F12810)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV31F25612)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV31F51212)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0xA6U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0xA8U /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKW21D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif (defined(MCU_MKW21D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif ((defined(MCU_MK20D5)) || (defined(MCU_PCK20L4))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif ((defined(MCU_MK60F12)) || (defined(MCU_MK60F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MK61F12)) || (defined(MCU_MK61F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK63F12)) || (defined(MCU_MK64F12))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK66F18))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_I2C3 0x7U /**< Clock gate identifier for I2C3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x24U /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0x29U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0x2AU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_USBHS 0x41U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBPHY 0x42U /**< Clock gate identifier for USBPHY */ + #define SIM_PDD_CLOCK_GATE_USBHSDCD 0x43U /**< Clock gate identifier for USBHSDCD */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDRAM 0xC3U /**< Clock gate identifier for Synchronous DRAM controller */ + +#elif ((defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_LCDC 0x56U /**< Clock gate identifier for Graphical LCD controller */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_LCDC 0x56U /**< Clock gate identifier for Graphical LCD controller */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif ((defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_MSCAN 0xFU /**< Clock gate identifier for Modular Scalable Controller Area Network (MSCAN) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x10U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C1) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif ((defined(MCU_MKW22D5)) || (defined(MCU_MKW24D5))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB Device Charger Detection Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif ((defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB Device Charger Detection Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642)) */ +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRH 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRH) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642)) */ +/* Clock 1 output divider constants */ +#define SIM_PDD_CLK_OUT1_DIVIDER_1 0U /**< Divide by 1 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_2 0x1U /**< Divide by 2 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_3 0x2U /**< Divide by 3 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_4 0x3U /**< Divide by 4 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_5 0x4U /**< Divide by 5 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_6 0x5U /**< Divide by 6 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_7 0x6U /**< Divide by 7 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_8 0x7U /**< Divide by 8 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_9 0x8U /**< Divide by 9 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_10 0x9U /**< Divide by 10 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_11 0xAU /**< Divide by 11 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_12 0xBU /**< Divide by 12 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_13 0xCU /**< Divide by 13 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_14 0xDU /**< Divide by 14 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_15 0xEU /**< Divide by 15 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_16 0xFU /**< Divide by 16 */ + +#if ((defined(MCU_MKL03Z4)) || (defined(MCU_MKV10Z7))) +/* Clock 4 output divider constants */ + #define SIM_PDD_CLK_OUT4_DIVIDER_1 0U /**< Divide by 1 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_2 0x1U /**< Divide by 2 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_3 0x2U /**< Divide by 3 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_4 0x3U /**< Divide by 4 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_5 0x4U /**< Divide by 5 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_6 0x5U /**< Divide by 6 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_7 0x6U /**< Divide by 7 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_8 0x7U /**< Divide by 8 */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Clock 4 output divider constants */ + #define SIM_PDD_CLK_OUT4_DIVIDER_1 0U /**< Divide by 1 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_2 0x1U /**< Divide by 2 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_3 0x2U /**< Divide by 3 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_4 0x3U /**< Divide by 4 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_5 0x4U /**< Divide by 5 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_6 0x5U /**< Divide by 6 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_7 0x6U /**< Divide by 7 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_8 0x7U /**< Divide by 8 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_9 0x8U /**< Divide by 9 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_10 0x9U /**< Divide by 10 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_11 0xAU /**< Divide by 11 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_12 0xBU /**< Divide by 12 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_13 0xCU /**< Divide by 13 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_14 0xDU /**< Divide by 14 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_15 0xEU /**< Divide by 15 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_16 0xFU /**< Divide by 16 */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Clock 5 output divider constants */ +#define SIM_PDD_CLK_OUT5_DIVIDER_1 0U /**< Divide by 1 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_2 0x1U /**< Divide by 2 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_3 0x2U /**< Divide by 3 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_4 0x3U /**< Divide by 4 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_5 0x4U /**< Divide by 5 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_6 0x5U /**< Divide by 6 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_7 0x6U /**< Divide by 7 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_8 0x7U /**< Divide by 8 */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4))) +/* Clock sources */ + #define SIM_PDD_UART0_DISABLE_CLOCK 0U /**< Disable the clock. */ + #define SIM_PDD_UART0_FLL_CLOCK 0x4000000U /**< MCG FLL clock. */ + #define SIM_PDD_UART0_EXTERNAL_REF_CLOCK 0x8000000U /**< External reference clock. */ + #define SIM_PDD_UART0_INTERNAL_REF_CLOCK 0xC000000U /**< Internal reference clock. */ + +#else /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/* Clock sources */ + #define SIM_PDD_UART0_DISABLE_CLOCK 0U /**< Disable the clock. */ + #define SIM_PDD_UART0_PLL_FLL_CLOCK 0x4000000U /**< MCG PLL or FLL clock. */ + #define SIM_PDD_UART0_EXTERNAL_REF_CLOCK 0x8000000U /**< External reference clock. */ + #define SIM_PDD_UART0_INTERNAL_REF_CLOCK 0xC000000U /**< Internal reference clock. */ + +#endif /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/* Clock sources */ +#define SIM_PDD_LPUART1_DISABLE_CLOCK 0U /**< Disable the clock. */ +#define SIM_PDD_LPUART1_FAST_INTERNAL_REF_CLOCK 0x10000000U /**< Fast internal reference clock. */ +#define SIM_PDD_LPUART1_EXTERNAL_REF_CLOCK 0x20000000U /**< External reference clock. */ +#define SIM_PDD_LPUART1_SLOW_INTERNAL_REF_CLOCK 0x30000000U /**< Slow internal reference clock. */ + +/* 32 kHz clock source constants */ +#define SIM_PDD_LPTMR_SYSTEM_OSCILLATOR 0U /**< System oscillator (OSC32KCLK) */ +#define SIM_PDD_LPTMR_LOW_POWER_OSCILLATOR 0xC0000U /**< Low power oscillator 1kHz (LPO) */ + +/* Clock for FTMx constants */ +#define SIM_PDD_FTM_FIXED_FREQUENCY 0U /**< Fixed frequency clock (MCGFFCLK) */ +#define SIM_PDD_FTM_INTERNAL_REFERENCE 0x1000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_FTM_SYSTEM_OSCILLATOR 0x2000000U /**< System oscillator clock (OSCERCLK) */ + +/* Clock to output on the CLKOUT pin constants */ +#define SIM_PDD_CLKOUT_BUS_CLOCK 0x40U /**< Bus clock */ +#define SIM_PDD_CLKOUT_LOW_POWER_OSCILLATOR 0x60U /**< Low power oscillator 1kHz (LPO) */ +#define SIM_PDD_CLKOUT_INTERNAL_REFERENCE 0x80U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_CLKOUT_SYSTEM_OSCILLATOR 0xC0U /**< System oscillator clock (OSCERCLK) */ + +#if (defined(MCU_MKV10Z7)) +/* FTM2 external clock pin constants */ + #define SIM_PDD_FTM2_CLKIN0_PIN 0U /**< FTM2 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM2_CLKIN1_PIN 0x10000000U /**< FTM2 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM2_CLKIN2_PIN 0x20000000U /**< FTM2 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM2 external clock pin constants */ + #define SIM_PDD_FTM2_CLKIN0_PIN 0U /**< FTM2 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM2_CLKIN1_PIN 0x4000000U /**< FTM2 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* FTM1 external clock pin constants */ + #define SIM_PDD_FTM1_CLKIN0_PIN 0U /**< FTM1 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM1_CLKIN1_PIN 0x4000000U /**< FTM1 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM1_CLKIN2_PIN 0x8000000U /**< FTM1 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM1 external clock pin constants */ + #define SIM_PDD_FTM1_CLKIN0_PIN 0U /**< FTM1 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM1_CLKIN1_PIN 0x2000000U /**< FTM1 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* FTM0 external clock pin constants */ + #define SIM_PDD_FTM0_CLKIN0_PIN 0U /**< FTM0 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM0_CLKIN1_PIN 0x1000000U /**< FTM0 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM0_CLKIN2_PIN 0x2000000U /**< FTM0 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM0 external clock pin constants */ + #define SIM_PDD_FTM0_CLKIN0_PIN 0U /**< FTM0 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM0_CLKIN1_PIN 0x1000000U /**< FTM0 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM2 channel 1 input capture source constants */ +#define SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1 0U /**< FTM2_CH1 pin is fed to FTM2 CH1 */ +#define SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1_XOR_FTM2_CH0_XOR_FTM1_CH1 0x400000U /**< FTM2_CH1 pin XOR FTM2_CH0 pin XOR FTM1_CH1 pin is fed to FTM2 CH1 */ + +/* FTM2 channel 0 input capture source constants */ +#define SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0 0U /**< FTM2_CH0 signal */ +#define SIM_PDD_FTM2_CH0_INPUT_CMP0 0x100000U /**< CMP0 output */ +#define SIM_PDD_FTM2_CH0_INPUT_CMP1 0x200000U /**< CMP1 output */ + +/* FTM1 channel 0 input capture source constants */ +#define SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0 0U /**< FTM1_CH0 signal */ +#define SIM_PDD_FTM1_CH0_INPUT_CMP0 0x40000U /**< CMP0 output */ +#define SIM_PDD_FTM1_CH0_INPUT_CMP1 0x80000U /**< CMP1 output */ + +/* Source of FTM2 hardware trigger 2 constants */ +#define SIM_PDD_FTM2_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM2_TRIGGER2_CMP1_OUTPUT 0x8000U /**< CMP1 output */ + +/* Source of FTM2 hardware trigger 1 constants */ +#define SIM_PDD_FTM2_TRIGGER1_PDB_TRIGGER1 0U /**< PDB output trigger 1 */ +#define SIM_PDD_FTM2_TRIGGER1_FTM1_MATCH 0x4000U /**< FTM1 channel match */ + +/* Source of FTM2 hardware trigger 0 constants */ +#define SIM_PDD_FTM2_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM2_TRIGGER0_FTM0_MATCH 0x2000U /**< FTM0 channel match */ + +/* Source of FTM1 hardware trigger 2 constants */ +#define SIM_PDD_FTM1_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM1_TRIGGER2_CMP1_OUTPUT 0x1000U /**< CMP1 output */ + +/* Source of FTM1 hardware trigger 1 constants */ +#define SIM_PDD_FTM1_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ +#define SIM_PDD_FTM1_TRIGGER1_FTM2_MATCH 0x800U /**< FTM2 channel match */ + +/* Source of FTM1 hardware trigger 0 constants */ +#define SIM_PDD_FTM1_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM1_TRIGGER0_FTM0_MATCH 0x400U /**< FTM0 channel match */ + +/* Source of FTM0 hardware trigger 2 constants */ +#define SIM_PDD_FTM0_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM0_TRIGGER2_CMP1_OUTPUT 0x200U /**< CMP1 output */ + +#if (defined(MCU_MKV10Z7)) +/* Source of FTM0 hardware trigger 1 constants */ + #define SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ + #define SIM_PDD_FTM0_TRIGGER1_FTM2_MATCH 0x100U /**< FTM2 channel match */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 hardware trigger 1 constants */ + #define SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ + #define SIM_PDD_FTM0_TRIGGER1_FTM2_MATCH 0x20000000U /**< FTM2 channel match */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM0 hardware trigger 0 constants */ + #define SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ + #define SIM_PDD_FTM0_TRIGGER0_FTM1_MATCH 0x80U /**< FTM1 channel match */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 hardware trigger 0 constants */ + #define SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ + #define SIM_PDD_FTM0_TRIGGER0_FTM1_MATCH 0x10000000U /**< FTM1 channel match */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM2 fault 0 constants */ + #define SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN 0U /**< FTM2_FLT0 pin */ + #define SIM_PDD_FTM2_FAULT0_CMP0_OUTPUT 0x8U /**< CMP0 output */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM2 fault 0 constants */ + #define SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN 0U /**< FTM2_FLT0 pin */ + #define SIM_PDD_FTM2_FAULT0_CMP0_OUTPUT 0x100U /**< CMP0 output */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM1 fault 0 constants */ + #define SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN 0U /**< FTM1_FLT0 pin */ + #define SIM_PDD_FTM1_FAULT0_CMP0_OUTPUT 0x4U /**< CMP0 output */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM1 fault 0 constants */ + #define SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN 0U /**< FTM1_FLT0 pin */ + #define SIM_PDD_FTM1_FAULT0_CMP0_OUTPUT 0x10U /**< CMP0 output */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 fault 1 constants */ +#define SIM_PDD_FTM0_FAULT1_FTM0_FLT1_PIN 0U /**< FTM0_FLT1 pin */ +#define SIM_PDD_FTM0_FAULT1_CMP1_OUTPUT 0x2U /**< CMP1 output */ + +/* Source of FTM0 fault 0 constants */ +#define SIM_PDD_FTM0_FAULT0_FTM0_FLT0_PIN 0U /**< FTM0_FLT0 pin */ +#define SIM_PDD_FTM0_FAULT0_CMP1_OUTPUT 0x1U /**< CMP1 output */ + +/* Source of UART 1 RxD constants */ +#define SIM_PDD_UART1_RX_PIN 0U /**< UART1_RX pin */ +#define SIM_PDD_UART1_CMP0_OUTPUT 0x40U /**< CMP0 output */ +#define SIM_PDD_UART1_CMP1_OUTPUT 0x80U /**< CMP1 output */ + +/* Source of UART 1 TxD constants */ +#define SIM_PDD_UART1_TX_PIN 0U /**< UART1_TX pin */ +#define SIM_PDD_UART1_TX_PIN_MUDULATED_FTM1_CHANNEL0 0x10U /**< UART1 Tx pin modulated with FTM1 channel 0 output */ +#define SIM_PDD_UART1_TX_PIN_MUDULATED_FTM2_CHANNEL0 0x20U /**< UART1 Tx pin modulated with FTM2 channel 0 output */ + +/* Source of UART 0 RxD constants */ +#define SIM_PDD_UART0_RX_PIN 0U /**< UART1_RX pin */ +#define SIM_PDD_UART0_CMP0_OUTPUT 0x4U /**< CMP0 output */ +#define SIM_PDD_UART0_CMP1_OUTPUT 0x8U /**< CMP1 output */ + +/* Source of UART 0 TxD constants */ +#define SIM_PDD_UART0_TX_PIN 0U /**< UART1_TX pin */ +#define SIM_PDD_UART0_TX_PIN_MUDULATED_FTM1_CHANNEL0 0x10U /**< UART1 Tx pin modulated with FTM1 channel 0 output */ +#define SIM_PDD_UART0_TX_PIN_MUDULATED_FTM2_CHANNEL0 0x20U /**< UART1 Tx pin modulated with FTM2 channel 0 output */ + +/* ADC1 alternate clock source constants */ +#define SIM_PDD_ADC1_ALT_CLK_CORE_CLK_DIV_5 0U /**< Core frequency divided by 5 (OUTDIV5) */ +#define SIM_PDD_ADC1_ALT_CLK_INTERNAL_REFERENCE 0x4000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_ADC1_ALT_CLK_SYSTEM_OSCILLATOR 0x8000000U /**< System oscillator clock (OSCERCLK) */ + +/* ADC0 alternate clock source constants */ +#define SIM_PDD_ADC0_ALT_CLK_CORE_CLK_DIV_5 0U /**< Core frequency divided by 5 (OUTDIV5) */ +#define SIM_PDD_ADC0_ALT_CLK_INTERNAL_REFERENCE 0x1000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_ADC0_ALT_CLK_SYSTEM_OSCILLATOR 0x2000000U /**< System oscillator clock (OSCERCLK) */ + +/* ADC1 pre-trigger source constants */ +#define SIM_PDD_ADC1_PRE_TRIGGER_A 0U /**< Pre-trigger A */ +#define SIM_PDD_ADC1_PRE_TRIGGER_B 0x1000U /**< Pre-trigger B */ + +/* ADC1 trigger source constants */ +#define SIM_PDD_ADC1_TRIGGER_EXTERNAL_PIN 0U /**< External trigger pin input (PDB0_EXTRG) */ +#define SIM_PDD_ADC1_TRIGGER_CMP0_OUTPUT 0x100U /**< HSCMP0 output */ +#define SIM_PDD_ADC1_TRIGGER_CMP1_OUTPUT 0x200U /**< HSCMP1 output */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL0_COMPLETE 0x400U /**< DMA channel 0 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL1_COMPLETE 0x500U /**< DMA channel 1 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL2_COMPLETE 0x600U /**< DMA channel 2 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL3_COMPLETE 0x700U /**< DMA channel 3 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_FTM0_OVERFLOW 0x800U /**< FTM0 overflow */ +#define SIM_PDD_ADC1_TRIGGER_FTM1_OVERFLOW 0x900U /**< FTM1 overflow */ +#define SIM_PDD_ADC1_TRIGGER_FTM2_OVERFLOW 0xA00U /**< FTM2 overflow */ +#define SIM_PDD_ADC1_TRIGGER_LOW_POWER_TIMER0 0xE00U /**< LPTMR0 trigger */ + +/* ADC0 pre-trigger source constants */ +#define SIM_PDD_ADC0_PRE_TRIGGER_A 0U /**< Pre-trigger A */ +#define SIM_PDD_ADC0_PRE_TRIGGER_B 0x10U /**< Pre-trigger B */ + +/* ADC0 trigger source constants */ +#define SIM_PDD_ADC0_TRIGGER_EXTERNAL_PIN 0U /**< External trigger pin input (PDB0_EXTRG) */ +#define SIM_PDD_ADC0_TRIGGER_CMP0_OUTPUT 0x1U /**< HSCMP0 output */ +#define SIM_PDD_ADC0_TRIGGER_CMP1_OUTPUT 0x2U /**< HSCMP1 output */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL0_COMPLETE 0x4U /**< DMA channel 0 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL1_COMPLETE 0x5U /**< DMA channel 1 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL2_COMPLETE 0x6U /**< DMA channel 2 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL3_COMPLETE 0x7U /**< DMA channel 3 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_FTM0_OVERFLOW 0x8U /**< FTM0 overflow */ +#define SIM_PDD_ADC0_TRIGGER_FTM1_OVERFLOW 0x9U /**< FTM1 overflow */ +#define SIM_PDD_ADC0_TRIGGER_FTM2_OVERFLOW 0xAU /**< FTM2 overflow */ +#define SIM_PDD_ADC0_TRIGGER_LOW_POWER_TIMER0 0xEU /**< LPTMR0 trigger */ + +#if (defined(MCU_MKV10Z7)) +/* V-family ID constant. */ + #define SIM_PDD_V_FAMILY_ID_MKV10ZX 0x10000000U /**< MKV10Zx V-family device ID */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* V-family ID constant. */ + #define SIM_PDD_V_FAMILY_ID_MKW24ZX 0x10U /**< MKW24Zx W-family device ID */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Sub-family ID constant. */ +#define SIM_PDD_SUB_FAMILY_ID_MKV10XXXX 0U /**< MKV10xxxx sub-family device ID */ + +/* Series ID constant. */ +#define SIM_PDD_SERIES_ID_V_FAMILY_MOTOR_CONTROL 0x600000U /**< V-family - motor control series ID */ + +/* System SRAM size constant. */ +#define SIM_PDD_SYSTEM_SRAM_512B 0U /**< System SRAM size is 512B */ +#define SIM_PDD_SYSTEM_SRAM_1KB 0x10000U /**< System SRAM size is 1kB */ +#define SIM_PDD_SYSTEM_SRAM_2KB 0x20000U /**< System SRAM size is 2kB */ +#define SIM_PDD_SYSTEM_SRAM_4KB 0x30000U /**< System SRAM size is 4kB */ +#define SIM_PDD_SYSTEM_SRAM_8KB 0x40000U /**< System SRAM size is 8kB */ +#define SIM_PDD_SYSTEM_SRAM_16KB 0x50000U /**< System SRAM size is 16kB */ +#define SIM_PDD_SYSTEM_SRAM_32KB 0x60000U /**< System SRAM size is 32kB */ +#define SIM_PDD_SYSTEM_SRAM_64KB 0x70000U /**< System SRAM size is 64kB */ + +/* Pincount indetification constant. */ +#define SIM_PDD_PINCOUNT_ID_32 0x2U /**< 32 pincount */ +#define SIM_PDD_PINCOUNT_ID_48 0x4U /**< 48 pincount */ +#define SIM_PDD_PINCOUNT_ID_64 0x5U /**< 64 pincount */ +#define SIM_PDD_PINCOUNT_ID_80 0x6U /**< 80 pincount */ +#define SIM_PDD_PINCOUNT_ID_81 0x7U /**< 81 pincount */ +#define SIM_PDD_PINCOUNT_ID_100 0x8U /**< 100 pincount */ +#define SIM_PDD_PINCOUNT_ID_121 0x9U /**< 121 pincount */ +#define SIM_PDD_PINCOUNT_ID_144 0xAU /**< 144 pincount */ +#define SIM_PDD_PINCOUNT_ID_196 0xCU /**< 196 pincount */ +#define SIM_PDD_PINCOUNT_ID_256 0xEU /**< 256 pincount */ + +/* Program flash size constants. */ +#define SIM_PDD_PROGRAM_FLASH_8KB_PROTECTION_256B 0U /**< 8 KB of program flash memory, 0.25 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_16KB_PROTECTION_512B 0x1000000U /**< 16 KB of program flash memory, 0.5 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_32KB_PROTECTION_1KB 0x3000000U /**< 32 KB of program flash memory, 1 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_64KB_PROTECTION_2KB 0x5000000U /**< 64 KB of program flash memory, 2 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_128KB_PROTECTION_4KB 0x7000000U /**< 128 KB of program flash memory, 4 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_256KB_PROTECTION_4KB 0x9000000U /**< 256 KB of program flash memory, 4 KB protection region */ + +/* Watchdog clock source constants */ +#define SIM_PDD_WDOG_INTERNAL_1KHZ 0U /**< Internal 1 kHz clock is source to watchdog */ +#define SIM_PDD_WDOG_INTERNAL_REFERENCE 0x2U /**< Internal reference clock (MCGIRCLK) is source to watchdog */ + + +/* ---------------------------------------------------------------------------- + -- SetClockGate + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + ) \ + ) +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + SIM_SCGC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU)))) \ + ) +#elif ((defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x5U) ? ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + )) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0U) ? ( \ + SIM_SCGC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x1U) ? ( \ + SIM_SCGC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x2U) ? ( \ + SIM_SCGC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC3_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x5U) ? ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + ))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemResetStatusIDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system reset status and ID register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SRSID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemResetStatusIDReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemResetStatusIDReg(PeripheralBase) ( \ + SIM_SRSID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption0Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Writes new value specified by the Value parameter into system options + * 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WriteSystemOption0Reg(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_WriteSystemOption0Reg(PeripheralBase, Value) ( \ + SIM_SOPT0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into system options + * 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WriteSystemOption0Reg(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_WriteSystemOption0Reg(PeripheralBase, Value) ( \ + SIM_SOPT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption0Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Reads system options 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption0Reg(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_ReadSystemOption0Reg(PeripheralBase) ( \ + SIM_SOPT0_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads system options 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption0Reg(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_ReadSystemOption0Reg(PeripheralBase) ( \ + SIM_SOPT_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WritePinSelection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into pin selection 0 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the pin selection 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_PINSEL, SIM_PINSEL0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WritePinSelection0Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WritePinSelection0Reg(PeripheralBase, Value) ( \ + SIM_PINSEL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniversallyUniqueIdentifierLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads Universally Unique Identifier Low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UUIDL. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniversallyUniqueIdentifierLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniversallyUniqueIdentifierLowReg(PeripheralBase) ( \ + SIM_UUIDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTriggerDelay + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Set ADC HW trigger delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Delay Parameter specifying the requested ADC HW trigger delay. Value + * should be in range from 0 to 255. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetTriggerDelay(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetTriggerDelay(PeripheralBase, Delay) ( \ + SIM_SOPT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT0_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT0_DELAY_MASK))) | ( \ + (uint32)((uint32)(Delay) << SIM_SOPT0_DELAY_SHIFT))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Set ADC HW trigger delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Delay Parameter specifying the requested ADC HW trigger delay. Value + * should be in range from 0 to 255. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetTriggerDelay(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetTriggerDelay(PeripheralBase, Delay) ( \ + SIM_SOPT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT_DELAY_MASK))) | ( \ + (uint32)((uint32)(Delay) << SIM_SOPT_DELAY_SHIFT))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption1Reg(PeripheralBase, Value) ( \ + SIM_SOPT1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption1Reg(PeripheralBase) ( \ + SIM_SOPT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePinSelection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into pin selection 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the pin selection 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_PINSEL1. + * @par Example: + * @code + * SIM_PDD_WritePinSelection1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WritePinSelection1Reg(PeripheralBase, Value) ( \ + SIM_PINSEL1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPinSelection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads pin selection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_PINSEL1. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadPinSelection1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadPinSelection1Reg(PeripheralBase) ( \ + SIM_PINSEL1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniversallyUniqueIdentifierMidHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads Universally Unique Identifier Middle High register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UUIDMH. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniversallyUniqueIdentifierMidHighReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniversallyUniqueIdentifierMidHighReg(PeripheralBase) ( \ + SIM_UUIDMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock divider register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockDividerReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockDividerReg(PeripheralBase, Value) ( \ + SIM_CLKDIV_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_CLKDIV. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockDividerReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockDividerReg(PeripheralBase) ( \ + SIM_CLKDIV_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSourceUART0 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4))) +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, FLL_CLOCK, + * EXTERNAL_REF_CLOCK, INTERNAL_REF_CLOCK. This parameter is of "Clock sources" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceUART0(_BASE_PTR, + * SIM_PDD_UART0_DISABLE_CLOCK); + * @endcode + */ + #define SIM_PDD_SetClockSourceUART0(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT2_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT2_UART0SRC_MASK))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, PLL_FLL_CLOCK, + * EXTERNAL_REF_CLOCK, INTERNAL_REF_CLOCK. This parameter is of "Clock + * sources" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceUART0(_BASE_PTR, + * SIM_PDD_UART0_DISABLE_CLOCK); + * @endcode + */ + #define SIM_PDD_SetClockSourceUART0(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT2_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT2_UART0SRC_MASK))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption2Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption2Reg(PeripheralBase) ( \ + SIM_SOPT2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 2 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption2Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption2Reg(PeripheralBase, Value) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption4Reg(PeripheralBase) ( \ + SIM_SOPT4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 4 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption4Reg(PeripheralBase, Value) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption5Reg(PeripheralBase) ( \ + SIM_SOPT5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 5 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption5Reg(PeripheralBase, Value) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption7Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption7Reg(PeripheralBase) ( \ + SIM_SOPT7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 7 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption7Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption7Reg(PeripheralBase, Value) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating4Reg(PeripheralBase) ( \ + SIM_SCGC4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 4. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * SIM_PDD_WriteClockGating4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating4Reg(PeripheralBase, Value) ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating5Reg(PeripheralBase) ( \ + SIM_SCGC5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 5. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * SIM_PDD_WriteClockGating5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating5Reg(PeripheralBase, Value) ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating6Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating6Reg(PeripheralBase) ( \ + SIM_SCGC6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 6. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * SIM_PDD_WriteClockGating6Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating6Reg(PeripheralBase, Value) ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock1OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock 1 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 1 output divider. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock1OutputDivider(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_SetClock1OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV1_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock4OutputDivider + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL03Z4)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets clock 4 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 4 output divider. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock4OutputDivider(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetClock4OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV4_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV4_SHIFT))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets clock 4 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 4 output divider. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock4OutputDivider(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetClock4OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV4_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV4_SHIFT))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadFlashConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadFlashConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadFlashConfiguration1Reg(PeripheralBase) ( \ + SIM_FCFG1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash configuration 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_WriteFlashConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteFlashConfiguration1Reg(PeripheralBase, Value) ( \ + SIM_FCFG1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG2. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadFlashConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadFlashConfiguration2Reg(PeripheralBase) ( \ + SIM_FCFG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationMidHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification mid-high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDMH. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationMidHighReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationMidHighReg(PeripheralBase) ( \ + SIM_UIDMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationMidLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification mid-low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDML. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationMidLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationMidLowReg(PeripheralBase) ( \ + SIM_UIDML_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDL. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationLowReg(PeripheralBase) ( \ + SIM_UIDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCOPControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads COP control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_COPC. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadCOPControlReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadCOPControlReg(PeripheralBase) ( \ + SIM_COPC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCOPControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into COP control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the COP control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_COPC. + * @par Example: + * @code + * SIM_PDD_WriteCOPControlReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteCOPControlReg(PeripheralBase, Value) ( \ + SIM_COPC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCOPServiceReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into COP service + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the COP service register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SRVCOP. + * @par Example: + * @code + * SIM_PDD_WriteCOPServiceReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteCOPServiceReg(PeripheralBase, Value) ( \ + SIM_SRVCOP_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSourceLPUART1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, + * FAST_INTERNAL_REF_CLOCK, EXTERNAL_REF_CLOCK, SLOW_INTERNAL_REF_CLOCK. This parameter is + * of "Clock sources" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceLPUART1(_BASE_PTR, + * SIM_PDD_LPUART1_DISABLE_CLOCK); + * @endcode + */ +#define SIM_PDD_SetClockSourceLPUART1(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_LPUART1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectLptrm32kHzClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the 32 kHz clock source (ERCLK32K) for LPTMR. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. The user should use one from the enumerated + * values. This parameter is of "32 kHz clock source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * SIM_PDD_SelectLptrm32kHzClockSource(_BASE_PTR, + * SIM_PDD_LPTMR_SYSTEM_OSCILLATOR); + * @endcode + */ +#define SIM_PDD_SelectLptrm32kHzClockSource(PeripheralBase, Source) ( \ + SIM_SOPT1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT1_OSC32KSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtmClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the fixed frequency clock for FTM0, FTM1 and FTM2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTMx clock source. The user should use one from the enumerated + * values. This parameter is of "Clock for FTMx constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SelectFtmClockSource(_BASE_PTR, + * SIM_PDD_FTM_FIXED_FREQUENCY); + * @endcode + */ +#define SIM_PDD_SelectFtmClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_FTMFFCLKSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClkOutPinClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock to output on the CLKOUT pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkOut Clock to output on the CLKOUT pin source. The user should use + * one from the enumerated values. This parameter is of "Clock to output on + * the CLKOUT pin constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SelectClkOutPinClock(_BASE_PTR, + * SIM_PDD_CLKOUT_BUS_CLOCK); + * @endcode + */ +#define SIM_PDD_SelectClkOutPinClock(PeripheralBase, ClkOut) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_CLKOUTSEL_MASK)))) | ( \ + (uint32)(ClkOut))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 2 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM2 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM2 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM2_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm2ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 1 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM1 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM1 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM1_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm1ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 0 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM0 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM0 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM0_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Channel1InputCaptureSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for flex timer 2 channel 1 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 1 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 1 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel1InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1); + * @endcode + */ +#define SIM_PDD_SelectFtm2Channel1InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2ICH1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Channel0InputCaptureSource + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Selects the source for flex timer 2 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm2Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2ICH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects the source for flex timer 2 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm2Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2CH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SelectFtm1Channel0InputCaptureSource + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Selects the source for flex timer 1 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM1 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM1 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm1Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1ICH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects the source for flex timer 1 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM1 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM1 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm1Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1CH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER1_PDB_TRIGGER1); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER1_PDB_CHANNEL1); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm0HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Hardw0areTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Hardw0areTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1); + * @endcode + */ +#define SIM_PDD_SelectFtm0Hardw0areTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm0HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM2 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Fault0Source(_BASE_PTR, + * SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm2Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM2FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM1 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Fault0Source(_BASE_PTR, + * SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm1Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM1FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Fault1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 fault 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 fault 1. The user should use one from the + * enumerated values. This parameter is of "Source of FTM0 fault 1 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Fault1Source(_BASE_PTR, + * SIM_PDD_FTM0_FAULT1_FTM0_FLT1_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0Fault1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM0FLT1_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM0 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Fault0Source(_BASE_PTR, + * SIM_PDD_FTM0_FAULT0_FTM0_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM0FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUart1OpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the open drain on UART1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of open drain on UART1. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_EnableUart1OpenDrain(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableUart1OpenDrain(PeripheralBase, State) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT5_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT5_UART1ODE_MASK))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT5_UART1ODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUart0OpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the open drain on UART0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of open drain on UART0. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_EnableUart0OpenDrain(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableUart0OpenDrain(PeripheralBase, State) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT5_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT5_UART0ODE_MASK))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT5_UART0ODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart1RxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 1 receive data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 1 receive data. The user should use one from the + * enumerated values. This parameter is of "Source of UART 1 RxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart1RxDataSource(_BASE_PTR, + * SIM_PDD_UART1_RX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart1RxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1RXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart1TxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 1 transmit data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 1 transmit data. The user should use one from + * the enumerated values. This parameter is of "Source of UART 1 TxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart1TxDataSource(_BASE_PTR, + * SIM_PDD_UART1_TX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart1TxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1TXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart0RxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 0 receive data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 0 receive data. The user should use one from the + * enumerated values. This parameter is of "Source of UART 0 RxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart0RxDataSource(_BASE_PTR, + * SIM_PDD_UART0_RX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart0RxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART0RXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart0TxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 0 transmit data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 0 transmit data. The user should use one from + * the enumerated values. This parameter is of "Source of UART 0 TxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart0TxDataSource(_BASE_PTR, + * SIM_PDD_UART0_TX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart0TxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1TXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1AlternateClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC1 alternate clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 alternate clock source. The user should use one from the + * enumerated values. This parameter is of "ADC1 alternate clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1AlternateClockSource(_BASE_PTR, + * SIM_PDD_ADC1_ALT_CLK_CORE_CLK_DIV_5); + * @endcode + */ +#define SIM_PDD_SelectAdc1AlternateClockSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1ALTCLKSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0AlternateClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC0 alternate clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 alternate clock source. The user should use one from the + * enumerated values. This parameter is of "ADC0 alternate clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0AlternateClockSource(_BASE_PTR, + * SIM_PDD_ADC0_ALT_CLK_CORE_CLK_DIV_5); + * @endcode + */ +#define SIM_PDD_SelectAdc0AlternateClockSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0ALTCLKSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAdc1AlternateTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables alternative conversion triggers for ADC1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ADC1 alternate trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_EnableAdc1AlternateTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableAdc1AlternateTrigger(PeripheralBase, State) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1ALTTRGEN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1PreTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC1 pre-trigger source when alternative triggers are + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 pre-trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC1 pre-trigger source constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1PreTriggerSource(_BASE_PTR, + * SIM_PDD_ADC1_PRE_TRIGGER_A); + * @endcode + */ +#define SIM_PDD_SelectAdc1PreTriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1PRETRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1TriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC1 trigger source when alternative triggers are + * functional in Stop and VLPS modes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC1 trigger source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1TriggerSource(_BASE_PTR, + * SIM_PDD_ADC1_TRIGGER_EXTERNAL_PIN); + * @endcode + */ +#define SIM_PDD_SelectAdc1TriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1TRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAdc0AlternateTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables alternative conversion triggers for ADC0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ADC0 alternate trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_EnableAdc0AlternateTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableAdc0AlternateTrigger(PeripheralBase, State) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0ALTTRGEN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0PreTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC0 pre-trigger source when alternative triggers are + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 pre-trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC0 pre-trigger source constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0PreTriggerSource(_BASE_PTR, + * SIM_PDD_ADC0_PRE_TRIGGER_A); + * @endcode + */ +#define SIM_PDD_SelectAdc0PreTriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0PRETRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0TriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC0 trigger source when alternative triggers are + * functional in Stop and VLPS modes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC0 trigger source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0TriggerSource(_BASE_PTR, + * SIM_PDD_ADC0_TRIGGER_EXTERNAL_PIN); + * @endcode + */ +#define SIM_PDD_SelectAdc0TriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0TRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT8. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption8Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption8Reg(PeripheralBase) ( \ + SIM_SOPT8_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 8 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT8. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption8Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption8Reg(PeripheralBase, Value) ( \ + SIM_SOPT8_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVFamilyDeviceId + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns the V-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "V-family ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetVFamilyDeviceId(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_GetVFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_FAMID_MASK) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns the W-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "V-family ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetVFamilyDeviceId(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_GetVFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_FAMID_MASK) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSubFamilyDeviceId + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the sub-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Sub-family ID constant." type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSubFamilyDeviceId(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSubFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SUBFAMID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSeriesDeviceId + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the series ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Series ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSeriesDeviceId(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSeriesDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SERIERID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSystemSramSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the system SRAM size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "System SRAM size constant." type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSystemSramSize(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSystemSramSize(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SRAMSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceRevisionNumber + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns device revision number value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint8 result = SIM_PDD_GetDeviceRevisionNumber(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetDeviceRevisionNumber(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_REVID_MASK)) >> ( \ + SIM_SDID_REVID_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceDieNumber + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns device die number value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint8 result = SIM_PDD_GetDeviceDieNumber(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetDeviceDieNumber(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_DIEID_MASK)) >> ( \ + SIM_SDID_DIEID_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPincountIndetification + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the pincount indetification of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Pincount indetification constant." type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_GetPincountIndetification(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetPincountIndetification(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_PINID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemDeviceIdentificationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system device identification register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemDeviceIdentificationReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemDeviceIdentificationReg(PeripheralBase) ( \ + SIM_SDID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl4Reg(PeripheralBase) ( \ + SIM_SCGC4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 4 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl4Reg(PeripheralBase, Value) ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl5Reg(PeripheralBase) ( \ + SIM_SCGC5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 5 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl5Reg(PeripheralBase, Value) ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl6Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl6Reg(PeripheralBase) ( \ + SIM_SCGC6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 6 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl6Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl6Reg(PeripheralBase, Value) ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC7. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl7Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl7Reg(PeripheralBase) ( \ + SIM_SCGC7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 7 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC7. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl7Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl7Reg(PeripheralBase, Value) ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableClock5OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the clock 5 output divider control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of clock 5 output divider control. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_EnableClock5OutputDivider(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableClock5OutputDivider(PeripheralBase, State) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV5EN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_CLKDIV1_OUTDIV5EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock5OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock 5 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 5 output divider. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock5OutputDivider(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_SetClock5OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV5_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV5_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockDivider1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock divider 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockDivider1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockDivider1Reg(PeripheralBase) ( \ + SIM_CLKDIV1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockDivider1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * divider 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock divider 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockDivider1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockDivider1Reg(PeripheralBase, Value) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetProgramFlashSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the amount of program flash memory available on the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Program flash size constants." type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetProgramFlashSize(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetProgramFlashSize(PeripheralBase) ( \ + (uint32)(SIM_FCFG1_REG(PeripheralBase) & SIM_FCFG1_PFSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashMemoryInDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the flash memory for the duration of doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of flash memory for the duration of doze mode. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_EnableFlashMemoryInDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableFlashMemoryInDozeMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SIM_FCFG1_REG(PeripheralBase) |= \ + SIM_FCFG1_FLASHDOZE_MASK) : ( \ + SIM_FCFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SIM_FCFG1_FLASHDOZE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashMemoryAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the flash memory access. When flash accesses are + * disabled, the flash memory is placed in a low power state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of flash memory access. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_EnableFlashMemoryAccess(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableFlashMemoryAccess(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SIM_FCFG1_REG(PeripheralBase) |= \ + SIM_FCFG1_FLASHDIS_MASK) : ( \ + SIM_FCFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SIM_FCFG1_FLASHDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFirstInvalidAddressValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the first invalid address value of program flash. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG2. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_GetFirstInvalidAddressValue(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetFirstInvalidAddressValue(PeripheralBase) ( \ + (uint32)((uint32)(SIM_FCFG2_REG(PeripheralBase) & SIM_FCFG2_MAXADDR_MASK) << 13U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectWatchdogClocktSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock source of the watchdog. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Watchdog clock source parameter. The user should use one from + * the enumerated values. This parameter is of "Watchdog clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * SIM_PDD_SelectWatchdogClocktSource(_BASE_PTR, + * SIM_PDD_WDOG_INTERNAL_1KHZ); + * @endcode + */ +#define SIM_PDD_SelectWatchdogClocktSource(PeripheralBase, Source) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_WDOGCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_WDOGCTRL_WDOGCLKS_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadWatchdogControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads watchdog control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadWatchdogControlReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadWatchdogControlReg(PeripheralBase) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWatchdogControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into watchdog + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the watchdog control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * SIM_PDD_WriteWatchdogControlReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteWatchdogControlReg(PeripheralBase, Value) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(SIM_PDD_H_) */ + +/* SIM_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h new file mode 100644 index 0000000..a8870d8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h @@ -0,0 +1,3857 @@ +/* + PDD layer implementation for peripheral type SPI + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SPI_PDD_H_) +#define SPI_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SPI PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK10D5) /* SPI0 */ && \ + !defined(MCU_MK10D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK10F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK10DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK11D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK11D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MK12D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK20D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK20D5) /* SPI0 */ && \ + !defined(MCU_MK20D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK20F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK20DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK21D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK21D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MK21F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK21F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK22D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F12810) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK22F25612) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F51212) /* SPI0, SPI1 */ && \ + !defined(MCU_MK24F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK30D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK30D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK30DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK40DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40X256VMD100) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK50D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK50D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK50DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK51D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK51D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK51DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK52D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK52DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK53D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK53DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60N512VMD100) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F15WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK63F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK63F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK64F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK65F18) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK65F18WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK66F18) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F15WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MKE02Z2) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE02Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_SKEAZN642) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE04Z1284) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE04Z4) /* SPI0 */ && \ + !defined(MCU_SKEAZN84) /* SPI0 */ && \ + !defined(MCU_MKE06Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL02Z4) /* SPI0 */ && \ + !defined(MCU_MKL03Z4) /* SPI0 */ && \ + !defined(MCU_MKL04Z4) /* SPI0 */ && \ + !defined(MCU_MKL05Z4) /* SPI0 */ && \ + !defined(MCU_MKL14Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL15Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL16Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL24Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL25Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL26Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL34Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL36Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL46Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV10Z7) /* SPI0 */ && \ + !defined(MCU_MKV31F12810) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV31F25612) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV31F51212) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW01Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW21D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW21D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW22D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW22D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW24D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW24D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_PCK20L4) /* SPI0 */ && \ + !defined(MCU_SKEAZ1284) /* SPI0, SPI1 */ + // Unsupported MCU is active + #error SPI PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Chip select masks. */ +#define SPI_PDD_CHIP_SELECT_0 0x1U /**< Chip select 0 mask. */ +#define SPI_PDD_CHIP_SELECT_1 0x2U /**< Chip select 1 mask. */ +#define SPI_PDD_CHIP_SELECT_2 0x4U /**< Chip select 2 mask. */ +#define SPI_PDD_CHIP_SELECT_3 0x8U /**< Chip select 3 mask. */ +#define SPI_PDD_CHIP_SELECT_4 0x10U /**< Chip select 4 mask. */ + +/* Interrupt/DMA masks */ +#define SPI_PDD_TRANSFER_COMPLETE_INT SPI_SR_TCF_MASK /**< Transfer complete interrupt mask. */ +#define SPI_PDD_QUEUE_FINISHED_INT SPI_SR_EOQF_MASK /**< Queue finished interrupt mask. */ +#define SPI_PDD_TX_FIFO_UNDERFLOW_INT SPI_SR_TFUF_MASK /**< Transmit FIFO underflow interrupt mask. */ +#define SPI_PDD_TX_FIFO_FILL_INT_DMA SPI_SR_TFFF_MASK /**< Transmit FIFO fill interrupt mask. */ +#define SPI_PDD_RX_FIFO_OVERFLOW_INT SPI_SR_RFOF_MASK /**< Receive FIFO overflow interrupt mask. */ +#define SPI_PDD_RX_FIFO_DRAIN_INT_DMA SPI_SR_RFDF_MASK /**< Receive FIFO drain interrupt mask. */ +#define SPI_PDD_ALL_INT 0x9A0A0000U /**< All interrupt masks. */ + +/* Request mask for DMA or interrupt selection */ +#define SPI_PDD_NO_DMA 0U /**< None DMA or interrupt request selection. */ +#define SPI_PDD_TX_FIFO_FILL_DMA SPI_RSER_TFFF_DIRS_MASK /**< Transmit FIFO fill DMA or interrupt request select. */ +#define SPI_PDD_RX_FIFO_DRAIN_DMA SPI_RSER_RFDF_DIRS_MASK /**< Receive FIFO drain DMA or interrupt request select. */ + +/* Rx buffer full (or fault) and Tx buffer empty interrupt masks constant. */ +#define SPI_PDD_RX_BUFFER_FULL_OR_FAULT SPI_C1_SPIE_MASK /**< Receiver buffer full and mode fault mask. */ +#define SPI_PDD_TX_BUFFER_EMPTY SPI_C1_SPTIE_MASK /**< Transmitter buffer empty mask. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_RX_BUFFER_FULL SPI_S_SPRF_MASK /**< Read buffer or FIFO full flag. */ +#define SPI_PDD_MATCH SPI_S_SPMF_MASK /**< SPI match flag. */ +#define SPI_PDD_TX_BUFFER_EMPTYG SPI_S_SPTEF_MASK /**< Transmit buffer or FIFO empty flag. */ +#define SPI_PDD_MASTER_FAULT SPI_S_MODF_MASK /**< Master mode fault flag. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_RX_FIFO_NEARLY_FULL SPI_S_RNFULLF_MASK /**< Receive FIFO nearly full flag. */ +#define SPI_PDD_TX_FIFO_NEARLY_EMPTY SPI_S_TNEAREF_MASK /**< Transmit FIFO nearly empty flag. */ +#define SPI_PDD_TX_BUFFER_FULL SPI_S_TXFULLF_MASK /**< Transmit FIFO full flag. */ +#define SPI_PDD_READ_FIFO_EMPTY SPI_S_RFIFOEF_MASK /**< SPI read FIFO empty flag. */ + +/* FIFO interrupt masks */ +#define SPI_PDD_TRANSMIT_FIFO_EMPTY SPI_C3_TNEARIEN_MASK /**< Transmit FIFO nearly empty mask. */ +#define SPI_PDD_RECEIVE_FIFO_FULL SPI_C3_RNFULLIEN_MASK /**< Receive FIFO nearly full mask. */ +#define SPI_PDD_TRANSMIT_RECEIVE_FIFO 0x6U /**< Receive FIFO nearly full 'or' transmit FIFO nearly empty masks. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_TX_FIFO_ERROR SPI_CI_TXFERR_MASK /**< Transmit FIFO error flag. */ +#define SPI_PDD_RX_FIFO_ERROR SPI_CI_RXFERR_MASK /**< Receive FIFO error flag. */ +#define SPI_PDD_TX_FIFO_OVERFLOW SPI_CI_TXFOF_MASK /**< Transmit FIFO overflow flag. */ +#define SPI_PDD_RX_FIFO_OVERFLOW SPI_CI_RXFOF_MASK /**< Receive FIFO overflow flag. */ + +/* FIFO interrupt masks */ +#define SPI_PDD_TX_FIFO_NEARLY_EMPTY_FLAG SPI_CI_TNEAREFCI_MASK /**< Transmit FIFO nearly empty flag mask. */ +#define SPI_PDD_RX_FIFO_NEARLY_FULL_FLAG SPI_CI_RNFULLFCI_MASK /**< Receive FIFO nearly full flag mask. */ +#define SPI_PDD_TX_FIFO_EMPTY_FLAG SPI_CI_SPTEFCI_MASK /**< Transmit FIFO empty flag mask. */ +#define SPI_PDD_RX_FIFO_FULL_FLAG SPI_CI_SPRFCI_MASK /**< Receive FIFO full flag mask. */ +#define SPI_PDD_CLEAR_ALL_FIFO_FLAGS 0xFU /**< All FIFO flags masks. */ + +/* SPI mode constants (for SetMasterSlaveMode). */ +#define SPI_PDD_MASTER_MODE 0x1U /**< Master mode. */ +#define SPI_PDD_SLAVE_MODE 0U /**< Slave mode. */ + +/* SPI clock polarity constants. */ +#define SPI_PDD_SPI_MODE 0U /**< SPI mode. */ + +/* SPI clock polarity constants. */ +#define SPI_PDD_SPI_PDD_0_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0U /**< 0 system clock between SCK edge and SIN sample. */ +#define SPI_PDD_SPI_PDD_1_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0x100U /**< 1 system clock between SCK edge and SIN sample. */ +#define SPI_PDD_SPI_PDD_2_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0x200U /**< 2 system clocks between SCK edge and SIN sample. */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI data shift order constants (for SetDataShiftOrder macro). */ + #define SPI_PDD_LSB_FIRST 0x1U /**< Data transfers start with least significant bit. */ + #define SPI_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI data shift order constants */ + #define SPI_PDD_LSB_FIRST 0x1000000U /**< Data transfers start with least significant bit */ + #define SPI_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* PCS to SCK delay prescaler constants (for SetPcsToSckDelayPrescaler macro). */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_1 0U /**< PCS to SCK Prescaler value is 1. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_3 0x1U /**< PCS to SCK Prescaler value is 3. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_5 0x2U /**< PCS to SCK Prescaler value is 5. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_7 0x3U /**< PCS to SCK Prescaler value is 7. */ + +/* PCS to SCK delay prescaler constants (for SetDelayAfterTransferPrescaler, + SetAfterSckDelayPrescaler macros). */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_1 0U /**< Delay after Transfer Prescaler value is 1. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_3 0x1U /**< Delay after Transfer Prescaler value is 3. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_5 0x2U /**< Delay after Transfer Prescaler value is 5. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_7 0x3U /**< Delay after Transfer Prescaler value is 7. */ + +/* Baud rate prescaler constats (for SetBaudRatePrescaler macro). */ +#define SPI_PDD_BAUD_RATE_PRESCALER_2 0U /**< Baud rate prescaler value is 2. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_3 0x1U /**< Baud rate prescaler value is 3. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_5 0x2U /**< Baud rate prescaler value is 5. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_7 0x3U /**< Baud rate prescaler value is 7. */ + +/* PCS to SCK delay scaler constants (for SetPcsToSckDelayScaler, + SetAfterSckDelayScaler, SetDelayAfterTransferScaler macros). */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_2 0U /**< PCS to SCK delay scaler value is 2. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_4 0x1U /**< PCS to SCK delay scaler value is 4. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_8 0x2U /**< PCS to SCK delay scaler value is 8. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_16 0x3U /**< PCS to SCK delay scaler value is 16. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_32 0x4U /**< PCS to SCK delay scaler value is 32. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_64 0x5U /**< PCS to SCK delay scaler value is 64. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_128 0x6U /**< PCS to SCK delay scaler value is 128. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_256 0x7U /**< PCS to SCK delay scaler value is 256. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_512 0x8U /**< PCS to SCK delay scaler value is 512. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_1024 0x9U /**< PCS to SCK delay scaler value is 1024. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_2048 0xAU /**< PCS to SCK delay scaler value is 2048. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_4096 0xBU /**< PCS to SCK delay scaler value is 4096. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_8192 0xCU /**< PCS to SCK delay scaler value is 8192. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_16384 0xDU /**< PCS to SCK delay scaler value is 16384. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_32768 0xEU /**< PCS to SCK delay scaler value is 32768. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_65535 0xFU /**< PCS to SCK delay scaler value is 65535. */ + +/* Baud rate scaler constants (for SetBaudRateScaler macro). */ +#define SPI_PDD_BAUD_RATE_SCALER_2 0U /**< Baud rate scaler value is 2. */ +#define SPI_PDD_BAUD_RATE_SCALER_4 0x1U /**< Baud rate scaler value is 4. */ +#define SPI_PDD_BAUD_RATE_SCALER_6 0x2U /**< Baud rate scaler value is 6. */ +#define SPI_PDD_BAUD_RATE_SCALER_8 0x3U /**< Baud rate scaler value is 8. */ +#define SPI_PDD_BAUD_RATE_SCALER_16 0x4U /**< Baud rate scaler value is 16. */ +#define SPI_PDD_BAUD_RATE_SCALER_32 0x5U /**< Baud rate scaler value is 32. */ +#define SPI_PDD_BAUD_RATE_SCALER_64 0x6U /**< Baud rate scaler value is 64. */ +#define SPI_PDD_BAUD_RATE_SCALER_128 0x7U /**< Baud rate scaler value is 128. */ +#define SPI_PDD_BAUD_RATE_SCALER_256 0x8U /**< Baud rate scaler value is 256. */ +#define SPI_PDD_BAUD_RATE_SCALER_512 0x9U /**< Baud rate scaler value is 512. */ +#define SPI_PDD_BAUD_RATE_SCALER_1024 0xAU /**< Baud rate scaler value is 1024. */ +#define SPI_PDD_BAUD_RATE_SCALER_2048 0xBU /**< Baud rate scaler value is 2048. */ +#define SPI_PDD_BAUD_RATE_SCALER_4096 0xCU /**< Baud rate scaler value is 4096. */ +#define SPI_PDD_BAUD_RATE_SCALER_8192 0xDU /**< Baud rate scaler value is 8192. */ +#define SPI_PDD_BAUD_RATE_SCALER_16384 0xEU /**< Baud rate scaler value is 16384. */ +#define SPI_PDD_BAUD_RATE_SCALER_32768 0xFU /**< Baud rate scaler value is 32768. */ + +/* SPI transaction data size constants. */ +#define SPI_PDD_4_BITS 0x18000000U /**< 4-bits transaction data size */ +#define SPI_PDD_5_BITS 0x20000000U /**< 5-bits transaction data size */ +#define SPI_PDD_6_BITS 0x28000000U /**< 6-bits transaction data size */ +#define SPI_PDD_7_BITS 0x30000000U /**< 7-bits transaction data size */ +#define SPI_PDD_8_BITS 0x38000000U /**< 8-bits transaction data size */ +#define SPI_PDD_9_BITS 0x40000000U /**< 9-bits transaction data size */ +#define SPI_PDD_10_BITS 0x48000000U /**< 10-bits transaction data size */ +#define SPI_PDD_11_BITS 0x50000000U /**< 11-bits transaction data size */ +#define SPI_PDD_12_BITS 0x58000000U /**< 12-bits transaction data size */ +#define SPI_PDD_13_BITS 0x60000000U /**< 13-bits transaction data size */ +#define SPI_PDD_14_BITS 0x68000000U /**< 14-bits transaction data size */ +#define SPI_PDD_15_BITS 0x70000000U /**< 15-bits transaction data size */ +#define SPI_PDD_16_BITS 0x78000000U /**< 16-bits transaction data size */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI clock polarity constants (for SetClockPolarity macro). */ + #define SPI_PDD_ACTIVE_HIGH 0U /**< Active-high SPI clock (idles low). */ + #define SPI_PDD_ACTIVE_LOW 0x8U /**< Active-low SPI clock (idles high). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI clock polarity constants. */ + #define SPI_PDD_ACTIVE_HIGH 0x4000000U /**< Active-high SPI clock (idles low, rising edge of SPI clock starts transaction) */ + #define SPI_PDD_ACTIVE_LOW 0U /**< Active-low SPI clock (idles high, falling edge of SPI clock starts transaction) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI clock phase constants (for SetClockPhase macro). */ + #define SPI_PDD_FIRST_EDGE 0U /**< First edge on SPSCK occurs at the middle of the first cycle of a data transfer. */ + #define SPI_PDD_SECOND_EDGE 0x4U /**< First edge on SPSCK occurs at the start of the first cycle of a data transfer. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI clock phase constants. */ + #define SPI_PDD_FIRST_EDGE 0U /**< First edge on SCK occurs at the middle of the first cycle of a data transfer */ + #define SPI_PDD_SECOND_EDGE 0x2000000U /**< First edge on SCK occurs at the start of the first cycle of a data transfer */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI slave select pin function constants (for SetSlaveSelectPinFunction + macro). */ +#define SPI_PDD_SS_AS_GPIO 0U /**< Slave select pin configured as GPIO. */ +#define SPI_PDD_SS_FOR_FAULT_DETECT 0x1U /**< Slave select pin configured for fault detection. */ +#define SPI_PDD_SS_AUTOMATIC_OUTPUT 0x2U /**< Slave select pin configured for automatic SPI output. */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* SPI data length constants (for SetWordLength, GetWordLength macro). */ + #define SPI_PDD_8_BIT 0U /**< 8-bit SPI shift register, match register and buffers. */ + #define SPI_PDD_16_BIT 0x40U /**< 16-bit SPI shift register, match register and buffers. */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* SPI data length constants (for SetWordLength, GetWordLength macro). */ + #define SPI_PDD_8_BIT 0U /**< 8-bit SPI shift register, match register and buffers. */ + #define SPI_PDD_16_BIT 0x1U /**< 16-bit SPI shift register, match register and buffers. */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Transmit FIFO nearly empty watermark constants (for SetTxFifoEmptyWatermark + macro). */ +#define SPI_PDD_16_BITS_OR_LESS 0U /**< 16 bits or less. */ +#define SPI_PDD_32_BITS_OR_LESS 0x20U /**< 32 bits or less. */ + +/* Receive FIFO nearly full watermark constants (for SetRxFifoFullWatermark + macro). */ +#define SPI_PDD_32_BITS_OR_MORE 0x10U /**< 32 bits or more. */ +#define SPI_PDD_48_BITS_OR_MORE 0U /**< 48 bits or more. */ + + +/* ---------------------------------------------------------------------------- + -- SetMasterSlaveMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Select master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode SPI mode value. The user should use one from the enumerated + * values. This parameter is of "SPI mode constants (for SetMasterSlaveMode)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMasterSlaveMode(_BASE_PTR, SPI_PDD_MASTER_MODE); + * @endcode + */ + #define SPI_PDD_SetMasterSlaveMode(PeripheralBase, Mode) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_MSTR_MASK))) | ( \ + (uint8)((uint8)(Mode) << SPI_C1_MSTR_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Select master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Device mode. This parameter is of "SPI mode constants (for + * SetMasterSlaveMode)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMasterSlaveMode(_BASE_PTR, SPI_PDD_MASTER_MODE); + * @endcode + */ + #define SPI_PDD_SetMasterSlaveMode(PeripheralBase, Mode) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_MSTR_MASK))) | ( \ + (uint32)((uint32)(Mode) << SPI_MCR_MSTR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableContinuousClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables continuous clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of continuous clock. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableContinuousClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableContinuousClock(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_CONT_SCKE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_CONT_SCKE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectModuleConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects among the different configurations of the module. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Configuration SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectModuleConfiguration(_BASE_PTR, + * SPI_PDD_SPI_MODE); + * @endcode + */ +#define SPI_PDD_SelectModuleConfiguration(PeripheralBase, Configuration) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_DCONF_MASK))) | ( \ + (uint32)((uint32)(Configuration) << SPI_MCR_DCONF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransfersInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables serial transfers in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state in debug mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTransfersInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTransfersInDebugMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_FRZ_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_FRZ_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableModifiedTransferFormat + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables modified SPI transfer format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state of modified SPI transfer format. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableModifiedTransferFormat(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableModifiedTransferFormat(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_MTFE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_MTFE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoOverflowOverwrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures SPI module to ignore the incoming serial data or overwrite + * existing data if the receive FIFO is full and new data is received. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state of receive FIFO. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableRxFifoOverflowOverwrite(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableRxFifoOverflowOverwrite(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_ROOE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_ROOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChipSelectInactiveStateMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Determines the inactive state of PCSx specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighMask Chip selects mask defining which inactive state of PCSx is + * high. Use constants from group "Chip select masks.". This parameter is 5 + * bits wide. + * @param LowMask Chip selects mask defining which inactive state of PCSx is + * low. Use constants from group "Chip select masks.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetChipSelectInactiveStateMask(_BASE_PTR, + * SPI_PDD_CHIP_SELECT_0, SPI_PDD_CHIP_SELECT_0); + * @endcode + */ + #define SPI_PDD_SetChipSelectInactiveStateMask(PeripheralBase, HighMask, LowMask) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_MCR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)(LowMask) << SPI_MCR_PCSIS_SHIFT))))) | ( \ + (uint32)((uint32)(HighMask) << SPI_MCR_PCSIS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Determines the inactive state of PCSx specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighMask Chip selects mask defining which inactive state of PCSx is + * high. Use constants from group "Chip select masks.". This parameter is 6 + * bits wide. + * @param LowMask Chip selects mask defining which inactive state of PCSx is + * low. Use constants from group "Chip select masks.". This parameter is 6 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetChipSelectInactiveStateMask(_BASE_PTR, + * SPI_PDD_CHIP_SELECT_0, SPI_PDD_CHIP_SELECT_0); + * @endcode + */ + #define SPI_PDD_SetChipSelectInactiveStateMask(PeripheralBase, HighMask, LowMask) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_MCR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)(LowMask) << SPI_MCR_PCSIS_SHIFT))))) | ( \ + (uint32)((uint32)(HighMask) << SPI_MCR_PCSIS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableModuleInDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SPI device operation in doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state in doze mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableModuleInDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableModuleInDozeMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DOZE_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DOZE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables/disables SPI device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define SPI_PDD_EnableDevice(PeripheralBase, State) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_SPE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C1_SPE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define SPI_PDD_EnableDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_MDIS_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_MDIS_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmit FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit FIFO. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTxFIFO(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DIS_TXF_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DIS_TXF_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receive FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive FIFO. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableRxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableRxFIFO(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DIS_RXF_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DIS_RXF_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Tx FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearTxFIFO(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearTxFIFO(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_CLR_TXF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Rx FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearRxFIFO(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearRxFIFO(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_CLR_RXF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSamplePoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the sample point. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Configuration SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectSamplePoint(_BASE_PTR, + * SPI_PDD_SPI_PDD_0_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE); + * @endcode + */ +#define SPI_PDD_SelectSamplePoint(PeripheralBase, Configuration) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_SMPL_PT_MASK))) | ( \ + (uint32)(Configuration))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHaltMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables halt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of halt mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableHaltMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableHaltMode(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_HALT_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuleConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Module configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the module configuration register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteModuleConfigurationReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteModuleConfigurationReg(PeripheralBase, Value) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuleConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Module configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadModuleConfigurationReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadModuleConfigurationReg(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransferCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transfer counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetTransferCounter(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetTransferCounter(PeripheralBase, Value) ( \ + SPI_TCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_TCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_TCR_SPI_TCNT_MASK))) | ( \ + (uint32)((uint32)(Value) << SPI_TCR_SPI_TCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransferCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transfer counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTransferCounter(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTransferCounter(PeripheralBase) ( \ + (uint16)(( \ + (uint32)(SPI_TCR_REG(PeripheralBase) & SPI_TCR_SPI_TCNT_MASK)) >> ( \ + SPI_TCR_SPI_TCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransferCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Transfer count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the transfer count register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteTransferCountReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteTransferCountReg(PeripheralBase, Value) ( \ + SPI_TCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransferCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Transfer count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadTransferCountReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadTransferCountReg(PeripheralBase) ( \ + SPI_TCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDoubleBaudRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SCK double baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param State Requested state of SCK double baud rate. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_EnableDoubleBaudRate(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableDoubleBaudRate(PeripheralBase, Index, State) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_DBR_MASK)))) | ( \ + (uint32)((uint32)(State) << SPI_CTAR_DBR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataShiftOrder + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order SPI data shift order value. The user should use one from the + * enumerated values. This parameter is of "SPI data shift order constants + * (for SetDataShiftOrder macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataShiftOrder(_BASE_PTR, SPI_PDD_LSB_FIRST); + * @endcode + */ + #define SPI_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_LSBFE_MASK))) | ( \ + (uint8)(Order))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Order SPI data shift order value. The user should use one from the + * enumerated values. This parameter is of "SPI data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataShiftOrder(_BASE_PTR, periphID, + * SPI_PDD_LSB_FIRST); + * @endcode + */ + #define SPI_PDD_SetDataShiftOrder(PeripheralBase, Index, Order) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_LSBFE_MASK)))) | ( \ + (uint32)(Order))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPcsToSckDelayPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets PCS to SCK delay prescaler value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK Delay Ppescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetPcsToSckDelayPrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetPcsToSckDelayPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PCSSCK_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PCSSCK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAfterSckDelayPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler value for the delay between the last edge of SCK + * and the negation of PCS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK Delay prescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetAfterSckDelayPrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetAfterSckDelayPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PASC_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PASC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDelayAfterTransferPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler value for the delay between the negation of the PCS + * signal at the end of a frame and the assertion of PCS at the beginning of the + * next frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Delay after Transfer prescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetDelayAfterTransferPrescaler(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define SPI_PDD_SetDelayAfterTransferPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PDT_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PDT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRatePrescaler + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI baud rate prescale divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler Baud rate prescale divisor value[0..7]. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_BR, + * SPI1_BR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRatePrescaler(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetBaudRatePrescaler(PeripheralBase, Prescaler) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_BR_REG(PeripheralBase) & (uint8)(~(uint8)SPI_BR_SPPR_MASK))) | ( \ + (uint8)((uint8)(Prescaler) << SPI_BR_SPPR_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the prescaler value for the baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Baud rate prescaler value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_BR, + * SPI1_BR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRatePrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ + #define SPI_PDD_SetBaudRatePrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PBR_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PBR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPcsToSckDelayScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the PCS to SCK delay scaler value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK delay scaler value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetPcsToSckDelayScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetPcsToSckDelayScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CSSCK_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_CSSCK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAfterSckDelayScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the scaler value for the after SCK delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Scaler value for the after SCK delay value[0..15]. This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetAfterSckDelayScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetAfterSckDelayScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_ASC_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_ASC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDelayAfterTransferScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the delay after transfer scaler. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Delay after transfer scaler value[0..15]. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetDelayAfterTransferScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetDelayAfterTransferScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(SPI_CTAR_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)SPI_CTAR_DT_MASK))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_DT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the scaler value for the baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Baud rate prescaler value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetBaudRateScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetBaudRateScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PBR_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PBR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMasterClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for master mode to the Clock transfer attribute + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Value stored to the master clock transfer attribute register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_WriteMasterClockTransferAttributeReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define SPI_PDD_WriteMasterClockTransferAttributeReg(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMasterClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Clock transfer attribute register for + * master mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadMasterClockTransferAttributeReg(_BASE_PTR, periphID); + * @endcode + */ +#define SPI_PDD_ReadMasterClockTransferAttributeReg(PeripheralBase, Index) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for slave mode to the Clock transfer attribute + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Value stored to the slave clock transfer attribute register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR_SLAVE[Index]. + * @par Example: + * @code + * SPI_PDD_WriteSlaveClockTransferAttributeReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveClockTransferAttributeReg(PeripheralBase, Index, Value) ( \ + SPI_CTAR_SLAVE_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSlaveClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Clock transfer attribute register for slave + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CTAR_SLAVE[Index]. + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadSlaveClockTransferAttributeReg(_BASE_PTR, periphID); + * @endcode + */ +#define SPI_PDD_ReadSlaveClockTransferAttributeReg(PeripheralBase, Index) ( \ + SPI_CTAR_SLAVE_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWordLength + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets the SPI word length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length SPI data length value. The user should use one from the + * enumerated values. This parameter is of "SPI data length constants (for + * SetWordLength, GetWordLength macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C2, + * SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetWordLength(_BASE_PTR, SPI_PDD_8_BIT); + * @endcode + */ + #define SPI_PDD_SetWordLength(PeripheralBase, Length) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_SPIMODE_MASK))) | ( \ + (uint8)(Length))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the number of bits transfered per frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Size SPI frame size value. The user should use one from the enumerated + * values. This parameter is of "SPI transaction data size constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C2, + * SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetWordLength(_BASE_PTR, periphID, SPI_PDD_4_BITS); + * @endcode + */ + #define SPI_PDD_SetWordLength(PeripheralBase, Index, Size) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_FMSZ_MASK)))) | ( \ + (uint32)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetClockPolarity + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants (for + * SetClockPolarity macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPolarity(_BASE_PTR, SPI_PDD_ACTIVE_HIGH); + * @endcode + */ + #define SPI_PDD_SetClockPolarity(PeripheralBase, Polarity) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_CPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI clock polarity (intended for slave mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Polarity SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPolarity(_BASE_PTR, periphID, + * SPI_PDD_ACTIVE_HIGH); + * @endcode + */ + #define SPI_PDD_SetClockPolarity(PeripheralBase, Index, Polarity) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CPOL_MASK)))) | ( \ + (uint32)(Polarity))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetClockPhase + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI clock phase. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Phase SPI phase value. The user should use one from the enumerated + * values. This parameter is of "SPI clock phase constants (for SetClockPhase + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPhase(_BASE_PTR, SPI_PDD_FIRST_EDGE); + * @endcode + */ + #define SPI_PDD_SetClockPhase(PeripheralBase, Phase) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_CPHA_MASK))) | ( \ + (uint8)(Phase))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI clock phase (intended for slave mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Phase SPI phase value. The user should use one from the enumerated + * values. This parameter is of "SPI clock phase constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPhase(_BASE_PTR, periphID, + * SPI_PDD_FIRST_EDGE); + * @endcode + */ + #define SPI_PDD_SetClockPhase(PeripheralBase, Index, Phase) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CPHA_MASK)))) | ( \ + (uint32)(Phase))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupt/DMA masks" for processing return + * value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + SPI_SR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + SPI_SR_TCF_MASK) | (( \ + SPI_SR_EOQF_MASK) | (( \ + SPI_SR_TFUF_MASK) | (( \ + SPI_SR_TFFF_MASK) | (( \ + SPI_SR_RFOF_MASK) | ( \ + SPI_SR_RFDF_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt flags to clear. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearInterruptFlags(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxRxActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns Tx/Rx active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetTxRxActiveFlag(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTxRxActiveFlag(PeripheralBase) ( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXRXS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxRxActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Tx/Rx active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearTxRxActiveFlag(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearTxRxActiveFlag(PeripheralBase) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) | SPI_SR_TXRXS_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_RFDF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_RFOF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_TFFF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_TFUF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_EOQF_MASK)) & ( \ + (uint32)(~(uint32)SPI_SR_TCF_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOCounter + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns transmit FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetTxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint16)(( \ + (uint16)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_TXCTR4_MASK)) >> ( \ + SPI_SREX_TXCTR4_SHIFT))) << ( \ + 4U))) | ( \ + (uint16)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXCTR_MASK)) >> ( \ + SPI_SR_TXCTR_SHIFT)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns transmit FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetTxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXCTR_MASK)) >> ( \ + SPI_SR_TXCTR_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOCounter + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns receive FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetRxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint16)(( \ + (uint16)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_RXCTR4_MASK)) >> ( \ + SPI_SREX_RXCTR4_SHIFT))) << ( \ + 4U))) | ( \ + (uint16)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_RXCTR_MASK)) >> ( \ + SPI_SR_RXCTR_SHIFT)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns receive FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetRxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_RXCTR_MASK)) >> ( \ + SPI_SR_RXCTR_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetTxNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns pointer to TX FIFO entry which is transmitted during the next + * transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTxNextPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXNXTPTR_MASK)) >> ( \ + SPI_SR_TXNXTPTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns pointer to RX FIFO entry which is transmitted during the next + * transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetRxNextPointer(PeripheralBase) ( \ + (uint8)(SPI_SR_REG(PeripheralBase) & SPI_SR_POPNXTPTR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the status register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_S, SPI1_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadStatusReg(PeripheralBase) ( \ + SPI_S_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_S, SPI1_S (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadStatusReg(PeripheralBase) ( \ + SPI_SR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA/interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDmasInterrupts(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_EnableDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA/interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableDmasInterrupts(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_DisableDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects DMA or interrupt for request defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group "Request + * mask for DMA or interrupt selection". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectDmasInterrupts(_BASE_PTR, SPI_PDD_NO_DMA); + * @endcode + */ +#define SPI_PDD_SelectDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_RSER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(SPI_RSER_TFFF_DIRS_MASK | SPI_RSER_RFDF_DIRS_MASK))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDmaInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DMA interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the DMA interrupt enable register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDmaInterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteDmaInterruptEnableReg(PeripheralBase, Value) ( \ + SPI_RSER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDmaInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DMA interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadDmaInterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadDmaInterruptEnableReg(PeripheralBase) ( \ + SPI_RSER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMasterPushTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for master mode to the Push TX FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the master push Tx FIFO register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMasterPushTxFIFOReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteMasterPushTxFIFOReg(PeripheralBase, Value) ( \ + SPI_PUSHR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveData8Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 8 bits data value intended for slave mode to the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bits data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlaveData8Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveData8Bits(PeripheralBase, Data) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveData16Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bits data value intended for slave mode to the data + * registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bits data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlaveData16Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveData16Bits(PeripheralBase, Data) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlavePushTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for slave mode to the Push TX FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the slave push Tx FIFO register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlavePushTxFIFOReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlavePushTxFIFOReg(PeripheralBase, Value) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData8Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 8 bits data value to the data registers (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bits data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData8Bits(PeripheralBase, Data) ( \ + *((uint16 *)&SPI_PUSHR_REG(PeripheralBase)) = (uint16)Data \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData16Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bits data value to the data registers (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bits data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData16Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData16Bits(PeripheralBase, Data) ( \ + *((uint16 *)&SPI_PUSHR_REG(PeripheralBase)) = (uint16)Data \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData8bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 8 bits value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bits(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData8bits(PeripheralBase) ( \ + (uint8)SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData16bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 16 bits value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_ReadData16bits(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData16bits(PeripheralBase) ( \ + (uint16)SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPopRxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Pop Rx FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadPopRxFIFOReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadPopRxFIFOReg(PeripheralBase) ( \ + SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the transfer attributes for the SPI data (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTxFIFOCommand(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetTxFIFOCommand(PeripheralBase, Index) ( \ + (uint16)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index] >> 16) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns he SPI data to be shifted out. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTxFIFOData(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetTxFIFOData(PeripheralBase, Index) ( \ + (uint16)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadTxFIFOReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_ReadTxFIFOReg(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Receive FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RXFR0, SPI1_RXFR0, + * SPI2_RXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetRxFIFOData(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetRxFIFOData(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_RXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Receive FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RXFR0, SPI1_RXFR0, + * SPI2_RXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadRxFIFOReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_ReadRxFIFOReg(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_RXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Rx buffer + * full (or fault) and Tx buffer empty interrupt masks constant.". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableInterruptMask(_BASE_PTR, + * SPI_PDD_RX_BUFFER_FULL_OR_FAULT); + * @endcode + */ +#define SPI_PDD_EnableInterruptMask(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Rx buffer + * full (or fault) and Tx buffer empty interrupt masks constant.". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableInterruptMask(_BASE_PTR, + * SPI_PDD_RX_BUFFER_FULL_OR_FAULT); + * @endcode + */ +#define SPI_PDD_DisableInterruptMask(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSlaveSelectPinFunction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SPI slave select pin function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Function Slave select pin function. The user should use one from the + * enumerated values. This parameter is of "SPI slave select pin function + * constants (for SetSlaveSelectPinFunction macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI0_C2, + * SPI1_C1, SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetSlaveSelectPinFunction(_BASE_PTR, + * SPI_PDD_SS_AS_GPIO); + * @endcode + */ +#define SPI_PDD_SetSlaveSelectPinFunction(PeripheralBase, Function) ( \ + ((Function) == SPI_PDD_SS_AS_GPIO) ? ( \ + (SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C1_SSOE_MASK)), \ + (SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_MODFEN_MASK))) : ( \ + ((Function) == SPI_PDD_SS_FOR_FAULT_DETECT) ? ( \ + (SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C1_SSOE_MASK)), \ + (SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_MODFEN_MASK)) : ( \ + (SPI_C1_REG(PeripheralBase) |= \ + SPI_C1_SSOE_MASK), \ + (SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_MODFEN_MASK)) \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataFeatures + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data transmission features(shift order, clock polarity and phase) + * defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of data features requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataFeatures(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetDataFeatures(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + SPI_C1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(SPI_C1_LSBFE_MASK | (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl1Reg(PeripheralBase) ( \ + SPI_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables receive data buffer hardware match interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableMatchInterrupt(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_EnableMatchInterrupt(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_SPMIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMatchInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables receive data buffer hardware match interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableMatchInterrupt(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_DisableMatchInterrupt(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_SPMIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOutputInBidirectionalMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables pin direction in a bidirectional mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of output pin in bidirectional mode. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableOutputInBidirectionalMode(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableOutputInBidirectionalMode(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_BIDIROE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_BIDIROE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOperateInWaitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables operate in wait mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device in wait mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableOperateInWaitMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableOperateInWaitMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_SPISWAI_MASK) : ( \ + SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_SPISWAI_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBidirectionalMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables bidirectional mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of bidirectional mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableBidirectionalMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableBidirectionalMode(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_SPC0_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl2Reg(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateDivisor + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SPI baud rate divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divisor Baud rate divisor value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRateDivisor(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetBaudRateDivisor(PeripheralBase, Divisor) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_BR_REG(PeripheralBase) & (uint8)(~(uint8)SPI_BR_SPR_MASK))) | ( \ + (uint8)(Divisor))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadBaudRateReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadBaudRateReg(PeripheralBase) ( \ + SPI_BR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the baud rate register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the baud rate register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteBaudRateReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteBaudRateReg(PeripheralBase, Value) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData8Bit + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes 8 bit data value to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bit data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bit(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteData8Bit(PeripheralBase, Data) ( \ + SPI_DL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes 8 bit data value to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bit data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bit(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteData8Bit(PeripheralBase, Data) ( \ + SPI_D_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadData8bit + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the content of the 8 bit data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bit(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadData8bit(PeripheralBase) ( \ + SPI_DL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Returns the content of the 8 bit data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bit(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadData8bit(PeripheralBase) ( \ + SPI_D_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadDataLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Reads data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadDataLowReg(PeripheralBase) ( \ + SPI_DL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadDataLowReg(PeripheralBase) ( \ + SPI_D_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteDataLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes new value specified by the Value parameter into data low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteDataLowReg(PeripheralBase, Value) ( \ + SPI_DL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into data low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteDataLowReg(PeripheralBase, Value) ( \ + SPI_D_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetMatch8BitValue + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes 8 bit match value to the match register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 8 bit match value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch8BitValue(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetMatch8BitValue(PeripheralBase, Value) ( \ + SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes 8 bit match value to the match register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 8 bit match value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch8BitValue(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetMatch8BitValue(PeripheralBase, Value) ( \ + SPI_M_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadMatchLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Reads match low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadMatchLowReg(PeripheralBase) ( \ + SPI_ML_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads match low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadMatchLowReg(PeripheralBase) ( \ + SPI_M_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteMatchLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes new value specified by the Value parameter into match low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteMatchLowReg(PeripheralBase, Value) ( \ + SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into match low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteMatchLowReg(PeripheralBase, Value) ( \ + SPI_M_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_TXDMAE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_TXDMAE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_RXDMAE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_RXDMAE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetWordLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current data word length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "SPI data length constants (for SetWordLength, + * GetWordLength macro)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetWordLength(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetWordLength(PeripheralBase) ( \ + (uint8)(SPI_C2_REG(PeripheralBase) & SPI_C2_SPIMODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData16Bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bit data value to the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bit data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_DL, SPI0_DH, + * SPI1_DL, SPI1_DH (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData16Bit(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData16Bit(PeripheralBase, Data) ( \ + (SPI_DL_REG(PeripheralBase) = \ + (uint8)(Data)), \ + (SPI_DH_REG(PeripheralBase) = \ + (uint8)((uint16)(Data) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData16bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 16 bit value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_DL, SPI0_DH, + * SPI1_DL, SPI1_DH (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_ReadData16bit(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData16bit(PeripheralBase) ( \ + (uint16)(( \ + SPI_DL_REG(PeripheralBase)) | ( \ + (uint16)((uint16)SPI_DH_REG(PeripheralBase) << 8U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_DH, SPI1_DH + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataHighReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadDataHighReg(PeripheralBase) ( \ + SPI_DH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into data high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data high register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_DH, SPI1_DH + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataHighReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteDataHighReg(PeripheralBase, Value) ( \ + SPI_DH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatch16BitValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bit match value to the match registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 16 bit match value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_ML, SPI0_MH, + * SPI1_ML, SPI1_MH (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch16BitValue(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetMatch16BitValue(PeripheralBase, Value) ( \ + (SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (SPI_MH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_MH, SPI1_MH + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchHighReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadMatchHighReg(PeripheralBase) ( \ + SPI_MH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into match high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match high register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MH, SPI1_MH + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchHighReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteMatchHighReg(PeripheralBase, Value) ( \ + SPI_MH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoEmptyWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of transmit FIFO nearly empty watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmit FIFO nearly empty watermark value. The user should use + * one from the enumerated values. This parameter is of "Transmit FIFO + * nearly empty watermark constants (for SetTxFifoEmptyWatermark macro)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_SetTxFifoEmptyWatermark(_BASE_PTR, + * SPI_PDD_16_BITS_OR_LESS); + * @endcode + */ +#define SPI_PDD_SetTxFifoEmptyWatermark(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_TNEAREF_MARK_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoFullWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of receive FIFO nearly full watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receive FIFO nearly full watermark value. The user should use + * one from the enumerated values. This parameter is of "Receive FIFO nearly + * full watermark constants (for SetRxFifoFullWatermark macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_SetRxFifoFullWatermark(_BASE_PTR, + * SPI_PDD_32_BITS_OR_MORE); + * @endcode + */ +#define SPI_PDD_SetRxFifoFullWatermark(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_RNFULLF_MARK_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables FIFO interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_EnableFifoInterruptMask(_BASE_PTR, + * SPI_PDD_TRANSMIT_FIFO_EMPTY); + * @endcode + */ +#define SPI_PDD_EnableFifoInterruptMask(PeripheralBase, Mask) ( \ + SPI_C3_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables FIFO interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_DisableFifoInterruptMask(_BASE_PTR, + * SPI_PDD_TRANSMIT_FIFO_EMPTY); + * @endcode + */ +#define SPI_PDD_DisableFifoInterruptMask(PeripheralBase, Mask) ( \ + SPI_C3_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_EnableFifoMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableFifoMode(PeripheralBase, State) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_FIFOMODE_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl3Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl3Reg(PeripheralBase) ( \ + SPI_C3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 3 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 3 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_WriteControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl3Reg(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadFifoStatusReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadFifoStatusReg(PeripheralBase) ( \ + SPI_CI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFifoInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears FIFO interrupt flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * SPI_PDD_ClearFifoInterruptFlag(_BASE_PTR, + * SPI_PDD_TX_FIFO_NEARLY_EMPTY_FLAG); + * @endcode + */ +#define SPI_PDD_ClearFifoInterruptFlag(PeripheralBase, Mask) ( \ + SPI_CI_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClearInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clear interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadClearInterruptReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadClearInterruptReg(PeripheralBase) ( \ + SPI_CI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clear interrupt + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clear interrupt register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * SPI_PDD_WriteClearInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteClearInterruptReg(PeripheralBase, Value) ( \ + SPI_CI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandFIFOCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the number of entries in the CMD FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint8 result = SPI_PDD_GetCommandFIFOCounter(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetCommandFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_CMDCTR_MASK)) >> ( \ + SPI_SREX_CMDCTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the command next pointer - indicates which CMD FIFO Entry is + * used during the next transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint8 result = SPI_PDD_GetCommandNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetCommandNextPointer(PeripheralBase) ( \ + (uint8)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_CMDNXTPTR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExtendedStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads extended status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadExtendedStatusReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadExtendedStatusReg(PeripheralBase) ( \ + SPI_SREX_REG(PeripheralBase) \ + ) +#endif /* #if defined(SPI_PDD_H_) */ + +/* SPI_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h new file mode 100644 index 0000000..c02d1c2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h @@ -0,0 +1,539 @@ +/* + PDD layer implementation for peripheral type SysTick + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SysTick_PDD_H_) +#define SysTick_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SysTick PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SysTick */ && \ + !defined(MCU_MK10D5) /* SysTick */ && \ + !defined(MCU_MK10D7) /* SysTick */ && \ + !defined(MCU_MK10F12) /* SysTick */ && \ + !defined(MCU_MK10DZ10) /* SysTick */ && \ + !defined(MCU_MK11D5) /* SysTick */ && \ + !defined(MCU_MK11D5WS) /* SysTick */ && \ + !defined(MCU_MK12D5) /* SysTick */ && \ + !defined(MCU_MK20D10) /* SysTick */ && \ + !defined(MCU_MK20D5) /* SysTick */ && \ + !defined(MCU_MK20D7) /* SysTick */ && \ + !defined(MCU_MK20F12) /* SysTick */ && \ + !defined(MCU_MK20DZ10) /* SysTick */ && \ + !defined(MCU_MK21D5) /* SysTick */ && \ + !defined(MCU_MK21D5WS) /* SysTick */ && \ + !defined(MCU_MK21F12) /* SysTick */ && \ + !defined(MCU_MK21F12WS) /* SysTick */ && \ + !defined(MCU_MK22D5) /* SysTick */ && \ + !defined(MCU_MK22F12810) /* SysTick */ && \ + !defined(MCU_MK22F12) /* SysTick */ && \ + !defined(MCU_MK22F25612) /* SysTick */ && \ + !defined(MCU_MK22F51212) /* SysTick */ && \ + !defined(MCU_MK24F12) /* SysTick */ && \ + !defined(MCU_MK30D10) /* SysTick */ && \ + !defined(MCU_MK30D7) /* SysTick */ && \ + !defined(MCU_MK30DZ10) /* SysTick */ && \ + !defined(MCU_MK40D10) /* SysTick */ && \ + !defined(MCU_MK40D7) /* SysTick */ && \ + !defined(MCU_MK40DZ10) /* SysTick */ && \ + !defined(MCU_MK40X256VMD100) /* SysTick */ && \ + !defined(MCU_MK50D10) /* SysTick */ && \ + !defined(MCU_MK50D7) /* SysTick */ && \ + !defined(MCU_MK50DZ10) /* SysTick */ && \ + !defined(MCU_MK51D10) /* SysTick */ && \ + !defined(MCU_MK51D7) /* SysTick */ && \ + !defined(MCU_MK51DZ10) /* SysTick */ && \ + !defined(MCU_MK52D10) /* SysTick */ && \ + !defined(MCU_MK52DZ10) /* SysTick */ && \ + !defined(MCU_MK53D10) /* SysTick */ && \ + !defined(MCU_MK53DZ10) /* SysTick */ && \ + !defined(MCU_MK60D10) /* SysTick */ && \ + !defined(MCU_MK60F12) /* SysTick */ && \ + !defined(MCU_MK60F15) /* SysTick */ && \ + !defined(MCU_MK60DZ10) /* SysTick */ && \ + !defined(MCU_MK60N512VMD100) /* SysTick */ && \ + !defined(MCU_MK61F12) /* SysTick */ && \ + !defined(MCU_MK61F15) /* SysTick */ && \ + !defined(MCU_MK61F12WS) /* SysTick */ && \ + !defined(MCU_MK61F15WS) /* SysTick */ && \ + !defined(MCU_MK63F12) /* SysTick */ && \ + !defined(MCU_MK63F12WS) /* SysTick */ && \ + !defined(MCU_MK64F12) /* SysTick */ && \ + !defined(MCU_MK65F18) /* SysTick */ && \ + !defined(MCU_MK65F18WS) /* SysTick */ && \ + !defined(MCU_MK66F18) /* SysTick */ && \ + !defined(MCU_MK70F12) /* SysTick */ && \ + !defined(MCU_MK70F15) /* SysTick */ && \ + !defined(MCU_MK70F12WS) /* SysTick */ && \ + !defined(MCU_MK70F15WS) /* SysTick */ && \ + !defined(MCU_MKE02Z2) /* SysTick */ && \ + !defined(MCU_MKE02Z4) /* SysTick */ && \ + !defined(MCU_SKEAZN642) /* SysTick */ && \ + !defined(MCU_MKE04Z1284) /* SysTick */ && \ + !defined(MCU_MKE04Z4) /* SysTick */ && \ + !defined(MCU_SKEAZN84) /* SysTick */ && \ + !defined(MCU_MKE06Z4) /* SysTick */ && \ + !defined(MCU_MKL02Z4) /* SysTick */ && \ + !defined(MCU_MKL03Z4) /* SysTick */ && \ + !defined(MCU_MKL04Z4) /* SysTick */ && \ + !defined(MCU_MKL05Z4) /* SysTick */ && \ + !defined(MCU_MKL14Z4) /* SysTick */ && \ + !defined(MCU_MKL15Z4) /* SysTick */ && \ + !defined(MCU_MKL16Z4) /* SysTick */ && \ + !defined(MCU_MKL24Z4) /* SysTick */ && \ + !defined(MCU_MKL25Z4) /* SysTick */ && \ + !defined(MCU_MKL26Z4) /* SysTick */ && \ + !defined(MCU_MKL34Z4) /* SysTick */ && \ + !defined(MCU_MKL36Z4) /* SysTick */ && \ + !defined(MCU_MKL46Z4) /* SysTick */ && \ + !defined(MCU_MKV10Z7) /* SysTick */ && \ + !defined(MCU_MKV31F12810) /* SysTick */ && \ + !defined(MCU_MKV31F25612) /* SysTick */ && \ + !defined(MCU_MKV31F51212) /* SysTick */ && \ + !defined(MCU_MKW01Z4) /* SysTick */ && \ + !defined(MCU_MKW21D5) /* SysTick */ && \ + !defined(MCU_MKW21D5WS) /* SysTick */ && \ + !defined(MCU_MKW22D5) /* SysTick */ && \ + !defined(MCU_MKW22D5WS) /* SysTick */ && \ + !defined(MCU_MKW24D5) /* SysTick */ && \ + !defined(MCU_MKW24D5WS) /* SysTick */ && \ + !defined(MCU_PCK20L4) /* SysTick */ && \ + !defined(MCU_SKEAZ1284) /* SysTick */ + // Unsupported MCU is active + #error SysTick PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Clock source constants. */ + #define SysTick_PDD_CORE_CLOCK 0x1U /**< 1 */ + #define SysTick_PDD_CORE_CLOCK_DIV16 0U /**< 1 */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock source constants. */ + #define SysTick_PDD_CORE_CLOCK 0x1U /**< 1 */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_TICKINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_COUNTFLAG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the SysTick interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_EnableInterrupt(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) |= \ + SysTick_CSR_TICKINT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the SysTick interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_DisableInterrupt(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SysTick_CSR_TICKINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears SysTick interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ClearInterruptFlag(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SysTick_CSR_COUNTFLAG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the SysTick device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of SysTick device. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SysTick_PDD_EnableDevice(PeripheralBase, State) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SysTick_CSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SysTick_CSR_ENABLE_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of SysTick device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_ENABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClkSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource New value of the clock source. Use constants from group + * "Clock source constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_SetClkSource(_BASE_PTR, SysTick_PDD_CORE_CLOCK); + * @endcode + */ +#define SysTick_PDD_SetClkSource(PeripheralBase, ClkSource) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SysTick_CSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SysTick_CSR_CLKSOURCE_MASK)))) | ( \ + (uint32)((uint32)(ClkSource) << SysTick_CSR_CLKSOURCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetClkSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Gets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Clock source constants." for processing + * return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint8 result = SysTick_PDD_GetClkSource(_BASE_PTR); + * @endcode + */ + #define SysTick_PDD_GetClkSource(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_CLKSOURCE_MASK)) >> ( \ + SysTick_CSR_CLKSOURCE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Gets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Clock source constants." for processing + * return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint8 result = SysTick_PDD_GetClkSource(_BASE_PTR); + * @endcode + */ + #define SysTick_PDD_GetClkSource(PeripheralBase) ( \ + 0x1U \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control and status register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_WriteControlStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteControlStatusReg(PeripheralBase, Value) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_ReadControlStatusReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadControlStatusReg(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteReloadValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the reload register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the reload register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_RVR. + * @par Example: + * @code + * SysTick_PDD_WriteReloadValueReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteReloadValueReg(PeripheralBase, Value) ( \ + SysTick_RVR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadReloadValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the reload register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_RVR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_ReadReloadValueReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadReloadValueReg(PeripheralBase) ( \ + SysTick_RVR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCurrentValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the current value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the current value register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CVR. + * @par Example: + * @code + * SysTick_PDD_WriteCurrentValueReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteCurrentValueReg(PeripheralBase, Value) ( \ + SysTick_CVR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCurrentValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the current value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CVR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_ReadCurrentValueReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadCurrentValueReg(PeripheralBase) ( \ + SysTick_CVR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCalibrationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the calibration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CALIB. + * @par Example: + * @code + * uint32 result = SysTick_PDD_ReadCalibrationReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadCalibrationReg(PeripheralBase) ( \ + SysTick_CALIB_REG(PeripheralBase) \ + ) +#endif /* #if defined(SysTick_PDD_H_) */ + +/* SysTick_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h new file mode 100644 index 0000000..8616787 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h @@ -0,0 +1,5346 @@ +/* + PDD layer implementation for peripheral type UART + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(UART_PDD_H_) +#define UART_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error UART PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK10D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK10D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK10F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK10DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK11D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK11D5WS) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK12D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK20D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK20D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK20D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK20F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK20DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK21D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK21D5WS) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK21F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK21F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK22D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK22F12810) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK22F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK22F25612) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK22F51212) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK24F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK30D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK30D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK30DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK40DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40X256VMD100) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK50D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK50D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK50DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK51D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK51D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK51DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK52D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK52DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK53D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK53DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60N512VMD100) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F15WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK63F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK63F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK64F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK65F18) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK65F18WS) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK66F18) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK70F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F15WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MKE02Z2) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE02Z4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_SKEAZN642) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE04Z1284) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE04Z4) /* UART0 */ && \ + !defined(MCU_SKEAZN84) /* UART0 */ && \ + !defined(MCU_MKE06Z4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKL14Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL15Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL16Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL24Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL25Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL26Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL34Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL36Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL46Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKV10Z7) /* UART0, UART1 */ && \ + !defined(MCU_MKV31F12810) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKV31F25612) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKV31F51212) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW01Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKW21D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW21D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW22D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW22D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW24D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW24D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_PCK20L4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_SKEAZ1284) /* UART0, UART1, UART2 */ + // Unsupported MCU is active + #error UART PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Interrupt masks */ +#define UART_PDD_INTERRUPT_TRANSMITTER UART_C2_TIE_MASK /**< Transmitter interrupt enable mask */ +#define UART_PDD_INTERRUPT_TRANSMITTER_COMPLETE UART_C2_TCIE_MASK /**< Transmitter complete interrupt enable mask */ +#define UART_PDD_INTERRUPT_RECEIVER UART_C2_RIE_MASK /**< Receiver interrupt enable mask */ +#define UART_PDD_INTERRUPT_IDLE UART_C2_ILIE_MASK /**< Idle interrupt enable mask */ +#define UART_PDD_INTERRUPT_PARITY_ERROR UART_C3_PEIE_MASK /**< Parity error interrupt enable mask */ +#define UART_PDD_INTERRUPT_FRAMING_ERROR UART_C3_FEIE_MASK /**< Framing error interrupt enable mask */ +#define UART_PDD_INTERRUPT_NOISE_ERROR UART_C3_NEIE_MASK /**< Noise error interrupt enable mask */ +#define UART_PDD_INTERRUPT_OVERRUN_ERROR UART_C3_ORIE_MASK /**< Overrun error interrupt enable mask */ + +/* Status flags constants. */ +#define UART_PDD_TX_DATA_EMPTY_FLAG UART_S1_TDRE_MASK /**< Transmitter FIFO word count is at or below watermark */ +#define UART_PDD_TX_IDLE_FLAG UART_S1_TC_MASK /**< No transmission in progress (transmission activity complete) */ +#define UART_PDD_RX_DATA_FULL_FLAG UART_S1_RDRF_MASK /**< Receiver FIFO word count is above watermark */ +#define UART_PDD_RX_IDLE_FLAG UART_S1_IDLE_MASK /**< Receiver input has become idle (after receiving a valid frame) */ +#define UART_PDD_RX_OVERRUN_FLAG UART_S1_OR_MASK /**< Receiver buffer overrun */ +#define UART_PDD_RX_NOISE_FLAG UART_S1_NF_MASK /**< Receiver input detect a noise. */ +#define UART_PDD_RX_FRAMING_ERROR_FLAG UART_S1_FE_MASK /**< Receiver framing error detect */ +#define UART_PDD_RX_PARITY_ERROR_FLAG UART_S1_PF_MASK /**< Receiver parity error detect */ + +/* Status 2 flags constants. */ +#define UART_PDD_LIN_BREAK_DETECT_FLAG UART_S2_LBKDIF_MASK /**< LIN break character is detected on the receiver input */ +#define UART_PDD_RXD_PIN_ACTIVE_EDGE_FLAG UART_S2_RXEDGIF_MASK /**< Active edge occurs on the RxD pin */ +#define UART_PDD_RECEIVER_ACTIVE_FLAG UART_S2_RAF_MASK /**< Receiver active, RxD input not idle */ + +/* Received data status constants. */ +#define UART_PDD_DATA_RECEIVED_WITH_NOISE UART_ED_NOISY_MASK /**< The data was received with noise */ +#define UART_PDD_DATA_RECEIVED_WITH_PARITY_ERROR UART_ED_PARITYE_MASK /**< The dataword was received with a parity error */ + +/* Enable FIFO masks */ +#define UART_PDD_TX_FIFO_ENABLE UART_PFIFO_TXFE_MASK /**< Transmitter FIFO enable mask */ +#define UART_PDD_RX_FIFO_ENABLE UART_PFIFO_RXFE_MASK /**< Receiver FIFO enable mask */ + +/* FIFO flush masks */ +#define UART_PDD_TX_FIFO_FLUSH UART_CFIFO_TXFLUSH_MASK /**< Transmitter FIFO flush command mask */ +#define UART_PDD_RX_FIFO_FLUSH UART_CFIFO_RXFLUSH_MASK /**< Receiver FIFO flush command mask */ + +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_PCK20L4))) +/* Rx buffer full, Tx buffer empty and error interrupt masks constant */ + #define UART_PDD_TX_FIFO_OVERFLOW_INT UART_CFIFO_TXOFE_MASK /**< Transmit FIFO overflow interrupt mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_INT UART_CFIFO_RXUFE_MASK /**< Receive FIFO underflow interrupt mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Rx buffer full, Tx buffer empty and error interrupt masks constant */ + #define UART_PDD_RX_FIFO_OVERFLOW_INT UART_CFIFO_RXOFE_MASK /**< Receive FIFO overflow interrupt mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_INT UART_CFIFO_TXOFE_MASK /**< Transmit FIFO overflow interrupt mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_INT UART_CFIFO_RXUFE_MASK /**< Receive FIFO underflow interrupt mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_PCK20L4))) +/* FIFO status flags constant */ + #define UART_PDD_TX_FIFO_EMPTY_FLAG UART_SFIFO_TXEMPT_MASK /**< Transmit buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_EMPTY_FLAG UART_SFIFO_RXEMPT_MASK /**< Receive buffer/FIFO empty mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_FLAG UART_SFIFO_TXOF_MASK /**< Transmit FIFO overflow flag mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_FLAG UART_SFIFO_RXUF_MASK /**< Receive FIFO underflow flag mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FIFO status flags constant */ + #define UART_PDD_TX_FIFO_EMPTY_FLAG UART_SFIFO_TXEMPT_MASK /**< Transmit buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_EMPTY_FLAG UART_SFIFO_RXEMPT_MASK /**< Receive buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_OVERFLOW_FLAG UART_SFIFO_RXOF_MASK /**< Receive FIFO overflow flag mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_FLAG UART_SFIFO_TXOF_MASK /**< Transmit FIFO overflow flag mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_FLAG UART_SFIFO_RXUF_MASK /**< Receive FIFO underflow flag mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* ISO7816 Interrupt masks */ +#define UART_PDD_ISO7816_WAIT_TIMER_INT UART_IE7816_WTE_MASK /**< Wait timer interrupt mask */ +#define UART_PDD_ISO7816_CHAR_WAIT_TIMER_INT UART_IE7816_CWTE_MASK /**< Character wait timer interrupt mask */ +#define UART_PDD_ISO7816_BLOCK_WAIT_TIMER_INT UART_IE7816_BWTE_MASK /**< Block wait timer interrupt mask */ +#define UART_PDD_ISO7816_INITIAL_CHAR_DETECTED_INT UART_IE7816_INITDE_MASK /**< Initial character detected interrupt mask */ +#define UART_PDD_ISO7816_GUARD_TIMER_VIOLATED_INT UART_IE7816_GTVE_MASK /**< Guard timer violated interrupt mask */ +#define UART_PDD_ISO7816_TRANSMIT_THRESHOLD_EXCEED_INT UART_IE7816_TXTE_MASK /**< Transmit threshold exceeded interrupt mask */ +#define UART_PDD_ISO7816_RECEIVE_THRESHOLD_EXCEED_INT UART_IE7816_RXTE_MASK /**< Receive threshold exceeded interrupt mask */ + +/* ISO7816 interrupt flag masks */ +#define UART_PDD_ISO7816_WAIT_TIMER_FLAG UART_IS7816_WT_MASK /**< Wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_CHAR_WAIT_TIMER_FLAG UART_IS7816_CWT_MASK /**< Character wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_BLOCK_WAIT_TIMER_FLAG UART_IS7816_BWT_MASK /**< Block wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_INITIAL_CHAR_DETECTED_FLAG UART_IS7816_INITD_MASK /**< Initial character detected interrupt flag mask */ +#define UART_PDD_ISO7816_GUARD_TIMER_VIOLATED_FLAG UART_IS7816_GTV_MASK /**< Guard timer violated interrupt flag mask */ +#define UART_PDD_ISO7816_TRANSMIT_THRESHOLD_EXCEED_FLAG UART_IS7816_TXT_MASK /**< Transmit threshold exceeded interrupt flag mask */ +#define UART_PDD_ISO7816_RECEIVE_THRESHOLD_EXCEED_FLAG UART_IS7816_RXT_MASK /**< Receive threshold exceeded interrupt flag mask */ + +/* CEA709.1-B interrupt masks constant */ +#define UART_PDD_CEA7091B_PREAMBLE_ERROR_FLAG UART_S3_PEF_MASK /**< Preamble error flag mask */ +#define UART_PDD_CEA7091B_WBASE_EXPIRED_FLAG UART_S3_WBEF_MASK /**< WBASE expired flag mask */ +#define UART_PDD_CEA7091B_INIT_SYNC_DETECTED_FLAG UART_S3_ISD_MASK /**< Initial sync detection flag mask */ +#define UART_PDD_CEA7091B_PACKED_RECEIVED_FLAG UART_S3_PRXF_MASK /**< Packet received flag mask */ +#define UART_PDD_CEA7091B_PACKED_TRANSMITTED_FLAG UART_S3_PTXF_MASK /**< Packet transmitted flag mask */ +#define UART_PDD_CEA7091B_PACKED_CYCLE_TIMER_FLAG UART_S3_PCTEF_MASK /**< Packet cycle timer expired flag mask */ +#define UART_PDD_CEA7091B_PREAMBLE_START_FLAG UART_S3_PSF_MASK /**< Preamble start flag mask */ +#define UART_PDD_CEA7091B_TRANSMISSION_FAIL_FLAG UART_S3_TXFF_MASK /**< Transmission fail flag mask */ + +/* CEA709.1-B interrupt masks constant */ +#define UART_PDD_CEA7091B_COLLISION_DETECTED_FLAG UART_S4_CDET_MASK /**< Collision detection flag mask */ +#define UART_PDD_CEA7091B_FRAMING_ERROR_FLAG UART_S4_FE_MASK /**< Framing error flag mask */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Loop mode */ + #define UART_PDD_LOOP_MODE_NORMAL 0U /**< Normal operation mode. No loopback selected. */ + #define UART_PDD_LOOP_MODE_LOCAL_LOOP 0x1U /**< Local loopback mode. */ + #define UART_PDD_LOOP_MODE_RX_TO_TX_PIN 0x2U /**< Receiver input connected to TXD pin (single wire operation) */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Loop mode */ + #define UART_PDD_LOOP_MODE_NORMAL 0U /**< Normal operation mode. No loopback selected */ + #define UART_PDD_LOOP_MODE_LOCAL_LOOP 0x80U /**< Local loopback mode. Receiver input internally connected to transmitter output */ + #define UART_PDD_LOOP_MODE_RX_TO_TX_PIN 0xA0U /**< Receiver input connected to TXD pin (single wire operation) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Data width */ + #define UART_PDD_WIDTH_8 0U /**< 8-bit communication */ + #define UART_PDD_WIDTH_9 0x10U /**< 9-bit communication */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Data width */ + #define UART_PDD_WIDTH_8 0U /**< 8-bit communication */ + #define UART_PDD_WIDTH_9 0x1U /**< 9-bit communication */ + #define UART_PDD_WIDTH_10 0x2U /**< 10-bit communication (10th bit can be used only as parity bit) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Wake-up condition constants. */ +#define UART_PDD_BY_IDLE_LINE 0U /**< Idle line wake-up */ +#define UART_PDD_BY_ADDRESS_MARK 0x8U /**< Address mark wake-up */ + +/* Idle line type constants. */ +#define UART_PDD_AFTER_START_BIT 0U /**< Idle character bit count starts after start bit. */ +#define UART_PDD_AFTER_STOP_BIT 0x4U /**< Idle character bit count starts after stop bit. */ + +/* Parity types */ +#define UART_PDD_PARITY_NONE 0U /**< No parity */ +#define UART_PDD_PARITY_EVEN 0x2U /**< Even parity */ +#define UART_PDD_PARITY_ODD 0x3U /**< Even parity */ + +/* Receiver power states. */ +#define UART_PDD_POWER_NORMAL 0U /**< Normal operation. */ +#define UART_PDD_POWER_STANDBY 0x2U /**< Standby mode (waiting for a wakeup condition). */ + +/* UART data shift order constants */ +#define UART_PDD_LSB_FIRST 0x20U /**< Data transfers start with least significant bit */ +#define UART_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit */ + +/* Break transmit character length constants */ +#define UART_PDD_BREAK_CHARACTER_10_11_12_BITS 0U /**< Break character is 10, 11, or 12 bits long */ +#define UART_PDD_BREAK_CHARACTER_13_14_BITS 0x4U /**< Break character is 13 or 14 bits long */ + +/* Transmitter pin data direction (in single-wire mode) constants */ +#define UART_PDD_TX_PIN_IS_AN_INPUT 0U /**< TxD pin is an input in single wire mode */ +#define UART_PDD_TX_PIN_IS_AN_OUTPUT 0x20U /**< TxD pin is an output in single wire mode */ + +/* Position of a parity bit */ +#define UART_PDD_PARITY_BIT_POSITION_9 0U /**< Parity bit is the 9-th bit in the serial transmission */ +#define UART_PDD_PARITY_BIT_POSITION_10 0x20U /**< Parity bit is the 10-th bit in the serial transmission */ + +/* Request-to-send transmitter polarity constants */ +#define UART_PDD_RTS_ACTIVE_LOW 0U /**< Transmitter RTS is active low */ +#define UART_PDD_RTS_ACTIVE_HIGH 0x4U /**< Transmitter RTS is active high */ + +/* Parity types */ +#define UART_PDD_TX_NARROW_PULSE_3_DIV_16 0U /**< 3/16 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_16 0x1U /**< 1/16 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_32 0x2U /**< 1/32 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_4 0x3U /**< 1/4 narrow pulse */ + +/* Transmit FIFO/Buffer depth constants. */ +#define UART_PDD_TX_FIFO_SIZE_1 0U /**< Transmit FIFO/Buffer depth = 1 dataword */ +#define UART_PDD_TX_FIFO_SIZE_4 0x10U /**< Transmit FIFO/Buffer depth = 4 datawords */ +#define UART_PDD_TX_FIFO_SIZE_8 0x20U /**< Transmit FIFO/Buffer depth = 8 datawords */ +#define UART_PDD_TX_FIFO_SIZE_16 0x30U /**< Transmit FIFO/Buffer depth = 16 datawords */ +#define UART_PDD_TX_FIFO_SIZE_32 0x40U /**< Transmit FIFO/Buffer depth = 32 datawords */ +#define UART_PDD_TX_FIFO_SIZE_64 0x50U /**< Transmit FIFO/Buffer depth = 64 datawords */ +#define UART_PDD_TX_FIFO_SIZE_128 0x60U /**< Transmit FIFO/Buffer depth = 128 datawords */ + +/* Receive FIFO/Buffer depth constants. */ +#define UART_PDD_RX_FIFO_SIZE_1 0U /**< Receive FIFO/Buffer depth = 1 dataword */ +#define UART_PDD_RX_FIFO_SIZE_4 0x1U /**< Receive FIFO/Buffer depth = 4 datawords */ +#define UART_PDD_RX_FIFO_SIZE_8 0x2U /**< Receive FIFO/Buffer depth = 8 datawords */ +#define UART_PDD_RX_FIFO_SIZE_16 0x3U /**< Receive FIFO/Buffer depth = 16 datawords */ +#define UART_PDD_RX_FIFO_SIZE_32 0x4U /**< Receive FIFO/Buffer depth = 32 datawords */ +#define UART_PDD_RX_FIFO_SIZE_64 0x5U /**< Receive FIFO/Buffer depth = 64 datawords */ +#define UART_PDD_RX_FIFO_SIZE_128 0x6U /**< Receive FIFO/Buffer depth = 128 datawords */ + +/* Transfer type constants */ +#define UART_PDD_ISO7816_TRANSFER_TYPE_T0 0U /**< T = 0 per the ISO-7816 specification */ +#define UART_PDD_ISO7816_TRANSFER_TYPE_T1 0x2U /**< T = 1 per the ISO-7816 specification */ + +/* Collision polarity constants */ +#define UART_PDD_CEA7091b_COLLISION_SIGNAL_LOW 0U /**< Collision signal is active low */ +#define UART_PDD_CEA7091b_COLLISION_SIGNAL_HIGH 0x10U /**< Collision signal is active high */ + +/* CEA709.1-B collision status constants. */ +#define UART_PDD_CEA7091B_NO_COLLISION 0U /**< No collision */ +#define UART_PDD_CEA7091B_COLLISION_PREAMBLE 0x4U /**< Collision occurred during preamble */ +#define UART_PDD_CEA7091B_COLLISION_SYNCH_OR_DATA 0x8U /**< Collision occurred during byte sync or data */ +#define UART_PDD_CEA7091B_COLLISION_LINE_CODE 0xCU /**< Collision occurred during line code violation */ + +/* Stop bit lengths */ +#define UART_PDD_STOP_BIT_LEN_1 0U /**< One stop bit. */ +#define UART_PDD_STOP_BIT_LEN_2 0x20U /**< Two stop bits. */ + + +/* ---------------------------------------------------------------------------- + -- SetBaudRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets new baud rate value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param BaudRate New baud rate value. This parameter is a 13-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART0_BDL, + * UART1_BDH, UART1_BDL, UART2_BDH, UART2_BDL, UART3_BDH, UART3_BDL, + * UART4_BDH, UART4_BDL, UART5_BDH, UART5_BDL (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBaudRate(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetBaudRate(PeripheralBase, BaudRate) ( \ + (UART_BDH_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_BDH_REG(PeripheralBase) & (uint8)(~(uint8)UART_BDH_SBR_MASK))) | ( \ + (uint8)((uint16)(BaudRate) >> 8U)))), \ + (UART_BDL_REG(PeripheralBase) = \ + (uint8)(BaudRate)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadBaudRateHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadBaudRateHighReg(PeripheralBase) ( \ + UART_BDH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into baud rate high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate high register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteBaudRateHighReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteBaudRateHighReg(PeripheralBase, Value) ( \ + UART_BDH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_BDL, UART1_BDL, + * UART2_BDL, UART3_BDL, UART4_BDL, UART5_BDL (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadBaudRateLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadBaudRateLowReg(PeripheralBase) ( \ + UART_BDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into baud rate low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate low register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDL, UART1_BDL, + * UART2_BDL, UART3_BDL, UART4_BDL, UART5_BDL (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteBaudRateLowReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteBaudRateLowReg(PeripheralBase, Value) ( \ + UART_BDL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLoopMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects the loop mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param LoopMode Loop mode. This parameter is of "Loop mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetLoopMode(_BASE_PTR, UART_PDD_LOOP_MODE_NORMAL); + * @endcode + */ + #define UART_PDD_SetLoopMode(PeripheralBase, LoopMode) ( \ + ((LoopMode) == UART_PDD_LOOP_MODE_NORMAL) ? ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)UART_C1_LOOPS_MASK)) & ( \ + (uint8)(~(uint8)UART_C1_RSRC_MASK)))) : (((LoopMode) == UART_PDD_LOOP_MODE_LOCAL_LOOP) ? ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) | UART_C1_LOOPS_MASK)) & ( \ + (uint8)(~(uint8)UART_C1_RSRC_MASK)))) : ( \ + UART_C1_REG(PeripheralBase) |= \ + (uint8)(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK)) \ + ) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects the loop mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param LoopMode Loop mode. This parameter is of "Loop mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetLoopMode(_BASE_PTR, UART_PDD_LOOP_MODE_NORMAL); + * @endcode + */ + #define UART_PDD_SetLoopMode(PeripheralBase, LoopMode) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_C1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK))))) | ( \ + (uint8)(LoopMode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableOperateInWaitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables operate in wait mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device in wait mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableOperateInWaitMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableOperateInWaitMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_UARTSWAI_MASK) : ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C1_UARTSWAI_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataWidth + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the communication width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data width. This parameter is of "Data width" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART0_C4, + * UART1_C1, UART1_C4, UART2_C1, UART2_C4, UART3_C1, UART3_C4, UART4_C1, + * UART4_C4, UART5_C1, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataWidth(_BASE_PTR, UART_PDD_WIDTH_8); + * @endcode + */ + #define UART_PDD_SetDataWidth(PeripheralBase, Width) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_M_MASK))) | ( \ + (uint8)(Width))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the communication width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data width. This parameter is of "Data width" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART0_C4, + * UART1_C1, UART1_C4, UART2_C1, UART2_C4, UART3_C1, UART3_C4, UART4_C1, + * UART4_C4, UART5_C1, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataWidth(_BASE_PTR, UART_PDD_WIDTH_8); + * @endcode + */ + #define UART_PDD_SetDataWidth(PeripheralBase, Width) ( \ + ( \ + ((Width) == UART_PDD_WIDTH_8) ? ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C1_M_MASK)) : (((Width) == UART_PDD_WIDTH_9) ? ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_M_MASK) : ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_M_MASK) \ + )), \ + ( \ + ((Width) == UART_PDD_WIDTH_8) ? ( \ + UART_C4_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C4_M10_MASK)) : (((Width) == UART_PDD_WIDTH_9) ? ( \ + UART_C4_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C4_M10_MASK)) : ( \ + UART_C4_REG(PeripheralBase) |= \ + UART_C4_M10_MASK) \ + )) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetWakeupCondition + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the wake-up condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Condition Wake-up condition. This parameter is of "Wake-up condition + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetWakeupCondition(_BASE_PTR, + * UART_PDD_BY_IDLE_LINE); + * @endcode + */ +#define UART_PDD_SetWakeupCondition(PeripheralBase, Condition) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_WAKE_MASK))) | ( \ + (uint8)(Condition))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectIdleLineType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the idle line type, it determines when the receiver starts + * counting logic 1s as idle character bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Idle line type. This parameter is of "Idle line type constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SelectIdleLineType(_BASE_PTR, + * UART_PDD_AFTER_START_BIT); + * @endcode + */ +#define UART_PDD_SelectIdleLineType(PeripheralBase, Type) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_ILT_MASK))) | ( \ + (uint8)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetParity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a communication parity type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Parity Parity type. This parameter is of "Parity types" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetParity(_BASE_PTR, UART_PDD_PARITY_NONE); + * @endcode + */ +#define UART_PDD_SetParity(PeripheralBase, Parity) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)0x3U))) | ( \ + (uint8)(Parity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl1Reg(PeripheralBase) ( \ + UART_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART0_C3, + * UART1_C2, UART1_C3, UART2_C2, UART2_C3, UART3_C2, UART3_C3, UART4_C2, + * UART4_C3, UART5_C2, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInterrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_EnableInterrupt(PeripheralBase, Mask) ( \ + (UART_C2_REG(PeripheralBase) |= \ + (uint8)((uint8)(Mask) & (uint8)(~(uint8)0xFU))), \ + (UART_C3_REG(PeripheralBase) |= \ + (uint8)((uint8)(Mask) & 0xFU)) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART0_C3, + * UART1_C2, UART1_C3, UART2_C2, UART2_C3, UART3_C2, UART3_C3, UART4_C2, + * UART4_C3, UART5_C2, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_DisableInterrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_DisableInterrupt(PeripheralBase, Mask) ( \ + (UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)((uint8)(Mask) & (uint8)(~(uint8)0xFU)))), \ + (UART_C3_REG(PeripheralBase) &= \ + (uint8)(~(uint8)((uint8)(Mask) & 0xFU))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxCompleteInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the transmiter complete interrupt enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetTxCompleteInterruptMask(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxCompleteInterruptMask(PeripheralBase) ( \ + (uint8)(UART_C2_REG(PeripheralBase) & UART_C2_TCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables UART transmitter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables transmitter. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitter(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_TE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C2_TE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiver + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables UART receiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receiver. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiver(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableReceiver(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_RE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C2_RE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReceiverPowerState + ---------------------------------------------------------------------------- */ + +/** + * @brief Places the receiver in a standby state where it waits for automatic + * hardware detection of a selected wakeup condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Receiver power state to be set. This parameter is of "Receiver + * power states." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetReceiverPowerState(_BASE_PTR, + * UART_PDD_POWER_NORMAL); + * @endcode + */ +#define UART_PDD_SetReceiverPowerState(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_RWU_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Set the break signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SetBreak(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) |= \ + UART_C2_SBK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the break signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ClearBreak(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C2_SBK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Send the break character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SendBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SendBreak(PeripheralBase) ( \ + (UART_C2_REG(PeripheralBase) |= \ + UART_C2_SBK_MASK), \ + (UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C2_SBK_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl2Reg(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus1Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus1Flags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus1Flags(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxCompleteStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the transmiter complete interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetTxCompleteStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxCompleteStatus(PeripheralBase) ( \ + (uint8)(UART_S1_REG(PeripheralBase) & UART_S1_TC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadInterruptStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadInterruptStatusReg(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetBreak(PeripheralBase) ( \ + (( \ + (uint8)(UART_S1_REG(PeripheralBase) & (uint8)(UART_S1_FE_MASK | UART_S1_RDRF_MASK))) == ( \ + (uint8)(UART_S1_FE_MASK | UART_S1_RDRF_MASK))) ? ( \ + 0x1U) : ( \ + 0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus1Reg(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus2Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the flags of the status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus2Flags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus2Flags(PeripheralBase) ( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & ( \ + (uint8)(UART_S2_LBKDIF_MASK | (UART_S2_RXEDGIF_MASK | UART_S2_RAF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStatus2Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the flags of the status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearStatus2Flags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearStatus2Flags(PeripheralBase, Mask) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataShiftOrder + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_MSBF_MASK))) | ( \ + (uint8)(Order))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_MSBF_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Order))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_MSBF_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Order))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_MSBF_MASK))) | ( \ + (uint8)(Order))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDataInversion + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RXINV_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RXINV_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveWakeupIdleDetect + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RWUID_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RWUID_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RWUID_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RWUID_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetBreakLength + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_BRK13_MASK))) | ( \ + (uint8)(Length))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_BRK13_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Length))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_BRK13_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Length))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_BRK13_MASK))) | ( \ + (uint8)(Length))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableLinBreakLongerCharacterDetection + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_LBKDE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_LBKDE_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_LBKDE_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_LBKDE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadStatus2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus2Reg(PeripheralBase) ( \ + UART_S2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatus2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteStatus2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteStatus2Reg(PeripheralBase, Value) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChar9Bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 9th bit of the character from the receive buffer shifted + * to its bit position (9th). Must be called prior to calling GetChar8 to read the + * whole 9-bit character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = UART_PDD_GetChar9Bit(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetChar9Bit(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)(UART_C3_REG(PeripheralBase) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)) << ( \ + 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- PutChar9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts 9-bits character into the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Char 9-bits character to be written to the data register. This + * parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART0_D, + * UART1_C3, UART1_D, UART2_C3, UART2_D, UART3_C3, UART3_D, UART4_C3, + * UART4_D, UART5_C3, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_PutChar9(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_PutChar9(PeripheralBase, Char) ( \ + (UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_T8_MASK))) | ( \ + (uint8)((uint8)((uint16)(Char) >> 8U) << UART_C3_T8_SHIFT)))), \ + (UART_D_REG(PeripheralBase) = \ + (uint8)(Char)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxPinDataDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter pin data direction in single-wire mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Transmitter pin data direction value. The user should use + * one from the enumerated values. This parameter is of "Transmitter pin + * data direction (in single-wire mode) constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetTxPinDataDirection(_BASE_PTR, + * UART_PDD_TX_PIN_IS_AN_INPUT); + * @endcode + */ +#define UART_PDD_SetTxPinDataDirection(PeripheralBase, Direction) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_TXDIR_MASK))) | ( \ + (uint8)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDataInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables transmit data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables transmit data inversion. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDataInversion(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitDataInversion(PeripheralBase, State) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_TXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C3_TXINV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl3Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl3Reg(PeripheralBase) ( \ + UART_C3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 3 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 3 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl3Reg(PeripheralBase, Value) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- PutChar8 + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts 8-bits character into the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Char 8-bits character to be written to the data register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_PutChar8(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_PutChar8(PeripheralBase, Char) ( \ + UART_D_REG(PeripheralBase) = \ + (uint8)(Char) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChar8 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a 8-bit character from the receive buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetChar8(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetChar8(PeripheralBase) ( \ + UART_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadDataReg(PeripheralBase) ( \ + UART_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteDataReg(PeripheralBase, Value) ( \ + UART_D_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMatchAddress1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns match address 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetMatchAddress1Value(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetMatchAddress1Value(PeripheralBase) ( \ + UART_MA1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatchAddress1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a new match address 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Match address 1 value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetMatchAddress1Value(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetMatchAddress1Value(PeripheralBase, Address) ( \ + UART_MA1_REG(PeripheralBase) = \ + (uint8)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match address 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadMatchAddress1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadMatchAddress1Reg(PeripheralBase) ( \ + UART_MA1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into match address 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match address 1 register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteMatchAddress1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteMatchAddress1Reg(PeripheralBase, Value) ( \ + UART_MA1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMatchAddress2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns match address 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetMatchAddress2Value(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetMatchAddress2Value(PeripheralBase) ( \ + UART_MA2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatchAddress2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a new match address 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Match address 2 value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetMatchAddress2Value(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetMatchAddress2Value(PeripheralBase, Address) ( \ + UART_MA2_REG(PeripheralBase) = \ + (uint8)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match address 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadMatchAddress2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadMatchAddress2Reg(PeripheralBase) ( \ + UART_MA2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into match address 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match address 2 register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteMatchAddress2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteMatchAddress2Reg(PeripheralBase, Value) ( \ + UART_MA2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchAddress1Mode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables address 1 match mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables address 1 match mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableMatchAddress1Mode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableMatchAddress1Mode(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_MAEN1_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_MAEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchAddress2Mode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables address 2 match mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables address 2 match mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableMatchAddress2Mode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableMatchAddress2Mode(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_MAEN2_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_MAEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPositionOfParityBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the position of the parity bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Position Position of a parity bit. This parameter is of "Position of a + * parity bit" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetPositionOfParityBit(_BASE_PTR, + * UART_PDD_PARITY_BIT_POSITION_9); + * @endcode + */ +#define UART_PDD_SetPositionOfParityBit(PeripheralBase, Position) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_M10_MASK))) | ( \ + (uint8)(Position))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateFineAdjust + ---------------------------------------------------------------------------- */ + +/** + * @brief Set new baud rate fine adjust value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FineAdjust New baud rate fine adjust value. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBaudRateFineAdjust(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetBaudRateFineAdjust(PeripheralBase, FineAdjust) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_BRFA_MASK))) | ( \ + (uint8)(FineAdjust))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl4Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl4Reg(PeripheralBase) ( \ + UART_C4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 4 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl4Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl4Reg(PeripheralBase, Value) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDma + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_TDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_TDMAS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_TDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_TDMAS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDma + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_RDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_RDMAS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_RDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_RDMAS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl5Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl5Reg(PeripheralBase) ( \ + UART_C5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 5 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl5Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl5Reg(PeripheralBase, Value) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataExtendedStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the received data status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ED, UART1_ED, + * UART2_ED, UART3_ED, UART4_ED, UART5_ED (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetRxDataExtendedStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetRxDataExtendedStatus(PeripheralBase) ( \ + UART_ED_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExtendedDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads extended data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ED, UART1_ED, + * UART2_ED, UART3_ED, UART4_ED, UART5_ED (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadExtendedDataReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadExtendedDataReg(PeripheralBase) ( \ + UART_ED_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiverRequestToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables receiver request-to-send, it allows the RTS output to + * control the CTS input of the transmitting device to prevent receiver overrun. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver request-to-send. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiverRequestToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableReceiverRequestToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_RXRTSE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_MODEM_RXRTSE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitterRequestToSendPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the polarity of the transmitter RTS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Request-to-send transmitter polarity. This parameter is of + * "Request-to-send transmitter polarity constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_SetTransmitterRequestToSendPolarity(_BASE_PTR, + * UART_PDD_RTS_ACTIVE_LOW); + * @endcode + */ +#define UART_PDD_SetTransmitterRequestToSendPolarity(PeripheralBase, Polarity) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXRTSPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitterRequestToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transmitter request-to-send, it allows control RTS + * before and after a transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter request-to-send. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitterRequestToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitterRequestToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXRTSE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_MODEM_TXRTSE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitterClearToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transmitter clear-to-send operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter clear-to-send operation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitterClearToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitterClearToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXCTSE_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModemReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads modem register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadModemReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadModemReg(PeripheralBase) ( \ + UART_MODEM_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModemReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into modem register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the modem register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteModemReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteModemReg(PeripheralBase, Value) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInfraredModulation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables infrared modulation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of infrared modulation. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInfraredModulation(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableInfraredModulation(PeripheralBase, State) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_IR_REG(PeripheralBase) & (uint8)(~(uint8)UART_IR_IREN_MASK))) | ( \ + (uint8)((uint8)(State) << UART_IR_IREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitterNarrowPulse + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a transmitter narrow pulse. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pulse narrow pulse. This parameter is of "Parity types" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetTransmitterNarrowPulse(_BASE_PTR, + * UART_PDD_TX_NARROW_PULSE_3_DIV_16); + * @endcode + */ +#define UART_PDD_SetTransmitterNarrowPulse(PeripheralBase, Pulse) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_IR_REG(PeripheralBase) & (uint8)(~(uint8)UART_IR_TNP_MASK))) | ( \ + (uint8)(Pulse))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInfraredReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads infrared register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadInfraredReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadInfraredReg(PeripheralBase) ( \ + UART_IR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInfraredReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into infrared register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the infrared register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteInfraredReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteInfraredReg(PeripheralBase, Value) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifo + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables FIFO specified by the FifoMask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FifoMask Specifies receive or transmit FIFO. Use constants from group + * "Enable FIFO masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableFifo(_BASE_PTR, UART_PDD_TX_FIFO_ENABLE); + * @endcode + */ +#define UART_PDD_EnableFifo(PeripheralBase, FifoMask) ( \ + UART_PFIFO_REG(PeripheralBase) |= \ + (uint8)(FifoMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFifoSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the maximum number of transmit datawords that can be stored in + * the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Transmit FIFO/Buffer depth constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetTxFifoSize(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxFifoSize(PeripheralBase) ( \ + (uint8)(UART_PFIFO_REG(PeripheralBase) & UART_PFIFO_TXFIFOSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFifoSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the maximum number of receive datawords that can be stored in + * the receive buffer before an overrun occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receive FIFO/Buffer depth constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetRxFifoSize(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetRxFifoSize(PeripheralBase) ( \ + (uint8)(UART_PFIFO_REG(PeripheralBase) & UART_PFIFO_RXFIFOSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoParametersReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO parameters register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoParametersReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoParametersReg(PeripheralBase) ( \ + UART_PFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoParametersReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO parameters + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO parameters register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoParametersReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoParametersReg(PeripheralBase, Value) ( \ + UART_PFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- FlushFifo + ---------------------------------------------------------------------------- */ + +/** + * @brief Flushes FIFO specified by the FifoMask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FifoMask Specifies receive or transmit FIFO. Use constants from group + * "FIFO flush masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_FlushFifo(_BASE_PTR, UART_PDD_TX_FIFO_FLUSH); + * @endcode + */ +#define UART_PDD_FlushFifo(PeripheralBase, FifoMask) ( \ + UART_CFIFO_REG(PeripheralBase) |= \ + (uint8)(FifoMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt FIFO requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableFifoInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_EnableFifoInterruptMask(PeripheralBase, Mask) ( \ + UART_CFIFO_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt FIFO requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_DisableFifoInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_DisableFifoInterruptMask(PeripheralBase, Mask) ( \ + UART_CFIFO_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoControlReg(PeripheralBase) ( \ + UART_CFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO control register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoControlReg(PeripheralBase, Value) ( \ + UART_CFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SFIFO, + * UART1_SFIFO, UART2_SFIFO, UART3_SFIFO, UART4_SFIFO, UART5_SFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoStatusFlags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoStatusFlags(PeripheralBase) ( \ + UART_SFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFifoStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears FIFO status flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of flag requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SFIFO, + * UART1_SFIFO, UART2_SFIFO, UART3_SFIFO, UART4_SFIFO, UART5_SFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_ClearFifoStatusFlags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearFifoStatusFlags(PeripheralBase, Mask) ( \ + UART_SFIFO_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoStatusReg(PeripheralBase) ( \ + UART_CFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO status register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoStatusReg(PeripheralBase, Value) ( \ + UART_CFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO transmit watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TWFIFO, + * UART1_TWFIFO, UART2_TWFIFO, UART3_TWFIFO, UART4_TWFIFO, UART5_TWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadTxFifoWatermarkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadTxFifoWatermarkReg(PeripheralBase) ( \ + UART_TWFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO transmit + * watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO transmit watermark register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TWFIFO, + * UART1_TWFIFO, UART2_TWFIFO, UART3_TWFIFO, UART4_TWFIFO, UART5_TWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteTxFifoWatermarkReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteTxFifoWatermarkReg(PeripheralBase, Value) ( \ + UART_TWFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO transmit count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TCFIFO, + * UART1_TCFIFO, UART2_TCFIFO, UART3_TCFIFO, UART4_TCFIFO, UART5_TCFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadTxFifoCountReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadTxFifoCountReg(PeripheralBase) ( \ + UART_TCFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO receive watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RWFIFO, + * UART1_RWFIFO, UART2_RWFIFO, UART3_RWFIFO, UART4_RWFIFO, UART5_RWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadRxFifoWatermarkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadRxFifoWatermarkReg(PeripheralBase) ( \ + UART_RWFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO receive + * watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO receive watermark register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_RWFIFO, + * UART1_RWFIFO, UART2_RWFIFO, UART3_RWFIFO, UART4_RWFIFO, UART5_RWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteRxFifoWatermarkReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteRxFifoWatermarkReg(PeripheralBase, Value) ( \ + UART_RWFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoCountkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO receive count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RCFIFO, + * UART1_RCFIFO, UART2_RCFIFO, UART3_RCFIFO, UART4_RCFIFO, UART5_RCFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadRxFifoCountkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadRxFifoCountkReg(PeripheralBase) ( \ + UART_RCFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGenerateNackOnOverflow + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating NACK if a receive buffer overrun. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state generating NACK on overflow. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableGenerateNackOnOverflow(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableGenerateNackOnOverflow(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_ONACK_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_ONACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGenerateNackOnError + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating NACK if a parity error occurs or if INIT + * is set and an invalid initial character is detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state generating NACK on error. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableGenerateNackOnError(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableGenerateNackOnError(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_ANACK_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_ANACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInitialCharDetection + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating initial char detection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of initial char detection. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInitialCharDetection(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableInitialCharDetection(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_INIT_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_INIT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransferType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transfer type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Transfer type. This parameter is of "Transfer type constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransferType(_BASE_PTR, + * UART_PDD_ISO7816_TRANSFER_TYPE_T0); + * @endcode + */ +#define UART_PDD_SetIso7816TransferType(PeripheralBase, Type) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_TTYPE_MASK))) | ( \ + (uint8)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIso7816Functionality + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables ISO-7816 functionality. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ISO-7816 functionality . This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableIso7816Functionality(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableIso7816Functionality(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_C7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_C7816_ISO_7816E_MASK)))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816ControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816ControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816ControlReg(PeripheralBase) ( \ + UART_C7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816ControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 control register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816ControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816ControlReg(PeripheralBase, Value) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIso7816Interrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables ISO7816 interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "ISO7816 Interrupt + * masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableIso7816Interrupt(_BASE_PTR, + * UART_PDD_ISO7816_WAIT_TIMER_INT); + * @endcode + */ +#define UART_PDD_EnableIso7816Interrupt(PeripheralBase, Mask) ( \ + UART_IE7816_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableIso7816Interrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_DisableIso7816Interrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_DisableIso7816Interrupt(PeripheralBase, Mask) ( \ + UART_IE7816_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816InterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816InterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816InterruptEnableReg(PeripheralBase) ( \ + UART_IE7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816InterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 interrupt + * enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 interrupt enable register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816InterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816InterruptEnableReg(PeripheralBase, Value) ( \ + UART_IE7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadIso7816StatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ISO7816 status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "ISO7816 interrupt flag masks" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadIso7816StatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadIso7816StatusReg(PeripheralBase) ( \ + UART_IS7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearIso7816InterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears ISO7816 interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "ISO7816 interrupt flag masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearIso7816InterruptFlags(_BASE_PTR, + * UART_PDD_ISO7816_WAIT_TIMER_FLAG); + * @endcode + */ +#define UART_PDD_ClearIso7816InterruptFlags(PeripheralBase, Mask) ( \ + UART_IS7816_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816InterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816InterruptStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816InterruptStatusReg(PeripheralBase) ( \ + UART_IS7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816InterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 interrupt + * status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 interrupt status register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816InterruptStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816InterruptStatusReg(PeripheralBase, Value) ( \ + UART_IS7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816WaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 wait timer interrupt value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 wait timer interrupt value[0..255]. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816WaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816WaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitTimerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait timer interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitTimerReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitTimerReg(PeripheralBase) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitTimerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait timer + * interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait timer interrupt register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitTimerReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitTimerReg(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816CharacterWaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 character wait time integer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 character wait time integer value[0..15]. This parameter + * is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816CharacterWaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816CharacterWaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_WP7816_T_TYPE1_CWI_MASK)))) | ( \ + (uint8)((uint8)(Value) << UART_WP7816_T_TYPE1_CWI_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816BlockWaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 block wait time integer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 block wait time integer value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816BlockWaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816BlockWaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_WP7816_T_TYPE1_BWI_MASK)))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitParameterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait parameter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816WaitParameterReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitParameterReg(PeripheralBase) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitParameterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait parameter + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait parameter register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitParameterReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitParameterReg(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitNReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait N register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WN7816, + * UART1_WN7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitNReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitNReg(PeripheralBase) ( \ + UART_WN7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitNReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait N register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait N register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WN7816, + * UART1_WN7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitNReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitNReg(PeripheralBase, Value) ( \ + UART_WN7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitFdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait FD register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WF7816, + * UART1_WF7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitFdReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitFdReg(PeripheralBase) ( \ + UART_WF7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitFdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait FD + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait FD register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WF7816, + * UART1_WF7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitFdReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitFdReg(PeripheralBase, Value) ( \ + UART_WF7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransmitNackThreshold + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 transmit NAC threshold value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 transmit NACK threshold value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransmitNackThreshold(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816TransmitNackThreshold(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_ET7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_ET7816_TXTHRESHOLD_MASK)))) | ( \ + (uint8)((uint8)(Value) << UART_ET7816_TXTHRESHOLD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816ReceiveNackThreshold + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 receive NAC threshold value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 receive NACK threshold value[0..15]. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816ReceiveNackThreshold(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816ReceiveNackThreshold(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_ET7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_ET7816_RXTHRESHOLD_MASK)))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816ErrorThresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 error threshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816ErrorThresholdReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816ErrorThresholdReg(PeripheralBase) ( \ + UART_ET7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816ErrorThresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 error threshold + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 error threshold register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816ErrorThresholdReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816ErrorThresholdReg(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransmitLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 transmit length value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 transmit length value[0..15]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransmitLength(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816TransmitLength(PeripheralBase, Value) ( \ + UART_TL7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816TransmitLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 transmit length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816TransmitLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816TransmitLengthReg(PeripheralBase) ( \ + UART_TL7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816TransmitLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 transmit length + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit error length register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816TransmitLengthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816TransmitLengthReg(PeripheralBase, Value) ( \ + UART_TL7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCea7091bMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the CEA709.1-B feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter clear-to-send operation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_EnableCea7091bMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableCea7091bMode(PeripheralBase, State) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_EN709_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C6_EN709_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendCea7091bPacket + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts CEA709.1-B transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_SendCea7091bPacket(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SendCea7091bPacket(PeripheralBase) ( \ + UART_C6_REG(PeripheralBase) |= \ + UART_C6_TX709_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCea7091bTransmittingPacket + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns if transmission CEA709.1-B packet is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * uint8 result = + * UART_PDD_IsCea7091bTransmittingPacket(_BASE_PTR); + * @endcode + */ +#define UART_PDD_IsCea7091bTransmittingPacket(PeripheralBase) ( \ + (uint8)(UART_C6_REG(PeripheralBase) & UART_C6_TX709_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCea7091bCollision + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the collision detect functionality. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of collision detect functionality. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_EnableCea7091bCollision(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableCea7091bCollision(PeripheralBase, State) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_CE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C6_CE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bCollisionSignalPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the collision polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Collision polarity. This parameter is of "Collision polarity + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_SetCea7091bCollisionSignalPolarity(_BASE_PTR, + * UART_PDD_CEA7091b_COLLISION_SIGNAL_LOW); + * @endcode + */ +#define UART_PDD_SetCea7091bCollisionSignalPolarity(PeripheralBase, Polarity) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_CP_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bControlReg(PeripheralBase) ( \ + UART_C6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_WriteCea7091bControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bControlReg(PeripheralBase, Value) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bPacketCycleTimeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets EA709.1-B packet cycle time counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value EA709.1-B packet cycle time counter value[0..65535]. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTL, UART0_PCTH + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetCea7091bPacketCycleTimeCounter(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetCea7091bPacketCycleTimeCounter(PeripheralBase, Value) ( \ + (UART_PCTL_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (UART_PCTH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bPacketCycleTimeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns EA709.1-B packet cycle time counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: UART0_PCTH, UART0_PCTL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * UART_PDD_GetCea7091bPacketCycleTimeCounter(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bPacketCycleTimeCounter(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)UART_PCTH_REG(PeripheralBase) << 8U)) | ( \ + (uint16)UART_PCTL_REG(PeripheralBase))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPacketCycleTimeCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B packet cycle time counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PCTH. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPacketCycleTimeCounterHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPacketCycleTimeCounterHighReg(PeripheralBase) ( \ + UART_PCTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPacketCycleTimeCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B packet + * cycle time counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B packet cycle time counter + * high register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTH. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPacketCycleTimeCounterHighReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPacketCycleTimeCounterHighReg(PeripheralBase, Value) ( \ + UART_PCTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPacketCycleTimeCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B packet cycle time counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PCTL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPacketCycleTimeCounterLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPacketCycleTimeCounterLowReg(PeripheralBase) ( \ + UART_PCTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPacketCycleTimeCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B packet + * cycle time counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B packet cycle time counter + * low register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPacketCycleTimeCounterLowReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPacketCycleTimeCounterLowReg(PeripheralBase, Value) ( \ + UART_PCTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bSecondaryDelayTimer + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets EA709.1-B secondary delay timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value EA709.1-B secondary delay timer value[0..65535]. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTL, UART0_SDTH + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetCea7091bSecondaryDelayTimer(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetCea7091bSecondaryDelayTimer(PeripheralBase, Value) ( \ + (UART_SDTL_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (UART_SDTH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bSecondaryDelayTimer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns EA709.1-B secondary delay timer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: UART0_SDTH, UART0_SDTL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * UART_PDD_GetCea7091bSecondaryDelayTimer(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bSecondaryDelayTimer(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)UART_SDTH_REG(PeripheralBase) << 8U)) | ( \ + (uint16)UART_SDTL_REG(PeripheralBase))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bSecondaryDelayTimerHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B secondary delay timer high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SDTH. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bSecondaryDelayTimerHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bSecondaryDelayTimerHighReg(PeripheralBase) ( \ + UART_SDTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bSecondaryDelayTimerHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B secondary + * delay timer high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B secondary delay timer high + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTH. + * @par Example: + * @code + * UART_PDD_WriteCea7091bSecondaryDelayTimerHighReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bSecondaryDelayTimerHighReg(PeripheralBase, Value) ( \ + UART_SDTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bSecondaryDelayTimerLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B secondary delay timer low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SDTL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bSecondaryDelayTimerLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bSecondaryDelayTimerLowReg(PeripheralBase) ( \ + UART_SDTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bSecondaryDelayTimerLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B secondary + * delay timer low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B secondary delay timer low + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bSecondaryDelayTimerLowReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bSecondaryDelayTimerLowReg(PeripheralBase, Value) ( \ + UART_SDTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPreambleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B preamble register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PRE. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPreambleReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPreambleReg(PeripheralBase) ( \ + UART_PRE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPreambleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B preamble + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B preamble register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PRE. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPreambleReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPreambleReg(PeripheralBase, Value) ( \ + UART_PRE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bTxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B transmit packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TPL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bTxPacketLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bTxPacketLengthReg(PeripheralBase) ( \ + UART_TPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bTxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B transmit + * packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B transmit packet length + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TPL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bTxPacketLengthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bTxPacketLengthReg(PeripheralBase, Value) ( \ + UART_TPL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IE. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bInterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bInterruptEnableReg(PeripheralBase) ( \ + UART_IE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B interrupt + * enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B interrupt enable register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE. + * @par Example: + * @code + * UART_PDD_WriteCea7091bInterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bInterruptEnableReg(PeripheralBase, Value) ( \ + UART_IE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bWBaseReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B WBase register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WB. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bWBaseReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bWBaseReg(PeripheralBase) ( \ + UART_WB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bWBaseReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B WBase + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B WBase register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WB. + * @par Example: + * @code + * UART_PDD_WriteCea7091bWBaseReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bWBaseReg(PeripheralBase, Value) ( \ + UART_WB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bStatusReg0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the CEA709.1-B status register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "CEA709.1-B interrupt masks constant" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bStatusReg0(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bStatusReg0(PeripheralBase) ( \ + UART_S3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCea7091bInterruptFlags0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CEA709.1-B interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "CEA709.1-B interrupt masks constant". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * UART_PDD_ClearCea7091bInterruptFlags0(_BASE_PTR, + * UART_PDD_CEA7091B_PREAMBLE_ERROR_FLAG); + * @endcode + */ +#define UART_PDD_ClearCea7091bInterruptFlags0(PeripheralBase, Mask) ( \ + UART_S3_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bStatusReg0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B status + * register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B status register 0. This + * parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * uint8 result = + * UART_PDD_WriteCea7091bStatusReg0(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bStatusReg0(PeripheralBase, Value) ( \ + UART_S3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bStatusReg1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the CEA709.1-B status register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "CEA709.1-B interrupt masks constant" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bStatusReg1(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bStatusReg1(PeripheralBase) ( \ + UART_S4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCea7091bInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CEA709.1-B interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "CEA709.1-B interrupt masks constant". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * UART_PDD_ClearCea7091bInterruptFlags1(_BASE_PTR, + * UART_PDD_CEA7091B_COLLISION_DETECTED_FLAG); + * @endcode + */ +#define UART_PDD_ClearCea7091bInterruptFlags1(PeripheralBase, Mask) ( \ + UART_S4_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bCollisionStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CEA709.1-B collision status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CEA709.1-B collision status constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetCea7091bCollisionStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bCollisionStatus(PeripheralBase) ( \ + (uint8)(UART_S4_REG(PeripheralBase) & UART_S4_CDET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bStatusReg1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B status + * register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B status register 1. This + * parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = + * UART_PDD_WriteCea7091bStatusReg1(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bStatusReg1(PeripheralBase, Value) ( \ + UART_S4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bRxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B received packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RPL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bRxPacketLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bRxPacketLengthReg(PeripheralBase) ( \ + UART_RPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bRxPreambleLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B received preamble length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RPREL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bRxPreambleLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bRxPreambleLengthReg(PeripheralBase) ( \ + UART_RPREL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bCollisionPulseWidthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B collision pulse width register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CPW. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bCollisionPulseWidthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bCollisionPulseWidthReg(PeripheralBase) ( \ + UART_CPW_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bCollisionPulseWidthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B collision + * pulse width register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B collision pulse width + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CPW. + * @par Example: + * @code + * UART_PDD_WriteCea7091bCollisionPulseWidthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bCollisionPulseWidthReg(PeripheralBase, Value) ( \ + UART_CPW_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStopBitLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the number of stop bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Stop bit length. This parameter is of "Stop bit lengths" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetStopBitLength(_BASE_PTR, + * UART_PDD_STOP_BIT_LEN_1); + * @endcode + */ +#define UART_PDD_SetStopBitLength(PeripheralBase, Length) ( \ + UART_BDH_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_BDH_REG(PeripheralBase) & (uint8)(~(uint8)UART_BDH_SBNS_MASK))) | ( \ + (uint8)(Length))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLinBreakDetectDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a LIN break detect DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of LIN break detect DMA request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakDetectDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableLinBreakDetectDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_LBKDDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_LBKDDMAS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the interrupt status flags specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of the flags to be cleared. This parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ClearInterruptFlags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + UART_S1_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatus1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteStatus1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteStatus1Reg(PeripheralBase, Value) ( \ + UART_S1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(UART_PDD_H_) */ + +/* UART_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h new file mode 100644 index 0000000..0b4152f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h @@ -0,0 +1,816 @@ +/* + PDD layer implementation for peripheral type USBDCD + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(USBDCD_PDD_H_) +#define USBDCD_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error USBDCD PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK20D10) /* USBDCD */ && \ + !defined(MCU_MK20D5) /* USBDCD */ && \ + !defined(MCU_MK20D7) /* USBDCD */ && \ + !defined(MCU_MK20F12) /* USBDCD */ && \ + !defined(MCU_MK20DZ10) /* USBDCD */ && \ + !defined(MCU_MK21D5) /* USBDCD */ && \ + !defined(MCU_MK21D5WS) /* USBDCD */ && \ + !defined(MCU_MK21F12) /* USBDCD */ && \ + !defined(MCU_MK21F12WS) /* USBDCD */ && \ + !defined(MCU_MK22D5) /* USBDCD */ && \ + !defined(MCU_MK22F12) /* USBDCD */ && \ + !defined(MCU_MK24F12) /* USBDCD */ && \ + !defined(MCU_MK40D10) /* USBDCD */ && \ + !defined(MCU_MK40D7) /* USBDCD */ && \ + !defined(MCU_MK40DZ10) /* USBDCD */ && \ + !defined(MCU_MK40X256VMD100) /* USBDCD */ && \ + !defined(MCU_MK50D10) /* USBDCD */ && \ + !defined(MCU_MK50D7) /* USBDCD */ && \ + !defined(MCU_MK50DZ10) /* USBDCD */ && \ + !defined(MCU_MK51D10) /* USBDCD */ && \ + !defined(MCU_MK51D7) /* USBDCD */ && \ + !defined(MCU_MK51DZ10) /* USBDCD */ && \ + !defined(MCU_MK52D10) /* USBDCD */ && \ + !defined(MCU_MK52DZ10) /* USBDCD */ && \ + !defined(MCU_MK53D10) /* USBDCD */ && \ + !defined(MCU_MK53DZ10) /* USBDCD */ && \ + !defined(MCU_MK60D10) /* USBDCD */ && \ + !defined(MCU_MK60F12) /* USBDCD */ && \ + !defined(MCU_MK60F15) /* USBDCD */ && \ + !defined(MCU_MK60DZ10) /* USBDCD */ && \ + !defined(MCU_MK60N512VMD100) /* USBDCD */ && \ + !defined(MCU_MK61F12) /* USBDCD */ && \ + !defined(MCU_MK61F15) /* USBDCD */ && \ + !defined(MCU_MK61F12WS) /* USBDCD */ && \ + !defined(MCU_MK61F15WS) /* USBDCD */ && \ + !defined(MCU_MK63F12) /* USBDCD */ && \ + !defined(MCU_MK63F12WS) /* USBDCD */ && \ + !defined(MCU_MK64F12) /* USBDCD */ && \ + !defined(MCU_MK65F18) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK65F18WS) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK66F18) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK70F12) /* USBDCD */ && \ + !defined(MCU_MK70F15) /* USBDCD */ && \ + !defined(MCU_MK70F12WS) /* USBDCD */ && \ + !defined(MCU_MK70F15WS) /* USBDCD */ && \ + !defined(MCU_MKW22D5) /* USBDCD */ && \ + !defined(MCU_MKW22D5WS) /* USBDCD */ && \ + !defined(MCU_MKW24D5) /* USBDCD */ && \ + !defined(MCU_MKW24D5WS) /* USBDCD */ && \ + !defined(MCU_PCK20L4) /* USBDCD */ + // Unsupported MCU is active + #error USBDCD PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Status flags constants (for ReadStatusReg macro). */ +#define USBDCD_PDD_ACTIVE_STATUS_INDICATOR USBDCD_STATUS_ACTIVE_MASK /**< Active status indicator - indicates whether the sequence is running */ +#define USBDCD_PDD_TIMEOUT_FLAG USBDCD_STATUS_TO_MASK /**< Timeout flag */ +#define USBDCD_PDD_ERROR_FLAG USBDCD_STATUS_ERR_MASK /**< Error flag */ + +/* Receiver status bits constants */ +#define USBDCD_PDD_DATA_PIN_NOT_DETECTED 0U /**< The module is either not enabled, or the module is enabled but the data pins have not yet been detected */ +#define USBDCD_PDD_DATA_PIN_CONTACT_COMPLETE 0x40000U /**< Data pin contact detection complete */ +#define USBDCD_PDD_CHARGER_PORT_COMPLETE 0x80000U /**< Charger port detection complete */ +#define USBDCD_PDD_CHARGER_TYPE_COMPLETE 0xC0000U /**< Charger type detection complete */ + +/* Receiver status bits constants */ +#define USBDCD_PDD_NO_RESULTS_REPORTED 0U /**< No results to report */ +#define USBDCD_PDD_ATTACHED_TO_HOST 0x10000U /**< Attached to a standard host */ +#define USBDCD_PDD_ATTACHED_TO_CHARGING_PORT 0x20000U /**< Attached to a charging port */ +#define USBDCD_PDD_ATTACHED_TO_DEDICATED_CHARGER 0x30000U /**< Attached to a dedicated charger. */ + + +/* ---------------------------------------------------------------------------- + -- PerformSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Perform a software reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_PerformSoftwareReset(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_PerformSoftwareReset(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_SR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- StartChangeDetectionSequence + ---------------------------------------------------------------------------- */ + +/** + * @brief Initiate the charger detection sequence. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_StartChangeDetectionSequence(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_StartChangeDetectionSequence(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_START_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts to the system. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_EnableInterrupt(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_IE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable interrupts to the system. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_DisableInterrupt(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)USBDCD_CONTROL_IE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(USBDCD_CONTROL_REG(PeripheralBase) & USBDCD_CONTROL_IF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ClearInterruptFlag(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_IACK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadControlReg(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteControlReg(PeripheralBase, Value) ( \ + USBDCD_CONTROL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSpeedInKhz + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the numerical value of clock speed in kHz. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Clock speed in kHz, value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetClockSpeedInKhz(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetClockSpeedInKhz(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_CLOCK_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_SPEED_MASK)) & ( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_UNIT_MASK))))) | ( \ + (uint32)((uint32)(Value) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSpeedInMhz + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the numerical value of clock speed in MHz. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Clock speed in MHz, value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetClockSpeedInMhz(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetClockSpeedInMhz(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_CLOCK_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_SPEED_MASK)))) | (( \ + (uint32)((uint32)(Value) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) | ( \ + USBDCD_CLOCK_CLOCK_UNIT_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadClockReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadClockReg(PeripheralBase) ( \ + USBDCD_CLOCK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into clock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteClockReg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteClockReg(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_GetStatusFlags(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetStatusFlags(PeripheralBase) ( \ + USBDCD_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChargerDetectionSequenceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns charger detection sequence status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receiver status bits constants" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * USBDCD_PDD_GetChargerDetectionSequenceStatus(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetChargerDetectionSequenceStatus(PeripheralBase) ( \ + (uint32)(USBDCD_STATUS_REG(PeripheralBase) & USBDCD_STATUS_SEQ_STAT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChargerDetectionSequenceResults + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns charger detection sequence status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receiver status bits constants" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * USBDCD_PDD_GetChargerDetectionSequenceResults(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetChargerDetectionSequenceResults(PeripheralBase) ( \ + (uint32)(USBDCD_STATUS_REG(PeripheralBase) & USBDCD_STATUS_SEQ_RES_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg + * macro)." for processing return value. + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadStatusReg(PeripheralBase) ( \ + USBDCD_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSequenceInitiationTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the system latency (in ms). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time System latency (in ms) value[0..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetSequenceInitiationTime(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetSequenceInitiationTime(PeripheralBase, Time) ( \ + USBDCD_TIMER0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER0_TSEQ_INIT_MASK)))) | ( \ + (uint32)((uint32)(Time) << USBDCD_TIMER0_TSEQ_INIT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUnitConnectionTimerElapse + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns unit connection timer elapse value (in ms). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 12-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * USBDCD_PDD_GetUnitConnectionTimerElapse(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetUnitConnectionTimerElapse(PeripheralBase) ( \ + (uint16)(USBDCD_TIMER0_REG(PeripheralBase) & USBDCD_TIMER0_TUNITCON_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer0Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer0Reg(PeripheralBase) ( \ + USBDCD_TIMER0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 0 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteTimer0Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer0Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodToDebounceDpSignal + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) to debounce the D+ signal during the data + * pin contact detection phase. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodToDebounceDpSignal(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodToDebounceDpSignal(PeripheralBase, Period) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER1_TDCD_DBNC_MASK)))) | ( \ + (uint32)((uint32)(Period) << USBDCD_TIMER1_TDCD_DBNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodComparator + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) comparator enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodComparator(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodComparator(PeripheralBase, Period) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER1_TVDPSRC_ON_MASK)))) | ( \ + (uint32)(Period))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer1Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer1Reg(PeripheralBase) ( \ + USBDCD_TIMER1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 1 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteTimer1Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer1Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodBeforeEnablingDpPullup + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) before enabling D+ pullup. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodBeforeEnablingDpPullup(_BASE_PTR, + * 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodBeforeEnablingDpPullup(PeripheralBase, Period) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER2_TVDPSRC_CON_MASK)))) | ( \ + (uint32)((uint32)(Period) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimeBeforeCheckDmLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) before check D- line. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Time (in ms) value[1..15]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_SetTimeBeforeCheckDmLine(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimeBeforeCheckDmLine(PeripheralBase, Value) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER2_CHECK_DM_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer2Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer2Reg(PeripheralBase) ( \ + USBDCD_TIMER2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 2 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_WriteTimer2Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer2Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(USBDCD_PDD_H_) */ + +/* USBDCD_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h new file mode 100644 index 0000000..d68f514 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h @@ -0,0 +1,4849 @@ +/* + PDD layer implementation for peripheral type USB + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(USB_PDD_H_) +#define USB_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error USB PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK20D10) /* USB0 */ && \ + !defined(MCU_MK20D5) /* USB0 */ && \ + !defined(MCU_MK20D7) /* USB0 */ && \ + !defined(MCU_MK20F12) /* USB0 */ && \ + !defined(MCU_MK20DZ10) /* USB0 */ && \ + !defined(MCU_MK21D5) /* USB0 */ && \ + !defined(MCU_MK21D5WS) /* USB0 */ && \ + !defined(MCU_MK21F12) /* USB0 */ && \ + !defined(MCU_MK21F12WS) /* USB0 */ && \ + !defined(MCU_MK22D5) /* USB0 */ && \ + !defined(MCU_MK22F12810) /* USB0 */ && \ + !defined(MCU_MK22F12) /* USB0 */ && \ + !defined(MCU_MK22F25612) /* USB0 */ && \ + !defined(MCU_MK22F51212) /* USB0 */ && \ + !defined(MCU_MK24F12) /* USB0 */ && \ + !defined(MCU_MK40D10) /* USB0 */ && \ + !defined(MCU_MK40D7) /* USB0 */ && \ + !defined(MCU_MK40DZ10) /* USB0 */ && \ + !defined(MCU_MK40X256VMD100) /* USB0 */ && \ + !defined(MCU_MK50D10) /* USB0 */ && \ + !defined(MCU_MK50D7) /* USB0 */ && \ + !defined(MCU_MK50DZ10) /* USB0 */ && \ + !defined(MCU_MK51D10) /* USB0 */ && \ + !defined(MCU_MK51D7) /* USB0 */ && \ + !defined(MCU_MK51DZ10) /* USB0 */ && \ + !defined(MCU_MK52D10) /* USB0 */ && \ + !defined(MCU_MK52DZ10) /* USB0 */ && \ + !defined(MCU_MK53D10) /* USB0 */ && \ + !defined(MCU_MK53DZ10) /* USB0 */ && \ + !defined(MCU_MK60D10) /* USB0 */ && \ + !defined(MCU_MK60F12) /* USB0 */ && \ + !defined(MCU_MK60F15) /* USB0 */ && \ + !defined(MCU_MK60DZ10) /* USB0 */ && \ + !defined(MCU_MK60N512VMD100) /* USB0 */ && \ + !defined(MCU_MK61F12) /* USB0 */ && \ + !defined(MCU_MK61F15) /* USB0 */ && \ + !defined(MCU_MK61F12WS) /* USB0 */ && \ + !defined(MCU_MK61F15WS) /* USB0 */ && \ + !defined(MCU_MK63F12) /* USB0 */ && \ + !defined(MCU_MK63F12WS) /* USB0 */ && \ + !defined(MCU_MK64F12) /* USB0 */ && \ + !defined(MCU_MK65F18) /* USB0 */ && \ + !defined(MCU_MK65F18WS) /* USB0 */ && \ + !defined(MCU_MK66F18) /* USB0 */ && \ + !defined(MCU_MK70F12) /* USB0 */ && \ + !defined(MCU_MK70F15) /* USB0 */ && \ + !defined(MCU_MK70F12WS) /* USB0 */ && \ + !defined(MCU_MK70F15WS) /* USB0 */ && \ + !defined(MCU_MKL24Z4) /* USB0 */ && \ + !defined(MCU_MKL25Z4) /* USB0 */ && \ + !defined(MCU_MKL26Z4) /* USB0 */ && \ + !defined(MCU_MKL46Z4) /* USB0 */ && \ + !defined(MCU_MKW22D5) /* USB0 */ && \ + !defined(MCU_MKW22D5WS) /* USB0 */ && \ + !defined(MCU_MKW24D5) /* USB0 */ && \ + !defined(MCU_MKW24D5WS) /* USB0 */ && \ + !defined(MCU_PCK20L4) /* USB0 */ + // Unsupported MCU is active + #error USB PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Otg interrupt masks */ +#define USB_PDD_A_VBUS_CHG_INT USB_OTGICR_AVBUSEN_MASK /**< Vbus change interrupt mask */ +#define USB_PDD_B_SESS_CHG_INT USB_OTGICR_BSESSEN_MASK /**< B session change interrupt mask */ +#define USB_PDD_SESS_VLD_CHG_INT USB_OTGICR_SESSVLDEN_MASK /**< Session valid change interrupt mask */ +#define USB_PDD_LINE_STATE_CHG_INT USB_OTGICR_LINESTATEEN_MASK /**< Line state change interrupt mask */ +#define USB_PDD_1_MSEC_INT USB_OTGICR_ONEMSECEN_MASK /**< 1 ms interrupt mask */ +#define USB_PDD_ID_CHG_INT USB_OTGICR_IDEN_MASK /**< ID change interrupt mask */ + +/* Otg interrupt masks */ +#define USB_PDD_ALL_INT_FLAGS 0xFFU /**< Value used to mask all Otg interrupts */ + +/* Otg status masks */ +#define USB_PDD_A_VBUS_VALID USB_OTGSTAT_AVBUSVLD_MASK /**< A VBus valid signal mask */ +#define USB_PDD_B_SESSION_END USB_OTGSTAT_BSESSEND_MASK /**< B session end signal mask */ +#define USB_PDD_SESSION_VALID USB_OTGSTAT_SESS_VLD_MASK /**< Session valid signal mask */ +#define USB_PDD_LINE_STABLE USB_OTGSTAT_LINESTATESTABLE_MASK /**< Line stable signal mask */ +#define USB_PDD_ID USB_OTGSTAT_ID_MASK /**< ID signal mask */ + +/* Usb interrupt masks */ +#define USB_PDD_STALL_INT USB_INTEN_STALLEN_MASK /**< Stall interrupt mask */ +#define USB_PDD_ATTACH_INT USB_INTEN_ATTACHEN_MASK /**< Attach interrupt mask */ +#define USB_PDD_RESUME_INT USB_INTEN_RESUMEEN_MASK /**< Resume interrupt mask */ +#define USB_PDD_SLEEP_INT USB_INTEN_SLEEPEN_MASK /**< Sleed interrupt mask */ +#define USB_PDD_TOK_DNE_INT USB_INTEN_TOKDNEEN_MASK /**< Token done interrupt mask */ +#define USB_PDD_SOF_TOK_INT USB_INTEN_SOFTOKEN_MASK /**< Star of frame interrupt mask */ +#define USB_PDD_ERROR_INT USB_INTEN_ERROREN_MASK /**< Error interrupt mask */ +#define USB_PDD_USB_RST_INT USB_INTEN_USBRSTEN_MASK /**< Bus reset interrupt mask */ + +/* Error interrupt masks */ +#define USB_PDD_BTS_ERR_INT USB_ERREN_BTSERREN_MASK /**< BTS error interrupt mask */ +#define USB_PDD_DMA_ERR_INT USB_ERREN_DMAERREN_MASK /**< DNA error interrupt mask */ +#define USB_PDD_BTO_ERR_INT USB_ERREN_BTOERREN_MASK /**< BTO errot interrupt mask */ +#define USB_PDD_DFN8_INT USB_ERREN_DFN8EN_MASK /**< DFN8 error interrupt mask */ +#define USB_PDD_CRC16_INT USB_ERREN_CRC16EN_MASK /**< CRC16 interrupt mask */ +#define USB_PDD_CRC5_EOF_INT USB_ERREN_CRC5EOFEN_MASK /**< CRC5 or EOF error interrupt mask */ +#define USB_PDD_PID_ERR_INT USB_ERREN_PIDERREN_MASK /**< PID error interrupt mask */ + +/* Conrol register masks */ +#define USB_PDD_JSTATE USB_CTL_JSTATE_MASK /**< J state mask */ +#define USB_PDD_SE0 USB_CTL_SE0_MASK /**< SE0 mask */ + +/* Otg output signal masks */ +#define USB_PDD_DP_PU_SIGNAL USB_OBSERVE_DPPU_MASK /**< D+ pull-up signal mask */ +#define USB_PDD_DP_PD_SIGNAL USB_OBSERVE_DPPD_MASK /**< D+ pull-down signal mask */ +#define USB_PDD_DM_PD_SIGNAL USB_OBSERVE_DMPD_MASK /**< D- pull-down signal mask */ + +/* Otg input signal masks */ +#define USB_PDD_DEVICE_VBUS_DETECT_SIGNAL USB_CONTROL_DPPULLUPNONOTG_MASK /**< Device mode Vbus detect signal mask */ + +/* Bus speed */ +#define USB_PDD_LOW_SPEED 0U /**< Low speed constant */ +#define USB_PDD_FULL_SPEED 0x80U /**< Full speed constant */ +#define USB_PDD_RESET 0x40U /**< Bus reset state constant */ + + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralIdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral ID register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_PERID. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadPeripheralIdReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralIdReg(PeripheralBase) ( \ + USB_PERID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralIdComplementReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral ID complement register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_IDCOMP. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadPeripheralIdComplementReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralIdComplementReg(PeripheralBase) ( \ + USB_IDCOMP_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralRevisionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral revision register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_REV. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadPeripheralRevisionReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralRevisionReg(PeripheralBase) ( \ + USB_REV_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAdditionalInfoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads additional info register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ADDINFO. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadAdditionalInfoReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadAdditionalInfoReg(PeripheralBase) ( \ + USB_ADDINFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOtgInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetOtgInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetOtgInterruptFlags(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearOtgInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Otg interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearOtgInterruptFlags(_BASE_PTR, + * USB_PDD_A_VBUS_CHG_INT); + * @endcode + */ +#define USB_PDD_ClearOtgInterruptFlags(PeripheralBase, Mask) ( \ + USB_OTGISTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetIdChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ID changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetIdChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetIdChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_IDCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- Get1msInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the 1 ms interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_Get1msInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Get1msInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_ONEMSEC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLineStateChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line state change flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetLineStateChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetLineStateChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_LINE_STATE_CHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Session valalid changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetSessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSessVldChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_SESSVLDCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBsessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the B session end changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetBsessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBsessVldChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_B_SESS_CHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAVbusChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the A Vbus changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetAVbusChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetAVbusChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_AVBUSCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearIdChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the ID changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearIdChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearIdChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_IDCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- Clear1msInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the 1 ms flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_Clear1msInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Clear1msInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_ONEMSEC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearLineStateChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Line state changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearLineStateChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearLineStateChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_LINE_STATE_CHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Session valid changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearSessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSessVldChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_SESSVLDCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBsessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the B session end changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearBsessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBsessVldChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_B_SESS_CHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAVbusChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the A Vbus changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearAVbusChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearAVbusChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_AVBUSCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOtgInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * uint8 result = USB_PDD_GetOtgInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetOtgInterruptMask(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOtgInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Otg interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_SetOtgInterruptMask(_BASE_PTR, + * USB_PDD_A_VBUS_CHG_INT); + * @endcode + */ +#define USB_PDD_SetOtgInterruptMask(PeripheralBase, Mask) ( \ + USB_OTGICR_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIdChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the ID changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableIdChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableIdChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_IDEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- Enable1msInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the 1 ms interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_Enable1msInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Enable1msInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_ONEMSECEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLineStateChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Line stable interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableLineStateChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableLineStateChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_LINESTATEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Session valid changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableSessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_SESSVLDEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBsessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the B session end changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableBsessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBsessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_BSESSEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAVbusChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the A Vbus changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableAVbusChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableAVbusChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_AVBUSEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableIdChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the ID changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableIdChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableIdChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_IDEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- Disable1msInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the 1 ms interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_Disable1msInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Disable1msInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_ONEMSECEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableLineStateChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Line state changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableLineStateChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableLineStateChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_LINESTATEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Session valid changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableSessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_SESSVLDEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBsessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the B session end changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableBsessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBsessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_BSESSEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAVbusChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the A Vbus changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableAVbusChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableAVbusChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_AVBUSEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg status masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgStatusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgStatusReg(PeripheralBase) ( \ + USB_OTGSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- BDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ID bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_BDevice(_BASE_PTR); + * @endcode + */ +#define USB_PDD_BDevice(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_ID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LineStateStable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line stable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_LineStateStable(_BASE_PTR); + * @endcode + */ +#define USB_PDD_LineStateStable(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_LINESTATESTABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SessionValid + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Session valid bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_SessionValid(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SessionValid(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_SESS_VLD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- BSessionEnd + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the B session end bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_BSessionEnd(_BASE_PTR); + * @endcode + */ +#define USB_PDD_BSessionEnd(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_BSESSEND_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- AVBusValid + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the A Vbus valid bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_AVBusValid(_BASE_PTR); + * @endcode + */ +#define USB_PDD_AVBusValid(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_AVBUSVLD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgStstusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgStstusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgStstusReg(PeripheralBase) ( \ + USB_OTGSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLineStateStableState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line stable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetLineStateStableState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetLineStateStableState(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_LINESTATESTABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgControlReg(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_WriteOtgControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgControlReg(PeripheralBase, Value) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDpPullUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D+ pull up. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDpPullUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDpPullUp(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DPHIGH_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DPHIGH_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDpPullDown + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D+ pull down. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDpPullDown(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDpPullDown(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DPLOW_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DPLOW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmPullDown + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D- pull up. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDmPullDown(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDmPullDown(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DMLOW_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DMLOW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVBUS + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBUS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVBUS(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVBUS(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL__MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL__SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOtgTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables OTG termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableOtgTermination(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableOtgTermination(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_OTGEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_OTGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVbusCharge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBus charge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVbusCharge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVbusCharge(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)((uint8)0x1U << 1U)))) | ( \ + (uint8)((uint8)(State) << 1U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVbusDischarge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBus discharge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVbusDischarge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVbusDischarge(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)0x1U))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeviceModeFullSpeedTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets full speed device termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetDeviceModeFullSpeedTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetDeviceModeFullSpeedTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + USB_OTGCTL_REG(PeripheralBase)) | (( \ + USB_OTGCTL_DPHIGH_MASK) | ( \ + USB_OTGCTL_OTGEN_MASK)))) & (( \ + (uint8)(~(uint8)USB_OTGCTL_DPLOW_MASK)) & ( \ + (uint8)(~(uint8)USB_OTGCTL_DMLOW_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHostModeTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets full speed host termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetHostModeTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetHostModeTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + 0x34U \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNoTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables all pull resistors. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetNoTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetNoTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + 0x4U \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUsbInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Usb interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Usb interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetUsbInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetUsbInterruptFlags(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearUsbInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Usb interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearUsbInterruptFlags(_BASE_PTR, + * USB_PDD_STALL_INT); + * @endcode + */ +#define USB_PDD_ClearUsbInterruptFlags(PeripheralBase, Mask) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStallInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Stall interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetStallInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetStallInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_STALL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAttachInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Attach interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetAttachInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetAttachInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_ATTACH_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetResumeInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResumeInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_RESUME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSuspendInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Suspend interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetSuspendInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSuspendInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_SLEEP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTokenDoneInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Token done interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetTokenDoneInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTokenDoneInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_TOKDNE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSofInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Sof interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetSofInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSofInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_SOFTOK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_ERROR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusResetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Bus reset interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetBusResetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBusResetInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_USBRST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStallInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Stall interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearStallInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearStallInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_STALL_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAttachInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Attach interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearAttachInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearAttachInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_ATTACH_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearResumeInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearResumeInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_RESUME_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSuspendInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Suspend interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearSuspendInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSuspendInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_SLEEP_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTokenDoneInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Token done interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearTokenDoneInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTokenDoneInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_TOKDNE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSofInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Sof interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearSofInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSofInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_SOFTOK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearErrorInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearErrorInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_ERROR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBusResetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Bus reset interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearBusResetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBusResetInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_USBRST_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUsbInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Usb interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Usb interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * uint8 result = USB_PDD_GetUsbInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetUsbInterruptMask(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetUsbInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Usb interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_SetUsbInterruptMask(_BASE_PTR, USB_PDD_STALL_INT); + * @endcode + */ +#define USB_PDD_SetUsbInterruptMask(PeripheralBase, Mask) ( \ + USB_INTEN_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStallInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Stall interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableStallInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableStallInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_STALLEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAttachInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Attach interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableAttachInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableAttachInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_ATTACHEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableResumeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Reume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableResumeInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableResumeInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_RESUMEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSuspendInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Suspend interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableSuspendInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSuspendInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_SLEEPEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTokenDoneInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Token done interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableTokenDoneInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableTokenDoneInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_TOKDNEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSofInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Sof interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableSofInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSofInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_SOFTOKEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableErrorInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_ERROREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusResetInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Bus reset interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableBusResetInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBusResetInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_USBRSTEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableStallInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Stall interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableStallInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableStallInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_STALLEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAttachInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Attach interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableAttachInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableAttachInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_ATTACHEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableResumeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableResumeInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableResumeInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_RESUMEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSuspendInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Suspend interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableSuspendInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSuspendInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_SLEEPEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTokenDoneInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Token done interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableTokenDoneInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableTokenDoneInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_TOKDNEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSofInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Sof interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableSofInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSofInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_SOFTOKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableErrorInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_ERROREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusResetInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Bus reset interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableBusResetInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBusResetInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_USBRSTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorsInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Error interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Error interrupt masks" for processing + * return value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorsInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorsInterruptFlags(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorsInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Error interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearErrorsInterruptFlags(_BASE_PTR, + * USB_PDD_BTS_ERR_INT); + * @endcode + */ +#define USB_PDD_ClearErrorsInterruptFlags(PeripheralBase, Mask) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBtsErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the BTS error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetBtsErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBtsErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_BTSERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDmaErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DMA error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDmaErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDmaErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_DMAERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBtoErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the BTO error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetBtoErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBtoErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_BTOERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDnf8ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DNF8 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDnf8ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDnf8ErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_DFN8_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCrc16ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CRC16 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetCrc16ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetCrc16ErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_CRC16_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCrc5EofErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CRC5 or EOF error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetCrc5EofErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetCrc5EofErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_CRC5EOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPidErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PID error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetPidErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetPidErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_PIDERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBtsErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the BTS error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearBtsErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBtsErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_BTSERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDmaErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the DMA error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearDmaErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearDmaErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_DMAERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBtoErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the BTO error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearBtoErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBtoErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDnf8ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the DFN8 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearDnf8ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearDnf8ErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCrc16ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the CRC16 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearCrc16ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearCrc16ErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCrc5EofErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the CRC5 or EOF error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearCrc5EofErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearCrc5EofErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPidErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PID error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearPidErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearPidErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBtsErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the BTS error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableBtsErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBtsErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_BTSERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DMA error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableDmaErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableDmaErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_DMAERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBtoErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the BTO error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableBtoErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBtoErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_BTOERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDnf8ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DNF8 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableDnf8ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableDnf8ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_DFN8EN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrc16ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CRC16 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableCrc16ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableCrc16ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_CRC16EN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrc5EofErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CRC5 or EOF error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableCrc5EofErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableCrc5EofErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_CRC5EOFEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePidErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PID error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnablePidErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnablePidErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_PIDERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBtsErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the BTS error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableBtsErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBtsErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_BTSERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDmaErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DMA error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableDmaErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableDmaErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_DMAERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBtoErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the BTO error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableBtoErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBtoErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_BTOERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDnf8ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DNF8 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableDnf8ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableDnf8ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_DFN8EN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableCrc16ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CRC16 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableCrc16ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableCrc16ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_CRC16EN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableCrc5EofErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CRC5 or EOF error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableCrc5EofErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableCrc5EofErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_CRC5EOFEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisablePidErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the PID error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisablePidErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisablePidErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_PIDERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Error interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Error interrupt masks" for processing + * return value. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorInterruptMask(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Error interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_SetErrorInterruptMask(_BASE_PTR, + * USB_PDD_BTS_ERR_INT); + * @endcode + */ +#define USB_PDD_SetErrorInterruptMask(PeripheralBase, Mask) ( \ + USB_ERREN_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_STAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadStatusReg(PeripheralBase) ( \ + USB_STAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransmitIndicator + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the TX bit in the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_STAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetTransmitIndicator(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTransmitIndicator(PeripheralBase) ( \ + (uint8)(USB_STAT_REG(PeripheralBase) & USB_STAT_TX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadControlReg(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Control register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteControlReg(PeripheralBase, Value) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusSpeed + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current bus speed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Bus speed" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetBusSpeed(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBusSpeed(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)((uint8)0x3U << 6U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSE0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the SEO signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetSE0(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSE0(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_SE0_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Device mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDevice(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_USBENSOFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSof + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SOF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableSof(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableSof(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_USBENSOFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetBdtPingPong + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets internal logic. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ResetBdtPingPong(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ResetBdtPingPong(PeripheralBase) ( \ + (USB_CTL_REG(PeripheralBase) |= \ + USB_CTL_ODDRST_MASK), \ + (USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_ODDRST_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartResumeSignaling + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts/stops resume signaling. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_StartResumeSignaling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StartResumeSignaling(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_RESUME_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_RESUME_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResumeSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of resume enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetResumeSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResumeSignalState(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_RESUME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHost + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Host mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableHost(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableHost(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_HOSTMODEEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_HOSTMODEEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartResetSignaling + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts/stops reset signaling. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_StartResetSignaling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StartResetSignaling(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_RESET_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_RESET_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResetSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of reset enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetResetSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResetSignalState(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_RESET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxSuspendFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears TxSuspend flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ClearTxSuspendFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTxSuspendFlag(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTokenBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears TokenBusy flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ClearTokenBusyFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTokenBusyFlag(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTokenBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of TokenBusy flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetTokenBusyFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTokenBusyFlag(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableModule + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables module. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_DisableModule(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableModule(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) = \ + 0U \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadAddressReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadAddressReg(PeripheralBase) ( \ + USB_ADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Address register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_WriteAddressReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteAddressReg(PeripheralBase, Value) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowSpeed + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables low speed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_EnableLowSpeed(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableLowSpeed(PeripheralBase, State) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ADDR_REG(PeripheralBase) & (uint8)(~(uint8)USB_ADDR_LSEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_ADDR_LSEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeviceAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets device address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address New device address. This parameter is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_SetDeviceAddress(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetDeviceAddress(PeripheralBase, Address) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ADDR_REG(PeripheralBase) & (uint8)(~(uint8)USB_ADDR_ADDR_MASK))) | ( \ + (uint8)(Address))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE1. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage1Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage1Reg(PeripheralBase) ( \ + USB_BDTPAGE1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 1 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE1. + * @par Example: + * @code + * USB_PDD_WriteBdtPage1Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage1Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFrameNumberLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame number low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_FRMNUML. + * @par Example: + * @code + * uint8 result = USB_PDD_GetFrameNumberLow(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetFrameNumberLow(PeripheralBase) ( \ + USB_FRMNUML_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameNumberLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Frame number low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the low part of the Frame number register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_FRMNUML. + * @par Example: + * @code + * USB_PDD_SetFrameNumberLow(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameNumberLow(PeripheralBase, Data) ( \ + USB_FRMNUML_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFrameNumberHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame number high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_FRMNUMH. + * @par Example: + * @code + * uint8 result = USB_PDD_GetFrameNumberHigh(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetFrameNumberHigh(PeripheralBase) ( \ + USB_FRMNUMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameNumberHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Frame number high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the high part of the Frame number register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_FRMNUMH. + * @par Example: + * @code + * USB_PDD_SetFrameNumberHigh(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameNumberHigh(PeripheralBase, Data) ( \ + USB_FRMNUMH_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTokenReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Token register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_TOKEN. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadTokenReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadTokenReg(PeripheralBase) ( \ + USB_TOKEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTokenReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Token register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Token register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_TOKEN. + * @par Example: + * @code + * USB_PDD_WriteTokenReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteTokenReg(PeripheralBase, Data) ( \ + USB_TOKEN_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSofTresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Sof treshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_SOFTHLD. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadSofTresholdReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadSofTresholdReg(PeripheralBase) ( \ + USB_SOFTHLD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSofTresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Sof theshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Sof treshold register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_SOFTHLD. + * @par Example: + * @code + * USB_PDD_SetSofTresholdReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetSofTresholdReg(PeripheralBase, Data) ( \ + USB_SOFTHLD_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE2. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage2Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage2Reg(PeripheralBase) ( \ + USB_BDTPAGE2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 2 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE2. + * @par Example: + * @code + * USB_PDD_WriteBdtPage2Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage2Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE3. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage3Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage3Reg(PeripheralBase) ( \ + USB_BDTPAGE3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 3 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE3. + * @par Example: + * @code + * USB_PDD_WriteBdtPage3Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage3Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEp0CtrlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the EP0 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadEp0CtrlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadEp0CtrlReg(PeripheralBase) ( \ + USB_ENDPT_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEp0CtrlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the EP0 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the EP0 control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * USB_PDD_WriteEp0CtrlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteEp0CtrlReg(PeripheralBase, Data) ( \ + USB_ENDPT_REG(PeripheralBase,0U) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEpCtrlRegAddr + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the EP_x register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * uint32 result = USB_PDD_GetEpCtrlRegAddr(_BASE_PTR, + * periphID); + * @endcode + */ +#define USB_PDD_GetEpCtrlRegAddr(PeripheralBase, EpNum) ( \ + (uint8 *)(void *)&(USB_ENDPT_REG(PeripheralBase,(EpNum))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDirectLowSpeedDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables direct low speed device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * USB_PDD_EnableDirectLowSpeedDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDirectLowSpeedDevice(PeripheralBase, State) ( \ + USB_ENDPT_REG(PeripheralBase,0U) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,0U)) & ( \ + (uint8)(~(uint8)USB_ENDPT_HOSTWOHUB_MASK)))) | ( \ + (uint8)((uint8)(State) << USB_ENDPT_HOSTWOHUB_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- StallControlEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Stall feature for given EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_StallControlEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StallControlEP(PeripheralBase, EpNum, State) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)))) | ( \ + (uint8)((uint8)(State) << USB_ENDPT_EPSTALL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableControlEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Control EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableControlEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableControlEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPCTLDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK)))))))) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPCTLDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)))))) | (( \ + USB_ENDPT_EPRXEN_MASK) | (( \ + USB_ENDPT_EPTXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBulkOrIntRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Bulk or Interrupt Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableBulkOrIntRxEP(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableBulkOrIntRxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | (( \ + USB_ENDPT_EPRXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBulkOrIntTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Bulk or Interrupt Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableBulkOrIntTxEP(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableBulkOrIntTxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | (( \ + USB_ENDPT_EPTXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIsoRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Isochronous Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableIsoRxEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableIsoRxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK)))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | ( \ + USB_ENDPT_EPRXEN_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIsoTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Isochronous Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableIsoTxEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableIsoTxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_HOSTWOHUB_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK))))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | ( \ + USB_ENDPT_EPTXEN_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_DisableRxEP(_BASE_PTR, periphID); + * @endcode + */ +#define USB_PDD_DisableRxEP(PeripheralBase, EpNum) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_DisableTxEP(_BASE_PTR, periphID); + * @endcode + */ +#define USB_PDD_DisableTxEP(PeripheralBase, EpNum) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUsbControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the USB control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadUsbControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadUsbControlReg(PeripheralBase) ( \ + USB_USBCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteUsbControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Usb control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Usb control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_WriteUsbControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteUsbControlReg(PeripheralBase, Value) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SuspendTransceiver + ---------------------------------------------------------------------------- */ + +/** + * @brief Suspends/Wakes up transceiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_SuspendTransceiver(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_SuspendTransceiver(PeripheralBase, State) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_USBCTRL_REG(PeripheralBase) & (uint8)(~(uint8)USB_USBCTRL_SUSP_MASK))) | ( \ + (uint8)((uint8)(State) << USB_USBCTRL_SUSP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWeakPullDowns + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables week pull downs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_EnableWeakPullDowns(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableWeakPullDowns(PeripheralBase, State) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_USBCTRL_REG(PeripheralBase) & (uint8)(~(uint8)USB_USBCTRL_PDE_MASK))) | ( \ + (uint8)((uint8)(State) << USB_USBCTRL_PDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgSignalObserveReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns content of the Otg observe register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgSignalObserveReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgSignalObserveReg(PeripheralBase) ( \ + USB_OBSERVE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgSignalObservelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the OTG observe register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg observel register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * USB_PDD_WriteOtgSignalObservelReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgSignalObservelReg(PeripheralBase, Value) ( \ + USB_OBSERVE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDpPullUpSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D+ pull up signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDpPullUpSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDpPullUpSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DPPU_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDpPullDownSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D+ pull down signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetDpPullDownSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDpPullDownSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DPPD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDmPullDownSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D- pull up signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetDmPullDownSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDmPullDownSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DMPD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgSignalControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CONTROL. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgSignalControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgSignalControlReg(PeripheralBase) ( \ + USB_CONTROL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgSignalControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the OTG control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CONTROL. + * @par Example: + * @code + * USB_PDD_WriteOtgSignalControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgSignalControlReg(PeripheralBase, Value) ( \ + USB_CONTROL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransceiverControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Transceiver control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadTransceiverControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadTransceiverControlReg(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransceiverControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Transceiver control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Transceiver control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_WriteTransceiverControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteTransceiverControlReg(PeripheralBase, Value) ( \ + USB_USBTRC0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetModule + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Starts module reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ResetModule(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ResetModule(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_USBRESET_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Starts module reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ResetModule(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ResetModule(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_USBRESET_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetModuleResetPendingFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of module reset pending flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetModuleResetPendingFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetModuleResetPendingFlag(PeripheralBase) ( \ + (uint8)(USB_USBTRC0_REG(PeripheralBase) & USB_USBTRC0_USBRESET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAsyncResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Clears asynchronous resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ClearAsyncResumeInterruptFlag(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ClearAsyncResumeInterruptFlag(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_SYNC_DET_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears asynchronous resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ClearAsyncResumeInterruptFlag(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ClearAsyncResumeInterruptFlag(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_SYNC_DET_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableAsyncResumeInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Enables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_EnableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_EnableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_USBRESMEN_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_EnableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_EnableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_USBRESMEN_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableAsyncResumeInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Disables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_DisableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_DisableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + USB_USBTRC0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)USB_USBTRC0_USBRESMEN_MASK)))) | ( \ + 0x40U)) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_DisableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_DisableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_USBTRC0_USBRESMEN_MASK) \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadFrameAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame Adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadFrameAdjustmentReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadFrameAdjustmentReg(PeripheralBase) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFrameAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Frame adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Frame adjustment register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * USB_PDD_WriteFrameAdjustmentReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteFrameAdjustmentReg(PeripheralBase, Value) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame adjustment. In Host mode, the frame adjustment is a twos + * complement number that adjusts the period of each USB frame in 12-MHz clock + * periods. A SOF is normally generated every 12,000 12-MHz clock cycles. The Frame + * Adjust Register can adjust this by -128 to +127 to compensate for inaccuracies + * in the USB 48-MHz clock. Changes to the ADJ bit take effect at the next start + * of the next frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Frame adjustment register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * USB_PDD_SetFrameAdjustment(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameAdjustment(PeripheralBase, Value) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(USB_PDD_H_) */ + +/* USB_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h new file mode 100644 index 0000000..302124e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h @@ -0,0 +1,413 @@ +/* + PDD layer implementation for peripheral type VREF + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(VREF_PDD_H_) +#define VREF_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error VREF PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* VREF */ && \ + !defined(MCU_MK10D5) /* VREF */ && \ + !defined(MCU_MK10D7) /* VREF */ && \ + !defined(MCU_MK10F12) /* VREF */ && \ + !defined(MCU_MK10DZ10) /* VREF */ && \ + !defined(MCU_MK11D5) /* VREF */ && \ + !defined(MCU_MK11D5WS) /* VREF */ && \ + !defined(MCU_MK12D5) /* VREF */ && \ + !defined(MCU_MK20D10) /* VREF */ && \ + !defined(MCU_MK20D5) /* VREF */ && \ + !defined(MCU_MK20D7) /* VREF */ && \ + !defined(MCU_MK20F12) /* VREF */ && \ + !defined(MCU_MK20DZ10) /* VREF */ && \ + !defined(MCU_MK21D5) /* VREF */ && \ + !defined(MCU_MK21D5WS) /* VREF */ && \ + !defined(MCU_MK21F12) /* VREF */ && \ + !defined(MCU_MK21F12WS) /* VREF */ && \ + !defined(MCU_MK22D5) /* VREF */ && \ + !defined(MCU_MK22F12810) /* VREF */ && \ + !defined(MCU_MK22F12) /* VREF */ && \ + !defined(MCU_MK22F25612) /* VREF */ && \ + !defined(MCU_MK22F51212) /* VREF */ && \ + !defined(MCU_MK24F12) /* VREF */ && \ + !defined(MCU_MK30D10) /* VREF */ && \ + !defined(MCU_MK30D7) /* VREF */ && \ + !defined(MCU_MK30DZ10) /* VREF */ && \ + !defined(MCU_MK40D10) /* VREF */ && \ + !defined(MCU_MK40D7) /* VREF */ && \ + !defined(MCU_MK40DZ10) /* VREF */ && \ + !defined(MCU_MK40X256VMD100) /* VREF */ && \ + !defined(MCU_MK50D10) /* VREF */ && \ + !defined(MCU_MK50D7) /* VREF */ && \ + !defined(MCU_MK50DZ10) /* VREF */ && \ + !defined(MCU_MK51D10) /* VREF */ && \ + !defined(MCU_MK51D7) /* VREF */ && \ + !defined(MCU_MK51DZ10) /* VREF */ && \ + !defined(MCU_MK52D10) /* VREF */ && \ + !defined(MCU_MK52DZ10) /* VREF */ && \ + !defined(MCU_MK53D10) /* VREF */ && \ + !defined(MCU_MK53DZ10) /* VREF */ && \ + !defined(MCU_MK60D10) /* VREF */ && \ + !defined(MCU_MK60F12) /* VREF */ && \ + !defined(MCU_MK60F15) /* VREF */ && \ + !defined(MCU_MK60DZ10) /* VREF */ && \ + !defined(MCU_MK60N512VMD100) /* VREF */ && \ + !defined(MCU_MK61F12) /* VREF */ && \ + !defined(MCU_MK61F15) /* VREF */ && \ + !defined(MCU_MK61F12WS) /* VREF */ && \ + !defined(MCU_MK61F15WS) /* VREF */ && \ + !defined(MCU_MK63F12) /* VREF */ && \ + !defined(MCU_MK63F12WS) /* VREF */ && \ + !defined(MCU_MK64F12) /* VREF */ && \ + !defined(MCU_MK65F18) /* VREF */ && \ + !defined(MCU_MK65F18WS) /* VREF */ && \ + !defined(MCU_MK66F18) /* VREF */ && \ + !defined(MCU_MK70F12) /* VREF */ && \ + !defined(MCU_MK70F15) /* VREF */ && \ + !defined(MCU_MK70F12WS) /* VREF */ && \ + !defined(MCU_MK70F15WS) /* VREF */ && \ + !defined(MCU_MKL03Z4) /* VREF */ && \ + !defined(MCU_MKV31F12810) /* VREF */ && \ + !defined(MCU_MKV31F25612) /* VREF */ && \ + !defined(MCU_MKV31F51212) /* VREF */ && \ + !defined(MCU_PCK20L4) /* VREF */ + // Unsupported MCU is active + #error VREF PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Position of a parity bit */ +#define VREF_PDD_DISABLED_OR_NOT_STABLE 0U /**< The module is disabled or not stable. */ +#define VREF_PDD_STABLE 0x4U /**< The module is stable. */ + +/* Type of the buffer mode. */ +#define VREF_PDD_BANDGAP_ON_ONLY 0U /**< Bandgap on only, for stabilization and startup. */ +#define VREF_PDD_HIGH_POWER_BUFFER 0x1U /**< High power buffer mode enabled. */ +#define VREF_PDD_LOW_POWER_BUFFER 0x2U /**< Low power buffer mode enabled. */ + + +/* ---------------------------------------------------------------------------- + -- EnableChopOscillator + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables chop oscillator. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables chop oscillator. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_EnableChopOscillator(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableChopOscillator(PeripheralBase, State) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & (uint8)(~(uint8)VREF_TRM_CHOPEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_TRM_CHOPEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTrimValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Set trim value for voltage reference correction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Trim value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_SetTrimValue(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_SetTrimValue(PeripheralBase, Value) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & (uint8)(~(uint8)VREF_TRM_TRIM_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTrimValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns trim value for voltage reference correction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * uint8 result = VREF_PDD_GetTrimValue(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_GetTrimValue(PeripheralBase) ( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & VREF_TRM_TRIM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * uint8 result = VREF_PDD_ReadTrimReg(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_ReadTrimReg(PeripheralBase) ( \ + VREF_TRM_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the trim register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_WriteTrimReg(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_WriteTrimReg(PeripheralBase, Value) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInternalVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables internal voltage reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables internal voltage reference. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableInternalVoltageReference(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableInternalVoltageReference(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_VREFEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_VREFEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRegulator + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables regulator. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables regulator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableRegulator(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableRegulator(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_REGEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_REGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondOrderCurvatureCompensation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables second order curvature compensation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables second order curvature compensation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableSecondOrderCurvatureCompensation(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableSecondOrderCurvatureCompensation(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_ICOMPEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_ICOMPEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInternalVoltageReferenceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the internal voltage reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Position of a parity bit" type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * uint8 result = + * VREF_PDD_GetInternalVoltageReferenceState(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_GetInternalVoltageReferenceState(PeripheralBase) ( \ + (uint8)(VREF_SC_REG(PeripheralBase) & VREF_SC_VREFST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectBufferMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects buffer mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Type of the match operation. This parameter is of "Type of the + * buffer mode." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_SelectBufferMode(_BASE_PTR, + * VREF_PDD_BANDGAP_ON_ONLY); + * @endcode + */ +#define VREF_PDD_SelectBufferMode(PeripheralBase, Mode) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_MODE_LV_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * uint8 result = VREF_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_ReadStatusControlReg(PeripheralBase) ( \ + VREF_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status and + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status and control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(VREF_PDD_H_) */ + +/* VREF_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h new file mode 100644 index 0000000..e1ce443 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h @@ -0,0 +1,1526 @@ +/* + PDD layer implementation for peripheral type WDOG + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(WDOG_PDD_H_) +#define WDOG_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error WDOG PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* WDOG */ && \ + !defined(MCU_MK10D5) /* WDOG */ && \ + !defined(MCU_MK10D7) /* WDOG */ && \ + !defined(MCU_MK10F12) /* WDOG */ && \ + !defined(MCU_MK10DZ10) /* WDOG */ && \ + !defined(MCU_MK11D5) /* WDOG */ && \ + !defined(MCU_MK11D5WS) /* WDOG */ && \ + !defined(MCU_MK12D5) /* WDOG */ && \ + !defined(MCU_MK20D10) /* WDOG */ && \ + !defined(MCU_MK20D5) /* WDOG */ && \ + !defined(MCU_MK20D7) /* WDOG */ && \ + !defined(MCU_MK20F12) /* WDOG */ && \ + !defined(MCU_MK20DZ10) /* WDOG */ && \ + !defined(MCU_MK21D5) /* WDOG */ && \ + !defined(MCU_MK21D5WS) /* WDOG */ && \ + !defined(MCU_MK21F12) /* WDOG */ && \ + !defined(MCU_MK21F12WS) /* WDOG */ && \ + !defined(MCU_MK22D5) /* WDOG */ && \ + !defined(MCU_MK22F12810) /* WDOG */ && \ + !defined(MCU_MK22F12) /* WDOG */ && \ + !defined(MCU_MK22F25612) /* WDOG */ && \ + !defined(MCU_MK22F51212) /* WDOG */ && \ + !defined(MCU_MK24F12) /* WDOG */ && \ + !defined(MCU_MK30D10) /* WDOG */ && \ + !defined(MCU_MK30D7) /* WDOG */ && \ + !defined(MCU_MK30DZ10) /* WDOG */ && \ + !defined(MCU_MK40D10) /* WDOG */ && \ + !defined(MCU_MK40D7) /* WDOG */ && \ + !defined(MCU_MK40DZ10) /* WDOG */ && \ + !defined(MCU_MK40X256VMD100) /* WDOG */ && \ + !defined(MCU_MK50D10) /* WDOG */ && \ + !defined(MCU_MK50D7) /* WDOG */ && \ + !defined(MCU_MK50DZ10) /* WDOG */ && \ + !defined(MCU_MK51D10) /* WDOG */ && \ + !defined(MCU_MK51D7) /* WDOG */ && \ + !defined(MCU_MK51DZ10) /* WDOG */ && \ + !defined(MCU_MK52D10) /* WDOG */ && \ + !defined(MCU_MK52DZ10) /* WDOG */ && \ + !defined(MCU_MK53D10) /* WDOG */ && \ + !defined(MCU_MK53DZ10) /* WDOG */ && \ + !defined(MCU_MK60D10) /* WDOG */ && \ + !defined(MCU_MK60F12) /* WDOG */ && \ + !defined(MCU_MK60F15) /* WDOG */ && \ + !defined(MCU_MK60DZ10) /* WDOG */ && \ + !defined(MCU_MK60N512VMD100) /* WDOG */ && \ + !defined(MCU_MK61F12) /* WDOG */ && \ + !defined(MCU_MK61F15) /* WDOG */ && \ + !defined(MCU_MK61F12WS) /* WDOG */ && \ + !defined(MCU_MK61F15WS) /* WDOG */ && \ + !defined(MCU_MK63F12) /* WDOG */ && \ + !defined(MCU_MK63F12WS) /* WDOG */ && \ + !defined(MCU_MK64F12) /* WDOG */ && \ + !defined(MCU_MK65F18) /* WDOG */ && \ + !defined(MCU_MK65F18WS) /* WDOG */ && \ + !defined(MCU_MK66F18) /* WDOG */ && \ + !defined(MCU_MK70F12) /* WDOG */ && \ + !defined(MCU_MK70F15) /* WDOG */ && \ + !defined(MCU_MK70F12WS) /* WDOG */ && \ + !defined(MCU_MK70F15WS) /* WDOG */ && \ + !defined(MCU_MKE02Z2) /* WDOG */ && \ + !defined(MCU_MKE02Z4) /* WDOG */ && \ + !defined(MCU_SKEAZN642) /* WDOG */ && \ + !defined(MCU_MKE04Z1284) /* WDOG */ && \ + !defined(MCU_MKE04Z4) /* WDOG */ && \ + !defined(MCU_SKEAZN84) /* WDOG */ && \ + !defined(MCU_MKE06Z4) /* WDOG */ && \ + !defined(MCU_MKV10Z7) /* WDOG */ && \ + !defined(MCU_MKV31F12810) /* WDOG */ && \ + !defined(MCU_MKV31F25612) /* WDOG */ && \ + !defined(MCU_MKV31F51212) /* WDOG */ && \ + !defined(MCU_MKW21D5) /* WDOG */ && \ + !defined(MCU_MKW21D5WS) /* WDOG */ && \ + !defined(MCU_MKW22D5) /* WDOG */ && \ + !defined(MCU_MKW22D5WS) /* WDOG */ && \ + !defined(MCU_MKW24D5) /* WDOG */ && \ + !defined(MCU_MKW24D5WS) /* WDOG */ && \ + !defined(MCU_PCK20L4) /* WDOG */ && \ + !defined(MCU_SKEAZ1284) /* WDOG */ + // Unsupported MCU is active + #error WDOG PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Windowing mode constants */ + #define WDOG_PDD_WINDOWING_DISABLED 0U /**< Disabled */ + #define WDOG_PDD_WINDOWING_ENABLED WDOG_CS2_WIN_MASK /**< Enabled */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Windowing mode constants */ + #define WDOG_PDD_WINDOWING_DISABLED 0U /**< Disabled */ + #define WDOG_PDD_WINDOWING_ENABLED WDOG_STCTRLH_WINEN_MASK /**< Enabled */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Clock source constants. */ + #define WDOG_PDD_SOURCE_BUSCLOCK 0U /**< Use bus clock as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_LPOCLK 0x1U /**< Use 1 kHz internal low-power oscillator as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_ICSIRCLK 0x2U /**< Use 32 kHz internal oscillator as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_ERCLK 0x3U /**< Use external clock as a clock source for the watchdog counter */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock source constants. */ + #define WDOG_PDD_SOURCE_DEDICATED 0U /**< Dedicated */ + #define WDOG_PDD_SOURCE_ALTERNATE WDOG_STCTRLH_CLKSRC_MASK /**< Alternate */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Refresh constants */ + #define WDOG_PDD_KEY_1 0x2A6U /**< First key of the refresh sequence */ + #define WDOG_PDD_KEY_2 0x80B4U /**< Second key of the refresh sequence */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Refresh constants */ + #define WDOG_PDD_KEY_1 0xA602U /**< First key of the refresh sequence */ + #define WDOG_PDD_KEY_2 0xB480U /**< Second key of the refresh sequence */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Unlock constants */ + #define WDOG_PDD_UNLOCK_1 0x20C5U /**< First key of the unlock sequence */ + #define WDOG_PDD_UNLOCK_2 0x28D9U /**< Second key of the unlock sequence */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Unlock constants */ + #define WDOG_PDD_UNLOCK_1 0xC520U /**< First key of the unlock sequence */ + #define WDOG_PDD_UNLOCK_2 0xD928U /**< Second key of the unlock sequence */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Reference clock prescaler constants */ + #define WDOG_PDD_DIVIDE_1 0U /**< Prescaler factor 1 */ + #define WDOG_PDD_DIVIDE_256 0x1U /**< Prescaler factor 256 */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Reference clock prescaler constants */ + #define WDOG_PDD_DIVIDE_1 0U /**< Prescaler factor 1 */ + #define WDOG_PDD_DIVIDE_2 0x1U /**< Prescaler factor 2 */ + #define WDOG_PDD_DIVIDE_3 0x2U /**< Prescaler factor 3 */ + #define WDOG_PDD_DIVIDE_4 0x3U /**< Prescaler factor 4 */ + #define WDOG_PDD_DIVIDE_5 0x4U /**< Prescaler factor 5 */ + #define WDOG_PDD_DIVIDE_6 0x5U /**< Prescaler factor 6 */ + #define WDOG_PDD_DIVIDE_7 0x6U /**< Prescaler factor 7 */ + #define WDOG_PDD_DIVIDE_8 0x7U /**< Prescaler factor 8 */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetAllowUpdateStatus + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns non-zero if watchdog registers can be unlocked. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetAllowUpdateStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetAllowUpdateStatus(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_UPDATE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns non-zero if watchdog registers can be unlocked. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetAllowUpdateStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetAllowUpdateStatus(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_ALLOWUPDATE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableUpdate + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief No further updates allowed to WDOG write once registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableUpdate(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableUpdate(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)WDOG_CS1_UPDATE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief No further updates allowed to WDOG write once registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableUpdate(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableUpdate(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) &= \ + (uint16)(~(uint16)WDOG_STCTRLH_ALLOWUPDATE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetWindowingMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Configures the windowing mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Windowing mode + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetWindowingMode(_BASE_PTR, + * WDOG_PDD_WINDOWING_DISABLED); + * @endcode + */ + #define WDOG_PDD_SetWindowingMode(PeripheralBase, Mode) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + WDOG_CS2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)WDOG_CS2_WIN_MASK)) & ( \ + (uint8)(~(uint8)WDOG_CS2_FLG_MASK))))) | ( \ + (uint8)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the windowing mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Windowing mode + * constants". This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetWindowingMode(_BASE_PTR, + * WDOG_PDD_WINDOWING_DISABLED); + * @endcode + */ + #define WDOG_PDD_SetWindowingMode(PeripheralBase, Mode) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_WINEN_MASK)))) | ( \ + (uint16)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_INT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_IRQRSTEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_EnableInterrupt(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) |= \ + WDOG_CS1_INT_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_EnableInterrupt(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) |= \ + WDOG_STCTRLH_IRQRSTEN_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableInterrupt(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)WDOG_CS1_INT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableInterrupt(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) &= \ + (uint16)(~(uint16)WDOG_STCTRLH_IRQRSTEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectClockSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Clock source + * constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SelectClockSource(_BASE_PTR, + * WDOG_PDD_SOURCE_BUSCLOCK); + * @endcode + */ + #define WDOG_PDD_SelectClockSource(PeripheralBase, Source) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + WDOG_CS2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)WDOG_CS2_CLK_MASK)) & ( \ + (uint8)(~(uint8)WDOG_CS2_FLG_MASK))))) | ( \ + (uint8)(Source))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Clock source + * constants.". This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SelectClockSource(_BASE_PTR, + * WDOG_PDD_SOURCE_DEDICATED); + * @endcode + */ + #define WDOG_PDD_SelectClockSource(PeripheralBase, Source) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_CLKSRC_MASK)))) | ( \ + (uint16)(Source))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of WDOG device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define WDOG_PDD_EnableDevice(PeripheralBase, State) ( \ + WDOG_CS1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & (uint8)(~(uint8)WDOG_CS1_EN_MASK))) | ( \ + (uint8)((uint8)(State) << WDOG_CS1_EN_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of WDOG device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define WDOG_PDD_EnableDevice(PeripheralBase, State) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_WDOGEN_MASK)))) | ( \ + (uint16)(State))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_EN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_WDOGEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog status and control register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog status and control register high. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH. + * @par Example: + * @code + * WDOG_PDD_WriteControlHighReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteControlHighReg(PeripheralBase, Value) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog status and control register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadControlHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadControlHighReg(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint8)(WDOG_CS2_REG(PeripheralBase) & WDOG_CS2_FLG_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLL_REG(PeripheralBase) & WDOG_STCTRLL_INTFLG_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_ClearInterruptFlag(PeripheralBase) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(WDOG_CS2_FLG_MASK | 0x1U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_ClearInterruptFlag(PeripheralBase) ( \ + WDOG_STCTRLL_REG(PeripheralBase) = \ + (uint16)(WDOG_STCTRLL_INTFLG_MASK | 0x1U) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog status and control register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog status and control register low. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL. + * @par Example: + * @code + * WDOG_PDD_WriteControlLowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteControlLowReg(PeripheralBase, Value) ( \ + WDOG_STCTRLL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog status and control register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadControlLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadControlLowReg(PeripheralBase) ( \ + WDOG_STCTRLL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register high. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutHighReg(PeripheralBase, Value) ( \ + WDOG_TOVALH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register high. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutHighReg(PeripheralBase, Value) ( \ + WDOG_TOVALH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTimeOutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimeOutHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimeOutHighReg(PeripheralBase) ( \ + WDOG_TOVALH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register low. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutLowReg(PeripheralBase, Value) ( \ + WDOG_TOVALL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register low. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutLowReg(PeripheralBase, Value) ( \ + WDOG_TOVALL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTimeOutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimeOutLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimeOutLowReg(PeripheralBase) ( \ + WDOG_TOVALL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register high. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * WDOG_PDD_WriteWindowHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowHighReg(PeripheralBase, Value) ( \ + WDOG_WINH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register high. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * WDOG_PDD_WriteWindowHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowHighReg(PeripheralBase, Value) ( \ + WDOG_WINH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWindowHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadWindowHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadWindowHighReg(PeripheralBase) ( \ + WDOG_WINH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register low. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * WDOG_PDD_WriteWindowLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowLowReg(PeripheralBase, Value) ( \ + WDOG_WINL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register low. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * WDOG_PDD_WriteWindowLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowLowReg(PeripheralBase, Value) ( \ + WDOG_WINL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWindowLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadWindowLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadWindowLowReg(PeripheralBase) ( \ + WDOG_WINL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRefreshReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. Use constants from group "Refresh constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_REFRESH, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteRefreshReg(_BASE_PTR, WDOG_PDD_KEY_1); + * @endcode + */ + #define WDOG_PDD_WriteRefreshReg(PeripheralBase, Value) ( \ + WDOG_CNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. Use constants from group "Refresh constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_REFRESH, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteRefreshReg(_BASE_PTR, WDOG_PDD_KEY_1); + * @endcode + */ + #define WDOG_PDD_WriteRefreshReg(PeripheralBase, Value) ( \ + WDOG_REFRESH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRefreshReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_REFRESH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadRefreshReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadRefreshReg(PeripheralBase) ( \ + WDOG_REFRESH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteUnlockReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Unlock constant. Use constants from group "Unlock constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_UNLOCK, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteUnlockReg(_BASE_PTR, WDOG_PDD_UNLOCK_1); + * @endcode + */ + #define WDOG_PDD_WriteUnlockReg(PeripheralBase, Value) ( \ + WDOG_CNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog unlock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Unlock constant. Use constants from group "Unlock constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_UNLOCK, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteUnlockReg(_BASE_PTR, WDOG_PDD_UNLOCK_1); + * @endcode + */ + #define WDOG_PDD_WriteUnlockReg(PeripheralBase, Value) ( \ + WDOG_UNLOCK_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadUnlockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog unlock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_UNLOCK. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadUnlockReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadUnlockReg(PeripheralBase) ( \ + WDOG_UNLOCK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerOutputHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog timer output register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog timer output register high. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TMROUTH. + * @par Example: + * @code + * WDOG_PDD_WriteTimerOutputHighReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimerOutputHighReg(PeripheralBase, Value) ( \ + WDOG_TMROUTH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerOutputHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog timer output register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TMROUTH. + * @par Example: + * @code + * uint16 result = + * WDOG_PDD_ReadTimerOutputHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimerOutputHighReg(PeripheralBase) ( \ + WDOG_TMROUTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerOutputLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog timer output register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog timer output register low. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TMROUTL. + * @par Example: + * @code + * WDOG_PDD_WriteTimerOutputLowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimerOutputLowReg(PeripheralBase, Value) ( \ + WDOG_TMROUTL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerOutputLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog timer output register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TMROUTL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimerOutputLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimerOutputLowReg(PeripheralBase) ( \ + WDOG_TMROUTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteResetCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog reset count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog reset count register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_RSTCNT. + * @par Example: + * @code + * WDOG_PDD_WriteResetCountReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteResetCountReg(PeripheralBase, Value) ( \ + WDOG_RSTCNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadResetCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog reset count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_RSTCNT. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadResetCountReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadResetCountReg(PeripheralBase) ( \ + WDOG_RSTCNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets prescale value of the watchdog counter reference clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Reference clock prescaler constants". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetPrescaler(_BASE_PTR, WDOG_PDD_DIVIDE_1); + * @endcode + */ + #define WDOG_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)((uint8)((uint8)(Prescaler) << WDOG_CS2_PRES_SHIFT) | 0x1U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Reference clock prescaler constants". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetPrescaler(_BASE_PTR, WDOG_PDD_DIVIDE_1); + * @endcode + */ + #define WDOG_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + WDOG_PRESC_REG(PeripheralBase) = \ + (uint16)((uint16)(Prescaler) << WDOG_PRESC_PRESCVAL_SHIFT) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WritePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog prescaler register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC. + * @par Example: + * @code + * WDOG_PDD_WritePrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WritePrescalerReg(PeripheralBase, Value) ( \ + WDOG_PRESC_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_PRESC. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadPrescalerReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadPrescalerReg(PeripheralBase) ( \ + WDOG_PRESC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog time-out value register. Because the WDOG + * peripheral is big endian, the conversion to the little endian is done in this + * macro. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVAL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimeOutReg(PeripheralBase, Value) ( \ + WDOG_TOVAL_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)((uint16)((uint16)(Value) & 0xFFU) << 8U)) | ( \ + (uint16)((uint16)(Value) >> 8U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog window register. Because the WDOG + * peripheral is big endian, the conversion to the little endian is done in this macro. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WIN. + * @par Example: + * @code + * WDOG_PDD_WriteWindowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteWindowReg(PeripheralBase, Value) ( \ + WDOG_WIN_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)((uint16)((uint16)(Value) & 0xFFU) << 8U)) | ( \ + (uint16)((uint16)(Value) >> 8U))) \ + ) +#endif /* #if defined(WDOG_PDD_H_) */ + +/* WDOG_PDD.h, eof. */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c new file mode 100644 index 0000000..36034c5 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c @@ -0,0 +1,556 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CDC1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_CDC_Device +** Version : Component 01.031, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** Component name : CDC1 +** CPU : Kinetis K20D72 +** CDC Settings : Enabled +** .inf ClassGuid : 4D36E978-E325-11CE-BFC1-08002BE10318 +** .inf VID : 2504 +** .inf PID : 0300 +** .inf PRVDR : Freescale +** .inf MFGNAME : My Company +** .inf DESCRIPTION : Freescale CDC Device +** .inf SERVICE : Virtual Com Driver +** Bus reported device : FSL CDC DEVICE +** Bus reported vendor : FREESCALE INC. +** Send Buffer : RingBuffer +** Receive Buffer : RingBuffer +** Use Timeout : Disabled +** Contents : +** ClearRxBuffer - void CDC1_ClearRxBuffer(void); +** ClearTxBuffer - void CDC1_ClearTxBuffer(void); +** GetFreeInTxBuf - word CDC1_GetFreeInTxBuf(void); +** GetCharsInTxBuf - word CDC1_GetCharsInTxBuf(void); +** GetCharsInRxBuf - word CDC1_GetCharsInRxBuf(void); +** GetChar - byte CDC1_GetChar(CDC1_TComData *Chr); +** RecvChar - byte CDC1_RecvChar(CDC1_TComData *Chr); +** SendChar - byte CDC1_SendChar(CDC1_TComData Chr); +** SendString - byte CDC1_SendString(CDC1_TComData *Chr); +** SendBlock - byte CDC1_SendBlock(byte *data, word dataSize); +** PutBufferChecked - byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +** App_Callback - void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +** Notify_Callback - void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +** App_Task - byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +** Init - byte CDC1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013 +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file CDC1.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CDC1_module CDC1 module documentation +** @{ +*/ + +/* MODULE CDC1. */ + +#include "CDC1.h" +#include "hidef.h" /* for EnableInterrupts; macro */ +#include "hal/derivative.h" /* include peripheral declarations */ +#include "usb_cdc.h" /* USB CDC Class Header File */ +#include +/* skip the inclusion in dependency state */ +#ifndef __NO_SETJMP + #include +#endif +#include +#include + +#define CONTROLLER_ID (0) /* ID to identify USB CONTROLLER */ + +#if HIGH_SPEED_DEVICE +static uint_32 g_cdcBuffer[DIC_BULK_OUT_ENDP_PACKET_SIZE>>1]; +#endif + +/* Virtual COM Application start Init Flag */ +static volatile boolean start_app = FALSE; + +/* Virtual COM Application Carrier Activate Flag */ +static volatile boolean start_transactions = FALSE; + +static volatile boolean transactionOngoing = FALSE; +/* +** =================================================================== +** Method : CDC1_GetFreeInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of free character in the send buffer +** Parameters : None +** Returns : +** --- - Number of free character in the receive +** buffer. +** =================================================================== +*/ +/* +word CDC1_GetFreeInTxBuf(void) +{ + *** Implemented as macro in the header file +} +*/ + +/* +** =================================================================== +** Method : CDC1_GetCharsInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the send buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ +/* +word CDC1_GetCharsInTxBuf(void) +{ + *** implemented as macro in the header file + return (word)Tx1_NofElements(); +} +*/ + +/* +** =================================================================== +** Method : CDC1_GetCharsInRxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the receive buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ +word CDC1_GetCharsInRxBuf(void) +{ + static uint8 txBuf[CDC1_DATA_BUFF_SIZE]; + + if(CDC1_App_Task(txBuf, sizeof(txBuf))!=ERR_OK) { /* call USB handler: if active, then this will empty the buffer */ + } + return (word)Rx1_NofElements(); +} + +/* +** =================================================================== +** Method : CDC1_GetChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is not +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ +/** +byte CDC1_GetChar(CDC1_TComData *Chr) +{ + *** implemented as macro in the header file + return Rx1_Get(Chr); +} +*/ +/* +** =================================================================== +** Method : CDC1_RecvChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ +byte CDC1_RecvChar(CDC1_TComData *Chr) +{ + while(Rx1_Get(Chr)!=ERR_OK) { + /* retry receiving until success */ + } + return ERR_OK; +} + +/* +** =================================================================== +** Method : CDC1_SendChar (component FSL_USB_CDC_Device) +** Description : +** Method to send a character to the USB interface. Method is +** non-blocking: If the output buffer is full, it tries to send +** it over USB. If this fails or buffer is still full, the +** character will be lost. If OnError() event is enabled, the +** error event will be called in case of error. +** Parameters : +** NAME - DESCRIPTION +** Chr - Character to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendChar(CDC1_TComData Chr) +{ + static uint8 txBuf[CDC1_DATA_BUFF_SIZE]; + + if(Tx1_Put(Chr)==ERR_TXFULL) { /* retry once, otherwise throw it away */ + if(CDC1_App_Task(txBuf, sizeof(txBuf))!=ERR_OK) { /* call USB handler: if active, then this will empty the buffer */ + return ERR_TXFULL; + } else { /* retry, as USB App_Task() should have sent the buffer */ + return Tx1_Put(Chr); /* retry. If buffer is still full, we will lose the character */ + } + } + return ERR_OK; +} + +/* +** =================================================================== +** Method : CDC1_SendBlock (component FSL_USB_CDC_Device) +** Description : +** Method to send a data block to the USB interface. Method is +** non-blocking: if data cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * data - Pointer to data to send. +** dataSize - Size of data in bytes +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendBlock(byte *data, word dataSize) +{ + byte res = ERR_OK; + + while(dataSize > 0) { + if(CDC1_SendChar(*data)!=ERR_OK) { + res = ERR_TXFULL; + } + dataSize--; data++; + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_SendString (component FSL_USB_CDC_Device) +** Description : +** Method to send a string to the USB interface. Method is +** non-blocking: if string cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to string to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendString(CDC1_TComData *Chr) +{ + byte res = ERR_OK; + + while(*Chr != '\0') { + if(CDC1_SendChar(*Chr)!=ERR_OK) { + res = ERR_TXFULL; + } + Chr++; + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_App_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle class callbacks from USB +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - gives the configuration value +** Returns : Nothing +** =================================================================== +*/ +void CDC1_App_Callback(byte controller_ID, byte event_type, void *val) +{ + UNUSED(controller_ID); + UNUSED(val); + if(event_type == USB_APP_BUS_RESET) { + start_app = FALSE; + } else if(event_type == USB_APP_ENUM_COMPLETE) { +#if HIGH_SPEED_DEVICE + /* prepare for the next receive event */ + USB_Class_CDC_Interface_DIC_Recv_Data(&controller_ID, + (uint_8_ptr)g_cdcBuffer, + DIC_BULK_OUT_ENDP_PACKET_SIZE); +#endif + start_app = TRUE; + } else if((event_type == USB_APP_DATA_RECEIVED)&&(start_transactions==TRUE)) { + /* Copy Received Data buffer to Application Buffer */ + USB_PACKET_SIZE BytesToBeCopied; + APP_DATA_STRUCT *dp_rcv = (APP_DATA_STRUCT*)val; + uint_8 index; + + BytesToBeCopied = (USB_PACKET_SIZE)((dp_rcv->data_size > CDC1_DATA_BUFF_SIZE) ? CDC1_DATA_BUFF_SIZE:dp_rcv->data_size); + for(index = 0; indexdata_ptr[index])!=ERR_OK) { + /* Failed to put byte into buffer. Is the buffer to small? Then increase the Rx buffer. + Otherwise not much we could do here, so we are loosing byte here. + */ + /* Enable OnError() event so this event will be called here */ + } + } + (void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, NULL, 0); /* see http://eprints.utar.edu.my/143/1/BI-2011-0708672-1.pdf, page 131 */ + } else if((event_type == USB_APP_SEND_COMPLETE)&&(start_transactions==TRUE)) { + transactionOngoing = FALSE; + /* Previous Send is complete. Queue next receive */ +#if HIGH_SPEED_DEVICE + //(void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, g_cdcBuffer, 0); +#else + (void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, NULL, 0); +#endif + } else if(event_type == USB_APP_ERROR) { /* detach? */ + start_app = FALSE; + start_transactions = FALSE; + } +} + +/* +** =================================================================== +** Method : CDC1_Notify_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle PSTN Sub Class callbacks +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - +** Returns : Nothing +** =================================================================== +*/ +void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val) +{ + UNUSED(controller_ID); + UNUSED(val); + if(start_app == TRUE) { + if(event_type == USB_APP_CDC_CARRIER_ACTIVATED) { + start_transactions = TRUE; + } else if(event_type == USB_APP_CDC_CARRIER_DEACTIVATED) { + start_transactions = FALSE; + } + } + start_transactions = TRUE; /* ??? see http://forums.freescale.com/t5/Freescale-MQX-trade-USB-Host/Cant-get-CDC-virtual-com-demo-to-work-with-VB2005-on-xp-sp3/m-p/92713#M302 */ +} + +/* +** =================================================================== +** Method : CDC1_RunUsbEngine (component FSL_USB_CDC_Device) +** +** Description : +** Runs the USB polling engine +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void CDC1_RunUsbEngine(void) +{ + /* not needed */ +} + +/* +** =================================================================== +** Method : CDC1_SendDataBlock (component FSL_USB_CDC_Device) +** +** Description : +** Sends a USB data block +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +byte CDC1_SendDataBlock(byte *data, word dataSize) +{ + uint8 res = ERR_OK; + + transactionOngoing = TRUE; + if(USB_Class_CDC_Interface_DIC_Send_Data(CONTROLLER_ID, data, dataSize)!=USB_OK) { + transactionOngoing = FALSE; + return ERR_FAULT; + } + /* wait for transaction finish */ + while(transactionOngoing) { /* wait until transaction is finished */ + CDC1_RunUsbEngine(); + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_App_Task (component FSL_USB_CDC_Device) +** Description : +** Application task to be called periodically from the main +** task. +** Parameters : +** NAME - DESCRIPTION +** * txBuf - Pointer to temporary buffer used to +** transmit data over USB. Should be equal or +** greater than the endpoint buffer size. Data +** will be sent in an asynchronous way, so +** make sure the buffer is *not* on the stack. +** This buffer must be available until the +** next transmission. +** txBufSize - Size of the buffer in bytes +** Returns : +** --- - Error code, returns ERR_OK if USB +** enumeration has been finished, error code +** otherwise. +** =================================================================== +*/ +byte CDC1_App_Task(byte *txBuf, size_t txBufSize) +{ + uint8 i, res; + + /* device is Kinetis K20D72 */ + CDC1_RunUsbEngine(); + /* call the periodic task function */ + USB_Class_CDC_Periodic_Task(); + /* check whether enumeration is complete or not */ + if((start_app==TRUE) && (start_transactions==TRUE)) { + if(Tx1_NofElements()!=0) { + i = 0; + while(iCDC1_GetFreeInTxBuf()) { /* no room at the Inn... */ + res = ERR_TXFULL; + } else { + res = ERR_OK; + while(bufSize>0 && res==ERR_OK) { + res = Tx1_Put(*buf); + bufSize--; + buf++; + } + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_ClearRxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the receiver buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/** +void CDC1_ClearRxBuffer(void) +{ + Implemented as macro in the header file +} +*/ + +/* +** =================================================================== +** Method : CDC1_ClearTxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the transmit buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/** +void CDC1_ClearTxBuffer(void) +{ + Implemented as macro in the header file +} +*/ + +/* END CDC1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h new file mode 100644 index 0000000..d0f14fa --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h @@ -0,0 +1,379 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CDC1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_CDC_Device +** Version : Component 01.031, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** Component name : CDC1 +** CPU : Kinetis K20D72 +** CDC Settings : Enabled +** .inf ClassGuid : 4D36E978-E325-11CE-BFC1-08002BE10318 +** .inf VID : 2504 +** .inf PID : 0300 +** .inf PRVDR : Freescale +** .inf MFGNAME : My Company +** .inf DESCRIPTION : Freescale CDC Device +** .inf SERVICE : Virtual Com Driver +** Bus reported device : FSL CDC DEVICE +** Bus reported vendor : FREESCALE INC. +** Send Buffer : RingBuffer +** Receive Buffer : RingBuffer +** Use Timeout : Disabled +** Contents : +** ClearRxBuffer - void CDC1_ClearRxBuffer(void); +** ClearTxBuffer - void CDC1_ClearTxBuffer(void); +** GetFreeInTxBuf - word CDC1_GetFreeInTxBuf(void); +** GetCharsInTxBuf - word CDC1_GetCharsInTxBuf(void); +** GetCharsInRxBuf - word CDC1_GetCharsInRxBuf(void); +** GetChar - byte CDC1_GetChar(CDC1_TComData *Chr); +** RecvChar - byte CDC1_RecvChar(CDC1_TComData *Chr); +** SendChar - byte CDC1_SendChar(CDC1_TComData Chr); +** SendString - byte CDC1_SendString(CDC1_TComData *Chr); +** SendBlock - byte CDC1_SendBlock(byte *data, word dataSize); +** PutBufferChecked - byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +** App_Callback - void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +** Notify_Callback - void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +** App_Task - byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +** Init - byte CDC1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013 +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file CDC1.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CDC1_module CDC1 module documentation +** @{ +*/ + +#ifndef __CDC1_H +#define __CDC1_H + +/* MODULE CDC1. */ + +/* Include shared modules, which are used for whole project */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "Tx1.h" +#include "Rx1.h" +#include /* for size_t */ + +//#include "Cpu.h" + + +#ifndef __BWUserType_CDC1_TComData +#define __BWUserType_CDC1_TComData + typedef byte CDC1_TComData ; /* User type for communication data type. */ +#endif + +/* + DATA_BUFF_SIZE should be greater than or equal to the endpoint buffer size, + otherwise there will be data loss. For MC9S08JS16, maximum DATA_BUFF_SIZE + supported is 16 Bytes +*/ +#define CDC1_DATA_BUFF_SIZE 64 + +#define CDC1_USB_ERR_SEND 1 /* Error while sending */ +#define CDC1_USB_ERR_BUSOFF 2 /* Bus not ready */ +#define CDC1_USB_ERR_INIT 3 /* USB initialization error */ +#define CDC1_USB_ERR_TX_CHAR 4 /* Error sending character */ +#define CDC1_USB_ERR_TX_STRING 5 /* Error sending string */ +#define CDC1_USB_ERR_CHECKED_TXFULL 6 /* Error during sending a checked block */ +#define CDC1_USB_ERR_RECEIVE 7 /* Error while starting an receive transaction */ +#define CDC1_USB_ERR_RX_PUT 8 /* Error while putting RX byte into buffer */ +#define CDC1_USB_ERR_TX_BLOCK 9 /* Error sending data block */ +#define CDC1_USB_TIMEOUT_SEND 10 /* Timeout while sending */ + + +#define CDC1_GetFreeInTxBuf() \ + Tx1_NofFreeElements() +/* +** =================================================================== +** Method : CDC1_GetFreeInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of free character in the send buffer +** Parameters : None +** Returns : +** --- - Number of free character in the receive +** buffer. +** =================================================================== +*/ + +byte CDC1_RecvChar(CDC1_TComData *Chr); +/* +** =================================================================== +** Method : CDC1_RecvChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ + +byte CDC1_SendChar(CDC1_TComData Chr); +/* +** =================================================================== +** Method : CDC1_SendChar (component FSL_USB_CDC_Device) +** Description : +** Method to send a character to the USB interface. Method is +** non-blocking: If the output buffer is full, it tries to send +** it over USB. If this fails or buffer is still full, the +** character will be lost. If OnError() event is enabled, the +** error event will be called in case of error. +** Parameters : +** NAME - DESCRIPTION +** Chr - Character to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +#define CDC1_GetCharsInTxBuf() \ + Tx1_NofElements() +/* +** =================================================================== +** Method : CDC1_GetCharsInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the send buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ + +word CDC1_GetCharsInRxBuf(void); +/* +** =================================================================== +** Method : CDC1_GetCharsInRxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the receive buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ + +byte CDC1_Init(void); +/* +** =================================================================== +** Method : CDC1_Init (component FSL_USB_CDC_Device) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +/* +** =================================================================== +** Method : CDC1_App_Task (component FSL_USB_CDC_Device) +** Description : +** Application task to be called periodically from the main +** task. +** Parameters : +** NAME - DESCRIPTION +** * txBuf - Pointer to temporary buffer used to +** transmit data over USB. Should be equal or +** greater than the endpoint buffer size. Data +** will be sent in an asynchronous way, so +** make sure the buffer is *not* on the stack. +** This buffer must be available until the +** next transmission. +** txBufSize - Size of the buffer in bytes +** Returns : +** --- - Error code, returns ERR_OK if USB +** enumeration has been finished, error code +** otherwise. +** =================================================================== +*/ + +byte CDC1_SendString(CDC1_TComData *Chr); +/* +** =================================================================== +** Method : CDC1_SendString (component FSL_USB_CDC_Device) +** Description : +** Method to send a string to the USB interface. Method is +** non-blocking: if string cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to string to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +#define CDC1_GetChar(Chr) \ + Rx1_Get(Chr) + +/* +** =================================================================== +** Method : CDC1_GetChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is not +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ + +byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +/* +** =================================================================== +** Method : CDC1_PutBufferChecked (component FSL_USB_CDC_Device) +** Description : +** Puts a data block into the output buffer, but does not send +** it. If there is not enough size available, then ERR_TXFULL +** is returned, otherwise ERR_OK. The application then needs to +** call USB_App_Callback() to actually send the buffer. +** Parameters : +** NAME - DESCRIPTION +** * buf - Pointer to buffer to be sent +** bufsize - Buffer size in bytes +** Returns : +** --- - Error code +** =================================================================== +*/ + +void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +/* +** =================================================================== +** Method : CDC1_App_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle class callbacks from USB +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - gives the configuration value +** Returns : Nothing +** =================================================================== +*/ + +void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +/* +** =================================================================== +** Method : CDC1_Notify_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle PSTN Sub Class callbacks +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - +** Returns : Nothing +** =================================================================== +*/ + +#define CDC1_ClearRxBuffer() \ + Rx1_Clear() +/* +** =================================================================== +** Method : CDC1_ClearRxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the receiver buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CDC1_ClearTxBuffer() \ + Tx1_Clear() +/* +** =================================================================== +** Method : CDC1_ClearTxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the transmit buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void CDC1_RunUsbEngine(void); +/* +** =================================================================== +** Method : CDC1_RunUsbEngine (component FSL_USB_CDC_Device) +** +** Description : +** Runs the USB polling engine +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +byte CDC1_SendBlock(byte *data, word dataSize); +/* +** =================================================================== +** Method : CDC1_SendBlock (component FSL_USB_CDC_Device) +** Description : +** Method to send a data block to the USB interface. Method is +** non-blocking: if data cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * data - Pointer to data to send. +** dataSize - Size of data in bytes +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +byte CDC1_SendDataBlock(byte *data, word dataSize); +/* +** =================================================================== +** Method : CDC1_SendDataBlock (component FSL_USB_CDC_Device) +** +** Description : +** Sends a USB data block +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END CDC1. */ + +#endif +/* ifndef __CDC1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c new file mode 100644 index 0000000..cf55876 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c @@ -0,0 +1,103 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CS1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : CriticalSection +** Version : Component 01.006, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** +** Contents : +** CriticalVariable - void CS1_CriticalVariable(void); +** EnterCritical - void CS1_EnterCritical(void); +** ExitCritical - void CS1_ExitCritical(void); +** +** License : Open Source (LGPL) +** Copyright : Erich Styger, 2014, all rights reserved. +** Web : www.mcuoneclipse.com +** This an open source software implementing a driver using Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file CS1.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CS1_module CS1 module documentation +** @{ +*/ + +/* MODULE CS1. */ + +#include "CS1.h" + +/* +** =================================================================== +** Method : CS1_CriticalVariable (component CriticalSection) +** Description : +** Defines a variable if necessary. This is a macro. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_CriticalVariable(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* +** =================================================================== +** Method : CS1_EnterCritical (component CriticalSection) +** Description : +** Enters a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_EnterCritical(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* +** =================================================================== +** Method : CS1_ExitCritical (component CriticalSection) +** Description : +** Exits a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_ExitCritical(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* END CS1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h new file mode 100644 index 0000000..d66cf32 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h @@ -0,0 +1,126 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CS1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : CriticalSection +** Version : Component 01.006, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** +** Contents : +** CriticalVariable - void CS1_CriticalVariable(void); +** EnterCritical - void CS1_EnterCritical(void); +** ExitCritical - void CS1_ExitCritical(void); +** +** License : Open Source (LGPL) +** Copyright : Erich Styger, 2014, all rights reserved. +** Web : www.mcuoneclipse.com +** This an open source software implementing a driver using Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file CS1.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CS1_module CS1 module documentation +** @{ +*/ + +#ifndef __CS1_H +#define __CS1_H + +/* MODULE CS1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ + +//#include "Cpu.h" + + +/* workaround macros for wrong EnterCritical()/ExitCritical() in the low level drivers. Will be removed once PEx is fixed */ +#define CS1_CriticalVariableDrv() \ + CS1_CriticalVariable() +#define CS1_EnterCriticalDrv() \ + CS1_EnterCritical() +#define CS1_ExitCriticalDrv() \ + CS1_ExitCritical() + +#define CS1_CriticalVariable() \ + uint8 cpuSR; /* variable to store current status */ + +/* +** =================================================================== +** Method : CS1_CriticalVariable (component CriticalSection) +** Description : +** Defines a variable if necessary. This is a macro. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CS1_EnterCritical() \ + do { \ + asm ( \ + "MRS R0, PRIMASK\n\t" \ + "CPSID I\n\t" \ + "STRB R0, %[output]" \ + : [output] "=m" (cpuSR) :: "r0"); \ + } while(0) + +/* +** =================================================================== +** Method : CS1_EnterCritical (component CriticalSection) +** Description : +** Enters a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CS1_ExitCritical() \ + do{ \ + asm ( \ + "ldrb r0, %[input]\n\t" \ + "msr PRIMASK,r0;\n\t" \ + ::[input] "m" (cpuSR) : "r0"); \ + } while(0) + +/* +** =================================================================== +** Method : CS1_ExitCritical (component CriticalSection) +** Description : +** Exits a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END CS1. */ + +#endif +/* ifndef __CS1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h new file mode 100644 index 0000000..b39e5d0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h @@ -0,0 +1,12 @@ +/****************************************************************************** + * Configuration file for the FSL USB stack created with Processor Expert. + *****************************************************************************/ +#ifndef __FSL_USB_STACK_CONFIG_ +#define __FSL_USB_STACK_CONFIG_ + +/* Overwrite initialization values from Processor Expert Init() component. These are 'known working values'. + * Otherwise you have to setup the bits (e.g. Pull-up/pull-down resistors! + * */ +#define USB_USER_CONFIG_USE_STACK_INIT 1 /* value set by component property 'Use USB Stack Initialization' */ + +#endif /* __FSL_USB_STACK_CONFIG_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h new file mode 100644 index 0000000..08bf3b0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h @@ -0,0 +1,96 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Const +** Version : Driver 01.00 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Const.h +** @version 01.00 +** @brief +** This component "PE_Const" contains internal definitions +** of the constants. +*/ +/*! +** @addtogroup PE_Const_module PE_Const module documentation +** @{ +*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + + +/* Reset cause constants */ +#define RSTSRC_WAKEUP 0x01U /*!< LLWU module wakeup reset */ +#define RSTSRC_LVD 0x02U /*!< Low-voltage detect reset */ +#define RSTSRC_LOC 0x04U /*!< Loss-of-clock reset */ +#define RSTSRC_LOL 0x08U /*!< Loss-of-lock reset */ +#define RSTSRC_COP 0x20U /*!< Watchdog reset */ +#define RSTSRC_WDOG 0x20U /*!< Watchdog reset */ +#define RSTSRC_PIN 0x40U /*!< External pin reset */ +#define RSTSRC_POR 0x80U /*!< Power-on reset */ +#define RSTSRC_JTAG 0x0100U /*!< JTAG reset pin */ +#define RSTSRC_LOCKUP 0x0200U /*!< Core Lock-up reset */ +#define RSTSRC_SW 0x0400U /*!< Software reset */ +#define RSTSRC_MDM_AP 0x0800U /*!< Reset caused by host debugger system */ +#define RSTSRC_EZPT 0x1000U /*!< EzPort reset */ +#define RSTSRC_SACKERR 0x2000U /*!< Stop Mode Acknowledge Error Reset */ + + +/* Low voltage interrupt cause constants */ +#define LVDSRC_LVD 0x01U /*!< Low voltage detect */ +#define LVDSRC_LVW 0x02U /*!< Low-voltage warning */ + +#endif /* _PE_Const_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h new file mode 100644 index 0000000..c53525e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h @@ -0,0 +1,128 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Error +** Version : Driver 01.00 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component "PE_Error" contains internal definitions +** of the error constants. +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Error.h +** @version 01.00 +** @brief +** This component "PE_Error" contains internal definitions +** of the error constants. +*/ +/*! +** @addtogroup PE_Error_module PE_Error module documentation +** @{ +*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0x00U /*!< OK */ +#define ERR_SPEED 0x01U /*!< This device does not work in the active speed mode. */ +#define ERR_RANGE 0x02U /*!< Parameter out of range. */ +#define ERR_VALUE 0x03U /*!< Parameter of incorrect value. */ +#define ERR_OVERFLOW 0x04U /*!< Timer overflow. */ +#define ERR_MATH 0x05U /*!< Overflow during evaluation. */ +#define ERR_ENABLED 0x06U /*!< Device is enabled. */ +#define ERR_DISABLED 0x07U /*!< Device is disabled. */ +#define ERR_BUSY 0x08U /*!< Device is busy. */ +#define ERR_NOTAVAIL 0x09U /*!< Requested value or method not available. */ +#define ERR_RXEMPTY 0x0AU /*!< No data in receiver. */ +#define ERR_TXFULL 0x0BU /*!< Transmitter is full. */ +#define ERR_BUSOFF 0x0CU /*!< Bus not available. */ +#define ERR_OVERRUN 0x0DU /*!< Overrun error is detected. */ +#define ERR_FRAMING 0x0EU /*!< Framing error is detected. */ +#define ERR_PARITY 0x0FU /*!< Parity error is detected. */ +#define ERR_NOISE 0x10U /*!< Noise error is detected. */ +#define ERR_IDLE 0x11U /*!< Idle error is detected. */ +#define ERR_FAULT 0x12U /*!< Fault error is detected. */ +#define ERR_BREAK 0x13U /*!< Break char is received during communication. */ +#define ERR_CRC 0x14U /*!< CRC error is detected. */ +#define ERR_ARBITR 0x15U /*!< A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 0x16U /*!< Protection error is detected. */ +#define ERR_UNDERFLOW 0x17U /*!< Underflow error is detected. */ +#define ERR_UNDERRUN 0x18U /*!< Underrun error is detected. */ +#define ERR_COMMON 0x19U /*!< Common error of a device. */ +#define ERR_LINSYNC 0x1AU /*!< LIN synchronization error is detected. */ +#define ERR_FAILED 0x1BU /*!< Requested functionality or process failed. */ +#define ERR_QFULL 0x1CU /*!< Queue is full. */ +#define ERR_PARAM_MASK 0x80U /*!< Invalid mask. */ +#define ERR_PARAM_MODE 0x81U /*!< Invalid mode. */ +#define ERR_PARAM_INDEX 0x82U /*!< Invalid index. */ +#define ERR_PARAM_DATA 0x83U /*!< Invalid data. */ +#define ERR_PARAM_SIZE 0x84U /*!< Invalid size. */ +#define ERR_PARAM_VALUE 0x85U /*!< Invalid value. */ +#define ERR_PARAM_RANGE 0x86U /*!< Invalid parameter's range or parameters' combination. */ +#define ERR_PARAM_LOW_VALUE 0x87U /*!< Invalid value (LOW part). */ +#define ERR_PARAM_HIGH_VALUE 0x88U /*!< Invalid value (HIGH part). */ +#define ERR_PARAM_ADDRESS 0x89U /*!< Invalid address. */ +#define ERR_PARAM_PARITY 0x8AU /*!< Invalid parity. */ +#define ERR_PARAM_WIDTH 0x8BU /*!< Invalid width. */ +#define ERR_PARAM_LENGTH 0x8CU /*!< Invalid length. */ +#define ERR_PARAM_ADDRESS_TYPE 0x8DU /*!< Invalid address type. */ +#define ERR_PARAM_COMMAND_TYPE 0x8EU /*!< Invalid command type. */ +#define ERR_PARAM_COMMAND 0x8FU /*!< Invalid command. */ +#define ERR_PARAM_RECIPIENT 0x90U /*!< Invalid recipient. */ +#define ERR_PARAM_BUFFER_COUNT 0x91U /*!< Invalid buffer count. */ +#define ERR_PARAM_ID 0x92U /*!< Invalid ID. */ +#define ERR_PARAM_GROUP 0x93U /*!< Invalid group. */ +#define ERR_PARAM_CHIP_SELECT 0x94U /*!< Invalid chip select. */ +#define ERR_PARAM_ATTRIBUTE_SET 0x95U /*!< Invalid set of attributes. */ +#define ERR_PARAM_SAMPLE_COUNT 0x96U /*!< Invalid sample count. */ +#define ERR_PARAM_CONDITION 0x97U /*!< Invalid condition. */ +#define ERR_PARAM_TICKS 0x98U /*!< Invalid ticks parameter. */ + +#endif /* __PE_Error_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h new file mode 100644 index 0000000..a7325ba --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h @@ -0,0 +1,2586 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Types +** Version : Driver 01.01 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** PE_Types.h - contains definitions of basic types, +** register access macros and hardware specific macros +** which can be used in user application. +** Settings : +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Types.h +** @version 01.01 +** @brief +** PE_Types.h - contains definitions of basic types, +** register access macros and hardware specific macros +** which can be used in user application. +*/ +/*! +** @addtogroup PE_Types_module PE_Types module documentation +** @{ +*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +/* Standard ANSI C types */ +#include +#include "hal/derivative.h" +//#ifndef FALSE +// #define FALSE 0x00u /* Boolean value FALSE. FALSE is defined always as a zero value. */ +//#endif +//#ifndef TRUE // zentrale Definition in TMCM. +// #define TRUE 0x01u /* Boolean value TRUE. TRUE is defined always as a non zero value. */ +//#endif + +#ifndef NULL + #define NULL 0x00u +#endif + +/* PE types definition */ +#ifndef __cplusplus + #ifndef bool +typedef unsigned char bool; + #endif +#endif +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long dword; +typedef unsigned long long dlong; +typedef unsigned char TPE_ErrCode; +#ifndef TPE_Float +typedef float TPE_Float; +#endif +#ifndef char_t +typedef char char_t; +#endif + +/**********************************************************/ +/* Uniform multiplatform 8-bits peripheral access macros */ +/**********************************************************/ + +/* Enable maskable interrupts */ +#define __EI()\ + do {\ + /*lint -save -e950 Disable MISRA rule (1.1) checking. */\ + __asm("CPSIE f");\ + /*lint -restore Enable MISRA rule (1.1) checking. */\ + } while(0) + +/* Disable maskable interrupts */ +#define __DI() \ + do {\ + /*lint -save -e950 Disable MISRA rule (1.1) checking. */\ + __asm ("CPSID f");\ + /*lint -restore Enable MISRA rule (1.1) checking. */\ + } while(0) + + + +/* Save status register and disable interrupts */ +#define EnterCritical() \ + do {\ + uint8 SR_reg_local;\ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm ( \ + "MRS R0, FAULTMASK\n\t" \ + "CPSID f\n\t" \ + "STRB R0, %[output]" \ + : [output] "=m" (SR_reg_local)\ + :: "r0");\ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\ + if(++SR_lock == 1u) {\ + SR_reg = SR_reg_local;\ + }\ + } while(0) + + +/* Restore status register */ +#define ExitCritical() \ + do {\ + if(--SR_lock == 0u) { \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm ( \ + "ldrb r0, %[input]\n\t"\ + "msr FAULTMASK,r0;\n\t" \ + ::[input] "m" (SR_reg) \ + : "r0"); \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\ + }\ + } while(0) + + +#define PE_DEBUGHALT() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm( "BKPT 255") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + +#define PE_NOP() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm( "NOP") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + +#define PE_WFI() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm("WFI") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + + +/* Interrupt definition template */ +/* For some reason GCC doesn't like this macro and gives out a warning, even when the compiled code works as intended + *#if !defined(PE_ISR) + * #define PE_ISR(ISR_name) \ + * void __attribute__ ((interrupt)) ISR_name(void) + *#endif +*/ +/* Logical Device Drivers (LDD) types */ + +/*! Logical Device Driver API version */ +#define PE_LDD_VERSION 0x0100U + +/* LDD driver states */ +#define PE_LDD_DRIVER_DISABLED_IN_CLOCK_CONFIGURATION 0x01U /*!< LDD driver is disabled in the selected clock configuration */ +#define PE_LDD_DRIVER_DISABLED_BY_USER 0x02U /*!< LDD driver is disabled by the user */ +#define PE_LDD_DRIVER_BUSY 0x04U /*!< LDD driver is busy */ + +/*! Macro to register component device structure */ +#define PE_LDD_RegisterDeviceStructure(ComponentIndex, DeviceStructure) (PE_LDD_DeviceDataList[ComponentIndex] = DeviceStructure) + +/*! Macro to unregister component device structure */ +#define PE_LDD_UnregisterDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex] = NULL) + +/*! Macro to get the component device structure */ +#define PE_LDD_GetDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex]) + +/* +** =========================================================================== +** LDD component ID specifying the component instance in the project. This ID +** is used internally as an index to the array of LDD device structures. +** =========================================================================== +*/ +#define PE_LDD_COMPONENT_BitIoLdd1_ID 0x00U +#define PE_LDD_COMPONENT_BitIoLdd2_ID 0x01U + +/* +** =================================================================== +** Global HAL types and constants +** =================================================================== +*/ +typedef uint32 LDD_TPinMask; /*!< Pin mask type. */ +typedef uint16 LDD_TError; /*!< Error type. */ +typedef uint32 LDD_TEventMask; /*!< Event mask type. */ +typedef uint8 LDD_TClockConfiguration; /*!< CPU clock configuration type. */ +typedef void LDD_TDeviceData; /*!< Pointer to private device structure managed and used by HAL components. */ +typedef void* LDD_TDeviceDataPtr; /*!< Obsolete type for backward compatibility. */ +typedef void LDD_TData; /*!< General pointer to data. */ +typedef void LDD_TUserData; /*!< Pointer to this type specifies the user or RTOS specific data will be passed as an event or callback parameter. */ + +/*! Driver operation mode type. */ +typedef enum { + DOM_NONE, + DOM_RUN, + DOM_WAIT, + DOM_SLEEP, + DOM_STOP +} LDD_TDriverOperationMode; + +typedef uint16 LDD_TDriverState; /*!< Driver state type. */ +typedef void LDD_TCallbackParam; /*!< Pointer to this type specifies the user data to be passed as a callback parameter. */ +typedef void (* LDD_TCallback)(LDD_TCallbackParam *CallbackParam); /*!< Callback type used for definition of callback functions. */ + +extern LDD_TDeviceData *PE_LDD_DeviceDataList[]; /*!< Array of LDD component device structures */ + + +/* Fills a memory area block by a specified value. Function defined in PE_LDD.c */ +extern void PE_FillMemory(register void* SourceAddressPtr, register uint8 c, register uint32 len); + + +/* +** =================================================================== +** RTOS specific types and constants +** =================================================================== +*/ +/* {Default RTOS Adapter} RTOS specific definition of type of Ioctl() command constants */ + + +/* +** =================================================================== +** Published RTOS settings and constants +** =================================================================== +*/ +/* {Default RTOS Adapter} No published RTOS settings */ + + +/* +** =================================================================== +** TimerUnit device types and constants +** =================================================================== +*/ +#define LDD_TIMERUNIT_ON_CHANNEL_0 0x01u /*!< OnChannel0 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_1 0x02u /*!< OnChannel1 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_2 0x04u /*!< OnChannel2 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_3 0x08u /*!< OnChannel3 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_4 0x10u /*!< OnChannel4 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_5 0x20u /*!< OnChannel5 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_6 0x40u /*!< OnChannel6 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_7 0x80u /*!< OnChannel7 event mask value */ +#define LDD_TIMERUNIT_ON_COUNTER_RESTART 0x0100u /*!< OnCounterRestart event mask value */ + +/*! Direction of counting */ +typedef enum { + DIR_UP, /*!< UP */ + DIR_DOWN /*!< DOWN */ +} LDD_TimerUnit_TCounterDirection; + +/*! Output action type (flip-flop action on overrun or compare match) */ +typedef enum { + OUTPUT_NONE, /*!< NONE */ + OUTPUT_TOGGLE, /*!< TOGGLE */ + OUTPUT_CLEAR, /*!< CLEAR */ + OUTPUT_SET /*!< SET */ +} LDD_TimerUnit_TOutAction; + +/*! Input edge type */ +typedef enum { + EDGE_NONE, /*!< NONE */ + EDGE_RISING, /*!< RISING */ + EDGE_FALLING, /*!< FALLING */ + EDGE_BOTH /*!< BOTH */ +} LDD_TimerUnit_TEdge; + +typedef float LDD_TimerUnit_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** CMT device types and constants +** =================================================================== +*/ +#define LDD_CMT_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** PPG device types and constants +** =================================================================== +*/ +#define LDD_PPG_ON_END 0x01u /*!< OnEnd event mask value */ + +typedef float LDD_PPG_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** PWM types and constants +** =================================================================== +*/ +#define LDD_PWM_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** Capture types and constants +** =================================================================== +*/ +#define LDD_CAPTURE_ON_CAPTURE 0x01u /*!< OnCapture event mask value */ +#define LDD_CAPTURE_ON_OVERRUN 0x02u /*!< OnOverrun event mask value */ + +/* +** =================================================================== +** TimerInt types and constants +** =================================================================== +*/ +#define LDD_TIMERINT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** TimerOut types and constants +** =================================================================== +*/ +#define LDD_TIMEROUT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** EventCntr types and constants +** =================================================================== +*/ +#define LDD_EVENTCNTR_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** FreeCntr types and constants +** =================================================================== +*/ +#define LDD_FREECNTR_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** RealTime types and constants +** =================================================================== +*/ + +typedef float LDD_RealTime_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** TimeDate types and constants +** =================================================================== +*/ +#define LDD_TIMEDATE_ON_ALARM 0x01u /*!< OnAlarm event mask value */ +#define LDD_TIMEDATE_ON_SECOND 0x02u /*!< OnSecond event mask value */ + +/*!< Time struct */ +typedef struct { + uint16 Hour; /*!< Hours (0 - 23) */ + uint16 Min; /*!< Minutes (0 - 59) */ + uint16 Sec; /*!< Seconds (0 - 59) */ + uint16 Sec100; /*!< Hundredths of seconds (0 - 99) */ +} LDD_TimeDate_TTimeRec; + +/*!< Date struct */ +typedef struct { + uint16 Year; /*!< Years (1998 - 2099) */ + uint16 Month; /*!< Months (1 - 12) */ + uint16 Day; /*!< Days (1 - 31) */ + uint16 DayOfWeek; /*!< Day of week (0-Sunday, .. 6-Saturday) */ +} LDD_TimeDate_TDateRec; + +/* +** =================================================================== +** UART device types and constants +** =================================================================== +*/ +#define LDD_SERIAL_RX_PIN 0x01u /*!< Receiver pin mask */ +#define LDD_SERIAL_TX_PIN 0x02u /*!< Transmitter pin mask */ +#define LDD_SERIAL_CTS_PIN 0x04u /*!< CTS pin mask */ +#define LDD_SERIAL_RTS_PIN 0x08u /*!< RTS pin mask */ + +#define LDD_SERIAL_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */ +#define LDD_SERIAL_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */ +#define LDD_SERIAL_ON_BREAK 0x04u /*!< OnBreak event mask */ +#define LDD_SERIAL_ON_TXCOMPLETE 0x08u /*!< OnTxComplete event mask */ +#define LDD_SERIAL_ON_ERROR 0x10u /*!< OnError event mask */ + +#define LDD_SERIAL_RX_OVERRUN 0x01u /*!< Receiver overrun */ +#define LDD_SERIAL_PARITY_ERROR 0x02u /*!< Parity error */ +#define LDD_SERIAL_FRAMING_ERROR 0x04u /*!< Framing error */ +#define LDD_SERIAL_NOISE_ERROR 0x08u /*!< Noise error */ + +typedef uint32 LDD_SERIAL_TError; /*!< Serial communication error type */ + +typedef uint8 LDD_SERIAL_TDataWidth; /*!< Bit length type. The number of bits transmitted by one character. */ + +typedef uint16 LDD_SERIAL_TSize; /*!< Type specifying the length of the data or buffer. */ + +typedef uint8 LDD_SERIAL_TBaudMode; /*!< Type specifying the baud mode. */ + +/*! Type specifying the parity. */ +typedef enum { + LDD_SERIAL_PARITY_UNDEF, /*!< Undefined parity */ + LDD_SERIAL_PARITY_NONE, /*!< Parity none */ + LDD_SERIAL_PARITY_ODD, /*!< Parity odd */ + LDD_SERIAL_PARITY_EVEN, /*!< Parity even */ + LDD_SERIAL_PARITY_MARK, /*!< Parity mark */ + LDD_SERIAL_PARITY_SPACE /*!< Parity space */ +} LDD_SERIAL_TParity; + +/*! Type specifying the stop bit length. */ +typedef enum { + LDD_SERIAL_STOP_BIT_LEN_UNDEF, /*!< Undefined bit length */ + LDD_SERIAL_STOP_BIT_LEN_1, /*!< 1 bit length */ + LDD_SERIAL_STOP_BIT_LEN_1_5, /*!< 1.5 bit length */ + LDD_SERIAL_STOP_BIT_LEN_2 /*!< 2 bit length */ +} LDD_SERIAL_TStopBitLen; + +/*! Communication statistics */ +typedef struct { + uint32 ReceivedChars; /*!< Number of received characters */ + uint32 SentChars; /*!< Number of transmitted characters */ + uint32 ReceivedBreaks; /*!< Number of received break characters */ + uint32 ParityErrors; /*!< Number of receiver parity errors */ + uint32 FramingErrors; /*!< Number of receiver framing errors */ + uint32 OverrunErrors; /*!< Number of receiver overrun errors */ + uint32 NoiseErrors; /*!< Number of receiver noise errors */ +} LDD_SERIAL_TStats; + +/*! Type specifying the loop mode operation. */ +typedef enum { + LOOPMODE_UNDEF, /*!< Undefined loop mode */ + LOOPMODE_NORMAL, /*!< Normal operation */ + LOOPMODE_AUTO_ECHO, /*!< Auto echo mode */ + LOOPMODE_LOCAL_LOOPBACK, /*!< Local loopback mode */ + LOOPMODE_REMOTE_LOOPBACK /*!< Remote loopback mode */ +} LDD_SERIAL_TLoopMode; + + +/* +** =================================================================== +** ADC device types and constants +** =================================================================== +*/ + +#define LDD_ADC_CHANNEL_0_PIN 0x01u /*!< Channel 0 pin mask */ +#define LDD_ADC_CHANNEL_1_PIN 0x02u /*!< Channel 1 pin mask */ +#define LDD_ADC_CHANNEL_2_PIN 0x04u /*!< Channel 2 pin mask */ +#define LDD_ADC_CHANNEL_3_PIN 0x08u /*!< Channel 3 pin mask */ +#define LDD_ADC_CHANNEL_4_PIN 0x10u /*!< Channel 4 pin mask */ +#define LDD_ADC_CHANNEL_5_PIN 0x20u /*!< Channel 5 pin mask */ +#define LDD_ADC_CHANNEL_6_PIN 0x40u /*!< Channel 6 pin mask */ +#define LDD_ADC_CHANNEL_7_PIN 0x80u /*!< Channel 7 pin mask */ +#define LDD_ADC_CHANNEL_8_PIN 0x0100u /*!< Channel 8 pin mask */ +#define LDD_ADC_CHANNEL_9_PIN 0x0200u /*!< Channel 9 pin mask */ +#define LDD_ADC_CHANNEL_10_PIN 0x0400u /*!< Channel 10 pin mask */ +#define LDD_ADC_CHANNEL_11_PIN 0x0800u /*!< Channel 11 pin mask */ +#define LDD_ADC_CHANNEL_12_PIN 0x1000u /*!< Channel 12 pin mask */ +#define LDD_ADC_CHANNEL_13_PIN 0x2000u /*!< Channel 13 pin mask */ +#define LDD_ADC_CHANNEL_14_PIN 0x4000u /*!< Channel 14 pin mask */ +#define LDD_ADC_CHANNEL_15_PIN 0x8000u /*!< Channel 15 pin mask */ +#define LDD_ADC_CHANNEL_16_PIN 0x00010000u /*!< Channel 16 pin mask */ +#define LDD_ADC_CHANNEL_17_PIN 0x00020000u /*!< Channel 17 pin mask */ +#define LDD_ADC_CHANNEL_18_PIN 0x00040000u /*!< Channel 18 pin mask */ +#define LDD_ADC_CHANNEL_19_PIN 0x00080000u /*!< Channel 19 pin mask */ +#define LDD_ADC_CHANNEL_20_PIN 0x00100000u /*!< Channel 20 pin mask */ +#define LDD_ADC_CHANNEL_21_PIN 0x00200000u /*!< Channel 21 pin mask */ +#define LDD_ADC_CHANNEL_22_PIN 0x00400000u /*!< Channel 22 pin mask */ +#define LDD_ADC_CHANNEL_23_PIN 0x00800000u /*!< Channel 23 pin mask */ +#define LDD_ADC_CHANNEL_24_PIN 0x01000000u /*!< Channel 24 pin mask */ +#define LDD_ADC_CHANNEL_25_PIN 0x02000000u /*!< Channel 25 pin mask */ +#define LDD_ADC_CHANNEL_26_PIN 0x04000000u /*!< Channel 26 pin mask */ +#define LDD_ADC_CHANNEL_27_PIN 0x08000000u /*!< Channel 27 pin mask */ +#define LDD_ADC_CHANNEL_28_PIN 0x10000000u /*!< Channel 28 pin mask */ +#define LDD_ADC_CHANNEL_29_PIN 0x20000000u /*!< Channel 29 pin mask */ +#define LDD_ADC_CHANNEL_30_PIN 0x40000000u /*!< Channel 30 pin mask */ +#define LDD_ADC_CHANNEL_31_PIN 0x80000000u /*!< Channel 31 pin mask */ +#define LDD_ADC_CHANNEL_32_PIN 0x01u /*!< Channel 32 pin mask */ +#define LDD_ADC_CHANNEL_33_PIN 0x02u /*!< Channel 33 pin mask */ +#define LDD_ADC_CHANNEL_34_PIN 0x04u /*!< Channel 34 pin mask */ +#define LDD_ADC_CHANNEL_35_PIN 0x08u /*!< Channel 35 pin mask */ +#define LDD_ADC_CHANNEL_36_PIN 0x10u /*!< Channel 36 pin mask */ +#define LDD_ADC_CHANNEL_37_PIN 0x20u /*!< Channel 37 pin mask */ +#define LDD_ADC_CHANNEL_38_PIN 0x40u /*!< Channel 38 pin mask */ +#define LDD_ADC_CHANNEL_39_PIN 0x80u /*!< Channel 39 pin mask */ +#define LDD_ADC_CHANNEL_40_PIN 0x0100u /*!< Channel 40 pin mask */ +#define LDD_ADC_CHANNEL_41_PIN 0x0200u /*!< Channel 41 pin mask */ +#define LDD_ADC_CHANNEL_42_PIN 0x0400u /*!< Channel 42 pin mask */ +#define LDD_ADC_CHANNEL_43_PIN 0x0800u /*!< Channel 43 pin mask */ +#define LDD_ADC_CHANNEL_44_PIN 0x1000u /*!< Channel 44 pin mask */ +#define LDD_ADC_CHANNEL_45_PIN 0x2000u /*!< Channel 45 pin mask */ +#define LDD_ADC_CHANNEL_46_PIN 0x4000u /*!< Channel 46 pin mask */ +#define LDD_ADC_CHANNEL_47_PIN 0x8000u /*!< Channel 47 pin mask */ +#define LDD_ADC_CHANNEL_48_PIN 0x00010000u /*!< Channel 48 pin mask */ +#define LDD_ADC_CHANNEL_49_PIN 0x00020000u /*!< Channel 49 pin mask */ +#define LDD_ADC_CHANNEL_50_PIN 0x00040000u /*!< Channel 50 pin mask */ +#define LDD_ADC_CHANNEL_51_PIN 0x00080000u /*!< Channel 51 pin mask */ +#define LDD_ADC_CHANNEL_52_PIN 0x00100000u /*!< Channel 52 pin mask */ +#define LDD_ADC_CHANNEL_53_PIN 0x00200000u /*!< Channel 53 pin mask */ +#define LDD_ADC_CHANNEL_54_PIN 0x00400000u /*!< Channel 54 pin mask */ +#define LDD_ADC_CHANNEL_55_PIN 0x00800000u /*!< Channel 55 pin mask */ +#define LDD_ADC_CHANNEL_56_PIN 0x01000000u /*!< Channel 56 pin mask */ +#define LDD_ADC_CHANNEL_57_PIN 0x02000000u /*!< Channel 57 pin mask */ +#define LDD_ADC_CHANNEL_58_PIN 0x04000000u /*!< Channel 58 pin mask */ +#define LDD_ADC_CHANNEL_59_PIN 0x08000000u /*!< Channel 59 pin mask */ +#define LDD_ADC_CHANNEL_60_PIN 0x10000000u /*!< Channel 60 pin mask */ +#define LDD_ADC_CHANNEL_61_PIN 0x20000000u /*!< Channel 61 pin mask */ +#define LDD_ADC_CHANNEL_62_PIN 0x40000000u /*!< Channel 62 pin mask */ +#define LDD_ADC_CHANNEL_63_PIN 0x80000000u /*!< Channel 63 pin mask */ + +#define LDD_ADC_TRIGGER_0_PIN 0x01u /*!< Trigger 0 pin mask */ +#define LDD_ADC_TRIGGER_1_PIN 0x02u /*!< Trigger 1 pin mask */ + +#define LDD_ADC_LOW_VOLT_REF_PIN 0x01u /*!< Low voltage reference pin mask */ +#define LDD_ADC_HIGH_VOLT_REF_PIN 0x02u /*!< High voltage reference pin mask */ + +#define LDD_ADC_ON_MEASUREMENT_COMPLETE 0x40u /*!< OnMeasurementComplete event mask */ +#define LDD_ADC_ON_ERROR 0x80u /*!< OnError event mask */ + +#define LDD_ADC_DMA_ERROR 0x01u /*!< DMA error mask */ + +typedef uint32 LDD_ADC_TErrorMask; /*!< ADC error type */ + +/*! Structure pins for pin connection method */ +typedef struct { + uint32 Channel0_31PinMask; /*!< Channel pin mask for channels 0 through 31 */ + uint32 Channel32_63PinMask; /*!< Channel pin mask for channels 32 through 63 */ + uint16 TriggerPinMask; /*!< Trigger pin mask */ + uint8 VoltRefPinMask; /*!< Voltage reference pin mask */ +} LDD_ADC_TPinMask; + +/*! Structure used to describing one sample */ +typedef struct { + uint8 ChannelIdx; /*!< Channel index */ +} LDD_ADC_TSample; + +/*! Type specifying the ADC compare mode */ +typedef enum { + LDD_ADC_LESS_THAN = 0x00u, /*!< Compare true if the result is less than the Low compare value */ + LDD_ADC_GREATER_THAN_OR_EQUAL = 0x01u, /*!< Compare true if the result is greater than or equal to Low compare value */ + LDD_ADC_INSIDE_RANGE_INCLUSIVE = 0x02u, /*!< Compare true if the result is greater than or equal to Low compare value and the result is less than or equal to High compare value */ + LDD_ADC_INSIDE_RANGE_NOT_INCLUSIVE = 0x03u, /*!< Compare true if the result is greater than Low compare value and the result is less than High compare value */ + LDD_ADC_OUTSIDE_RANGE_INCLUSIVE = 0x04u, /*!< Compare true if the result is less than or equal to Low compare value or the result is greater than or equal to High compare value */ + LDD_ADC_OUTSIDE_RANGE_NOT_INCLUSIVE = 0x05u /*!< Compare true if the result is less than Low compare value or the result is greater than High compare value */ +} LDD_ADC_TCompareMode; + +/* +** =================================================================== +** I2C device types and constants +** =================================================================== +*/ + +#define LDD_I2C_SDA_PIN 0x01u /*!< SDA pin mask */ +#define LDD_I2C_SCL_PIN 0x02u /*!< SCL pin mask */ + +#define LDD_I2C_ON_MASTER_BLOCK_SENT 0x0001u /*!< OnMasterBlockSent event mask */ +#define LDD_I2C_ON_MASTER_BLOCK_RECEIVED 0x0002u /*!< OnMasterBlockReceived event mask */ +#define LDD_I2C_ON_SLAVE_BLOCK_SENT 0x0004u /*!< OnSlaveBlockSent event mask */ +#define LDD_I2C_ON_SLAVE_BLOCK_RECEIVED 0x0008u /*!< OnSlaveBlockReceived event mask */ +#define LDD_I2C_ON_SLAVE_TX_REQUEST 0x0010u /*!< OnSlaveTxRequest event mask */ +#define LDD_I2C_ON_SLAVE_RX_REQUEST 0x0020u /*!< OnSlaveRxRequest event mask */ +#define LDD_I2C_ON_ERROR 0x0040u /*!< OnError event mask */ +#define LDD_I2C_ON_SLAVE_SM_BUS_CALL_ADDR 0x0080u /*!< OnSlaveSMBusCallAddr event mask */ +#define LDD_I2C_ON_SLAVE_SM_BUS_ALERT_RESPONSE 0x0100u /*!< OnSlaveSMBusAlertResponse event mask */ +#define LDD_I2C_ON_SLAVE_GENERAL_CALL_ADDR 0x0200u /*!< OnSlaveGeneralCallAddr event mask */ +#define LDD_I2C_ON_MASTER_BYTE_RECEIVED 0x0400u /*!< OnMasterByteReceived event mask */ +#define LDD_I2C_ON_SLAVE_BYTE_RECEIVED 0x0800u /*!< OnMasterByteReceived event mask */ +#define LDD_I2C_ON_BUS_START_DETECTED 0x1000u /*!< OnBusStartDetected event mask */ +#define LDD_I2C_ON_BUS_STOP_DETECTED 0x2000u /*!< OnBusStopDetected event mask */ + +#define LDD_I2C_SLAVE_TX_UNDERRUN 0x0001u /*!< SlaveTxUnderrun error mask */ +#define LDD_I2C_SLAVE_RX_OVERRUN 0x0002u /*!< SlaveRxOverrun error mask */ +#define LDD_I2C_ARBIT_LOST 0x0004u /*!< ArbitLost error mask */ +#define LDD_I2C_MASTER_NACK 0x0008u /*!< MasterNACK error mask */ +#define LDD_I2C_SCL_LOW_TIMEOUT 0x0010u /*!< SCLLowTimeout error mask */ +#define LDD_I2C_SDA_LOW_TIMEOUT 0x0020u /*!< SDALowTimeout error mask */ +#define LDD_I2C_SLAVE_NACK 0x0040u /*!< SlaveNACK error mask */ + +typedef uint16 LDD_I2C_TSize; /*!< Type specifying the length of the data or buffer. */ +typedef uint16 LDD_I2C_TAddr; /*!< Type specifying the address variable */ +typedef uint16 LDD_I2C_TErrorMask; /*!< Type specifying the error mask type. */ +typedef bool LDD_I2C_TMode; /*!< Type specifynng the Actual operating mode */ + +/*! Type specifying the address type */ +typedef enum { + LDD_I2C_ADDRTYPE_7BITS, /*!< 7 bits address */ + LDD_I2C_ADDRTYPE_10BITS, /*!< 10 bits address */ + LDD_I2C_ADDRTYPE_GENERAL_CALL /*!< General call address */ +} LDD_I2C_TAddrType; + +/*! Type specifying generate the stop condition */ +typedef enum { + LDD_I2C_NO_SEND_STOP, /*!< Do not send stop signal */ + LDD_I2C_SEND_STOP /*!< Send stop signal */ +} LDD_I2C_TSendStop; + +/*! Type specifying the I2C state of BUS. */ +typedef enum { + LDD_I2C_BUSY, /*!< The bus is busy */ + LDD_I2C_IDLE /*!< The bus is idle */ +} LDD_I2C_TBusState; + +/*! Type specifying the I2C byte acknowledge response. */ +typedef enum { + LDD_I2C_ACK_BYTE, /*!< Byte acknowledged */ + LDD_I2C_NACK_BYTE /*!< Byte not acknowledged */ +} LDD_I2C_TAckType; + +/*! Communication statistics */ +typedef struct { + uint32 MasterSentChars; /*!< Number of master transmitted characters. */ + uint32 MasterReceivedChars; /*!< Number of master received characters. */ + uint32 MasterNacks; /*!< Number of no acknowledges. */ + uint32 ArbitLost; /*!< Number of lost the bus arbitration. */ + uint32 SlaveSentChars; /*!< Number of slave transmitted characters. */ + uint32 SlaveReceivedChars; /*!< Number of slave received characters. */ + uint32 SlaveTxUnderrun; /*!< Number of slave underrun. */ + uint32 SlaveRxOverrun; /*!< Number of slave overrun. */ + uint32 SlaveGeneralCallAddr; /*!< Number of a general call address. */ + uint32 SlaveSmBusCallAddr; /*!< Number of a SMBus call address. */ + uint32 SlaveSmBusAlertResponse; /*!< Number of slave SMBus alert response received. */ + uint32 SCLLowTimeout; /*!< Number of SCL low timeout occur. */ + uint32 SDALowTimeout; /*!< Number of SCL low timeout occur. */ +} LDD_I2C_TStats; + + +/* +** =================================================================== +** SegLCD device types and constants +** =================================================================== +*/ + +#define LDD_SEGLCD_ON_FRAME_FREQUENCY 0x0001u /*!< OnFrameFrequency event mask */ +#define LDD_SEGLCD_ON_FAULT_DETECT_COMPLETE 0x0002u /*!< OnFaultDetectComplete event mask */ + +typedef uint8 LDD_SegLCD_TPinIndex; /*!< Type specifying the segment LCD pin index variable */ +typedef uint8 LDD_SegLCD_TFrontplaneData; /*!< Type specifying the frontplane/backplane segment variable */ +typedef uint8 LDD_SegLCD_TFaultValue; /*!< Type specifying the frontplane/backplane segment variable */ + +/*! Types specifying the segment LCD blinking. */ +typedef enum { + LDD_SEGLCD_BLINK_OFF, /*!< Disables display blinking */ + LDD_SEGLCD_BLINK_ALL, /*!< Display blank during the blink period */ + LDD_SEGLCD_BLINK_ALL_ALTERNATE /*!< Blinking between alternate backplane */ +} LDD_SegLCD_TBlinking; + +/*! Segment LCD blank state type. */ +typedef enum { + LDD_SEGLCD_BLANK_STATE, /*!< Blank display mode */ + LDD_SEGLCD_NORMAL_STATE, /*!< Normal display mode */ + LDD_SEGLCD_ALTERNATE_STATE /*!< Alternate display mode */ +} LDD_SegLCD_TSetBlank; + +/*! Segment LCD pin type (frontplane/backplane) */ +typedef enum { + LDD_SEGLCD_BACKPLANE_PIN, /*!< Backplane pin */ + LDD_SEGLCD_FRONTPLANE_PIN /*!< Frontplane pin */ +} LDD_SegLCD_TPinType; + + +/* +** =================================================================== +** GPIO device types and constants +** =================================================================== +*/ + +#define LDD_GPIO_PIN_0 0x01u /*!< Pin 0 inside the port */ +#define LDD_GPIO_PIN_1 0x02u /*!< Pin 1 inside the port */ +#define LDD_GPIO_PIN_2 0x04u /*!< Pin 2 inside the port */ +#define LDD_GPIO_PIN_3 0x08u /*!< Pin 3 inside the port */ +#define LDD_GPIO_PIN_4 0x10u /*!< Pin 4 inside the port */ +#define LDD_GPIO_PIN_5 0x20u /*!< Pin 5 inside the port */ +#define LDD_GPIO_PIN_6 0x40u /*!< Pin 6 inside the port */ +#define LDD_GPIO_PIN_7 0x80u /*!< Pin 7 inside the port */ +#define LDD_GPIO_PIN_8 0x0100u /*!< Pin 8 inside the port */ +#define LDD_GPIO_PIN_9 0x0200u /*!< Pin 9 inside the port */ +#define LDD_GPIO_PIN_10 0x0400u /*!< Pin 10 inside the port */ +#define LDD_GPIO_PIN_11 0x0800u /*!< Pin 11 inside the port */ +#define LDD_GPIO_PIN_12 0x1000u /*!< Pin 12 inside the port */ +#define LDD_GPIO_PIN_13 0x2000u /*!< Pin 13 inside the port */ +#define LDD_GPIO_PIN_14 0x4000u /*!< Pin 14 inside the port */ +#define LDD_GPIO_PIN_15 0x8000u /*!< Pin 15 inside the port */ +#define LDD_GPIO_PIN_16 0x00010000u /*!< Pin 16 inside the port */ +#define LDD_GPIO_PIN_17 0x00020000u /*!< Pin 17 inside the port */ +#define LDD_GPIO_PIN_18 0x00040000u /*!< Pin 18 inside the port */ +#define LDD_GPIO_PIN_19 0x00080000u /*!< Pin 19 inside the port */ +#define LDD_GPIO_PIN_20 0x00100000u /*!< Pin 20 inside the port */ +#define LDD_GPIO_PIN_21 0x00200000u /*!< Pin 21 inside the port */ +#define LDD_GPIO_PIN_22 0x00400000u /*!< Pin 22 inside the port */ +#define LDD_GPIO_PIN_23 0x00800000u /*!< Pin 23 inside the port */ +#define LDD_GPIO_PIN_24 0x01000000u /*!< Pin 24 inside the port */ +#define LDD_GPIO_PIN_25 0x02000000u /*!< Pin 25 inside the port */ +#define LDD_GPIO_PIN_26 0x04000000u /*!< Pin 26 inside the port */ +#define LDD_GPIO_PIN_27 0x08000000u /*!< Pin 27 inside the port */ +#define LDD_GPIO_PIN_28 0x10000000u /*!< Pin 28 inside the port */ +#define LDD_GPIO_PIN_29 0x20000000u /*!< Pin 29 inside the port */ +#define LDD_GPIO_PIN_30 0x40000000u /*!< Pin 30 inside the port */ +#define LDD_GPIO_PIN_31 0x80000000u /*!< Pin 31 inside the port */ + +#define LDD_GPIO_ON_PORT_EVENT 0x01u /*!< OnPortEvent event mask */ + +typedef uint32 LDD_GPIO_TBitField; /*!< Abstract type specifying the bit field within the port. */ + +/*! Defines condition when event is invoked. */ +typedef enum { + LDD_GPIO_DISABLED = 0x00u, /*!< Event doesn't invoke */ + LDD_GPIO_LOW = 0x00080000u, /*!< Event when logic zero */ + LDD_GPIO_HIGH = 0x000C0000u, /*!< Event when logic one */ + LDD_GPIO_RISING = 0x00090000u, /*!< Event on rising edge */ + LDD_GPIO_FALLING = 0x000A0000u, /*!< Event on falling edge */ + LDD_GPIO_BOTH = 0x000B0000u /*!< Event on rising and falling edge */ +} LDD_GPIO_TEventCondition; /*!< Defines condition when event is invoked. */ + +#define LDD_GPIO_EVENT_CONDITIONS_MASK 0x000F0000u + +/* +** =================================================================== +** BITSIO device types and constants +** =================================================================== +*/ +#define LDD_BITSIO_PIN_0 0x01U /*!< Pin 0 inside pin list of component */ +#define LDD_BITSIO_PIN_1 0x02U /*!< Pin 1 inside pin list of component */ +#define LDD_BITSIO_PIN_2 0x04U /*!< Pin 2 inside pin list of component */ +#define LDD_BITSIO_PIN_3 0x08U /*!< Pin 3 inside pin list of component */ +#define LDD_BITSIO_PIN_4 0x10U /*!< Pin 4 inside pin list of component */ +#define LDD_BITSIO_PIN_5 0x20U /*!< Pin 5 inside pin list of component */ +#define LDD_BITSIO_PIN_6 0x40U /*!< Pin 6 inside pin list of component */ +#define LDD_BITSIO_PIN_7 0x80U /*!< Pin 7 inside pin list of component */ +#define LDD_BITSIO_PIN_8 0x0100U /*!< Pin 8 inside pin list of component */ +#define LDD_BITSIO_PIN_9 0x0200U /*!< Pin 9 inside pin list of component */ +#define LDD_BITSIO_PIN_10 0x0400U /*!< Pin 10 inside pin list of component */ +#define LDD_BITSIO_PIN_11 0x0800U /*!< Pin 11 inside pin list of component */ +#define LDD_BITSIO_PIN_12 0x1000U /*!< Pin 12 inside pin list of component */ +#define LDD_BITSIO_PIN_13 0x2000U /*!< Pin 13 inside pin list of component */ +#define LDD_BITSIO_PIN_14 0x4000U /*!< Pin 14 inside pin list of component */ +#define LDD_BITSIO_PIN_15 0x8000U /*!< Pin 15 inside pin list of component */ +#define LDD_BITSIO_PIN_16 0x00010000U /*!< Pin 16 inside pin list of component */ +#define LDD_BITSIO_PIN_17 0x00020000U /*!< Pin 17 inside pin list of component */ +#define LDD_BITSIO_PIN_18 0x00040000U /*!< Pin 18 inside pin list of component */ +#define LDD_BITSIO_PIN_19 0x00080000U /*!< Pin 19 inside pin list of component */ +#define LDD_BITSIO_PIN_20 0x00100000U /*!< Pin 20 inside pin list of component */ +#define LDD_BITSIO_PIN_21 0x00200000U /*!< Pin 21 inside pin list of component */ +#define LDD_BITSIO_PIN_22 0x00400000U /*!< Pin 22 inside pin list of component */ +#define LDD_BITSIO_PIN_23 0x00800000U /*!< Pin 23 inside pin list of component */ +#define LDD_BITSIO_PIN_24 0x01000000U /*!< Pin 24 inside pin list of component */ +#define LDD_BITSIO_PIN_25 0x02000000U /*!< Pin 25 inside pin list of component */ +#define LDD_BITSIO_PIN_26 0x04000000U /*!< Pin 26 inside pin list of component */ +#define LDD_BITSIO_PIN_27 0x08000000U /*!< Pin 27 inside pin list of component */ +#define LDD_BITSIO_PIN_28 0x10000000U /*!< Pin 28 inside pin list of component */ +#define LDD_BITSIO_PIN_29 0x20000000U /*!< Pin 29 inside pin list of component */ +#define LDD_BITSIO_PIN_30 0x40000000U /*!< Pin 30 inside pin list of component */ +#define LDD_BITSIO_PIN_31 0x80000000U /*!< Pin 31 inside pin list of component */ + +/* +** =================================================================== +** Ethernet device types and constants +** =================================================================== +*/ + +#define LDD_ETH_MDC_PIN 0x01u /*!< MDC pin mask */ +#define LDD_ETH_MDIO_PIN 0x02u /*!< MDIO pin mask */ +#define LDD_ETH_COL_PIN 0x04u /*!< COL pin mask */ +#define LDD_ETH_CRS_PIN 0x08u /*!< CRS pin mask */ +#define LDD_ETH_TXCLK_PIN 0x10u /*!< TXCLK pin mask */ +#define LDD_ETH_TXD0_PIN 0x20u /*!< TXD0 pin mask */ +#define LDD_ETH_TXD1_PIN 0x40u /*!< TXD1 pin mask */ +#define LDD_ETH_TXD2_PIN 0x80u /*!< TXD2 pin mask */ +#define LDD_ETH_TXD3_PIN 0x0100u /*!< TXD3 pin mask */ +#define LDD_ETH_TXEN_PIN 0x0200u /*!< TXEN pin mask */ +#define LDD_ETH_TXER_PIN 0x0400u /*!< TXER pin mask */ +#define LDD_ETH_RXCLK_PIN 0x0800u /*!< RXCLK pin mask */ +#define LDD_ETH_RXDV_PIN 0x1000u /*!< RXDV pin mask */ +#define LDD_ETH_RXD0_PIN 0x2000u /*!< RXD0 pin mask */ +#define LDD_ETH_RXD1_PIN 0x4000u /*!< RXD1 pin mask */ +#define LDD_ETH_RXD2_PIN 0x8000u /*!< RXD2 pin mask */ +#define LDD_ETH_RXD3_PIN 0x00010000u /*!< RXD3 pin mask */ +#define LDD_ETH_RXER_PIN 0x00020000u /*!< RXER pin mask */ + +#define LDD_ETH_ON_FRAME_TRANSMITTED 0x01u /*!< OnFrameTransmitted event mask */ +#define LDD_ETH_ON_FRAME_TRANSMITTED_TIMESTAMPED 0x02u /*!< OnFrameTransmittedTimestamped event mask */ +#define LDD_ETH_ON_FRAME_RECEIVED 0x04u /*!< OnFrameReceived event mask */ +#define LDD_ETH_ON_FRAME_RECEIVED_TIMESTAMPED 0x08u /*!< OnFrameReceivedTimestamped event mask */ +#define LDD_ETH_ON_MII_FINISHED 0x10u /*!< OnMIIFinished event mask */ +#define LDD_ETH_ON_FATAL_ERROR 0x20u /*!< OnFatalError event mask */ +#define LDD_ETH_ON_WAKE_UP 0x40u /*!< OnWakeUp event mask */ + +typedef uint8 LDD_ETH_TMACAddress[6]; /*!< Ethernet MAC address */ + +/*! Ethernet duplex mode */ +typedef enum { + LDD_ETH_FULL_DUPLEX, /*!< Full duplex mode */ + LDD_ETH_HALF_DUPLEX /*!< Half duplex mode */ +} LDD_ETH_TDuplexMode; + +/*! Ethernet address filter mode options */ +typedef enum { + LDD_ETH_PROMISC, /*!< Promiscuous mode */ + LDD_ETH_REJECT_BC, /*!< Reject broadcast frames */ + LDD_ETH_ACCEPT_BC /*!< Accept broadcast frames */ +} LDD_ETH_TFilterMode; + +/*! Ethernet sleep mode options */ +typedef enum { + LDD_ETH_ENABLED, /*!< Sleep mode enabled */ + LDD_ETH_ENABLED_WITH_WAKEUP, /*!< Sleep mode enabled, waiting for wake-up */ + LDD_ETH_DISABLED /*!< Sleep mode disabled */ +} LDD_ETH_TSleepMode; + +/*! Ethernet frame buffer (fragment) descriptor */ +typedef struct { + uint8 *DataPtr; /*!< Pointer to buffer data */ + uint16 Size; /*!< Buffer data size */ +} LDD_ETH_TBufferDesc; + +typedef LDD_ETH_TBufferDesc* LDD_ETH_TBufferDescPtr; /*!< Frame buffer descriptor pointer type */ + +/*! Ethernet communication statistics */ +typedef struct { + uint32 TxRMONDropEvents; /*!< Count of frames not counted correctly */ + uint32 TxRMONOctets; /*!< Octet count for frames transmitted without error */ + uint32 TxRMONPackets; /*!< Transmitted packet count */ + uint32 TxRMONBroadcastPackets; /*!< Transmitted broadcast packets */ + uint32 TxRMONMulticastPackets; /*!< Transmitted multicast packets */ + uint32 TxRMONCRCAlignErrors; /*!< Transmitted packets with CRC or alignment error */ + uint32 TxRMONUndersizePackets; /*!< Transmitted packets smaller than 64 bytes with good CRC */ + uint32 TxRMONOversizePackets; /*!< Transmitted packets greater than max. frame length with good CRC */ + uint32 TxRMONFragments; /*!< Transmitted packets smaller than 64 bytes with bad CRC */ + uint32 TxRMONJabbers; /*!< Transmitted packets greater than max. frame length with bad CRC */ + uint32 TxRMONCollisions; /*!< Transmit collision count */ + uint32 TxRMONPackets64Octets; /*!< Transmitted 64 byte packets */ + uint32 TxRMONPackets65To127Octets; /*!< Transmitted 65 to 127 byte packets */ + uint32 TxRMONPackets128To255Octets; /*!< Transmitted 128 to 255 byte packets */ + uint32 TxRMONPackets256To511Octets; /*!< Transmitted 256 to 511 byte packets */ + uint32 TxRMONPackets512To1023Octets; /*!< Transmitted 512 to 1023 byte packets */ + uint32 TxRMONPackets1024To2047Octets; /*!< Transmitted 1024 to 2047 byte packets */ + uint32 TxRMONPacketsGreaterThan2048Octets; /*!< Transmitted packets greater than 2048 byte */ + uint32 TxIEEEDrop; /*!< Count of frames not counted correctly */ + uint32 TxIEEEFrameOK; /*!< Frames transmitted OK */ + uint32 TxIEEESingleCollision; /*!< Frames transmitted with single collision */ + uint32 TxIEEEMultipleCollisions; /*!< Frames transmitted with multiple collisions */ + uint32 TxIEEEDeferralDelay; /*!< Frames transmitted after deferral delay */ + uint32 TxIEEELateCollision; /*!< Frames transmitted with late collision */ + uint32 TxIEEEExcessiveCollision; /*!< Frames transmitted with excessive collisions */ + uint32 TxIEEEFIFOUnderrun; /*!< Frames transmitted with transmit FIFO underrun */ + uint32 TxIEEECarrierSenseError; /*!< Frames transmitted with carrier sense error */ + uint32 TxIEEESQEError; /*!< Frames transmitted with SQE error */ + uint32 TxIEEEPauseFrame; /*!< Flow control pause frames transmitted */ + uint32 TxIEEEOctetsOK; /*!< Octet count for frames transmitted without error */ + uint32 RxRMONDropEvents; /*!< Count of frames not counted correctly */ + uint32 RxRMONOctets; /*!< Octet count for frames recieved without error */ + uint32 RxRMONPackets; /*!< Received packet count */ + uint32 RxRMONBroadcastPackets; /*!< Received broadcast packets */ + uint32 RxRMONMulticastPackets; /*!< Received multicast packets */ + uint32 RxRMONCRCAlignErrors; /*!< Received packets with CRC or alignment error */ + uint32 RxRMONUndersizePackets; /*!< Received packets smaller than 64 bytes with good CRC */ + uint32 RxRMONOversizePackets; /*!< Received packets greater than max. frame length with good CRC */ + uint32 RxRMONFragments; /*!< Received packets smaller than 64 bytes with bad CRC */ + uint32 RxRMONJabbers; /*!< Received packets greater than max. frame length with bad CRC */ + uint32 RxRMONPackets64Octets; /*!< Received 64 byte packets */ + uint32 RxRMONPackets65To127Octets; /*!< Received 65 to 127 byte packets */ + uint32 RxRMONPackets128To255Octets; /*!< Received 128 to 255 byte packets */ + uint32 RxRMONPackets256To511Octets; /*!< Received 256 to 511 byte packets */ + uint32 RxRMONPackets512To1023Octets; /*!< Received 512 to 1023 byte packets */ + uint32 RxRMONPackets1024To2047Octets; /*!< Received 1024 to 2047 byte packets */ + uint32 RxRMONPacketsGreaterThan2048Octets; /*!< Received packets greater than 2048 byte */ + uint32 RxIEEEDrop; /*!< Count of frames not counted correctly */ + uint32 RxIEEEFrameOK; /*!< Frames received OK */ + uint32 RxIEEECRCError; /*!< Frames received with CRC error */ + uint32 RxIEEEAlignmentError; /*!< Frames received with alignment error */ + uint32 RxIEEEFIFOOverflow; /*!< Receive FIFO overflow count */ + uint32 RxIEEEPauseFrame; /*!< Flow control pause frames received */ + uint32 RxIEEEOctetsOK; /*!< Octet count for frames received without error */ +} LDD_ETH_TStats; + +/* +** =================================================================== +** FlexCAN device types and constants +** =================================================================== +*/ + +typedef uint8 LDD_CAN_TMBIndex; /*!< CAN message buffer index */ +typedef uint32 LDD_CAN_TAccMask; /*!< Type specifying the acceptance mask variable. */ +typedef uint32 LDD_CAN_TMessageID; /*!< Type specifying the ID mask variable. */ +typedef uint8 LDD_CAN_TErrorCounter; /*!< Type specifying the error counter variable. */ +typedef uint32 LDD_CAN_TErrorMask; /*!< Type specifying the error mask variable. */ +typedef uint16 LDD_CAN_TBufferMask; /*!< Type specifying the message buffer mask variable. */ +#define LDD_CAN_RX_PIN 0x01U /*!< Rx pin mask */ +#define LDD_CAN_TX_PIN 0x02U /*!< Tx pin mask */ + +#define LDD_CAN_ON_FULL_RXBUFFER 0x01U /*!< OnFullRxBuffer event mask */ +#define LDD_CAN_ON_FREE_TXBUFFER 0x02U /*!< OnFreeTxBuffer event mask */ +#define LDD_CAN_ON_BUSOFF 0x04U /*!< OnBusOff event mask */ +#define LDD_CAN_ON_TXWARNING 0x08U /*!< OnTransmitterWarning event mask */ +#define LDD_CAN_ON_RXWARNING 0x10U /*!< OnReceiverWarning event mask */ +#define LDD_CAN_ON_ERROR 0x20U /*!< OnError event mask */ +#define LDD_CAN_ON_WAKEUP 0x40U /*!< OnWakeUp event mask */ + +#define LDD_CAN_BIT0_ERROR 0x4000UL /*!< Bit0 error detect error mask */ +#define LDD_CAN_BIT1_ERROR 0x8000UL /*!< Bit1 error detect error mask */ +#define LDD_CAN_ACK_ERROR 0x2000UL /*!< Acknowledge error detect error mask */ +#define LDD_CAN_CRC_ERROR 0x1000UL /*!< Cyclic redundancy check error detect error mask */ +#define LDD_CAN_FORM_ERROR 0x0800UL /*!< Message form error detect error mask */ +#define LDD_CAN_STUFFING_ERROR 0x0400UL /*!< Bit stuff error detect error mask */ + +#define LDD_CAN_MESSAGE_ID_EXT 0x80000000UL /*!< Value specifying extended Mask, ID */ + +/*! Type specifying the CAN frame type. */ +typedef enum { + LDD_CAN_MB_RX_NOT_ACTIVE = 0x00U, + LDD_CAN_MB_RX_FULL = 0x02U, + LDD_CAN_MB_RX_EMPTY = 0x04U, + LDD_CAN_MB_RX_OVERRUN = 0x06U, + LDD_CAN_MB_RX_BUSY = 0x01U, + LDD_CAN_MB_RX_RANSWER = 0x0AU +} LDD_CAN_TRxBufferState; + +/*! Type specifying the CAN frame type. */ +typedef enum { + LDD_CAN_DATA_FRAME, /*!< Data frame type received or transmitted */ + LDD_CAN_REMOTE_FRAME, /*!< Remote frame type */ + LDD_CAN_RESPONSE_FRAME /*!< Response frame type - Tx buffer send data after receiving remote frame with the same ID */ +} LDD_CAN_TFrameType; + +/*! Type specifying the CAN communication statistics. */ +typedef struct { + uint32 TxFrames; /*!< Transmitted frame counter */ + uint32 TxWarnings; /*!< Transmission warning counter */ + uint32 RxFrames; /*!< Received frame counter */ + uint32 RxWarnings; /*!< Reception warning counter */ + uint32 BusOffs; /*!< Bus off counter */ + uint32 Wakeups; /*!< Wakeup counter */ + uint32 Bit0Errors; /*!< Bit0 error counter */ + uint32 Bit1Errors; /*!< Bit1 error counter */ + uint32 AckErrors; /*!< ACK error counter */ + uint32 CrcErrors; /*!< CRC error counter */ + uint32 FormErrors; /*!< Message form error counter */ + uint32 BitStuffErrors; /*!< Bit stuff error counter */ + uint32 Errors; /*!< Error counter */ +} LDD_CAN_TStats; + +/*! Type specifying the CAN frame features. */ +typedef struct { + LDD_CAN_TMessageID MessageID; /*!< Message ID */ + LDD_CAN_TFrameType FrameType; /*!< Type of the frame DATA/REMOTE */ + uint8 *Data; /*!< Message data buffer */ + uint8 Length; /*!< Message length */ + uint16 TimeStamp; /*!< Message time stamp */ + uint8 LocPriority; /*!< Local Priority Tx Buffers */ +} LDD_CAN_TFrame; + +/* +** =================================================================== +** USB device types and constants +** =================================================================== +*/ + +/* Events' masks */ +#define LDD_USB_ON_DEVICE_RESET 0x00000001u /*!< OnDeviceReset event mask */ +#define LDD_USB_ON_DEVICE_SPEED_DETECT 0x00000002u /*!< OnDeviceSpeedDetect event mask */ +#define LDD_USB_ON_DEVICE_SUSPEND 0x00000004u /*!< OnDeviceSuspend event mask */ +#define LDD_USB_ON_DEVICE_RESUME 0x00000008u /*!< OnDeviceResume event mask */ +#define LDD_USB_ON_DEVICE_SETUP_PACKET 0x00000010u /*!< OnDeviceSetupPacket event mask */ +#define LDD_USB_ON_DEVICE_SOF 0x00000020u /*!< OnDeviceSof event mask */ +#define LDD_USB_ON_DEVICE_1MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */ +#define LDD_USB_ON_DEVICE_1_MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */ +#define LDD_USB_ON_DEVICE_ERROR 0x00000080u /*!< OnDeviceError event mask */ +#define LDD_USB_ON_HOST_DEVICE_DEATTACH 0x00000100u /*!< OnHostDeviceAttach event mask */ +#define LDD_USB_ON_HOST_RESET_RECOVERY 0x00000200u /*!< OnHostResetRecovery event mask */ +#define LDD_USB_ON_HOST_RESUME_RECOVERY 0x00000400u /*!< OnHostResumeRecovery event mask */ +#define LDD_USB_ON_HOST_1MS_TIMER 0x00000800u /*!< 1 ms timer event mask */ +#define LDD_USB_ON_HOST_1_MS_TIMER 0x00000800u /*!< 1 ms timer event mask */ +#define LDD_USB_ON_HOST_ERROR 0x00001000u /*!< OnHostError event mask */ +#define LDD_USB_ON_OTG_DEVICE 0x00002000u /*!< OnOtgDevice event mask */ +#define LDD_USB_ON_OTG_HOST 0x00004000u /*!< OnOtgHost event mask */ +#define LDD_USB_ON_OTG_STATE_CHANGE 0x00008000u /*!< OnOtgStageChange event mask */ +#define LDD_USB_ON_SIGNAL_CHANGE 0x00010000u /*!< OnSignalChange event mask */ + +/* Data pins' masks */ +#define LDD_USB_DP_PIN 0x00000001u /*!< Data+ pin mask */ +#define LDD_USB_DM_PIN 0x00000002u /*!< Data- pin mask */ + +/* Pullup/pulldown pin masks */ +#define LDD_USB_DP_PU_PIN 0x00000004u /*!< Data+ pull-up pin mask */ +#define LDD_USB_DM_PU_PIN 0x00000008u /*!< Data- pull-up pin mask */ +#define LDD_USB_DP_PD_PIN 0x00000010u /*!< Data+ pull-down pin mask */ +#define LDD_USB_DM_PD_PIN 0x00000020u /*!< Data- pull-down pin mask */ + +/* VBUS pins' mask */ +#define LDD_USB_DEVICE_VBUS_DETECT_PIN 0x00000040u /*!< VBUS detect pin mask */ +#define LDD_USB_HOST_VBUS_ENABLE_PIN 0x00000080u /*!< VBUS enable pin mask */ +#define LDD_USB_HOST_VBUS_OVERCURRENT_PIN 0x00000100u /*!< VBUS overcurrent pin mask */ + +/* OTG pins' masks */ +#define LDD_USB_OTG_ID_PIN 0x00000200u /*!< ID pin mask */ +#define LDD_USB_OTG_VBUS_VALID_PIN 0x00000400u /*!< VBUS valid pin mask */ +#define LDD_USB_OTG_SESSION_VALID_PIN 0x00000800u /*!< SESSION valid pin mask */ +#define LDD_USB_OTG_B_SESSION_END_PIN 0x00004000u /*!< B SESSION end pin mask */ +#define LDD_USB_OTG_VBUS_ENABLE_PIN 0x00008000u /*!< VBUS drive pin mask */ +#define LDD_USB_OTG_VBUS_CHARGE_PIN 0x00010000u /*!< VBUS charge pin mask */ +#define LDD_USB_OTG_VBUS_DISCHARGE_PIN 0x00020000u /*!< VBUS discharge pin mask */ + +/* ULPI pins' masks */ +#define LDD_USB_ULPI_CLK_PIN 0x00080000u /*!< ULPI_CLK pin mask */ +#define LDD_USB_ULPI_DIR_PIN 0x00100000u /*!< ULPI_DIR pin mask */ +#define LDD_USB_ULPI_NXT_PIN 0x00200000u /*!< ULPI_NXT pin mask */ +#define LDD_USB_ULPI_STP_PIN 0x00400000u /*!< ULPI_STOP pin mask */ +#define LDD_USB_ULPI_DATA_0_PIN 0x00800000u /*!< ULPI_DATA_0 pin mask */ +#define LDD_USB_ULPI_DATA_1_PIN 0x01000000u /*!< ULPI_DATA_1 pin mask */ +#define LDD_USB_ULPI_DATA_2_PIN 0x02000000u /*!< ULPI_DATA_2 pin mask */ +#define LDD_USB_ULPI_DATA_3_PIN 0x04000000u /*!< ULPI_DATA_3 pin mask */ +#define LDD_USB_ULPI_DATA_4_PIN 0x08000000u /*!< ULPI_DATA_4 pin mask */ +#define LDD_USB_ULPI_DATA_5_PIN 0x10000000u /*!< ULPI_DATA_5 pin mask */ +#define LDD_USB_ULPI_DATA_6_PIN 0x20000000u /*!< ULPI_DATA_6 pin mask */ +#define LDD_USB_ULPI_DATA_7_PIN 0x40000000u /*!< ULPI_DATA_7 pin mask */ + +/* Alternate clock pin*/ +#define LDD_USB_CLKIN_PIN 0x80000000u /*!< Alternate clock pin mask */ +#define LDD_USB_ALT_CLK_PIN 0x80000000u /*!< Alternate clock pin mask */ + +/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Cmd/CmdStatusPtr param. values */ +#define LDD_USB_CMD_GET_EP_STATUS 0x00u /*!< Get endpoint status command ID */ +#define LDD_USB_CMD_SET_EP_HALT_FATURE 0x01u /*!< Set endpoint HALT feature command ID */ +#define LDD_USB_CMD_CLR_EP_HALT_FATURE 0x02u /*!< Clear endpoint HALT feature command ID */ + +#define LDD_USB_CMD_EP_STATUS_HALT_MASK 0x01u /*!< Endpoint halt status mask */ + + +/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Recipient param. values */ +/* (see USB 2.0, chapter 9.3.4 wIndex description)*/ +#define LDD_USB_ID_EP0_OUT 0x00u /*!< EP0 OUT component ID */ +#define LDD_USB_ID_EP0_IN 0x80u /*!< EP0 IN component ID */ +#define LDD_USB_ID_EP1_OUT 0x01u /*!< EP1 OUT component ID */ +#define LDD_USB_ID_EP1_IN 0x81u /*!< EP1 IN component ID */ +#define LDD_USB_ID_EP2_OUT 0x02u /*!< EP2 OUT component ID */ +#define LDD_USB_ID_EP2_IN 0x82u /*!< EP2 IN component ID */ +#define LDD_USB_ID_EP3_OUT 0x03u /*!< EP3 OUT component ID */ +#define LDD_USB_ID_EP3_IN 0x83u /*!< EP3 IN component ID */ +#define LDD_USB_ID_EP4_OUT 0x04u /*!< EP4 OUT component ID */ +#define LDD_USB_ID_EP4_IN 0x84u /*!< EP4 IN component ID */ +#define LDD_USB_ID_EP5_OUT 0x05u /*!< EP5 OUT component ID */ +#define LDD_USB_ID_EP5_IN 0x85u /*!< EP5 IN component ID */ +#define LDD_USB_ID_EP6_OUT 0x06u /*!< EP6 OUT component ID */ +#define LDD_USB_ID_EP6_IN 0x86u /*!< EP6 IN component ID */ +#define LDD_USB_ID_EP7_OUT 0x07u /*!< EP7 OUT component ID */ +#define LDD_USB_ID_EP7_IN 0x87u /*!< EP7 IN component ID */ +#define LDD_USB_ID_EP8_OUT 0x08u /*!< EP8 OUT component ID */ +#define LDD_USB_ID_EP8_IN 0x88u /*!< EP8 IN component ID */ +#define LDD_USB_ID_EP9_OUT 0x09u /*!< EP9 OUT component ID */ +#define LDD_USB_ID_EP9_IN 0x89u /*!< EP9 IN component ID */ +#define LDD_USB_ID_EP10_OUT 0x0Au /*!< EP10 OUT component ID */ +#define LDD_USB_ID_EP10_IN 0x8Au /*!< EP10 IN component ID */ +#define LDD_USB_ID_EP11_OUT 0x0Bu /*!< EP11 OUT component ID */ +#define LDD_USB_ID_EP11_IN 0x8Bu /*!< EP11 IN component ID */ +#define LDD_USB_ID_EP12_OUT 0x0Cu /*!< EP12 OUT component ID */ +#define LDD_USB_ID_EP12_IN 0x8Cu /*!< EP12 IN component ID */ +#define LDD_USB_ID_EP13_OUT 0x0Du /*!< EP13 OUT component ID */ +#define LDD_USB_ID_EP13_IN 0x8Du /*!< EP13 IN component ID */ +#define LDD_USB_ID_EP14_OUT 0x0Eu /*!< EP14 OUT component ID */ +#define LDD_USB_ID_EP14_IN 0x8Eu /*!< EP14 IN component ID */ +#define LDD_USB_ID_EP15_OUT 0x0Fu /*!< EP15 OUT component ID */ +#define LDD_USB_ID_EP15_IN 0x8Fu /*!< EP15 IN component ID */ +#define LDD_USB_ID_EP_MASK 0x8Fu /*!< EP15 IN component ID */ + +/* Token PID */ +#define LDD_USB_PID_OUT 0x01u /*!< OUT */ +#define LDD_USB_PID_IN 0x09u /*!< IN */ +#define LDD_USB_PID_SOF 0x05u /*!< SOF */ +#define LDD_USB_PID_SETUP 0x0Du /*!< SETUP */ +/* Data PID */ +#define LDD_USB_PID_DATA0 0x03u /*!< DATA0 */ +#define LDD_USB_PID_DATA1 0x0Bu /*!< DATA1 */ +#define LDD_USB_PID_DATA2 0x07u /*!< DATA2 */ +#define LDD_USB_PID_MDATA 0x0Fu /*!< MDATA */ +/* Handshake PID */ +#define LDD_USB_PID_ACK 0x02u /*!< ACK */ +#define LDD_USB_PID_NACK 0x0Au /*!< NACK */ +#define LDD_USB_PID_STALL 0x0Eu /*!< STALL */ +#define LDD_USB_PID_NYET 0x06u /*!< NYET */ +/* Special PID */ +#define LDD_USB_PID_PRE 0x0Cu /*!< PRE */ +#define LDD_USB_PID_ERR 0x0Cu /*!< ERR */ +#define LDD_USB_PID_SPLIT 0x08u /*!< SPLIT */ +#define LDD_USB_PID_PING 0x04u /*!< PING */ + +/* Data direction */ +#define LDD_USB_DIR_OUT 0x00u /*!< Recipient is Device */ +#define LDD_USB_DIR_IN 0x80u /*!< Recipient is Host */ +#define LDD_USB_DIR_MASK 0x80u /*!< Bit mask for data transfer direction */ + +/* Flags used in the TD.Head.Flags variable */ + +/* The following flag can be used to force zero-length termination(ZLT) of the transfer. + Note: ZLT can be set for all transfer during the initialization of the endpoint. +*/ +#define LDD_USB_DEVICE_TRANSFER_FLAG_ZLT 0x01u + +/* If the TRANSFER_FLAG_EXT_PARAM is defined all variables of the TD are used + and TD must NOT be freed until transfer is done or is cancelled + (TransferState != LDD_USB_TRANSFER_PENDING) + If not defined only the Head member of TD is used and TD can be freed after + Send/Recv() method returns. +*/ +#define LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM 0x02u + + +#define ERR_COMPONET_SPECIFIC 0x100u + +/* Device mode USB specific error codes */ +#define ERR_USB_DEVICE_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Device mode is disabled (by the user or by the clock configuration) */ +#define ERR_USB_DEVICE_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Device mode is disabled by the OTG driver */ +#define ERR_USB_DEVICE_VBUS_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< No VBUS is detected */ +#define ERR_USB_DEVICE_VBUS_ON (ERR_COMPONET_SPECIFIC + 0x03u) /*!< VBUS is detected */ +#define ERR_USB_DEVICE_ENABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is enabled */ +#define ERR_USB_DEVICE_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Device is suspended */ +#define ERR_USB_DEVICE_SUSPENDED_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Device is suspended and ready to generate resume signaling */ +#define ERR_USB_DEVICE_RESUME_PENDING (ERR_COMPONET_SPECIFIC + 0x07u) /*!< Device generates resume signaling */ + +/* Host mode USB specific error codes */ +#define ERR_USB_HOST_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Host mode is disabled (by the user or by the clock configuration) */ +#define ERR_USB_HOST_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Host mode is disabled by the OTG driver */ +#define ERR_USB_HOST_PORT_POWERED_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< Port is power off */ +#define ERR_USB_HOST_PORT_DISCONNECTED (ERR_COMPONET_SPECIFIC + 0x03u) /*!< Port is power on */ +#define ERR_USB_HOST_PORT_DISABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is connected to the port */ +#define ERR_USB_HOST_PORT_RESETING (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Port generates reset signaling */ +#define ERR_USB_HOST_PORT_RESET_RECOVERING (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Port waits 10ms for reset recovery */ +#define ERR_USB_HOST_PORT_ENABLED (ERR_COMPONET_SPECIFIC + 0x07u) /*!< PortDevice is connected, reset and ready to use */ +#define ERR_USB_HOST_PORT_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x08u) /*!< Port is suspended */ +#define ERR_USB_HOST_PORT_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x09u) /*!< Port can generate resume signaling */ +#define ERR_USB_HOST_PORT_RESUMING (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< Port generates resume signaling */ +#define ERR_USB_HOST_PORT_RESUME_RECOVERING (ERR_COMPONET_SPECIFIC + 0x0Bu) /*!< Port generates resume signaling */ + +/* OTG mode USB specific error codes */ +#define ERR_USB_OTG_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< OTG device is DISABLED state */ +#define ERR_USB_OTG_ENABLED_PENDING (ERR_COMPONET_SPECIFIC + 0x01u) /*!< OTG device is in ENABLED_PENDING state */ +#define ERR_USB_OTG_A_IDLE (ERR_COMPONET_SPECIFIC + 0x02u) /*!< OTG device is in A_IDLE state */ +#define ERR_USB_OTG_A_WAIT_VRISE (ERR_COMPONET_SPECIFIC + 0x03u) /*!< OTG device is in WAIT_VRISE state */ +#define ERR_USB_OTG_A_WAIT_VFALL (ERR_COMPONET_SPECIFIC + 0x05u) /*!< OTG device is in A_WAIT_VFALL state */ +#define ERR_USB_OTG_A_WAIT_BCON (ERR_COMPONET_SPECIFIC + 0x07u) /*!< OTG device is in A_WAIT_BCON state */ +#define ERR_USB_OTG_A_VBUS_ERROR (ERR_COMPONET_SPECIFIC + 0x09u) /*!< OTG device is in A_VBUS_ERROR state */ +#define ERR_USB_OTG_A_SUSPEND (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< OTG device is in A_SUSPEND state */ + +#define ERR_USB_OTG_B_IDLE (ERR_COMPONET_SPECIFIC + 0x0Cu) /*!< OTG device is in B_IDLE state */ +#define ERR_USB_OTG_B_SRP_INIT (ERR_COMPONET_SPECIFIC + 0x0Eu) /*!< OTG device is in B_SRP_INIT state */ +#define ERR_USB_OTG_B_WAIT_ACON (ERR_COMPONET_SPECIFIC + 0x0Fu) /*!< OTG device is in B_WAIT_ACON state */ + +#define ERR_USB_OTG_A_HOST (ERR_COMPONET_SPECIFIC + 0x10u) /*!< OTG device is in A_HOST state */ +#define ERR_USB_OTG_A_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x11u) /*!< OTG device is in A_PERIPHERAL state */ +#define ERR_USB_OTG_B_HOST (ERR_COMPONET_SPECIFIC + 0x12u) /*!< OTG device is in B_HOST state */ +#define ERR_USB_OTG_B_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x13u) /*!< OTG device is in B_PERIPHERAL state */ + +/*! Device speed symbolic names */ +typedef enum { + LDD_USB_LOW_SPEED = 0x00u, /*!< Low-speed - 6 Mb/s mode */ + LDD_USB_FULL_SPEED = 0x01u, /*!< Full-speed - 12 Mb/s mode */ + LDD_USB_HIGH_SPEED = 0x02u, /*!< High-speed - 480 Mb/s mode */ + LDD_USB_SPEED_UNKNOWN = 0xFFu /*!< Unkown speed mode */ +} LDD_USB_TBusSpeed; + +/*! Transfer type symbolic names */ +typedef enum { + LDD_USB_CONTROL = 0x00u, /*!< Conrol transfer type */ + LDD_USB_ISOCHRONOUS = 0x01u, /*!< Isochronous transfer type */ + LDD_USB_BULK = 0x02u, /*!< Bulk transfer type */ + LDD_USB_INTERRUPT = 0x03u /*!< Interrupt transfer type */ +} LDD_USB_TTransferType; + +/*! Transfer state symbolic names */ +typedef enum { + LDD_USB_TRANSFER_NONE = 0x00u, /*!< Default valeu for new TD */ + LDD_USB_TRANSFER_DONE = 0x01u, /*!< Transfer done */ + LDD_USB_TRANSFER_ERROR_CANCELLED = 0x02u, /*!< Transfer cancelled by the user */ + LDD_USB_TRANSFER_ERROR_STALLED = 0x03u, /*!< Transfer stalled */ + LDD_USB_TRANSFER_ERROR_BUS_TIMEOUT = 0x04u, /*!< Bus timeute detected */ + LDD_USB_TRANSFER_ERROR_DATA = 0x05u, /*!< Data error deteceted */ + LDD_USB_TRANSFER_ERROR_PID = 0x06u, /*!< PID error deteceted */ + LDD_USB_TRANSFER_ERROR_EOF = 0x07u, /*!< EOF error deteceted */ + LDD_USB_TRANSFER_ERROR_CRC16 = 0x08u, /*!< CRC16 error deteceted */ + LDD_USB_TRANSFER_ERROR_DFN8 = 0x09u, /*!< DFN8 error deteceted */ + LDD_USB_TRANSFER_ERROR_DMA = 0x0Au, /*!< DMA error deteceted */ + LDD_USB_TRANSFER_ERROR_BTS = 0x0Bu, /*!< BTS error deteceted */ + LDD_USB_TRANSFER_ERROR = 0x0Fu, /*!< Transfer error deteceted */ + LDD_USB_TRANSFER_QUEUED = 0x10u, /*!< Transfer queued */ + LDD_USB_TRANSFER_PENDING = 0x30u /*!< Transfer in proggress */ +} LDD_USB_TTransferState; + +/*! Setup data packet structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TSDP_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request code */ + uint16 wValue; /*!< Word-sized field that varies according to request */ + uint16 wIndex; /*!< Word-sized field that varies according to request, typically used to pass an index or offset */ + uint16 wLength; /*!< Number of bytes to transfer if there is a data stage */ +} LDD_USB_TSDP; + +/*! Endpoint descriptor structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TEpDescriptor_Struct { + uint8 bLength; /*!< Size of this descriptor in bytes */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint8 bEndpointAddress; /*!< Endpoint address */ + uint8 bmAttributes; /*!< Endpoint attributes */ + uint16 wMaxPacketSize; /*!< Maximum packet size the endpoint is capable of sending or receiving */ + uint8 bInterval; /*!< Interval for polling endpoint for data transfers */ +} LDD_USB_TEpDescriptor; + +/*! Standard device descriptor structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TDevDescriptor_Struct { + uint8 bLength; /*!< Size of this descriptor in bytes */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint16 bcdUSB; /*!< USB specification release number in binary-coded Decimal */ + uint8 bDeviceClass; /*!< Class code (assigned by the USB-IF) */ + uint8 bDeviceSubClass; /*!< Subclass code (assigned by the USB-IF) */ + uint8 bDeviceProtocol; /*!< Protocol code (assigned by the USB-IF) */ + uint8 bMaxPacketSize0; /*!< Maximum packet size for endpoint zero */ + uint16 idVendor; /*!< Vendor ID (assigned by the USB-IF) */ + uint16 idProduct; /*!< Product ID (assigned by the manufacturer) */ + uint16 bcdDevice; /*!< Device release number in binary-coded decimal */ + uint8 iManufacturer; /*!< Index of string descriptor describing manufacturer */ + uint8 iProduct; /*!< Index of string descriptor describing product */ + uint8 iSerialNumber; /*!< Index of string descriptor describing the devices serial number */ + uint8 bNumConfigurations; /*!< Number of possible configurations */ +} LDD_USB_TDevDescriptor; + + +/*! Device transfer descriptor structure forward declaration */ +struct LDD_USB_Device_TTD_Struct; + +/*! Device transfer done callback prototype */ +typedef void (LDD_USB_Device_TTransferDoneCalback)(LDD_TDeviceData *DevDataPtr, struct LDD_USB_Device_TTD_Struct *TrParamPtr); + +/*! Device transfer descriptor structure - head part */ +typedef struct LDD_USB_Device_TTD_Head_Struct { + uint8 EpNum; /*!< Endpoint number */ + LDD_TData *BufferPtr; /*!< Buffer address */ + uint16 BufferSize; /*!< Buffer size */ + uint8 Flags; /*!< Transfer flags - see constants definition */ +} LDD_USB_Device_TTD_Head; + +/*! Device transfer descriptor structure */ +typedef struct LDD_USB_Device_TTD_Struct { + /* Requierd variables */ + LDD_USB_Device_TTD_Head Head; /*!< Td head data, not changed by the driver */ + /* Optional items - the following items are used */ + /* only if Head.Flags & LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM != 0 */ + LDD_USB_TTransferState TransferState; /*!< Transfer state. Set by the driver */ + uint16 TransmittedDataSize; /*!< Transmitted data size. Set by the driver */ + LDD_USB_Device_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */ + uint8 *ParamPtr; /*!< User parameter. Not changed by the driver */ +} LDD_USB_Device_TTD; + +/*! USB device states symbolic names */ +typedef enum { + LDD_USB_DEVICE_DISABLED = ERR_USB_DEVICE_DISABLED, /*!< Device mode is disabled (by the user or by the clock configuration) */ + LDD_USB_DEVICE_DISABLED_BY_OTG = ERR_USB_DEVICE_DISABLED_BY_OTG, /*!< Device mode is disabled by the OTG driver */ + LDD_USB_DEVICE_VBUS_OFF = ERR_USB_DEVICE_VBUS_OFF, /*!< No VBUS is detected */ + LDD_USB_DEVICE_VBUS_ON = ERR_USB_DEVICE_VBUS_ON, /*!< VBUS is detected */ + LDD_USB_DEVICE_ENABLED = ERR_USB_DEVICE_ENABLED, /*!< Device is enabled - reset by the host */ + LDD_USB_DEVICE_SUSPENDED = ERR_USB_DEVICE_SUSPENDED, /*!< Device is suspended - Bus is idle more then 3 ms */ + LDD_USB_DEVICE_SUSPENDED_RESUME_READY = ERR_USB_DEVICE_SUSPENDED_RESUME_READY, /*!< Device can generate resume signaling - Bus is idle more then 5 ms. */ + LDD_USB_DEVICE_RESUME_PENDING = ERR_USB_DEVICE_RESUME_PENDING /*!< Device generates resume signaling */ +} LDD_USB_Device_TState; + +/*! USB host mode states symbolic names */ +typedef enum { + LDD_USB_HOST_DISABLED = ERR_USB_HOST_DISABLED, /*!< Host mode is disabled (by the user or by the clock configuration) */ + LDD_USB_HOST_DISABLED_BY_OTG = ERR_USB_HOST_DISABLED_BY_OTG, /*!< Host mode is disabled by the OTG driver */ + LDD_USB_HOST_PORT_POWERED_OFF = ERR_USB_HOST_PORT_POWERED_OFF, /*!< Port is powered-off */ + LDD_USB_HOST_PORT_DISCONNECTED = ERR_USB_HOST_PORT_DISCONNECTED, /*!< No device is connected */ + LDD_USB_HOST_PORT_DISABLED = ERR_USB_HOST_PORT_DISABLED, /*!< Device is connected to the port */ + LDD_USB_HOST_PORT_RESETING = ERR_USB_HOST_PORT_RESETING, /*!< Port generates reset signaling */ + LDD_USB_HOST_PORT_RESET_RECOVERING = ERR_USB_HOST_PORT_RESET_RECOVERING, /*!< Port waits 10 ms for reset recovery */ + LDD_USB_HOST_PORT_ENABLED = ERR_USB_HOST_PORT_ENABLED, /*!< Device is connected, reset and ready to use */ + LDD_USB_HOST_PORT_SUSPENDED = ERR_USB_HOST_PORT_SUSPENDED, /*!< Port is suspended */ + LDD_USB_HOST_PORT_RESUME_READY = ERR_USB_HOST_PORT_RESUME_READY, /*!< Port is ready to generate resume signaling */ + LDD_USB_HOST_PORT_RESUMING = ERR_USB_HOST_PORT_RESUMING, /*!< Port generates resume signaling */ + LDD_USB_HOST_PORT_RESUME_RECOVERING = ERR_USB_HOST_PORT_RESUME_RECOVERING /*!< Port waits 10 ms for resume recovery */ +} LDD_USB_Host_TState; + +/*! USB otg mode states symbolic names */ +typedef enum { + LDD_USB_OTG_DISABLED = ERR_USB_OTG_DISABLED, /*!< OTG device is in DISABLED state */ + LDD_USB_OTG_ENABLED = ERR_USB_OTG_ENABLED_PENDING, /*!< OTG device is in ENABLED_PENDING state */ + LDD_USB_OTG_A_IDLE = ERR_USB_OTG_A_IDLE, /*!< OTG device is in A_IDLE state */ + LDD_USB_OTG_A_WAIT_VRISE = ERR_USB_OTG_A_WAIT_VRISE, /*!< OTG device is in A_WAIT_VRISE state */ + LDD_USB_OTG_A_WAIT_VFALL = ERR_USB_OTG_A_WAIT_VFALL, /*!< OTG device is in A_WAIT_VFALL state */ + LDD_USB_OTG_A_WAIT_BCON = ERR_USB_OTG_A_WAIT_BCON, /*!< OTG device is in A_WAIT_BCON state */ + LDD_USB_OTG_A_VBUS_ERROR = ERR_USB_OTG_A_VBUS_ERROR, /*!< OTG device is in A_VBUS_ERROR state */ + LDD_USB_OTG_A_SUSPEND = ERR_USB_OTG_A_SUSPEND, /*!< OTG device is in A_SUSPEND state */ + LDD_USB_OTG_B_IDLE = ERR_USB_OTG_B_IDLE, /*!< OTG device is in B_IDLE state */ + LDD_USB_OTG_B_SRP_INIT = ERR_USB_OTG_B_SRP_INIT, /*!< OTG device is in B_SRP_INIT state */ + LDD_USB_OTG_B_WAIT_ACON = ERR_USB_OTG_B_WAIT_ACON, /*!< OTG device is in B_WAIT_ACON state */ + LDD_USB_OTG_A_HOST = ERR_USB_OTG_A_HOST, /*!< OTG device is in A_HOST state */ + LDD_USB_OTG_A_PERIPHERAL = ERR_USB_OTG_A_PERIPHERAL, /*!< OTG device is in A_PERIPHERAL state */ + LDD_USB_OTG_B_HOST = ERR_USB_OTG_B_HOST, /*!< OTG device is in B_HOST state */ + LDD_USB_OTG_B_PERIPHERAL = ERR_USB_OTG_B_PERIPHERAL /*!< OTG device is in B_PERIPHERAL state */ +} LDD_USB_Otg_TState; + +/*! USB Otg commands symbolic names */ +typedef enum { + LDD_USB_OTG_CMD_SET_A_BUS_REQUEST, /*!< A-device application wants to use the bus */ + LDD_USB_OTG_CMD_CLR_A_BUS_REQUEST, /*!< A-device application doesn't want to use the bus */ + LDD_USB_OTG_CMD_SET_B_BUS_REQUEST, /*!< B-device application wants to use the bus */ + LDD_USB_OTG_CMD_CLR_B_BUS_REQUEST, /*!< B-device application doesn't want to use the bus */ + LDD_USB_OTG_CMD_SET_A_BUS_DROP, /*!< A-device application needs to power down the bus */ + LDD_USB_OTG_CMD_CLR_A_BUS_DROP, /*!< A-device application doesn't need to power down the bus */ + LDD_USB_OTG_CMD_SET_A_SUSPEND_REQUEST, /*!< A-device application wants to suspend the bus */ + LDD_USB_OTG_CMD_CLR_A_SUSPEND_REQUEST, /*!< A-device application doesn't want to suspend the bus */ + LDD_USB_OTG_CMD_SET_A_SET_B_HNP_EN_REQUEST, /*!< A-device sets HNP enabled feature on B-device */ + LDD_USB_OTG_CMD_CLR_A_SET_B_HNP_EN_REQUEST, /*!< A-device clears HNP enabled feature on B-device */ + LDD_USB_OTG_CMD_SET_B_HNP_EN_REQUEST, /*!< Enable B-device HNP */ + LDD_USB_OTG_CMD_CLR_B_HNP_EN_REQUEST /*!< Disable B-device HNP */ +} LDD_USB_Otg_TCmd; + +/*! USB host port control commands symbolic names */ +typedef enum { + LDD_USB_HOST_PORT_CMD_POWER_ON, /*!< Power-on the bus */ + LDD_USB_HOST_PORT_CMD_POWER_OFF, /*!< Power-off the bus */ + LDD_USB_HOST_PORT_CMD_RESET, /*!< Perform the bus reset signaling and call event after the reset recovery interval elapse */ + LDD_USB_HOST_PORT_CMD_RESUME, /*!< Perform the bus resume signaling and call event after the resume recovery interval elapse */ + LDD_USB_HOST_PORT_CMD_SUSPEND, /*!< Suspend the bus and transceiver */ + LDD_USB_HOST_PORT_CMD_DISABLE /*!< Disable the port */ +} LDD_USB_Host_TPortControlCmd; + +/*! USB host handle prototypes */ +typedef void LDD_USB_Host_TPipeHandle; /*!< Pipe handle prototype */ +typedef void LDD_USB_Host_TTransferHandle; /*!< Transfer handle prototype */ + +/*! USB host pipe descriptor structure */ +typedef struct LDD_USB_Host_TPipeDescr_Struct { + uint8 DevAddress; /*!< Device address */ + LDD_USB_TBusSpeed DevSpeed; /*!< Device speed */ + uint8 EpNumber; /*!< EP number */ + uint8 EpDir; /*!< EP direction */ + LDD_USB_TTransferType TransferType; /*!< EP Transfer type */ + uint16 MaxPacketSize; /*!< EP max. packet size */ + uint8 TrPerUFrame; /*!< Transaction pre microframe */ + uint32 Interval; /*!< Interval for polling endpoint for data transfers */ + uint32 NAKCount; /*!< NAK count */ + uint8 Flags; /*!< 1 = ZLT */ +} LDD_USB_Host_TPipeDescr; + +/*! USB host transfer done callback prototype */ +typedef void (LDD_USB_Host_TTransferDoneCalback)( + LDD_TDeviceData *DevDataPtr, /*!< User value passed as parameter of the Init() method */ + LDD_TData *BufferPtr, /*!< Buffer address */ + uint16 BufferSize, /*!< Transferred data size */ + uint8 *ParamPtr, /*!< User value passed in Send()/Recv() method */ + LDD_USB_TTransferState Status /*!< Transfer status */ +); + +/*! USB host transfer descriptor structure */ +typedef struct LDD_USB_Host_TTD_Struct { + LDD_TData *BufferPtr; /*!< Buffer address */ + uint16 BufferSize; /*!< Buffer size */ + uint8 Flags; /*!< Transfer flags */ + LDD_USB_Host_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */ + uint8 *ParamPtr; /*!< User parameter. Not changed by the driver */ + LDD_USB_TSDP *SDPPrt; /*!< Setup data buffer pointer */ +} LDD_USB_Host_TTD; + +/*! Following USB constants and types are for test purpose only */ + +/* Request types */ +#define LDD_USB_REQ_TYPE_STANDARD 0x00u /*!< Standard request */ +#define LDD_USB_REQ_TYPE_CLASS 0x20u /*!< Class request */ +#define LDD_USB_REQ_TYPE_VENDOR 0x40u /*!< Vendor request */ +#define LDD_USB_REQ_TYPE_MASK 0x60u /*!< Bit mask for request type (bmRequestType) */ + +/* Request recepient */ +#define LDD_USB_REQ_RECP_DEVICE 0x00u /*!< Recipient = Device */ +#define LDD_USB_REQ_RECP_INTERFACE 0x01u /*!< Recipient = Interface */ +#define LDD_USB_REQ_RECP_ENDPOINT 0x02u /*!< Recipient = Endpoint */ +#define LDD_USB_REQ_RECP_OTHER 0x03u /*!< Recipient = Other */ +#define LDD_USB_REQ_RECP_MASK 0x03u /*!< Bit mask for recipient */ + +/* Standard request codes (bRequest) */ +#define LDD_USB_REQ_GET_STATUS 0x00u /*!< GET_STATUS request code */ +#define LDD_USB_REQ_CLEAR_FEATURE 0x01u /*!< CLEAR_FEATURE request code */ +#define LDD_USB_REQ_SET_FEATURE 0x03u /*!< SET_FEATURE request code */ +#define LDD_USB_REQ_GET_STATE 0x04u /*!< GET_STATE request code (for Hub Class only)*/ +#define LDD_USB_REQ_SET_ADDRESS 0x05u /*!< SET_ADDRESS request code */ +#define LDD_USB_REQ_GET_DESCRIPTOR 0x06u /*!< GET_DESCRIPTOR request code */ +#define LDD_USB_REQ_SET_DESCRIPTOR 0x07u /*!< SET_DESCRIPTOR request code, this request is not supported */ +#define LDD_USB_REQ_GET_CONFIGURATION 0x08u /*!< GET_CONFIGURATION request code */ +#define LDD_USB_REQ_SET_CONFIGURATION 0x09u /*!< SET_CONFIGURATION request code */ +#define LDD_USB_REQ_GET_INTERFACE 0x0Au /*!< GET_INTERFACE request code */ +#define LDD_USB_REQ_SET_INTERFACE 0x0Bu /*!< SET_INTERFACE request code */ +#define LDD_USB_REQ_SYNCH_FRAME 0x0Cu /*!< SYNCH_FRAME request code */ + +/* Standard request words for device (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_DEV_STATUS 0x0080u /*!< GET_DEVICE_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_DEV_FEATURE 0x0100u /*!< CLEAR_DEVICE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_DEV_FEATURE 0x0300u /*!< SET_DEVICE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_ADDRESS 0x0500u /*!< SET_DEVICE_ADDRESS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_DESCRIPTOR 0x0680u /*!< GET_DESCRIPTOR bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_DESCRIPTOR 0x0700u /*!< SET_DESCRIPTOR bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_CONFIGURATION 0x0880u /*!< GET_DEVICE_CONFIGURATION bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_CONFIGURATION 0x0900u /*!< SET_DEVICE_CONFIGURATION bmRequestType and bRequest word */ + +/* Standard request words for interface (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_INT_STATUS 0x0081u /*!< GET_INTERFACE_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_INT_FEATURE 0x0101u /*!< CLEAR_INTERFACE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_INT_FEATURE 0x0301u /*!< SET_INTERFACE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_INTERFACE 0x0A81u /*!< GET_DEVICE_INTERFACE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_INTERFACE 0x0B01u /*!< SET_DEVICE_INTERFACE bmRequestType and bRequest word */ + +/* Standard request words for endpoint (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_EP_STATUS 0x0082u /*!< GET_ENDPOINT_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_EP_FEATURE 0x0102u /*!< CLEAR_ENDPOINT_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_EP_FEATURE 0x0302u /*!< ENDPOINT_ bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SYNCH_FRAME 0x0C12u /*!< SYNCH_DEVICE_FRAME bmRequestType and bRequest code */ + +#define LDD_USB_STATUS_DEVICE_SELF_POWERED_MASK 0x01u +#define LDD_USB_STATUS_DEVICE_REMOTE_WAKEUP_MASK 0x02u + +/* Standard descriptors */ +#define LDD_USB_DT_DEVICE 0x01u /*!< Device descriptor */ +#define LDD_USB_DT_CONFIGURATION 0x02u /*!< Configuration descriptor */ +#define LDD_USB_DT_STRING 0x03u /*!< String descriptor */ +#define LDD_USB_DT_INTERFACE 0x04u /*!< Interface descriptor */ +#define LDD_USB_DT_ENDPOINT 0x05u /*!< Endpoint descriptor */ +#define LDD_USB_DT_DEVICE_QUALIFIER 0x06u /*!< Device qualifier descriptor */ +#define LDD_USB_DT_OTHER_SPEED_CONFIGURATION 0x07u /*!< Other speed configuration descriptor */ +#define LDD_USB_DT_INTERFACE_POWER 0x08u /*!< Interface-level power management descriptor */ +#define LDD_USB_DT_OTG 0x09u /*!< OTG descriptor */ +#define LDD_USB_DT_DEBUG 0x0Au /*!< Debug descriptor */ +#define LDD_USB_DT_INTERFACE_ASSOCIATION 0x0Bu /*!< Interface association descriptor */ + +/* Standard feature selectors */ +#define LDD_USB_FEATURE_EP_HALT 0x00u /*!< Endpoint HALT feature selector */ +#define LDD_USB_FEATURE_DEV_REMOTE_WAKEUP 0x01u /*!< Remote Wake-up feature selector */ +#define LDD_USB_FEATURE_DEV_TEST_MODE 0x02u /*!< Test mode feature selector */ + +/*! Get decriptor request structure */ +typedef struct LDD_USB_TGetDecriptorRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 bDescriptorIndex; /*!< Descriptor index */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint16 wLanguageID; /*!< Language ID */ + uint16 wLength; /*!< Requested data size */ +} LDD_USB_TGetDecriptorRequest; + +/*! Get endpoint status request structure */ +typedef struct LDD_USB_TEndpointStatusRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wValue; /*!< Not used, should be set to zero */ + uint8 bEndpoint; /*!< Endpoint address */ + uint8 bIndexHigh; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Reqested data size, should be set to 2 */ +} LDD_USB_TEndpointStatusRequest; + +/*! Clear/Set endpoint feature request structure */ +typedef struct LDD_USB_TEndpointFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint8 bEndpoint; /*!< Endpoint address */ + uint8 bIndexHigh; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TEndpointFeatureRequest; + +/*! Clear/Set interface request structure */ +typedef struct LDD_USB_TInterfaceFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TInterfaceFeatureRequest; + +/*! Clear/Set device request structure */ +typedef struct LDD_USB_TDeviceFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TDeviceFeatureRequest; + +/*! Get interface request structure */ +typedef struct LDD_USB_TGetInterfaceRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wWalue; /*!< Not used, should be zero */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Reqested data size, should be set to 1 */ +} LDD_USB_TGetInterfaceRequest; + +/*! Set interface request structure */ +typedef struct LDD_USB_TSetInterfaceRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wAltSet; /*!< Alternate setting */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetInterfaceRequest; + +/*! Set address request structure */ +typedef struct LDD_USB_TSetAddressRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 DeviceAddress; /*!< Device address */ + uint8 bValueHigh; /*!< Not used, should be set to zero */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetAddressRequest; + +/*! Set address request structure */ +typedef struct LDD_USB_TSetConfigRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 bValueHigh; /*!< Not used, should be set to zero */ + uint8 ConfigNumber; /*!< Configuration number */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetConfigRequest; + +/* +** =================================================================== +** DAC device types and constants +** =================================================================== +*/ +#define LDD_DAC_OUTPUT_PIN_0 0x01u /*!< DAC output pin 0 mask */ + +#define LDD_DAC_ON_BUFFER_END 0x01U /*!< OnBufferEnd event mask */ +#define LDD_DAC_ON_BUFFER_START 0x02U /*!< OnBufferStart event mask */ +#define LDD_DAC_ON_BUFFER_WATERMARK 0x04U /*!< OnBufferWatermark event mask */ +#define LDD_DAC_ON_COMPLETE LDD_DMA_ON_COMPLETE /*!< OnComplete event mask */ +#define LDD_DAC_ON_ERROR LDD_DMA_ON_ERROR /*!< OnError event mask */ + +/*! Type specifying the DAC buffer work mode */ +typedef enum { + LDD_DAC_BUFFER_NORMAL_MODE = 0x00U, /*!< Normal (cyclic) mode */ + LDD_DAC_BUFFER_SWING_MODE = 0x01U, /*!< Swing mode */ + LDD_DAC_BUFFER_SCAN_MODE = 0x02U /*!< One-time scan mode */ +} LDD_DAC_TBufferMode; + +/*! Type specifying the DAC buffer watermark levels */ +typedef enum { + LDD_DAC_BUFFER_WATERMARK_L1 = 0x00U, + LDD_DAC_BUFFER_WATERMARK_L2 = 0x01U, + LDD_DAC_BUFFER_WATERMARK_L3 = 0x02U, + LDD_DAC_BUFFER_WATERMARK_L4 = 0x03U +} LDD_DAC_TBufferWatermark; + +#define LDD_DAC_DMA_ERROR 0x01u /*!< DMA error mask */ + +typedef void* LDD_DAC_TDataPtr; /*!< Type specifying the pointer to the DAC data variable */ +typedef uint32 LDD_DAC_TData; /*!< The DAC data variable type */ +typedef uint32 LDD_DAC_TErrorMask; /*!< Error mask */ +typedef uint32 LDD_DAC_TArrayLength; /*!< Array length type */ + +/* +** =================================================================== +** FLASH device types and constants +** =================================================================== +*/ +#define LDD_FLASH_ON_OPERATION_COMPLETE 0x02u /*!< OnOperationComplete event mask */ +#define LDD_FLASH_ON_ERROR 0x04u /*!< OnError event mask */ + +#define LDD_FLASH_READ_COLLISION_ERROR 0x40u /*!< Read collision error flag's mask */ +#define LDD_FLASH_ACCESS_ERROR 0x20u /*!< Access error flag's mask */ +#define LDD_FLASH_PROTECTION_VIOLATION 0x10u /*!< Protection violation error flag's mask */ +#define LDD_FLASH_ERASE_VERIFICATION_ERROR 0x08u /*!< Erase verification error flag's mask */ +#define LDD_FLASH_MULTIPLE_WRITE_ERROR 0x04u /*!< Multiple write to one flash memory location error flag's mask */ + +/*! Type specifying HW commands for a flash device */ +typedef enum { + LDD_FLASH_READ_1S_BLOCK = 0x00u, /*!< Checks if an entire program flash or data flash logical block has been erased to the specified margin level */ + LDD_FLASH_READ_1S_SECTION = 0x01u, /*!< Checks if a section of program flash or data flash memory is erased to the specified read margin level */ + LDD_FLASH_WRITE_BYTE = 0x04u, /*!< Program byte */ + LDD_FLASH_WRITE_WORD = 0x05u, /*!< Program word */ + LDD_FLASH_WRITE_LONG_WORD = 0x06u, /*!< Program long word */ + LDD_FLASH_WRITE_PHRASE = 0x07u, /*!< Program phrase */ + LDD_FLASH_ERASE_FLASH_BLOCK = 0x08u, /*!< Erase flash memory block */ + LDD_FLASH_ERASE_SECTOR = 0x09u, /*!< Erase sector */ + LDD_FLASH_ERASE_ALL_FLASH_BLOCKS = 0x44u /*!< Erase all flash memory blocks */ +} LDD_FLASH_TCommand; + +/*! Type specifying possible FLASH component operation types */ +typedef enum { + LDD_FLASH_NO_OPERATION, /*!< No operation - initial state */ + LDD_FLASH_READ, /*!< Read operation */ + LDD_FLASH_WRITE, /*!< Write operation */ + LDD_FLASH_ERASE, /*!< Erase operation */ + LDD_FLASH_ERASE_BLOCK, /*!< Erase block operation */ + LDD_FLASH_VERIFY_ERASED_BLOCK /*!< Verify erased block operation */ +} LDD_FLASH_TOperationType; + +/*! Type specifying possible FLASH component operation states */ +typedef enum { + LDD_FLASH_FAILED = 0x00u, /*!< Operation has failed */ + LDD_FLASH_STOP = 0x01u, /*!< The operation has been stopped */ + LDD_FLASH_IDLE = 0x02u, /*!< No operation in progress */ + LDD_FLASH_STOP_REQ = 0x03u, /*!< The operation is in the STOP request mode */ + LDD_FLASH_START = 0x04u, /*!< Start of the operation, no operation steps have been done yet */ + LDD_FLASH_RUNNING = 0x05u /*!< Operation is in progress */ +} LDD_FLASH_TOperationStatus; + +typedef uint8 LDD_FLASH_TErrorFlags; /*!< Type specifying FLASH component's error flags bit field */ + +typedef uint32 LDD_FLASH_TAddress; /*!< Type specifying the Address parameter used by the FLASH component's methods */ + +typedef uint32 LDD_FLASH_TDataSize; /*!< Type specifying the Size parameter used by the FLASH component's methods */ + +typedef uint16 LDD_FLASH_TErasableUnitSize; /*!< Type specifying the Size output parameter of the GetErasableUnitSize method (pointer to a variable of this type is passed to the method) */ + +/*! Type specifying the FLASH component's rrror status information */ +typedef struct { + LDD_FLASH_TOperationType CurrentOperation; /*!< Current operation */ + LDD_FLASH_TCommand CurrentCommand; /*!< Last flash controller command */ + LDD_FLASH_TErrorFlags CurrentErrorFlags; /*!< Bitfield with error flags. See FLASH2.h for details */ + LDD_FLASH_TAddress CurrentAddress; /*!< Address of the flash memory location the error status is related to */ + LDD_TData *CurrentDataPtr; /*!< Pointer to current input data the error status is related to */ + LDD_FLASH_TDataSize CurrentDataSize; /*!< Size of the current input data to be programmed or erased in bytes */ +} LDD_FLASH_TErrorStatus; + +/* +** =================================================================== +** HSCMP device types and constants +** =================================================================== +*/ + +#define LDD_ANALOGCOMP_ON_COMPARE 0x01u /*!< OnCompare event mask */ + +/* Positive input pin masks */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_0_MASK 0x01U /*!< Mask for positive input pin 0 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_1_MASK 0x02U /*!< Mask for positive input pin 1 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_2_MASK 0x04U /*!< Mask for positive input pin 2 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_3_MASK 0x08U /*!< Mask for positive input pin 3 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_4_MASK 0x10U /*!< Mask for positive input pin 4 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_5_MASK 0x20U /*!< Mask for positive input pin 5 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_6_MASK 0x40U /*!< Mask for positive input pin 6 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_7_MASK 0x80U /*!< Mask for positive input pin 7 */ + +/* Negative input pin masks */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_0_MASK 0x0100U /*!< Mask for negative input pin 0 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_1_MASK 0x0200U /*!< Mask for negative input pin 1 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_2_MASK 0x0400U /*!< Mask for negative input pin 2 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_3_MASK 0x0800U /*!< Mask for negative input pin 3 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_4_MASK 0x1000U /*!< Mask for negative input pin 4 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_5_MASK 0x2000U /*!< Mask for negative input pin 5 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_6_MASK 0x4000U /*!< Mask for negative input pin 6 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_7_MASK 0x8000U /*!< Mask for negative input pin 7 */ + +/* Output pin masks */ +#define LDD_ANALOGCOMP_OUTPUT_PIN_MASK 0x00010000U /*!< Mask for output pin */ + +/* Window Sample pin masks */ +#define LDD_ANALOGCOMP_WINDOWSAMPLE_PIN_MASK 0x00020000UL + +/*! Type specifying comparator input number */ +typedef enum { + LDD_ANALOGCOMP_INPUT_0 = 0x00U, /*!< Analog input 0 selected */ + LDD_ANALOGCOMP_INPUT_1 = 0x01U, /*!< Analog input 1 selected */ + LDD_ANALOGCOMP_INPUT_2 = 0x02U, /*!< Analog input 2 selected */ + LDD_ANALOGCOMP_INPUT_3 = 0x03U, /*!< Analog input 3 selected */ + LDD_ANALOGCOMP_INPUT_4 = 0x04U, /*!< Analog input 4 selected */ + LDD_ANALOGCOMP_INPUT_5 = 0x05U, /*!< Analog input 5 selected */ + LDD_ANALOGCOMP_INPUT_6 = 0x06U, /*!< Analog input 6 selected */ + LDD_ANALOGCOMP_INPUT_7 = 0x07U, /*!< Analog input 7 selected */ + LDD_ANALOGCOMP_INPUT_DISABLED = 0x08U /*!< Analog input disabled */ +} LDD_AnalogComp_TComparatorInput; + +/*! Type specifying current comparator output status */ +typedef enum { + LDD_ANALOGCOMP_NO_EDGE = 0x00U, /*!< No edge detected on output */ + LDD_ANALOGCOMP_FALLING_EDGE = 0x02U, /*!< Falling edge detected on output */ + LDD_ANALOGCOMP_RISING_EDGE = 0x04U, /*!< Rising edge detected on output */ + LDD_ANALOGCOMP_BOTH_EDGES = 0x06U /*!< Both edges detected on output */ +} LDD_AnalogComp_TCompareStatus; + +/*! Type specifying requested comparator mode */ +typedef enum { + LDD_ANALOGCOMP_RISING_EDGE_MODE = 0x10U, /*!< Rising edge detection */ + LDD_ANALOGCOMP_FALLING_EDGE_MODE = 0x08U, /*!< Falling edge detection */ + LDD_ANALOGCOMP_BOTH_EDGES_MODE = 0x18U /*!< Both edges detection */ +} LDD_AnalogComp_TComparatorMode; + +typedef uint8 LDD_AnalogComp_TOutputValue; /*!< Type specifying comparator output value */ + +/* +** =================================================================== +** SDHC component types and constants +** =================================================================== +*/ + +#define LDD_SDHC_CARD_DATA_WIDTH_1_BIT 0x01u /*!< Card supports 1 bit data bus */ +#define LDD_SDHC_CARD_DATA_WIDTH_4_BIT 0x02u /*!< Card supports 4 bit data bus */ +#define LDD_SDHC_CARD_DATA_WIDTH_8_BIT 0x04u /*!< Card supports 8 bit data bus */ +#define LDD_SDHC_CARD_BLOCK_READ 0x01u /*!< Card supports block reading */ +#define LDD_SDHC_CARD_BLOCK_WRITE 0x04u /*!< Card supports block writing */ +#define LDD_SDHC_CARD_ERASE 0x08u /*!< Card supports block erasion */ +#define LDD_SDHC_CARD_WRITE_PROTECTION 0x10u /*!< Card supports write protection */ +#define LDD_SDHC_CARD_IO 0x80u /*!< Card supports IO */ + +#define LDD_SDHC_CLK_PIN 0x01u /*!< SD clock pin mask */ +#define LDD_SDHC_CMD_PIN 0x02u /*!< SD command line pin mask */ +#define LDD_SDHC_DAT0_PIN 0x04u /*!< SD data line 0 pin mask */ +#define LDD_SDHC_DAT1_PIN 0x08u /*!< SD data line 1 pin mask */ +#define LDD_SDHC_DAT2_PIN 0x10u /*!< SD data line 2 pin mask */ +#define LDD_SDHC_DAT3_PIN 0x20u /*!< SD data line 3 pin mask */ +#define LDD_SDHC_DAT4_PIN 0x40u /*!< SD data line 4 pin mask */ +#define LDD_SDHC_DAT5_PIN 0x80u /*!< SD data line 5 pin mask */ +#define LDD_SDHC_DAT6_PIN 0x0100u /*!< SD data line 6 pin mask */ +#define LDD_SDHC_DAT7_PIN 0x0200u /*!< SD data line 7 pin mask */ +#define LDD_SDHC_CD_PIN 0x0400u /*!< SD card detection pin mask */ +#define LDD_SDHC_WP_PIN 0x0800u /*!< SD write protection pin mask */ +#define LDD_SDHC_LCTL_PIN 0x1000u /*!< SD LED control pin mask */ +#define LDD_SDHC_VS_PIN 0x2000u /*!< SD voltage control pin mask */ + +#define LDD_SDHC_ON_CARD_INSERTED 0x01u /*!< OnCardInserted event mask */ +#define LDD_SDHC_ON_CARD_REMOVED 0x02u /*!< OnCardRemoved event mask */ +#define LDD_SDHC_ON_FINISHED 0x04u /*!< OnFinished event mask */ + +/*! Card types */ +typedef enum { + LDD_SDHC_SD, /*!< Secure Digital memory card */ + LDD_SDHC_SDIO, /*!< Secure Digital IO card */ + LDD_SDHC_SDCOMBO, /*!< Combined Secure Digital memory and IO card */ + LDD_SDHC_MMC, /*!< MultiMediaCard memory card */ + LDD_SDHC_CE_ATA /*!< Consumer Electronics ATA card */ +} LDD_SDHC_TCardType; + +/*! Card access properties */ +typedef struct { + uint16 MaxBlockLength; /*!< Max. transferable block length */ + bool MisalignBlock; /*!< Indicates if the data block can be spread over more than one physical block of the memory device */ + bool PartialBlock; /*!< Indicates whether partial block sizes can be used in block access */ +} LDD_SDHC_TCardAccess; + +/*! Card erasion properties */ +typedef struct { + uint16 SectorSize; /*!< The size of an erasable unit */ + uint8 Pattern; /*!< Memory content after erase */ +} LDD_SDHC_TCardErase; + +/*! Card write protection properties */ +typedef struct { + uint16 GroupSize; /*!< The size of write protected group in number of erase groups */ + bool Permanent; /*!< Indicates whether card is permanently write protected (read-only) */ +} LDD_SDHC_TCardWriteProtect; + +/*! Card capabilities */ +typedef struct { + uint8 DataWidths; /*!< Bit mask of supported data bus widths */ + uint8 Operations; /*!< Bit mask of supported operations */ + bool HighSpeed; /*!< Indicates whether the card supports high clock configuration (SD bus clock frequency higher than about 25MHz) */ + bool HighCapacity; /*!< Indicates whether the card requires block addressing instead of byte addressing */ + bool LowVoltage; /*!< Indicates whether the card supports the host's low voltage range */ + LDD_SDHC_TCardAccess Read; /*!< Card data read access capabilities */ + LDD_SDHC_TCardAccess Write; /*!< Card data write access capabilities */ + LDD_SDHC_TCardErase Erase; /*!< Card data erasion capabilities */ + LDD_SDHC_TCardWriteProtect WriteProtect; /*!< Write protection properties */ +} LDD_SDHC_TCardCaps; + +/*! Card features description */ +typedef struct { + LDD_SDHC_TCardType Type; /*!< Card type */ + uint16 BlockLength; /*!< Physical memory block length */ + uint32 BlockCount; /*!< Number of physical memory blocks */ + LDD_SDHC_TCardCaps Caps; /*!< Card capabilities */ +} LDD_SDHC_TCardInfo; + +/*! Transfer operations */ +typedef enum { + LDD_SDHC_READ, /*!< Read operation */ + LDD_SDHC_WRITE /*!< Write operation */ +} LDD_SDHC_TTransferOperation; + +/*! Transfer buffer descriptor */ +typedef struct { + uint16 Size; /*!< Buffer data size */ + uint8 *DataPtr; /*!< Pointer to buffer data */ +} LDD_SDHC_TBufferDesc; + +/*! Voltage options */ +typedef enum { + LDD_SDHC_LOW_VOLTAGE, /*!< Low voltage */ + LDD_SDHC_HIGH_VOLTAGE /*!< High voltage */ +} LDD_SDHC_TVoltage; + +/*! Write protection types */ +typedef enum { + LDD_SDHC_GROUP, /*!< Write protection by groups */ + LDD_SDHC_CARD /*!< Whole card write protection */ +} LDD_SDHC_TWriteProtectType; + +/*! Component states */ +typedef enum { + LDD_SDHC_DISABLED, /*!< Disabled */ + LDD_SDHC_RESET, /*!< Resetting card */ + LDD_SDHC_IDLE, /*!< Idling */ + LDD_SDHC_VOLTAGE_VALIDATION, /*!< Validating voltage */ + LDD_SDHC_CARD_REGISTRATION, /*!< Registrating card */ + LDD_SDHC_CARD_SELECTION, /*!< Selecting card */ + LDD_SDHC_CARD_INFO_RETRIEVAL, /*!< Retrieving card info */ + LDD_SDHC_TRANSFER, /*!< Transferring data */ + LDD_SDHC_ERASION, /*!< Erasing blocks */ + LDD_SDHC_IO_REG_TRANSFER, /*!< Transferring IO registers */ + LDD_SDHC_DATA_WIDTH_SELECTION, /*!< Selecting data width */ + LDD_SDHC_BUS_CLOCK_SELECTION, /*!< Selecting bus clock */ + LDD_SDHC_WRITE_PROTECTION_SETUP, /*!< Setting up write protection */ + LDD_SDHC_WRITE_PROTECTION_RETRIEVAL /*!< Retrieving write protection configuration */ +} LDD_SDHC_TStatus; + +/*! Operation completion error codes */ +typedef enum { + LDD_SDHC_ERR_OK, /*!< No error */ + LDD_SDHC_ERR_DMA, /*!< DMA or block size error */ + LDD_SDHC_ERR_NOT_SUPPORTED, /*!< Initiated operation is not supported by the card (supported operations are contained in the card information structure) */ + LDD_SDHC_ERR_TIMEOUT, /*!< Command or data timeout */ + LDD_SDHC_ERR_COMMAND_CRC, /*!< Command CRC check failed */ + LDD_SDHC_ERR_DATA_CRC, /*!< Data CRC check failed */ + LDD_SDHC_ERR_ADDRESS_OUT_OF_RANGE, /*!< The card address is beyond the card capacity */ + LDD_SDHC_ERR_ADDRESS_MISALIGN, /*!< The card address does not align with physical blocks of the card */ + LDD_SDHC_ERR_BLOCK_LEN_ERROR, /*!< Block length exceeds the maximum value for the card */ + LDD_SDHC_ERR_WP_VIOLATION, /*!< Attempt to program a write protected block */ + LDD_SDHC_ERR_CARD_IS_LOCKED, /*!< The card is locked by the host */ + LDD_SDHC_ERR_WP_ERASE_SKIP, /*!< Only partial address space was erased due to existing write protected blocks */ + LDD_SDHC_ERR_INTERNAL_FAILURE, /*!< Internal component error */ + LDD_SDHC_ERR_CARD_FAILURE /*!< The card was unable to complete the operation */ +} LDD_SDHC_TError; + +/* +** =================================================================== +** DMA device types and constants +** =================================================================== +*/ + +#define LDD_DMA_ON_COMPLETE 0x01U /*!< OnTransferComplete event mask. */ +#define LDD_DMA_ON_ERROR 0x02U /*!< OnError event mask. */ + +#define LDD_DMA_UNKNOWN_ERROR 0x80000000U /*!< Unknown error. */ +#define LDD_DMA_CHANNEL_PRIORITY_ERROR 0x4000U /*!< Channel priority error. */ +#define LDD_DMA_SOURCE_ADDRESS_ERROR 0x80U /*!< Address inconsistency with transfer size error. */ +#define LDD_DMA_SOURCE_OFFSET_ERROR 0x40U /*!< Offset inconsistency with transfer size error. */ +#define LDD_DMA_DESTINATION_ADDRESS_ERROR 0x20U /*!< Address inconsistency with transfer size error. */ +#define LDD_DMA_DESTINATION_OFFSET_ERROR 0x10U /*!< Offset inconsistency with transfer size error. */ +#define LDD_DMA_COUNT_ERROR 0x08U /*!< Byte count inconsistency with transfer sizes or transfer count error. */ +#define LDD_DMA_SCATTER_GATHER_ERROR 0x04U /*!< Scatter/gather configuration error. */ +#define LDD_DMA_SOURCE_BUS_ERROR 0x02U /*!< Bus error on a source read. */ +#define LDD_DMA_DESTINATION_BUS_ERROR 0x01U /*!< Bus error on a destination write. */ + +#define LDD_DMA_CHANNEL_0_MASK 0x01UL /*!< DMA channel 0 mask. */ +#define LDD_DMA_CHANNEL_1_MASK 0x02UL /*!< DMA channel 1 mask. */ +#define LDD_DMA_CHANNEL_2_MASK 0x04UL /*!< DMA channel 2 mask. */ +#define LDD_DMA_CHANNEL_3_MASK 0x08UL /*!< DMA channel 3 mask. */ +#define LDD_DMA_CHANNEL_4_MASK 0x10UL /*!< DMA channel 4 mask. */ +#define LDD_DMA_CHANNEL_5_MASK 0x20UL /*!< DMA channel 5 mask. */ +#define LDD_DMA_CHANNEL_6_MASK 0x40UL /*!< DMA channel 6 mask. */ +#define LDD_DMA_CHANNEL_7_MASK 0x80UL /*!< DMA channel 7 mask. */ +#define LDD_DMA_CHANNEL_8_MASK 0x0100UL /*!< DMA channel 8 mask. */ +#define LDD_DMA_CHANNEL_9_MASK 0x0200UL /*!< DMA channel 9 mask. */ +#define LDD_DMA_CHANNEL_10_MASK 0x0400UL /*!< DMA channel 10 mask. */ +#define LDD_DMA_CHANNEL_11_MASK 0x0800UL /*!< DMA channel 11 mask. */ +#define LDD_DMA_CHANNEL_12_MASK 0x1000UL /*!< DMA channel 12 mask. */ +#define LDD_DMA_CHANNEL_13_MASK 0x2000UL /*!< DMA channel 13 mask. */ +#define LDD_DMA_CHANNEL_14_MASK 0x4000UL /*!< DMA channel 14 mask. */ +#define LDD_DMA_CHANNEL_15_MASK 0x8000UL /*!< DMA channel 15 mask. */ +#define LDD_DMA_CHANNEL_16_MASK 0x00010000UL /*!< DMA channel 16 mask. */ +#define LDD_DMA_CHANNEL_17_MASK 0x00020000UL /*!< DMA channel 17 mask. */ +#define LDD_DMA_CHANNEL_18_MASK 0x00040000UL /*!< DMA channel 18 mask. */ +#define LDD_DMA_CHANNEL_19_MASK 0x00080000UL /*!< DMA channel 19 mask. */ +#define LDD_DMA_CHANNEL_20_MASK 0x00100000UL /*!< DMA channel 21 mask. */ +#define LDD_DMA_CHANNEL_21_MASK 0x00200000UL /*!< DMA channel 22 mask. */ +#define LDD_DMA_CHANNEL_22_MASK 0x00400000UL /*!< DMA channel 23 mask. */ +#define LDD_DMA_CHANNEL_23_MASK 0x00800000UL /*!< DMA channel 24 mask. */ +#define LDD_DMA_CHANNEL_24_MASK 0x01000000UL /*!< DMA channel 25 mask. */ +#define LDD_DMA_CHANNEL_25_MASK 0x02000000UL /*!< DMA channel 26 mask. */ +#define LDD_DMA_CHANNEL_26_MASK 0x04000000UL /*!< DMA channel 27 mask. */ +#define LDD_DMA_CHANNEL_27_MASK 0x08000000UL /*!< DMA channel 28 mask. */ +#define LDD_DMA_CHANNEL_28_MASK 0x10000000UL /*!< DMA channel 29 mask. */ +#define LDD_DMA_CHANNEL_29_MASK 0x20000000UL /*!< DMA channel 30 mask. */ +#define LDD_DMA_CHANNEL_30_MASK 0x40000000UL /*!< DMA channel 31 mask. */ +#define LDD_DMA_CHANNEL_31_MASK 0x80000000UL /*!< DMA channel 32 mask. */ + +/* Action executed after request and transfer service completes */ +#define LDD_DMA_NO_ACTION 0x00U /*!< No action performed after request serviced. */ +#define LDD_DMA_DESTINATION_ADDRESS_ADJUSTMENT 0x01U /*!< Destination address adjustment after request serviced. */ +#define LDD_DMA_SOURCE_ADDRESS_ADJUSTMENT 0x02U /*!< Source address adjustment after request serviced. */ +#define LDD_DMA_ADDRESS_ADJUSTMENT 0x01U /*!< Address adjustment after transfer completed. */ +#define LDD_DMA_SCATTER_GATHER 0x02U /*!< Scatter/gather performed after transfer completed. */ + +typedef void LDD_DMA_TData; +typedef uint8 LDD_DMA_TTransactionSize; /* Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint32 LDD_DMA_TTransactionCount; +typedef uint32 LDD_DMA_TRequestCount; +typedef uint32 LDD_DMA_TTransferDataSize; + +typedef uint32 LDD_DMA_TAddress; /*!< Type specifying the address parameter used by the DMA component's methods. */ +typedef int32 LDD_DMA_TAddressOffset; /*!< Type specifying the address signed offset parameter used by the DMA component's methods. */ +typedef uint32 LDD_DMA_TByteCount; /*!< Type specifying the byte count/minor loop count parameter used by the DMA component's methods. */ +typedef uint8 LDD_DMA_TTransferSize; /*!< Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint8 LDD_DMA_TModuloSize; /*!< Type specifying the modulo size parameter used by the DMA component's methods. */ + /*!< This value power of two represents size of used circular buffer (0U - buffer disabled). See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TTriggerSource; /*!< Type specifying the trigger source signal number. See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TChannelNumber; /*!< Type specifying the DMA channel number. See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TRecordNumber; /*!< Type specifying the DMA descriptor record number. */ +typedef uint32 LDD_DMA_TChannelMask; /*!< Type specifying the DMA channel mask. For possible values see channel mask constants. */ +typedef uint8 LDD_DMA_TChannelPriority; /*!< Type specifying the DMA channel priority number. See the MCU manual for detail description of allowed values. */ +typedef uint16 LDD_DMA_TOuterLoopCount; /*!< Type specifying the transfer outer/major loop count. */ +typedef uint8 LDD_DMA_TAfterRequest; /*!< Type specifying the operation executed after request service is completed. */ +typedef uint8 LDD_DMA_TAfterTransfer; /*!< Type specifying the operation executed after transfer service is completed. */ +typedef uint8 LDD_DMA_TBandwidthControl; /*!< Type specifying the bandwidth control. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint32 LDD_DMA_TErrorFlags; /*!< DMA controller error flags. See the DMA_LDD component's header file for detail description of allowed values. */ + +/*! Type specifying a DMA channel status. */ +typedef enum { + LDD_DMA_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */ + LDD_DMA_BUSY, /*!< Channel is active, request is serviced. */ + LDD_DMA_DONE, /*!< Transfer is completed, waiting to start of next transfer. */ + LDD_DMA_ERROR /*!< Error detected. */ +} LDD_DMA_TChannelStatus; + +/*! Type specifying a DMA transfer state. */ +typedef enum { + LDD_DMA_TRANSFER_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */ + LDD_DMA_TRANSFER_BUSY, /*!< Channel is active, request is serviced. */ + LDD_DMA_TRANSFER_ERROR /*!< Error detected. */ +} LDD_DMA_TTransferState; + +/*! Type specifying the DMA transfer mode. */ +typedef enum { + LDD_DMA_CYCLE_STEAL_TRANSFERS, /*!< Only single read/write transfer is done per one service request. */ + LDD_DMA_SINGLE_TRANSFER, /*!< Transfer of all bytes defined by Data size is done after single service request. */ + LDD_DMA_NESTED_TRANSFERS /*!< Sequence of transfers triggered by service requests. One request transfers number of bytes defined by Byte count value. */ +} LDD_DMA_TTransferMode; + +/*! Type specifying the DMA trigger source type. */ +typedef enum { + LDD_DMA_SW_TRIGGER, /*!< Explicit software trigger. */ + LDD_DMA_HW_TRIGGER, /*!< Peripheral device trigger. */ + LDD_DMA_ALWAYS_ENABLED_TRIGGER /*!< Always enabled trigger. */ +} LDD_DMA_TTriggerType; + +/*! Type specifying the DMA error information structure. */ +typedef struct { + LDD_DMA_TChannelNumber ChannelNumber; /*!< Last error recorded channel number. */ + LDD_DMA_TErrorFlags ErrorFlags; /*!< Channel error flags. */ +} LDD_DMA_TError; + +/*! Type specifying the DMA Transfer descriptor information structure. */ +typedef struct { + LDD_TUserData *UserDataPtr; /*!< User device data structure pointer to be returned by the DMA_LDD component's ISR to the dynamic callback of this transfer descriptor. */ + LDD_DMA_TAddress SourceAddress; /*!< Address of a DMA transfer source data. */ + LDD_DMA_TAddressOffset SourceAddressOffset; /*!< Offset to be added to the source address after each elemental read operation. */ + LDD_DMA_TTransferSize SourceTransferSize; /*!< Source data transfer size (size of a elemental read operation). See the DMA_PDD header file for detail description of allowed values. */ + LDD_DMA_TModuloSize SourceModuloSize; /*!< Source address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */ + LDD_DMA_TAddress DestinationAddress; /*!< Address of a DMA transfer destination. */ + LDD_DMA_TAddressOffset DestinationAddressOffset; /*!< Offset to be added to the destination address after each elemental write operation. */ + LDD_DMA_TTransferSize DestinationTransferSize; /*!< Destination data transfer size (size of a elemental write operation). See the DMA_PDD header file for detail description of allowed values. */ + LDD_DMA_TModuloSize DestinationModuloSize; /*!< Destination address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */ + LDD_DMA_TTransferMode TransferMode; /*!< Selects DMA transfer mode. For the description of allowed values see the LDD_DMA_TTransferMode type declaration. */ + LDD_DMA_TByteCount ByteCount; /*!< Size of data in bytes to be transferred in single transfer. */ + LDD_DMA_TOuterLoopCount OuterLoopCount; /*!< Number of the outer loop iteration in the Nested operation mode, otherwise should have value of one. */ + bool InnerLoopChannelLink; /*!< TRUE - Inner loop channel linking enabled (if the nested operation is used, then this item enables the minor (inner) loop channel linking). */ + LDD_DMA_TChannelNumber InnerLoopLinkedChannel; /*!< Linked DMA channel number (used only if the InnerLoopChannelLink item is set TRUE) */ + bool OuterLoopChannelLink; /*!< TRUE - Outer (major) loop channel linking is enabled. Enables channel linking after transfer completes. */ + LDD_DMA_TChannelNumber OuterLoopLinkedChannel; /*!< Outer (major) loop linked DMA channel number (used only if the OuterLoopChannelLink item is set TRUE). */ + LDD_DMA_TAfterRequest AfterRequestComplete; /*!< Type of an action after the elemental read/write operation is done. For the description of allowed values see the LDD_DMA_TAfterRequest type declaration. */ + LDD_DMA_TAddressOffset AddressOffset; /*!< Address offset value. Address specified in AfterRequestComplete item is adjusted by stored value. See the LDD_DMA_TAfterRequest type declaration. */ + LDD_DMA_TAfterTransfer AfterTransferComplete; /*!< Type of an action executed after the last transfer operation is done. For the description of allowed values see the LDD_DMA_TAfterTransfer type declaration. */ + LDD_DMA_TAddressOffset SourceAddressAdjustment; /*!< Source address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */ + LDD_DMA_TAddressOffset DestinationAddressAdjustment; /*!< Destination address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */ + LDD_DMA_TAddress ScatterGatherAddress; /*!< Scatter / gather address. Used only if the AfterTransferComplete item is set to LDD_DMA_SCATTER_GATHER. */ + LDD_DMA_TBandwidthControl BandwidthControl; /*!< DMA channel bandwidth control. See the DMA_PDD header file for detail description of allowed values. */ + bool ChannelAutoSelection; /*!< TRUE - DMA channel autoselection engine is used. FALSE - DMA fixed channel is used. */ + LDD_DMA_TChannelNumber ChannelNumber; /*!< If ChannelAutoSelection is FALSE this item contains fixed channel number. If ChannelAutoSelection is TRUE then after allocation this item is filled by autoselected channel number. */ + LDD_DMA_TTriggerType TriggerType; /*!< DMA transfer trigger type. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */ + LDD_DMA_TTriggerSource TriggerSource; /*!< Trigger source number. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */ + bool PeriodicTrigger; /*!< TRUE - periodic trigger is required, FALSE - periodic trigger is not required. */ + bool DisableAfterRequest; /*!< TRUE - DMA transfer request is automatically disabled after transfer complete. */ + bool Interrupts; /*!< TRUE - interrupts are requested. */ + bool OnComplete; /*!< TRUE - event is enabled during initialization. */ + bool OnHalfComplete; /*!< TRUE - event is enabled during initialization. */ + bool OnError; /*!< TRUE - event is enabled during initialization. */ + void (*OnCompleteEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnComplete event, NULL if event is not used. */ + void (*OnErrorEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnError event, NULL if event is not used. */ + bool ChannelEnabled; /*!< TRUE - DMA channel is allocated and used by DMATransfer component. */ +} LDD_DMA_TTransferDescriptor; + +typedef LDD_DMA_TTransferDescriptor *LDD_DMA_TTransferDescriptorPtr; /*!< Type specifying address of the DMA Transfer descriptor structure. */ + +/* +** =================================================================== +** SPI device types and constants - SPIMaster_LDD +** =================================================================== +*/ + +#define LDD_SPIMASTER_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SPIMASTER_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SPIMASTER_CLK_PIN 0x04U /*!< Clock pin mask */ +#define LDD_SPIMASTER_CS_0_PIN 0x08U /*!< Chip select 0 pin mask */ +#define LDD_SPIMASTER_CS_1_PIN 0x10U /*!< Chip select 1 pin mask */ +#define LDD_SPIMASTER_CS_2_PIN 0x20U /*!< Chip select 2 pin mask */ +#define LDD_SPIMASTER_CS_3_PIN 0x40U /*!< Chip select 3 pin mask */ +#define LDD_SPIMASTER_CS_4_PIN 0x80U /*!< Chip select 4 pin mask */ +#define LDD_SPIMASTER_CS_5_PIN 0x0100U /*!< Chip select 5 pin mask */ +#define LDD_SPIMASTER_CS_6_PIN 0x0200U /*!< Chip select 6 pin mask */ +#define LDD_SPIMASTER_CS_7_PIN 0x0400U /*!< Chip select 7 pin mask */ +#define LDD_SPIMASTER_CSS_PIN 0x0800U /*!< Chip select strobe pin mask */ + +#define LDD_SPIMASTER_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */ +#define LDD_SPIMASTER_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */ +#define LDD_SPIMASTER_ON_ERROR 0x04U /*!< OnError event mask */ + +#define LDD_SPIMASTER_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SPIMASTER_PARITY_ERROR 0x02U /*!< Parity error */ +#define LDD_SPIMASTER_RX_DMA_ERROR 0x04U /*!< Receive DMA channel error */ +#define LDD_SPIMASTER_TX_DMA_ERROR 0x08U /*!< Transmit DMA channel error */ + +typedef uint32 LDD_SPIMASTER_TError; /*!< Communication error type */ + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxParityErrors; /*!< Number of receiver parity errors, which have occured */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ +} LDD_SPIMASTER_TStats; + +/* +** =================================================================== +** SPI device types and constants - SPISlave_LDD +** =================================================================== +*/ + +#define LDD_SPISLAVE_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SPISLAVE_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SPISLAVE_CLK_PIN 0x04U /*!< Clock pin mask */ +#define LDD_SPISLAVE_SS_PIN 0x08U /*!< Slave select pin mask */ + +#define LDD_SPISLAVE_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */ +#define LDD_SPISLAVE_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */ +#define LDD_SPISLAVE_ON_ERROR 0x04U /*!< OnError event mask */ + +#define LDD_SPISLAVE_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SPISLAVE_TX_UNDERFLOW 0x02U /*!< Transmitter underflow */ +#define LDD_SPISLAVE_PARITY_ERROR 0x04U /*!< Parity error */ +#define LDD_SPISLAVE_RX_DMA_ERROR 0x08U /*!< Receive DMA channel error */ +#define LDD_SPISLAVE_TX_DMA_ERROR 0x10U /*!< Transmit DMA channel error */ + +typedef uint32 LDD_SPISLAVE_TError; /*!< Communication error type */ + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxParityErrors; /*!< Number of receiver parity errors, which have occured */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ + uint32 TxUnderruns; /*!< Number of transmitter underruns, which have occured */ +} LDD_SPISLAVE_TStats; + +/* +** =================================================================== +** I2S device types and constants +** =================================================================== +*/ + +#define LDD_SSI_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SSI_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SSI_RX_CLK_PIN 0x04U /*!< Rx clock pin mask */ +#define LDD_SSI_TX_CLK_PIN 0x08U /*!< Tx clock pin mask */ +#define LDD_SSI_RX_FS_PIN 0x10U /*!< Rx frame sync pin mask */ +#define LDD_SSI_TX_FS_PIN 0x20U /*!< Tx frame sync pin mask */ +#define LDD_SSI_MCLK_PIN 0x40U /*!< Master clock pin mask */ +#define LDD_SSI_INPUT_PIN_CHANNEL_0 0x80U /*!< Input pin mask for data channel 0 */ +#define LDD_SSI_INPUT_PIN_CHANNEL_1 0x0100U /*!< Input pin mask for data channel 1 */ +#define LDD_SSI_OUTPUT_PIN_CHANNEL_0 0x0200U /*!< Output pin mask for data channel 0 */ +#define LDD_SSI_OUTPUT_PIN_CHANNEL_1 0x0400U /*!< Output pin mask for data channel 1 */ + +#define LDD_SSI_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */ +#define LDD_SSI_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */ +#define LDD_SSI_ON_ERROR 0x04u /*!< OnError event mask */ +#define LDD_SSI_ON_BLOCK_RECEIVED_1 0x08u /*!< OnBlockReceived event mask for second channel */ +#define LDD_SSI_ON_BLOCK_SENT_1 0x10u /*!< OnBlockSent event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_FRAME_SYNC 0x20u /*!< OnReceiveFrameSync event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_FRAME_SYNC 0x40u /*!< OnTransmitFrameSync event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_LAST_SLOT 0x80u /*!< OnReceiveLastSlot event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_LAST_SLOT 0x0100u /*!< OnTransmitLastSlot event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_COMPLETE 0x0200u /*!< OnReceiveComplete event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_COMPLETE 0x0400u /*!< OnTransmitComplete event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */ + +#define LDD_SSI_RECEIVER 0x01U /*!< Receive section of the device. */ +#define LDD_SSI_TRANSMITTER 0x02U /*!< Transmit section of the device. */ + +#define LDD_SSI_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SSI_RX_OVERFLOW_1 0x02U /*!< Receiver overflow 1 */ +#define LDD_SSI_RX_SYNC_ERROR 0x04U /*!< Receiver frame sync error */ +#define LDD_SSI_RX_DMA_ERROR 0x08U /*!< Receiver DMA error */ + +#define LDD_SSI_TX_UNDERFLOW 0x10U /*!< Transmitter underflow */ +#define LDD_SSI_TX_UNDERFLOW_1 0x20U /*!< Transmitter underflow 1 */ +#define LDD_SSI_TX_SYNC_ERROR 0x40U /*!< Transmitter frame sync error */ +#define LDD_SSI_TX_DMA_ERROR 0x80U /*!< Transmitter DMA error */ + +#define LDD_SSI_RX_FRAME_COMPLETE 0x01U /*!< Receive frame is finished after disabling transfer */ +#define LDD_SSI_TX_FRAME_COMPLETE 0x02U /*!< Transmit frame is finished after disabling transfer */ +#define LDD_SSI_RX_FRAME_SYNC 0x04U /*!< Receiver frame sync */ +#define LDD_SSI_TX_FRAME_SYNC 0x08U /*!< Transmit frame sync */ +#define LDD_SSI_RX_LAST_SLOT 0x10U /*!< Receive last time slot */ +#define LDD_SSI_TX_LAST_SLOT 0x20U /*!< Transmit last time slot */ +#define LDD_SSI_AC97_TAG 0x40U /*!< AC97 tag updated */ +#define LDD_SSI_AC97_COMMAND_ADDRESS 0x80U /*!< AC97 command address updated */ +#define LDD_SSI_AC97_COMMAND_DATA 0x0100U /*!< AC97 command data updated */ + +typedef uint8 LDD_SSI_TSectionMask; /*!< Device section type */ + +typedef uint32 LDD_SSI_TError; /*!< Communication error type */ + +typedef uint32 LDD_SSI_TComStatus; /*!< Communication status type */ + +/*! Group of pointers to data blocks. */ +typedef struct { + LDD_TData *Channel0Ptr; /*!< Pointer to data block to send/received via data channel 0 */ + LDD_TData *Channel1Ptr; /*!< Pointer to data block to send/received via data channel 1 */ +} LDD_SSI_TDataBlocks; + +/*! Command type */ +typedef enum { + LDD_SSI_READ_COMMAND = 0x08u, + LDD_SSI_WRITE_COMMAND = 0x10u +} LDD_SSI_TAC97CommandType; + +/*! AC97 command */ +typedef struct { + LDD_SSI_TAC97CommandType Type; /*!< Command type */ + uint32 Address; /*!< Command address */ + uint32 Data; /*!< Command data */ +} LDD_SSI_TAC97Command; + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ + uint32 TxUnderruns; /*!< Number of transmitter underruns, which have occured */ + uint32 RxChars1; /*!< Number of received characters for second channel */ + uint32 TxChars1; /*!< Number of transmitted characters for second channel */ + uint32 RxOverruns1; /*!< Number of receiver overruns, which have occured for second channel */ + uint32 TxUnderruns1; /*!< Number of transmitter underruns, which have occured for second channel */ +} LDD_SSI_TStats; + +/* +** =================================================================== +** RTC device types and constants +** =================================================================== +*/ + +#define LDD_RTC_ON_SECOND 0x10u /*!< OnSecond event mask */ +#define LDD_RTC_ON_MONOTONIC_OVERFLOW 0x08u /*!< OnMonotonicCounter event mask */ +#define LDD_RTC_ON_ALARM 0x04u /*!< OnAlarm event mask */ +#define LDD_RTC_ON_TIME_OVERFLOW 0x02u /*!< OnTimeOverflow event mask */ +#define LDD_RTC_ON_TIME_INVALID 0x01u /*!< OnTimeInvalid event mask */ +#define LDD_RTC_ON_STOPWATCH 0x0100u /*!< OnStopwatch event mask */ + +/*! Structure used for time operation */ +typedef struct { + uint32 Second; /*!< seconds (0 - 59) */ + uint32 Minute; /*!< minutes (0 - 59) */ + uint32 Hour; /*!< hours (0 - 23) */ + uint32 DayOfWeek; /*!< day of week (0-Sunday, .. 6-Saturday) */ + uint32 Day; /*!< day (1 - 31) */ + uint32 Month; /*!< month (1 - 12) */ + uint32 Year; /*!< year */ +} LDD_RTC_TTime; + + + +/* +** =================================================================== +** CRC device types and constants +** =================================================================== +*/ + +#define LDD_CRC_16_SEED_LOW 0x00U /*!< CRC 16bit seed low */ +#define LDD_CRC_16_POLY_LOW 0x8005U /*!< CRC 16bit poly low */ +#define LDD_CRC_32_SEED_LOW 0xFFFFU /*!< CRC 32bit seed low */ +#define LDD_CRC_32_SEED_HIGH 0xFFFFU /*!< CRC 32bit seed high */ +#define LDD_CRC_32_POLY_LOW 0x1DB7U /*!< CRC 32bit poly low */ +#define LDD_CRC_32_POLY_HIGH 0x04C1U /*!< CRC 32bit poly high */ +#define LDD_CRC_CCITT_SEED_LOW 0xFFFFU /*!< CRC CCITT seed low */ +#define LDD_CRC_CCITT_POLY_LOW 0x1021U /*!< CRC CCITT poly low */ +#define LDD_CRC_MODBUS_16_SEED_LOW 0xFFFFU /*!< CRC MODBUS16 seed low */ +#define LDD_CRC_MODBUS_16_POLY_LOW 0x8005U /*!< CRC MODBUS16 poly low */ +#define LDD_CRC_KERMIT_SEED_LOW 0x00U /*!< CRC KERMIT seed low */ +#define LDD_CRC_KERMIT_POLY_LOW 0x1021U /*!< CRC KERMIT poly low */ +#define LDD_CRC_DNP_SEED_LOW 0x00U /*!< CRC DNP seed low */ +#define LDD_CRC_DNP_POLY_LOW 0x3D65U /*!< CRC DNP poly low */ + +/*! Transpose type */ +typedef enum { + LDD_CRC_NO_TRANSPOSE = 0, /*!< No transposition */ + LDD_CRC_BITS = 1, /*!< Bits are transposed */ + LDD_CRC_BITS_AND_BYTES = 2, /*!< Bits and bytes are transposed */ + LDD_CRC_BYTES = 3 /*!< Bytes are transposed */ +} LDD_CRC_TTransposeType; + +/*! CRC standard */ +typedef enum { + LDD_CRC_16, /*!< CRC16 standard */ + LDD_CRC_CCITT, /*!< CCITT standard */ + LDD_CRC_MODBUS_16, /*!< MODBUS16 standard */ + LDD_CRC_KERMIT, /*!< KERMIT standard */ + LDD_CRC_DNP, /*!< DNP standard */ + LDD_CRC_32, /*!< CRC32 standard */ + LDD_CRC_USER /*!< User defined type */ +} LDD_CRC_TCRCStandard; + +/*! User CRC standard */ +typedef struct { + bool Width32bit; /*!< 32bit CRC? */ + bool ResultXORed; /*!< Result XORed? */ + uint16 SeedLow; /*!< Seed low value */ + uint16 SeedHigh; /*!< Seed high value */ + uint16 PolyLow; /*!< Poly low value */ + uint16 PolyHigh; /*!< Poly high value */ + LDD_CRC_TTransposeType InputTransposeMode; /*!< Input transpose type */ + LDD_CRC_TTransposeType OutputTransposeMode; /*!< Output transpose type */ +} LDD_CRC_TUserCRCStandard; + +/* +** =================================================================== +** RNG device types and constants +** =================================================================== +*/ + + +#define LDD_RNG_LFSR_ERROR 0x01U /*!< Linear feedback shift register error */ +#define LDD_RNG_OSCILLATOR_ERROR 0x02U /*!< Oscillator error */ +#define LDD_RNG_SELF_TEST_ERROR 0x04U /*!< Self test error */ +#define LDD_RNG_STATISTICAL_ERROR 0x08U /*!< LStatistical test error */ +#define LDD_RNG_FIFO_UNDERFLOW_ERROR 0x10U /*!< FIFO underflow error */ + +#define LDD_RNG_SELF_TETS_RESEED_ERROR 0x00200000U /*!< Reseed self test fail */ +#define LDD_RNG_SELF_TEST_PRNG_ERROR 0x00400000U /*!< PRNG self test fail */ +#define LDD_RNG_SELF_TEST_TRNG_ERROR 0x00800000U /*!< TRNG self test fail */ +#define LDD_RNG_MONOBIT_TEST_ERROR 0x01000000U /*!< Monobit test fail */ +#define LDD_RNG_LENGTH_1_RUN_TEST_ERROR 0x02000000U /*!< Length 1 run test fail */ +#define LDD_RNG_LENGTH_2_RUN_TEST_ERROR 0x04000000U /*!< Length 2 run test fail */ +#define LDD_RNG_LENGTH_3_RUN_TEST_ERROR 0x08000000U /*!< Length 3 run test fail */ +#define LDD_RNG_LENGTH_4_RUN_TEST_ERROR 0x10000000U /*!< Length 4 run test fail */ +#define LDD_RNG_LENGTH_5_RUN_TEST_ERROR 0x20000000U /*!< Length 5 run test fail */ +#define LDD_RNG_LENGTH_6_RUN_TEST_ERROR 0x40000000U /*!< Length 6 run test fail */ +#define LDD_RNG_LONG_RUN_TEST_ERROR 0x80000000U /*!< Long run test fail */ + +#define LDD_RNG_ON_SEED_GENERATION_DONE 0x01U /*!< OnSeedGenerationDone event mask */ +#define LDD_RNG_ON_SELF_TEST_DONE 0x02U /*!< OnSelfTestDone event mask */ +#define LDD_RNG_ON_ERROR_LFSR 0x04U /*!< OnErrorLFSR event mask */ +#define LDD_RNG_ON_OSC_ERROR 0x08U /*!< OnOscError event mask */ +#define LDD_RNG_ON_SELF_TEST_ERROR 0x10U /*!< OnSelfTestError event mask */ +#define LDD_RNG_ON_STATISTICAL_ERROR 0x20U /*!< OnStatisticalError event mask */ +#define LDD_RNG_ON_FIFO_UNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */ +#define LDD_RNG_ON_FIFOUNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */ + +#define LDD_RNG_STATUS_ERROR 0xFFFFU /*!< Error in RNG module flag */ +#define LDD_RNG_STATUS_NEW_SEED_DONE 0x40U /*!< New seed done flag */ +#define LDD_RNG_STATUS_SEED_DONE 0x20U /*!< Seed done flag */ +#define LDD_RNG_STATUS_SELF_TEST_DONE 0x10U /*!< Self test done flag */ +#define LDD_RNG_STATUS_RESEED_NEEDED 0x08U /*!< Reseed needed flag */ +#define LDD_RNG_STATUS_SLEEP 0x04U /*!< RNG in sleep mode */ +#define LDD_RNG_STATUS_BUSY 0x02U /*!< RNG busy flag */ + + +/* +** =================================================================== +** RNGA device types and constants +** =================================================================== +*/ + +#define LDD_RNG_ON_ERROR 0x01U /*!< OnError event mask */ + +#define LDD_RNG_STATUS_SECURITY_VIOLATION 0x01U /*!< Security violation occured */ +#define LDD_RNG_STATUS_LAST_READ_UNDERFLOW 0x02U /*!< Last read from RNGA caused underflow error */ +#define LDD_RNG_STATUS_OUT_REG_UNDERFLOW 0x04U /*!< The RNGA Output Register has been read while empty since last read of the RNGA Status Register. */ +#define LDD_RNG_STATUS_ERR_INT_PENDING 0x08U /*!< Error interrupt pending */ +#define LDD_RNG_STATUS_SLEEP_MODE 0x10U /*!< Sleep mode enabled */ + +/*! RNGA sleep mode */ +typedef enum { + LDD_RNG_SLEEP_ENABLED, /*!< RNGA is in sleep mode */ + LDD_RNG_SLEEP_DISABLED /*!< RNGA is running */ +} LDD_RNG_TSleepMode; + +/* +** =================================================================== +** DryIce device types and constants +** =================================================================== +*/ + +#define LDD_DRY_ON_TAMPER_DETECTED 0x01U /*!< OnTamperDetected event mask */ + +/* Tamper flags */ +#define LDD_DRY_TIME_OVERFLOW 0x04U /*!< RTC time overflow has occurred. */ +#define LDD_DRY_MONOTONIC_OVERFLOW 0x08U /*!< RTC monotonic overflow has occurred. */ +#define LDD_DRY_VOLTAGE_TAMPER 0x10U /*!< VBAT voltage is outside of the valid range. */ +#define LDD_DRY_CLOCK_TAMPER 0x20U /*!< The 32.768 kHz clock source is outside the valid range. */ +#define LDD_DRY_TEMPERATURE_TAMPER 0x40U /*!< The junction temperature is outside of specification. */ +#define LDD_DRY_SECURITY_TAMPER 0x80U /*!< The (optional) security module asserted its tamper detect. */ +#define LDD_DRY_FLASH_SECURITY 0x0100U /*!< The flash security is disabled. */ +#define LDD_DRY_TEST_MODE 0x0200U /*!< Any test mode has been entered. */ +/* Tamper flags indicating that the pin does not equal its expected value and was not filtered by the glitch filter (if enabled). */ +#define LDD_DRY_TAMPER_PIN_0 0x00010000U /*!< Mismatch on tamper pin 0. */ +#define LDD_DRY_TAMPER_PIN_1 0x00020000U /*!< Mismatch on tamper pin 1. */ +#define LDD_DRY_TAMPER_PIN_2 0x00040000U /*!< Mismatch on tamper pin 2. */ +#define LDD_DRY_TAMPER_PIN_3 0x00080000U /*!< Mismatch on tamper pin 3. */ +#define LDD_DRY_TAMPER_PIN_4 0x00100000U /*!< Mismatch on tamper pin 4. */ +#define LDD_DRY_TAMPER_PIN_5 0x00200000U /*!< Mismatch on tamper pin 5. */ +#define LDD_DRY_TAMPER_PIN_6 0x00400000U /*!< Mismatch on tamper pin 6. */ +#define LDD_DRY_TAMPER_PIN_7 0x00800000U /*!< Mismatch on tamper pin 7. */ + +#define LDD_DRY_SECURE_KEY_WORD_0 0x01U /*!< Secure key word 0 mask */ +#define LDD_DRY_SECURE_KEY_WORD_1 0x02U /*!< Secure key word 1 mask */ +#define LDD_DRY_SECURE_KEY_WORD_2 0x04U /*!< Secure key word 2 mask */ +#define LDD_DRY_SECURE_KEY_WORD_3 0x08U /*!< Secure key word 3 mask */ +#define LDD_DRY_SECURE_KEY_WORD_4 0x10U /*!< Secure key word 4 mask */ +#define LDD_DRY_SECURE_KEY_WORD_5 0x20U /*!< Secure key word 5 mask */ +#define LDD_DRY_SECURE_KEY_WORD_6 0x40U /*!< Secure key word 6 mask */ +#define LDD_DRY_SECURE_KEY_WORD_7 0x80U /*!< Secure key word 7 mask */ + +/* +** =================================================================== +** NFC device types and constants +** =================================================================== +*/ + +/* Events' masks */ +#define LDD_NFC_ON_CMD_ERROR 0x01U /*!< OnCmdError event mask */ +#define LDD_NFC_ON_CMD_DONE 0x02U /*!< OnCmdDone event mask */ + +/* Pins' masks */ +#define LDD_NFC_CE0_PIN 0x01U /*!< CE0 pin mask */ +#define LDD_NFC_RB0_PIN 0x02U /*!< RB0 pin mask */ +#define LDD_NFC_CE1_PIN 0x04U /*!< CE1 pin mask */ +#define LDD_NFC_RB1_PIN 0x08U /*!< RB1 pin mask */ +#define LDD_NFC_CE2_PIN 0x10U /*!< CE2 pin mask */ +#define LDD_NFC_RB2_PIN 0x20U /*!< RB2 pin mask */ +#define LDD_NFC_CE3_PIN 0x40U /*!< CE3 pin mask */ +#define LDD_NFC_RB3_PIN 0x80U /*!< RB3 pin mask */ +#define LDD_NFC_ALE_PIN 0x0100U /*!< ALE pin mask */ +#define LDD_NFC_CLE_PIN 0x0200U /*!< CLE pin mask */ +#define LDD_NFC_RE_PIN 0x0400U /*!< RE pin mask */ +#define LDD_NFC_WE_PIN 0x0800U /*!< WE pin mask */ +#define LDD_NFC_D0_PIN 0x00010000U /*!< D0 pin mask */ +#define LDD_NFC_D1_PIN 0x00020000U /*!< D1 pin mask */ +#define LDD_NFC_D2_PIN 0x00040000U /*!< D2 pin mask */ +#define LDD_NFC_D3_PIN 0x00080000U /*!< D3 pin mask */ +#define LDD_NFC_D4_PIN 0x00100000U /*!< D4 pin mask */ +#define LDD_NFC_D5_PIN 0x00200000U /*!< D5 pin mask */ +#define LDD_NFC_D6_PIN 0x00400000U /*!< D6 pin mask */ +#define LDD_NFC_D7_PIN 0x00800000U /*!< D7 pin mask */ +#define LDD_NFC_D8_PIN 0x01000000U /*!< D8 pin mask */ +#define LDD_NFC_D9_PIN 0x02000000U /*!< D9 pin mask */ +#define LDD_NFC_D10_PIN 0x04000000U /*!< D10 pin mask */ +#define LDD_NFC_D11_PIN 0x08000000U /*!< D11 pin mask */ +#define LDD_NFC_D12_PIN 0x10000000U /*!< D12 pin mask */ +#define LDD_NFC_D13_PIN 0x20000000U /*!< D13 pin mask */ +#define LDD_NFC_D14_PIN 0x40000000U /*!< D14 pin mask */ +#define LDD_NFC_D15_PIN 0x80000000U /*!< D15 pin mask */ + +typedef uint32 LDD_NFC_TTargetID; /*!< NFC target ID type */ + +/*! NCF command codes */ +typedef enum { + LDD_NFC_CMD_NONE = 0x00U, /* No command */ + LDD_NFC_CMD_RESET = 0x01U, /* Reset command */ + LDD_NFC_CMD_ERASE = 0x02U, /* Erase command */ + LDD_NFC_CMD_READ_ID = 0x03U, /* Read ID command */ + LDD_NFC_CMD_READ_PAGES = 0x04U, /* Read pages command */ + LDD_NFC_CMD_WRITE_PAGES = 0x05U, /* Write pages command */ + LDD_NFC_CMD_ERASE_BLOCKS = 0x06U, /* Erase page command */ + LDD_NFC_CMD_READ_RAW_PAGE = 0x07U, /* Read raw page command */ + LDD_NFC_CMD_WRITE_RAW_PAGE = 0x08U /* Write raw page command */ +} LDD_NFC_TeCmd; + +/* +** =================================================================== +** LCDC device types and constants +** =================================================================== +*/ + +#define LDD_LCDC_ON_ERROR 0x01U /*!< OnError event mask */ +#define LDD_LCDC_ON_START_OF_FRAME 0x02U /*!< OnStartOfFrame event mask */ +#define LDD_LCDC_ON_END_OF_FRAME 0x04U /*!< OnEndOfFrame event mask */ + +#define LDD_LCDC_NO_ERR 0x00U /*!< No error */ +#define LDD_LCDC_PLANE_0_UNDERRUN_ERR 0x01U /*!< Plane 0 underrurn error */ +#define LDD_LCDC_PLANE_1_UNDERRUN_ERR 0x02U /*!< Plane 1 underrurn error */ + +#define LDD_LCDC_REVERSED_VERTICAL_SCAN 0x8000U /*!< Enable reversed vertical scan (flip along x-axis) */ + +/*! Bitmap description */ +typedef struct { + LDD_TData *Address; /*!< Bitmap starting address */ + uint16 Width; /*!< Bitmap width */ + uint16 Height; /*!< Bitmap height */ + uint16 Format; /*!< Bitmap format */ +} LDD_LCDC_TBitmap; + +/*! Window description */ +typedef struct { + uint16 X; /*!< Window position in bitmap - X */ + uint16 Y; /*!< Window position in bitmap - Y */ + uint16 Width; /*!< Window width */ + uint16 Height; /*!< Window height */ +} LDD_LCDC_TWindow; + +/*! Cursor type */ +typedef enum { + LDD_LCDC_DISABLED = 0, /*!< Cursor disabled */ + LDD_LCDC_ALWAYS_1, /*!< Cursor 1''s, monochrome display only. */ + LDD_LCDC_ALWAYS_0, /*!< Cursor 0''s, monochrome display only. */ + LDD_LCDC_COLOR, /*!< Defined cursor color, color display only. */ + LDD_LCDC_INVERTED, /*!< Inverted background, monochrome display only. */ + LDD_LCDC_INVERTED_COLOR, /*!< Inverted cursor color, color display only. */ + LDD_LCDC_AND, /*!< Cursor color AND backgroun, color display only. */ + LDD_LCDC_OR, /*!< Cursor color OR backgroun, color display only. */ + LDD_LCDC_XOR +} LDD_LCDC_CursorOperation; + +/*! Plane identification */ +typedef enum { + LDD_LCDC_PLANE_COMMON, /*!< Common for all planes */ + LDD_LCDC_PLANE_0, /*!< Plane (layer) 0 */ + LDD_LCDC_PLANE_1 /*!< Plane (layer) 1 */ +} LDD_LCDC_TPlaneID; + + +/* +** =================================================================== +** Interrupt vector constants +** =================================================================== +*/ +#define LDD_ivIndex_INT_Initial_Stack_Pointer 0x00u +#define LDD_ivIndex_INT_Initial_Program_Counter 0x01u +#define LDD_ivIndex_INT_NMI 0x02u +#define LDD_ivIndex_INT_Hard_Fault 0x03u +#define LDD_ivIndex_INT_Mem_Manage_Fault 0x04u +#define LDD_ivIndex_INT_Bus_Fault 0x05u +#define LDD_ivIndex_INT_Usage_Fault 0x06u +#define LDD_ivIndex_INT_Reserved7 0x07u +#define LDD_ivIndex_INT_Reserved8 0x08u +#define LDD_ivIndex_INT_Reserved9 0x09u +#define LDD_ivIndex_INT_Reserved10 0x0Au +#define LDD_ivIndex_INT_SVCall 0x0Bu +#define LDD_ivIndex_INT_DebugMonitor 0x0Cu +#define LDD_ivIndex_INT_Reserved13 0x0Du +#define LDD_ivIndex_INT_PendableSrvReq 0x0Eu +#define LDD_ivIndex_INT_SysTick 0x0Fu +#define LDD_ivIndex_INT_DMA0 0x10u +#define LDD_ivIndex_INT_DMA1 0x11u +#define LDD_ivIndex_INT_DMA2 0x12u +#define LDD_ivIndex_INT_DMA3 0x13u +#define LDD_ivIndex_INT_DMA4 0x14u +#define LDD_ivIndex_INT_DMA5 0x15u +#define LDD_ivIndex_INT_DMA6 0x16u +#define LDD_ivIndex_INT_DMA7 0x17u +#define LDD_ivIndex_INT_DMA8 0x18u +#define LDD_ivIndex_INT_DMA9 0x19u +#define LDD_ivIndex_INT_DMA10 0x1Au +#define LDD_ivIndex_INT_DMA11 0x1Bu +#define LDD_ivIndex_INT_DMA12 0x1Cu +#define LDD_ivIndex_INT_DMA13 0x1Du +#define LDD_ivIndex_INT_DMA14 0x1Eu +#define LDD_ivIndex_INT_DMA15 0x1Fu +#define LDD_ivIndex_INT_DMA_Error 0x20u +#define LDD_ivIndex_INT_MCM 0x21u +#define LDD_ivIndex_INT_FTFL 0x22u +#define LDD_ivIndex_INT_Read_Collision 0x23u +#define LDD_ivIndex_INT_LVD_LVW 0x24u +#define LDD_ivIndex_INT_LLW 0x25u +#define LDD_ivIndex_INT_Watchdog 0x26u +#define LDD_ivIndex_INT_Reserved39 0x27u +#define LDD_ivIndex_INT_I2C0 0x28u +#define LDD_ivIndex_INT_I2C1 0x29u +#define LDD_ivIndex_INT_SPI0 0x2Au +#define LDD_ivIndex_INT_SPI1 0x2Bu +#define LDD_ivIndex_INT_SPI2 0x2Cu +#define LDD_ivIndex_INT_CAN0_ORed_Message_buffer 0x2Du +#define LDD_ivIndex_INT_CAN0_Bus_Off 0x2Eu +#define LDD_ivIndex_INT_CAN0_Error 0x2Fu +#define LDD_ivIndex_INT_CAN0_Tx_Warning 0x30u +#define LDD_ivIndex_INT_CAN0_Rx_Warning 0x31u +#define LDD_ivIndex_INT_CAN0_Wake_Up 0x32u +#define LDD_ivIndex_INT_I2S0_Tx 0x33u +#define LDD_ivIndex_INT_I2S0_Rx 0x34u +#define LDD_ivIndex_INT_CAN1_ORed_Message_buffer 0x35u +#define LDD_ivIndex_INT_CAN1_Bus_Off 0x36u +#define LDD_ivIndex_INT_CAN1_Error 0x37u +#define LDD_ivIndex_INT_CAN1_Tx_Warning 0x38u +#define LDD_ivIndex_INT_CAN1_Rx_Warning 0x39u +#define LDD_ivIndex_INT_CAN1_Wake_Up 0x3Au +#define LDD_ivIndex_INT_Reserved59 0x3Bu +#define LDD_ivIndex_INT_UART0_LON 0x3Cu +#define LDD_ivIndex_INT_UART0_RX_TX 0x3Du +#define LDD_ivIndex_INT_UART0_ERR 0x3Eu +#define LDD_ivIndex_INT_UART1_RX_TX 0x3Fu +#define LDD_ivIndex_INT_UART1_ERR 0x40u +#define LDD_ivIndex_INT_UART2_RX_TX 0x41u +#define LDD_ivIndex_INT_UART2_ERR 0x42u +#define LDD_ivIndex_INT_UART3_RX_TX 0x43u +#define LDD_ivIndex_INT_UART3_ERR 0x44u +#define LDD_ivIndex_INT_UART4_RX_TX 0x45u +#define LDD_ivIndex_INT_UART4_ERR 0x46u +#define LDD_ivIndex_INT_Reserved71 0x47u +#define LDD_ivIndex_INT_Reserved72 0x48u +#define LDD_ivIndex_INT_ADC0 0x49u +#define LDD_ivIndex_INT_ADC1 0x4Au +#define LDD_ivIndex_INT_CMP0 0x4Bu +#define LDD_ivIndex_INT_CMP1 0x4Cu +#define LDD_ivIndex_INT_CMP2 0x4Du +#define LDD_ivIndex_INT_FTM0 0x4Eu +#define LDD_ivIndex_INT_FTM1 0x4Fu +#define LDD_ivIndex_INT_FTM2 0x50u +#define LDD_ivIndex_INT_CMT 0x51u +#define LDD_ivIndex_INT_RTC 0x52u +#define LDD_ivIndex_INT_RTC_Seconds 0x53u +#define LDD_ivIndex_INT_PIT0 0x54u +#define LDD_ivIndex_INT_PIT1 0x55u +#define LDD_ivIndex_INT_PIT2 0x56u +#define LDD_ivIndex_INT_PIT3 0x57u +#define LDD_ivIndex_INT_PDB0 0x58u +#define LDD_ivIndex_INT_USB0 0x59u +#define LDD_ivIndex_INT_USBDCD 0x5Au +#define LDD_ivIndex_INT_Reserved91 0x5Bu +#define LDD_ivIndex_INT_Reserved92 0x5Cu +#define LDD_ivIndex_INT_Reserved93 0x5Du +#define LDD_ivIndex_INT_Reserved94 0x5Eu +#define LDD_ivIndex_INT_Reserved95 0x5Fu +#define LDD_ivIndex_INT_SDHC 0x60u +#define LDD_ivIndex_INT_DAC0 0x61u +#define LDD_ivIndex_INT_Reserved98 0x62u +#define LDD_ivIndex_INT_TSI0 0x63u +#define LDD_ivIndex_INT_MCG 0x64u +#define LDD_ivIndex_INT_LPTimer 0x65u +#define LDD_ivIndex_INT_Reserved102 0x66u +#define LDD_ivIndex_INT_PORTA 0x67u +#define LDD_ivIndex_INT_PORTB 0x68u +#define LDD_ivIndex_INT_PORTC 0x69u +#define LDD_ivIndex_INT_PORTD 0x6Au +#define LDD_ivIndex_INT_PORTE 0x6Bu +#define LDD_ivIndex_INT_Reserved108 0x6Cu +#define LDD_ivIndex_INT_Reserved109 0x6Du +#define LDD_ivIndex_INT_SWI 0x6Eu +#define LDD_ivIndex_INT_Reserved111 0x6Fu +#define LDD_ivIndex_INT_Reserved112 0x70u +#define LDD_ivIndex_INT_Reserved113 0x71u +#define LDD_ivIndex_INT_Reserved114 0x72u +#define LDD_ivIndex_INT_Reserved115 0x73u +#define LDD_ivIndex_INT_Reserved116 0x74u +#define LDD_ivIndex_INT_Reserved117 0x75u +#define LDD_ivIndex_INT_Reserved118 0x76u +#define LDD_ivIndex_INT_Reserved119 0x77u + +#endif /* __PE_Types_H */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld new file mode 100644 index 0000000..dabf117 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld @@ -0,0 +1,223 @@ +/* ################################################################### */ +/*## +/*## This component module is generated by Processor Expert. Do not modify it. */ +/*## */ +/*## Filename : ProcessorExpert.ld */ +/*## */ +/*## Project : Landungsbruecke_KDS_v2.0.0 */ +/*## */ +/*## Processor : MK20DN512VLL10 */ +/*## */ +/*## Compiler : GNU C Compiler */ +/*## */ +/*## Date/Time : 2015-01-09, 16:27, # CodeGen: 0 */ +/*## */ +/*## Abstract : */ +/*## */ +/*## This file is used by the linker. It describes files to be linked, */ +/*## memory ranges, stack size, etc. For detailed description about linker */ +/*## command files see compiler documentation. This file is generated by default. */ +/*## You can switch off generation by setting the property "Generate linker file = no" */ +/*## in the "Build options" tab of the CPU component and then modify this file as needed. */ +/*## +/*## */ +/*## ###################################################################*/ + + +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20000000; /* end of m_data */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x00; /* required amount of heap */ +__stack_size = 0x0400; /* required amount of stack */ + +MEMORY { + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000001E0 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_20000000 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + m_cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into INTERNAL_FLASH */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into INTERNAL_FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + ___m_data_20000000_ROMStart = ___ROM_AT + SIZEOF(.data); + .m_data_20000000 : AT(___m_data_20000000_ROMStart) + { + . = ALIGN(4); + ___m_data_20000000_RAMStart = .; + *(.m_data_20000000) /* This is an User defined section */ + ___m_data_20000000_RAMEnd = .; + . = ALIGN(4); + } > m_data_20000000 + ___m_data_20000000_ROMSize = ___m_data_20000000_RAMEnd - ___m_data_20000000_RAMStart; + + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data) +SIZEOF(.m_data_20000000); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(___m_data_20000000_ROMStart); + LONG(___m_data_20000000_RAMStart); + LONG(___m_data_20000000_ROMSize); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + __HeapBase = .; + . = . + __heap_size; + __HeapLimit = .; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c new file mode 100644 index 0000000..862de15 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Rx1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Rx1 +** Buffer Size : 1 +** Contents : +** Clear - void Rx1_Clear(void); +** Put - byte Rx1_Put(Rx1_ElementType elem); +** Get - byte Rx1_Get(Rx1_ElementType *elemP); +** NofElements - Rx1_BufSizeType Rx1_NofElements(void); +** NofFreeElements - Rx1_BufSizeType Rx1_NofFreeElements(void); +** Init - void Rx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Rx1.c +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Rx1_module Rx1 module documentation +** @{ +*/ + +/* MODULE Rx1. */ + +#include "Rx1.h" + +#if Rx1_IS_REENTRANT + #define Rx1_DEFINE_CRITICAL() CS1_CriticalVariable() + #define Rx1_ENTER_CRITICAL() CS1_EnterCritical() + #define Rx1_EXIT_CRITICAL() CS1_ExitCritical() +#else + #define Rx1_DEFINE_CRITICAL() /* nothing */ + #define Rx1_ENTER_CRITICAL() /* nothing */ + #define Rx1_EXIT_CRITICAL() /* nothing */ +#endif +static Rx1_ElementType Rx1_buffer[Rx1_BUF_SIZE]; /* ring buffer */ +static Rx1_BufSizeType Rx1_inIdx; /* input index */ +static Rx1_BufSizeType Rx1_outIdx; /* output index */ +static Rx1_BufSizeType Rx1_inSize; /* size data in buffer */ +/* +** =================================================================== +** Method : Rx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Rx1_Put(Rx1_ElementType elem) +{ + byte res = ERR_OK; + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + if(Rx1_inSize==Rx1_BUF_SIZE) { + res = ERR_TXFULL; + } else { + Rx1_buffer[Rx1_inIdx] = elem; + Rx1_inSize++; + Rx1_inIdx++; + if(Rx1_inIdx==Rx1_BUF_SIZE) { + Rx1_inIdx = 0; + } + } + Rx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Rx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Rx1_Get(Rx1_ElementType *elemP) +{ + byte res = ERR_OK; + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + if(Rx1_inSize==0) { + res = ERR_RXEMPTY; + } else { + *elemP = Rx1_buffer[Rx1_outIdx]; + Rx1_inSize--; + Rx1_outIdx++; + if(Rx1_outIdx==Rx1_BUF_SIZE) { + Rx1_outIdx = 0; + } + } + Rx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Rx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Rx1_BufSizeType Rx1_NofElements(void) +{ + return Rx1_inSize; +} + +/* +** =================================================================== +** Method : Rx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Rx1_BufSizeType Rx1_NofFreeElements(void) +{ + return (Rx1_BufSizeType)(Rx1_BUF_SIZE-Rx1_inSize); +} + +/* +** =================================================================== +** Method : Rx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Rx1_Init(void) +{ + Rx1_inIdx = 0; + Rx1_outIdx = 0; + Rx1_inSize = 0; +} + +/* +** =================================================================== +** Method : Rx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Rx1_Clear(void) +{ + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + Rx1_Init(); + Rx1_EXIT_CRITICAL(); +} + +/* END Rx1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h new file mode 100644 index 0000000..f39cdee --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h @@ -0,0 +1,167 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Rx1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Rx1 +** Buffer Size : 1 +** Contents : +** Clear - void Rx1_Clear(void); +** Put - byte Rx1_Put(Rx1_ElementType elem); +** Get - byte Rx1_Get(Rx1_ElementType *elemP); +** NofElements - Rx1_BufSizeType Rx1_NofElements(void); +** NofFreeElements - Rx1_BufSizeType Rx1_NofFreeElements(void); +** Init - void Rx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Rx1.h +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Rx1_module Rx1 module documentation +** @{ +*/ + +#ifndef __Rx1_H +#define __Rx1_H + +/* MODULE Rx1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "CS1.h" + +//#include "Cpu.h" + + +#define Rx1_BUF_SIZE 64 /* number of elements in the buffer */ +#define Rx1_ELEM_SIZE 1 /* size of a single element in bytes */ + #define Rx1_IS_REENTRANT 0 /* 0: Critical section NOT used for accessing shared data, 1 otherwise */ +#if Rx1_ELEM_SIZE==1 + typedef uint8 Rx1_ElementType; /* type of single element */ +#elif Rx1_ELEM_SIZE==2 + typedef uint16 Rx1_ElementType; /* type of single element */ +#elif Rx1_ELEM_SIZE==4 + typedef uint32 Rx1_ElementType; /* type of single element */ +#else + #error "illegal element type size in properties" +#endif +#if Rx1_BUF_SIZE<=256 + typedef uint8 Rx1_BufSizeType; /* up to 256 elements (index 0x00..0xFF) */ +#else + typedef uint16 Rx1_BufSizeType; /* more than 256 elements, up to 2^16 */ +#endif + +byte Rx1_Put(Rx1_ElementType elem); +/* +** =================================================================== +** Method : Rx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte Rx1_Get(Rx1_ElementType *elemP); +/* +** =================================================================== +** Method : Rx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ + +Rx1_BufSizeType Rx1_NofElements(void); +/* +** =================================================================== +** Method : Rx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Rx1_Init(void); +/* +** =================================================================== +** Method : Rx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +Rx1_BufSizeType Rx1_NofFreeElements(void); +/* +** =================================================================== +** Method : Rx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Rx1_Clear(void); +/* +** =================================================================== +** Method : Rx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Rx1. */ + +#endif +/* ifndef __Rx1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c new file mode 100644 index 0000000..b4ba188 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Tx1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Tx1 +** Buffer Size : 1 +** Contents : +** Clear - void Tx1_Clear(void); +** Put - byte Tx1_Put(Tx1_ElementType elem); +** Get - byte Tx1_Get(Tx1_ElementType *elemP); +** NofElements - Tx1_BufSizeType Tx1_NofElements(void); +** NofFreeElements - Tx1_BufSizeType Tx1_NofFreeElements(void); +** Init - void Tx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Tx1.c +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Tx1_module Tx1 module documentation +** @{ +*/ + +/* MODULE Tx1. */ + +#include "Tx1.h" + +#if Tx1_IS_REENTRANT + #define Tx1_DEFINE_CRITICAL() CS1_CriticalVariable() + #define Tx1_ENTER_CRITICAL() CS1_EnterCritical() + #define Tx1_EXIT_CRITICAL() CS1_ExitCritical() +#else + #define Tx1_DEFINE_CRITICAL() /* nothing */ + #define Tx1_ENTER_CRITICAL() /* nothing */ + #define Tx1_EXIT_CRITICAL() /* nothing */ +#endif +static Tx1_ElementType Tx1_buffer[Tx1_BUF_SIZE]; /* ring buffer */ +static Tx1_BufSizeType Tx1_inIdx; /* input index */ +static Tx1_BufSizeType Tx1_outIdx; /* output index */ +static Tx1_BufSizeType Tx1_inSize; /* size data in buffer */ +/* +** =================================================================== +** Method : Tx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Tx1_Put(Tx1_ElementType elem) +{ + byte res = ERR_OK; + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + if(Tx1_inSize==Tx1_BUF_SIZE) { + res = ERR_TXFULL; + } else { + Tx1_buffer[Tx1_inIdx] = elem; + Tx1_inSize++; + Tx1_inIdx++; + if(Tx1_inIdx==Tx1_BUF_SIZE) { + Tx1_inIdx = 0; + } + } + Tx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Tx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Tx1_Get(Tx1_ElementType *elemP) +{ + byte res = ERR_OK; + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + if(Tx1_inSize==0) { + res = ERR_RXEMPTY; + } else { + *elemP = Tx1_buffer[Tx1_outIdx]; + Tx1_inSize--; + Tx1_outIdx++; + if(Tx1_outIdx==Tx1_BUF_SIZE) { + Tx1_outIdx = 0; + } + } + Tx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Tx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Tx1_BufSizeType Tx1_NofElements(void) +{ + return Tx1_inSize; +} + +/* +** =================================================================== +** Method : Tx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Tx1_BufSizeType Tx1_NofFreeElements(void) +{ + return (Tx1_BufSizeType)(Tx1_BUF_SIZE-Tx1_inSize); +} + +/* +** =================================================================== +** Method : Tx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Tx1_Init(void) +{ + Tx1_inIdx = 0; + Tx1_outIdx = 0; + Tx1_inSize = 0; +} + +/* +** =================================================================== +** Method : Tx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Tx1_Clear(void) +{ + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + Tx1_Init(); + Tx1_EXIT_CRITICAL(); +} + +/* END Tx1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h new file mode 100644 index 0000000..a5a2a0e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h @@ -0,0 +1,167 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Tx1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Tx1 +** Buffer Size : 1 +** Contents : +** Clear - void Tx1_Clear(void); +** Put - byte Tx1_Put(Tx1_ElementType elem); +** Get - byte Tx1_Get(Tx1_ElementType *elemP); +** NofElements - Tx1_BufSizeType Tx1_NofElements(void); +** NofFreeElements - Tx1_BufSizeType Tx1_NofFreeElements(void); +** Init - void Tx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Tx1.h +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Tx1_module Tx1 module documentation +** @{ +*/ + +#ifndef __Tx1_H +#define __Tx1_H + +/* MODULE Tx1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "CS1.h" + +//#include "Cpu.h" + + +#define Tx1_BUF_SIZE 64 /* number of elements in the buffer */ +#define Tx1_ELEM_SIZE 1 /* size of a single element in bytes */ + #define Tx1_IS_REENTRANT 0 /* 0: Critical section NOT used for accessing shared data, 1 otherwise */ +#if Tx1_ELEM_SIZE==1 + typedef uint8 Tx1_ElementType; /* type of single element */ +#elif Tx1_ELEM_SIZE==2 + typedef uint16 Tx1_ElementType; /* type of single element */ +#elif Tx1_ELEM_SIZE==4 + typedef uint32 Tx1_ElementType; /* type of single element */ +#else + #error "illegal element type size in properties" +#endif +#if Tx1_BUF_SIZE<=256 + typedef uint8 Tx1_BufSizeType; /* up to 256 elements (index 0x00..0xFF) */ +#else + typedef uint16 Tx1_BufSizeType; /* more than 256 elements, up to 2^16 */ +#endif + +byte Tx1_Put(Tx1_ElementType elem); +/* +** =================================================================== +** Method : Tx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte Tx1_Get(Tx1_ElementType *elemP); +/* +** =================================================================== +** Method : Tx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ + +Tx1_BufSizeType Tx1_NofElements(void); +/* +** =================================================================== +** Method : Tx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Tx1_Init(void); +/* +** =================================================================== +** Method : Tx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +Tx1_BufSizeType Tx1_NofFreeElements(void); +/* +** =================================================================== +** Method : Tx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Tx1_Clear(void); +/* +** =================================================================== +** Method : Tx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Tx1. */ + +#endif +/* ifndef __Tx1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c new file mode 100644 index 0000000..7c61997 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c @@ -0,0 +1,396 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB0.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : Init_USB_OTG +** Version : Component 01.004, Driver 01.04, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +** Settings : +** Component name : USB0 +** Device : USB0 +** Settings : +** Clock gate : Enabled +** Clock settings : +** Clock divider : +** Clock divider source : PLL/FLL clock +** Clock divider input frequency : 96 MHz +** Clock divider fraction : multiply by 1 +** Clock divider divisor : divide by 2 +** Module clock source : Clock divider output +** Module clock frequency : 48 MHz +** Pull-up/pull-down settings : +** Weak pulldowns : Enabled +** Pull-up/pull-down control : Mode dependent +** D+ pull-up : Disabled +** D+ pull-down : Disabled +** D- pull-down : Disabled +** D+ pull-up for non-OTG mode : Disabled +** Endpoints : +** EP0 : Disabled +** Direct low speed : Disabled +** Retry : Enabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP1 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP2 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP3 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP4 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP5 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP6 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP7 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP8 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP9 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP10 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP11 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP12 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP13 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP14 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP15 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** Buffer descriptor table : +** External object declaration : extern uint8 g_Mem[]; +** Address : ((uint32)&g_Mem[0]) +** SOF threshold : 0 +** Pins : +** Alternate clock source : Disabled +** SOF output : Disabled +** Data plus : Enabled +** Pin : USB0_DP +** Pin signal : +** Data minus : Enabled +** Pin : USB0_DM +** Pin signal : +** Interrupts : +** USB : +** Interrupt : INT_USB0 +** Interrupt request : Disabled +** Interrupt priority : 0 (Highest) +** ISR Name : USB_ISR +** Stall : Enabled +** Attach : Enabled +** Resume : Enabled +** Sleep : Enabled +** Token OK : Enabled +** Start of frame : Enabled +** Error interrupt : Enabled +** USB reset : Enabled +** Asynchronous Resume interrupt : Enabled +** Error interrupts : +** Bit stuff error : Disabled +** DMA error : Disabled +** Bus turnaround timeout : Disabled +** Data length error : Disabled +** CRC16 error : Disabled +** CRC5 or EOF : Disabled +** PID error : Disabled +** OTG interrupts : +** ID pin changed : Disabled +** 1 ms interrupt : Disabled +** Line stage change : Disabled +** Session valid : Disabled +** "B" session end : Disabled +** "A" bus valid : Disabled +** Initialization : +** Mode : Device +** USB transceiver suspend state : Enabled +** Call Init method : yes +** Contents : +** Init - void USB0_Init(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file USB0.c +** @version 01.04 +** @brief +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +*/ +/*! +** @addtogroup USB0_module USB0 module documentation +** @{ +*/ + +/* MODULE USB0. */ + +#include "USB0.h" + /* Including shared modules, which are used in the whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "hal/derivative.h" + + +/* +** =================================================================== +** Method : USB0_Init (component Init_USB_OTG) +** Description : +** This method initializes registers of the USB_OTG module +** according to the Peripheral Initialization settings. +** Call this method in user code to initialize the module. By +** default, the method is called by PE automatically; see "Call +** Init method" property of the component for more details. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +extern uint8 g_Mem[]; +void USB0_Init(void) +{ + /* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ + SIM_CLKDIV2 = (uint32)((SIM_CLKDIV2 & (uint32)~(uint32)( + SIM_CLKDIV2_USBDIV(0x06) | + SIM_CLKDIV2_USBFRAC_MASK + )) | (uint32)( + SIM_CLKDIV2_USBDIV(0x01) + )); + /* SIM_SOPT2: USBSRC=1 */ + SIM_SOPT2 |= SIM_SOPT2_USBSRC_MASK; + /* SIM_SCGC4: USBOTG=1 */ + SIM_SCGC4 |= SIM_SCGC4_USBOTG_MASK; + /* USB0_CTL: ODDRST=1 */ + USB0_CTL |= USB_CTL_ODDRST_MASK; + /* USB0_USBCTRL: SUSP=1,PDE=1,??=0,??=0,??=0,??=0,??=0,??=0 */ + USB0_USBCTRL = (USB_USBCTRL_SUSP_MASK | USB_USBCTRL_PDE_MASK); + /* USB0_OTGISTAT: IDCHG=1,ONEMSEC=1,LINE_STATE_CHG=1,??=1,SESSVLDCHG=1,B_SESS_CHG=1,??=1,AVBUSCHG=1 */ + USB0_OTGISTAT = USB_OTGISTAT_IDCHG_MASK | + USB_OTGISTAT_ONEMSEC_MASK | + USB_OTGISTAT_LINE_STATE_CHG_MASK | + USB_OTGISTAT_SESSVLDCHG_MASK | + USB_OTGISTAT_B_SESS_CHG_MASK | + USB_OTGISTAT_AVBUSCHG_MASK | + 0x12U; + /* USB0_ISTAT: STALL=1,ATTACH=1,RESUME=1,SLEEP=1,TOKDNE=1,SOFTOK=1,ERROR=1,USBRST=1 */ + USB0_ISTAT = USB_ISTAT_STALL_MASK | + USB_ISTAT_ATTACH_MASK | + USB_ISTAT_RESUME_MASK | + USB_ISTAT_SLEEP_MASK | + USB_ISTAT_TOKDNE_MASK | + USB_ISTAT_SOFTOK_MASK | + USB_ISTAT_ERROR_MASK | + USB_ISTAT_USBRST_MASK; + /* USB0_ERRSTAT: BTSERR=1,??=1,DMAERR=1,BTOERR=1,DFN8=1,CRC16=1,CRC5EOF=1,PIDERR=1 */ + USB0_ERRSTAT = USB_ERRSTAT_BTSERR_MASK | + USB_ERRSTAT_DMAERR_MASK | + USB_ERRSTAT_BTOERR_MASK | + USB_ERRSTAT_DFN8_MASK | + USB_ERRSTAT_CRC16_MASK | + USB_ERRSTAT_CRC5EOF_MASK | + USB_ERRSTAT_PIDERR_MASK | + 0x40U; + /* USB0_INTEN: STALLEN=1,ATTACHEN=1,RESUMEEN=1,SLEEPEN=1,TOKDNEEN=1,SOFTOKEN=1,ERROREN=1,USBRSTEN=1 */ + USB0_INTEN = USB_INTEN_STALLEN_MASK | + USB_INTEN_ATTACHEN_MASK | + USB_INTEN_RESUMEEN_MASK | + USB_INTEN_SLEEPEN_MASK | + USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SOFTOKEN_MASK | + USB_INTEN_ERROREN_MASK | + USB_INTEN_USBRSTEN_MASK; + /* USB0_ERREN: BTSERREN=0,??=0,DMAERREN=0,BTOERREN=0,DFN8EN=0,CRC16EN=0,CRC5EOFEN=0,PIDERREN=0 */ + USB0_ERREN = 0x00U; + /* USB0_USBTRC0: USBRESET=0,??=1,USBRESMEN=1,??=0,??=0,??=0,SYNC_DET=0,USB_RESUME_INT=0 */ + USB0_USBTRC0 = (USB_USBTRC0_USBRESMEN_MASK | 0x40U); + /* USB0_OTGICR: IDEN=0,ONEMSECEN=0,LINESTATEEN=0,??=0,SESSVLDEN=0,BSESSEN=0,??=0,AVBUSEN=0 */ + USB0_OTGICR = 0x00U; + /* USB0_ADDR: LSEN=0,ADDR=0 */ + USB0_ADDR = USB_ADDR_ADDR(0x00); + /* USB0_ENDPT0: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT0 = 0x00U; + /* USB0_ENDPT1: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT1 = 0x00U; + /* USB0_ENDPT2: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT2 = 0x00U; + /* USB0_ENDPT3: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT3 = 0x00U; + /* USB0_ENDPT4: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT4 = 0x00U; + /* USB0_ENDPT5: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT5 = 0x00U; + /* USB0_ENDPT6: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT6 = 0x00U; + /* USB0_ENDPT7: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT7 = 0x00U; + /* USB0_ENDPT8: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT8 = 0x00U; + /* USB0_ENDPT9: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT9 = 0x00U; + /* USB0_ENDPT10: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT10 = 0x00U; + /* USB0_ENDPT11: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT11 = 0x00U; + /* USB0_ENDPT12: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT12 = 0x00U; + /* USB0_ENDPT13: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT13 = 0x00U; + /* USB0_ENDPT14: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT14 = 0x00U; + /* USB0_ENDPT15: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT15 = 0x00U; + USB0_BDTPAGE1 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x08) & 0xFEU); + USB0_BDTPAGE2 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x10) & 0xFFU); + USB0_BDTPAGE3 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x18) & 0xFFU); + /* USB0_SOFTHLD: CNT=0 */ + USB0_SOFTHLD = USB_SOFTHLD_CNT(0x00); + /* USB0_OTGCTL: DPHIGH=0,??=0,DPLOW=0,DMLOW=0,??=0,OTGEN=0,??=0,??=0 */ + USB0_OTGCTL = 0x00U; + /* USB0_CONTROL: ??=0,??=0,??=0,DPPULLUPNONOTG=0,??=0,??=0,??=0,??=0 */ + USB0_CONTROL = 0x00U; + /* USB0_CTL: TXSUSPENDTOKENBUSY=0,HOSTMODEEN=0,ODDRST=0,USBENSOFEN=1 */ + USB0_CTL = (uint8)((USB0_CTL & (uint8)~(uint8)( + USB_CTL_TXSUSPENDTOKENBUSY_MASK | + USB_CTL_HOSTMODEEN_MASK | + USB_CTL_ODDRST_MASK + )) | (uint8)( + USB_CTL_USBENSOFEN_MASK + )); +} + +/* +** ################################################################### +** +** The interrupt service routine(s) must be implemented +** by user in one of the following user modules. +** +** If the "Generate ISR" option is enabled, Processor Expert generates +** ISR templates in the CPU event module. +** +** User modules: +** main.c +** Events.c +** +** ################################################################### +PE_ISR(USB_ISR) +{ +// NOTE: The routine should include actions to clear the appropriate +// interrupt flags. +// +} +*/ + + +/* END USB0. */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h new file mode 100644 index 0000000..269de05 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h @@ -0,0 +1,279 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB0.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : Init_USB_OTG +** Version : Component 01.004, Driver 01.04, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +** Settings : +** Component name : USB0 +** Device : USB0 +** Settings : +** Clock gate : Enabled +** Clock settings : +** Clock divider : +** Clock divider source : PLL/FLL clock +** Clock divider input frequency : 96 MHz +** Clock divider fraction : multiply by 1 +** Clock divider divisor : divide by 2 +** Module clock source : Clock divider output +** Module clock frequency : 48 MHz +** Pull-up/pull-down settings : +** Weak pulldowns : Enabled +** Pull-up/pull-down control : Mode dependent +** D+ pull-up : Disabled +** D+ pull-down : Disabled +** D- pull-down : Disabled +** D+ pull-up for non-OTG mode : Disabled +** Endpoints : +** EP0 : Disabled +** Direct low speed : Disabled +** Retry : Enabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP1 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP2 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP3 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP4 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP5 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP6 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP7 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP8 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP9 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP10 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP11 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP12 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP13 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP14 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP15 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** Buffer descriptor table : +** External object declaration : extern uint8 g_Mem[]; +** Address : ((uint32)&g_Mem[0]) +** SOF threshold : 0 +** Pins : +** Alternate clock source : Disabled +** SOF output : Disabled +** Data plus : Enabled +** Pin : USB0_DP +** Pin signal : +** Data minus : Enabled +** Pin : USB0_DM +** Pin signal : +** Interrupts : +** USB : +** Interrupt : INT_USB0 +** Interrupt request : Disabled +** Interrupt priority : 0 (Highest) +** ISR Name : USB_ISR +** Stall : Enabled +** Attach : Enabled +** Resume : Enabled +** Sleep : Enabled +** Token OK : Enabled +** Start of frame : Enabled +** Error interrupt : Enabled +** USB reset : Enabled +** Asynchronous Resume interrupt : Enabled +** Error interrupts : +** Bit stuff error : Disabled +** DMA error : Disabled +** Bus turnaround timeout : Disabled +** Data length error : Disabled +** CRC16 error : Disabled +** CRC5 or EOF : Disabled +** PID error : Disabled +** OTG interrupts : +** ID pin changed : Disabled +** 1 ms interrupt : Disabled +** Line stage change : Disabled +** Session valid : Disabled +** "B" session end : Disabled +** "A" bus valid : Disabled +** Initialization : +** Mode : Device +** USB transceiver suspend state : Enabled +** Call Init method : yes +** Contents : +** Init - void USB0_Init(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file USB0.h +** @version 01.04 +** @brief +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +*/ +/*! +** @addtogroup USB0_module USB0 module documentation +** @{ +*/ + +#ifndef USB0_H_ +#define USB0_H_ + +/* MODULE USB0. */ + +/* Including shared modules, which are used in the whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +//#include "Cpu.h" + +/* Peripheral base address parameter */ +#define USB0_DEVICE USB0_BASE_PTR + + +/* +** =================================================================== +** Method : USB0_Init (component Init_USB_OTG) +** Description : +** This method initializes registers of the USB_OTG module +** according to the Peripheral Initialization settings. +** Call this method in user code to initialize the module. By +** default, the method is called by PE automatically; see "Call +** Init method" property of the component for more details. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void USB0_Init(void); +/* +** =================================================================== +** The interrupt service routine must be implemented by user in one +** of the user modules (see USB0.c file for more information). +** =================================================================== +*/ +//PE_ISR(USB_ISR); +void __attribute((interrupt)) USB_ISR(void); + + +/* END USB0. */ +#endif /* #ifndef __USB0_H_ */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c new file mode 100644 index 0000000..962305f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c @@ -0,0 +1,112 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_Stack +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a wrapper to the FSL USB Stack. +** Settings : +** Component name : USB1 +** Freescale USB Stack Version : v4.1.1 +** USB : Init_USB_OTG_VAR0 +** Device Class : CDC Device +** CDC Device : Enabled +** CDCDevice : FSL_USB_CDC_Device +** HID Keyboard Device : Disabled +** MSD Host : Disabled +** Call Init Method : yes +** Contents : +** Init - byte USB1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013-2014. +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file USB1.c +** @version 01.00 +** @brief +** This component implements a wrapper to the FSL USB Stack. +*/ +/*! +** @addtogroup USB1_module USB1 module documentation +** @{ +*/ + +/* MODULE USB1. */ + +#include "USB1.h" +#include "hal/derivative.h" /* include peripheral declarations */ + +/* +** =================================================================== +** Method : USB1_usb_int_dis (component FSL_USB_Stack) +** +** Description : +** Disables USB interrupts (if supported) +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void USB1_usb_int_dis(void) +{ + /* Kinetis K20D72 */ + NVICISER1 = (1<<9); /* Disable interrupts from USB module (Interrupt Clear-Enable Register) */ +} + +/* +** =================================================================== +** Method : USB1_usb_int_en (component FSL_USB_Stack) +** +** Description : +** Enables USB interrupts (if supported). +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void USB1_usb_int_en(void) +{ + /* Kinetis K20D72 */ + NVICICPR2 = (1<<9); /* Clear any pending interrupts on USB (Interrupt Clear-Pending Register) */ + NVICISER2 = (1<<9); /* Enable interrupts from USB module (Interrupt Set-Enable Register) */ +} + +/* +** =================================================================== +** Method : USB1_Init (component FSL_USB_Stack) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ +byte USB1_Init(void) +{ + byte err; + + /* Initialize the USB interface */ + err = CDC1_Init(); + if(err != ERR_OK) { + /* Error initializing USB Class */ + return ERR_FAILED; + } + USB1_usb_int_en(); + return ERR_OK; +} + +/* END USB1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h new file mode 100644 index 0000000..dea3004 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h @@ -0,0 +1,132 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_Stack +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a wrapper to the FSL USB Stack. +** Settings : +** Component name : USB1 +** Freescale USB Stack Version : v4.1.1 +** USB : Init_USB_OTG_VAR0 +** Device Class : CDC Device +** CDC Device : Enabled +** CDCDevice : FSL_USB_CDC_Device +** HID Keyboard Device : Disabled +** MSD Host : Disabled +** Call Init Method : yes +** Contents : +** Init - byte USB1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013-2014. +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file USB1.h +** @version 01.00 +** @brief +** This component implements a wrapper to the FSL USB Stack. +*/ +/*! +** @addtogroup USB1_module USB1 module documentation +** @{ +*/ + +#ifndef __USB1_H +#define __USB1_H + +/* MODULE USB1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "USB0.h" +#include "CDC1.h" +#include /* for size_t */ + +/* Interfaces/wrappers to the CDC device class, needed by FSShell: */ +#define USB1_SendString(str) CDC1_SendString(str) +#define USB1_RecvChar(chr) CDC1_GetChar(chr) +#define USB1_SendChar(chr) CDC1_SendChar(chr) +#define USB1_GetCharsInRxBuf() CDC1_GetCharsInRxBuf() + +//#include "Cpu.h" + + +#ifndef __BWUserType_USB1_TComData +#define __BWUserType_USB1_TComData + typedef byte USB1_TComData ; /* User type for communication data type. */ +#endif + +/* + DATA_BUFF_SIZE should be greater than or equal to the endpoint buffer size, + otherwise there will be data loss. For MC9S08JS16, maximum DATA_BUFF_SIZE + supported is 16 Bytes +*/ +#define USB1_DATA_BUFF_SIZE 64 /* data buffer size as specified in the properties */ + +#define USB1_USB_ERR_SEND 1 /* Error while sending */ +#define USB1_USB_ERR_BUSOFF 2 /* Bus not ready */ +#define USB1_USB_ERR_INIT 3 /* USB initialization error */ +#define USB1_USB_ERR_TX_CHAR 4 /* Error sending character */ +#define USB1_USB_ERR_TX_STRING 5 /* Error sending string */ +#define USB1_USB_ERR_CHECKED_TXFULL 6 /* Error during sending a checked block */ +#define USB1_USB_ERR_RECEIVE 7 /* Error while starting a receive transaction */ + +byte USB1_Init(void); +/* +** =================================================================== +** Method : USB1_Init (component FSL_USB_Stack) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ + +void USB1_usb_int_dis(void); +/* +** =================================================================== +** Method : USB1_usb_int_dis (component FSL_USB_Stack) +** +** Description : +** Disables USB interrupts (if supported) +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void USB1_usb_int_en(void); +/* +** =================================================================== +** Method : USB1_usb_int_en (component FSL_USB_Stack) +** +** Description : +** Enables USB interrupts (if supported). +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END USB1. */ + +#endif +/* ifndef __USB1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h new file mode 100644 index 0000000..e2e8dbf --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h @@ -0,0 +1,211 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file USB_Config.h + * + * @author B14088 + * + * @version + * + * @date Oct 31, 2010 + * + * @brief + *****************************************************************************/ + +#ifndef USB_CONFIG_H_ +#define USB_CONFIG_H_ + +/*****************************************************************************/ +/* Includes Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Typedef Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Function's Prototypes */ +/*****************************************************************************/ +/* CDC class services */ +extern void USB_Class_CDC_Service_Dic_Bulk_In (PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_Class_CDC_Service_Dic_Bulk_Out(PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_Class_CDC_Service_Cic_Notify(PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_NULL_CALLBACK (PTR_USB_DEV_EVENT_STRUCT event); + +/*****************************************************************************/ +/* Defines & Macros Section */ +/*****************************************************************************/ + +#define REMOTE_WAKEUP_SUPPORT (TRUE) + +/* CDC specific configuration parameters */ +#define DATA_CLASS_SUPPORT (TRUE) +#define CIC_NOTIF_ELEM_SUPPORT (TRUE) /* Mandatory */ +#define DIC_ISOCHRONOUS_SETTING (FALSE) +#define IMPLEMENT_QUEUING (FALSE) + +/* Hardware components configuration */ +#define USB_HW_VREG_EN TRUE +#define USB_HW_PU_EN TRUE + +/* Event callbacks assignation */ +#define USB_EP0_CALLBACK USB_Control_Service + +#if DIC_ISOCHRONOUS_SETTING +#define USB_EP1_CALLBACK USB_Class_CDC_Service_Dic_Iso_In +#define USB_EP2_CALLBACK USB_Class_CDC_Service_Dic_Iso_Out +#else +#define USB_EP1_CALLBACK USB_Class_CDC_Service_Dic_Bulk_In +#define USB_EP2_CALLBACK USB_Class_CDC_Service_Dic_Bulk_Out +#endif + +#define USB_EP3_CALLBACK USB_Class_CDC_Service_Cic_Notify +#define USB_EP4_CALLBACK USB_NULL_CALLBACK +#define USB_EP5_CALLBACK USB_NULL_CALLBACK +#define USB_EP6_CALLBACK USB_NULL_CALLBACK +#define USB_EP7_CALLBACK USB_NULL_CALLBACK +#define USB_EP8_CALLBACK USB_NULL_CALLBACK +#define USB_EP9_CALLBACK USB_NULL_CALLBACK +#define USB_EP10_CALLBACK USB_NULL_CALLBACK +#define USB_EP11_CALLBACK USB_NULL_CALLBACK +#define USB_EP12_CALLBACK USB_NULL_CALLBACK +#define USB_EP13_CALLBACK USB_NULL_CALLBACK +#define USB_EP14_CALLBACK USB_NULL_CALLBACK +#define USB_EP15_CALLBACK USB_NULL_CALLBACK + +#define USB_BUS_RESET_CALLBACK USB_Reset_Service +#define USB_SUSPEND_CALLBACK USB_Suspend_Service +#define USB_SOF_CALLBACK USB_Sof_Service +#define USB_RESUME_CALLBACK USB_Resume_Service +#define USB_SLEEP_CALLBACK USB_Suspend_Service +#define USB_SPEED_DETECTION_CALLBACK USB_NULL_CALLBACK +#define USB_ERROR_CALLBACK USB_Error_Service +#define USB_STALL_CALLBACK USB_Stall_Service + +/* Endpoints configuration */ +#define USB_EP0_ENABLE TRUE +#define USB_EP0_DIR EP_CTRL +#define USB_EP0_HSHK TRUE +#define USB_EP0_SIZE 32 + +#if DIC_ISOCHRONOUS_SETTING +#define USB_EP1_ENABLE TRUE +#define USB_EP1_DIR USB_DIR_IN +#define USB_EP1_HSHK FALSE +#define USB_EP1_SIZE 64 + +#define USB_EP2_ENABLE TRUE +#define USB_EP2_DIR EP_OUT +#define USB_EP2_HSHK FALSE +#define USB_EP2_SIZE 64 +#else +#define USB_EP1_ENABLE TRUE +#define USB_EP1_DIR EP_IN +#define USB_EP1_HSHK TRUE +#define USB_EP1_SIZE 32 + +#define USB_EP2_ENABLE TRUE +#define USB_EP2_DIR EP_OUT +#define USB_EP2_HSHK TRUE +#define USB_EP2_SIZE 32 +#endif + +#define USB_EP3_ENABLE TRUE +#define USB_EP3_DIR EP_IN +#define USB_EP3_HSHK TRUE +#define USB_EP3_SIZE 32 + +#define USB_EP4_ENABLE FALSE +#define USB_EP4_DIR NA +#define USB_EP4_HSHK TRUE +#define USB_EP4_SIZE 0 + +#define USB_EP5_ENABLE FALSE +#define USB_EP5_DIR NA +#define USB_EP5_HSHK TRUE +#define USB_EP5_SIZE 0 + +#define USB_EP6_ENABLE FALSE +#define USB_EP6_DIR NA +#define USB_EP6_HSHK TRUE +#define USB_EP6_SIZE 0 + +#define USB_EP7_ENABLE FALSE +#define USB_EP7_DIR NA +#define USB_EP7_HSHK TRUE +#define USB_EP7_SIZE 0 + +#define USB_EP8_ENABLE FALSE +#define USB_EP8_DIR NA +#define USB_EP8_HSHK TRUE +#define USB_EP8_SIZE 0 + +#define USB_EP9_ENABLE FALSE +#define USB_EP9_DIR NA +#define USB_EP9_HSHK TRUE +#define USB_EP9_SIZE 0 + +#define USB_EP10_ENABLE FALSE +#define USB_EP10_DIR NA +#define USB_EP10_HSHK TRUE +#define USB_EP10_SIZE 0 + +#define USB_EP11_ENABLE FALSE +#define USB_EP11_DIR NA +#define USB_EP11_HSHK TRUE +#define USB_EP11_SIZE 0 + +#define USB_EP12_ENABLE FALSE +#define USB_EP12_DIR NA +#define USB_EP12_HSHK TRUE +#define USB_EP12_SIZE 0 + +#define USB_EP13_ENABLE FALSE +#define USB_EP13_DIR NA +#define USB_EP13_HSHK TRUE +#define USB_EP13_SIZE 0 + +#define USB_EP14_ENABLE FALSE +#define USB_EP14_DIR NA +#define USB_EP14_HSHK TRUE +#define USB_EP14_SIZE 0 + +#define USB_EP15_ENABLE FALSE +#define USB_EP15_DIR NA +#define USB_EP15_HSHK TRUE +#define USB_EP15_SIZE 0 + +/*****************************************************************************/ +/* Extern Variables Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Function Prototypes Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ + +#endif /* USB_CONFIG_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h new file mode 100644 index 0000000..4512365 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h @@ -0,0 +1,64 @@ +/******************************************************/ +/** +* @file hidef.h +* Machine/compiler dependent declarations. +*/ +/*---------------------------------------------------- + Copyright (c) Freescale DevTech + All rights reserved + Do not modify! + *****************************************************/ + +#ifndef _H_HIDEF_ +#define _H_HIDEF_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef EnableInterrupts + #ifndef DisableInterrupts + + #if defined(__CWCC__) + #pragma gcc_extensions on + + /**** Version for ColFire V1 */ + #include + #include "types.h" + + /*!< Macro to enable all interrupts. */ + #define EnableInterrupts asm ("CPSIE i") + + /*!< Macro to disable all interrupts. */ + #define DisableInterrupts asm ("CPSID i") + + #elif defined(__IAR_SYSTEMS_ICC__) + #include + + #define EnableInterrupts; __enable_interrupt() + #define DisableInterrupts __disable_interrupt() + + #elif defined (__CC_ARM) + #define EnableInterrupts __enable_irq() + #define DisableInterrupts __disable_irq() + + #elif defined (__GNUC__) + #include + #include "types.h" + + /*!< Macro to enable all interrupts. */ + #define EnableInterrupts asm ("CPSIE i") + + /*!< Macro to disable all interrupts. */ + #define DisableInterrupts asm ("CPSID i") + #endif + + #ifdef __cplusplus + } + #endif + + #endif + #endif /* #ifdef DisableInterrupts */ +#endif/* #ifdef EnableInterrupts */ +/*****************************************************/ +/* end hidef.h */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h new file mode 100644 index 0000000..f119a4b --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h @@ -0,0 +1,180 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file types.h + * + * @author + * + * @version + * + * @date + * + * @brief The file contains definitions of datatypes. + * + *****************************************************************************/ + + +#ifndef _TYPES_H +#define _TYPES_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define LSB(a) ((a)._byte.byte0) +#define MSB(a) ((a)._byte.byte1) + +#define LOWER_LSB(a) ((a)._byte.byte0) +#define LOWER_MSB(a) ((a)._byte.byte1) +#define UPPER_LSB(a) ((a)._byte.byte2) +#define UPPER_MSB(a) ((a)._byte.byte3) + +#define _PTR_ * +#define _CODE_PTR_ * + +#ifndef TRUE +#define FALSE 0 +#define TRUE 1 +#endif + +#define BYTESWAP16(x) (uint_16)((((x) & 0xFF00) >> 0x8) | (((x) & 0xFF) << 0x8)) +#define BYTESWAP32(val) (uint_32)((BYTESWAP16((uint_32)(val) & (uint_32)0xFFFF) << 0x10) | \ + (BYTESWAP16((uint_32)((val) >> 0x10)))) + +#ifdef CPU_LITTLE_ENDIAN /* << EST: defined by Processor Expert CPU.h for Kinetis devices */ + #ifndef LITTLE_ENDIAN /* might be defined already on the compiler command line? */ + #define LITTLE_ENDIAN + #endif +#endif + +#ifndef LITTLE_ENDIAN +#define ieee_htons(x) (uint_16)(x) +#define ieee_htonl(x) (uint_32)(x) +#define ieee_ntohs(x) (uint_16)(x) +#define ieee_ntohl(x) (uint_32)(x) +#else +#define ieee_htons(x) BYTESWAP16(x) +#define ieee_htonl(x) BYTESWAP32(x) +#define ieee_ntohs(x) BYTESWAP16(x) +#define ieee_ntohl(x) BYTESWAP32(x) +#endif + +#ifndef UNUSED + #define UNUSED(x) (void)(x); +#endif +/****************************************************************************** + * Types + *****************************************************************************/ +typedef void _PTR_ pointer; /* Machine representation of a pointer */ +typedef unsigned char uint_8; /* 8-bit*/ +typedef signed char int_8; /* 8-bit*/ + +typedef unsigned short uint_16; /* 16-bit*/ +typedef signed short int_16; /* 16-bit*/ + +typedef unsigned long uint_32; /* 32-bit*/ +typedef signed long int_32; /* 32-bit*/ + +typedef unsigned char boolean; /* 8-bit*/ + +typedef uint_8* uint_8_ptr; /* ptr to 8-bit*/ +typedef uint_16* uint_16_ptr; /* ptr to 16-bit */ +typedef uint_32* uint_32_ptr; /* ptr to 32-bit*/ + +typedef uint_8_ptr uint8_ptr; /* ptr to 8-bit*/ + +/* definition of 8 bit word */ +typedef union _BYTE +{ + uint_8 _byte; + struct + { + unsigned b0:1; + unsigned b1:1; + unsigned b2:1; + unsigned b3:1; + unsigned b4:1; + unsigned b5:1; + unsigned b6:1; + unsigned b7:1; + }Bit; +} BYTE; + +/* definition of 16 bit word */ +typedef union _WORD +{ + uint_16 _word; + struct + { + uint_8 byte1; + uint_8 byte0; + }_byte; + struct + { + BYTE HighB; + BYTE LowB; + }_Byte; +} WORD; + +/* definition of 32 bit word */ +typedef union _DWORD +{ + uint_32 _dword; + struct + { + uint_8 byte3; + uint_8 byte2; + uint_8 byte1; + uint_8 byte0; + }_byte; + struct + { + uint_16 word1; + uint_16 word0; + }_word; + struct + { + BYTE Byte3; + BYTE Byte2; + BYTE Byte1; + BYTE Byte0; + }_Byte; + struct + { + WORD Word1; + WORD Word0; + }_Word; +} DWORD; + +/****************************************************************************** + * Global Functions - None + *****************************************************************************/ + +#endif + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h new file mode 100644 index 0000000..d9f24bb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_bdt_kinetis.h + * + * @author + * + * @version + * + * @date Jun-05-2009 + * + * @brief The file contains definitions of Buffer Descriptor Table. + * + *****************************************************************************/ + +#ifndef _USBBDT_H +#define _USBBDT_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +/* Buffer Descriptor Status Register Initialization Parameters */ +#define _BDTSTALL (0x04) /* Buffer Stall enable */ +#define _DATA0 (0x00) /* DATA0 packet expected next */ +#define _DATA1 (0x40) /* DATA1 packet expected next */ +#define _DTS (0x08) /* DTS Mask */ +#define _SIE (0x80) /* SIE owns buffer */ +#define _CPU (0x00) /* CPU owns buffer */ +#define _KEEP (0x20) /* keep bit */ + +#define MAX_BDT_INDEX (64) /* Maximum BDT Indexes */ + + +/****************************************************************************** + * Types + *****************************************************************************/ + /* This structure is an exact replica of the BDT MAP in the USB RAM + The BDT_STAT defines the stat byte of the buffer descriptor vector. + McuCtlBit structure defines the bits that have a meaning from CPU + point of view.SieCtlBit structure defines the bits that have a + meaning from USB controller point of view. + */ + +#if defined(__CWCC__) +#pragma align_array_members on +#endif +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) +typedef struct _MCU_CTL_BIT{ + uint_8 :1; + uint_8 :1; + uint_8 bdtstall:1; /* Buffer Stall Enable */ + uint_8 dts:1; /* Data Toggle Synch Enable */ + uint_8 keep:1; /* Address Increment Disable */ + uint_8 ninc:1; /* BD Keep Enable */ + uint_8 data:1; /* Data Toggle Synch Value */ + uint_8 own:1; /* USB Ownership */ +}MCU_CTL_BIT; /* read Stat */ + +typedef struct _SIE_CTL_BIT{ + uint_8 :1; + uint_8 :1; + uint_8 pid0:1; /* Packet Identifier bit 0 */ + uint_8 pid1:1; /* Packet Identifier bit 1 */ + uint_8 pid2:1; /* Packet Identifier bit 2 */ + uint_8 pid3:1; /* Packet Identifier bit 3 */ + uint_8 :1; + uint_8 own:1; +}SIE_CTL_BIT; /* write Stat */ + +typedef struct _REC_PID{ + uint_8 :2; + uint_8 pid:4; /* Packet Identifier */ + uint_8 :2; +}REC_PID; + +typedef union _BD_STAT +{ + uint_8 _byte; + MCU_CTL_BIT McuCtlBit; + SIE_CTL_BIT SieCtlBit; + REC_PID RecPid; +} BD_STAT; /* Buffer Descriptor Status Register */ + +typedef struct _BUFF_DSC +{ + BD_STAT Stat; + uint_8 reserved1; + uint_16 cnt; /* Count of bytes receieved or sent */ + /* six MSB bits are reserved ones */ + uint_32 addr; /* Buffer Address */ +} BUFF_DSC, *P_BUFF_DSC; /* Buffer Descriptor Table */ + +typedef struct _g_bdtmap { + + BUFF_DSC ep_dsc[MAX_BDT_INDEX]; /* Endpoint Descriptor */ +}BDTMAP; +#if defined(__CWCC__) +#pragma align_array_members off +#pragma options align=reset +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma pack() +#else /* e.g. gcc */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#endif +/****************************************************************************** + * Global Functions - None + *****************************************************************************/ + +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c new file mode 100644 index 0000000..b2b02c8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c @@ -0,0 +1,809 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack CDC layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_cdc.h" /* USB CDC Class Header File */ +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ +#ifdef _MC9S08JS16_H +#pragma DATA_SEG APP_DATA +#endif + +/* CDC Class Callback Function Pointer */ +static USB_CLASS_CALLBACK g_cdc_class_callback = NULL; + +/* CDC Class Vendor Callback Function Pointer */ +static USB_REQ_FUNC g_vendor_req_callback = NULL; + +/* CDC endpoint info array */ +#ifndef COMPOSITE_DEV +static USB_CLASS_CDC_ENDPOINT g_cdc_ep[CDC_DESC_ENDPOINT_COUNT]; +#else +static USB_CLASS_CDC_ENDPOINT g_cdc_ep[COMPOSITE_DESC_ENDPOINT_COUNT]; +#endif +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +#if CIC_NOTIF_ELEM_SUPPORT +void USB_Class_CDC_Service_Cic_Notify(PTR_USB_DEV_EVENT_STRUCT event); +#endif +#if !DIC_ISOCHRONOUS_SETTING +void USB_Class_CDC_Service_Dic_Bulk_In(PTR_USB_DEV_EVENT_STRUCT event); +void USB_Class_CDC_Service_Dic_Bulk_Out(PTR_USB_DEV_EVENT_STRUCT event); +#else +static void USB_Class_CDC_Service_Dic_Iso_In(PTR_USB_DEV_EVENT_STRUCT event); +static void USB_Class_CDC_Service_Dic_Iso_Out(PTR_USB_DEV_EVENT_STRUCT event); +#endif +#ifndef COMPOSITE_DEV +static uint_8 USB_Other_Requests( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +#endif + void USB_Class_CDC_Event( + uint_8 controller_ID, + uint_8 event, + void* val); + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + + /***************************************************************************** + * Local Functions + *****************************************************************************/ +#if CIC_NOTIF_ELEM_SUPPORT +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Cic_Notify + * + * @brief The function is callback function of CIC Notification endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower layer when data on CIC Endpoint is sent + *****************************************************************************/ +void USB_Class_CDC_Service_Cic_Notify ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + break; + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + + if(g_cdc_class_callback != NULL) + { + uint_8 event_type = USB_APP_SEND_COMPLETE; + + if(event->errors != 0) + { + event_type = USB_APP_ERROR; + } + g_cdc_class_callback(event->controller_ID, event_type, + (uint_8*)(&(event->errors))); + } +} +#endif + +#if !DIC_ISOCHRONOUS_SETTING +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Bulk_In + * + * @brief The function is callback function of DIC Bulk In Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC SEND Interface is sent + *****************************************************************************/ +void USB_Class_CDC_Service_Dic_Bulk_In ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT bulk_in_recv; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + bulk_in_recv.data_ptr = event->buffer_ptr; + bulk_in_recv.data_size = event->len; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + break; + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_SEND_COMPLETE, + (void*)&bulk_in_recv); + } + } +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Bulk_Out + * + * @brief The function is callback function of DIC Bulk Out Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC RECV Interface is received + *****************************************************************************/ +void USB_Class_CDC_Service_Dic_Bulk_Out ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ APP_DATA_STRUCT bulk_out_recv; + + bulk_out_recv.data_ptr = event->buffer_ptr; + bulk_out_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_DATA_RECEIVED, + (void*)&bulk_out_recv); + } + } +} + +#else +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Iso_In + * + * @brief The function is callback function of DIC Isochronous In Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC SEND Interface is sent + *****************************************************************************/ +static void USB_Class_CDC_Service_Dic_Iso_In ( + PTR_USB_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT iso_in_recv; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + { + break; + } + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + + iso_in_recv.data_ptr = event->buffer_ptr; + iso_in_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_SEND_COMPLETE, + (void*)&iso_in_recv); + } + } +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Iso_Out + * + * @brief This is a callback function of DIC Isochronous Out Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC RECV Interface is received + *****************************************************************************/ +static void USB_Class_CDC_Service_Dic_Iso_Out ( + PTR_USB_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT iso_out_recv; + + iso_out_recv.data_ptr = event->buffer_ptr; + iso_out_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_DATA_RECEIVED, + (void*)&iso_out_recv); + } + } +} +#endif +/**************************************************************************//*! + * + * @name USB_Class_CDC_Event + * + * @brief The function initializes CDC endpoints + * + * @param controller_ID : Controller ID + * @param event : Event Type + * @param val : Pointer to configuration Value + * + * @return None + * + ****************************************************************************** + * + *****************************************************************************/ +void USB_Class_CDC_Event ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 event, /* [IN] Event Type */ + void* val /* [OUT] Pointer to configuration Value */ +) +{ + uint_8 index; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(controller_ID); + + if(event == USB_APP_ENUM_COMPLETE) + { + uint_8 count = 0,ep_count = 0; + uint_8 index_num = 0; + +#ifdef COMPOSITE_DEV + DEV_ARCHITECTURE_STRUCT_PTR dev_arc_ptr; + CLASS_ARC_STRUCT_PTR dev_class_ptr; + dev_arc_ptr = (DEV_ARCHITECTURE_STRUCT *)USB_Desc_Get_Class_Architecture(controller_ID); + for(count = 0; count < dev_arc_ptr->cl_count; count++) + { + dev_class_ptr = (CLASS_ARC_STRUCT_PTR)dev_arc_ptr->value[count]; + /* Initializes sub_classes */ + ep_count = dev_class_ptr->value[0]; + if(dev_class_ptr->class_type == 0x02/*CDC_CC*/) + break; + index_num +=dev_class_ptr->value[0]; + } +#else + ep_count = usb_ep_data->count; +#endif + + for(count=index_num; countep[count]); // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + (void)_usb_device_deinit_endpoint(&controller_ID, + ep_struct_ptr->ep_num, ep_struct_ptr->direction); + } + + /* intialize all non control endpoints */ + for(count=index_num; countep[count]); // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + + (void)_usb_device_init_endpoint(&controller_ID, ep_struct->ep_num, + ep_struct->size, ep_struct->direction, ep_struct->type, FALSE); + + /* register callback service for Non Control EndPoints */ + switch(ep_struct->type) + { +#if CIC_NOTIF_ELEM_SUPPORT + case USB_INTERRUPT_PIPE : + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Cic_Notify); + break; +#endif +#if !DIC_ISOCHRONOUS_SETTING + case USB_BULK_PIPE : +#ifdef MULTIPLE_DEVICES + if(ep_struct->direction == USB_RECV) + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Bulk_Out); + } + else + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Bulk_In); + } +#endif + break; +#else + case USB_ISOCHRONOUS_PIPE : + if(ep_struct->direction == USB_RECV) + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Iso_Out); + } + else + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Iso_In); + } + break; +#endif + default: + break; + } + /* set the EndPoint Status as Idle in the device layer */ + (void)_usb_device_set_status(&controller_ID, + (uint_8)(USB_STATUS_ENDPOINT | ep_struct->ep_num | + (ep_struct->direction << USB_COMPONENT_DIRECTION_SHIFT)), + (uint_8)USB_STATUS_IDLE); + } + } + else if(event == USB_APP_BUS_RESET) + { +#if IMPLEMENT_QUEUING + for(index = 0; index < usb_ep_data->count; index++) + { + g_cdc_ep[index].bin_consumer = 0x00; + g_cdc_ep[index].bin_producer = 0x00; + } +#endif + } + if(g_cdc_class_callback != NULL) + { + g_cdc_class_callback(controller_ID, event, val); + } +} + +/**************************************************************************//*! + * + * @name USB_Other_Requests + * + * @brief The function provides flexibilty to add class and vendor specific + * requests + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data: : Data to be send back + * @param size: : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * Handles CDC Class requests and forwards vendor specific request to the + * application + *****************************************************************************/ +#ifndef COMPOSITE_DEV +static uint_8 USB_Other_Requests +#else +uint_8 USB_CDC_Other_Requests +#endif +( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet,/* [IN] Pointer to Setup Packet Received */ + uint_8_ptr *data, /* [OUT] Pointer to Data Buffer to be sent */ + USB_PACKET_SIZE *size /* [OUT] Size of Data buffer */ +) +{ + uint_8 status = USBERR_INVALID_REQ_TYPE; + if((setup_packet->request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_CLASS) + { + /* class request so handle it here */ + status=USB_OK; + + /* call for class/subclass specific requests */ + switch(setup_packet->request) + { + case SEND_ENCAPSULATED_COMMAND : + /* Add code to transfer Request and Acknowledgement */ + *size=0; + break; + case GET_ENCAPSULATED_RESPONSE : + /* + Add code for handling Transfer Response/Requests and + Notification + */ + *size=0; + break; + case SET_COMM_FEATURE : + status = USB_Class_CDC_PSTN_Set_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case GET_COMM_FEATURE : + status = USB_Class_CDC_PSTN_Get_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case CLEAR_COMM_FEATURE : /* Verify this implementation */ + *size = COMM_FEATURE_DATA_SIZE; + **data = 0x00; *(++(*data)) = 0x00;/* clear both feature bytes */ + status = USB_Class_CDC_PSTN_Set_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case GET_LINE_CODING : + status = USB_Class_CDC_PSTN_Get_Line_Coding(controller_ID, + setup_packet, data, size); + break; + case SET_LINE_CODING : + status = USB_Class_CDC_PSTN_Set_Line_Coding(controller_ID, + setup_packet, data, size); + break; + case SET_CONTROL_LINE_STATE : + status = USB_Class_CDC_PSTN_Set_Ctrl_Line_State(controller_ID, + setup_packet, data, size); + break; + case SEND_BREAK : + status = USB_Class_CDC_PSTN_Send_Break(controller_ID, + setup_packet, data, size); + break; + default: + *size=0; + break; + } + } + else if((setup_packet->request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_VENDOR) + { + /* vendor specific request */ + if(g_vendor_req_callback != NULL) + { + status = g_vendor_req_callback(controller_ID, setup_packet, data, + size); + } + } + return status; +} + + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +/**************************************************************************//*! + * + * @name USB_Class_CDC_Init + * + * @brief The function initializes the Device and Controller layer + * + * @param controller_ID: Controller ID + * @param cdc_class_callback: CDC Class Callback + * @param vendor_req_callback: vendor specific class request callback + * @param param_callback: PSTN Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * This function initializes the CDC Class layer and layers it is dependent upon + *****************************************************************************/ +uint_8 USB_Class_CDC_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK cdc_class_callback, /* [IN] CDC Class Callback */ + USB_REQ_FUNC vendor_req_callback, /* [IN] Vendor Request Callback */ + USB_CLASS_CALLBACK pstn_callback, /* [IN] PSTN Callback */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ + uint_8 index,status = USB_OK; + USB_ENDPOINTS *usb_ep_data = + (USB_ENDPOINTS *)USB_Desc_Get_Endpoints(controller_ID); +#ifndef COMPOSITE_DEV + /* Initialize the device layer*/ + status = _usb_device_init(controller_ID, NULL, + (uint_8)(usb_ep_data->count+1), bVregEn); + /* +1 is for Control Endpoint */ + + if(status == USB_OK) + { + /* Initialize the generic class functions */ + status = USB_Class_Init(controller_ID,USB_Class_CDC_Event, + USB_Other_Requests); +#endif +#if IMPLEMENT_QUEUING + for(index = 0; index < usb_ep_data->count; index++) + { + g_cdc_ep[index].endpoint = usb_ep_data->ep[index].ep_num; + g_cdc_ep[index].type = usb_ep_data->ep[index].type; + g_cdc_ep[index].bin_consumer = 0x00; + g_cdc_ep[index].bin_producer = 0x00; + } +#endif +#if PSTN_SUBCLASS_NOTIF_SUPPORT + /* Initialize the pstn subclass functions */ + status = USB_Class_CDC_Pstn_Init(controller_ID,pstn_callback); +#endif + if(status == USB_OK) + { + /* save the callback pointer */ + g_cdc_class_callback = cdc_class_callback; + + /* save the callback pointer */ + g_vendor_req_callback = vendor_req_callback; + } +#ifndef COMPOSITE_DEV + } +#endif + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_DeInit + * + * @brief The function de-initializes the Device and Controller layer + * + * @param controller_ID : Controller ID + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + *This function de-initializes the CDC Class layer + *****************************************************************************/ +uint_8 USB_Class_CDC_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 status = USB_OK; +#ifdef COMPOSITE_DEV + UNUSED(controller_ID); +#endif + /* save the callback pointer */ + g_cdc_class_callback = NULL; + + /* free the vendor request callback pointer */ + g_vendor_req_callback = NULL; + +#ifndef COMPOSITE_DEV + /* call common class deinit function */ + status = USB_Class_DeInit(controller_ID); + + if(status == USB_OK) + /* Call device deinit function */ + status = _usb_device_deinit(); +#endif + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Send_Data + * + * @brief This function is used to send data from CDC Class over send endpoints + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param app_buff : Buffer to send + * @param size : Length of the transfer + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Helper function. Sends DATA over CIC and DIC Interfaces to Host + *****************************************************************************/ +uint_8 USB_Class_CDC_Send_Data ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8_ptr app_buff, /* Pointer to Application Buffer */ + USB_PACKET_SIZE size /* Size of Application Buffer */ +) +{ + uint_8 status = USB_OK; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(controller_ID); + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == ep_num) + { + break; + } + } + + producer = g_cdc_ep[index].bin_producer; + consumer = g_cdc_ep[index].bin_consumer; + + if(((uint_8)(producer - consumer)) != (uint_8)(MAX_QUEUE_ELEMS)) + { + /* the bin is not full*/ + + uint_8 queue_num = (uint_8)(producer % MAX_QUEUE_ELEMS); + + /* put all send request parameters in the endpoint data structure */ + g_cdc_ep[index].queue[queue_num].controller_ID = controller_ID; + g_cdc_ep[index].queue[queue_num].channel = ep_num; + g_cdc_ep[index].queue[queue_num].app_data.data_ptr = app_buff; + g_cdc_ep[index].queue[queue_num].app_data.data_size = size; + + /* increment producer bin by 1*/ + g_cdc_ep[index].bin_producer = ++producer; + + if((uint_8)(producer - consumer) == (uint_8)1) + { +#endif + status = USB_Class_Send_Data(controller_ID, ep_num, app_buff,size); +#if IMPLEMENT_QUEUING + } + } + else /* bin is full */ + { + status = USBERR_DEVICE_BUSY; + } +#endif + return status; +} + +/* EOF */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h new file mode 100644 index 0000000..89f27ab --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h @@ -0,0 +1,202 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack CDC class layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_CDC_H +#define _USB_CDC_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_descriptor.h" +#include "usb_class.h" +#include "usb_cdc_pstn.h" +#include "usb_devapi.h" +#ifdef COMPOSITE_DEV +#include "usb_composite.h" +#endif + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +/* Class specific request Codes */ +#define SEND_ENCAPSULATED_COMMAND (0x00) +#define GET_ENCAPSULATED_RESPONSE (0x01) +#define SET_COMM_FEATURE (0x02) +#define GET_COMM_FEATURE (0x03) +#define CLEAR_COMM_FEATURE (0x04) +#define SET_AUX_LINE_STATE (0x10) +#define SET_HOOK_STATE (0x11) +#define PULSE_SETUP (0x12) +#define SEND_PULSE (0x13) +#define SET_PULSE_TIME (0x14) +#define RING_AUX_JACK (0x15) +#define SET_LINE_CODING (0x20) +#define GET_LINE_CODING (0x21) +#define SET_CONTROL_LINE_STATE (0x22) +#define SEND_BREAK (0x23) +#define SET_RINGER_PARAMS (0x30) +#define GET_RINGER_PARAMS (0x31) +#define SET_OPERATION_PARAM (0x32) +#define GET_OPERATION_PARAM (0x33) +#define SET_LINE_PARAMS (0x34) +#define GET_LINE_PARAMS (0x35) +#define DIAL_DIGITS (0x36) +#define SET_UNIT_PARAMETER (0x37) +#define GET_UNIT_PARAMETER (0x38) +#define CLEAR_UNIT_PARAMETER (0x39) +#define GET_PROFILE (0x3A) +#define SET_ETHERNET_MULTICAST_FILTERS (0x40) +#define SET_ETHERNET_POW_PATTER_FILTER (0x41) +#define GET_ETHERNET_POW_PATTER_FILTER (0x42) +#define SET_ETHERNET_PACKET_FILTER (0x43) +#define GET_ETHERNET_STATISTIC (0x44) +#define SET_ATM_DATA_FORMAT (0x50) +#define GET_ATM_DEVICE_STATISTICS (0x51) +#define SET_ATM_DEFAULT_VC (0x52) +#define GET_ATM_VC_STATISTICS (0x53) +#define MDLM_SPECIFIC_REQUESTS_MASK (0x7F) + +/* Class Specific Notification Codes */ +#define NETWORK_CONNECTION_NOTIF (0x00) +#define RESPONSE_AVAIL_NOTIF (0x01) +#define AUX_JACK_HOOK_STATE_NOTIF (0x08) +#define RING_DETECT_NOTIF (0x09) +#define SERIAL_STATE_NOTIF (0x20) +#define CALL_STATE_CHANGE_NOTIF (0x28) +#define LINE_STATE_CHANGE_NOTIF (0x29) +#define CONNECTION_SPEED_CHANGE_NOTIF (0x2A) +#define MDLM_SPECIFIC_NOTIF_MASK (0x5F) + +/* Events to the Application */ /* 0 to 4 are reserved for class events */ +#define USB_APP_CDC_CARRIER_DEACTIVATED (0x21) +#define USB_APP_CDC_CARRIER_ACTIVATED (0x22) + +/* other macros */ +#define NOTIF_PACKET_SIZE (0x08) +#define NOTIF_REQUEST_TYPE (0xA1) + +/* macros for queuing */ +#define MAX_QUEUE_ELEMS (4) + +#if CIC_NOTIF_ELEM_SUPPORT +#define CIC_SEND_ENDPOINT CIC_NOTIF_ENDPOINT +#endif + +#if DIC_ISOCHRONOUS_SETTING + #define DIC_SEND_ENDPOINT DIC_ISO_IN_ENDPOINT + #define DIC_RECV_ENDPOINT DIC_ISO_OUT_ENDPOINT +#else + #define DIC_SEND_ENDPOINT DIC_BULK_IN_ENDPOINT + #define DIC_RECV_ENDPOINT DIC_BULK_OUT_ENDPOINT +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ +#ifndef COMPOSITE_DEV +typedef struct _app_data_struct +{ + uint_8_ptr data_ptr; /* pointer to buffer */ + USB_PACKET_SIZE data_size; /* buffer size of endpoint */ +}APP_DATA_STRUCT; +#endif + +/* structure to hold a request in the endpoint queue */ +typedef struct _usb_class_cdc_queue +{ + uint_8 controller_ID; /* Controller ID */ + uint_8 channel; /* Endpoint Number */ + APP_DATA_STRUCT app_data; /* Application Data Structure */ +}USB_CLASS_CDC_QUEUE, *PTR_USB_CLASS_CDC_QUEUE; + +/* USB class cdc endpoint data */ +typedef struct _usb_class_cdc_endpoint +{ + uint_8 endpoint; /* endpoint num */ + uint_8 type; /* type of endpoint (interrupt, bulk or isochronous) */ + uint_8 bin_consumer;/* the num of queued elements */ + uint_8 bin_producer;/* the num of de-queued elements */ + USB_CLASS_CDC_QUEUE queue[MAX_QUEUE_ELEMS]; /* queue data */ +}USB_CLASS_CDC_ENDPOINT; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Class_CDC_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK cdc_class_callback, /* [IN] CDC Class Callback */ + USB_REQ_FUNC vendor_req_callback, /* [IN] Vendor Request Callback */ + USB_CLASS_CALLBACK pstn_callback, /* [IN] PSTN Callback */ + uint_8 bVregEn /* Enables or disables internal regulator */ +); + +#ifdef COMPOSITE_DEV +extern uint_8 USB_CDC_Other_Requests(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +#endif + +extern uint_8 USB_Class_CDC_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Class_CDC_Send_Data ( + uint_8 controller_ID, + uint_8 ep_num, + uint_8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +#if CIC_NOTIF_ELEM_SUPPORT +#define USB_Class_CDC_Interface_CIC_Send_Data(a,b,c) \ + USB_Class_CDC_Send_Data(a,CIC_SEND_ENDPOINT,b,c) +#endif + +#define USB_Class_CDC_Interface_DIC_Send_Data(a,b,c) \ + USB_Class_CDC_Send_Data(a,DIC_SEND_ENDPOINT,b,c) +#define USB_Class_CDC_Interface_DIC_Recv_Data(a,b,c) \ + _usb_device_recv_data(a,DIC_RECV_ENDPOINT,b,c) +#define USB_Class_CDC_Interface_DIC_Get_Send_Buffer(a,b,c) \ + _usb_device_get_send_buffer(a,DIC_SEND_ENDPOINT,b,c) + +#define USB_Class_CDC_Periodic_Task USB_Class_Periodic_Task + +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c new file mode 100644 index 0000000..1674391 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c @@ -0,0 +1,398 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc_pstn.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB CDC_PSTN Sub Class implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ + #include "usb_cdc_pstn.h" /* USB CDC PSTN Sub Class Header File */ + + /***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/***************************************************************************** + * Global Functions Prototypes + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables + *****************************************************************************/ +/* PSTN subclass callback pointer */ +static USB_CLASS_CALLBACK g_pstn_callback = NULL; +/* data terminal equipment present or not */ +static boolean g_dte_present = FALSE; +static uint_8 g_dte_status = 0; /* Status of DATA TERMINAL EQUIPMENT */ +static uint_16 g_break_duration = 0; /* Length of time in milliseconds of the + break signal */ +static uint_8 g_current_interface = 0; +static UART_BITMAP g_uart_bitmap; + +#if CIC_NOTIF_ELEM_SUPPORT +static uint_8 g_serial_state_buf[NOTIF_PACKET_SIZE+UART_BITMAP_SIZE] = +{ + NOTIF_REQUEST_TYPE,SERIAL_STATE_NOTIF, + 0x00,0x00,/*wValue*/ + 0x00,0x00,/*interface - modifies*/ + UART_BITMAP_SIZE,0x00,/* wlength*/ + 0x00,0x00 /*data initialized - modifies*/ +};/*uart bitmap*/ +#endif + /***************************************************************************** + * Local Functions + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Pstn_Init + * + * @brief The function initializes the PSTN Module + * + * @param controller_ID : Controller ID + * @param callback : PSTN Callback + * + * @return error + * USB_OK : Always + ****************************************************************************** + * PSTN Sub Class Initialization routine + *****************************************************************************/ +uint_8 USB_Class_CDC_Pstn_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK callback /* [IN] PSTN Callback */ +) +{ + uint_8 error = USB_OK; + UNUSED (controller_ID); + + /* save input parameters */ + g_pstn_callback = callback; + return error; +} +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Get_Line_Coding + * + * @brief This function is called in response to GetLineCoding request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data to be send + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE: When request for + * invalid Interface is presented + ****************************************************************************** + * Calls application to receive Line Coding Information + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Get_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data to be send */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + UNUSED (size); + g_current_interface = (uint_8)setup_packet->index ; + status = USB_Desc_Get_Line_Coding(controller_ID, g_current_interface, + data); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Line_Coding + * + * @brief This function is called in response to SetLineCoding request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Calls Applciation to update Line Coding Information + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + UNUSED(data); + + *size = 0; + + g_current_interface = (uint_8)setup_packet->index ; + status = USB_Desc_Set_Line_Coding(controller_ID, g_current_interface, + (uint_8_ptr *)&setup_packet); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Ctrl_Line_State + * + * @brief This function is called in response to Set Control Line State + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : Always + ****************************************************************************** + * Updates Control Line State + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Ctrl_Line_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + UNUSED(data); + *size = 0; + + g_dte_status = (uint_8)setup_packet->value ; + g_uart_bitmap._byte = 0x00; /* initialize */ + /* activate/deactivate Tx carrier */ + g_uart_bitmap.Bitmap_Uart.bTxCarrier = (g_dte_status & + CARRIER_ACTIVATION_CHECK) ? 1 : 0 ; + /* activate carrier and DTE */ + g_uart_bitmap.Bitmap_Uart.bRxCarrier = (g_dte_status & + CARRIER_ACTIVATION_CHECK) ? 1 : 0 ; + + /* Indicates to DCE if DTE is present or not */ + g_dte_present = (boolean)((g_dte_status & DTE_PRESENCE_CHECK) ? + TRUE : FALSE); + UNUSED(g_dte_present); +#if CIC_NOTIF_ELEM_SUPPORT + /* Send Notification to Host - Parameter on Device side has changed */ + USB_Class_CDC_PSTN_Send_Serial_State(controller_ID); +#endif + if(g_pstn_callback != NULL) + { + if(g_dte_status & CARRIER_ACTIVATION_CHECK) + { + g_pstn_callback(controller_ID, USB_APP_CDC_CARRIER_ACTIVATED, + NULL); + } + else + { + g_pstn_callback(controller_ID, USB_APP_CDC_CARRIER_DEACTIVATED, + NULL); + } + } + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Send_Break + * + * @brief This function is called in response to Set Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : Always + ****************************************************************************** + * Updates Break Duration Information from Host + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Send_Break ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + UNUSED (controller_ID); + UNUSED (data); + *size = 0; + + g_break_duration = setup_packet->value; + UNUSED(g_break_duration); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Get_Comm_Feature + * + * @brief This function is called in response to GetCommFeature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data to be send + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Returns the status of the get comm feature request + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Get_Comm_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data to send */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ uint_8 status; + + status = USB_OK; + *size = COMM_FEATURE_DATA_SIZE; + g_current_interface = (uint_8)setup_packet->index ; + if(setup_packet->value == ABSTRACT_STATE_FEATURE) + { + status = USB_Desc_Get_Abstract_State(controller_ID, + g_current_interface, data); + } + else if(setup_packet->value == COUNTRY_SETTING_FEATURE) + { + status = USB_Desc_Get_Country_Setting(controller_ID, + g_current_interface, data); + } + else + { + *size = 0; /* for Reserved/Invalid Feature Selector Value */ + } + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Comm_Feature + * + * @brief This function is called in response to SetCommFeature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Sets the comm feature specified by Host + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Comm_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + status = USB_OK; + *size = COMM_FEATURE_DATA_SIZE; + g_current_interface = (uint_8)setup_packet->index ; + if(setup_packet->value == ABSTRACT_STATE_FEATURE) + { + status = USB_Desc_Set_Abstract_State(controller_ID, + g_current_interface, data); + } + else if(setup_packet->value == COUNTRY_SETTING_FEATURE) + { + status = USB_Desc_Set_Country_Setting(controller_ID, + g_current_interface, data); + } + else + { + *size = 0; /* for Reserved/Invalid Feature Selector Value */ + } + return status; +} + +#if CIC_NOTIF_ELEM_SUPPORT +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Send_Serial_State + * + * @brief This function is called to send serial state notification + * + * @param controller_ID : Controller ID + * + * @return NONE + ****************************************************************************** + * Returns the Serial State + *****************************************************************************/ +void USB_Class_CDC_PSTN_Send_Serial_State ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + /* update array for current interface */ + g_serial_state_buf[4] = g_current_interface; + /* Lower byte of UART BITMAP */ + g_serial_state_buf[NOTIF_PACKET_SIZE+UART_BITMAP_SIZE-2] = + g_uart_bitmap._byte; + (void)USB_Class_CDC_Interface_CIC_Send_Data(controller_ID, + g_serial_state_buf, (NOTIF_PACKET_SIZE + UART_BITMAP_SIZE)); +} +#endif + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h new file mode 100644 index 0000000..223c475 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc_pstn.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB CDC_PSTN Sub Class API header function + * + *****************************************************************************/ + +#ifndef _USB_CDC_PSTN_H +#define _USB_CDC_PSTN_H + +/****************************************************************************** + * Includes + *****************************************************************************/ + #include "usb_cdc.h" /* USB CDC Class Header File */ +/****************************************************************************** + * Constants - None + *****************************************************************************/ +#ifdef __MCF52xxx_H__ +#pragma reverse_bitfields on +#endif +typedef struct _BITMAP_UART +{ + uint_8 bRxCarrier : 1; /* Receive Carrier Activation Flag */ + uint_8 bTxCarrier : 1; /* Transmit Carrier Activation Flag */ + uint_8 bBreak : 1; /* Break Flag */ + uint_8 bRingSignal : 1; /* Ring Signal Flag */ + uint_8 bFraming : 1; /* Frame Flag */ + uint_8 bParity : 1; /* Parity Flag */ + uint_8 bOverRun : 1; /* OverRun Flag */ + uint_8 reserved1 : 1; /* Reserved */ +}BITMAP_UART; +#ifdef __MCF52xxx_H__ +#pragma reverse_bitfields off +#endif + + +typedef union _UART_BITMAP +{ + uint_8 _byte; + BITMAP_UART Bitmap_Uart; +}UART_BITMAP; /* UART STATE BITMAP */ + + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define UART_BITMAP_SIZE (0x02) +#define ABSTRACT_STATE_FEATURE (0x01) +#define COUNTRY_SETTING_FEATURE (0x02) +#define CARRIER_ACTIVATION_CHECK (0x02) +#define DTE_PRESENCE_CHECK (0x01) + +extern uint_8 USB_Class_CDC_Pstn_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK callback +); + +extern uint_8 USB_Class_CDC_PSTN_Get_Line_Coding ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Line_Coding ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Ctrl_Line_State ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Send_Break ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Get_Comm_Feature ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Comm_Feature ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +#if CIC_NOTIF_ELEM_SUPPORT +extern void USB_Class_CDC_PSTN_Send_Serial_State (uint_8 controller_ID); +#endif +#endif + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c new file mode 100644 index 0000000..8f4730a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c @@ -0,0 +1,493 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_class.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains USB stack Class module implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_class.h" /* USB class Header File */ +#include "usb_devapi.h" /* USB device Header file */ +#include "usb_framework.h" /* USB framework module header file */ +#include "hidef.h" /* for EnableInterrupts; macro */ + +#if 0 /* << EST */ +#if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) +#include "exceptions.h" +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + /* Class callback pointer */ +static USB_CLASS_CALLBACK g_class_callback = NULL; +/* save the device state before device goes to suspend state */ +static uint_8 g_device_state_before_suspend; +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +void USB_Suspend_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Resume_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Stall_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Sof_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Reset_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Error_Service (PTR_USB_DEV_EVENT_STRUCT event ); + +/***************************************************************************** + * Local Variables + *****************************************************************************/ + + /***************************************************************************** + * Local Functions - None + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/**************************************************************************//*! + * + * @name USB_Suspend_Service + * + * @brief The function is called when host suspends the USB port + * + * @param event : Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Sets the device state as USB_STATE_SUSPEND + *****************************************************************************/ +void USB_Suspend_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* Get the status of the device before suspend, so that on resume we + can get back to the same state */ + (void)_usb_device_get_status(&(event->controller_ID), + USB_STATUS_DEVICE_STATE, &g_device_state_before_suspend); + /* Set the device state in the Device Layer to SUSPEND */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + USB_STATE_SUSPEND); + + /* let the application know that bus suspend has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_SUSPEND, NULL); + + return; +} + +/**************************************************************************//*! + * + * @name USB_Resume_Service + * + * @brief The function is called when host resumes the USB port + * + * @param event : Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Restore the state of the device before suspend + *****************************************************************************/ +void USB_Resume_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_8 device_state; + (void)_usb_device_get_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + &device_state); + if(device_state == USB_STATE_SUSPEND) + { + /* + Set the device state in the Device Layer to the state + before suspend + */ + (void)_usb_device_set_status(&(event->controller_ID), + USB_STATUS_DEVICE_STATE, g_device_state_before_suspend); + } + + /* let the application know that bus resume has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_RESUME, NULL); + + return; +} + +/**************************************************************************//*! + * + * @name USB_Stall_Service + * + * @brief The function is called when endpoint is stalled + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * This function sends STALL Packet for the endpoint to be stalled. Also, sets + * the status of Endpoint as STALLED + *****************************************************************************/ +void USB_Stall_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + if(event->ep_num == CONTROL_ENDPOINT) + { + /* Update the Endpoint Status in the Device Layer to Idle */ + (void)_usb_device_set_status(&(event->controller_ID), + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (event->direction << USB_COMPONENT_DIRECTION_SHIFT)), + (uint_16)USB_STATUS_IDLE); + } + return; +} + +/**************************************************************************//*! + * + * @name USB_Sof_Service + * + * @brief The function is called when SOF flag is set (from ISR) + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * This function is called when SOF token is received by controller. Updates + * SOF Count status. + *****************************************************************************/ +void USB_Sof_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_16 sof_count; + + /* update SOF */ + sof_count = event->buffer_ptr[0]; + sof_count <<= SOF_HIGH_BYTE_SHIFT; + sof_count |= event->buffer_ptr[1]; + + /* write SOF to status */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_SOF_COUNT, + (uint_8)sof_count); + return; +} +/**************************************************************************//*! + * + * @name USB_Reset_Service + * + * @brief The function is called upon a bus reset event. + Initializes the control endpoint. + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Reset Callback function. This function re-initializes CONTROL Endpoint + *****************************************************************************/ +void USB_Reset_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + + USB_EP_STRUCT ep_struct; + uint_8 err; + + /* Initialize the endpoint 0 in both directions */ + ep_struct.direction = USB_SEND; + ep_struct.ep_num = CONTROL_ENDPOINT; + ep_struct.size = CONTROL_MAX_PACKET_SIZE; + ep_struct.type = USB_CONTROL_PIPE; + + /* Deinit Endpoint in case its already initialized */ + err = _usb_device_deinit_endpoint(&(event->controller_ID), + ep_struct.ep_num, ep_struct.direction); + /* now initialize the endpoint */ + err = _usb_device_init_endpoint(&(event->controller_ID), + ep_struct.ep_num, (uint_16)ep_struct.size, ep_struct.direction, ep_struct.type, TRUE); + + ep_struct.direction = USB_RECV; + /* Deinit Endpoint in case its already initialized */ + (void)_usb_device_deinit_endpoint(&(event->controller_ID), + ep_struct.ep_num, ep_struct.direction); + /* now initialize the endpoint */ + (void)_usb_device_init_endpoint(&(event->controller_ID), + ep_struct.ep_num, (uint_16)ep_struct.size, ep_struct.direction, ep_struct.type, TRUE); + + /* set the default device state */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + USB_STATE_DEFAULT); + + /* set the default device state */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE, + SELF_POWERED >> SELF_POWER_BIT_SHIFT); + + /* set the EndPoint Status as Idle in the device layer */ + (void)_usb_device_set_status(&(event->controller_ID), + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (USB_SEND << USB_COMPONENT_DIRECTION_SHIFT)), + USB_STATUS_IDLE); + /* let the application know that bus reset has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_RESET, NULL); + + UNUSED(err); + return; +} + +/**************************************************************************//*! + * + * @name USB_Error_Service + * + * @brief The function is called when an error has been detected + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Calls application with the error code received from the lower layer + *****************************************************************************/ +void USB_Error_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* notify the application of the error */ + g_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + return; +} + + +/**************************************************************************//*! + * + * @name USB_Class_Init + * + * @brief The function initializes the Class Module + * + * @param controller_ID : Controller ID + * @param class_callback : Class callback + * @param other_req_callback : Other Requests Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Initializes USB Class Module + *****************************************************************************/ +uint_8 USB_Class_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK class_callback, /* [IN] Class Callback */ + USB_REQ_FUNC other_req_callback /* [IN] Other Requests Callback */ +) +{ + uint_8 status = USB_Framework_Init(controller_ID,class_callback, + other_req_callback); + + /* save callback address */ + g_class_callback = class_callback; + + if(status == USB_OK) + { + /* Register all the services here */ + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_BUS_RESET, USB_Reset_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_SOF,USB_Sof_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_SLEEP,USB_Suspend_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_RESUME,USB_Resume_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_STALL,USB_Stall_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_ERROR,USB_Error_Service); + + /* set the device state as powered */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE,USB_STATE_POWERED); + g_device_state_before_suspend = USB_STATE_POWERED; + } + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_DeInit + * + * @brief The function De-initializes the Class Module + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * De-initializes USB Class Module + *****************************************************************************/ +uint_8 USB_Class_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 status = USB_OK; + /* Free class_callback */ + g_class_callback = NULL; + + /* Unegister all the services here */ + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_BUS_RESET); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_SOF); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_SLEEP); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_RESUME); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_STALL); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_ERROR); + + if(status == USB_OK) + /* Call Framework deinit function */ + status = USB_Framework_DeInit(controller_ID); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_Initiate_Resume + * + * @brief The function initiates resume procedure + * + * @param controller_ID : Controller ID + * + * @return device_state + ******************************************************************************/ +uint_8 USB_Class_Initiate_Resume( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 device_state, state; + + (void)_usb_device_get_status(&controller_ID, USB_STATUS_DEVICE_STATE, + &device_state); + (void)_usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &state); + if((device_state == USB_STATE_SUSPEND) && + (state & REMOTE_WAKEUP_STATUS_MASK ) && + (USB_Frame_Remote_Wakeup(controller_ID) == TRUE)) + { + DisableInterrupts; +#if 0 + #if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) + usb_int_dis(); + #endif +#else /* << EST */ + /* device is Kinetis K20D72 << EST */ +#endif + /* Resume the bus */ + _usb_device_assert_resume(&controller_ID); + + device_state = USB_STATE_CONFIG; + /* Set the device state in the Device Layer to DEFAULT */ + (void)_usb_device_set_status(&controller_ID, USB_STATUS_DEVICE_STATE, + USB_STATE_CONFIG); + EnableInterrupts;; + #if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) + usb_int_en(); + #endif + } + return device_state; +} + +/**************************************************************************//*! + * + * @name USB_Class_Send_Data + * + * @brief The function calls the device to send data upon receiving an IN token + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param buff_ptr : Buffer to send + * @param size : Length of transfer + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Used by Application to send Data on USB Bus if not suspended + *****************************************************************************/ +uint_8 USB_Class_Send_Data ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8_ptr buff_ptr, /* [IN] Buffer to send */ + USB_PACKET_SIZE size /* [IN] Length of the transfer */ +) +{ + + uint_8 status = USB_OK; + uint_8 device_state; + + device_state = USB_Class_Initiate_Resume(controller_ID); + + if(device_state != USB_STATE_SUSPEND) + { /* if not suspended */ + status = _usb_device_send_data(&controller_ID, ep_num, buff_ptr, size); + } + + return status; + } + +/**************************************************************************//*! + * + * @name USB_Class_Periodic_Task + * + * @brief The function calls for periodic tasks + * + * @param None + * + * @return None + ****************************************************************************** + * Called to check for any pending requests + *****************************************************************************/ +void USB_Class_Periodic_Task (void) +{ +#ifdef DELAYED_PROCESSING + USB_Framework_Periodic_Task(); +#endif +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h new file mode 100644 index 0000000..d791d4c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_class.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack class layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_CLASS_H +#define _USB_CLASS_H + + +/*#define DELAYED_PROCESSING 1 This define is used to delay the control + processing and not have it executed as part + of the interrupt routine */ +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define SOF_HIGH_BYTE_SHIFT (8) +#define GET_STATUS_DEVICE_MASK (0x0003) +#ifdef OTG_BUILD +#define GET_STATUS_OTG_MASK (0x0001) +#endif +#define REMOTE_WAKEUP_STATUS_MASK (0x0002) +#define BUS_POWERED (0x80) +#define SELF_POWERED (0x40) +#define SELF_POWER_BIT_SHIFT (6) + +/* Events to the Application */ +#define USB_APP_BUS_RESET (0) +#define USB_APP_CONFIG_CHANGED (1) +#define USB_APP_ENUM_COMPLETE (2) +#define USB_APP_SEND_COMPLETE (3) +#define USB_APP_DATA_RECEIVED (4) +#define USB_APP_ERROR (5) +#define USB_APP_GET_DATA_BUFF (6) +#define USB_APP_EP_STALLED (7) +#define USB_APP_EP_UNSTALLED (8) +#define USB_APP_GET_TRANSFER_SIZE (9) +#define USB_APP_BUS_SUSPEND (0x0A) +#define USB_APP_BUS_RESUME (0x0B) + +/* max packet size for the control endpoint */ + +/* USB Specs define CONTROL_MAX_PACKET_SIZE for High Speed device as only 64, + whereas for FS its allowed to be 8, 16, 32 or 64 */ + +#if HIGH_SPEED_DEVICE +#define CONTROL_MAX_PACKET_SIZE (64) /* max supported value is 64*/ +#else +#define CONTROL_MAX_PACKET_SIZE (16) /* max supported value is 16*/ +#endif + +/* identification values and masks to identify request types */ +#define USB_REQUEST_CLASS_MASK (0x60) +#define USB_REQUEST_CLASS_STRD (0x00) +#define USB_REQUEST_CLASS_CLASS (0x20) +#define USB_REQUEST_CLASS_VENDOR (0x40) + +/****************************************************************************** + * Types + *****************************************************************************/ +/* eight byte usb setup packet structure */ +typedef struct _USB_SETUP_STRUCT { + uint_8 request_type; /* bmRequestType */ + uint_8 request; /* Request code */ + uint_16 value; /* wValue */ + uint_16 index; /* wIndex */ + uint_16 length; /* Length of the data */ +} USB_SETUP_STRUCT; + +/* callback function pointer structure for Application to handle events */ +typedef void(_CODE_PTR_ USB_CLASS_CALLBACK)(uint_8, uint_8, void*); + +/* callback function pointer structure to handle USB framework request */ +typedef uint_8 (_CODE_PTR_ USB_REQ_FUNC)(uint_8, USB_SETUP_STRUCT *, + uint_8_ptr*, + USB_PACKET_SIZE*); + +/*callback function pointer structure for application to provide class params*/ +typedef uint_8 (_CODE_PTR_ USB_CLASS_SPECIFIC_HANDLER_FUNC)( + uint_8, + uint_16, + uint_16, // Application needs to know which Interface is being communicated with + uint_8_ptr*, + USB_PACKET_SIZE*); + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Class_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK class_callback, + USB_REQ_FUNC other_req_callback +); + +extern uint_8 USB_Class_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Class_Initiate_Resume( + uint_8 controller_ID +); + +extern uint_8 USB_Class_Send_Data ( + uint_8 controller_ID, + uint_8 ep_num, + uint_8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern void USB_Class_Periodic_Task(void); + +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c new file mode 100644 index 0000000..ff4febb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c @@ -0,0 +1,2954 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2012 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dci_kinetis.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains Kinetis USB stack controller layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include +#include "usb_dciapi.h" /* USB DCI API Header File */ +#include "usb_devapi.h" /* USB Device API Header File */ +#include "usb_dci_kinetis.h" /* USB DCI Header File */ +#include "usb_bdt_kinetis.h" /* USB BDT Structure Header File */ +#include "wdt_kinetis.h" +#include "usb_class.h" + +/***************************************************************************** + * Constant and Macro's - None + *****************************************************************************/ +/**************************************************************************** + * Global Variables + ****************************************************************************/ +#ifdef USE_FEEDBACK_ENDPOINT + extern uint_32 feedback_data; + extern uint_32 gNrSamples; +#endif + +/* location for BDT Table and buff */ +#if (defined(__CWCC__)||defined(__GNUC__)) + __attribute__((__aligned__(512))) +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma data_alignment = 512 +#endif + +#if !HIGH_SPEED_DEVICE + #if defined __CC_ARM + __align(512) uint_8 g_Mem[BYTES_1024]; + #else +#if 0 + static uint_8 g_Mem[BYTES_1024]; +#else + uint_8 g_Mem[BYTES_1024]; +#endif + #endif + /* Pointer to BDT Map Structure */ + BDTMAP *g_bdtmap = NULL; + /* per endpoint per direction bdt index structure */ + static BDT_ELEM g_bdt_elem[MAX_BDT_INDEX >> 1]; +#endif +/* stores Controller ID */ +static uint_8 g_dci_controller_Id = 0; +#if HIGH_SPEED_DEVICE +static uint_8 g_dci_address_state = 0; +#endif /* HIGH_SPEED_DEVICE */ + +#if !HIGH_SPEED_DEVICE +/* Start BDT buffer Address */ +static uint_32 g_bdt_address; +#endif /* HIGH_SPEED_DEVICE */ +/* Transfer direction */ +static uint_8 g_trf_direction = USB_TRF_UNKNOWN; + + +// HIGH_SPEED_DEVICE +#if HIGH_SPEED_DEVICE + #define MAX_DTDS_PER_EP 5 // maximum number of transfer descriptors + #define DTD_FREE 0 + #define DTD_BUSY 1 + #define MAX_ENDPOINT_NUMBER 4 + + // QH structures are 64-byte aligned + #define TOTAL_QHD_SIZE (SIZE_OF_QHD * (MAX_ENDPOINT_NUMBER * 2)) + // TD structures are 64-byte aligned + #define TOTAL_QTD_SIZE ((SIZE_OF_DTD0) * (MAX_ENDPOINT_NUMBER * 2) * MAX_DTDS_PER_EP) + + #ifdef __CWCC__ + #pragma define_section usb_dqh ".usb_dqh" RW + __declspec(usb_dqh) uint_8 g_usbd_qh_buf[TOTAL_QHD_SIZE]; // 512 + #pragma define_section usb_dtd ".usb_dtd" RW + __declspec(usb_dtd) uint_8 g_usbd_td_buf[TOTAL_QTD_SIZE]; // 1280 + #else + #pragma data_alignment=(0x1000) + uint_8 g_usbd_qh_buf[TOTAL_QHD_SIZE]; // 512 + #pragma data_alignment=(0x800) + uint_8 g_usbd_td_buf[TOTAL_QTD_SIZE]; // 1280 + #endif + + + /* flag status for td */ + static struct _td_status + { + uint_8 status; // DTD_BUSY or DTD_FREE + unsigned int total_bytes; // Original total bytes to transfer (not used by EP0) + volatile struct dtd_setup_t *phys_td; // Pointer to physical TD (not used by EP0) + } g_usbd_td_flag[MAX_ENDPOINT_NUMBER * 2][MAX_DTDS_PER_EP]; + static struct dtd_setup_t *g_usbd_qh_tail[MAX_ENDPOINT_NUMBER * 2]; +#endif // HIGH_SPEED_DEVICE + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +static void USB_Bus_Reset_Handler(void); +#if !HIGH_SPEED_DEVICE +static uint_8 USB_DCI_Get_BDT_Index(uint_8 ep_num, + uint_8 direction, + boolean odd); +static uint_8 USB_DCI_Validate_Param(uint_8 ep_num, + uint_8 direction, + boolean odd); +#ifdef LONG_SEND_TRANSACTION +static void USB_DCI_Prepare_Send_Data(P_BUFF_DSC buffer_dsc, + P_BDT_ELEM bdt_elem); +#endif /* LONG_SEND_TRANSACTION */ +static void USB_Bus_Token_Cpl_Handler(uint_8 stat, + USB_DEV_EVENT_STRUCT* event); +#endif /* HIGH_SPEED_DEVICE */ + +// HIGH_SPEED_DEVICE +#if HIGH_SPEED_DEVICE +static uint_8 K70_ULPI_SetDeviceMode(uint_8 controller_ID); +static void usbd_ep_qh_init(uint_8 controller_ID, + unsigned char endpt_number, unsigned char direction, + unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult, uint_32 next_dtd); +static void usbd_setup_qhead(struct dqh_t *qhead); +static void usbd_setup_td(struct dtd_t *td); +static unsigned int usbd_get_dqh(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction); +static void usbd_ep_setup(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned char ep_type); +static void usbd_ep_complete_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_setup_packet_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_read_setup_packet(uint_8 controller_ID, unsigned char *setup_packet); +static void usbd_port_change( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_ep0_complete(USB_DEV_EVENT_STRUCT* event); +static void usbd_dtd_complete(USB_DEV_EVENT_STRUCT* event); +static usb_status_t usbd_receive_data_ep0out(uint_8 controller_ID, unsigned int ep0_data_buffer, unsigned int sz); +static usb_status_t usbd_receive_data_epxout(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz); +static void usbd_add_td(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td); +static void usbd_prime_ep(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td); +static usb_status_t usbd_send_data_epxin(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz); +static usb_status_t usbd_send_data_ep0in(uint_8 controller_ID, + unsigned int ep0_data_buffer, unsigned int sz, + unsigned char zlt_enable); + +#endif +#ifdef USB_LOWPOWERMODE + static void Enter_StopMode(STOP_MODE stop_mode); +#endif +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_Bus_Reset_Handler + * + * @brief The function handles Bus Reset Interrupt + * + * @param None + * + * @return None + * + ****************************************************************************** + * This functions is called when USB Bus Reset event is received on USB Bus. + * This function clears all the errors conditions and reinit Global data + * structures. Also resets USB device controller. + *****************************************************************************/ +static void USB_Bus_Reset_Handler (void) +{ +#if !HIGH_SPEED_DEVICE + USB0_ERRSTAT = ERR_STAT_CLEAR_ALL; /* clear USB error flag */ + USB0_CTL |= USB_CTL_ODDRST_MASK; /* Reset to Even buffer */ + USB0_ADDR = 0; /* reset to default address */ + /* Select System Clock and Disable Weak Pull Downs */ + USB0_USBCTRL = 0x00; + + /* Clear bdt elem structure */ + Clear_Mem((uint_8_ptr)(g_bdt_elem), + (sizeof(BDT_ELEM) * (MAX_BDT_INDEX >> 1)), + (uint_8)UNINITIALISED_VAL); + + /* Clear Memory for BDT and buffer Data */ + Clear_Mem((uint_8_ptr)g_bdtmap,(uint_32) BYTES_1024, (uint_8)0); + + /* Initialize BDT buffer address */ + g_bdt_address = ((uint_32)g_bdtmap + BYTES_512); + + g_trf_direction = USB_TRF_UNKNOWN; + + USB0_CTL &= ~USB_CTL_ODDRST_MASK; + USB0_USBTRC0 |= 0x40; /* attach CFv1 core to USB bus */ + + USB0_ERREN = ERR_ENB_ENABLE_ALL; /* Enable All Error Interrupts */ + USB0_INTEN = INTENB_BUS_RESET_VAL; /* Enable All Interrupts except RESUME */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + +#else + uint_32 reg; + + //Clear the device address + USBHS_DEVICEADDR &= ~USBHS_DEVICEADDR_USBADR_MASK; + + // 1. Clear all setup token semaphores + reg = USBHS_EPSETUPSR; + USBHS_EPSETUPSR = reg; + + // 2. Clear all the endpoint complete status bits + reg = USBHS_EPCOMPLETE; + USBHS_EPCOMPLETE = reg; + + // 3. Cancel all primed status + while(USBHS_EPPRIME); + USBHS_EPFLUSH = 0xFFFFFFFF; + + // 4. If reset bit is not cleared at this point force reset device + if(!(USBHS_PORTSC1 & USBHS_PORTSC1_PR_MASK)){ + USBHS_USBCMD |= USBHS_USBCMD_RST_MASK; + } + + // 5. Free(reset) all allocated dTDs + memset(g_usbd_td_buf, 0, TOTAL_QTD_SIZE); + memset(g_usbd_td_flag, + 0, + MAX_ENDPOINT_NUMBER * 2 * MAX_DTDS_PER_EP * sizeof(g_usbd_td_flag)/sizeof(*g_usbd_td_flag) + ); + + g_trf_direction = USB_TRF_UNKNOWN; + UNUSED(g_trf_direction); +#endif +} + +#if !HIGH_SPEED_DEVICE +/**************************************************************************//*! + * + * @name USB_DCI_Get_BDT_Index + * + * @brief The function maps endpoint number and direction to bdt index + * + * @param ep_num : Endpoint Number + * @param direction: Endpoint direction + * @param odd : Odd or even buffer + * + * @return bdt index : Mapped bdt index + * INVALID_BDT_INDEX : In case of error + * + ****************************************************************************** + * This function returns BDT Index from Endpoint number, direction, + * odd/even buffer + *****************************************************************************/ +static uint_8 USB_DCI_Get_BDT_Index ( + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8 direction, /* [IN] Endpoint direction */ + boolean odd /* [IN] Odd or even buffer */ +) +{ + uint_8 bdt_index = INVALID_BDT_INDEX; + + if(ep_num < MAX_SUPPORTED_ENDPOINTS) + { + /* per endpoint 4 bdt_index -- 2 for recv 2 for send */ + bdt_index=(uint_8)((ep_num * 4) + (uint_8)odd); + + if(direction == USB_SEND) + { + bdt_index += 2; + } + } + return bdt_index; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Validate_Param + * + * @brief The function validates endpoint number & direction parameters + * and returns bdt index. + * + * @param ep_num : Endpoint Number + * @param direction: Endpoint direction + * @param odd : odd or even buffer + * + * @return bdt index : mapped bdt index + * INVALID_BDT_INDEX : incase of error + * + ****************************************************************************** + * This function validates endpoint parameters and returns bdt index + *****************************************************************************/ +static uint_8 USB_DCI_Validate_Param ( + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8 direction, /* [IN] Endpoint direction */ + boolean odd /* [IN] Odd or even buffer */ +) +{ + /* Get bdt index mapped to endpoint number-direction and odd/even buffer */ + uint_8 bdt_index = USB_DCI_Get_BDT_Index(ep_num, direction, odd); + + if((bdt_index != INVALID_BDT_INDEX) && + (g_bdt_elem[TRANSFER_INDEX(bdt_index)].len == + (uint_16)UNINITIALISED_VAL)) + { + /* Incase length in bdt_elem is uninitialised return invalid index */ + bdt_index = INVALID_BDT_INDEX; + } + return bdt_index; +} +#endif /* HIGH_SPEED_DEVICE */ + +#ifdef LONG_SEND_TRANSACTION +#if !HIGH_SPEED_DEVICE +/**************************************************************************//*! + * + * @name USB_DCI_Prepare_Send_Data + * + * @brief The function sets up the BDT for Send + * + * @param buffer_dsc : Pointer to buffer descriptor element in USB_RAM + * @param bdt_elem : Pointer to per endpoint/direction structure + * + * @return None + * + ****************************************************************************** + * This functions configures Buffer Descriptor (Address and Count) + *****************************************************************************/ +static void USB_DCI_Prepare_Send_Data ( + P_BUFF_DSC buffer_dsc, /* [OUT] Pointer to buffer descriptor + element in USB_RAM */ + P_BDT_ELEM bdt_elem /* [IN] Pointer to per endpoint/direction + structure */ +) +{ + uint_8_ptr buff_ptr = bdt_elem->app_buffer + bdt_elem->curr_offset; + uint_16 current_count = 0; + + /* adjust size based on the input at the init endpoint */ + if((bdt_elem->app_len - bdt_elem->curr_offset) > bdt_elem->len) + { + /* If size of packet is greater than endpoint buffer size */ + current_count = bdt_elem->len; + } + else + { + /* If size of packet is smaller than endpoint buffer size */ + current_count = (uint_16)(bdt_elem->app_len - bdt_elem->curr_offset); + } + + buffer_dsc->cnt = SWAP16(current_count); + + buffer_dsc->addr = SWAP32((uint_32)buff_ptr); +} +#endif /* HIGH_SPEED_DEVICE */ +#endif /* LONG_SEND_TRANSACTION */ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_DCI_Init + * + * @brief The function initializes the Controller layer + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : Always + ****************************************************************************** + * Initializes the USB controller + *****************************************************************************/ +uint_8 USB_DCI_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ +#if !HIGH_SPEED_DEVICE +#if USB_USER_CONFIG_USE_STACK_INIT + /* Select System Clock and Disable Weak Pull Downs */ + USB0_USBCTRL = 0x00; +#endif + + /* save the controller_ID for future use */ + g_dci_controller_Id = controller_ID; + + /* Clear bdt elem structure */ + Clear_Mem((uint_8_ptr)(g_bdt_elem), + (sizeof(BDT_ELEM) * (MAX_BDT_INDEX >> 1)), + (uint_8)UNINITIALISED_VAL); + g_bdtmap = (BDTMAP *)((uint_32)g_Mem); + + /* Clear Memory for BDT and buffer Data */ + Clear_Mem((uint_8_ptr)g_bdtmap,(uint_32) BYTES_1024, (uint_8)0); + + #ifndef OTG_BUILD + #if 1 /* hardware bug workaround */ /* << EST: need to keep this workaround for FRDM-KL25Z */ + /* Hard Reset to the USB Module */ + USB0_USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + + /* loop till the Reset bit clears */ + while((USB0_USBTRC0 & USB_USBTRC0_USBRESET_MASK)) + { + }; + #if !USB_USER_CONFIG_USE_STACK_INIT + { + /* need to re-init USB, as the hard reset above has reset the whole module! */ + void USB0_Init(void); /* prototype */ + USB0_Init(); /* call Processor Expert Init_USB_OTG Init() */ + } + #endif + + #endif + #endif + + g_trf_direction = USB_TRF_UNKNOWN; + +#if USB_USER_CONFIG_USE_STACK_INIT + /* Asynchronous Resume Interrupt Enable */ + USB0_USBTRC0 |= 0x40; /* undocumented bit???? */ +#endif + if(bVregEn) + { + SIM_SOPT1 |= SIM_SOPT1_USBREGEN_MASK; // enable usb voltage regulator + } + else + { + SIM_SOPT1 &= ~SIM_SOPT1_USBREGEN_MASK; // disable usb voltage regulator + } + + /* Set the BDT Table address, Need to be on 512 byte boundary */ + /* D8 Bit is masked in BDT_PAGE_01 */ + USB0_BDTPAGE1 = (uint_8)(((uint_32)g_bdtmap >> 8)& 0xFE); + USB0_BDTPAGE2 = (uint_8)((uint_32)g_bdtmap >> 16); + USB0_BDTPAGE3 = (uint_8)((uint_32)g_bdtmap >> 24); + + /* Initialized BDT buffer address */ + g_bdt_address = ((uint_32)g_bdtmap + BYTES_512); + +#if USB_USER_CONFIG_USE_STACK_INIT + #ifndef OTG_BUILD + /* Pull Up configuration */ + USB0_CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK; + #endif +#endif + USB0_CTL = USB_CTL_USBENSOFEN_MASK; /* Enable USB module */ + USB0_ISTAT = INT_STAT_CLEAR_ALL; /* Clear USB interrupts*/ + + /* Remove suspend state */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + +#if USB_USER_CONFIG_USE_STACK_INIT + /* Enable USB RESET Interrupt */ + USB0_INTEN |= USB_INTEN_USBRSTEN_MASK; + + /* Enable USB Sleep Interrupt */ + USB0_INTEN |= USB_INTEN_SLEEPEN_MASK; + + USB0_OTGCTL = USB_OTGCTL_DPHIGH_MASK | USB_OTGCTL_OTGEN_MASK; +#endif /* USB_USER_CONFIG_USE_STACK_INIT */ +#else // HIGH_SPEED_DEVICE + /* save the controller_ID for future use */ + g_dci_controller_Id = controller_ID; + memset(g_usbd_qh_buf, 0, TOTAL_QHD_SIZE); + memset(g_usbd_td_buf, 0, TOTAL_QTD_SIZE); + + // initialize module in device mode + uint_8 status; + status = K70_ULPI_SetDeviceMode(controller_ID); + if(status != USB_OK) + return status; + + // initialize endpoint 0 + usbd_ep_qh_init(controller_ID, EP0, IN, 64, 0, 0, 1); + usbd_ep_qh_init(controller_ID, EP0, OUT, 64, 0, 0, 1); + + // setup interrupts + USBHS_USBINTR = USBHS_USBINTR_UE_MASK // USB interrupt + | USBHS_USBINTR_UEE_MASK // USB error + | USBHS_USBINTR_PCE_MASK // Port change + | USBHS_USBINTR_URE_MASK // Reset enable + | USBHS_USBINTR_SRE_MASK // SOF received + | USBHS_USBINTR_SLE_MASK // suspend received + | USBHS_USBINTR_SEE_MASK; // System error + + // enable pullup on DP and initiate attach event + USBHS_USBCMD |= USBHS_USBCMD_RS_MASK; +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_DeInit + * + * @brief The function de-initializes the Controller layer + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : Always + ****************************************************************************** + * Initializes the USB controller + *****************************************************************************/ +uint_8 USB_DCI_DeInit(void) +{ +#if !HIGH_SPEED_DEVICE + +#ifdef MCU_MK70F12 +#if 0 /* hardware bug workaround */ + // Reset module + USB0_USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + + // Wait for reset to complete + while((USB0_USBTRC0 & USB_USBTRC0_USBRESET_MASK)); +#endif + +#else + /* Detach CFv1 core to USB bus*/ + USB0_USBTRC0 &= ~0x40; +#endif + + + /* Clear USB interrupts*/ + USB0_ISTAT = INT_STAT_CLEAR_ALL; + + /* Disable USB RESET Interrupt */ + USB0_INTEN &= ~USB_INTEN_USBRSTEN_MASK; + + /* Disable USB module */ + USB0_CTL &= ~USB_CTL_USBENSOFEN_MASK; + + USB0_OTGCTL &= ~(USB_OTGCTL_DPHIGH_MASK | USB_OTGCTL_OTGEN_MASK); +#else // HIGH_SPEED_DEVICE + +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Init_EndPoint + * + * @brief The function initializes an endpoint + * + * @param controller_ID : Controller ID + * @param ep_ptr : Pointer to EndPoint Structures + * @param flag : Zero Termination + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_INIT_FAILED : When Error + ****************************************************************************** + * + * This function initializes an endpoint and the Bufffer Descriptor Table + * entry associated with it. Incase the input parameters are invalid it will + * return USBERR_EP_INIT_FAILED error. + * + *****************************************************************************/ +uint_8 USB_DCI_Init_EndPoint ( + uint_8 controller_ID,/* [IN] Controller ID */ + USB_EP_STRUCT_PTR ep_ptr, /* [IN] Pointer to Endpoint structure, + (endpoint number, + endpoint type, + endpoint direction, + max packet size) */ + boolean flag /* [IN] Zero Termination */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_8 bdtmap_index; + uint_8 bdtelem_index; + uint_8 ep_num = ep_ptr->ep_num; + uint_8 direction = ep_ptr->direction; + uint_32 ep_ctrl[2] = {EP_OUT, EP_IN}; + P_BUFF_DSC temp; + P_BDT_ELEM bdt_elem; + UNUSED(controller_ID); + + /* if the max packet size is greater than the max buffer size */ + if(ep_ptr->size > MAX_EP_BUFFER_SIZE) + { + ep_ptr->size = MAX_EP_BUFFER_SIZE; + } + + /* Get the bdt index correspoding to the endpoint */ + bdtmap_index = USB_DCI_Get_BDT_Index(ep_num, direction, + USB_RAM_EVEN_BUFFER); + bdtelem_index = (uint_8)TRANSFER_INDEX(bdtmap_index); + + /* + incase the bdtmap_index is invalid + or already initialised return with an error + */ + if((bdtmap_index == INVALID_BDT_INDEX) || + (g_bdt_elem[bdtelem_index].len != (uint_16)UNINITIALISED_VAL) || + (ep_ptr->type > USB_INTERRUPT_PIPE) || + (ep_ptr->direction > USB_SEND)) + { + return USBERR_EP_INIT_FAILED; + } + + bdt_elem = &g_bdt_elem[bdtelem_index]; + /* Reset Handler resets bdtmap_index to UNINITIALISED_VAL */ + if(bdt_elem->bdtmap_index == (uint_8)UNINITIALISED_VAL) + { + bdt_elem->bdtmap_index = 0; + } + + /* update bdt element structure */ + bdt_elem->len = (uint_16)ep_ptr->size; + bdt_elem->flag = flag; + /* preserving even/odd buffer bit */ + bdt_elem->bdtmap_index &= 0x01; + bdt_elem->bdtmap_index |= ((direction << 1) | (ep_num << 2)); + bdt_elem->addr = g_bdt_address; + bdt_elem->type = ep_ptr->type; + bdt_elem->direction = direction; + + temp = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + + /* Update BDTMAP for endpoint's EVEN Buffer */ + temp->cnt = SWAP16((uint_16)ep_ptr->size); + temp->addr = SWAP32(g_bdt_address); + temp->Stat._byte = (_CPU | _DATA0 | _DTS); + + /* Update BDTMAP for endpoint's ODD Buffer */ + temp = &g_bdtmap->ep_dsc[(uint8)((bdt_elem->bdtmap_index) ^ 1)]; + + temp->cnt = SWAP16((uint_16)ep_ptr->size); + temp->addr = SWAP32(g_bdt_address); + temp->Stat._byte = (_CPU | _DATA1 | _DTS); + + /* update the buffer address for the next endpoint */ + g_bdt_address += ep_ptr->size; + + if(direction == USB_RECV) + { + /* + For Recv Endpoints + Give SIE Control to DATA0 + */ + temp = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + temp->Stat._byte |= _SIE; + } + + /* enable handshake for Non-Isochronous Endpoints */ + ep_ctrl[direction] |= ((ep_ptr->type != USB_ISOCHRONOUS_PIPE) ? + HSHK_EN:0x00); + /* set the EndPoint Control MCU Register*/ + *((&USB0_ENDPT0) + (4 * ep_num)) |= ep_ctrl[direction]; +#else /* HIGH_SPEED_DEVICE */ + unsigned char mult; + + /* No need to initialize EP0 */ + if(ep_ptr->ep_num == CONTROL_ENDPOINT) + return USB_OK; + + switch (ep_ptr->type & 0x3) { + case EP_TRANSFER_TYPE_CONTROL: + case EP_TRANSFER_TYPE_BULK: + case EP_TRANSFER_TYPE_INTERRUPT: + mult = 0; + break; + case EP_TRANSFER_TYPE_ISOCHRONOUS: + /* Calculate the ISO transfer High-Bandwidth Pipe Multiplier + * The ISO endpoints, must set Mult 1, 2, 3 for high speed + * and only 1 for full speed + */ +#ifdef ULPI_FORCE_FULLSPEED + mult = 1; +#else + mult = (unsigned char)(1 + (((ep_ptr->size) >> 11) & 0x03)); +#endif + } + + /* setup dQH */ + usbd_ep_qh_init(controller_ID, ep_ptr->ep_num, ep_ptr->direction, ep_ptr->size, flag, mult, 0xDEAD0001); + + /* enable endpoint */ + usbd_ep_setup(controller_ID, ep_ptr->ep_num, ep_ptr->direction, ep_ptr->type); +#endif /* HIGH_SPEED_DEVICE */ + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Cancel_Transfer + * + * @brief The function cancels any pending Transfers which ahve not been sent + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USBERR_NOT_SUPPORTED : Always + ****************************************************************************** + * This function just returns Error Code not supported + *****************************************************************************/ +uint_8 USB_DCI_Cancel_Transfer ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ +#if !HIGH_SPEED_DEVICE +#ifdef LONG_TRANSACTION + uint_8 status= USBERR_UNKNOWN_ERROR; + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + uint_8 bdtelem_index = (uint_8)TRANSFER_INDEX(bdt_index); + UNUSED(handle); + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + P_BDT_ELEM bdt_elem = &g_bdt_elem[bdtelem_index]; + P_BUFF_DSC buffer_dsc = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + P_BUFF_DSC buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index ^ 1]; + /* Clear SIE Control Bit for both buffers*/ + buffer_dsc->Stat._byte &= ~_SIE; + buffer_dsc_alt->Stat._byte &= ~_SIE; + bdt_elem->app_len = (USB_PACKET_SIZE)UNINITIALISED_VAL; + + status = USB_OK; + } + return status; +#else + return USBERR_NOT_SUPPORTED; +#endif +#else // HIGH_SPEED_DEVICE +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif + return USBERR_NOT_SUPPORTED; +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Deinit_EndPoint + * + * @brief The function de initializes an endpoint + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USB_OK : When successfull + * USBERR_EP_DEINIT_FAILED : When unsuccessfull + ****************************************************************************** + * + * This function un-intializes the endpoint by clearing the corresponding + * endpoint control register and then clearing the bdt elem. + * + *****************************************************************************/ +uint_8 USB_DCI_Deinit_EndPoint ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (ep_num, direction, + USB_RAM_EVEN_BUFFER); + uint_8 bdtelem_index = (uint_8)TRANSFER_INDEX(bdt_index); + + /* in case the bdt_index is invalid*/ + if(bdt_index == INVALID_BDT_INDEX) + { + return USBERR_EP_DEINIT_FAILED; + } + USB_DCI_Cancel_Transfer(&controller_ID, ep_num, direction); + /* delete buffer space for both even and odd buffers */ + g_bdt_address -= (g_bdt_elem[bdtelem_index].len); + + /* Disable endpoint */ + *((&USB0_ENDPT0) + (4 * ep_num)) = EP_DISABLE; + + /* un-initialize the bdt_elem structure for this endpoint */ + g_bdt_elem[bdtelem_index].len = (uint_16)UNINITIALISED_VAL; + g_bdt_elem[bdtelem_index].addr = (uint_32)UNINITIALISED_VAL; +#else // HIGH SPEED + uint_32 reg; + + if(ep_num<1) + return USB_INVALID; + + // clear qhd + dqh_setup_t *dqh_word = (dqh_setup_t*)usbd_get_dqh(controller_ID, ep_num, direction); + memset((void *)dqh_word, 0, SIZE_OF_QHD); + + // clear endpoint register + reg = USBHS_EPCR(ep_num-1); + USBHS_EPCR(ep_num-1) &= ~reg; + + // flush endpoint Tx(IN) buffer + if(direction) + USBHS_EPFLUSH |= USBHS_EPFLUSH_FETB(ep_num-1); + // flush endpoint Rx(OUT) buffer + else + USBHS_EPFLUSH |= USBHS_EPFLUSH_FERB(ep_num-1); +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Stall_EndPoint + * + * @brief The function stalls an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function stalls the endpoint by setting Endpoint BDT + *****************************************************************************/ +void USB_DCI_Stall_EndPoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number to stall */ + uint_8 direction /* [IN] Direction to stall */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + bdt_index = bdt_elem->bdtmap_index; + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + (void)USB_DCI_Cancel_Transfer(handle, endpoint_number, direction); + + /* Stall endpoint */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte |= (_SIE | _BDTSTALL); + } +#else // HIGH SPEED + // check if it is control endpoint + if(endpoint_number == 0){ + // stall both directions + USBHS_EPCR0 |= USBHS_EPCR0_TXS_MASK|USBHS_EPCR0_RXS_MASK; + }else{ + + USBHS_EPCR(endpoint_number-1) |= direction?USBHS_EPCR0_TXS_MASK:USBHS_EPCR0_RXS_MASK; + } +#endif + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Unstall_EndPoint + * + * @brief The function unstalls an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function unstalls the endpoint by clearing Endpoint Control Register + * and BDT + *****************************************************************************/ +void USB_DCI_Unstall_EndPoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number to unstall */ + uint_8 direction /* [IN] Direction to unstall */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + bdt_index = bdt_elem->bdtmap_index; + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + volatile ENDPT0STR *endpoint = (volatile ENDPT0STR*)(&USB0_ENDPT0 + (4 * endpoint_number)); + + /* Enable ENDPTx for non control endpoints */ + /* For Control Endpoint the default Value 0x0D */ + if(endpoint_number != CONTROL_ENDPOINT) + { + uint_8 endpt; + /* Enable handshaking for non isochronous endpoint */ + endpt = (uint_8)((bdt_elem->type != USB_ISOCHRONOUS_PIPE) ? + HSHK_EN:0); + /* + Enable the endpoint in the specified direction and disable + control tranfers (valid only in case the endpoint is + bidirectional) + */ + endpt |= (uint_8)(EP_CTL_DIS | + ((direction == USB_SEND)?EP_IN:EP_OUT)); + endpoint->Byte |= endpt; + } + /* Clear Endpoint Stall bit is endpoint control register */ + endpoint->Bits.EP_STALL = 0; + + /* Unstall endpoint by clearing stall bit in BDT */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte &= ~(_SIE | _BDTSTALL); + /* We Require DATA0 PID to be zero on unstall */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte = _DATA0; + if(direction == USB_RECV) + { + /* Initiate Next receive Transfer */ + USB_DCI_Recv_Data(handle, endpoint_number, NULL, 0); + } + } +#else + // todo //: Dieses To-do hatte kein Kommentar - ist das noch notwendig? (LH) + // This function unstalls the endpoint by clearing Endpoint Control Register + // and QH + if(endpoint_number == 0){ + // unstall both directions + USBHS_EPCR0 &= ~(direction ? USBHS_EPCR0_TXS_MASK:USBHS_EPCR0_RXS_MASK); + }else{ + USBHS_EPCR(endpoint_number-1) &= ~(direction?USBHS_EPCR_TXS_MASK:USBHS_EPCR_RXS_MASK); + } +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif +#endif + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Get_Setup_Data + * + * @brief The function copies Setup Packet from USB RAM to application buffer + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * + * @return None + * + ****************************************************************************** + * Copies setup packet from USB RAM to Application Buffer + *****************************************************************************/ +void USB_DCI_Get_Setup_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number for the transaction */ + uint_8_ptr buffer_ptr /* [IN] Pointer to the buffer into which to read data */ +) +{ + +#if !HIGH_SPEED_DEVICE + uint_8_ptr addr; + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_RECV, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + UNUSED(handle); + bdt_index = bdt_elem->bdtmap_index; + + /* address correponding to the endpoint */ + addr = (uint_8_ptr)SWAP32(g_bdtmap->ep_dsc[bdt_index].addr); + + /* copy bdt buffer to application buffer */ + (void)memcpy(buffer_ptr, addr, USB_SETUP_PKT_SIZE); + return; +#else // HIGH SPEED +#if USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Get_Transfer_Status + * + * @brief The function retrieves the Transfer status of an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USBERR_TR_FAILED : When unsuccessful + * USB_STATUS_IDLE : No transfer on endpoint + * USB_STATUS_DISABLED : endpoint is disabled + * USB_STATUS_STALLED : endpoint is stalled + * USB_STATUS_TRANSFER_IN_PROGRESS : When SIE has control of BDT + ****************************************************************************** + * + * This function retrieves the transfer status of the endpoint by checking the + * BDT as well as the endpoint control register + * + *****************************************************************************/ +uint_8 USB_DCI_Get_Transfer_Status ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ + uint_8 status = USB_STATUS_DISABLED; + +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + UNUSED(handle); + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + uint_8 ep_control = (uint_8)(*((&USB0_ENDPT0)+4*endpoint_number)); + + status = USB_STATUS_IDLE; + + /* Check for direction in endpoint control register */ + if((ep_control & (EP_IN|EP_OUT)) == EP_DISABLE) + { + status = USB_STATUS_DISABLED; + } + /* Check for stall bit in endpoint control register */ + else if((ep_control & EPCTL_STALL) == EPCTL_STALL) + { + status = USB_STATUS_STALLED ; + } + /* Check whether SIE has control of BDT */ + else if((g_bdtmap->ep_dsc[bdt_index].Stat.SieCtlBit.own == 1) + || (g_bdtmap->ep_dsc[bdt_index ^ 1].Stat.SieCtlBit.own == 1)) + { + status = USB_STATUS_TRANSFER_IN_PROGRESS; + } + } +#else +#if USART_DEBUG + printf("%s, ep_num is %d\n", __func__, endpoint_number); +#endif /* USART_DEBUG */ + status = USB_OK; +#endif /* HIGH_SPEED_DEVICE */ + return status; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Clear_DATA0_Endpoint + * + * @brief The function clear the DATA0/1 bit + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function clear the DATA0/1 bit + *****************************************************************************/ +void USB_DCI_Clear_DATA0_Endpoint ( + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ + +#if !HIGH_SPEED_DEVICE + + uint_8 bdt_index = USB_DCI_Validate_Param(endpoint_number, direction, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + bdt_index = bdt_elem->bdtmap_index; + + /*Check for a valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + //ENDPT0STR *endpoint = (ENDPT0STR*)(&USB0_ENDPT0 + (4 * endpoint_number)); /* << EST not used */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte = _DATA0; + } + return; +#else // HIGH SPEED +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Recv_Data + * + * @brief The function retrieves data received on an RECV endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * @param size : Size of the buffer + * + * @return status + * USB_OK : When successful + * USBERR_RX_FAILED : When unsuccessful + ****************************************************************************** + * This function retrieves data received data on a RECV endpoint by copying it + * from USB RAM to application buffer + *****************************************************************************/ +uint_8 USB_DCI_Recv_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number for the transaction */ + uint8_ptr buffer_ptr, /* [OUT] Pointer to the buffer into which to receive data */ + uint_32 size /* [IN] Number of bytes to receive */ +) +{ + uint_8 status = USBERR_RX_FAILED; +#if !HIGH_SPEED_DEVICE + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_RECV, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + UNUSED(handle); + + /* For selecting even/odd buffer */ + bdt_index = bdt_elem->bdtmap_index; + + if(bdt_index != INVALID_BDT_INDEX) + { + P_BUFF_DSC buffer_dsc = &g_bdtmap->ep_dsc[bdt_index ^ 1]; + P_BUFF_DSC buffer_dsc_alt = NULL; + + /* Check for valid bdt index */ + if(bdt_elem->len != (uint_16)UNINITIALISED_VAL) + { + /* Does MCU owns it */ + if(buffer_dsc->Stat.SieCtlBit.own == FALSE) + { + if(size == 0) + { + /* + Give control to the other buffer to recv the next + packet + */ + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt->cnt = SWAP16(bdt_elem->len); + buffer_dsc_alt->addr = SWAP32(bdt_elem->addr); + + /* Give the ownership to SIE and TOGGLE DATA BIT */ + buffer_dsc_alt->Stat._byte = (uint_8)( + (buffer_dsc_alt->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + return USB_OK; + } + /* adjust size based on the input at the init endpoint */ +#ifdef LONG_RECEIVE_TRANSACTION + /* Initialise transfer */ + bdt_elem->app_len = size; + bdt_elem->app_buffer = buffer_ptr; +#endif + if(size > bdt_elem->len) + { + size = bdt_elem->len; + } + +#ifdef LONG_RECEIVE_TRANSACTION + bdt_elem->curr_offset = 0; +#endif + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt->cnt = SWAP16(size); + buffer_dsc_alt->addr = SWAP32((uint_32)buffer_ptr); + buffer_dsc_alt->Stat._byte = (uint_8)( + (buffer_dsc_alt->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + status = USB_OK; + } + } + } + return status; +#else + if(endpoint_number != 0) + { + status = usbd_receive_data_epxout(0, (unsigned int)buffer_ptr, endpoint_number, size); + } + else + status = usbd_receive_data_ep0out(0, (unsigned int)buffer_ptr, size); + + if(status != USB_SUCCESS) + { + return USBERR_RX_FAILED; + } + else + { + return USB_OK; + } +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Send_Data + * + * @brief The function configures Controller to send data on an SEND endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * @param size : Size of the buffer + * + * @return status + * USB_OK : When successfull + * USBERR_TX_FAILED : When unsuccessfull + ****************************************************************************** + * This function configures Controller to send data on a SEND endpoint by + * setting the BDT to send data. + *****************************************************************************/ +uint_8 USB_DCI_Send_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint8_ptr buffer_ptr, /* [IN] Application buffer pointer */ + uint_32 size /* [IN] Size of the buffer */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_8 status = USBERR_TX_FAILED; + P_BUFF_DSC buffer_dsc; + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_SEND, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + UNUSED(handle); + + if(bdt_index == INVALID_BDT_INDEX) + return USBERR_TX_FAILED; + + /* Send Data After Toggling Buffer */ + bdt_index = (uint_8)bdt_elem->bdtmap_index; + + buffer_dsc = &g_bdtmap->ep_dsc[bdt_index]; + + /* Does MCU owns it and it is not stalled */ + if(!((buffer_dsc->Stat.SieCtlBit.own) ||/* For MCU: own is 0 */ + (*(&USB0_ENDPT0 + (endpoint_number * 4)) & ENDPT_EP_STALL_MASK))) + { + /* Now configure buffer_dsc->addr and buffer_dsc->cnt */ +#ifdef LONG_SEND_TRANSACTION + /* Initialize transfer */ + bdt_elem->app_len = size; + bdt_elem->app_buffer = buffer_ptr; + bdt_elem->curr_offset = 0; + + /* Prepare for send */ + USB_DCI_Prepare_Send_Data(buffer_dsc, bdt_elem); +#else + buffer_dsc->addr = SWAP32(buffer_ptr); + + /* Adjust size based on the input at the init endpoint */ + if((uint_16)size > bdt_elem->len) + { + buffer_dsc->cnt = SWAP16(bdt_elem->len); + } + else + { + buffer_dsc->cnt = SWAP16((uint_16)size); + } +#endif + if(endpoint_number == CONTROL_ENDPOINT) + { + /* Set up the control endpoint bdt for next packet */ + buffer_dsc->Stat._byte = (_SIE | _DATA1 | _DTS); + } + else + { + buffer_dsc->Stat._byte = (uint_8)( + (buffer_dsc->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + } + + status = USB_OK; + } /* Does MCU own IN BDT */ + return status; +#else // HIGH SPEED + usb_status_t status; + + if(endpoint_number != 0) { + status = usbd_send_data_epxin(0, (unsigned int)buffer_ptr, endpoint_number, size); + } + + /* Send descriptor - Data Phase */ + //zlt is false=>not zero length packet, send dev descriptor to host. + else + status = usbd_send_data_ep0in(0, (unsigned int)buffer_ptr, size, 0); + + if(status != USB_SUCCESS) + return USBERR_TX_FAILED; + + return USB_OK; +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Set_Address + * + * @brief The function configures Controller to send data on an SEND endpoint + * + * @param handle : USB Device handle + * @param address : Controller Address + * + * @return None + * + ****************************************************************************** + * Assigns the Address to the Controller + *****************************************************************************/ +void USB_DCI_Set_Address ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 address /* [IN] Address of the USB device */ +) +{ + + UNUSED(handle); + + /* set the address */ +#if !HIGH_SPEED_DEVICE + USB0_ADDR = address; +#else + USBHS_DEVICEADDR = USBHS_DEVICEADDR_USBADR(address); +#endif + + _usb_device_set_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + USB_STATE_ADDRESS); + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Shutdown + * + * @brief The function shuts down the controller + * + * @param handle : USB Device handle + * + * @return None + * + ****************************************************************************** + * Resets USB Device Controller + *****************************************************************************/ +void USB_DCI_Shutdown ( + _usb_device_handle handle /* [IN] USB Device handle */ +) +{ + UNUSED(handle); +#if !HIGH_SPEED_DEVICE + /* Reset the Control Register */ + USB0_CTL = 0; + /* Initiate Reset in the USB Control0 Register */ + #ifndef OTG_BUILD + + USB0_USBTRC0 = _USBRESET; + #endif + + _usb_device_set_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + USB_STATE_UNKNOWN); + return; +#else +#if USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Assert_Resume + * + * @brief The function makes the Controller start USB RESUME signaling + * + * @param handle : USB Device handle + * + * @return None + * + ****************************************************************************** + * + * This function starts RESUME signalling and then stops it after some delay. + * In this delay make sure that COP is reset. + * + *****************************************************************************/ +void USB_DCI_Assert_Resume ( + _usb_device_handle handle /* [IN] USB Device handle */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_16 delay_count; + + /* Clear SUSP Bit from USB_CTRL */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + + (void)handle; + + /* Reset Low Power RESUME enable */ + USB0_USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + + USB_DCI_WAKEUP + + USB0_CTL |= USB_CTL_RESUME_MASK; /* Start RESUME signaling and make SUSPEND bit 0*/ + + delay_count = ASSERT_RESUME_DELAY_COUNT; /* Set RESUME line for 1-15 ms*/ + + do + { + delay_count--; + Watchdog_Reset(); /* Reset the COP */ + }while(delay_count); + + USB0_CTL &= ~USB_CTL_RESUME_MASK; /* Stop RESUME signalling */ + + return; +#else +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_Bus_Token_Cpl_Handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param stat : BDT stat byte + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +#if !HIGH_SPEED_DEVICE +void USB_Bus_Token_Cpl_Handler ( + uint_8 stat, /* [IN] Value of STAT register */ + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + uint_8 bdt_index = 0 ; + P_BUFF_DSC buffer_dsc = NULL; + P_BUFF_DSC buffer_dsc_alt = NULL;/* stores data of alternate buffer */ + P_BDT_ELEM bdt_elem = NULL; + boolean odd = (boolean)((stat & 0x04) >> 2); + + /* Get the direction from STAT register */ + event->direction = (uint_8)((stat & ENDPOINT_DIRECTION_MASK) >> + ENDPOINT_DIRECTION_SHIFT); + + + /* Get bdt index corresponding to endpoint number and direction */ + bdt_index = USB_DCI_Get_BDT_Index(event->ep_num,event->direction, odd); + + buffer_dsc = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index ^ 1]; + + bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + /* Get address from BDT */ + event->buffer_ptr = (uint_8_ptr)SWAP32(buffer_dsc->addr); + + /* Get len from BDT */ + event->len = SWAP16(buffer_dsc->cnt); + + /* Prepare for Next USB Transaction */ + bdt_index = (uint_8)(bdt_elem->bdtmap_index ^ 1); + bdt_elem->bdtmap_index = bdt_index; + + /* Toggle Data PID*/ + buffer_dsc_alt->Stat._byte = (uint_8)((buffer_dsc->Stat.McuCtlBit.data ^ 1) << 6); + + if(event->direction == USB_SEND) + { + if(event->ep_num == CONTROL_ENDPOINT) + { + /* for Control Endpoint */ + /* For Transfer Direction Host to Device */ + if(g_trf_direction == USB_RECV) + { + /* + Enters here for first time after Set_Address TRANSFER + Completed + */ + /* make Transfer Direction UNKNOWN */ + g_trf_direction = USB_TRF_UNKNOWN; + /* Cancel any pending Transfers on RECV Control Endpoint*/ + USB_DCI_Cancel_Transfer(&(event->controller_ID), (uint_8)CONTROL_ENDPOINT, + (uint_8)USB_RECV); + /* We Require DATA0 PID for Setup Token */ + buffer_dsc_alt->Stat._byte = _DATA0; + /* Prepare for Next SETUP PACKET Receive */ + USB_DCI_Recv_Data(&(event->controller_ID), + CONTROL_ENDPOINT, + NULL,0); + + } + }/* ep_num is CONTROL ENDPOINT */ + +#ifdef LONG_SEND_TRANSACTION + if( (g_trf_direction == USB_SEND) || + (event->ep_num != CONTROL_ENDPOINT) ) + { + /* update the request */ + bdt_elem->curr_offset += event->len; + /* + Initiate next USB SEND if: + 1. More Data is still pending OR + 2. Send Data == Endpoint Size AND + 3. Zero Termination Flag is TRUE + */ + if((bdt_elem->app_len > bdt_elem->curr_offset) || + (((uint_8)event->len == bdt_elem->len) && (bdt_elem->flag == TRUE)) + ) + { + /* send next Req */ + USB_DCI_Prepare_Send_Data(buffer_dsc_alt, bdt_elem); + + /* give the ownership to SIE and TOGGLE DATA BIT */ + buffer_dsc_alt->Stat._byte = (uint_8)( + ((buffer_dsc_alt->Stat.McuCtlBit.data) << 6) | + _SIE | _DTS);; + return; + } + else + { + event->buffer_ptr = bdt_elem->app_buffer; + event->len = bdt_elem->curr_offset; + } + } +#endif + }/* End of SEND loop */ + else /* direction IS USB_RECV */ + { + if(event->ep_num == CONTROL_ENDPOINT) + { + /* for Control Endpoint */ + if(buffer_dsc->Stat.RecPid.pid == USB_SETUP_TOKEN) + { + /* set setup phase */ + event->setup = TRUE; + /* Transfer direction of next packet */ + g_trf_direction = (uint_8)((uint_8) + (event->buffer_ptr[0]) >> 7); + } + else if(g_trf_direction == USB_SEND) + { + /* make Transfer Direction UNKNOWN */ + g_trf_direction = USB_TRF_UNKNOWN; + /* Cancel any pending Transfers on SEND Control Endpoint*/ + USB_DCI_Cancel_Transfer(&(event->controller_ID), (uint_8)CONTROL_ENDPOINT, + (uint_8)USB_SEND); + /* We Require DATA0 PID for Setup Token */ + buffer_dsc_alt->Stat._byte = _DATA0; + /* Prepare for Next SETUP PACKET Receive */ + USB_DCI_Recv_Data(&(event->controller_ID), + CONTROL_ENDPOINT, + NULL,0); + } + } /* ep_num is CONTROL ENDPOINT */ + +#ifdef LONG_RECEIVE_TRANSACTION + /* For NON CONTROL ENDPOINT only */ + if(bdt_elem->app_len != (USB_PACKET_SIZE)UNINITIALISED_VAL) + { + /* on control endpoint the data is only 8 bytes */ + USB_PACKET_SIZE size = event->len; + bdt_elem->curr_offset += size; + + /* + Initiate next USB RECV if: + 1. More Data is still pending OR + 2. Received Data == Endpoint Size AND + 3. Zero Termination Flag is TRUE + */ + if( + ( (size == bdt_elem->len) && + (bdt_elem->app_len > bdt_elem->curr_offset) + ) || + ( (bdt_elem->app_len)&& + (!(bdt_elem->app_len % bdt_elem->len)) && + (bdt_elem->flag == TRUE) + ) + ) + { + /* send next IO */ + uint_16 count; + count = (uint_16)(((bdt_elem->app_len - bdt_elem->curr_offset) + > bdt_elem->len) ? bdt_elem->len : + (bdt_elem->app_len - bdt_elem->curr_offset)); + if(count == 0) + { + /* For Zero byte Packet Receive */ + buffer_dsc_alt->addr = SWAP32(bdt_elem->addr); + buffer_dsc_alt->cnt = 0; + } + else + { + buffer_dsc_alt->addr = SWAP32((uint_32)(bdt_elem->app_buffer + bdt_elem->curr_offset)); + buffer_dsc_alt->cnt = SWAP16(count); + } + + /* give the ownership to SIE and Toggle DATA bit*/ + buffer_dsc_alt->Stat._byte = (uint_8)(( + (buffer_dsc_alt->Stat.McuCtlBit.data) << 6) | + _SIE | _DTS); + return; + } + else /* request completed */ + { + /* populate buffer structure */ + event->buffer_ptr = bdt_elem->app_buffer; + event->len = bdt_elem->curr_offset; + bdt_elem->app_len = (USB_PACKET_SIZE)UNINITIALISED_VAL; + } + } +#endif + } /* End of RECV loop */ + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); + + return; +} +#endif // HIGH_SPEED_DEVICE + +#if HIGH_SPEED_DEVICE +/**************************************************************************//*! + * */ +uint_32 sof_counter = 0; +static uint_32 micro_sof_counter = 0; +void USBHS_ISR(void){ + uint_32 usbsts; + uint_32 reg; + USB_DEV_EVENT_STRUCT event; + + // get interrupt status + reg = USBHS_USBINTR; + usbsts = USBHS_USBSTS & reg; + + // clear interrupt status + USBHS_USBSTS |= usbsts; + + // initialize event structure + event.controller_ID = g_dci_controller_Id; + event.setup = FALSE; + event.buffer_ptr = NULL; + event.len = 0; + event.direction = USB_RECV; + event.errors = NO_ERRORS; + event.ep_num = (uint_8)UNINITIALISED_VAL; + + // handle SOF + if(usbsts & USBHS_USBSTS_SRI_MASK){ + //USBHS_USBSTS |= USBHS_USBSTS_SRI_MASK; +#ifdef ULPI_FORCE_FULLSPEED + sof_counter++; +#else + if(++micro_sof_counter == 8){ + //sof_counter++; + //micro_sof_counter = 0; + } +#endif + } + + // handle Suspend + if(usbsts & USBHS_USBSTS_SLI_MASK){ + USB_Device_Call_Service(USB_SERVICE_SUSPEND, &event); + return; + } + + // handle Bus Reset + if(usbsts & USBHS_USBSTS_URI_MASK){ + // handle reset + USB_Bus_Reset_Handler(); + + // notify device layer + USB_Device_Call_Service(USB_SERVICE_BUS_RESET, &event); + return; + } + + // handle Transaction Complete + if(usbsts & USBHS_USBSTS_UI_MASK){ + if(!USBHS_EPSETUPSR && !USBHS_EPCOMPLETE){ +#ifdef USART_DEBUG + printf("Warning: unexpected UI interrupt\n"); +#endif /* USART_DEBUG */ + } + + // Handle dTD complete interrupt. + // Must process EP complete events first, because setup complete events + // trigger stack to re-prime endpoints. + if(USBHS_EPCOMPLETE) + usbd_ep_complete_handler(&event); + + // Handle setup compete packet interrupt + if(USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(1)) + usbd_setup_packet_handler(&event); + + // + if( (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(2))|| + (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(4))|| + (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(8))){ +#if USART_DEBUG + printf(""); +#endif /* USART_DEBUG */ + } + } + + // handle Port Change + if(usbsts & USBHS_USBSTS_PCI_MASK){ + usbd_port_change(&event); + } + + // handle USB Error + if(usbsts & USBHS_USBSTS_UEI_MASK){ +#ifdef USART_DEBUG + printf("USBHS: Error\n"); +#endif + // Notify Device Layer of ERROR Event to error service + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + } + + // handle USB System Error + if(usbsts & USBHS_USBSTS_SEI_MASK){ +#ifdef USART_DEBUG + printf("USBHS: System Error\n"); +#endif + // Notify Device Layer of ERROR Event to error service + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + } + +} +#endif // HIGH_SPEED_DEVICE + +/**************************************************************************//*! + * + * @name USB_ISR + * + * @brief The function handles USB interrupts on the bus. + * + * @param None + * + * @return None + * + ****************************************************************************** + * This function is hooked onto interrupt 69 and handles the USB interrupts. + * After handling the interrupt it calls the Device Layer to notify it about + * the event. + *****************************************************************************/ +#if !HIGH_SPEED_DEVICE +void USB_ISR(void) +{ + /* Which interrupt occured and also was enabled */ + uint_8 v1 = USB0_ISTAT; + uint_8 v2 = USB0_INTEN; + uint_8 intr_stat = (uint_8)(v1 & v2); + uint_8 stat = (uint_8)USB0_STAT; + USB_DEV_EVENT_STRUCT event; + uint_8 dev_state = USB_STATUS_UNKNOWN; + + /* initialize event structure */ + event.controller_ID = g_dci_controller_Id; + event.setup = FALSE; + event.buffer_ptr = NULL; + event.len = 0; + event.direction = USB_RECV; + event.errors = NO_ERRORS; + + event.ep_num = (uint_8)UNINITIALISED_VAL; + + /* Get the device state from the Device Layer */ + (void)_usb_device_get_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + &dev_state); + + /* if current device state is SUSPEND and Low Power Resume Flag set */ + if((USB0_USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) && (dev_state == USB_STATE_SUSPEND)) + { + /* Clear SUSP Bit from USB_CTRL */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + + /* Reset Low Power RESUME enable */ + USB0_USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + } + + /* SOF received */ + if(SOF_TOKEN_FLAG(intr_stat)) + { + uint_16 sof_count; + uint_16 tmp1, tmp2, tmp3; + tmp1 = USB0_FRMNUMH; + tmp2 = FRAME_HIGH_BYTE_SHIFT; + tmp3 = USB0_FRMNUML; + /* Clear SOF Interrupt */ + USB0_ISTAT = USB_ISTAT_SOFTOK_MASK; + sof_count = (uint_16)((tmp1 << tmp2) | tmp3); + /*address of Lower byte of Frame number*/ + event.buffer_ptr = (uint_8_ptr)(&sof_count); + /* Notify Device Layer of SOF Event */ + (void)USB_Device_Call_Service(USB_SERVICE_SOF, &event); + +#ifdef USE_FEEDBACK_ENDPOINT + // set feedback rate info number + if(gNrSamples!=0) + feedback_data = gNrSamples; + gNrSamples = 0; +#endif + } + + if(BUS_RESET_FLAG(intr_stat)) + { + /* Clear Reset Flag */ + USB0_ISTAT = USB_ISTAT_USBRST_MASK; + + /* Handle RESET Interrupt */ + USB_Bus_Reset_Handler(); + + /* Notify Device Layer of RESET Event */ + (void)USB_Device_Call_Service(USB_SERVICE_BUS_RESET, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + + /* No need to process other interrupts */ + return; + } + + if(TOKEN_COMPL_FLAG(intr_stat)) + { + /* Clear TOKEN Interrupt */ + USB0_ISTAT = USB_ISTAT_TOKDNE_MASK; + + event.ep_num = (uint_8)((stat & ENDPOINT_NUMBER_MASK) >> + ENDPOINT_NUMBER_SHIFT); + + USB_Bus_Token_Cpl_Handler(stat, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + + if(ERROR_FLAG(intr_stat)) + { + /* Clear ERROR Interrupt */ + USB0_ISTAT = USB_ISTAT_ERROR_MASK; + + v1 = USB0_ERRSTAT; + v2 = USB0_ERREN; + event.errors = (uint_8)(v1 & v2); + + /* Notify Device Layer of ERROR Event to error service */ + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + + USB0_ERRSTAT = ERR_STAT_CLEAR_ALL; /*clear all errors*/ + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + + if(SLEEP_FLAG(intr_stat)) + { + /* Clear RESUME Interrupt if Pending */ + USB0_ISTAT = USB_ISTAT_RESUME_MASK; + + /* Clear SLEEP Interrupt */ + USB0_ISTAT = USB_ISTAT_SLEEP_MASK; + + /* Notify Device Layer of SLEEP Event */ + (void)USB_Device_Call_Service(USB_SERVICE_SLEEP, &event); + + /* Set Low Power RESUME enable */ + USB0_USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; + + /* Set SUSP Bit in USB_CTRL */ + USB0_USBCTRL |= USB_USBCTRL_SUSP_MASK; + + /* Enable RESUME Interrupt */ + USB0_INTEN |= USB_INTEN_RESUMEEN_MASK; +#ifdef USB_LOWPOWERMODE + /* Enter Stop3 Mode*/ + Enter_StopMode(STOP_MODE3); +#endif + } + + if(RESUME_FLAG(intr_stat)) + { + /* Clear RESUME Interrupt */ + USB0_ISTAT = USB_ISTAT_RESUME_MASK; + + /* Notify Device Layer of RESUME Event */ + (void)USB_Device_Call_Service(USB_SERVICE_RESUME, &event); + + /* Disable RESUME Interrupt */ + USB0_INTEN &= ~USB_INTEN_RESUMEEN_MASK; + } + + if(STALL_FLAG(intr_stat)) + { + uint_8 endp_status; + event.ep_num = (uint_8)UNINITIALISED_VAL; + + /* If Control Endpoint is stalled then unstall it. + For other endpoints host issues clear endpoint feature request + to unstall them */ + + /* Get Control Endpoint Status*/ + (void)_usb_device_get_status(&(event.controller_ID), + (USB_STATUS_ENDPOINT|CONTROL_ENDPOINT), + &endp_status); + if(endp_status == USB_STATUS_STALLED) + { + event.ep_num = CONTROL_ENDPOINT; + event.direction = USB_SEND; + } + + /* Clear STALL Interrupt */ + USB0_ISTAT = USB_ISTAT_STALL_MASK; + + /* Notify Device Layer of STALL Event */ + (void)USB_Device_Call_Service(USB_SERVICE_STALL, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + return; +} +#endif // HIGH_SPEED_DEVICE + +/**************************************************************************//*! + * + * @name Clear_Mem + * + * @brief The function clears memory starting from start_addr till count bytes + * + * @param start_addr : Buffer Start address + * @param count : Count of Bytes + * @param val : Value to be set + * + * @return None + ****************************************************************************** + * This function is an implementation of memset + *****************************************************************************/ +void Clear_Mem ( + uint_8_ptr start_addr, /* [OUT] Buffer Start address */ + uint_32 count, /* [IN] Count of Bytes */ + uint_8 val /* [IN] Value to be set */ +) +{ + (void)memset(start_addr, val, count); + return; +} + +#ifdef USB_LOWPOWERMODE +/**************************************************************************//*! + * + * @name Enter_StopMode + * + * @brief The function configures STOP Mode + * + * @param stop_mode : STOP MODE to be entered + * + * @return None + ****************************************************************************** + * This function configures different STOP MODES defined by the controller. + * Used to put controller into low power mode. Only STOP MODE 3 is implemented + *****************************************************************************/ +static void Enter_StopMode(STOP_MODE stop_mode) +{ + switch(stop_mode) + { + case STOP_MODE1: + /* + We enter Default Stop Mode + */ + break; + case STOP_MODE2: + /* Save IO Pin Status in a global variable + IO Pin Status is to be restored at POR. + Check if PPDC + */ + /* Set PPDC */ + break; + case STOP_MODE3: + /* Clear PPDC */ + SPMSC2_PPDC = 0; + /* Disable Low Voltage Detect */ + SPMSC1_LVDSE = 0; + break; + case STOP_MODE4: + break; + } + /* Enter STOP Mode*/ + _Stop; +} + +#endif + + +/* HIGH_SPEED_DEVICE */ +#if HIGH_SPEED_DEVICE + +extern void delay(int delayloop); + +static uint_8 K70_ULPI_SetDeviceMode(uint_8 controller_ID){ + // device init + unsigned int count = 10000; + unsigned int reg; + + // reset usb controller + reg = USBHS_USBCMD; + reg |= USBHS_USBCMD_RST_MASK; + USBHS_USBCMD = reg; + // check if reset done, port is enabled + while(USBHS_USBCMD & USBHS_USBCMD_RST_MASK); + + // enable USB work in device mode + reg = USBHS_USBMODE; + reg &= ~0x3; + reg |= 0x2; // device mode + + // Disable Setup Lockout by writing '1' to SLOM in USBMODE + reg &= ~(USBHS_USBMODE_SDIS_MASK); + // Setup Lockouts Off + reg |= USBHS_USBMODE_SLOM_MASK; + // this register can only be written once after reset + USBHS_USBMODE = reg; + + // wait for mode to be set + while(((USBHS_USBMODE & 0x3) != 0x2) && (--count)) ; + + if(count == 0) + return USBERR_INIT_FAILED; //timeout + +#ifdef ULPI_FORCE_FULLSPEED + reg = USBHS_PORTSC1; + reg |= USBHS_PORTSC1_PFSC_MASK; + USBHS_PORTSC1 = reg; /* force full speed */ +#endif + + // Configure ENDPOINTLISTADDR Pointer + USBHS_EPLISTADDR = (unsigned int)g_usbd_qh_buf & 0xFFFFF800; + + // Set OTG termination, controls the pulldown on DM + reg = USBHS_OTGSC; + reg |= (0x1 << 3); + USBHS_OTGSC = reg; + + // clear the usb intr status + USBHS_USBSTS = 0xFFFFFFFF; + + return USB_OK; +} + +/*! + * Initialize the USB device endpoint queue head structure + */ +static void usbd_ep_qh_init(uint_8 controller_ID, + unsigned char endpt_number, unsigned char direction, unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult, uint_32 next_dtd) +{ + struct dqh_t qhead; + unsigned int total_bytes; + + memset((void*)&qhead, 0, sizeof(qhead)); + + // Initialize device queue head in system memory + if(endpt_number == CONTROL_ENDPOINT) + total_bytes = 8; // 8 bytes for the 1st setup packet + else + total_bytes = max_pkt_len; + qhead.dqh_base = usbd_get_dqh(controller_ID, endpt_number, direction); + qhead.next_link_ptr = next_dtd; + qhead.zlt = zlt; + qhead.mps = max_pkt_len; + qhead.ios = IOS_SET; + // todo LOW CHECK 2: check this + qhead.terminate = TERMINATE; + qhead.total_bytes = total_bytes; + qhead.ioc = IOC_SET; + qhead.status = NO_STATUS; + qhead.mult = mult; + qhead.buffer_ptr0 = 0; + qhead.current_offset = 0; + qhead.buffer_ptr1 = 0; + qhead.buffer_ptr2 = 0; + qhead.buffer_ptr3 = 0; + qhead.buffer_ptr4 = 0; + + /* Set Device Queue Head */ + usbd_setup_qhead(&qhead); + // Initialize TD list to empty + g_usbd_qh_tail[(endpt_number * 2) + direction] = NULL; +} + +/*! + * Setup the queue head for the USB device + * + * @param qhead The queue head data structure that contains the necessary configuration data + */ +static void usbd_setup_qhead(struct dqh_t *qhead) +{ + volatile struct dqh_setup_t *dqh_word = (volatile struct dqh_setup_t *)qhead->dqh_base; + + // 0x0 + // Bit31:30 Mult; Bit29 zlt; Bit26:16 mps; Bit15 ios + dqh_word->dqh_word0 = + (((uint_32)((qhead->zlt) << 29)) | + ((uint_32)((qhead->mps) << 16)) | + (((uint_32)(qhead->ios) <<15)) | + (uint_32)((qhead->mult) << 30)); + + // 0x4 + // Current dTD Pointer => for hw use, not modified by DCD software + dqh_word->dqh_word1 = 0x0; + + // 0x8 + // Next dTD Pointer + dqh_word->dqh_word2 = (((qhead->next_link_ptr) & 0xFFFFFFE0) | qhead->terminate); + + // 0xC + // Bit30:16 total_bytes; Bit15 ioc; Bit11:10 MultO; Bit7:0 status + dqh_word->dqh_word3 = + ((((uint_32)(qhead->total_bytes) & 0x7FFF) << 16) | + ((uint_32)(qhead->ioc) << 15) | + (qhead->status)); + + // 0x10 + // Bit31:12 Buffer Pointer (Page 0) + dqh_word->dqh_word4 = + ((qhead->buffer_ptr0 & 0xFFFFF000) | + (qhead->current_offset & 0xFFF)); + + // 0x14 + // Bit31:12 Buffer Pointer (Page 1) + dqh_word->dqh_word5 = (qhead->buffer_ptr1 & 0xFFFFF000); + + // 0x18 + // Bit31:12 Buffer Pointer (Page 2) + dqh_word->dqh_word6 = (qhead->buffer_ptr2 & 0xFFFFF000); + + // 0x1C + // Bit31:12 Buffer Pointer (Page 3) + dqh_word->dqh_word7 = (qhead->buffer_ptr3 & 0xFFFFF000); + + // 0x20 + // Bit31:12 Buffer Pointer (Page 4) + dqh_word->dqh_word8 = (qhead->buffer_ptr4 & 0xFFFFF000); + + // 0x24 + // Reserved + dqh_word->dqh_word9 = 0; + + // 0x28 + // Setup Buffer 0 + dqh_word->dqh_word10 = 0; + + // 0x2C + // Setup Buffer 1 + dqh_word->dqh_word11 = 0; +} + +/*! + * Setup the transfer descriptor + * + * @param td The TD data sturcture that contains the necessary configuration data + */ +static void usbd_setup_td(struct dtd_t *td) +{ + volatile struct dtd_setup_t *dtd_word = (volatile struct dtd_setup_t *)td->dtd_base; + + /* Bit31:5 Next Link Pointer ; Bit0 terminate */ + dtd_word->dtd_word0 = ((td->next_link_ptr & 0xFFFFFFE0) | td->terminate); + + /* Bit30:16 total_bytes, Bit15 ioc, Bit7:0 status */ + dtd_word->dtd_word1 = ((unsigned int)td->total_bytes & 0x7FFF) << 16; + dtd_word->dtd_word1 |= ((unsigned int)td->ioc << 15) | (td->status); + + /* Bit31:12 Buffer Pointer Page 0 ; Bit11:0 Current Offset */ + dtd_word->dtd_word2 = ((td->buffer_ptr0 & 0xFFFFF000) | (td->current_offset & 0xFFF)); + + /* Bit31:12 Buffer Pointer Page 1 ; Bit10:0 Frame Number */ + dtd_word->dtd_word3 = (td->buffer_ptr1 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 2 ; */ + dtd_word->dtd_word4 = (td->buffer_ptr2 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 3 ; */ + dtd_word->dtd_word5 = (td->buffer_ptr3 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 4 ; */ + dtd_word->dtd_word6 = (td->buffer_ptr4 & 0xFFFFF000); + +} +/*! + * Get the offset of DQH from the QH buffer base + * + * @param endpt_number The end point number, start from 0 + * @param direction The In or Out endpoint + * + * @return The relative offset of DQH + * @return 0 if can't find a free DTD + */ +static unsigned int usbd_get_dqh(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction) +{ + + unsigned char *qh_buf = g_usbd_qh_buf; + + /* direction OUT = 0 and IN = 1 */ + return (unsigned int)(qh_buf + (SIZE_OF_QHD * (endpt_number * 2 + direction))); +} + +/*! + * Get the offset of DTD from the TD buffer base + * + * @param endpt_number The end point number, start from 0 + * @param direction The In or Out endpoint + * + * @return The relative offset of DTD + */ +static unsigned int usbd_get_dtd(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned int sz) +{ + /* If Maximum EPs supported in n then EPno will range from 0 to (n-1) */ + unsigned int i; + unsigned char *td_buf = g_usbd_td_buf; + + int td_index = (endpt_number * 2) + direction; + + for(i = 0; i < MAX_DTDS_PER_EP; i++) { + + if(g_usbd_td_flag[td_index][i].status == DTD_FREE || + g_usbd_td_flag[td_index][i].total_bytes == 0) { + g_usbd_td_flag[td_index][i].status = DTD_BUSY; + // printf("ep%d direction%d alloc = %d\n", endpt_number, direction, i); + g_usbd_td_flag[td_index][i].phys_td = (volatile struct dtd_setup_t *) + ((unsigned int) td_buf + + (SIZE_OF_DTD0) *(td_index) * MAX_DTDS_PER_EP + + i * (SIZE_OF_DTD0)); + g_usbd_td_flag[td_index][i].total_bytes = sz; +#if USART_DEBUG + if(endpt_number == 1){ + printf("usbd_get_dtd ep1\n"); + } + if(endpt_number == 2){ + printf("usbd_get_dtd ep2\n"); + } + if(endpt_number == 3){ + printf("usbd_get_dtd ep3\n"); + } +#endif /* USART_DEBUG */ + return (unsigned int)g_usbd_td_flag[td_index][i].phys_td ; + } + } + // todo LOW 3: clear dtd and g_usbd_td_flag and point to first item +#ifdef USART_DEBUG + printf("Cannot get dTD!\n"); +#endif + return 0; +} + +static void usbd_ep_setup(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned char ep_type) +{ + if(endpt_number == CONTROL_ENDPOINT){ + return; + } + + unsigned int temp = 0; + + if(direction) { + //if(endpt_number) + temp |= USBHS_EPCR_TXR_MASK; + temp |= USBHS_EPCR_TXE_MASK; + temp |= ((unsigned int)(ep_type) << USBHS_EPCR_TXT_SHIFT); + /* configure RX endpoint as bulk(see K70 RM) */ + temp |= ((unsigned int)(2) << USBHS_EPCR_RXT_SHIFT); + } else { +// /if(endpt_number) + temp |= USBHS_EPCR_RXR_MASK; + temp |= USBHS_EPCR_RXE_MASK; + temp |= ((unsigned int)(ep_type) << USBHS_EPCR_RXT_SHIFT); + /* configure TX endpoint as bulk(see K70 RM) */ + temp |= ((unsigned int)(2) << USBHS_EPCR_TXT_SHIFT); + } + + // Initialize endpoints 1-3 + USBHS_EPCR(endpt_number-1) = temp; +} + +/**************************************************************************//*! + * + * @name usbd_setup_packet_handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +static void usbd_setup_packet_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + unsigned char setup_packet[8]; + + // Clear setup complete register + USBHS_EPSETUPSR = USBHS_EPSETUPSR; + + // Read setup packet + usbd_read_setup_packet(event->controller_ID, setup_packet); + + // Assume EP0 + event->ep_num = CONTROL_ENDPOINT; + + // Direction of setup complete is always Receive + event->direction = USB_RECV; + event->buffer_ptr = setup_packet; + event->len = sizeof(setup_packet); + event->setup = TRUE; + + /* Transfer direction of next packet */ + g_trf_direction = (uint_8)((uint_8) + (event->buffer_ptr[0]) >> 7); + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); +} + +// Read in setup packet. Assumes EP0. +static void usbd_read_setup_packet(uint_8 controller_ID, unsigned char *setup_packet) +{ + dqh_setup_t *dqh_word; + uint_32 dqh_address; + uint_32 reg; + uint_32 count = 10000; + int i; + usb_standard_device_request_t *setup_struct; + + // a. Clear setup complete register + reg = USBHS_EPSETUPSR; + USBHS_EPSETUPSR = reg; + + /* Get the Device Queue Head Address for EP0 OUT */ + dqh_address = usbd_get_dqh(controller_ID, EP0, OUT); + dqh_word = (dqh_setup_t *) dqh_address; + + do { + // b. Setup tripwire bit + USBHS_USBCMD |= USBHS_USBCMD_SUTW_MASK; + + // c. Copy the SetupBuffer into local software byte array + reg = (dqh_word->dqh_word10); + + /* This is due to the simulator bug for word variant access on EMI but actually design has word invariant access */ + for(i = 0; i < 4; i++) { + setup_packet[i] = (unsigned int)((reg >> (8 * i)) & 0xFF); + } + reg = (dqh_word->dqh_word11); + for(i = 0; i < 4; i++) { + setup_packet[i + 4] = (unsigned int)((reg >> (8 * i)) & 0xFF); + } + + // todo LOW 3: change to processor speed independent count + // d. Read USBCMD[SUTW] bit (if set, continue, else goto step b) + } while(!(USBHS_USBCMD & USBHS_USBCMD_SUTW_MASK) && (--count)); + + if(!count){ +#ifdef USART_DEBUG + printf("error getting setup buffer\n"); +#endif /* USART_DEBUG */ + } + + // e. Clear USBCMD[SUTW] bit + USBHS_USBCMD &= ~USBHS_USBCMD_SUTW_MASK; + + setup_struct = (usb_standard_device_request_t *)setup_packet; + if(setup_struct->bRequest == SET_ADDRESS) { + g_dci_address_state = 1; + } +} + + +static void usbd_port_change( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +){ +} + + +/**************************************************************************//*! + * + * @name usbd_dtd_handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +static void usbd_ep_complete_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + int i; + unsigned int ep_complete; + + // todo LOW CHECK 2: check this +#if USART_DEBUG + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(2)){ + printf("ep1: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(4)){ + printf("ep2: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(8)){ + printf("ep3: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(2)){ + printf("ep1: SEND\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(4)){ + printf("ep2: SEND\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(8)){ + printf("ep3: SEND\n"); + } +#endif /* USART_DEBUG */ + // Get and clear endpoint complete register + ep_complete = USBHS_EPCOMPLETE; + USBHS_EPCOMPLETE = ep_complete; + + // Handle all ep bits set in ep complete register + for(i = 0; i < 16; i++) + { + // Determine bit position in ep complete register + // (skip over the reserved bits) + unsigned int ep_bit = (i < 8) ? i : (i + 8); + + if(ep_complete & (1 << ep_bit)) + { + if(ep_bit < 8) + { + // Endpoint Receive Complete Event + event->direction = USB_RECV; + event->ep_num = i; + } + else + { + // Endpoint Transmit Complete Event + event->direction = USB_SEND; + event->ep_num = ep_bit - 16; + } + + if(event->ep_num == CONTROL_ENDPOINT) + { + // Control endpoint handling + usbd_ep0_complete(event); + } + else + { + // Non-control endpoint handling + usbd_dtd_complete(event); + } + } + } +} + +// Control endpoint complete handling +static void usbd_ep0_complete(USB_DEV_EVENT_STRUCT* event) +{ + volatile struct dtd_setup_t *dtd_word; + unsigned int i; + unsigned int endpt_number = event->ep_num; + unsigned int direction = event->direction; + + // Walk the TD status array to find the next completed TD + for(i = 0; i < MAX_DTDS_PER_EP; i++) + { + unsigned int td_index = (endpt_number * 2) + direction; + + // Get dTD associated with this endpoint and direction + dtd_word = g_usbd_td_flag[td_index][i].phys_td; + + // Determine if dTD is busy (not free) and completed (not active) + if((g_usbd_td_flag[td_index][i].status == DTD_BUSY) && ((dtd_word->dtd_word1 & 0x80) != 0x80)) + { + // Mark dTD as free + g_usbd_td_flag[td_index][i].status = DTD_FREE; + + if(g_dci_address_state ==1) { + event->ep_num = CONTROL_ENDPOINT; + event->buffer_ptr = 0; + event->len = 0; + g_dci_address_state =0; + } + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); + } + } +} + +// Handle endpoint dTD complete +static void usbd_dtd_complete(USB_DEV_EVENT_STRUCT* event) +{ + volatile struct dtd_setup_t *dtd_word; + unsigned int i; + unsigned int endpt_number = event->ep_num; + unsigned int direction = event->direction; + + // todo LOW CHECK 2: check this +#if USART_DEBUG + if(event->ep_num == 1){ + printf("usbd_dtd_complete ep1\n"); + } + if(event->ep_num == 2){ + printf("usbd_dtd_complete ep2\n"); + } + if(event->ep_num == 3){ + printf("usbd_dtd_complete ep3\n"); + } +#endif /*USART_DEBUG */ + // Walk the TD status array to find the next completed TD + for(i = 0; i < MAX_DTDS_PER_EP; i++) + { + unsigned int td_index = (endpt_number * 2) + direction; + + // Get dTD associated with this endpoint and direction + dtd_word = g_usbd_td_flag[td_index][i].phys_td; + + // Determine if dTD is busy (not free) and completed (not active) + if((g_usbd_td_flag[td_index][i].status == DTD_BUSY) && ((dtd_word->dtd_word1 & 0x80) != 0x80)) + { + // Get original number of bytes to transfer + unsigned int total_bytes = g_usbd_td_flag[td_index][i].total_bytes; + // Subtract number of remaining bytes not transferred + event->len = total_bytes - (dtd_word->dtd_word1 >> 16) & 0x7FFF; + event->buffer_ptr = (uint_8 *)dtd_word->dtd_word2 - event->len; + + // Mark dTD as free + g_usbd_td_flag[td_index][i].status = DTD_FREE; + + // If this was the tail, mark list as empty + if(dtd_word == g_usbd_qh_tail[td_index]) + g_usbd_qh_tail[td_index] = NULL; + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); +// break; + } + } +} + +/*! + * Receive data through EPx + * + * @param epx_data_buffer EPx receive buffer + * @param sz Number of bytes to receive + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_receive_data_epxout(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int direction = OUT; + + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, ep_num, direction, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get the total bytes to be received */ + total_bytes = sz; + +#if USART_DEBUG + if(total_bytes > 20 * 1024) + printf("Error!!! %s, size is %d\n", __func__, sz); +#endif /* USART_DEBUG */ + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = epx_data_buffer; + td.current_offset = (epx_data_buffer & 0xFFF); + td.buffer_ptr1 = (epx_data_buffer & 0xFFFFF000) + 0x1000; + td.buffer_ptr2 = (epx_data_buffer & 0xFFFFF000) + 0x2000; + td.buffer_ptr3 = (epx_data_buffer & 0xFFFFF000) + 0x3000; + td.buffer_ptr4 = (epx_data_buffer & 0xFFFFF000) + 0x4000; + + /* Set the Transfer Descriptor */ + usbd_setup_td(&td); + + // Add TD to TD list for this endpoint + direction + usbd_add_td(controller_ID, ep_num, direction, &td); + + return USB_SUCCESS; +} + +/*! + * Receive data through EP0 + * + * @param ep0_data_buffer EP0 receive buffer + * @param sz Number of bytes to receive + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_receive_data_ep0out(uint_8 controller_ID, unsigned int ep0_data_buffer, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int dqh_address; + unsigned int temp; + +// printf_info("%s, size is %d\n", __func__, sz); + + // Yi if(ep0_data_buffer != NULL) + // memset((void *)ep0_data_buffer, 0x0, 256); // todo LOW 2: hard-coded size + + /* Get Device Device Queue Head of the requested endpoint */ + dqh_address = usbd_get_dqh(controller_ID, EP0, OUT); + + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, EP0, OUT, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get the total bytes to be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = dtd_address + 0x20; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = ep0_data_buffer; + td.current_offset = (ep0_data_buffer & 0xFFF); + td.buffer_ptr1 = 0; + td.buffer_ptr2 = 0; + td.buffer_ptr3 = 0; + td.buffer_ptr4 = 0; + + /* Set the Transfer Descriptor */ + usbd_setup_td(&td); + + //Yi + //(*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = dtd_address; + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + /* 3. prime endpoint by writing '1' in ENDPTPRIME */ + temp = USBHS_EPPRIME; + temp |= EPOUT_PRIME; + USBHS_EPPRIME = temp; + while(USBHS_EPPRIME & EPOUT_PRIME) ; //wait prime end + + return USB_SUCCESS; +} + +// Prime endpoint +static void usbd_prime_ep(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td) +{ + unsigned int temp; + + unsigned int ep_mask = (direction == OUT ? EPOUT_PRIME : EPIN_PRIME); + // Get Device Device Queue Head of the requested endpoint + unsigned int dqh_address = usbd_get_dqh(controller_ID, ep_num, direction); + + /* Enable ZLT when data size is in multiple of Maximum Packet Size */ + /* set ZLT enable */ + if(direction == IN) + { + (*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + } + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = td->dtd_base; + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + /* 3. prime endpoint by writing '1' in ENDPTPRIME */ + temp = USBHS_EPPRIME; + temp |= ep_mask << ep_num; + USBHS_EPPRIME = temp; +} + +// Add TD to TD list and prime endpoint based on this algorithm: +// Appendix +// 5.5.3 Executing A Transfer Descriptor +// To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device +// controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. +// Determine whether the link list is empty: +// Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets +// are outstanding). +// Case 1: Link list is empty +// 1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. +// 2. Clear active & halt bit in dQH (in case set from a previous error). +// 3. Prime endpoint by writing '1' to correct bit position in ENDPTPRIME. +// Case 2: Link list is not empty +// 1. Add dTD to end of linked list. +// 2. Read correct prime bit in ENDPTPRIME - if '1' DONE. +// 3. Set ATDTW bit in USBCMD register to '1'. +// 4. Read correct status bit in ENDPTPRIME. (store in tmp. variable for later) [[this should be ENDPTSTATUS, not ENDPTPRIME]} +// 5. Read ATDTW bit in USBCMD register. +// If '0' goto 3. +// If '1' continue to 6. +// 6. Write ATDTW bit in USBCMD register to '0'. +// 7. If status bit read in (4) is '1' DONE. +// 8. If status bit read in (4) is '0' then Goto Case 1: Step 1. +// +static void usbd_add_td(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td) +{ + // Get the index into the TD list for this endpoint + direction + int td_index = (ep_num * 2) + direction; + + if(g_usbd_qh_tail[td_index] == NULL) + { + // Case 1: Link list is empty + + usbd_prime_ep(controller_ID, ep_num, direction, td); + } + else + { + // Case 2: Link list is not empty + + unsigned int ep_mask = (direction == OUT ? EPOUT_PRIME : EPIN_PRIME); + + // Add TD to tail next_link_ptr + // Clear Terminate bit to indicate pointer is valid + g_usbd_qh_tail[td_index]->dtd_word0 = td->dtd_base & 0xFFFFFFE0; + + // If EP is already primed, we are done + if(!(USBHS_EPPRIME & (ep_mask << ep_num))) + { + // EP not primed, check if it is active + unsigned int ep_status = 0; + unsigned int temp; + + // Use Add dTD Tripwire to properly read endpoint status register + do + { + /* write '1' to Add Tripwire (ATDTW) in USBCMD register */ + temp = USBHS_USBCMD; + temp |= (0x1 << USBHS_USBCMD_ATDTW_SHIFT); + USBHS_USBCMD = temp; + + // Read endpoint status + ep_status = USBHS_EPSR & (ep_mask << ep_num); + + } while(!USBHS_USBCMD & (0x1 << USBHS_USBCMD_ATDTW_SHIFT)); + + /* write '0' to Add Tripwire (ATDTW) in USBCMD register */ + temp = USBHS_USBCMD; + temp &= ~(0x1 << USBHS_USBCMD_ATDTW_SHIFT); + USBHS_USBCMD = temp; + + if(!ep_status) + { + // Status is inactive, so need to prime EP + usbd_prime_ep(controller_ID, ep_num, direction, td); + } + } + } + + // Make this TD the tail + g_usbd_qh_tail[td_index] = (struct dtd_setup_t *)td->dtd_base; +} + +/*! + * Send data through endpoint x + * + * @param epx_data_buffer EPx send buffer + * @param sz Number of bytes to send + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_send_data_epxin(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int direction = IN; + + /* verify Endpoint Number and address */ + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, ep_num, direction, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get Total Bytes to Be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = epx_data_buffer; + td.current_offset = (epx_data_buffer & 0xFFF); + td.buffer_ptr1 = (epx_data_buffer & 0xFFFFF000) + 0x1000; + td.buffer_ptr2 = (epx_data_buffer & 0xFFFFF000) + 0x2000; + td.buffer_ptr3 = (epx_data_buffer & 0xFFFFF000) + 0x3000; + td.buffer_ptr4 = (epx_data_buffer & 0xFFFFF000) + 0x4000; + + /* Set the transfer descriptor */ + usbd_setup_td(&td); + + // Add TD to TD list for this endpoint + direction + usbd_add_td(controller_ID, ep_num, direction, &td); + + return USB_SUCCESS; +} + +/*! + * Send data through endpoint 0 + * + * @param ep0_data_buffer EP0 send buffer + * @param sz Number of bytes to send + * @param zlt_enable If ZLT is enabled + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_send_data_ep0in(uint_8 controller_ID, + unsigned int ep0_data_buffer, unsigned int sz, + unsigned char zlt_enable) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address, dqh_address; + + /* varify Endpoint Number and address */ + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, EP0, IN, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get Device Queue head of the requested endpoint */ + dqh_address = usbd_get_dqh(controller_ID, EP0, IN); + + /* Get Total Bytes to Be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = ep0_data_buffer; + td.current_offset = (ep0_data_buffer & 0xFFF); + td.buffer_ptr1 = 0; + td.buffer_ptr2 = 0; + td.buffer_ptr3 = 0; + td.buffer_ptr4 = 0; + + /* Set the transfer descriptor */ + usbd_setup_td(&td); + + /* Enable ZLT when data size is in multiple of Maximum Packet Size */ + /* set ZLT enable */ + (*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = (dtd_address); + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + USBHS_EPPRIME |= EPIN_PRIME; + + /* 4. wait for prime complete */ + while(USBHS_EPPRIME & EPIN_PRIME); + + return USB_SUCCESS; +} +#endif /* HIGH_SPEED_DEVICE */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h new file mode 100644 index 0000000..79d50ff --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h @@ -0,0 +1,311 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dci_kinetis.h + * + * @author + * + * @version + * + * @date + * + * @brief The file contains Macro's and functions needed by the DCI layer. + * + *****************************************************************************/ + +#ifndef _USB_DCI_H +#define _USB_DCI_H +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "hal/derivative.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define BYTES_1024 (1024) +#define BYTES_512 (512) +#define ENDPT_EP_STALL_MASK (0x02) +#define FRAME_HIGH_BYTE_SHIFT (8) + +#ifdef USB_LOWPOWERMODE +typedef enum _stopmode +{ + STOP_MODE1 = 1, /* STOP MODE 1 */ + STOP_MODE2 = 2, /* STOP MODE 2 */ + STOP_MODE3 = 3, /* STOP MODE 3 */ + STOP_MODE4 = 4 /* STOP MODE 4 */ +}STOP_MODE; +#endif + +/* USBTRC0 Initialization Parameters */ +#define _USBPHYEN (0x01) /* Use internal transceiver */ +#define _USBPUEN (0x40) /* Use internal pull-up resistor */ +#define _USBREGEN (0x04) /* Use the internal regulator */ +#define _USBRESET (0x80) + +#define UCFG_VAL (_USBPUEN|_USBREGEN) + +#define CTL_RESET_VAL (0) /* value programmed to the CTL + register in RESET */ + +#define EP_CTRL (0x0C) /* Cfg Control pipe for this endpoint */ +// HIGH_SPEED_DEVICE +#if !HIGH_SPEED_DEVICE +#define EP_OUT (0x08) /* Cfg OUT only pipe for this endpoint*/ +#define EP_IN (0x04) /* Cfg IN only pipe for this endpoint */ +#endif +#define HSHK_EN (0x01) /* Enable handshake packet */ + /* Handshake should be disable for + isochorous transfer */ +#define EP_CTL_DIS (0x10) + +#define EP_DISABLE (0) + +#define TRANSFER_INDEX(x) (x>>1) + +#define MAX_EP_BUFFER_SIZE USB_MAX_EP_BUFFER_SIZE /*Max Endpoint Buffer Size*/ + +/* Macro's to check whether corresponding INT_STAT bit is set */ +#define BUS_RESET_FLAG(x) ((x) & 1) +#define ERROR_FLAG(x) ((x) & 2) +#define SOF_TOKEN_FLAG(x) ((x) & 4) +#define SLEEP_FLAG(x) ((x) & 0x10) +#define RESUME_FLAG(x) ((x) & 0x20) +#define STALL_FLAG(x) ((x) & 0x80) +#define TOKEN_COMPL_FLAG(x) ((x) & 8) + +/* Setup the controller for Remote Wakeup */ +#define USB_DCI_WAKEUP \ +{ \ + USB0_ISTAT |= USB_ISTAT_RESUME_MASK; \ + USB0_INTEN &= ~USB_INTEN_RESUMEEN_MASK; \ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; \ +} + +/* control endpoint transfer types */ +#define USB_TRF_UNKNOWN (0xFF) + + +#define BDT_MIN_BUFFER_SIZE (16) /* space occupied by smallest + buffer in BDT */ + +#define BDT_MIN_BUFFER_ADDR_INC (4) /* min offset increment + correspoding to min buffer + size */ + +#define BDT_OFFSET_SHIFT (4) /* bdt offset shift */ + +#define INVALID_BDT_INDEX (0xFF)/* invalid bdt index */ + +#define ENDPOINT_NUMBER_SHIFT (4) /* endpoint shift & mask to */ +#define ENDPOINT_NUMBER_MASK (0xF0)/* use in setting and getting + status */ + +#define ENDPOINT_DIRECTION_SHIFT (3) /* direction shift & mask to */ +#define ENDPOINT_DIRECTION_MASK (0x08)/* be used for STAT byte + in BDT */ + +#define SEND_CONTROL_ENDPOINT_BDT_INDEX (2) /* BDT Index for Control Endpoint + SEND direction */ +#define RECV_CONTROL_ENDPOINT_BDT_INDEX (0) /* BDT Index for Control Endpoint + RECV direction */ + +#define EPCTL_STALL (0x02)/* Stall bit in Endpoint + Control Reg */ + +#define USB_SETUP_TOKEN (0x0d)/* Setup Token PID */ +#define USB_SETUP_DIRECTION (0x80)/* Data xfer direction + for Setup packet */ + +#define INT_STAT_CLEAR_ALL (0xBF)/* Value to clear + all Interrupts */ +#define ERR_STAT_CLEAR_ALL (0xBF)/* Value to clear + all Errors */ +#define ERR_ENB_ENABLE_ALL (0xBF)/* Value to enable + all Error Interrupts */ +#define INTENB_BUS_RESET_VAL (0x9F)/* Value to enable + Interrupts in Bus Reset */ +#define INTENB_DISABLE_ALL_VAL (0x00)/* Value to disable all + Interrupts */ + +#define MAX_USB_RAM_BUFFER_INDEX (14) /* MAX possible RAM buffer + Index */ + +#define EP_START_BUFFER_ADDR (0x08)/* First USB_RAM buffer offset*/ + +#define ASSERT_RESUME_DELAY_COUNT (20000)/* Delay for assert resume, 48MHz clock */ + +#define NO_ERRORS (0) /* Init value for error */ + +#define USB_RAM_EVEN_BUFFER (0) +#define USB_RAM_ODD_BUFFER (1) + +#define SWAP16(val) (val) + +#define SWAP32(val) (val) + +/****************************************************************************** + * Types + *****************************************************************************/ +#ifdef LONG_SEND_TRANSACTION + #define LONG_TRANSACTION +#endif + +#ifdef LONG_RECEIVE_TRANSACTION + #define LONG_TRANSACTION +#endif + +typedef union { + uint_8 Byte; + struct { + uint_8 EP_HSHK :1; /* When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous */ + uint_8 EP_STALL :1; /* When set this bit indicates that the endpoint is stalled */ + uint_8 EP_TX_EN :1; /* This bit, when set, enables the endpoint for TX transfers */ + uint_8 EP_RX_EN :1; /* This bit, when set, enables the endpoint for RX transfers */ + uint_8 EP_CTRL_DIS :1; /* This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set */ + uint_8 :1; + uint_8 RETRY_DIS :1; /* This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) */ + uint_8 HOST_WO_HUB :1; /* This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) */ + } Bits; +} ENDPT0STR; + +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) +/* This structure is used to hold endpoint paramaetes and the + transaction parameters on the IO's happening on them */ +typedef struct _BDT_ELEM +{ + uint_16 len; /* endpoint max buffer len */ + uint_32 addr; /* endpoint buffer addr in USB_RAM */ +#ifdef LONG_TRANSACTION + uint_8_ptr app_buffer; /* application buffer pointer */ + USB_PACKET_SIZE app_len; /* application buffer len */ + USB_PACKET_SIZE curr_offset; /* current offset for long transactions */ +#endif + uint_8 flag; /* zero termination flag */ + uint_8 bdtmap_index; /* Corresponding to the buffer */ + uint_8 direction; /* Direction (Send/Receive) */ + uint_8 type; /* Type of Endpoint */ +} BDT_ELEM, *P_BDT_ELEM; +#if defined(__CWCC__) + #pragma options align = reset +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma pack() +#else /* gcc */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#endif + + +uint_8 USB_DCI_DeInit(void); + + /***************************************************************************** + * Global Functions + *****************************************************************************/ +//extern uint_8 USB_Device_Call_Service( +// uint_8 type, +// PTR_USB_DEV_EVENT_STRUCT event +//); + +#ifndef OTG_BUILD +void USB_ISR(void); +#endif + +#if HIGH_SPEED_DEVICE + /* Device Queue Head and Device Transfer Descriptor Related Defination */ + #define SIZE_OF_QHD 0x40 + #define SIZE_OF_DTD0 0x20 + #define SIZE_OF_DTD1 0x20 + #define dTD_SIZE_EPIN (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 + #define dTD_SIZE_EPOUT (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 + #define BUFFER_USED_PER_EP ((SIZE_OF_QHD + dTD_SIZE_EPIN) +(SIZE_OF_QHD + dTD_SIZE_EPOUT)) //0x100 + #define ZLT_ENABLE 0 + #define ZLT_DISABLE 1 + #define IOS_NOTSET 0 + #define IOS_SET 1 + #define IOC_NOTSET 0 + #define IOC_SET 1 + #define TERMINATE 1 + #define NOT_TERMINATE 0 + #define NO_STATUS 0 + #define ACTIVE 0x00000080 + #define EPOUT_COMPLETE 0x00000001 + #define EPIN_COMPLETE 0x00010000 + #define EPOUT_PRIME 0x00000001 + #define EPIN_PRIME 0x00010000 + #define EPOUT_ENABLE 0x00000080 + #define EPIN_ENABLE 0x00800000 + #define STALL_RX 0x00000001 + #define STALL_TX 0x00010000 + + /* Maximum packet size defination */ + #define MPS_8 8 + #define MPS_64 64 + + /* enum for endpoint numbers */ + enum { + EP0, + EP1, + EP2, + EP3, + EP4, + EP5 + }; + + enum { + OUT, + IN + }; + + /* enum for data transfer type on endpoints */ + enum { + CONTROL, + ISOCHRONOUS, + BULK, + INTERRUPT + }; + + /* Status of all transaction on USB */ + typedef enum { + USB_SUCCESS, + USB_FAILURE, + USB_INVALID = -1 /* Always Keep this entry in last */ + } usb_status_t; + + /* USB Device State which are handled by DCD */ + typedef enum { + USB_DEV_DUMMY_STATE, + USB_DEV_DEFAULT_STATE, + USB_DEV_ADDRESSED_STATE, + USB_DEV_CONFIGURED_STATE + } usb_state_t; +#endif // HIGH_SPEED_DEVICE + +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h new file mode 100644 index 0000000..1e7ec1d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h @@ -0,0 +1,262 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dciapi.h + * + * @author + * + * @version + * + * @date Jun-05-2009 + * + * @brief The file contains DCI api function definetions . + * + *****************************************************************************/ + +#ifndef _USB_DCIAPI_H +#define _USB_DCIAPI_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define MAX_SUPPORTED_ENDPOINTS (USB_SERVICE_MAX_EP + 1) + /* Maximum endpoints supported */ +#define MIN_SUPPORTED_ENDPOINTS (1) /* Minimum endpoints supported */ +#define DOUBLE_BUFFERED_ENPOINT_NUMBER (0) /* First double buffered endpoint */ + +#ifdef MCU_MK70F12 +#define NUM_USB_CONTROLLERS (2) +#else +#define NUM_USB_CONTROLLERS (1) +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef enum USB_Controllers_t +{ + MAX3353, + ULPI +}USB_Controllers_t; + +#if HIGH_SPEED_DEVICE +typedef struct dqh_setup_t { + unsigned int dqh_word0; + unsigned int dqh_word1; + unsigned int dqh_word2; + unsigned int dqh_word3; + unsigned int dqh_word4; + unsigned int dqh_word5; + unsigned int dqh_word6; + unsigned int dqh_word7; + unsigned int dqh_word8; + unsigned int dqh_word9; + unsigned int dqh_word10; + unsigned int dqh_word11; +} dqh_setup_t; + +typedef struct dtd_setup_t { + unsigned int dtd_word0; + unsigned int dtd_word1; + unsigned int dtd_word2; + unsigned int dtd_word3; + unsigned int dtd_word4; + unsigned int dtd_word5; + unsigned int dtd_word6; + unsigned int dtd_word7; +} dtd_setup_t; + +typedef struct dqh_t { + unsigned int dqh_base; + unsigned int next_link_ptr; + unsigned int buffer_ptr0; + unsigned int buffer_ptr1; + unsigned int buffer_ptr2; + unsigned int buffer_ptr3; + unsigned int buffer_ptr4; + unsigned short total_bytes; + unsigned short mps; + unsigned short current_offset; + unsigned char zlt; + unsigned char ios; + unsigned char terminate; + unsigned char ioc; + unsigned char status; + unsigned char mult; +} dqh_t; + +typedef struct dtd_t { + unsigned int dtd_base; + unsigned int next_link_ptr; + unsigned int buffer_ptr0; + unsigned int buffer_ptr1; + unsigned int buffer_ptr2; + unsigned int buffer_ptr3; + unsigned int buffer_ptr4; + unsigned short total_bytes; + unsigned short current_offset; + unsigned char terminate; + unsigned char ioc; + unsigned char status; +} dtd_t; + +typedef struct { + unsigned int ep_dqh_base_addrs; /* Base Address of Queue Header */ + unsigned int ep_dtd_base_addrs; /* Base Address of Transfer Descriptor */ + unsigned int ep0_buffer_addrs; /* Buffer Addres for EP0 IN */ + unsigned int buffer1_address; /* Buffer1 address for bulk transfer */ + unsigned int buffer1_status; /* Status of Buffer1 */ + unsigned int buffer2_address; /* Buffer2 address for bulk transfer */ + unsigned int buffer2_status; /* Status of Buffer2 */ +} buffer_map_t; + +/* USB standard device request*/ +typedef struct usb_standrd_device_request { + unsigned char bmRequestType; + unsigned char bRequest; + unsigned short wValue; + unsigned short wIndex; + unsigned short wLength; +} usb_standard_device_request_t; + +#endif // HIGH_SPEED_DEVICE + + /***************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_DCI_Init( + uint_8 controller_ID, + uint_8 bVregEn +); + +extern uint_8 USB_DCI_Init_EndPoint( + uint_8 controller_ID, + USB_EP_STRUCT_PTR ep_ptr, + boolean flag +); + +extern uint_8 USB_DCI_Cancel_Transfer( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern uint_8 USB_DCI_Deinit_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Stall_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Unstall_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Get_Setup_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr +); + +extern uint_8 USB_DCI_Get_Transfer_Status( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Clear_DATA0_Endpoint( + uint_8 ep_num, + uint_8 direction +); + +extern uint_8 USB_DCI_Recv_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern uint_8 USB_DCI_Send_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern void USB_DCI_Set_Address( + uint_8 controller_ID, + uint_8 address +); + +extern void USB_DCI_Shutdown( + uint_8 controller_ID +); + +extern void USB_DCI_Assert_Resume( + uint_8 controller_ID +); + +extern void Clear_Mem(uint_8* start_addr,uint_32 count, uint_8 val); + +#define USB_DCI_Cancel_Transfer _usb_device_cancel_transfer + +#define USB_DCI_Recv_Data _usb_device_recv_data + +#define USB_DCI_Send_Data _usb_device_send_data + +#define USB_DCI_Shutdown _usb_device_shutdown + +#define USB_DCI_Stall_EndPoint _usb_device_stall_endpoint + +#define USB_DCI_Unstall_EndPoint _usb_device_unstall_endpoint + +#define USB_DCI_Get_Transfer_Status _usb_device_get_transfer_status + +#define USB_DCI_Clear_DATA0_Endpoint _usb_device_clear_data0_endpoint + +#define USB_DCI_Get_Setup_Data _usb_device_read_setup_data + +#define USB_DCI_Set_Address _usb_device_set_address + +#define USB_DCI_Assert_Resume _usb_device_assert_resume + +#endif + + + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c new file mode 100644 index 0000000..2f938c2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c @@ -0,0 +1,889 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_descriptor.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief This file contains USB descriptors for Virtual COM Loopback + * Application + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "hal/derivative.h" +#include "types.h" +#include "usb_class.h" +#include "usb_descriptor.h" + +#if (defined __MCF52xxx_H__)||(defined __MK_xxx_H__) +/* Put CFV2 descriptors in RAM */ +#define USB_DESC_CONST +#else +#define USB_DESC_CONST const +#endif + +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ +/* structure containing details of all the endpoints used by this device */ +USB_DESC_CONST USB_ENDPOINTS usb_desc_ep = +{ + CDC_DESC_ENDPOINT_COUNT, + { + #if DATA_CLASS_SUPPORT + #if DIC_ISOCHRONOUS_SETTING + { + DIC_ISO_IN_ENDPOINT, + USB_ISOCHRONOUS_PIPE, + USB_SEND, + DIC_ISO_IN_ENDP_PACKET_SIZE + }, + { + DIC_ISO_OUT_ENDPOINT, + USB_ISOCHRONOUS_PIPE, + USB_RECV, + DIC_ISO_OUT_ENDP_PACKET_SIZE + } + #else + { + DIC_BULK_IN_ENDPOINT, + USB_BULK_PIPE, + USB_SEND, + DIC_BULK_IN_ENDP_PACKET_SIZE + }, + { + DIC_BULK_OUT_ENDPOINT, + USB_BULK_PIPE, + USB_RECV, + DIC_BULK_OUT_ENDP_PACKET_SIZE + } + #endif + #endif + #if CIC_NOTIF_ELEM_SUPPORT + , + { + CIC_NOTIF_ENDPOINT, + USB_INTERRUPT_PIPE, + USB_SEND, + CIC_NOTIF_ENDP_PACKET_SIZE + } + #endif + + } +}; + +uint_8 USB_DESC_CONST g_device_descriptor[DEVICE_DESCRIPTOR_SIZE] = +{ + DEVICE_DESCRIPTOR_SIZE, /* Device Descriptor Size */ + USB_DEVICE_DESCRIPTOR, /* Device Type of descriptor */ + 0x00, 0x02, /* BCD USB version */ + 0x02, /* Device Class is indicated in + the interface descriptors */ + 0x00, /* Device Subclass is indicated + in the interface descriptors */ + 0x00, /* Device Protocol */ + CONTROL_MAX_PACKET_SIZE, /* Max Packet size */ + (0x2A3C&0xFF),((0x2A3C>>8)&0xFF), /* Vendor ID "Trinamic" */ + (0x0700&0xFF),((0x0700>>8)&0xFF), /* "TRINAMIC Evaluation Device" */ + 0x02,0x00, /* BCD Device version */ + 0x01, /* Manufacturer string index */ + 0x02, /* Product string index */ + 0x00, /* Serial number string index */ + 0x01 /* Number of configurations */ +}; + +uint_8 USB_DESC_CONST g_config_descriptor[CONFIG_DESC_SIZE] = +{ + CONFIG_ONLY_DESC_SIZE, /* Configuration Descriptor Size */ + USB_CONFIG_DESCRIPTOR, /* "Configuration" type of descriptor */ + CONFIG_DESC_SIZE, 0x00, /* Total length of the Configuration descriptor */ + (uint_8)(1+DATA_CLASS_SUPPORT),/*NumInterfaces*/ + 0x01, /* Configuration Value */ + 0x00, /* Configuration Description String Index*/ + BUS_POWERED|SELF_POWERED|(REMOTE_WAKEUP_SUPPORT<> 0) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>> 8) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>>16) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>>24) & 0x000000FF, + /*e.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */ + LINE_CODE_CHARFORMAT_IFACE0, + LINE_CODE_PARITYTYPE_IFACE0, + LINE_CODE_DATABITS_IFACE0 + } +}; + +static uint_8 g_abstract_state[USB_MAX_SUPPORTED_INTERFACES][COMM_FEATURE_DATA_SIZE] = +{ + { (STATUS_ABSTRACT_STATE_IFACE0>>0) & 0x00FF, + (STATUS_ABSTRACT_STATE_IFACE0>>8) & 0x00FF + } +}; + +static uint_8 g_country_code[USB_MAX_SUPPORTED_INTERFACES][COMM_FEATURE_DATA_SIZE] = +{ + { (COUNTRY_SETTING_IFACE0>>0) & 0x00FF, + (COUNTRY_SETTING_IFACE0>>8) & 0x00FF + } +}; + +static uint_8 g_alternate_interface[USB_MAX_SUPPORTED_INTERFACES]; + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + + + /***************************************************************************** + * Local Functions - None + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +/**************************************************************************//*! + * + * @name USB_Desc_Get_Descriptor + * + * @brief The function returns the correponding descriptor + * + * @param controller_ID : Controller ID + * @param type : type of descriptor requested + * @param sub_type : string index for string descriptor + * @param index : string descriptor language Id + * @param descriptor : output descriptor pointer + * @param size : size of descriptor returned + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is used to pass the pointer to the requested descriptor + *****************************************************************************/ +uint_8 USB_Desc_Get_Descriptor ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 type, /* [IN] type of descriptor requested */ + uint_8 str_num, /* [IN] string index for string descriptor */ + uint_16 index, /* [IN] string descriptor language Id */ + uint_8_ptr *descriptor, /* [OUT] output descriptor pointer */ + USB_PACKET_SIZE *size /* [OUT] size of descriptor returned */ +) +{ + UNUSED (controller_ID); + + /* string descriptors are handled saperately */ + if(type == USB_STRING_DESCRIPTOR) + { + if(index == 0) + { + /* return the string and size of all languages */ + *descriptor = (uint_8_ptr) (unsigned long) g_languages.languages_supported_string; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + *size = g_languages.languages_supported_size; + } else + { + uint_8 lang_id=0; + uint_8 lang_index=USB_MAX_LANGUAGES_SUPPORTED; + + for(;lang_id< USB_MAX_LANGUAGES_SUPPORTED;lang_id++) + { + /* check whether we have a string for this language */ + if(index == g_languages.usb_language[lang_id].language_id) + { /* check for max descriptors */ + if(str_num < USB_MAX_STRING_DESCRIPTORS) + { /* setup index for the string to be returned */ + lang_index=str_num; + } + + break; + } + + } + + /* set return val for descriptor and size */ + *descriptor = (uint_8_ptr) (unsigned long) g_languages.usb_language[lang_id]. // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + lang_desc[lang_index]; + *size = g_languages.usb_language[lang_id]. + lang_desc_size[lang_index]; + } + + } + else if(type < USB_MAX_STD_DESCRIPTORS+1) + { + /* Set return val for descriptor and size */ + *descriptor = (uint_8_ptr) (unsigned long) g_std_descriptors [type]; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + + /* if there is no descriptor then return error */ + if(*descriptor == NULL) + { + return USBERR_INVALID_REQ_TYPE; + } + + *size = g_std_desc_size[type]; + } + else /* invalid descriptor */ + { + return USBERR_INVALID_REQ_TYPE; + } + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Interface + * + * @brief The function returns the alternate interface + * + * @param controller_ID : Controller Id + * @param interface : Interface number + * @param alt_interface : Output alternate interface + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is called by the framework module to get the current interface + *****************************************************************************/ +uint_8 USB_Desc_Get_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] interface number */ + uint_8_ptr alt_interface /* [OUT] output alternate interface */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get alternate interface*/ + *alt_interface = g_alternate_interface[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Interface + * + * @brief The function sets the alternate interface + * + * @param controller_ID : Controller Id + * @param interface : Interface number + * @param alt_interface : Input alternate interface + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is called by the framework module to set the interface + *****************************************************************************/ +uint_8 USB_Desc_Set_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] interface number */ + uint_8 alt_interface /* [IN] input alternate interface */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set alternate interface*/ + g_alternate_interface[interface]=alt_interface; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Valid_Configation + * + * @brief The function checks whether the configuration parameter + * input is valid or not + * + * @param controller_ID : Controller Id + * @param config_val : Configuration value + * + * @return TRUE When Valid + * FALSE When Error + ***************************************************************************** + * This function checks whether the configuration is valid or not + *****************************************************************************/ +boolean USB_Desc_Valid_Configation ( + uint_8 controller_ID,/*[IN] Controller ID */ + uint_16 config_val /*[IN] configuration value */ +) +{ + uint_8 loop_index=0; + UNUSED (controller_ID); + + /* check with only supported val right now */ + while(loop_index < (USB_MAX_CONFIG_SUPPORTED+1)) + { + if(config_val == g_valid_config_values[loop_index]) + { + return TRUE; + } + loop_index++; + } + + return FALSE; +} +/**************************************************************************//*! + * + * @name USB_Desc_Valid_Interface + * + * @brief The function checks whether the interface parameter + * input is valid or not + * + * @param controller_ID : Controller Id + * @param interface : Target interface + * + * @return TRUE When Valid + * FALSE When Error + ***************************************************************************** + * This function checks whether the interface is valid or not + *****************************************************************************/ +boolean USB_Desc_Valid_Interface ( + uint_8 controller_ID, /*[IN] Controller ID */ + uint_8 interface /*[IN] target interface */ +) +{ + uint_8 loop_index=0; + UNUSED (controller_ID); + + /* check with only supported val right now */ + while(loop_index < USB_MAX_SUPPORTED_INTERFACES) + { + if(interface == g_alternate_interface[loop_index]) + { + return TRUE; + } + loop_index++; + } + + return FALSE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Remote_Wakeup + * + * @brief The function checks whether the remote wakeup is supported or not + * + * @param controller_ID : Controller ID + * + * @return REMOTE_WAKEUP_SUPPORT (TRUE) - if remote wakeup supported + ***************************************************************************** + * This function returns remote wakeup is supported or not + *****************************************************************************/ +boolean USB_Desc_Remote_Wakeup ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return REMOTE_WAKEUP_SUPPORT; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Endpoints + * + * @brief The function returns with the list of all non control endpoints used + * + * @param controller_ID : Controller ID + * + * @return pointer to USB_ENDPOINTS + ***************************************************************************** + * This function returns the information about all the non control endpoints + * implemented + *****************************************************************************/ +void* USB_Desc_Get_Endpoints ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return (void*) (unsigned long) &usb_desc_ep; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Line_Coding + * + * @brief The function returns the Line Coding/Configuraion + * + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param coding_data : Output line coding data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns current Line Coding Parameters + *****************************************************************************/ +uint_8 USB_Desc_Get_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *coding_data /* [OUT] Line Coding Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *coding_data = g_line_coding[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Line_Coding + * + * @brief The function sets the Line Coding/Configuraion + * + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param coding_data : Output line coding data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets Line Coding Structure with the HOST specified values + *****************************************************************************/ +uint_8 USB_Desc_Set_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *coding_data /* [IN] Line Coding Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set line coding data*/ + for(count = 0; count < LINE_CODING_SIZE; count++) + { + g_line_coding[interface][count] = *((*coding_data + + USB_SETUP_PKT_SIZE) + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Abstract_State + * + * @brief The function gets the current setting for communication feature + * (ABSTRACT_STATE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns ABSTRACT STATE Communication Feature to the Host + *****************************************************************************/ +uint_8 USB_Desc_Get_Abstract_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *feature_data = g_abstract_state[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Country_Setting + * + * @brief The function gets the current setting for communication feature + * (COUNTRY_CODE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns the country Code to the Host + *****************************************************************************/ +uint_8 USB_Desc_Get_Country_Setting ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *feature_data = g_country_code[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Abstract_State + * + * @brief The function gets the current setting for communication feature + * (ABSTRACT_STATE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets the ABSTRACT State specified by the Host + *****************************************************************************/ +uint_8 USB_Desc_Set_Abstract_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set Abstract State Feature*/ + for(count = 0; count < COMM_FEATURE_DATA_SIZE; count++) + { + g_abstract_state[interface][count] = *(*feature_data + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Country_Setting + * + * @brief The function gets the current setting for communication feature + * (COUNTRY_CODE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets the country code specified by the HOST + *****************************************************************************/ +uint_8 USB_Desc_Set_Country_Setting( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + for(count = 0; count < COMM_FEATURE_DATA_SIZE; count++) + { + g_country_code[interface][count] = *(*feature_data + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h new file mode 100644 index 0000000..a7ac870 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h @@ -0,0 +1,301 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_descriptor.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file is a header file for USB Descriptors required for Virtual + * COM Loopback Application + *****************************************************************************/ + +#ifndef _USB_DESCRIPTOR_H +#define _USB_DESCRIPTOR_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_class.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define REMOTE_WAKEUP_SUPPORT (FALSE) +#define DATA_CLASS_SUPPORT (TRUE) +#define CIC_NOTIF_ELEM_SUPPORT (TRUE) /* Mandatory */ +#define DIC_ISOCHRONOUS_SETTING (FALSE) + +#define IMPLEMENT_QUEUING (TRUE) + +/* Communication Class SubClass Codes */ +#define DIRECT_LINE_CONTROL_MODEL (0x01) +#define ABSTRACT_CONTROL_MODEL (0x02) +#define TELEPHONE_CONTROL_MODEL (0x03) +#define MULTI_CHANNEL_CONTROL_MODEL (0x04) +#define CAPI_CONTROL_MOPDEL (0x05) +#define ETHERNET_NETWORKING_CONTROL_MODEL (0x06) +#define ATM_NETWORKING_CONTROL_MODEL (0x07) +#define WIRELESS_HANDSET_CONTROL_MODEL (0x08) +#define DEVICE_MANAGEMENT (0x09) +#define MOBILE_DIRECT_LINE_MODEL (0x0A) +#define OBEX (0x0B) +#define ETHERNET_EMULATION_MODEL (0x0C) + +/* Communication Class Protocol Codes */ +#define NO_CLASS_SPECIFIC_PROTOCOL (0x00) +#define AT_250_PROTOCOL (0x01) +#define AT_PCCA_101_PROTOCOL (0x02) +#define AT_PCCA_101_ANNEX_O (0x03) +#define AT_GSM_7_07 (0x04) +#define AT_3GPP_27_007 (0x05) +#define AT_TIA_CDMA (0x06) +#define ETHERNET_EMULATION_PROTOCOL (0x07) +#define EXTERNAL_PROTOCOL (0xFE) +#define VENDOR_SPECIFIC (0xFF) + +/* Data Class Protocol Codes */ +/* #define NO_CLASS_SPECIFIC_PROTOCOL (0x00) */ +#define PYHSICAL_INTERFACE_PROTOCOL (0x30) +#define HDLC_PROTOCOL (0x31) +#define TRANSPARENT_PROTOCOL (0x32) +#define MANAGEMENT_PROTOCOL (0x50) +#define DATA_LINK_Q931_PROTOCOL (0x51) +#define DATA_LINK_Q921_PROTOCOL (0x52) +#define DATA_COMPRESSION_V42BIS (0x90) +#define EURO_ISDN_PROTOCOL (0x91) +#define RATE_ADAPTION_ISDN_V24 (0x92) +#define CAPI_COMMANDS (0x93) +#define HOST_BASED_DRIVER (0xFD) +#define CDC_UNIT_FUNCTIONAL (0xFE) +/* #define VENDOR_SPECIFIC (0xFF) */ + +/* Descriptor SubType in Communications Class Functional Descriptors */ +#define HEADER_FUNC_DESC (0x00) +#define CALL_MANAGEMENT_FUNC_DESC (0x01) +#define ABSTRACT_CONTROL_FUNC_DESC (0x02) +#define DIRECT_LINE_FUNC_DESC (0x03) +#define TELEPHONE_RINGER_FUNC_DESC (0x04) +#define TELEPHONE_REPORT_FUNC_DESC (0x05) +#define UNION_FUNC_DESC (0x06) +#define COUNTRY_SELECT_FUNC_DESC (0x07) +#define TELEPHONE_MODES_FUNC_DESC (0x08) +#define USB_TERMINAL_FUNC_DESC (0x09) +#define NETWORK_CHANNEL_FUNC_DESC (0x0A) +#define PROTOCOL_UNIT_FUNC_DESC (0x0B) +#define EXTENSION_UNIT_FUNC_DESC (0x0C) +#define MULTI_CHANNEL_FUNC_DESC (0x0D) +#define CAPI_CONTROL_FUNC_DESC (0x0E) +#define ETHERNET_NETWORKING_FUNC_DESC (0x0F) +#define ATM_NETWORKING_FUNC_DESC (0x10) +#define WIRELESS_CONTROL_FUNC_DESC (0x11) +#define MOBILE_DIRECT_LINE_FUNC_DESC (0x12) +#define MDLM_DETAIL_FUNC_DESC (0x13) +#define DEVICE_MANAGEMENT_FUNC_DESC (0x14) +#define OBEX_FUNC_DESC (0x15) +#define COMMAND_SET_FUNC_DESC (0x16) +#define COMMAND_SET_DETAIL_FUNC_DESC (0x17) +#define TELEPHONE_CONTROL_FUNC_DESC (0x18) +#define OBEX_SERVICE_ID_FUNC_DESC (0x19) + + +#define CIC_SUBCLASS_CODE ABSTRACT_CONTROL_MODEL +#define CIC_PROTOCOL_CODE NO_CLASS_SPECIFIC_PROTOCOL +#define DIC_PROTOCOL_CODE NO_CLASS_SPECIFIC_PROTOCOL +#define CIC_ENDP_COUNT (0+(CIC_NOTIF_ELEM_SUPPORT & 0x01) * 1) +#define DIC_ENDP_COUNT (2) + +#define CIC_NOTIF_ENDPOINT (3) +#define CIC_NOTIF_ENDP_PACKET_SIZE (16) +#define DIC_BULK_IN_ENDPOINT (1) +#define DIC_BULK_IN_ENDP_PACKET_SIZE (16)/* max supported is 64 */ +#define DIC_BULK_OUT_ENDPOINT (2) +#define DIC_BULK_OUT_ENDP_PACKET_SIZE (16)/* max supported is 64*/ + +#if DIC_ISOCHRONOUS_SETTING +#define DIC_ISO_IN_ENDPOINT (1) +#define DIC_ISO_IN_ENDP_PACKET_SIZE (64) +#define DIC_ISO_OUT_ENDPOINT (2) +#define DIC_ISO_OUT_ENDP_PACKET_SIZE (64) +#endif +#define REMOTE_WAKEUP_SHIFT (5) + +/* Various descriptor sizes */ +#define DEVICE_DESCRIPTOR_SIZE (18) +#define CONFIG_ONLY_DESC_SIZE (9) +#define CONFIG_DESC_SIZE (CONFIG_ONLY_DESC_SIZE + 28 + \ + (CIC_NOTIF_ELEM_SUPPORT & 0x01) \ + * 7 + DATA_CLASS_SUPPORT * 23) +#define DEVICE_QUALIFIER_DESCRIPTOR_SIZE (10) +#define IFACE_ONLY_DESC_SIZE (9) +#define ENDP_ONLY_DESC_SIZE (7) + +/* Max descriptors provided by the Application */ +#define USB_MAX_STD_DESCRIPTORS (7) + +/* Max configuration supported by the Application */ +#define USB_MAX_CONFIG_SUPPORTED (1) + +/* Max string descriptors supported by the Application */ +#define USB_MAX_STRING_DESCRIPTORS (3) + +/* Max language codes supported by the USB */ +#define USB_MAX_LANGUAGES_SUPPORTED (1) + +/* string descriptors sizes */ +#define USB_STR_DESC_SIZE (2) +#define USB_STR_0_SIZE (2) +#define USB_STR_1_SIZE (56) +#define USB_STR_2_SIZE (36) +#define USB_STR_n_SIZE (32) + +/* descriptors codes */ +#define USB_DEVICE_DESCRIPTOR (1) +#define USB_CONFIG_DESCRIPTOR (2) +#define USB_STRING_DESCRIPTOR (3) +#define USB_IFACE_DESCRIPTOR (4) +#define USB_ENDPOINT_DESCRIPTOR (5) +#define USB_DEVQUAL_DESCRIPTOR (6) +#define USB_CS_INTERFACE (0x24) +#define USB_CS_ENDPOINT (0x25) + +#define USB_MAX_SUPPORTED_INTERFACES (2) + +/* Implementation Specific Macros */ +#define LINE_CODING_SIZE (0x07) +#define COMM_FEATURE_DATA_SIZE (0x02) + +#define LINE_CODE_DTERATE_IFACE0 (115200) /*e.g 9600 is 0x00002580 */ +#define LINE_CODE_CHARFORMAT_IFACE0 (0x00) /* 1 stop bit */ +#define LINE_CODE_PARITYTYPE_IFACE0 (0x00) /* No Parity */ +#define LINE_CODE_DATABITS_IFACE0 (0x08) /* Data Bits Format */ + +#define LINE_CODE_DTERATE_IFACE1 (9600) /*e.g. 115200 is 0x0001C200*/ +#define LINE_CODE_CHARFORMAT_IFACE1 (0x00) /* 1 stop bit */ +#define LINE_CODE_PARITYTYPE_IFACE1 (0x00) /* No Parity */ +#define LINE_CODE_DATABITS_IFACE1 (0x08) /* Data Bits Format */ + +#define STATUS_ABSTRACT_STATE_IFACE0 (0x0000) /* Disable Multiplexing + ENDP in this interface will + continue to accept/offer data*/ +#define STATUS_ABSTRACT_STATE_IFACE1 (0x0000) /* Disable Multiplexing + ENDP in this interface will + continue to accept/offer data*/ +#define COUNTRY_SETTING_IFACE0 (0x0000) /* Country Code in the format as + defined in [ISO3166] */ +#define COUNTRY_SETTING_IFACE1 (0x0000) /* Country Code in the format as + defined in [ISO3166] */ + +/* Notifications Support */ +#define PSTN_SUBCLASS_NOTIF_SUPPORT (TRUE) +#define WMC_SUBCLASS_NOTIF_SUPPORT (FALSE) +#define CDC_CLASS_NOTIF_SUPPORT (FALSE) + +#define CDC_DESC_ENDPOINT_COUNT (CIC_ENDP_COUNT+(DATA_CLASS_SUPPORT & 0x01) \ + *DIC_ENDP_COUNT) + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef const struct _USB_LANGUAGE +{ + uint_16 const language_id; /* Language ID */ + uint_8 const ** lang_desc; /* Language Descriptor String */ + uint_8 const * lang_desc_size; /* Language Descriptor Size */ +} USB_LANGUAGE; + +typedef const struct _USB_ALL_LANGUAGES +{ + /* Pointer to Supported Language String */ + uint_8 const *languages_supported_string; + /* Size of Supported Language String */ + uint_8 const languages_supported_size; + /* Array of Supported Languages */ + USB_LANGUAGE usb_language[USB_MAX_SUPPORTED_INTERFACES]; +}USB_ALL_LANGUAGES; + +typedef const struct _USB_ENDPOINTS +{ + /* Number of non control Endpoints */ + uint_8 count; + /* Array of Endpoints Structures */ + USB_EP_STRUCT ep[CDC_DESC_ENDPOINT_COUNT]; +}USB_ENDPOINTS; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Desc_Get_Descriptor( + uint_8 controller_ID, + uint_8 type, + uint_8 str_num, + uint_16 index, + uint_8_ptr *descriptor, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Desc_Get_Interface( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr alt_interface); + + +extern uint_8 USB_Desc_Set_Interface( + uint_8 controller_ID, + uint_8 interface, + uint_8 alt_interface); + +extern boolean USB_Desc_Valid_Configation( + uint_8 controller_ID, + uint_16 config_val); + +extern boolean USB_Desc_Valid_Interface( + uint_8 controller_ID, + uint_8 interface); + +extern boolean USB_Desc_Remote_Wakeup(uint_8 controller_ID); + +extern void* USB_Desc_Get_Endpoints(uint_8 controller_ID); + +extern uint_8 USB_Desc_Get_Line_Coding( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *coding_data); + +extern uint_8 USB_Desc_Set_Line_Coding( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *coding_data); + +extern uint_8 USB_Desc_Get_Abstract_State( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Get_Country_Setting( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Set_Abstract_State( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Set_Country_Setting( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); + +#endif + + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h new file mode 100644 index 0000000..80da323 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h @@ -0,0 +1,480 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_devapi.h + * + * @author + * + * @version + * + * @date + * + * @brief This file contains S08 USB stack device layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_DEVAPI_H +#define _USB_DEVAPI_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" /* User Defined Data Types */ +#include "hidef.h" /* for EnableInterrupts; macro */ +#include +#include "hal/derivative.h" /* include peripheral declarations */ +#include "usb_user_config.h" /* User Configuration File << EST 'user_config.h' conflicts with MQX Lite */ +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H +#define USB_MAX_EP_BUFFER_SIZE (512) +#else +#define USB_MAX_EP_BUFFER_SIZE (255) +#endif +#else +/* device is Kinetis K20D72 << EST */ +#define USB_MAX_EP_BUFFER_SIZE (512) +#endif +#ifndef CONTROL_ENDPOINT +#define CONTROL_ENDPOINT (0) +#endif + +#define USB_SETUP_PKT_SIZE (8) /* Setup Packet Size */ + +/* Error codes */ +#define USB_OK (0x00) +#define USBERR_ALLOC (0x81) +#define USBERR_BAD_STATUS (0x82) +#define USBERR_CLOSED_SERVICE (0x83) +#define USBERR_OPEN_SERVICE (0x84) +#define USBERR_TRANSFER_IN_PROGRESS (0x85) +#define USBERR_ENDPOINT_STALLED (0x86) +#define USBERR_ALLOC_STATE (0x87) +#define USBERR_DRIVER_INSTALL_FAILED (0x88) +#define USBERR_DRIVER_NOT_INSTALLED (0x89) +#define USBERR_INSTALL_ISR (0x8A) +#define USBERR_INVALID_DEVICE_NUM (0x8B) +#define USBERR_ALLOC_SERVICE (0x8C) +#define USBERR_INIT_FAILED (0x8D) +#define USBERR_SHUTDOWN (0x8E) +#define USBERR_INVALID_PIPE_HANDLE (0x8F) +#define USBERR_OPEN_PIPE_FAILED (0x90) +#define USBERR_INIT_DATA (0x91) +#define USBERR_SRP_REQ_INVALID_STATE (0x92) +#define USBERR_TX_FAILED (0x93) +#define USBERR_RX_FAILED (0x94) +#define USBERR_EP_INIT_FAILED (0x95) +#define USBERR_EP_DEINIT_FAILED (0x96) +#define USBERR_TR_FAILED (0x97) +#define USBERR_BANDWIDTH_ALLOC_FAILED (0x98) +#define USBERR_INVALID_NUM_OF_ENDPOINTS (0x99) +#define USBERR_NOT_SUPPORTED (0x9A) + +#define USBERR_DEVICE_NOT_FOUND (0xC0) +#define USBERR_DEVICE_BUSY (0xC1) +#define USBERR_NO_DEVICE_CLASS (0xC3) +#define USBERR_UNKNOWN_ERROR (0xC4) +#define USBERR_INVALID_BMREQ_TYPE (0xC5) +#define USBERR_GET_MEMORY_FAILED (0xC6) +#define USBERR_INVALID_MEM_TYPE (0xC7) +#define USBERR_NO_DESCRIPTOR (0xC8) +#define USBERR_NULL_CALLBACK (0xC9) +#define USBERR_NO_INTERFACE (0xCA) +#define USBERR_INVALID_CFIG_NUM (0xCB) +#define USBERR_INVALID_ANCHOR (0xCC) +#define USBERR_INVALID_REQ_TYPE (0xCD) + +/* Pipe Types */ +#define USB_CONTROL_PIPE (0x00) +#define USB_ISOCHRONOUS_PIPE (0x01) +#define USB_BULK_PIPE (0x02) +#define USB_INTERRUPT_PIPE (0x03) + +/* Device States */ +#define USB_STATE_UNKNOWN (0xFF) +#define USB_STATE_PENDING_ADDRESS (0x04) +#define USB_STATE_POWERED (0x03) +#define USB_STATE_DEFAULT (0x02) +#define USB_STATE_ADDRESS (0x01) +#define USB_STATE_CONFIG (0x00) +#define USB_STATE_SUSPEND (0x80) + +/* Get_Status Request information for DEVICE */ +#define USB_SELF_POWERED (0x01) +#define USB_REMOTE_WAKEUP (0x02) + +/* Get_Status Request information for OTG (WINDEX = 0xF000) */ +#ifdef OTG_BUILD +#define USB_OTG_HOST_REQUEST_FLAG (0x01) +#endif + +/* Bus Control values */ +#define USB_NO_OPERATION (0x00) +#define USB_ASSERT_BUS_RESET (0x01) +#define USB_DEASSERT_BUS_RESET (0x02) +#define USB_ASSERT_RESUME (0x03) +#define USB_DEASSERT_RESUME (0x04) +#define USB_SUSPEND_SOF (0x05) +#define USB_RESUME_SOF (0x06) + +/* possible values of Status */ +#define USB_STATUS_IDLE (0) +#define USB_STATUS_TRANSFER_ACCEPTED (6) +#define USB_STATUS_TRANSFER_PENDING (2) +#define USB_STATUS_TRANSFER_IN_PROGRESS (3) +#define USB_STATUS_ERROR (4) +#define USB_STATUS_DISABLED (5) +#define USB_STATUS_STALLED (1) +#define USB_STATUS_TRANSFER_QUEUED (7) + +#define USB_STATUS_UNKNOWN (0xFF) + +#define USB_CONTROL_ENDPOINT (0) + +#define USB_RECV (0) +#define USB_SEND (1) + +#define USB_DEVICE_DONT_ZERO_TERMINATE (0x1) + +#define USB_SETUP_DATA_XFER_DIRECTION (0x80) + +#define USB_SPEED_FULL (0) +#define USB_SPEED_LOW (1) +#define USB_SPEED_HIGH (2) + +#define USB_MAX_PKTS_PER_UFRAME (0x6) + +#define USB_TEST_MODE_TEST_PACKET (0x0400) + +/* Available service types */ +/* Services 0 through 15 are reserved for endpoints */ +#define USB_SERVICE_EP0 (0x00) +#define USB_SERVICE_EP1 (0x01) +#define USB_SERVICE_EP2 (0x02) +#define USB_SERVICE_EP3 (0x03) +#define USB_SERVICE_EP4 (0x04) +#define USB_SERVICE_EP5 (0x05) +#define USB_SERVICE_EP6 (0x06) +#define USB_SERVICE_EP7 (0x07) +#define USB_SERVICE_EP8 (0x08) +#define USB_SERVICE_EP9 (0x09) +#define USB_SERVICE_EP10 (0x0A) +#define USB_SERVICE_EP11 (0x0B) +#define USB_SERVICE_EP12 (0x0C) +#define USB_SERVICE_EP13 (0x0d) +#define USB_SERVICE_EP14 (0x0E) +#define USB_SERVICE_EP15 (0x0F) + +#define USB_SERVICE_BUS_RESET (0x10) +#define USB_SERVICE_SUSPEND (0x11) +#define USB_SERVICE_SOF (0x12) +#define USB_SERVICE_RESUME (0x13) +#define USB_SERVICE_SLEEP (0x14) +#define USB_SERVICE_SPEED_DETECTION (0x15) +#define USB_SERVICE_ERROR (0x16) +#define USB_SERVICE_STALL (0x17) +#define USB_SERVICE_MAX (0x18) + +#if 0 /* << EST */ +#if (defined(_MCF51JM128_H) ||defined(_MCF51MM256_H) || (defined _MCF51JE256_H)) + #define USB_SERVICE_MAX_EP USB_SERVICE_EP15 +#else + #ifdef DOUBLE_BUFFERING_USED + #define USB_SERVICE_MAX_EP USB_SERVICE_EP6 + #else + #define USB_SERVICE_MAX_EP USB_SERVICE_EP4 + #endif +#endif +#else +/* device is Kinetis K20D72 << EST */ +#ifdef DOUBLE_BUFFERING_USED + #define USB_SERVICE_MAX_EP USB_SERVICE_EP6 +#else + #define USB_SERVICE_MAX_EP USB_SERVICE_EP4 +#endif +#endif + +/* Informational Request/Set Types */ +/* component parameter in USB_Device_Get/Set_Status */ +#define USB_COMPONENT_DIRECTION_SHIFT (7) +#define USB_COMPONENT_DIRECTION_MASK (0x01) +#define USB_STATUS_DEVICE_STATE (0x01) +#define USB_STATUS_INTERFACE (0x02) +#define USB_STATUS_ADDRESS (0x03) +#define USB_STATUS_CURRENT_CONFIG (0x04) +#define USB_STATUS_SOF_COUNT (0x05) +#define USB_STATUS_DEVICE (0x06) + +// Endpoint attributes +#define EP_TRANSFER_TYPE_CONTROL (0x0<<0) +#define EP_TRANSFER_TYPE_ISOCHRONOUS (0x1<<0) +#define EP_TRANSFER_TYPE_BULK (0x2<<0) +#define EP_TRANSFER_TYPE_INTERRUPT (0x3<<0) + +/* Standard Request Code */ +#define GET_STATUS 0x0 +#define CLEAR_FEATURE 0x1 +#define SET_FEATURE 0x3 +#define SET_ADDRESS 0x5 +#define GET_DESCRIPTOR 0x6 +#define SET_DESCRIPTOR 0x7 +#define GET_CONFIGURATION 0x8 +#define SET_CONFIGURATION 0x9 +#define GET_INTERFACE 0xA +#define SET_INTERFACE 0xB +#define SYNCH_FRAME 0xC + +#ifdef OTG_BUILD + #define USB_STATUS_OTG (0x07) + #define USB_STATUS_TEST_MODE (0x08) +#else + #define USB_STATUS_TEST_MODE (0x07) +#endif + +#define USB_STATUS_ENDPOINT (0x10) +#define USB_STATUS_ENDPOINT_NUMBER_MASK (0x0F) + +#define UNINITIALISED_VAL (0xFFFFFFFF) + +#if 0 /* << EST */ +#if (defined MCU_MK40N512VMD100) || (defined MCU_MK53N512CMD100) || (defined MCU_MK60N512VMD100) || (defined MCU_MK70F12) + #define USB_DEVICE_ASSERT_RESUME() USB0_CTL |= USB_CTL_RESUME_MASK; + #define USB_DEVICE_DEASSERT_RESUME() USB0_CTL &= ~USB_CTL_RESUME_MASK; +#elif (defined _MC9S08JE128_H) || (defined _MC9S08JM16_H) || defined(_MC9S08JM60_H) || (defined _MC9S08JS16_H) || (defined _MC9S08MM128_H) + #define USB_DEVICE_ASSERT_RESUME() CTL_CRESUME = 1; + #define USB_DEVICE_DEASSERT_RESUME() CTL_CRESUME = 0; +#elif (defined _MCF51JE256_H) || (defined MCU_mcf51jf128) || defined(_MCF51MM256_H) + #define USB_DEVICE_ASSERT_RESUME() USBTRC0_USBRESMEN = 1; + #define USB_DEVICE_DEASSERT_RESUME() USBTRC0_USBRESMEN = 0; +#elif (defined __MCF52221_H__) || defined(__MCF52259_H__) + #define USB_DEVICE_ASSERT_RESUME() CTL |= MCF_USB_OTG_CTL_RESUME; + #define USB_DEVICE_DEASSERT_RESUME() CTL &= ~MCF_USB_OTG_CTL_RESUME; +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif + +#define USB_PROCESS_PENDING() ((gu8ProcessPendingFlag != 0) || (gtUSBEPEventFlags != 0)) + + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef void _PTR_ _usb_device_handle; +typedef uint_8 T_EP_BITFIELD; + +#if 0 /* << EST */ +#if !(defined _MC9S08JE128_H) && !(defined _MC9S08JM16_H) && !defined(_MC9S08JM60_H) && !(defined _MC9S08JS16_H) && !(defined _MC9S08MM128_H) +#pragma pack (1) /* Enforce 1 byte struct alignment */ +#endif +#else +#ifndef __HIWARE__ +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) /* Enforce 1 byte struct alignment */ +#endif +#endif + +#ifdef __MK_xxx_H__ + #if (defined(__CWCC__) || defined(__GNUC__)) + #define ALIGN __attribute__ ((packed)) + #elif((defined __IAR_SYSTEMS_ICC__) || (defined __CC_ARM)) + #define ALIGN + #else + #define ALIGN + #endif +#else + #define ALIGN +#endif + +typedef struct _USB_DEV_EVENT_STRUCT +{ + uint_8 controller_ID; /* controller ID */ + uint_8 ep_num; + boolean setup; /* is setup packet */ + boolean direction; /* direction of endpoint */ + uint_8* buffer_ptr; /* pointer to buffer */ + uint_8 errors; /* Any errors */ + USB_PACKET_SIZE len; /* buffer size of endpoint */ +}ALIGN USB_DEV_EVENT_STRUCT, *PTR_USB_DEV_EVENT_STRUCT; + +// Same endpoint can have multiple function assignments in g_usb_CB, depending on user input +#ifndef MULTIPLE_DEVICES + typedef void(_CODE_PTR_ const USB_SERVICE_CALLBACK)(PTR_USB_DEV_EVENT_STRUCT); +#else + typedef void(_CODE_PTR_ USB_SERVICE_CALLBACK)(PTR_USB_DEV_EVENT_STRUCT); +#endif + +typedef struct _USB_EP_STRUCT +{ + uint_8 ep_num; /* endpoint number */ + uint_8 type; /* type of endpoint */ + uint_8 direction; /* direction of endpoint */ + USB_PACKET_SIZE size ALIGN; /* buffer size of endpoint */ +}ALIGN USB_EP_STRUCT, *USB_EP_STRUCT_PTR; + +#if (defined(__CWCC__))/*||defined(__GNUC__))*/ /* << EST: that pragma does not exist for gcc */ + #pragma options align = reset +#elif defined(__GNUC__) /* << EST */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) + #pragma pack() +#endif + + +extern volatile uint_8 gu8ProcessPendingFlag; +extern volatile T_EP_BITFIELD gtUSBEPEventFlags; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 _usb_device_init ( + uint_8 device_number, + _usb_device_handle _PTR_ handle, + uint_8 number_of_endpoints, + uint_8 bVregEn +); + +extern uint_8 _usb_device_deinit(void); + +extern uint_8 _usb_device_init_endpoint( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_16 max_packet_size, + uint_8 direction, + uint_8 endpoint_type, + uint_8 flag +); + +extern uint_8 _usb_device_cancel_transfer ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern uint_8 _usb_device_deinit_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern uint_8 _usb_device_recv_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint8_ptr buffer_ptr, + uint_32 size +); + +extern uint_8 _usb_device_send_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint8_ptr buffer_ptr, + uint_32 size +); + +extern uint_8 _usb_device_get_send_buffer ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8_ptr *buff_ptr, /* [OUT] Buffer for IN endpoint */ + USB_PACKET_SIZE *size /* [OUT] Size of IN endpoint */ +); + +extern void _usb_device_shutdown ( + _usb_device_handle handle +); + +extern void _usb_device_stall_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_unstall_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_read_setup_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8_ptr buffer_ptr +); + +extern uint_8 _usb_device_get_status ( + _usb_device_handle handle, + uint_8 component, + uint_8_ptr status +); + +extern uint_8 _usb_device_set_status ( + _usb_device_handle handle, + uint_8 component, + uint_8 setting +); + +extern void _usb_device_clear_data0_endpoint( + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_assert_resume ( + _usb_device_handle handle +); + +extern uint_8 _usb_device_register_service ( + uint_8 controller_ID, + uint_8 type, + USB_SERVICE_CALLBACK service +); + +extern uint_8 _usb_device_unregister_service ( + _usb_device_handle handle, + uint_8 event_endpoint +); + +extern uint_8 _usb_device_get_transfer_status ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_set_address ( + _usb_device_handle handle, + uint_8 address +); + +extern uint_8 USB_Device_Call_Service( + uint_8 type, + PTR_USB_DEV_EVENT_STRUCT event +); + +extern void USB_Engine(void); + +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c new file mode 100644 index 0000000..a346225 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c @@ -0,0 +1,629 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_driver.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains S08 USB stack device layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_devapi.h" /* USB Device Layer API Header File */ +#include "usb_dciapi.h" /* USB Controller API Header File */ +#ifdef _MK_xxx_H_ + #include "usb_dci_kinetis.h" +#endif +#ifndef MULTIPLE_DEVICES + #include "USB_Config.h" +#endif + +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + + +/**************************************************************************** + * Global Variables + ****************************************************************************/ +extern void USB_Control_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Reset_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Sof_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Resume_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Suspend_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Error_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Stall_Service (PTR_USB_DEV_EVENT_STRUCT event ); + +/* Array of USB Service pointers */ +#ifdef MULTIPLE_DEVICES + static USB_SERVICE_CALLBACK g_usb_CB[USB_SERVICE_MAX]; +#else + static USB_SERVICE_CALLBACK g_usb_CB[USB_SERVICE_MAX] = { + USB_EP0_CALLBACK, + USB_EP1_CALLBACK, + USB_EP2_CALLBACK, + USB_EP3_CALLBACK, + USB_EP4_CALLBACK, + USB_EP5_CALLBACK, + USB_EP6_CALLBACK, + USB_EP7_CALLBACK, + USB_EP8_CALLBACK, + USB_EP9_CALLBACK, + USB_EP10_CALLBACK, + USB_EP11_CALLBACK, + USB_EP12_CALLBACK, + USB_EP13_CALLBACK, + USB_EP14_CALLBACK, + USB_EP15_CALLBACK, + USB_BUS_RESET_CALLBACK, + USB_SUSPEND_CALLBACK, + USB_SOF_CALLBACK, + USB_RESUME_CALLBACK, + USB_SLEEP_CALLBACK, + USB_SPEED_DETECTION_CALLBACK, + USB_ERROR_CALLBACK, + USB_STALL_CALLBACK +}; +#endif +/* Array of USB Component Status */ +/* Test mode is the last service */ +static uint_8 g_usb_component_status[USB_STATUS_TEST_MODE]; +/* Array of USB Endpoint Status */ +static uint_8 g_usb_ep_status[MAX_SUPPORTED_ENDPOINTS]; +/* Current un-initialized non CONTROL Endpoint */ +static uint_8 g_EPn=0; +/* Maximum number of Non CONTROL Endpoint required by upper layer */ +static uint_8 g_EPn_max=0; + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes - None + *****************************************************************************/ +static void USB_Device_Init_Params(void); + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions + *****************************************************************************/ +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/***************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_DCI_DeInit(void); + +/**************************************************************************//*! + * + * @name USB_Device_Init_Params + * + * @brief The function initializes the Device Layer Structures + * + * @param None + * + * @return None + * + ****************************************************************************** + * Initializes USB Device Layer Structures + *****************************************************************************/ +static void USB_Device_Init_Params(void) +{ + uint_8 loop_index=0; + + g_EPn= g_EPn_max; /* 1 control endpoint */ + + /* + Initialize USB_STATUS_DEVICE_STATE, USB_STATUS_INTERFACE, + USB_STATUS_ADDRESS, USB_STATUS_CURRENT_CONFIG, USB_STATUS_SOF_COUNT + and USB_STATUS_DEVICE to USB_STATUS_UNKNOWN + */ + for(loop_index = 0; loop_index < USB_STATUS_TEST_MODE; loop_index++) + { + #ifdef OTG_BUILD + if(loop_index != (USB_STATUS_OTG-1)) /* Do not initialize the OTG status with 0xFFFF */ + #endif + { + g_usb_component_status[loop_index] = USB_STATUS_UNKNOWN; + } + } + + /* Initialize status of All Endpoints to USB_STATUS_DISABLED */ + for(loop_index = 0; loop_index < MAX_SUPPORTED_ENDPOINTS; loop_index++) + { + g_usb_ep_status[loop_index] = USB_STATUS_DISABLED; + } +} + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + + +/**************************************************************************//*! + * + * @name _usb_device_init + * + * @brief The function initializes the Device and Controller layer + * + * @param device_number : USB Device controller to initialize + * @param handle : pointer to USB Device handle + * @param number_of_endpoints : Endpoint count of the application + * + * @return status + * USB_OK : When Successfull + * USBERR_INVALID_NUM_OF_ENDPOINTS : When endpoints > max Supported + ****************************************************************************** + * This function initializes the Device layer and the Controller layer of the + * S08 USB stack. It initializes the variables used for this layer and then + * calls the controller layer initialize function + *****************************************************************************/ +uint_8 _usb_device_init ( + uint_8 device_number, /* [IN] USB Device controller to initialize */ + _usb_device_handle _PTR_ handle, /* [IN] Pointer to USB Device handle */ + uint_8 number_of_endpoints, /* [IN] Number of endpoints to initialize */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ + UNUSED(handle); + + /* validate endpoints param */ + if((number_of_endpoints > MAX_SUPPORTED_ENDPOINTS) || + (number_of_endpoints < MIN_SUPPORTED_ENDPOINTS)) + { + return USBERR_INVALID_NUM_OF_ENDPOINTS; + } + + /* init variables */ + g_EPn_max = (uint_8)(number_of_endpoints - 1); + + USB_Device_Init_Params(); + +#ifdef MULTIPLE_DEVICES + /* Initialize all services to null value */ + Clear_Mem((uint_8_ptr)g_usb_CB, + (uint_32)(sizeof(USB_SERVICE_CALLBACK) * USB_SERVICE_MAX), (uint_8)0); +#endif + /* Call controller layer initialization function */ + return USB_DCI_Init(device_number, bVregEn); + +} + +/**************************************************************************//*! + * + * @name _usb_device_deinit + * + * @brief The function de-initializes the Device and Controller layer + * + * @return status + * USB_OK : When Successfull + * USBERR_INVALID_NUM_OF_ENDPOINTS : When endpoints > max Supported + ****************************************************************************** + * This function de-initializes the Device layer and the Controller layer + *****************************************************************************/ +uint_8 _usb_device_deinit(void) +{ + g_EPn_max = 0; + /* Call controller layer de-initialization function */ + return USB_DCI_DeInit(); +} + +/**************************************************************************//*! + * + * @name _usb_device_init_endpoint + * + * @brief The function initializes the endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param max_packet_size : Maximum packet size (in bytes) for the endpoint + * @param direction : Direction of transfer + * @param endpoint_type : Type of endpoint + * @param flag : Zero termination flag + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_INIT_FAILED : When endpoints > max Supported + ****************************************************************************** + * + * This function initializes an endpoint the Device layer and the Controller + * layer in the S08 USB stack. It validate whether all endpoints have already + * been initialized or not and then calls the controller layer endpoint + * initialize function + * + *****************************************************************************/ +uint_8 _usb_device_init_endpoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number*/ + uint_16 max_packet_size, /* [IN] Maximum packet size (in bytes) for the endpoint */ + uint_8 direction, /* [IN] Direction of transfer */ + uint_8 endpoint_type, /* [IN] Type of endpoint */ + uint_8 flag /* [IN] Zero termination flag */ +) +{ + USB_EP_STRUCT ep_str; + + uint_8 status = USB_OK; + + /* check if all endpoint have already been initialised */ + if((g_EPn == 0) && (endpoint_number != CONTROL_ENDPOINT)) + { + return USBERR_EP_INIT_FAILED; + } + + ep_str.direction = direction; + ep_str.ep_num = endpoint_number; + +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H + ep_str.size = max_packet_size; +#else + ep_str.size = (char)max_packet_size; +#endif +#else +/* device is Kinetis K20D72 << EST */ + ep_str.size = max_packet_size; +#endif + + ep_str.type = endpoint_type; + + /* call controller layer for initiazation */ + status = USB_DCI_Init_EndPoint(*((uint_8*)handle), &ep_str, flag); + + /* if endpoint successfully initialised update counter */ + if((ep_str.ep_num != CONTROL_ENDPOINT) && (status == USB_OK)) + { + g_EPn--; + } + + return status; +} + + +/**************************************************************************//*! + * + * @name _usb_device_deinit_endpoint + * + * @brief The function de-initializes the endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_DEINIT_FAILED : When endpoints > max Supported + ****************************************************************************** + * + * This function deinitializes an endpoint the Device layer and the Controller + * layer in the S08 USB stack. It validate whether all endpoints have already + * been deinitialized or not and then calls the controller layer endpoint + * deinitialize function + * + *****************************************************************************/ +uint_8 _usb_device_deinit_endpoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Direction */ +) +{ + uint_8 status=USB_OK; + + /* check if all endpoint have already been initialised */ + if((g_EPn == g_EPn_max) && (endpoint_number != CONTROL_ENDPOINT)) + { + return USBERR_EP_DEINIT_FAILED; + } + + /* call controller layer for initiazation */ + status = USB_DCI_Deinit_EndPoint(*((uint_8*)handle), endpoint_number, direction); + + /* if endpoint successfully deinitialised update counter */ + if((endpoint_number != CONTROL_ENDPOINT) && (status == USB_OK)) + { + g_EPn++; + } + + return status; +} + +/**************************************************************************//*! + * + * @name _usb_device_get_status + * + * @brief The function retrieves various endpoint as well as USB component status + * + * @param handle : USB Device handle + * @param component : USB component + * @param status : Pointer to 16 bit return value + * + * @return status + * USB_OK : When Successfull + * USBERR_BAD_STATUS : When error + * + ****************************************************************************** + * This function retrieves the endpoint as well USB component status which is + * stored by calling USB_Device_Set_Status. This function can be called by Ap- + * plication as well as the DCI layer. + *****************************************************************************/ +uint_8 _usb_device_get_status ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 component, /* [IN] USB component */ + uint_8_ptr status /* [OUT] Pointer to 16 bit return value */ +) +{ + /* get the endpoint number from component input variable */ + uint_8 ep_num = (uint_8)(component & USB_STATUS_ENDPOINT_NUMBER_MASK); + UNUSED (handle); + + if((component <= USB_STATUS_TEST_MODE) && + (component >= USB_STATUS_DEVICE_STATE)) + { + /* Get the corresponding component status + -1 as components start from 1 */ + *status = g_usb_component_status[component-1]; + } + else if((component & USB_STATUS_ENDPOINT) && + (ep_num < MAX_SUPPORTED_ENDPOINTS)) + { + /* Get the corresponding endpoint status */ + *status = g_usb_ep_status[ep_num]; + } + else + { + return USBERR_BAD_STATUS; + } + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name _usb_device_set_status + * + * @brief The function saves status of endpoints as well as USB components. + * + * @param handle : USB Device handle + * @param component : USB component + * @param setting : Value to be set + * + * @return status + * USB_OK : When Successfull + * USBERR_BAD_STATUS : When error + * + ****************************************************************************** + * This function sets the endpoint as well USB component status which can be + * retrieved by calling _usb_device_get_status. This function can be called by + * Application as well as the DCI layer. + *****************************************************************************/ +uint_8 _usb_device_set_status( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 component, /* [IN] USB Component status to set */ + uint_8 setting /* [IN] Status to set */ +) +{ + /* get the endpoint number from component input variable */ + uint_8 ep_num = (uint_8)(component & USB_STATUS_ENDPOINT_NUMBER_MASK); + UNUSED (handle); + + if((component <= USB_STATUS_TEST_MODE) && + (component >= USB_STATUS_DEVICE_STATE)) + { + /* + Set the corresponding component setting + -1 as components start from 1 + */ + g_usb_component_status[component-1] = setting; + } + else if((component & USB_STATUS_ENDPOINT) && + (ep_num < MAX_SUPPORTED_ENDPOINTS)) + { + uint_8 direction = + (uint_8)((component >> USB_COMPONENT_DIRECTION_SHIFT) & + USB_COMPONENT_DIRECTION_MASK); + /* HALT Endpoint */ + if(setting == USB_STATUS_STALLED) + { + _usb_device_stall_endpoint(handle, ep_num, direction); + } + else if((setting == USB_STATUS_IDLE) && + (g_usb_ep_status[ep_num] == USB_STATUS_STALLED)) + { + _usb_device_unstall_endpoint(handle, ep_num, direction); + + if(ep_num == CONTROL_ENDPOINT) + { + direction = (uint_8)((direction == USB_SEND)? + (USB_RECV):(USB_SEND)); + _usb_device_unstall_endpoint(handle, ep_num, direction); + } + } + /* Set the corresponding endpoint setting */ + g_usb_ep_status[ep_num] = setting; + } + else + { + return USBERR_BAD_STATUS; + } + return USB_OK; +} + +/**************************************************************************//*! + * + * @name _usb_device_register_service + * + * @brief The function registers a callback function from the Application layer + * + * @param controller_ID : Controller ID + * @param type : event type or endpoint number + * @param service : callback function pointer + * + * @return status + * USB_OK : When Successfull + * USBERR_ALLOC_SERVICE : When invalid type or already registered + * + ****************************************************************************** + * This function registers a callback function from the application if it is + * called not already registered so that the registered callback function can + * be if the event of that type occurs + *****************************************************************************/ +uint_8 _usb_device_register_service( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 type, /* [IN] type of event or endpoint + number to service */ + USB_SERVICE_CALLBACK service /* [IN] pointer to callback + function */ +) +{ + UNUSED (controller_ID); + UNUSED (service); +#ifdef MULTIPLE_DEVICES + /* check if the type is valid and callback for the type + is not already registered */ + if(((type <= USB_SERVICE_MAX_EP) || + ((type < USB_SERVICE_MAX) && (type >= USB_SERVICE_BUS_RESET))) && + (g_usb_CB[type] == NULL)) + { + + /* register the callback function */ + g_usb_CB[type] = service; + return USB_OK; + } + else + { + return USBERR_ALLOC_SERVICE; + } +#else + UNUSED(type); + return USB_OK; +#endif + +} + +/**************************************************************************//*! + * + * @name _usb_device_unregister_service + * + * @brief The function unregisters an event or endpoint callback function + * + * @param handle : USB Device handle + * @param event_endpoint : event type or endpoint number + * + * @return status + * USB_OK : When Successfull + * USBERR_UNKNOWN_ERROR : When invalid type or not registered + * + ***************************************************************************** + * This function un registers a callback function which has been previously + * registered by the application layer + *****************************************************************************/ +uint_8 _usb_device_unregister_service( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 event_endpoint /* [IN] Endpoint (0 through 15) or event to service */ +) +{ + UNUSED (handle); + /* check if the type is valid and callback for the type + is already registered */ + if(((event_endpoint <= USB_SERVICE_MAX_EP) || + ((event_endpoint < USB_SERVICE_MAX) && (event_endpoint >= USB_SERVICE_BUS_RESET))) && + (g_usb_CB[event_endpoint] != NULL)) + { +#ifdef MULTIPLE_DEVICES + /* unregister the callback */ + g_usb_CB[event_endpoint] = NULL; +#endif + return USB_OK; + } + else + { + return USBERR_UNKNOWN_ERROR; + } +} + +/**************************************************************************//*! + * + * @name USB_Device_Call_Service + * + * @brief The function is a device layer event handler + * + * @param type : Type of service or endpoint + * @param event : Pointer to event structure + * + * @return status + * USB_OK : Always + * + ***************************************************************************** + * + * This function calls the registered service callback function of the applic- + * ation layer based on the type of event received. This function is called + * from the DCI layer. + * + *****************************************************************************/ +uint_8 USB_Device_Call_Service( + uint_8 type, /* [IN] Type of service or endpoint */ + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to event structure */ +) +{ + + if(type == USB_SERVICE_BUS_RESET) + { /* if it is an reset interrupt then reset all status structures */ + USB_Device_Init_Params(); + } + + /* check if the callback is registered or not */ + if(g_usb_CB[type] != NULL) + { + /* call the callback function */ + g_usb_CB[type](event); + } + + return USB_OK; +} + +void USB_NULL_CALLBACK (PTR_USB_DEV_EVENT_STRUCT event) +{ + UNUSED(event); + + #if (defined(__CWCC__) || defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)) + asm("nop"); + #elif defined (__CC_ARM) + __nop(); + #endif +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c new file mode 100644 index 0000000..e2239e7 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c @@ -0,0 +1,1177 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_framework.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains USB stack framework module implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" /* Contains User Defined Data Types */ +#include "usb_class.h" /* USB class Header File */ +#include "usb_framework.h" /* USB Framework Header File */ +#include "usb_descriptor.h" /* USB descriptor Header File */ +#if defined(__IAR_SYSTEMS_ICC__) +#include +#endif +#ifdef OTG_BUILD +#include "usb_otg_main.h" /* OTG header file */ +#endif +#include +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ +/**************************************************************************** + * Global Variables + ****************************************************************************/ +static USB_SETUP_STRUCT g_setup_pkt; + +/*is used to store the value of data which needs to be sent to the USB +host in response to the standard requests.*/ +static uint_16 g_std_framework_data; +/*used to store the address received in Set Address in the standard request.*/ +static uint_8 g_assigned_address; +/* Framework module callback pointer */ +static USB_CLASS_CALLBACK g_framework_callback=NULL; +/* Other Requests Callback pointer */ +static USB_REQ_FUNC g_other_req_callback=NULL; + +#ifdef DELAYED_PROCESSING +static USB_DEV_EVENT_STRUCT g_f_event; +/* initially no pending request */ +static boolean g_control_pending=FALSE; +#endif + + +boolean const g_validate_request[MAX_STRD_REQ][3] = +{ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Get_Status*/ + /* configured state: valid for existing interfaces/endpoints + address state : valid only for interface or endpoint 0 + default state : not specified + */ + {TRUE,TRUE,FALSE}, /* Clear Feature */ + /* configured state: valid only for device in configured state + address state : valid only for device (in address state), + interface and endpoint 0 + default state : not specified + */ + {FALSE,FALSE,FALSE}, /*reserved for future use*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ +#ifdef OTG_BUILD + {TRUE,TRUE,TRUE}, /* Set Feature */ + /* configured state: A B-device that supports OTG features + address state : shall be able to accept the SetFeature command + default state : in the Default, Addressed and Configured states + */ +#else + {TRUE,TRUE,FALSE}, /* Set Feature */ + /* configured state: valid only for device in configured state + address state : valid only for interface or endpoint 0 + default state : not specified + */ +#endif + + {FALSE,FALSE,FALSE},/*reserved for future use*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ + {FALSE,TRUE,TRUE}, /*USB_Strd_Req_Set_Address*/ + /* configured state: not specified + address state : changes to default state if specified addr == 0, + but uses newly specified address + default state : changes to address state if specified addr != 0 + */ + {TRUE,TRUE,TRUE}, /*USB_Strd_Req_Get_Descriptor*/ + /* configured state: valid request + address state : valid request + default state : valid request + */ + {FALSE,FALSE,FALSE}, /*Set Descriptor*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Get_Config*/ + /* configured state: bConfiguration Value of current config returned + address state : value zero must be returned + default state : not specified + */ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Set_Config*/ + /* configured state: If the specified configuration value is zero, + then the device enters the Address state.If the + specified configuration value matches the + configuration value from a config descriptor, + then that config is selected and the device + remains in the Configured state. Otherwise, the + device responds with a Request Error. + + address state : If the specified configuration value is zero, + then the device remains in the Address state. If + the specified configuration value matches the + configuration value from a configuration + descriptor, then that configuration is selected + and the device enters the Configured state. + Otherwise,response is Request Error. + default state : not specified + */ + {TRUE,FALSE,FALSE}, /*USB_Strd_Req_Get_Interface*/ + /* configured state: valid request + address state : request error + default state : not specified + */ + {TRUE,FALSE,FALSE}, /*USB_Strd_Req_Set_Interface*/ + /* configured state: valid request + address state : request error + default state : not specified + */ + {TRUE,FALSE,FALSE} /*USB_Strd_Req_Sync_Frame*/ + /* configured state: valid request + address state : request error + default state : not specified + */ +}; +/***************************************************************************** + * Global Functions Prototypes - None + *****************************************************************************/ + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +void USB_Control_Service (PTR_USB_DEV_EVENT_STRUCT event ); +static void USB_Control_Service_Handler(uint_8 controller_ID, + uint_8 status, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Status(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Feature(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Address(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Assign_Address(uint_8 controller_ID); +static uint_8 USB_Strd_Req_Get_Config(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Config(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Interface(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Interface(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Sync_Frame(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Descriptor(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +#ifdef DELAYED_PROCESSING +static void USB_Control_Service_Callback(PTR_USB_DEV_EVENT_STRUCT event ); +#endif + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables + *****************************************************************************/ + +/* used for extended OUT transactions on CONTROL ENDPOINT*/ +static USB_SETUP_STRUCT ext_req_to_host_setup; +static uint_8 ext_req_to_host_buffer[USB_OUT_PKT_SIZE]; + + +/***************************************************************************** + * Global Variables + *****************************************************************************/ +USB_REQ_FUNC +#if 0 /* << EST */ +#if ((!defined(_MC9S08MM128_H)) && (!defined(_MC9S08JE128_H))) +const +#endif +#else +/* device is Kinetis K20D72 << EST */ +const +#endif +g_standard_request[MAX_STRD_REQ] = +{ + USB_Strd_Req_Get_Status, + USB_Strd_Req_Feature, + NULL, + USB_Strd_Req_Feature, + NULL, + USB_Strd_Req_Set_Address, + USB_Strd_Req_Get_Descriptor, + NULL, + USB_Strd_Req_Get_Config, + USB_Strd_Req_Set_Config, + USB_Strd_Req_Get_Interface, + USB_Strd_Req_Set_Interface, + USB_Strd_Req_Sync_Frame +}; + +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/**************************************************************************//*! + * + * @name USB_Framework_Init + * + * @brief The function initializes the Class Module + * + * @param controller_ID : Controller ID + * @param class_callback : Class callback pointer + * @param other_req_callback: Other Request Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + * + ****************************************************************************** + * This function registers the service on the control endpoint + *****************************************************************************/ +uint_8 USB_Framework_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK class_callback, /* Class Callback */ + USB_REQ_FUNC other_req_callback /* Other Request Callback */ +) +{ + uint_8 error=USB_OK; + + /* save input parameters */ + g_framework_callback = class_callback; + g_other_req_callback = other_req_callback; + + /* Register CONTROL service */ + error = _usb_device_register_service(controller_ID, USB_SERVICE_EP0, + +#ifdef DELAYED_PROCESSING + USB_Control_Service_Callback +#else + USB_Control_Service +#endif + ); + + return error; +} + +/**************************************************************************//*! + * + * @name USB_Framework_DeInit + * + * @brief The function De-initializes the Class Module + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * Others : Errors + * + ****************************************************************************** + * This function unregisters control service + *****************************************************************************/ +uint_8 USB_Framework_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 error; + /* Free framwork_callback */ + g_framework_callback = NULL; + + /* Free other_req_callback */ + g_other_req_callback = NULL; + + /* Unregister CONTROL service */ + error = _usb_device_unregister_service(&controller_ID, USB_SERVICE_EP0); + + /* Return error */ + return error; +} +#ifdef DELAYED_PROCESSING +/**************************************************************************//*! + * + * @name USB_Framework_Periodic_Task + * + * @brief The function is called to respond to any control request + * + * @param None + * + * @return None + * + ****************************************************************************** + * This function checks for any pending requests and handles them if any + *****************************************************************************/ +void USB_Framework_Periodic_Task(void) +{ + /* if control request pending to be completed */ + if(g_control_pending==TRUE) + { + /* handle pending control request */ + USB_Control_Service(&g_f_event); + g_control_pending = FALSE; + } +} +#endif +/**************************************************************************//*! + * + * @name USB_Framework_Reset + * + * @brief The function resets the framework + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * + ****************************************************************************** + * This function is used to reset the framework module + *****************************************************************************/ +uint_8 USB_Framework_Reset ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return USB_OK; +} + +#ifdef DELAYED_PROCESSING +/**************************************************************************//*! + * + * @name USB_Control_Service_Callback + * + * @brief The function can be used as a callback function to the service. + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * This function saves the event parameters and queues a pending request + *****************************************************************************/ +void USB_Control_Service_Callback ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* save the event parameters */ + g_f_event.buffer_ptr = event->buffer_ptr; + g_f_event.controller_ID = event->controller_ID; + g_f_event.ep_num = event->ep_num; + g_f_event.setup = event->setup; + g_f_event.len = event->len; + g_f_event.errors = event->errors; + + /* set the pending request flag */ + g_control_pending = TRUE; + +} +#endif + +/**************************************************************************//*! + * + * @name USB_Control_Service + * + * @brief Called upon a completed endpoint 0 transfer + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * This function handles the data sent or received on the control endpoint + *****************************************************************************/ +void USB_Control_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_8 device_state = 0; + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_8_ptr data = NULL; + USB_PACKET_SIZE size; + + /* get the device state */ + (void)_usb_device_get_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + &device_state); + + if(event->setup == TRUE) + { + /* get the setup packet */ + (void)memcpy(&g_setup_pkt, event->buffer_ptr, USB_SETUP_PKT_SIZE); + + /* take care of endianess of the 16 bt fields correctly */ + g_setup_pkt.index = BYTE_SWAP16(g_setup_pkt.index); + g_setup_pkt.value = BYTE_SWAP16(g_setup_pkt.value); + g_setup_pkt.length = BYTE_SWAP16(g_setup_pkt.length); + + /* if the request is standard request */ + if((g_setup_pkt.request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_STRD) + { + /* if callback is not NULL */ + if(g_standard_request[g_setup_pkt.request] != NULL) + { + /* if the request is valid in this device state */ + if((device_state < USB_STATE_POWERED) && + (g_validate_request[g_setup_pkt.request][device_state] + ==TRUE)) + { + /* Standard Request function pointers */ + status = g_standard_request[g_setup_pkt.request] + (event->controller_ID, &g_setup_pkt, &data, + (USB_PACKET_SIZE *)&size); + } + } + } + else /* for Class/Vendor requests */ + { + /*get the length from the setup_request*/ + size = (USB_PACKET_SIZE)g_setup_pkt.length; + if(size <= USB_OUT_PKT_SIZE) { + if( (size != 0) && + ((g_setup_pkt.request_type & USB_DATA_DIREC_MASK) == + USB_DATA_TO_DEVICE) ) + { + (void)memcpy(&ext_req_to_host_setup, &g_setup_pkt, USB_SETUP_PKT_SIZE); + + /* expecting host to send data (OUT TRANSACTION)*/ + (void)_usb_device_recv_data(&(event->controller_ID), + CONTROL_ENDPOINT, ext_req_to_host_buffer, + (USB_PACKET_SIZE)(size)); + return; + } + else if(g_other_req_callback != NULL)/*call class/vendor request*/ + { + status = g_other_req_callback(event->controller_ID, + &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + } + } + else + { + /* incase of error Stall endpoint */ + USB_Control_Service_Handler(event->controller_ID, + USBERR_INVALID_REQ_TYPE, &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + return; + } + } + + USB_Control_Service_Handler(event->controller_ID, + status, &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + } + /* if its not a setup request */ + else if(device_state == USB_STATE_PENDING_ADDRESS) + { + /* Device state is PENDING_ADDRESS */ + /* Assign the new adddress to the Device */ + (void)USB_Strd_Req_Assign_Address(event->controller_ID); + return; + } + else if( ((g_setup_pkt.request_type & + USB_DATA_DIREC_MASK) == USB_DATA_TO_DEVICE) && + (event->direction == USB_RECV) ) + { + /* execution enters Control Service because of + OUT transaction on CONTROL_ENDPOINT*/ + if(g_other_req_callback != NULL) + { /* class or vendor request */ + size = (USB_PACKET_SIZE)(event->len + USB_SETUP_PKT_SIZE); + status = g_other_req_callback(event->controller_ID, + &ext_req_to_host_setup, &data, + &size); + } + + USB_Control_Service_Handler(event->controller_ID, + status, &g_setup_pkt, &data, + (USB_PACKET_SIZE*)&size); + } + return; +} + +/**************************************************************************//*! + * + * @name USB_Control_Service_Handler + * + * @brief The function is used to send a response to the Host based. + * + * @param controller_ID : Controller ID + * @param status : Status of request + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return None + * + ****************************************************************************** + * This function sends a response to the data received on the control endpoint. + * the request is decoded in the control service + *****************************************************************************/ +static void USB_Control_Service_Handler ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 status, /* [IN] Device Status */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + if(status == USBERR_INVALID_REQ_TYPE) + { + /* incase of error Stall endpoint */ + (void)_usb_device_set_status(&controller_ID, + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (USB_SEND << USB_COMPONENT_DIRECTION_SHIFT)), + USB_STATUS_STALLED); + } + else /* Need to send Data to the USB Host */ + { + /* send the data prepared by the handlers.*/ + if(*size > setup_packet->length) + { + *size = (USB_PACKET_SIZE)setup_packet->length; + } + + /* send the data to the host */ + (void)USB_Class_Send_Data(controller_ID, + CONTROL_ENDPOINT, *data, *size); + if((setup_packet->request_type & USB_DATA_DIREC_MASK) == + USB_DATA_TO_HOST) + { /* Request was to Get Data from device */ + /* setup rcv to get status from host */ + (void)_usb_device_recv_data(&controller_ID, + CONTROL_ENDPOINT,NULL,0); + } + + } + return; +} +/*************************************************************************//*! + * + * @name USB_Strd_Req_Get_Status + * + * @brief This function is called in response to Get Status request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is called by the host to know the status of the + * device, the interface and the endpoint + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Status ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8_ptr pu8ConfigDesc = NULL; + uint_16 u16DescSize; + uint_8 interface, endpoint = 0; + uint_8 status; + uint_8 device_state = USB_STATE_POWERED; + + + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE_STATE, &device_state); + + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_DEVICE) + { + #ifdef OTG_BUILD + if(setup_packet->index == USB_WINDEX_OTG_STATUS_SEL) + { + uint_8 temp; + /* Request for Device */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_OTG, &temp); + g_std_framework_data = (uint_16)temp; + g_std_framework_data &= GET_STATUS_OTG_MASK; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *size = OTG_STATUS_SIZE; + } + else + #endif + { + uint_8 device_state1; + + /* Request for Device */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_state1); + g_std_framework_data = (uint_16)device_state1; + g_std_framework_data &= GET_STATUS_DEVICE_MASK; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + + /* Set Self Powered bit in device state according to configuration */ + status = USB_Desc_Get_Descriptor(controller_ID, USB_CONFIG_DESCRIPTOR, + 0, 0, &pu8ConfigDesc, (USB_PACKET_SIZE *)&u16DescSize); + + if((pu8ConfigDesc[7] & SELF_POWERED) != 0) + { + g_std_framework_data |= BYTE_SWAP16(0x0001); + } + else + { + g_std_framework_data &= BYTE_SWAP16(~0x0001); + } + *size = DEVICE_STATUS_SIZE; + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_INTERFACE) + { + /* Request for Interface */ + interface = (uint_8) setup_packet->index; + if((device_state == USB_STATE_ADDRESS) && (interface > 0)) + { + status = USBERR_INVALID_REQ_TYPE; + } + else + { + /* Interface requests always return 0 */ + g_std_framework_data = 0x0000; + *size = INTERFACE_STATUS_SIZE; + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_ENDPOINT) + { + /* Request for Endpoint */ + if((device_state == USB_STATE_ADDRESS) && (endpoint > 0)) + { + status = USBERR_INVALID_REQ_TYPE; + } + else + { + uint_8 device_state2; + endpoint = (uint_8)(((uint_8) setup_packet->index) | + USB_STATUS_ENDPOINT); + status = _usb_device_get_status(&controller_ID, + endpoint, + &device_state2); + g_std_framework_data = (uint_16)device_state2; + /* All other fields except HALT must be zero */ + g_std_framework_data &= 0x0001; /* LSB is for the HALT feature */ + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *size = ENDP_STATUS_SIZE; + } + } + + *data = (uint_8_ptr)&g_std_framework_data; + return status; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Feature + * + * @brief This function is called in response to Clear or Set Feature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request, used to set/clear a feature on the device + * (device_remote_wakeup and test_mode) or on the endpoint(ep halt) + *****************************************************************************/ +static uint_8 USB_Strd_Req_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 device_status; + uint_8 set_request; + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_8 epinfo; + uint_8 event; + + UNUSED (data); + + *size=0; + /* Find whether its a clear feature request or a set feature request */ + set_request = (uint_8)((setup_packet->request & USB_SET_REQUEST_MASK) >> 1 ); + + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_DEVICE) + { + /* Request for Device */ + if(set_request == TRUE) + { + /* Standard Feature Selector */ + if((setup_packet->value == DEVICE_FEATURE_REMOTE_WAKEUP) || (setup_packet->value == DEVICE_FEATURE_TEST_MODE)) + { + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_status); + + if(status == USB_OK) + { + /* Add the request to be set to the device_status */ + device_status |= (uint_16)(1 << (uint_8)setup_packet->value); + + /* Set the status on the device */ + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE, device_status); + } + } + #ifdef OTG_BUILD + /* OTG Feature Selector */ + else if(setup_packet->value == DEVICE_SET_FEATURE_B_HNP_ENABLE) + { + OTG_DESCRIPTOR_PTR_T otg_desc_ptr; + USB_PACKET_SIZE size; + + status = USB_Desc_Get_Descriptor(controller_ID, USB_OTG_DESCRIPTOR,(uint_8)UNINITIALISED_VAL, + (uint_16)UNINITIALISED_VAL,(uint_8_ptr *)&otg_desc_ptr,&size); + if(status == USB_OK) + { + if(otg_desc_ptr->bmAttributes & USB_OTG_HNP_SUPPORT) + { + _usb_otg_hnp_enable(controller_ID, set_request); + } + } + } + #endif + else + { + status = USBERR_INVALID_REQ_TYPE; + } + } + else //(set_request == FALSE) it is a clear feature request + { + if(setup_packet->value == DEVICE_FEATURE_REMOTE_WAKEUP) + { + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_status); + + if(status == USB_OK) + { + /* Remove the request to be cleared from device_status */ + device_status &= (uint_16)~(1 << (uint_8)setup_packet->value); + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE, device_status); + } + } + else + { + status = USBERR_INVALID_REQ_TYPE; + } + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_ENDPOINT) + { + /* Request for Endpoint */ + epinfo = (uint_8)(setup_packet->index & 0x00FF); + status = _usb_device_set_status(&controller_ID, (uint_8)(epinfo|USB_STATUS_ENDPOINT), set_request); + + event = (uint_8)(set_request ? USB_APP_EP_STALLED : USB_APP_EP_UNSTALLED); + + if(setup_packet->request == CLEAR_FEATURE) + { + uint_8 epnum = epinfo & 0x0F; + uint_8 dir = (epinfo & 0x80) >> 7; + _usb_device_clear_data0_endpoint(epnum,dir); + event = USB_APP_EP_UNSTALLED; // as far as the application is concerned, this is an UNSTALL. + } + + /* Inform the upper layers of stall/unstall */ + g_framework_callback(controller_ID,event,(void*)&epinfo); + } + return status; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Address + * + * @brief This function is called in response to Set Address request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request, saves the new address in a global variable. this + * address is assigned to the device after this transaction completes + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Address ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + UNUSED (data); + *size=0; + /* update device state */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE, USB_STATE_PENDING_ADDRESS); + + /*store the address from setup_packet into assigned_address*/ + g_assigned_address = (uint_8)setup_packet->value; + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Assign_Address + * + * @brief This function assigns the address to the Device + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK: Always + * + ****************************************************************************** + * This function assigns the new address and is called (from the control + * service) after the set address transaction completes + *****************************************************************************/ +static uint_8 USB_Strd_Req_Assign_Address ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + /* Set Device Address */ + (void)_usb_device_set_address(&controller_ID, g_assigned_address); + + /* Set Device state */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE, USB_STATE_ADDRESS); + /* Set Device state */ + (void)_usb_device_set_status(&controller_ID, USB_STATUS_ADDRESS, + g_assigned_address); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Get_Config + * + * @brief This function is called in response to Get Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : Always + * + ****************************************************************************** + * This is a ch9 request and is used to know the currently used configuration + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Config ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 device_status; + + UNUSED(setup_packet); + + *size = CONFIG_SIZE; + (void)_usb_device_get_status(&controller_ID, USB_STATUS_CURRENT_CONFIG, &device_status); + g_std_framework_data = (uint_16)device_status; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *data = (uint_8_ptr)(&g_std_framework_data); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Config + * + * @brief This function is called in response to Set Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used by the host to set the new configuration + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Config ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_16 config_val; + + UNUSED (data); + *size = 0; + status = USB_STATUS_ERROR; + config_val = setup_packet->value; + + if(USB_Desc_Valid_Configation(controller_ID, config_val)) + /*if valid configuration (fn returns boolean value)*/ + { + uint_8 device_state = USB_STATE_CONFIG; + + /* if config_val is 0 */ + if(!config_val) + { + device_state = USB_STATE_ADDRESS ; + } + + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE_STATE, + device_state); + status = _usb_device_set_status(&controller_ID, + USB_STATUS_CURRENT_CONFIG, (uint_8)config_val); + /* + Callback to the app. to let the application know about the new + Configuration + */ + g_framework_callback(controller_ID,USB_APP_CONFIG_CHANGED, + (void *)&config_val); + g_framework_callback(controller_ID,USB_APP_ENUM_COMPLETE, NULL); + } + + return status; + } + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Get_Interface + * + * @brief This function is called in response to Get Interface request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used to know the current interface + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + + /* Request type not for interface */ + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) != USB_REQUEST_SRC_INTERFACE) + { + return USB_STATUS_ERROR; + } + else + { + *size = INTERFACE_SIZE; + status = USB_Desc_Get_Interface(controller_ID,(uint_8)setup_packet->index, + (uint_8_ptr)&g_std_framework_data); + *data = (uint_8_ptr)&g_std_framework_data; + + return status; + } +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Interface + * + * @brief This function is called in response to Set Interface request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : Always + * + ****************************************************************************** + * This is a ch9 request and is used by the host to set the interface + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + + UNUSED (data); + *size=0; + + /* Request type not for interface */ + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) != USB_REQUEST_SRC_INTERFACE) + { + return USB_STATUS_ERROR; + } + else + { + /* Set Interface and alternate interface from setup_packet */ + status = USB_Desc_Set_Interface(controller_ID,(uint_8)setup_packet->index, + (uint_8)setup_packet->value); + + UNUSED (status); + + return USB_OK; + } +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Sync_Frame + * + * @brief This function is called in response to Sync Frame request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This req is used to set and then report an ep's synchronization frame + *****************************************************************************/ +static uint_8 USB_Strd_Req_Sync_Frame ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + uint_8 device_status; + + UNUSED(setup_packet); + *size = FRAME_SIZE; + + /* Get the frame number */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_SOF_COUNT, + &device_status); + g_std_framework_data = (uint_16)device_status; + *data = (uint_8_ptr)&g_std_framework_data; + + return status; +} + + +/**************************************************************************//*! + * + * @name USB_Std_Req_Get_Descriptor + * + * @brief This function is called in response to Get Descriptor request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used to send the descriptor requested by the + * host + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Descriptor ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 type = USB_uint_16_high(setup_packet->value); + uint_16 index = (uint_16)UNINITIALISED_VAL; + uint_8 str_num = (uint_8)UNINITIALISED_VAL; + uint_8 status; + + /* for string descriptor set the language and string number */ + index = setup_packet->index; + /*g_setup_pkt.lValue*/ + str_num = USB_uint_16_low(setup_packet->value); + + /* Call descriptor class to get descriptor */ + status = USB_Desc_Get_Descriptor(controller_ID, type, str_num, index, data, size); + + return status; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h new file mode 100644 index 0000000..b709830 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_framwork.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB Framework module API header function. + * + *****************************************************************************/ + +#ifndef _USB_FRAMEWORK_H +#define _USB_FRAMEWORK_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_class.h" +#include "usb_descriptor.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define MAX_STRD_REQ (13) /* Max value of standard request */ +/* size of data to be returned for various Get Desc calls */ +#define DEVICE_STATUS_SIZE (2) +#ifdef OTG_BUILD +#define OTG_STATUS_SIZE (2) +#endif +#define INTERFACE_STATUS_SIZE (2) + +#define CONFIG_SIZE (1) +#define INTERFACE_SIZE (1) +#define FRAME_SIZE (2) +#define ENDP_STATUS_SIZE (2) + +#ifdef OTG_BUILD +#define DEVICE_SET_FEATURE_B_HNP_ENABLE (0x0003) /* B HNP enable SET/CLEAR feature value */ +#define DEVICE_SET_FEATURE_A_HNP_SUPPORT (0x0004) /* A HNP support SET/CLEAR feature value */ +#endif + +/* Standard Feature Selectors */ +#define DEVICE_FEATURE_REMOTE_WAKEUP (0x0001) +#define DEVICE_FEATURE_TEST_MODE (0x0002) +#define DEVICE_SET_FEATURE_MASK ((uint_16)((1<<(DEVICE_FEATURE_REMOTE_WAKEUP)) | (1<<(DEVICE_FEATURE_TEST_MODE)))) +#define DEVICE_CLEAR_FEATURE_MASK ((uint_16)(1<<(DEVICE_FEATURE_REMOTE_WAKEUP))) + + + +#define REPORT_DESCRIPTOR_TYPE (0x22) +#define STRING_DESCRIPTOR_TYPE (0x03) + +/* masks and values for provides of Get Desc information */ +#define USB_REQUEST_SRC_MASK (0x03) +#define USB_REQUEST_SRC_DEVICE (0x00) +#define USB_REQUEST_SRC_INTERFACE (0x01) +#define USB_REQUEST_SRC_ENDPOINT (0x02) + +#define USB_SET_REQUEST_MASK (0x02) + +/* wIndex values for GET_Status */ +#ifdef OTG_BUILD +#define USB_WINDEX_OTG_STATUS_SEL (0xF000) +#endif + +/* for transfer direction check */ +#define USB_DATA_TO_HOST (0x80) +#define USB_DATA_TO_DEVICE (0x00) +#define USB_DATA_DIREC_MASK (0x80) + +#define USB_uint_16_low(x) ((uint_8)x) /* lsb byte */ +#define USB_uint_16_high(x) ((uint_8)(x>>8)) /* msb byte */ + +#ifdef CPU_LITTLE_ENDIAN /* << EST: defined by Processor Expert CPU.h for Kinetis devices */ + #ifndef LITTLE_ENDIAN /* might be defined already on the compiler command line? */ + #define LITTLE_ENDIAN + #endif +#endif + +#if(defined LITTLE_ENDIAN) +#define BYTE_SWAP16(a) (a) +#else +#define BYTE_SWAP16(a) (uint_16)((((uint_16)(a)&0xFF00)>>8) | \ + (((uint_16)(a)&0x00FF)<<8)) +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern boolean USB_Frame_Remote_Wakeup(uint_8 controller_ID); + +#define USB_Frame_Remote_Wakeup USB_Desc_Remote_Wakeup + +typedef struct _app_data_struct +{ + uint_8_ptr data_ptr; /* pointer to buffer */ + USB_PACKET_SIZE data_size; /* buffer size of endpoint */ +}APP_DATA_STRUCT; + +extern uint_8 USB_Framework_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK callback, + USB_REQ_FUNC other_req_callback +); + +extern uint_8 USB_Framework_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Framework_Reset ( + uint_8 controller_ID +); +#ifdef DELAYED_PROCESSING +extern void USB_Framework_Periodic_Task(void); +#endif + +#endif + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h new file mode 100644 index 0000000..b58d26e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_user_config.h << EST 'user_config.h' conflicts with MQX Lite + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains User Modifiable Macros for Virtual COM Loopback + * Application + * + *****************************************************************************/ +#if 0 /* << EST */ +#include "derivative.h" + +#if (defined MCU_MK70F12) || (defined __MCF52277_H__) + #define HIGH_SPEED_DEVICE (0) +#else + #define HIGH_SPEED_DEVICE (0) +#endif + +#if (defined MCU_MK20D7) || (defined MCU_MK40D7) + #define MCGOUTCLK_72_MHZ +#endif + +#if ((defined __MK_xxx_H__)||(defined MCU_mcf51jf128)) + #define KEY_PRESS_SIM_TMR_INTERVAL (1000) /* 2s between simulated key press events */ +#else + #ifdef __MCF52277_H__ + #define BUTTON_PRESS_SIMULATION (1) + #define KEY_PRESS_SIM_TMR_INTERVAL (2000) /* 2s between simulated key press events */ + #endif +#endif + +#else +#include "FSL_USB_Stack_Config.h" + +/* device is Kinetis K20D72 << EST */ +#define HIGH_SPEED_DEVICE (0) + + +#endif +/* + Below two MACROS are required for Virtual COM Loopback + Application to execute +*/ +#define LONG_SEND_TRANSACTION /* support to send large data pkts */ +#define LONG_RECEIVE_TRANSACTION /* support to receive large data pkts */ +#ifndef _MC9S08JS16_H +#define USB_OUT_PKT_SIZE 32 /* Define the maximum data length received from the host */ +#else +#define USB_OUT_PKT_SIZE 16 /* Define the maximum data length received from the host */ +#endif + +/* User Defined MACRO to set number of Timer Objects */ +#define MAX_TIMER_OBJECTS 5 + +#if MAX_TIMER_OBJECTS +/* When Enabled Timer Callback is invoked with an argument */ +#define TIMER_CALLBACK_ARG +#undef TIMER_CALLBACK_ARG +#endif + +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H +#define USB_PACKET_SIZE uint_16 /* support 16/32 bit packet size */ +#else +#define USB_PACKET_SIZE uint_8 /* support 8 bit packet size */ +#endif +#else +/* device is Kinetis K20D72 << EST */ +#define USB_PACKET_SIZE uint_16 /* support 16/32 bit packet size */ +#endif + +#if 0 /* << EST */ +#ifndef _MCF51JM128_H +/* Use double buffered endpoints 5 & 6. To be only used with S08 cores */ +#define DOUBLE_BUFFERING_USED +#endif +#else +/* device is Kinetis K20D72 << EST */ +/* Use double buffered endpoints 5 & 6. To be only used with S08 cores */ +#define DOUBLE_BUFFERING_USED +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c new file mode 100644 index 0000000..ef4190d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c @@ -0,0 +1,46 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file wdt_kinetis.c + * + * @author + * + * @version + * + * @date + * + * @brief This file contains the implementation of the Watchdog service routines on CFV2 + *****************************************************************************/ + +#include "types.h" /* User Defined Data Types */ +#include "hal/derivative.h" /* include peripheral declarations */ +#include "wdt_kinetis.h" /* own header with public declarations */ + +/*****************************************************************************/ +void Watchdog_Reset(void) +{ +#if defined(MCU_MKL25Z4) || defined(MCU_MKL26Z4) || defined(MCU_MKL46Z4) + (void)(RCM_SRS0 |= RCM_SRS0_WDOG_MASK); +#else + (void)(WDOG_REFRESH = 0xA602, WDOG_REFRESH = 0xB480); +#endif +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h new file mode 100644 index 0000000..1efdb26 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file Wdt_kinetis.h + * + * @brief This is the header file for the Watchdog service routines on CFV2 + *****************************************************************************/ + + #ifndef _WDT_KINETIS_ + #define _WDT_KINETIS_ + + /***************************************************************************** + * Public functions + * + ****************************************************************************/ + extern void Watchdog_Reset(void); + + #endif /* _INIT_HW_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c new file mode 100644 index 0000000..9f22f30 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c @@ -0,0 +1,302 @@ +/* + * kinetis_sysinit.c - Default init routines for Flycatcher + * Kinetis ARM systems + * Copyright © 2012 Freescale semiConductor Inc. All Rights Reserved. + */ + +#include "hal/derivative.h" +#include "kinetis_sysinit.h" + +/** + **=========================================================================== + ** External declarations + **=========================================================================== + */ +#if __cplusplus +extern "C" { +#endif +extern unsigned long _estack; +extern void __thumb_startup(void); +#if __cplusplus +} +#endif + +/** + **=========================================================================== + ** Default interrupt handler + **=========================================================================== + */ +void Default_Handler(void) +{ + // Uncomment this breakpoint instruction if you are debugging a hard + // fault during development. If this breakpoint is hit without a + // debugger attached a LOCKUP is triggered. For this processor this + // causes an immediate system reset. + //asm volatile ("bkpt"); + + while(1); + + /* Fault registers: + * 0xE000ED2C: HFSR (HardFault status register) + * 0xE000ED28: MMFSR (MemManage fault status register) + * 0xE000ED34: MMFAR (MemManage fault address register) + * 0xE000ED29: BFSR (BusFault status register) + * 0xE000ED38: BFAR (BusFault address register) + */ +} + +/* Weak definitions of handlers point to Default_Handler if not implemented */ +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); + +void DMA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 0 transfer complete interrupt */ +void DMA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 1 transfer complete interrupt */ +void DMA2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 2 transfer complete interrupt */ +void DMA3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 3 transfer complete interrupt */ +void DMA4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 4 transfer complete interrupt */ +void DMA5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 5 transfer complete interrupt */ +void DMA6_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 6 transfer complete interrupt */ +void DMA7_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 7 transfer complete interrupt */ +void DMA8_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 8 transfer complete interrupt */ +void DMA9_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 9 transfer complete interrupt */ +void DMA10_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 10 transfer complete interrupt */ +void DMA11_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 11 transfer complete interrupt */ +void DMA12_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 12 transfer complete interrupt */ +void DMA13_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 13 transfer complete interrupt */ +void DMA14_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 14 transfer complete interrupt */ +void DMA15_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 15 transfer complete interrupt */ +void DMA_Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA error interrupt */ +void MCMNormal_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* MCM normal interrupt */ +void FlashCmd_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Flash memory command complete interrupt */ +void FlashReadErr_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Flash read collision interrupt */ +void LVD_LVW_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low Voltage Detect, Low Voltage Warning */ +void LLW_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low Leakage Wakeup */ +void Watchdog_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* WDOG or EVM interrupt (shared) */ +void Reserved39_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 39 */ +void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2C0 interrupt */ +void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2C1 interrupt */ +void SPI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI0 interrupt */ +void SPI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI1 interrupt */ +void SPI2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI 2 interrupt */ +void CAN0Msg_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 message buffer (0-15) interrupt */ +void CAN0BusOff_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Bus Off interrupt */ +void CAN0Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Error interrupt */ +void CAN0Xmit_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Transmit warning interrupt */ +void CAN0Rcv_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Recieve warning interrupt */ +void CAN0Wake_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Wake Up interrupt */ +void I2S0_Tx_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2S0 transmit interrupt */ +void I2S0_Rx_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2S0 receive interrupt */ +void CAN1Msg_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Msg interrupt */ +void CAN1BusOff_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1BusOff interrupt */ +void CAN1Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Error interrupt */ +void CAN1Xmit_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Xmit interrupt */ +void CAN1Rcv_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Rcv interrupt */ +void CAN1Wake_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Wake interrupt */ +void Reserved59_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 59 */ +void UART0_LON_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 LON interrupt */ +void UART0_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 receive/transmit interrupt */ +void UART0Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 error interrupt */ +void UART1_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART1 receive/transmit interrupt */ +void UART1Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART1 error interrupt */ +void UART2_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART2 receive/transmit interrupt */ +void UART2Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART2 error interrupt */ +void UART3_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART3 receive/transmit interrupt */ +void UART3Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART3 error interrupt */ +void UART4_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART4 receive/transmit interrupt */ +void UART4Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART4 error interrupt */ +void Reserved71_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 71 */ +void Reserved72_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 72 */ +void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* ADC0 interrupt */ +void ADC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* ADC1 interrupt */ +void CMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP0 interrupt */ +void CMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP1 interrupt */ +void CMP2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP2 interrupt */ +void FTM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM0 fault, all sources interrupt */ +void FTM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM1 fault, all sources interrupt */ +void FTM2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM2 fault, all sources interrupt */ +void CMT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMT interrupt */ +void RTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* RTC alarm interrupt */ +void RTCSeconds_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* RTC seconds interrupt */ +void PIT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 0 interrupt */ +void PIT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 1 interrupt */ +void PIT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 2 interrupt */ +void PIT3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 3 interrupt */ +void PDB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PDB0 interrupt */ +void USB_ISR(void) __attribute__ ((weak, alias("Default_Handler"))); /* USB OTG interrupt */ +void USBCharge_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* USB charger detect interrupt */ +void Reserved91_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 91 */ +void Reserved92_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 92 */ +void Reserved93_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 93 */ +void Reserved94_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 94 */ +void Reserved95_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 95 */ +void SDHC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SDHC interrupt */ +void DAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DAC0 interrupt */ +void Reserved98_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 98 */ +void TSI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* TSI all sources interrupt */ +void MCG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* MCG interrupt */ +void LPTimer_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low-power Timer interrupt */ +void Reserved102_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 102 */ +void PORTA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port A pin detect interrupt */ +void PORTB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port B pin detect interrupt */ +void PORTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port C pin detect interrupt */ +void PORTD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port D pin detect interrupt */ +void PORTE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port E pin detect interrupt */ +void Reserved108_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 108 */ +void Reserved109_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 109 */ +void SWI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Software interrupt */ + +/* The Interrupt Vector Table */ +void (* const InterruptVector[])(void) __attribute__ ((section(".vectortable"))) = { + /* Processor exceptions */ + (void(*)(void)) &_estack, + __thumb_startup, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + /* Interrupts */ + DMA0_IRQHandler, /* DMA channel 0 transfer complete interrupt */ + DMA1_IRQHandler, /* DMA channel 1 transfer complete interrupt */ + DMA2_IRQHandler, /* DMA channel 2 transfer complete interrupt */ + DMA3_IRQHandler, /* DMA channel 3 transfer complete interrupt */ + DMA4_IRQHandler, /* DMA channel 4 transfer complete interrupt */ + DMA5_IRQHandler, /* DMA channel 5 transfer complete interrupt */ + DMA6_IRQHandler, /* DMA channel 6 transfer complete interrupt */ + DMA7_IRQHandler, /* DMA channel 7 transfer complete interrupt */ + DMA8_IRQHandler, /* DMA channel 8 transfer complete interrupt */ + DMA9_IRQHandler, /* DMA channel 9 transfer complete interrupt */ + DMA10_IRQHandler, /* DMA channel 10 transfer complete interrupt */ + DMA11_IRQHandler, /* DMA channel 11 transfer complete interrupt */ + DMA12_IRQHandler, /* DMA channel 12 transfer complete interrupt */ + DMA13_IRQHandler, /* DMA channel 13 transfer complete interrupt */ + DMA14_IRQHandler, /* DMA channel 14 transfer complete interrupt */ + DMA15_IRQHandler, /* DMA channel 15 transfer complete interrupt */ + DMA_Error_IRQHandler, /* DMA error interrupt */ + MCMNormal_IRQHandler, /* MCM normal interrupt */ + FlashCmd_IRQHandler, /* Flash memory command complete interrupt */ + FlashReadErr_IRQHandler, /* Flash read collision interrupt */ + LVD_LVW_IRQHandler, /* Low Voltage Detect, Low Voltage Warning */ + LLW_IRQHandler, /* Low Leakage Wakeup */ + Watchdog_IRQHandler, /* WDOG or EVM interrupt (shared) */ + Reserved39_IRQHandler, /* Reserved interrupt 39 */ + I2C0_IRQHandler, /* I2C0 interrupt */ + I2C1_IRQHandler, /* I2C1 interrupt */ + SPI0_IRQHandler, /* SPI0 interrupt */ + SPI1_IRQHandler, /* SPI1 interrupt */ + SPI2_IRQHandler, /* SPI2 interrupt 44 */ + CAN0Msg_IRQHandler, /* CAN0 message buffer (0-15) interrupt */ + CAN0BusOff_IRQHandler, /* CAN0 Bus Off interrupt */ + CAN0Error_IRQHandler, /* CAN0 Error interrupt */ + CAN0Xmit_IRQHandler, /* CAN0 Transmit warning interrupt */ + CAN0Rcv_IRQHandler, /* CAN0 Recieve warning interrupt */ + CAN0Wake_IRQHandler, /* CAN0 Wake Up interrupt */ + I2S0_Tx_IRQHandler, /* I2S0 transmit interrupt */ + I2S0_Rx_IRQHandler, /* I2S0 receive interrupt */ + CAN1Msg_IRQHandler, /* Reserved interrupt 53 */ + CAN1BusOff_IRQHandler, /* Reserved interrupt 54 */ + CAN1Error_IRQHandler, /* Reserved interrupt 55 */ + CAN1Xmit_IRQHandler, /* Reserved interrupt 56 */ + CAN1Rcv_IRQHandler, /* Reserved interrupt 57 */ + CAN1Wake_IRQHandler, /* Reserved interrupt 58 */ + Reserved59_IRQHandler, /* Reserved interrupt 59 */ + UART0_LON_IRQHandler, /* UART0 LON interrupt */ + UART0_RX_TX_IRQHandler, /* UART0 receive/transmit interrupt */ + UART0Error_IRQHandler, /* UART0 error interrupt */ + UART1_RX_TX_IRQHandler, /* UART1 receive/transmit interrupt */ + UART1Error_IRQHandler, /* UART1 error interrupt */ + UART2_RX_TX_IRQHandler, /* UART2 receive/transmit interrupt */ + UART2Error_IRQHandler, /* UART2 error interrupt */ + UART3_RX_TX_IRQHandler, /* UART3 receive/transmit interrupt */ + UART3Error_IRQHandler, /* UART3 error interrupt */ + UART4_RX_TX_IRQHandler, /* UART4 receive/transmit */ + UART4Error_IRQHandler, /* UART4 error interrupt */ + Reserved71_IRQHandler, /* Reserved interrupt 71 */ + Reserved72_IRQHandler, /* Reserved interrupt 72 */ + ADC0_IRQHandler, /* ADC0 interrupt */ + ADC1_IRQHandler, /* ADC1 interrupt */ + CMP0_IRQHandler, /* CMP0 interrupt */ + CMP1_IRQHandler, /* CMP1 interrupt */ + CMP2_IRQHandler, /* CMP2 interrupt */ + FTM0_IRQHandler, /* FTM0 fault, all sources interrupt */ + FTM1_IRQHandler, /* FTM1 fault, all sources interrupt */ + FTM2_IRQHandler, /* FTM2 fault, all sources interrupt */ + CMT_IRQHandler, /* CMT interrupt */ + RTC_IRQHandler, /* RTC alarm interrupt */ + RTCSeconds_IRQHandler, /* RTC seconds interrupt */ + PIT0_IRQHandler, /* PIT timer channel 0 interrupt */ + PIT1_IRQHandler, /* PIT timer channel 1 interrupt */ + PIT2_IRQHandler, /* PIT timer channel 2 interrupt */ + PIT3_IRQHandler, /* PIT timer channel 3 interrupt */ + PDB0_IRQHandler, /* PDB0 interrupt */ + USB_ISR, /* USB OTG interrupt */ + USBCharge_IRQHandler, /* USB charger detect interrupt */ + Reserved91_IRQHandler, /* Reserved interrupt 91 */ + Reserved92_IRQHandler, /* Reserved interrupt 92 */ + Reserved93_IRQHandler, /* Reserved interrupt 93 */ + Reserved94_IRQHandler, /* Reserved interrupt 94 */ + Reserved95_IRQHandler, /* Reserved interrupt 95 */ + SDHC_IRQHandler, /* SDHC interrupt */ + DAC0_IRQHandler, /* DAC0 interrupt */ + Reserved98_IRQHandler, /* Reserved interrupt 98 */ + TSI_IRQHandler, /* TSI all sources interrupt */ + MCG_IRQHandler, /* MCG interrupt */ + LPTimer_IRQHandler, /* Low-power Timer interrupt */ + Reserved102_IRQHandler, /* Reserved interrupt 102 */ + PORTA_IRQHandler, /* Port A pin detect interrupt */ + PORTB_IRQHandler, /* Port B pin detect interrupt */ + PORTC_IRQHandler, /* Port C pin detect interrupt */ + PORTD_IRQHandler, /* Port D pin detect interrupt */ + PORTE_IRQHandler, /* Port E pin detect interrupt */ + Reserved108_IRQHandler, /* Reserved interrupt 108 */ + Reserved109_IRQHandler, /* Reserved interrupt 109 */ + SWI_IRQHandler /* Software interrupt */ +}; + +/** + **=========================================================================== + ** Reset handler + **=========================================================================== + */ +void __init_hardware(void) +{ + SCB_VTOR = (uint32)&InterruptVector[0]; /* Set the interrupt vector table position */ + + #if defined(MKL25Z128) + // Disable the Watchdog because it may reset the core before entering main(). + SIM_COPC = KINETIS_WDOG_DISABLED_CTRL; + + #elif defined(MKE02Z64) + // Disable the Watchdog because it may reset the core before entering main(). + WDOG_CNT = 0x20C5; + WDOG_CNT = 0x28D9; + WDOG_TOVAL = 0x28D9; + WDOG_CS2 = WDOG_CS2_CLK(0); + WDOG_CS1 = WDOG_CS1_UPDATE_MASK; //watchdog setting can be changed later + + #elif defined(MK20DN512) || defined(MK20DX256) + // Disable the Watchdog because it may reset the core before entering main(). + WDOG_UNLOCK = 0xC520; // Write 0xC520 to the unlock register + WDOG_UNLOCK = 0xD928; // Followed by 0xD928 to complete the unlock + WDOG_STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; // Clear the WDOGEN bit to disable the watchdog + #else + #error "MCU sub-model not supported!" + #endif +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h new file mode 100644 index 0000000..e224cc6 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h @@ -0,0 +1,41 @@ +/* + FILE : kinetis_sysinit.h + PURPOSE : system initialization header for Kinetis ARM architecture + LANGUAGE: C + Copyright © 2012 Freescale semiConductor Inc. All Rights Reserved. +*/ +#ifndef KINETIS_SYSINIT_H +#define KINETIS_SYSINIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tmc/helpers/API_Header.h" + +/* Word to be written in SIM_COP in order to disable the Watchdog */ +#define KINETIS_WDOG_DISABLED_CTRL 0x0 + +/* + Initializes the Kinetis hardware: e.g. disables the Watchdog +*/ +void __init_hardware(void); + +/* +** =================================================================== +** Method : Default_Handler +** +** Description : +** The default interrupt handler. +** =================================================================== +*/ +void Default_Handler(void); + +void SetBASEPRI(uint32 Level) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef KINETIS_SYSINIT_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c new file mode 100644 index 0000000..9561129 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c @@ -0,0 +1,134 @@ +#include "hal/derivative.h" + +/***********************************************************************/ +/* + * Initialize the NVIC to enable the specified IRQ. + * + * NOTE: The function only initializes the NVIC to enable a single IRQ. + * Interrupts will also need to be enabled in the ARM core. This can be + * done using the EnableInterrupts; macro. + * + * Parameters: + * irq irq number to be enabled (the irq number NOT the vector number) + */ + +void enable_irq (int irq) +{ + + int div; + + /* Make sure that the IRQ is an allowable number. Right now up to 91 is + * used. + */ + // if(irq > 91) + //printf("\nERR! Invalid IRQ value passed to enable irq function!\n"); + + /* Determine which of the NVICISERs corresponds to the irq */ + div = irq/32; + + switch (div) + { + case 0x0: + NVICICPR0 |= 1 << (irq%32); + NVICISER0 |= 1 << (irq%32); + break; + case 0x1: + NVICICPR1 |= 1 << (irq%32); + NVICISER1 |= 1 << (irq%32); + break; + case 0x2: + NVICICPR2 |= 1 << (irq%32); + NVICISER2 |= 1 << (irq%32); + break; + } +} +/***********************************************************************/ +/* + * Initialize the NVIC to disable the specified IRQ. + * + * NOTE: The function only initializes the NVIC to disable a single IRQ. + * If you want to disable all interrupts, then use the DisableInterrupts + * macro instead. + * + * Parameters: + * irq irq number to be disabled (the irq number NOT the vector number) + */ + +void disable_irq (int irq) +{ + + /* Make sure that the IRQ is an allowable number. Right now up to 32 is + * used. + * + * NOTE: If you are using the interrupt definitions from the header + * file, you MUST SUBTRACT 16!!! + */ + if(irq > 128) + { + /* Set the ICER register accordingly */ + NVICICER3 = 1 << (irq%32); + } + else if(irq > 64) + { + /* Set the ICER register accordingly */ + NVICICER2 = 1 << (irq%32); + } + else if(irq > 32) + { + /* Set the ICER register accordingly */ + NVICICER1 = 1 << (irq%32); + } + else + { + /* Set the ICER register accordingly */ + NVICICER0 = 1 << (irq%32); + } +} +/***********************************************************************/ +/* + * Initialize the NVIC to set specified IRQ priority. + * + * NOTE: The function only initializes the NVIC to set a single IRQ priority. + * Interrupts will also need to be enabled in the ARM core. This can be + * done using the EnableInterrupts; macro. + * + * Parameters: + * irq irq number to be enabled (the irq number NOT the vector number) + * prio irq priority. 0-3 levels. 0 max priority + */ + +void set_irq_priority (int irq, int prio) +{ + /*irq priority pointer*/ + uint32 *prio_reg; + uint8 err = 0; + uint8 div = 0; + uint8 off = 0; + + /* Make sure that the IRQ is an allowable number. Right now up to 32 is + * used. + * + * NOTE: If you are using the interrupt definitions from the header + * file, you MUST SUBTRACT 16!!! + */ + if(irq > 32) + { + err = 1; + } + + if(prio > 3) + { + err = 1; + } + + if(err != 1) + { + /* Determine which of the NVICIPx corresponds to the irq */ + div = irq / 4; + off = irq % 4; + prio_reg = (uint32 *)((uint32)&NVIC_IP(div)); + /* Assign priority to IRQ */ + *prio_reg |= ( (prio&0x3) << (8 - ARM_INTERRUPT_LEVEL_BITS) ) << (off * 8); + } +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h new file mode 100644 index 0000000..67ecca5 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h @@ -0,0 +1,26 @@ +/* + * nvic.h + * + * Created on: Nov 6, 2012 + * Author: B34443 + */ + +#ifndef NVIC_H_ +#define NVIC_H_ + + /* ARM Cortex M0 implementation for interrupt priority shift */ + #define ARM_INTERRUPT_LEVEL_BITS 2 + +#ifndef EnableInterrupts + #define EnableInterrupts asm(" CPSIE i") +#endif + +#ifndef DisableInterrupts + #define DisableInterrupts asm(" CPSID i") +#endif + + void enable_irq(int); + void disable_irq(int); + void set_irq_priority(int, int); + +#endif /* NVIC_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S new file mode 100644 index 0000000..5cc3b34 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S @@ -0,0 +1,78 @@ +/******************************************************************************** + * \file startup.s + * \brief Startup file for Kinetis L (KL25Z). + * This module performs: + * - Set the initial SP + * - Set the initial PC == __thumb_startup, + * - Branches to main in the C library (which eventually + * calls main()). + ******************************************************************************/ + .syntax unified + .cpu cortex-m4 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. defined in linker script */ +.word ___ROM_AT +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word __START_BSS +/* end address for the .bss section. defined in linker script */ +.word __END_BSS + +/** + * \brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * \param None + * \retval : None +*/ + .section .text.__thumb_startup + .weak __thumb_startup + .type __thumb_startup, %function +__thumb_startup: +/* Call the C hardware init function (which also has to switch off the watchdog) */ + bl __init_hardware + +/* Copy the data segment initializers from flash to SRAM: */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =___ROM_AT + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =__START_BSS + b LoopFillZerobss + +/* Zero fill the bss segment: */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = __END_BSS + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point: */ + bl main + blx r0 /*Call the startup code of the application (address returned by the main() function of the boot loader)*/ + bx lr +.size __thumb_startup, .-__thumb_startup + +/****END OF FILE****/ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h new file mode 100644 index 0000000..29fdd9d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h @@ -0,0 +1,9 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef Landungsbruecke + #define Landungsbruecke +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c new file mode 100644 index 0000000..f6fb5f2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c @@ -0,0 +1,236 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/ADCs.h" + +/* analog channel selection values (ADCx_SC1n Register, DIFF & ADCH fields) */ + +// ADCH // DIFF = 0 | DIFF = 1 +#define DAD0 0x00 // DADP0 | DAD0 +#define DAD1 0x01 // DADP1 | DAD1 +#define DAD2 0x02 // DADP2 | DAD2 +#define DAD3 0x03 // DADP3 | DAD3 +#define AD04 0x04 // AD4 | Reserved +#define AD05 0x05 // AD5 | Reserved +#define AD06 0x06 // AD6 | Reserved +#define AD07 0x07 // AD7 | Reserved +#define AD08 0x08 // AD8 | Reserved +#define AD09 0x09 // AD9 | Reserved +#define AD10 0x0A // AD10 | Reserved +#define AD11 0x0B // AD11 | Reserved +#define AD12 0x0C // AD12 | Reserved +#define AD13 0x0D // AD13 | Reserved +#define AD14 0x0E // AD14 | Reserved +#define AD15 0x0F // AD15 | Reserved +#define AD16 0x10 // AD16 | Reserved +#define AD17 0x11 // AD17 | Reserved +#define AD18 0x12 // AD18 | Reserved +#define AD19 0x13 // AD19 | Reserved +#define AD20 0x14 // AD20 | Reserved +#define AD21 0x15 // AD21 | Reserved +#define AD22 0x16 // AD22 | Reserved +#define AD23 0x17 // AD23 | Reserved +#define AD24 0x18 // Reserved | Reserved +#define AD25 0x19 // Reserved | Reserved +#define AD26 0x1A // Temp Sensor (single ended) | Temp Sensor (differential) +#define AD27 0x1B // Bandgap (single ended) | Bandgap (differential) +#define AD28 0x1C // Reserved | Reserved +#define AD29 0x1D // VRefSH | -VRefSH (differential) +#define AD30 0x1E // VRefSL | -VRefSL (differential) +#define AD31 0x1F // Module disabled | Module diabled + +static void init(void); +static void deInit(void); + +/* ADCs are scanned using two DMA channels. Upon ADC read complete, the first DMA channel (Channel 1 for ADC 0, Channel 3 for ADC 1) + * will write the result of the ADC measurement to the result array. Upon DMA completion the first channel triggers the + * second DMA channel (Channel 0 for ADC 0, Channel 2 for ADC 1) to write a new MUX value into the ADC's configuration register. + * This repeats, creating an infinite loop reading out 3 Samples per ADC. + * + * This loop gets initialised by an initial DMA request for the second Channel to write the first MUX value. + */ + +/* Result buffer indices: + * Input Signal, ADC Channel, Pin + * ADC0[0]: ADC0_DP1, DAD1, 14 + * ADC0[1]: ADC0_SE12, AD12, 55 + * ADC0[2]: ADC0_SE13, AD13, 56 + * ADC1[0]: ADC1_DP0, DAD0, 20 + * ADC1[1]: ADC1_DP1, DAD1, 16 + * ADC1[2]: ADC1_DP3, DAD3, 18 + */ + +// ADC Result buffers +volatile uint16_t adc0_result[3] = { 0 }; +volatile uint16_t adc1_result[3] = { 0 }; +// ADC Multiplexer selection +const uint8_t adc0_mux[3] = { DAD1, AD12, AD13 }; +const uint8_t adc1_mux[3] = { DAD0, DAD1, DAD3 }; + +ADCTypeDef ADCs = +{ + .AIN0 = &adc1_result[1], + .AIN1 = &adc1_result[2], + .AIN2 = &adc1_result[0], + .DIO4 = &adc0_result[1], + .DIO5 = &adc0_result[2], + .VM = &adc0_result[0], + .init = init, + .deInit = deInit +}; + +static void init(void) +{ + // === ADC initialization === + // enable clock for ADC0 & ADC1 + SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; + SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK; + + HAL.IOs->pins->DIO4.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO5.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->DIO4); + HAL.IOs->config->set(&HAL.IOs->pins->DIO5); + + // CFG1: set ADC clocks + ADC0_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + ADC1_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + + // CFG2: configuration for high speed conversions and selects the long sample time duration + ADC0_CFG2 = ADC_CFG2_ADLSTS(0); // use default longest sample time + ADC1_CFG2 = ADC_CFG2_ADLSTS(0); // use default longest sample time + + // SC2: conversion + ADC0_SC2 = ADC_SC2_DMAEN_MASK; // enable DMA + ADC1_SC2 = ADC_SC2_DMAEN_MASK; // enable DMA; + + // average over 4 samples, single measurement (trigger from having DMA write the MUX value to SC1A) + ADC0_SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0); + ADC1_SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0); + + ADC0_SC3 |= ADC_SC3_CAL_MASK; + while(ADC0_SC3 & ADC_SC3_CAL_MASK); + + uint16_t cal = 0; + cal += ADC0_CLP0; + cal += ADC0_CLP1; + cal += ADC0_CLP2; + cal += ADC0_CLP3; + cal += ADC0_CLP4; + cal += ADC0_CLPS; + cal >>= 1; + cal |= 1<<15; + + ADC0_PG = cal; + + ADC1_SC3 |= ADC_SC3_CAL_MASK; + while(ADC1_SC3 & ADC_SC3_CAL_MASK); + + cal = 0; + cal += ADC1_CLP0; + cal += ADC1_CLP1; + cal += ADC1_CLP2; + cal += ADC1_CLP3; + cal += ADC1_CLP4; + cal += ADC1_CLPS; + cal >>= 1; + cal |= 1<<15; + + ADC1_PG = cal; + + // === DMA initialization === + + // enable clock for DMA + SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; + + // enable clock for DMA mux + SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; + + // === setup DMA channels for ADC0 === + + // DMA channel 0, use for write ADC mux channel, from SRAM to ADC + DMAMUX_CHCFG0 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x36); // DMA source: DMA Mux channel 1 (Source Number 54) + DMA_TCD0_SADDR = (uint32_t) &adc0_mux[0]; // Source address: ADC Mux Settings Array + DMA_TCD0_SOFF = 0x01; // Source address increment (Added after each major loop step) + DMA_TCD0_SLAST = (uint32_t) -3; // Source address decrement (Added on major loop completion) + DMA_TCD0_DADDR = (uint32_t) &ADC0_SC1A; // Destination address: ADC0 control register (containing ADC Mux bitfield) + DMA_TCD0_DOFF = 0x00; // Destination address increment (Added after each major loop step) + DMA_TCD0_DLASTSGA = 0x00; // Destination address decrement (Added on major loop completion) + DMA_TCD0_NBYTES_MLNO = 0x01; // Number of bytes transferred per request (1 Byte ADC Setting) + DMA_TCD0_BITER_ELINKNO = 0x03; // Disable channel link, beginning major iteration count: 3 + DMA_TCD0_CITER_ELINKNO = 0x03; // Disable channel link, current major iteration count: 3 + DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); // Source and destination size: 8 bit + DMA_TCD0_CSR = DMA_CSR_START_MASK; // Request channel start, to initiate our readout loop + + // DMA channel 1, use for read ADC result data, from ADC to SRAM + DMAMUX_CHCFG1 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x28); // DMA source: ADC0 (Source Number 40) + DMA_TCD1_SADDR = (uint32_t) &ADC0_RA; // Source address: ADC0 result register + DMA_TCD1_SOFF = 0x00; // Source address increment (Added after each major loop step) + DMA_TCD1_SLAST = 0x00; // Source address decrement (Added on major loop completion) + DMA_TCD1_DADDR = (uint32_t) &adc0_result[0]; // Destination address: ADC0 result buffer + DMA_TCD1_DOFF = 0x02; // Destination address increment (Added after each major loop step) + DMA_TCD1_DLASTSGA = (uint32_t) -6; // Destination address decrement (Added on major loop completion) + DMA_TCD1_NBYTES_MLNO = 0x02; // Number of bytes transferred per request (2 Byte ADC Result) + DMA_TCD1_BITER_ELINKYES = (DMA_BITER_ELINKYES_ELINK_MASK|DMA_BITER_ELINKYES_LINKCH(0)|0x03); // Enable channel link (to channel 0) on major loop step, beginning major iteration count: 3 + DMA_TCD1_CITER_ELINKYES = (DMA_CITER_ELINKYES_ELINK_MASK|DMA_BITER_ELINKYES_LINKCH(0)|0x03); // Enable channel link (to channel 0) on major loop step, current major iteration count: 3 + DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1); // Source and destination size: 16 bit + DMA_TCD1_CSR = (DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK); // Major loop completion starts request for Channel 0 + + // Start the DMA Channel 1 + DMA_SERQ = 1; + + // === setup DMA channels for ADC1 === + + // DMA channel 2, use for write ADC mux channel, from SRAM to ADC + DMAMUX_CHCFG2 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x38); // DMA source: DMA Mux channel 2 (Source Number 56) + DMA_TCD2_SADDR = (uint32_t) &adc1_mux[0]; // Source address: ADC Mux Settings + DMA_TCD2_SOFF = 0x01; // Source address increment (Added after each major loop step) + DMA_TCD2_SLAST = (uint32_t) -3; // Source address decrement (Added on major loop completion) + DMA_TCD2_DADDR = (uint32_t) &ADC1_SC1A; // Destination address: ADC1 control register (containing ADC Mux bitfield) + DMA_TCD2_DOFF = 0x00; // Destination address increment (Added for each major loop step) + DMA_TCD2_DLASTSGA = 0x00; // Destination address decrement (Added on major loop completion) + DMA_TCD2_NBYTES_MLNO = 0x01; // Number of bytes transferred per request (1 Byte ADC Setting) + DMA_TCD2_BITER_ELINKNO = 0x03; // Disable channel link, beginning major iteration count: 3 + DMA_TCD2_CITER_ELINKNO = 0x03; // Disable channel link, current major iteration count: 3 + DMA_TCD2_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); // Source and destination size: 8 bit + DMA_TCD2_CSR = DMA_CSR_START_MASK; // Request channel start, to initiate our readout loop + + // DMA channel 3, use for read ADC result data, from ADC to SRAM + DMAMUX_CHCFG3 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x29); // DMA source: ADC1 (Source Number 41) + DMA_TCD3_SADDR = (uint32_t) &ADC1_RA; // Source address: ADC1 result register + DMA_TCD3_SOFF = 0x00; // Source address increment (Added after each major loop step) + DMA_TCD3_SLAST = 0x00; // Source address decrement (Added on major loop completion) + DMA_TCD3_DADDR = (uint32_t) &adc1_result[0]; // Destination address: ADC0 result buffer + DMA_TCD3_DOFF = 0x02; // Destination address increment (Added after each major loop step) + DMA_TCD3_DLASTSGA = (uint32_t) -6; // Destination address decrement (Added on major loop completion) + DMA_TCD3_NBYTES_MLNO = 0x02; // Number of bytes transferred per request (2 Byte ADC Result) + DMA_TCD3_BITER_ELINKYES = DMA_BITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(2) | 0x03; // Enable channel link (to channel 2) on major loop step, beginning major iteration count: 3 + DMA_TCD3_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(2) | 0x03; // Enable channel link (to channel 2) on major loop step, current major iteration count: 3 + DMA_TCD3_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1); // Source and destination size: 16 bit + DMA_TCD3_CSR = DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK; // Major loop completion starts request for Channel 2 + + // Start the DMA Channel 3 + DMA_SERQ = 3; + + EnableInterrupts; +} + +static void deInit() +{ + // disable clock for DMA + SIM_SCGC7 &= ~(SIM_SCGC7_DMA_MASK); + + // disable clock for DMA mux + SIM_SCGC6 &= ~(SIM_SCGC6_DMAMUX_MASK); + + // disable clock for ADC0/ADC1 + SIM_SCGC6 &= ~(SIM_SCGC6_ADC0_MASK); + SIM_SCGC3 &= ~(SIM_SCGC3_ADC1_MASK); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c new file mode 100644 index 0000000..fdbd2d4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" + +static void init(void); +static void reset(uint8_t ResetPeripherals); +static void NVIC_init(void); +static void NVIC_DeInit(void); +static void get_hwid(void); + +uint8_t hwid; + +static const IOsFunctionsTypeDef IOFunctions = +{ + .config = &IOs, + .pins = &IOMap, +}; + +const HALTypeDef HAL = +{ + .init = init, + .reset = reset, + .NVIC_DeInit = NVIC_DeInit, + .SPI = &SPI, + .USB = &USB, + .LEDs = &LEDs, + .ADCs = &ADCs, + .IOs = &IOFunctions, + .RS232 = &RS232, + .WLAN = &WLAN, + .Timer = &Timer, + .UART = &UART +}; + +static void init(void) +{ + Cpu.initClocks(); + Cpu.initLowLevel(); + NVIC_init(); + EnableInterrupts;; + + systick_init(); + wait(100); + + IOs.init(); + IOMap.init(); + LEDs.init(); + ADCs.init(); + SPI.init(); + WLAN.init(); + RS232.init(); + USB.init(); + + // Determine HW version + get_hwid(); +} + +static void __attribute((noreturn)) reset(uint8_t ResetPeripherals) +{ + DisableInterrupts; + + if(ResetPeripherals) + SCB_AIRCR = SCB_AIRCR_VECTKEY(0x5FA) | SCB_AIRCR_SYSRESETREQ_MASK; + else + SCB_AIRCR = SCB_AIRCR_VECTKEY(0x5FA) | SCB_AIRCR_VECTRESET_MASK; + + // SYSRESETREQ does not happen instantly since peripheral reset timing is not specified. + // Trap execution here so nothing else happens until the reset completes. + while(1); +} + +static void NVIC_init(void) +{ + uint8_t i; + + // Disable all interrupts + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICER); i++) + { + // Interrupt clear-enable Registers + NVIC_ICER(i) = 0xFFFFFFFF; + } + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICPR); i++) + { + // Interrupt clear-pending Registers + NVIC_ICPR(i) = 0xFFFFFFFF; + } + + // Set all interrupt priorities to the same level + // The priority is stored in the uint8_t IP register, but not all of the + // bits are used. For the Processor of the Landungsbruecke the 4 upper bits + // are implemented. Here we set the interrupt priority to the middle of the + // available values to allow other code to increase or decrease specific + // interrupt priorities. + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->IP); i++) + { + // Interrupt priority registers + NVIC_IP(i) = 0x80; + } + + // Special interrupt priorities + // PortB interrupt - used for ID detection by measuring a pulse duration + // Needs to be the fastest interrupt to ensure correct measurement. + NVIC_IP(INT_PORTB-16) = 0x00; + // FTM1 interrupt - used by the StepDir generator. If this gets preempted + // the StepDir movement quality gets degraded. + NVIC_IP(INT_FTM1-16) = 0x10; + // USB interrupt - needed for communication + NVIC_IP(INT_USB0-16) = 0x20; +} + +static void NVIC_DeInit(void) +{ + uint8_t i; + + asm volatile("CPSID I\n"); // disable interrupts + + // Clear all NVIC interrupts + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICER); i++) + { + // Interrupt clear-enable Registers + NVIC_ICER(i) = 0xFFFFFFFF; + } + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICPR); i++) + { + // Interrupt clear-pending Registers + NVIC_ICPR(i) = 0xFFFFFFFF; + } + + // Reset interrupt priorities + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->IP); i++) + { + // Interrupt priority registers + NVIC_IP(i) = 0x00; + } + + SYST_CSR = 0; // disable systick +} + +typedef enum { + STATE_Z = 0, + STATE_LOW = 1, + STATE_HIGH = 2 +} Tristate; + +// Helper for get_hwid() +static Tristate getTristate(IOPinTypeDef *pin) +{ + // Input with pulldown + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + pin->configuration.GPIO_OType = GPIO_OType_OD; + pin->configuration.GPIO_PuPd = GPIO_PuPd_DOWN; + HAL.IOs->config->set(pin); + + if (HAL.IOs->config->isHigh(pin)) { + // High despite pulldown -> High state + return STATE_HIGH; + } + + // Input with pullup + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + pin->configuration.GPIO_OType = GPIO_OType_OD; + pin->configuration.GPIO_PuPd = GPIO_PuPd_UP; + HAL.IOs->config->set(pin); + + if (HAL.IOs->config->isHigh(pin)) { + // High from pullup -> Z state + return STATE_Z; + } else { + // Low despite pullup -> Low state + return STATE_LOW; + } +} + +// Determines HW version of Landungsbruecke to distinct between 1.X and 2.0+ +static void get_hwid(void) +{ + static uint8_t hwid_map[27] = { + // Z Z Z L L L H H H <- ID_HW_1 + // Z L H Z L H Z L H <- ID_HW_0 + 1, 0, 0, 0, 0, 0, 0, 0, 0, // Z + 0, 0, 0, 0, 0, 0, 0, 2, 0, // L <- ID_HW_2 + 0, 0, 0, 0, 0, 0, 0, 0, 0 // H + }; + + uint8_t tmp; + tmp = getTristate(&HAL.IOs->pins->ID_HW_0) + + getTristate(&HAL.IOs->pins->ID_HW_1) * 3 + + getTristate(&HAL.IOs->pins->ID_HW_2) * (3*3); + + hwid = hwid_map[tmp]; +} + +void _exit(int32_t i) // function has the attribute noreturn per default +{ + UNUSED(i); + while(1) {}; +} + +void _kill(void) +{ +} + +void _getpid(void) +{ +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c new file mode 100644 index 0000000..88546d8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c @@ -0,0 +1,1228 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/IOMap.h" +#include "hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h" + +static void init(); + +static IOPinTypeDef *_pins[] = +{ + &IOMap.ID_CLK, + &IOMap.ID_CH0, + &IOMap.ID_CH1, + &IOMap.DIO0, + &IOMap.DIO1, + &IOMap.DIO2, + &IOMap.DIO3, + &IOMap.DIO4, + &IOMap.DIO5, + &IOMap.DIO6, + &IOMap.DIO7, + &IOMap.DIO8, + &IOMap.DIO9, + &IOMap.DIO10, + &IOMap.DIO11, + &IOMap.CLK16, + &IOMap.SPI2_CSN0, + &IOMap.SPI2_CSN1, + &IOMap.SPI2_CSN2, + &IOMap.SPI2_SCK, + &IOMap.SPI2_SDO, + &IOMap.SPI2_SDI, + &IOMap.SPI1_CSN, + &IOMap.SPI1_SCK, + &IOMap.SPI1_SDI, + &IOMap.SPI1_SDO, + &IOMap.DIO12, + &IOMap.DIO13, + &IOMap.DIO14, + &IOMap.DIO15, + &IOMap.DIO16, + &IOMap.DIO17, + &IOMap.DIO18, + &IOMap.DIO19, + &IOMap.WIRELESS_TX, + &IOMap.WIRELESS_RX, + &IOMap.WIRELESS_NRST, + &IOMap.RS232_TX, + &IOMap.RS232_RX, + &IOMap.USB_V_BUS, + &IOMap.USB_V_DM, + &IOMap.USB_V_DP, + &IOMap.LED_STAT, + &IOMap.LED_ERROR, + &IOMap.EXTIO_2, + &IOMap.EXTIO_3, + &IOMap.EXTIO_4, + &IOMap.EXTIO_5, + &IOMap.EXTIO_6, + &IOMap.EXTIO_7, + &IOMap.EEPROM_SCK, + &IOMap.EEPROM_SI, + &IOMap.EEPROM_SO, + &IOMap.EEPROM_NCS, + &IOMap.MIXED0, + &IOMap.MIXED1, + &IOMap.MIXED2, + &IOMap.MIXED3, + &IOMap.MIXED4, + &IOMap.MIXED5, + &IOMap.MIXED6, + &IOMap.ID_HW_0, + &IOMap.ID_HW_1, + &IOMap.ID_HW_2, + &IOMap.DUMMY +}; + +IOPinMapTypeDef IOMap = +{ + .init = init, + .pins = &_pins[0], + .ID_CLK = // IOPinTypeDef ID_CLK + { + .setBitRegister = &(GPIOB_PSOR), // uint32_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // uint32_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // Peripheral Port Base Pointer + .GPIOBase = PTB_BASE_PTR, // Peripheral PTA base pointer, GPIO; + .bitWeight = GPIO_PDD_PIN_20, // uint32_t pinBitWeight Pin masks; + .bit = 20, // uint8_t bit; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_CH0 = // IOPinTypeDef ID_CH0 + { + .setBitRegister = &(GPIOB_PSOR), // uint32_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // uint32_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // Peripheral Port Base Pointer + .GPIOBase = PTB_BASE_PTR, // Peripheral PTA base pointer, GPIO; + .bitWeight = GPIO_PDD_PIN_18, // uint32_t pinBitWeight; + .bit = 18, // uint8_t bit; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_CH1 = // IOPinTypeDef ID_CH1 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_19, // uint32_t pinBitWeight; + .bit = 19, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO0 = // IOPinTypeDef DIO0 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_12, // uint32_t pinBitWeight; + .bit = 12, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO1 = // IOPinTypeDef DIO1 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_13, // uint32_t pinBitWeight; + .bit = 13, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO3 = // IOPinTypeDef DIO3 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO4 = // IOPinTypeDef DIO4 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO5 = // IOPinTypeDef DIO5 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .DIO6 = // IOPinTypeDef DIO6 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO7 = // IOPinTypeDef DIO7 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO8 = // IOPinTypeDef DIO8 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO9 = // IOPinTypeDef DIO9 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO10 = // IOPinTypeDef DIO10 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_7, // uint32_t pinBitWeight; + .bit = 7, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO11 = // IOPinTypeDef DIO11 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .CLK16 = // IOPinTypeDef CLK16 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AF5, // GPIOMode_TypeDef GPIO_Mode; ?? + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN0 = // IOPinTypeDef SPI2_CSN0 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN1 = // IOPinTypeDef SPI2_CSN1 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN2 = // IOPinTypeDef SPI2_CSN2 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SCK = // IOPinTypeDef SPI2_SCK + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_21, // uint32_t pinBitWeight; + .bit = 21, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SDO = // IOPinTypeDef SPI2_SDO + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_23, // uint32_t pinBitWeight; + .bit = 23, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SDI = // IOPinTypeDef SPI2_SDI + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_22, // uint32_t pinBitWeight; + .bit = 22, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_CSN = // IOPinTypeDef SPI1_CSN + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_10, // uint32_t pinBitWeight; + .bit = 10, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SCK = // IOPinTypeDef SPI1_SCK + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_11, // uint32_t pinBitWeight; + .bit = 11, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SDO = // IOPinTypeDef SPI1_SDO + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SDI = // IOPinTypeDef SPI1_SDI + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO12 = // IOPinTypeDef DIO12 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO13 = // IOPinTypeDef DIO13 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .DIO14 = // IOPinTypeDef DIO14 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_18, // uint32_t pinBitWeight; + .bit = 18, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO15 = // IOPinTypeDef DIO15 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO16 = // IOPinTypeDef DIO16 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO17 = // IOPinTypeDef DIO17 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO18 = // IOPinTypeDef DIO18 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO19 = // IOPinTypeDef DIO19 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_15, // uint32_t pinBitWeight; + .bit = 15, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .WIRELESS_TX = // IOPinTypeDef WIRELESS_TX + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_14, // uint32_t pinBitWeight; + .bit = 14, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .WIRELESS_RX = // IOPinTypeDef WIRELESS_RX + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_15, // uint32_t pinBitWeight; + .bit = 15, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .WIRELESS_NRST = // IOPinTypeDef WIRELESS_NRST + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .RS232_TX = // IOPinTypeDef RS232_TX + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_24, // uint32_t pinBitWeight; + .bit = 24, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .RS232_RX = // IOPinTypeDef RS232_RX + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_25, // uint32_t pinBitWeight; + .bit = 25, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .USB_V_BUS = // IOPinTypeDef USB_V_BU + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, // GPIO_TypeDef *port; + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_100MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .LED_STAT = // IOPinTypeDef LED_STAT + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .LED_ERROR = // IOPinTypeDef LED_ERROR + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_2 = // IOPinTypeDef EXTIO_2 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_3 = // IOPinTypeDef EXTIO_3 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + .EXTIO_4 = // IOPinTypeDef EXTIO_4 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + .EXTIO_5 = // IOPinTypeDef EXTIO_5 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_6 = // IOPinTypeDef EXTIO_6 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_7= // IOPinTypeDef EXTIO_7 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .EEPROM_SCK = // IOPinTypeDef EEPROM_SCK + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .EEPROM_SI = // IOPinTypeDef EEPROM_SI + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_7, // uint32_t pinBitWeight; + .bit = 7, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EEPROM_SO = // IOPinTypeDef EEPROM_SO + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EEPROM_NCS = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_8, // uint32_t pinBitWeight; + .bit = 8, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED0 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_11, // uint32_t pinBitWeight; + .bit = 11, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED1 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_12, // uint32_t pinBitWeight; + .bit = 12, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_13, // uint32_t pinBitWeight; + .bit = 13, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED3 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_14, // uint32_t pinBitWeight; + .bit = 14, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED4 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_10, // uint32_t pinBitWeight; + .bit = 10, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED5 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_9, // uint32_t pinBitWeight; + .bit = 9, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED6 = // IOPinTypeDef + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_0 = // IOPinTypeDef + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_26, // uint32_t pinBitWeight; + .bit = 26, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_1 = // IOPinTypeDef + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_9, // uint32_t pinBitWeight; + .bit = 9, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DUMMY = // Dummy Pin + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = DUMMY_BITWEIGHT, // invalid + .bit = -1, // invalid + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + } +}; + + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CLK); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO0); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO3); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO4); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO5); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO6); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO7); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO8); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO9); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO12); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO13); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO14); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO15); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO16); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO19); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_NRST); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_BUS); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_2); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_3); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_4); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_5); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->reset(&HAL.IOs->pins->CLK16); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED0); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED1); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED2); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED3); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED4); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED5); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED6); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_1); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_2); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c new file mode 100644 index 0000000..bc5153f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/IOs.h" + +static void init(); +static void setPinConfiguration(IOPinTypeDef *pin); +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef*to); +static void resetPinConfiguration(IOPinTypeDef *pin); +static void setPin2Output(IOPinTypeDef *pin); +static void setPin2Input(IOPinTypeDef *pin); +static void setPinHigh(IOPinTypeDef *pin); +static void setPinLow(IOPinTypeDef *pin); +static void setPinState(IOPinTypeDef *pin, IO_States state); +static IO_States getPinState(IOPinTypeDef *pin); +static uint8_t isPinHigh(IOPinTypeDef *pin); + +IOsTypeDef IOs = +{ + .init = init, + .set = setPinConfiguration, + .reset = resetPinConfiguration, + .copy = copyPinConfiguration, + .toOutput = setPin2Output, + .toInput = setPin2Input, + .setHigh = setPinHigh, + .setLow = setPinLow, + .setToState = setPinState, + .getState = getPinState, + .isHigh = isPinHigh +}; + +static void init() +{ + // Set the Clock divider for core/system clock + // 96 MHz / 2 = 48 MHz + SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV1(1); + + SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |SIM_SCGC5_PORTD_MASK); + + // Ausgabe des 16Mhz Taktes auf den CLK16 Pin + SIM_SOPT2 &= ~SIM_SOPT2_CLKOUTSEL_MASK; + SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(6); + PORTC_PCR3 = PORT_PCR_MUX(5); +} + +static void setPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + uint32_t config = 0; + switch(pin->configuration.GPIO_Mode) + { + case GPIO_Mode_IN: + GPIO_PDD_SetPortInputDirectionMask(pin->GPIOBase, pin->bitWeight); + config |= PORT_PCR_MUX(1); + break; + case GPIO_Mode_OUT: + GPIO_PDD_SetPortOutputDirectionMask(pin->GPIOBase, pin->bitWeight); + config |= PORT_PCR_MUX(1); + break; + case GPIO_Mode_AN: config |= PORT_PCR_MUX(0); break; + case GPIO_Mode_AF1: config |= PORT_PCR_MUX(1); break; + case GPIO_Mode_AF2: config |= PORT_PCR_MUX(2); break; + case GPIO_Mode_AF3: config |= PORT_PCR_MUX(3); break; + case GPIO_Mode_AF4: config |= PORT_PCR_MUX(4); break; + case GPIO_Mode_AF5: config |= PORT_PCR_MUX(5); break; + case GPIO_Mode_AF6: config |= PORT_PCR_MUX(6); break; + case GPIO_Mode_AF7: config |= PORT_PCR_MUX(7); break; + } + + switch(pin->configuration.GPIO_OType) + { + case GPIO_OType_PP: + break; + case GPIO_OType_OD: + config |= PORT_PCR_ODE_MASK; // enable open drain + break; + } + switch(pin->configuration.GPIO_Speed) // die Auswahl der Frequenz bewirkt keine Änderung + { + case GPIO_Speed_2MHz: break; + case GPIO_Speed_25MHz: break; + case GPIO_Speed_50MHz: break; + case GPIO_Speed_100MHz: break; + } + + switch(pin->configuration.GPIO_PuPd) + { + case GPIO_PuPd_NOPULL: + config &= ~PORT_PCR_PE_MASK; + break; + case GPIO_PuPd_UP: + config |= PORT_PCR_PE_MASK; + config |= PORT_PCR_PS_MASK; + break; + case GPIO_PuPd_DOWN: + config |= PORT_PCR_PE_MASK; + config &= ~(PORT_PCR_PS_MASK); + break; + } + + PORT_PCR_REG(pin->portBase, pin->bit) = config; +} + +static void setPin2Output(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + setPinConfiguration(pin); +} + +static void setPin2Input(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + setPinConfiguration(pin); +} + +static void setPinState(IOPinTypeDef *pin, IO_States state) +{ + if(IS_DUMMY_PIN(pin)) + return; + + switch(state) + { + case IOS_LOW: + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + pin->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + pin->configuration.GPIO_OType = GPIO_OType_PP; + setPinConfiguration(pin); + *pin->resetBitRegister = pin->bitWeight; + break; + case IOS_HIGH: + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + pin->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + pin->configuration.GPIO_OType = GPIO_OType_PP; + setPinConfiguration(pin); + *pin->setBitRegister = pin->bitWeight; + break; + case IOS_OPEN: + pin->configuration.GPIO_Mode = GPIO_Mode_AN; + setPinConfiguration(pin); + break; + case IOS_NOCHANGE: + break; + } + + pin->state = state; + + setPinConfiguration(pin); +} + +static IO_States getPinState(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return IOS_OPEN; + + if(pin->configuration.GPIO_Mode == GPIO_Mode_AN) + pin->state = IOS_OPEN; + else if(GPIO_PDIR_REG(pin->GPIOBase) & pin->bitWeight) + pin->state = IOS_HIGH; + else + pin->state = IOS_LOW; + + return pin->state; +} + +static void setPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->setBitRegister = pin->bitWeight; + pin->state = IOS_HIGH; +} + +static void setPinLow(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->resetBitRegister = pin->bitWeight; + pin->state = IOS_LOW; +} + +static uint8_t isPinHigh(IOPinTypeDef *pin) // Die Abfrage eines Pins funktioniert nur, wenn der Pin AF1 ist +{ + if(IS_DUMMY_PIN(pin)) + return -1; + + return (GPIO_PDIR_REG(pin->GPIOBase) & pin->bitWeight)? 1 : 0; +} + +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef *to) +{ + if(IS_DUMMY_PIN(to)) + return; + + to->configuration.GPIO_Mode = from->GPIO_Mode; + to->configuration.GPIO_OType = from->GPIO_OType; + to->configuration.GPIO_PuPd = from->GPIO_PuPd; + to->configuration.GPIO_Speed = from->GPIO_Speed; + setPinConfiguration(to); +} + +static void resetPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + copyPinConfiguration(&(pin->resetConfiguration), pin); + + // Extra Reset Konfiguration für CLK16 + if(pin == &IOMap.CLK16) + { + SIM_SOPT2 &= ~SIM_SOPT2_CLKOUTSEL_MASK; + SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(6); + PORTC_PCR3 = PORT_PCR_MUX(5); + } +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c new file mode 100644 index 0000000..acdb2fa --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c @@ -0,0 +1,80 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/LEDs.h" + +static void init(); +static void onStat(); +static void onError(); +static void offStat(); +static void offError(); +static void toggleStat(); +static void toggleError(); + +LEDsTypeDef LEDs = +{ + .init = init, + .stat = + { + .on = onStat, + .off = offStat, + .toggle = toggleStat, + }, + .error = + { + .on = onError, + .off = offError, + .toggle = toggleError, + }, +}; + +static void init() +{ + HAL.IOs->pins->LED_ERROR.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->LED_ERROR.configuration.GPIO_OType = GPIO_OType_PP; + HAL.IOs->pins->LED_STAT.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->LED_STAT.configuration.GPIO_OType = GPIO_OType_PP; + + HAL.IOs->config->set(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->set(&HAL.IOs->pins->LED_STAT); + + LED_OFF(); + LED_ERROR_OFF(); +} + +static void onStat() +{ + LED_ON(); +} + +static void onError() +{ + LED_ERROR_ON(); +} + +static void offStat() +{ + LED_OFF(); +} + +static void offError() +{ + LED_ERROR_OFF(); +} + +static void toggleStat() +{ + LED_TOGGLE(); +} + +static void toggleError() +{ + LED_ERROR_TOGGLE(); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c new file mode 100644 index 0000000..fb2abfb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c @@ -0,0 +1,188 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 5 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static volatile uint32_t available = 0; + +RXTXTypeDef RS232 = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd; + + SIM_SCGC1 |= (SIM_SCGC1_UART4_MASK); + + HAL.IOs->pins->RS232_RX.configuration.GPIO_Mode = GPIO_Mode_AF3; + HAL.IOs->pins->RS232_TX.configuration.GPIO_Mode = GPIO_Mode_AF3; + + HAL.IOs->config->set(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->set(&HAL.IOs->pins->RS232_TX); + /* Disable the transmitter and receiver */ + UART_C2_REG(UART4_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Configure the UART for 8-bit mode, no parity */ + /* We need all default settings, so entire register is cleared */ + UART_C1_REG(UART4_BASE_PTR) = 0; + + ubd = (CPU_BUS_CLK_HZ / 16) / (RS232.baudRate); + + UART_BDH_REG(UART4_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART4_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + + /* Enable receiver and transmitter */ + UART_C2_REG(UART4_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + + enable_irq(INT_UART4_RX_TX-16); +} + +static void deInit() +{ + SIM_SCGC1 &= ~(SIM_SCGC1_UART4_MASK); + + HAL.IOs->pins->RS232_RX.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->RS232_TX.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->set(&HAL.IOs->pins->RS232_TX); + + disable_irq(INT_UART4_RX_TX-16); + + clearBuffers(); +} + +void UART4_RX_TX_IRQHandler(void) +{ + uint32_t status = UART4_S1; + + if(status & UART_S1_RDRF_MASK) + { + buffers.rx.buffer[buffers.rx.wrote] = UART4_D; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + UART4_S1 &= ~(UART_S1_RDRF_MASK); + } + + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART4_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { // empty buffer -> turn off send interrupt + UART4_C2 &= ~UART_C2_TIE_MASK; + } + UART4_S1 &= ~(UART_S1_TDRE_MASK); + } +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + + // enable send interrupt + UART4_C2 |= UART_C2_TIE_MASK; +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + disable_irq(INT_UART4_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART4_RX_TX-16); +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c new file mode 100644 index 0000000..96026b3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c @@ -0,0 +1,27 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/RXTX.h" +#include "hal/WLAN.h" +#include "hal/UART.h" + +UART0_Interrupt uart0_interrupt = UART0_INTERRUPT_UART; + +void UART0_RX_TX_IRQHandler(void) +{ + switch(uart0_interrupt) { + case UART0_INTERRUPT_WLAN: + UART0_RX_TX_IRQHandler_WLAN(); + break; + case UART0_INTERRUPT_UART: + default: + UART0_RX_TX_IRQHandler_UART(); + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c new file mode 100644 index 0000000..8db3fca --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c @@ -0,0 +1,426 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" + +void init(); +void reset_ch1(); +void reset_ch2(); + +static void setTMCSPIParameters(SPI_MemMapPtr basePtr); + +static uint8_t readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); +static uint8_t spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer); +static uint8_t spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer); +static void spi_ch1_readWriteArray(uint8_t *data, size_t length); +static void spi_ch2_readWriteArray(uint8_t *data, size_t length); + +SPIChannelTypeDef *SPIChannel_1_default; +SPIChannelTypeDef *SPIChannel_2_default; + +static IOPinTypeDef IODummy = { .bitWeight = DUMMY_BITWEIGHT }; + +SPITypeDef SPI= +{ + .ch1 = + { + .periphery = SPI1_BASE_PTR, + .CSN = &IODummy, + .readWrite = spi_ch1_readWrite, + .readWriteArray = spi_ch1_readWriteArray, + .reset = reset_ch1 + }, + .ch2 = + { + .periphery = SPI2_BASE_PTR, + .CSN = &IODummy, + .readWrite = spi_ch2_readWrite, + .readWriteArray = spi_ch2_readWriteArray, + .reset = reset_ch2 + }, + .init = init +}; + + +void init() +{ + // SPI0 -> EEPROM + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; // enable clock for PORT C + SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK; // enable clock for SPI0 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI0 pins: + // SCK: Port C, Pin 5 + // SDI: Port C, Pin 6 + // SDO: Port C, Pin 7 + // CSN: Port C, Pin 8 + HAL.IOs->pins->EEPROM_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_SI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_SO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_NCS.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->setHigh(&HAL.IOs->pins->EEPROM_NCS); + + setTMCSPIParameters(SPI0_BASE_PTR); + + // SPI1 -> ch1 + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; // enable clock for PORT B + SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK; // enable clock for SPI1 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI1 pins: + // SCK: Port B, Pin 11 + // SDI: Port B, Pin 16 + // SDO: Port B, Pin 17 + // CSN: Port B, Pin 10 + HAL.IOs->pins->SPI1_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_SDI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_SDO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_CSN.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI1_CSN); + + setTMCSPIParameters(SPI1_BASE_PTR); + + // SPI2 -> ch2 + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; // enable clocks + SIM_SCGC3 |= SIM_SCGC3_SPI2_MASK; // enable clock for SPI2 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI2 pins: + // SCK: Port B, Pin 21 + // SDI: Port B, Pin 22 + // SDO: Port B, Pin 23 + // CSN0: Port C, Pin 0 + // CSN1: Port A, Pin 5 + // CSN2: Port C, Pin 4 + HAL.IOs->pins->SPI2_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_SDI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_SDO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_CSN0.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->SPI2_CSN1.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->SPI2_CSN2.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN2); + + setTMCSPIParameters(SPI2_BASE_PTR); + + // configure default SPI channel_1 + SPIChannel_1_default = &HAL.SPI->ch1; + SPIChannel_1_default->CSN = &HAL.IOs->pins->SPI1_CSN; + // configure default SPI channel_2 + SPIChannel_2_default = &HAL.SPI->ch2; + SPIChannel_2_default->CSN = &HAL.IOs->pins->SPI2_CSN0; +} + +void setTMCSPIParameters(SPI_MemMapPtr basePtr) +{ + // set SPI2 to STOP mode + SPI_MCR_REG(basePtr) = SPI_MCR_HALT_MASK; + + // set SPI2 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(basePtr) |= SPI_MCR_MSTR_MASK + | SPI_MCR_CLR_RXF_MASK + | SPI_MCR_CLR_TXF_MASK; + + // baudrate => 48MHz/18 = 2.66MHz + SPI_CTAR_REG(basePtr, 0) = SPI_CTAR_FMSZ(7) // duty cycle 50/50; 8bit frame(7+1); inactive SCK state low; capture->leading; MSB first; + | SPI_CTAR_DT(2) // CS a SCK = 21ns[2ns]; after SCK = 21ns [2ns]; After transfer*8= 168ns [50ns] + | SPI_CTAR_BR(2) // prescaler value: 6 (BR=2, PBR=1 => 2,66MHz) (BR=1, PBR=1 => 4MHz) (BR=0, PBR=1 => ?MHz) + | SPI_CTAR_PBR(1) // prescaler value: 3 + | SPI_CTAR_CPHA_MASK // clock phase + | SPI_CTAR_PCSSCK(1) // shift NCS->SCK + | SPI_CTAR_PASC(1) // shift NCS->SCK + | SPI_CTAR_CPOL_MASK; // clk high in idle + + // set SPI2 to RUNNING mode + SPI_SR_REG(basePtr) |= SPI_SR_EOQF_MASK; + SPI_MCR_REG(basePtr) &= ~SPI_MCR_HALT_MASK; + SPI_MCR_REG(basePtr) &= ~SPI_MCR_FRZ_MASK; +} + +void reset_ch1() +{ + // configure SPI1 pins PORTB_PCR11(SCK), PORTB_PCR17(SDI), PORTB_PCR15(SDO), PORTB_PCR10(CSN) + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(SPI.ch1.CSN); + + // set SPI0 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(SPI.ch1.periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; +} + +void reset_ch2() +{ +// // configure SPI2 pins PORTB_PCR21(SCK), PORTB_PCR23(SDI), PORTB_PCR22(SDO), PORTC_PCR0(CSN0), PORTA_PCR0(CSN5), PORTA_PCR4(CSN2) + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(SPI.ch2.CSN); + SPI.ch2.readWrite = spi_ch2_readWrite; + + // set SPI0 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(SPI.ch2.periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; +} + +// Helper lookup tables +static uint8_t PBR_values[4] = { 2, 3, 5, 7 }; +static uint16_t BR_values[16] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768 }; + +uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel) +{ + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + uint8_t pbr = PBR_values[FIELD_GET(tmp, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR_SHIFT)]; + uint8_t br = BR_values[FIELD_GET(tmp, SPI_CTAR_BR_MASK, SPI_CTAR_BR_SHIFT)]; + + return CPU_BUS_CLK_HZ / pbr / br; +} + +// Set the SPI frequency to the next-best available frequency (rounding down). +// Returns the actual frequency set or 0 if no suitable frequency was found. +uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency) +{ + if (!SPIChannel) + return 0; + + uint32_t bestFrequency = 0; + uint8_t bestPBR = 0; + uint8_t bestBR = 0; + + // Find the highest frequency that is lower or equal to the desired frequency + for (uint32_t i = 0; i < ARRAY_SIZE(PBR_values); i++) + { + // For each possible PBR prescaler value... + uint8_t pbr = PBR_values[i]; + uint32_t pbrFreq = CPU_BUS_CLK_HZ / pbr; + + // Calculate the ideal divisor (rounding up to not exceed the desired frequency) + uint32_t divisor = (pbrFreq + desiredFrequency - 1) / desiredFrequency; + + // Find the next-largest available BR divisor + uint32_t j; + for (j = 0; j < ARRAY_SIZE(BR_values); j++) + { + if (BR_values[j] >= divisor) + break; + } + + // If no BR divisor value is larger, check the next PBR value + if (j == ARRAY_SIZE(BR_values)) + continue; + + // Calculate the resulting actual frequency + uint32_t actualFrequency = pbrFreq / BR_values[j]; + + // Sanity check: Verify that the actual frequency is smaller than the desired frequency + if (actualFrequency > desiredFrequency) + continue; + + // Check if the actual frequency is better than the previous ones + // and store the parameters if it is. + if (actualFrequency > bestFrequency) + { + bestFrequency = actualFrequency; + bestPBR = i; + bestBR = j; + } + } + + // If we couldn't find a suitable frequency, abort + if (bestFrequency == 0) + return 0; + + // Update the hardware parameters + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0) & ~(SPI_CTAR_DT_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_PBR_MASK); + tmp |= SPI_CTAR_DT(0); + tmp |= SPI_CTAR_PBR(bestPBR); + tmp |= SPI_CTAR_BR(bestBR); + SPI_CTAR_REG(SPIChannel->periphery, 0) = tmp; + + return bestFrequency; +} + +uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel) +{ + if (!SPIChannel) + return 0; + + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + uint8_t cpol = FIELD_GET(tmp, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL_SHIFT); + uint8_t cpha = FIELD_GET(tmp, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA_SHIFT); + + return (cpol << 1) | cpha; +} + +bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode) +{ + if (!SPIChannel) + return false; + + if (mode > 3) + return false; + + uint8_t cpol = (mode>>1) & 1; + uint8_t cpha = mode & 1; + + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + tmp &= ~(SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK); + tmp |= cpol ? SPI_CTAR_CPOL_MASK : 0; + tmp |= cpha ? SPI_CTAR_CPHA_MASK : 0; + SPI_CTAR_REG(SPIChannel->periphery, 0) = tmp; + + return true; +} + +int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address) +{ + // clear write bit + address &= 0x7F; + + SPIChannel->readWrite(address, false); + int value = SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, true); + + return value; +} + +int32_t spi_ch1_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_1_default, address); +} + +int32_t spi_ch2_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_2_default, address); +} + +void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value) +{ + SPIChannel->readWrite(address|0x80, false); + SPIChannel->readWrite(0xFF & (value>>24), false); + SPIChannel->readWrite(0xFF & (value>>16), false); + SPIChannel->readWrite(0xFF & (value>>8), false); + SPIChannel->readWrite(0xFF & (value>>0), true); +} + +void spi_ch1_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_1_default, address, value); +} + +void spi_ch2_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_2_default, address, value); +} + +uint8_t spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(&SPI.ch1, data, lastTransfer); +} + +uint8_t spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(&SPI.ch2, data, lastTransfer); +} + +static void spi_ch1_readWriteArray(uint8_t *data, size_t length) +{ + for(size_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch1, data[i], (i == (length - 1))? true:false); + } +} + +static void spi_ch2_readWriteArray(uint8_t *data, size_t length) +{ + for(size_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch2, data[i], (i == (length - 1))? true:false); + } +} + +uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(SPIChannel_1_default, data, lastTransfer); +} + +uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + return SPIChannel->readWrite(data, lastTransfer); +} + +uint8_t readWrite(SPIChannelTypeDef *SPIChannel, uint8_t writeData, uint8_t lastTransfer) +{ + uint8_t readData = 0; + + if(IS_DUMMY_PIN(SPIChannel->CSN)) + return 0; + + HAL.IOs->config->setLow(SPIChannel->CSN); // Chip Select + + if(lastTransfer) + { + // send last byte + SPI_PUSHR_REG(SPIChannel->periphery) = SPI_PUSHR_EOQ_MASK | SPI_PUSHR_TXDATA(writeData) ; + + while(!(SPI_SR_REG(SPIChannel->periphery) & SPI_SR_EOQF_MASK)) {} // wait until End Of Queue flag has been set -> transfer done + + SPI_SR_REG(SPIChannel->periphery) |= SPI_SR_EOQF_MASK; // clear EOQ Flag by writing a 1 to EOQF + + HAL.IOs->config->setHigh(SPIChannel->CSN); // reset CSN manual, falls Probleme Auftreten, dann diese Zeile unter die while Schleife + + // wait for an answer + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT) == 0) {} + + // read the data + readData = SPI_POPR_REG(SPIChannel->periphery); + + // clear TXF and RXF + SPI_MCR_REG(SPIChannel->periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; + } else { + // continuous transfer + SPI_PUSHR_REG(SPIChannel->periphery) = SPI_PUSHR_CONT_MASK | SPI_PUSHR_TXDATA(writeData); // | SPI_PUSHR_PCS(0x0); + + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT) > 3) {} // wait if TX counter > 3 + + // wait for an answer + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT) == 0) {} + + // read the data + readData = SPI_POPR_REG(SPIChannel->periphery); + } + + return readData; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c new file mode 100644 index 0000000..f85f9c9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/SysTick.h" + +volatile uint32_t systick = 0; + +void __attribute__ ((interrupt)) SysTick_Handler(void); + +void SysTick_Handler(void) +{ + systick++; +} + +void systick_init() +{ + SYST_RVR = 48000; + SYST_CSR = 7; + + // Enable the DWT CYCCNT for the µs counter + DWT_CTRL |= 0x00000001; +} + +uint32_t systick_getTick() +{ + return systick; +} + +uint32_t systick_getMicrosecondTick() +{ + // 48 MHz CYCCNT / 48 -> µs counter + return DWT_CYCCNT / 48; +} + +/* Systick values are in milliseconds, accessing the value is faster. As a result + * we have a random invisible delay of less than a millisecond whenever we use + * systicks. This can result in a situation where we access the systick just before it changes: + * -> Access at 0,99ms gives systick 0ms + * -> Access at 1.01ms gives systick 1ms + * -> systick difference of 1ms, even though only 0.02 ms passed + * To prevent this, we generally apply a correction of -1 to any systick difference. + * In wait() this is done by using '<=' instead of '<' + * In timeDiff() the subtraction is carried out on the result. + * That subtraction is prevented from underflowing to UINT32_MAX, returning 0 in + * that case (Saturated subtraction). + * + */ +void wait(uint32_t delay) // wait for [delay] ms/systicks +{ + uint32_t startTick = systick; + while((systick-startTick) <= delay) {} +} + +uint32_t timeSince(uint32_t tick) // time difference since the [tick] timestamp in ms/systicks +{ + return timeDiff(systick, tick); +} + +uint32_t timeDiff(uint32_t newTick, uint32_t oldTick) // Time difference between newTick and oldTick timestamps +{ + uint32_t tickDiff = newTick - oldTick; + + // Prevent subtraction underflow - saturate to 0 instead + if(tickDiff != 0) + return tickDiff - 1; + else + return 0; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c new file mode 100644 index 0000000..496b530 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c @@ -0,0 +1,271 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/Timer.h" + +#define MAX_ARR_HALF TIMER_MAX >> 1 + +void __attribute__ ((interrupt)) FTM0_IRQHandler(void); + +static void init(void); +static void deInit(void); +static void setDuty(timer_channel channel, float duty); +static float getDuty(timer_channel channel); +static void setModulo(timer_channel channel, uint16_t modulo); +static uint16_t getModulo(timer_channel channel); +static void setModuloMin(timer_channel channel, uint16_t modulo_min); +static void setFrequency(timer_channel channel, float freq); +static void setFrequencyMin(timer_channel channel, float freq_min); + +static uint16_t modulo_buf = 0; +static uint16_t modulo_min_buf = 0; +static float duty_buf[] = { .5f, .5f, .5f }; +static float freq_min_buf = 0.0f; + +TimerTypeDef Timer = +{ + .initialized = false, + .init = init, + .deInit = deInit, + .setDuty = setDuty, + .getDuty = getDuty, + .setPeriod = setModulo, + .getPeriod = getModulo, + .setPeriodMin = setModuloMin, + .setFrequency = setFrequency, + .setFrequencyMin = setFrequencyMin, + .overflow_callback = NULL +}; + +static void init(void) +{ + // enable clock for FTM0 + SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; + + // enable clock for port D + SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; + + // disable write protection + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + + // FAULTM = 1 - Fault control is enabled for all channels, + // FTMEN = 1 - all registers are available for use with no restrictions. + FTM0_MODE |= FTM_MODE_FAULTM_MASK | FTM_MODE_FTMEN_MASK; + + // setting for Center Aligned PWM in Combine Mode + FTM0_MOD = TIMER_MAX; // set PWM frequency + modulo_buf = TIMER_MAX; + FTM0_CNTIN = 0; // CTNMAX = 1 - PWM update at counter in max. value + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + + // SWSYNC = 1 - set PWM value update. This bit is cleared automatically. + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + + // disable all channels outputs using the OUTPUT MASK feature + FTM0_OUTMASK = FTM_OUTMASK_CH0OM_MASK | FTM_OUTMASK_CH1OM_MASK + | FTM_OUTMASK_CH4OM_MASK | FTM_OUTMASK_CH5OM_MASK + | FTM_OUTMASK_CH6OM_MASK | FTM_OUTMASK_CH7OM_MASK; + + /* COMBINE = 1 - combine mode set, COMP = 1 - complementary PWM set, + DTEN = 1 - deadtime enabled, SYNCEN = 1 - PWM update synchronization enabled, + FAULTEN = 1 - fault control enabled */ + FTM0_COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DTEN0_MASK + | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_COMBINE0_MASK + | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_DTEN2_MASK + | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_COMBINE2_MASK + | FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_DTEN3_MASK + | FTM_COMBINE_COMP3_MASK | FTM_COMBINE_COMBINE3_MASK; + + // initialize setting of value registers to duty cycle + FTM0_C0V = 0; + FTM0_C1V = (uint16_t)(duty_buf[1] * TIMER_MAX); + FTM0_C4V = 0; + FTM0_C5V = (uint16_t)(duty_buf[2] * TIMER_MAX); + FTM0_C6V = 0; + FTM0_C7V = (uint16_t)(duty_buf[0] * TIMER_MAX); + + // set channel mode to generate positive PWM + FTM0_C0SC |= FTM_CnSC_ELSB_MASK; + FTM0_C1SC |= FTM_CnSC_ELSB_MASK; + FTM0_C4SC |= FTM_CnSC_ELSB_MASK; + FTM0_C5SC |= FTM_CnSC_ELSB_MASK; + FTM0_C6SC |= FTM_CnSC_ELSB_MASK; + FTM0_C7SC |= FTM_CnSC_ELSB_MASK; + + // enable loading of the MOD, CNTIN, and CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + // enable the generation of the trigger when the FTM counter is equal to the CNTIN register + FTM0_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK; + FTM0_MODE |= FTM_MODE_INIT_MASK; + + // set system clock as source for FTM0 (CLKS[1:0] = 01) + FTM0_SC |= FTM_SC_CLKS(1); // Periodendauer 166,66us + + // initialize pwm pin for FTM0 + + + + + // ATTENTION The Pins had to configure as AF4 near the initialisation !!!!!! + + + + + // enable PWM outputs of FTM0 + FTM0_OUTMASK = 0; + + FTM0_SC |= (uint32_t)(FTM_SC_TOIE_MASK); + + enable_irq(INT_FTM0-16); + + Timer.initialized = true; +} + +static void deInit(void) +{ + disable_irq(INT_FTM0-16); + SIM_SCGC6 &= ~SIM_SCGC6_FTM0_MASK; +} + +static void setDuty(timer_channel channel, float duty) +{ + duty = (duty < 0.0f) ? 0.0f : duty; + duty = (duty > 1.0f) ? 1.0f : duty; + + switch(channel) { + case TIMER_CHANNEL_2: + duty_buf[1] = duty; + FTM0_C1V = (uint16_t) (duty * modulo_buf); + break; + case TIMER_CHANNEL_3: + duty_buf[2] = duty; + FTM0_C5V = (uint16_t) (duty * modulo_buf); + break; + case TIMER_CHANNEL_1: + default: + duty_buf[0] = duty; + FTM0_C7V = (uint16_t) (duty * modulo_buf); + break; + } + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +static float getDuty(timer_channel channel) +{ + uint16_t duty = 0; + switch(channel) { + case TIMER_CHANNEL_2: + duty = (FTM0_C1V - FTM0_C0V); + break; + case TIMER_CHANNEL_3: + duty = (FTM0_C5V - FTM0_C4V); + break; + case TIMER_CHANNEL_1: + default: + duty = (FTM0_C7V - FTM0_C6V); + break; + } + + return (((float)duty) / modulo_buf); +} + +static void setModulo(timer_channel channel, uint16_t modulo) +{ + UNUSED(channel); + disable_irq(INT_FTM0-16); + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + FTM0_MOD = modulo; + modulo_buf = modulo; + FTM0_CNTIN = 0; + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + enable_irq(INT_FTM0-16); +} + +static uint16_t getModulo(timer_channel channel) +{ + UNUSED(channel); + //return FTM0_MOD; + return modulo_buf; +} + +static void setModuloMin(timer_channel channel, uint16_t modulo_min) +{ + UNUSED(channel); + modulo_min_buf = modulo_min; +} + +static void setFrequencyMin(timer_channel channel, float freq_min) +{ + UNUSED(channel); + freq_min_buf = freq_min; +} + +static void setFrequency(timer_channel channel, float freq) +{ + UNUSED(channel); + + if(freq < freq_min_buf) + return; + + if(freq < ((float)CPU_BUS_CLK_HZ / ((1 << 0b111) * 0xFFFF))) + return; + + if(freq > (float)CPU_BUS_CLK_HZ) + return; + + disable_irq(INT_FTM0-16); + + uint8_t ps = 0b000; + uint16_t modulo = 0xFFFF; + + for(; ps < 0b111; ps++) + { + if(freq > ((float)CPU_BUS_CLK_HZ / ((1 << ps) * modulo))) + { + modulo = (float)CPU_BUS_CLK_HZ / ((1 << ps) * freq); + if((modulo < modulo_min_buf) && (ps > 0b000)) + modulo = (float)CPU_BUS_CLK_HZ / ((1 << (ps - 1)) * freq); + break; + } + } + + modulo_buf = modulo; + + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + FTM0_SC |= FTM_SC_PS(ps); + FTM0_MOD = modulo; + FTM0_CNTIN = 0; + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + setDuty(TIMER_CHANNEL_1, duty_buf[0]); + setDuty(TIMER_CHANNEL_2, duty_buf[1]); + setDuty(TIMER_CHANNEL_3, duty_buf[2]); + + enable_irq(INT_FTM0-16); +} + +void FTM0_IRQHandler() +{ + if(FTM0_SC & FTM_SC_TOF_MASK) + { + // overflow detected + if(Timer.overflow_callback) + Timer.overflow_callback(TIMER_CHANNEL_2); + FTM0_SC &= ~FTM_SC_TOF_MASK; + } + + // Stop the timer + //FTM2_SC &= ~FTM_SC_CLKS_MASK; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c new file mode 100644 index 0000000..e3ae77a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c @@ -0,0 +1,470 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/UART.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#define BUFFER_SIZE 32 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 +#define WRITE_READ_DELAY 10 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static volatile uint32_t available = 0; + +UART_Config UART = +{ + .mode = UART_MODE_DUAL_WIRE, + .pinout = UART_PINS_1, + .rxtx = + { + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable + } +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd = (CPU_BUS_CLK_HZ / 16) / UART.rxtx.baudRate; + + // One wire UART communication needs the TxD pin to be in open drain mode + // and a pull-up resistor on the RxD pin. + switch(UART.pinout) { + case UART_PINS_2: + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO10) + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO11) + HAL.IOs->pins->DIO10.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO11.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; + UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + UART_C1_REG(UART0_BASE_PTR) = 0; + UART_C4_REG(UART0_BASE_PTR) = 0; + UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + enable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; + UART_C1_REG(UART2_BASE_PTR) = 0; + switch(UART.mode) { + case UART_MODE_SINGLE_WIRE: + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + HAL.IOs->pins->DIO18.configuration.GPIO_OType = GPIO_OType_OD; // RxD as open drain output + HAL.IOs->pins->DIO17.configuration.GPIO_PuPd = GPIO_PuPd_UP; // TxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + // Enable single wire UART + UART_C1_REG(UART2_BASE_PTR) |= (UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK); + // Set TxD as output in single wire UART + UART_C3_REG(UART2_BASE_PTR) |= UART_C3_TXDIR_MASK; + break; + case UART_MODE_DUAL_WIRE: + case UART_MODE_DUAL_WIRE_PushPull: + default: + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + HAL.IOs->pins->DIO17.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO18.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + break; + } + UART_C2_REG(UART2_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + UART_BDH_REG(UART2_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART2_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + UART_C2_REG(UART2_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + enable_irq(INT_UART2_RX_TX-16); + break; + } + +// /* Disable the transmitter and receiver */ +// UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); +// +// /* Configure the UART for 8-bit mode, no parity */ +// /* We need all default settings, so entire register is cleared */ +// UART_C1_REG(UART0_BASE_PTR) = 0; +// +// ubd = (CPU_BUS_CLK_HZ / 16) / UART.baudRate; +// +// UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; +// UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); +// +// /* Enable receiver and transmitter */ +// UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + +} + +static void deInit() +{ + switch(UART.pinout) { + case UART_PINS_2: + SIM_SCGC4 &= ~(SIM_SCGC4_UART0_MASK); + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + disable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + SIM_SCGC4 &= ~(SIM_SCGC4_UART2_MASK); + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + disable_irq(INT_UART2_RX_TX-16); + break; + } + + clearBuffers(); +} + +void UART0_RX_TX_IRQHandler_UART(void) +{ + static uint8_t isSending = false; + uint32_t status = UART0_S1; + + // Receive interrupt + if(status & UART_S1_RDRF_MASK) + { + // One-wire UART communication: + buffers.rx.buffer[buffers.rx.wrote] = UART0_D; + if(!isSending) // Only move ring buffer index & available counter when the received byte wasn't the send echo + { + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(status & UART_S1_TC_MASK) + { + // Last bit has been sent + isSending = false; + UART0_C2 &= ~UART_C2_TCIE_MASK; + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART0_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + + isSending = true; // Ignore echo + UART0_C2 |= UART_C2_TCIE_MASK; // Turn on transmission complete interrupt + } + else + { + UART0_C2 &= ~UART_C2_TIE_MASK; // empty buffer -> turn off transmit buffer empty interrupt + } + } +} + +void UART2_RX_TX_IRQHandler(void) +{ + static uint8_t isSending = false; + uint32_t status = UART2_S1; + + // Receive interrupt + if(status & UART_S1_RDRF_MASK) + { + // One-wire UART communication: + buffers.rx.buffer[buffers.rx.wrote] = UART2_D; + if(!isSending) // Only move ring buffer index & available counter when the received byte wasn't the send echo + { + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(status & UART_S1_TC_MASK) + { + // Last bit has been sent + isSending = false; + UART2_C2 &= ~UART_C2_TCIE_MASK; + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART2_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + + isSending = true; // Ignore echo + UART2_C2 |= UART_C2_TCIE_MASK; // Turn on transmission complete interrupt + } + else + { + UART2_C2 &= ~UART_C2_TIE_MASK; // empty buffer -> turn off transmit buffer empty interrupt + } + } +} + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = systick_getTick(); + while(uart->rxtx.bytesAvailable() < readLength) + { + if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + { + // Abort on timeout + return -1; + } + } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value) +{ + uint8_t readData[8], dataRequest[4]; + uint32_t timeout; + + dataRequest[0] = 0x05; // Sync byte + dataRequest[1] = slave; // Slave address + dataRequest[2] = address; // Register address + dataRequest[3] = tmc_CRC8(dataRequest, 3, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + channel->rxtx.txN(dataRequest, ARRAY_SIZE(dataRequest)); + + // Wait for reply with timeout limit + timeout = systick_getTick(); + while(channel->rxtx.bytesAvailable() < ARRAY_SIZE(readData)) + if(timeSince(timeout) > UART_TIMEOUT_VALUE) // Timeout + return; + + channel->rxtx.rxN(readData, ARRAY_SIZE(readData)); + // Check if the received data is correct (CRC, Sync, Slave address, Register address) + // todo CHECK 2: Only keep CRC check? Should be sufficient for wrong transmissions (LH) #1 + if(readData[7] != tmc_CRC8(readData, 7, 1) || readData[0] != 0x05 || readData[1] != 0xFF || readData[2] != address) + return; + + *value = readData[3] << 24 | readData[4] << 16 | readData[5] << 8 | readData[6]; + return; +} + +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value) +{ + uint8_t writeData[8]; + + writeData[0] = 0x05; // Sync byte + writeData[1] = slave; // Slave address + writeData[2] = address | TMC_WRITE_BIT; // Register address with write bit set + writeData[3] = value >> 24; // Register Data + writeData[4] = value >> 16; // Register Data + writeData[5] = value >> 8; // Register Data + writeData[6] = value & 0xFF; // Register Data + writeData[7] = tmc_CRC8(writeData, 7, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + for(uint32_t i = 0; i < ARRAY_SIZE(writeData); i++) + channel->rxtx.tx(writeData[i]); + + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); +} + +void UART_setEnabled(UART_Config *channel, uint8_t enabled) +{ + switch(channel->pinout) + { + case UART_PINS_2: + if (enabled) + { + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO10) + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO11) + HAL.IOs->pins->DIO10.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO11.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + } + else + { + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + } + break; + case UART_PINS_1: + if (enabled) + { + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + + if (channel->mode == UART_MODE_SINGLE_WIRE) + { + HAL.IOs->pins->DIO18.configuration.GPIO_OType = GPIO_OType_OD; // RxD as open drain output + HAL.IOs->pins->DIO17.configuration.GPIO_PuPd = GPIO_PuPd_UP; // TxD with pull-up resistor + } + else + { + HAL.IOs->pins->DIO17.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO18.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + } + + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + } + else + { + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + } + break; + default: + break; + + } +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + + // enable send interrupt + switch(UART.pinout) { + case UART_PINS_2: + UART0_C2 |= UART_C2_TIE_MASK; + break; + case UART_PINS_1: + default: + UART2_C2 |= UART_C2_TIE_MASK; + break; + } +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + switch(UART.pinout) { + case UART_PINS_2: + disable_irq(INT_UART0_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + disable_irq(INT_UART2_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART2_RX_TX-16); + break; + } +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c new file mode 100644 index 0000000..4157498 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c @@ -0,0 +1,114 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/USB.h" + +#include "hal/Landungsbruecke/freescale/USB_CDC/USB0.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/USB1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/Tx1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/Rx1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/CDC1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/CS1.h" + +#if USB_USE_UNIQUE_SERIAL_NUMBER +#error "Landungsbruecke and LandungsbrueckeSmall do not yet support unique serial numbers" +#endif + + +extern uint8_t USB_DCI_DeInit(void); +extern uint8_t USB_Class_CDC_DeInit(uint8_t controller_ID); +extern uint8_t USB_Class_DeInit(uint8_t controller_ID); + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +RXTXTypeDef USB = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +void init() +{ + USB0_Init(); + Tx1_Init(); + Rx1_Init(); + USB1_Init(); + enable_irq(INT_USB0-16); +} + +uint8_t rx(uint8_t *ch) +{ + return rxN(ch,1); +} + +uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(CDC1_GetCharsInRxBuf() >= number) + { + for(int32_t i = 0; i < number; i++) + { + if(CDC1_GetChar(&str[i])!= ERR_OK) + return false; + } + return true; + } + return false; +} + +void tx(uint8_t ch) +{ + CDC1_SendChar(ch); +} + +void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + { + tx(str[i]); + } +} + +static void clearBuffers(void) +{ + DisableInterrupts; + Tx1_Init(); + Rx1_Init(); + EnableInterrupts; +} + +static uint32_t bytesAvailable() +{ + return CDC1_GetCharsInRxBuf(); +} + +static void deInit(void) +{ + USB_DCI_DeInit(); + USB_Class_CDC_DeInit(0); + USB_Class_DeInit(0); + + SIM_SCGC4 &= ~SIM_SCGC4_USBOTG_MASK; + SIM_SCGC6 &= ~SIM_SCGC6_USBDCD_MASK; + SIM_SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c new file mode 100644 index 0000000..f7b24e1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c @@ -0,0 +1,349 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +//#include "hal/WLAN.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#include + +#define BUFFER_SIZE 1024 +#define WLAN_CMD_BUFFER_SIZE 128 // ascii command string buffer + +#define CMDBUFFER_END_CHAR '\0' + +#define INTR_PRI 6 + +#define UART_TIMEOUT_VALUE 5 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +// ring buffers (used in BufferingTypedef struct) +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; + +static int8_t cmdBuffer[WLAN_CMD_BUFFER_SIZE]; +static uint32_t cmdBufferSize = 0; +static uint32_t cmdEnabledTime; // systick timestamp when command mode sequence has been sent + +static WLANStateTypedef wlanState = WLAN_DATA_MODE; + +static volatile uint32_t available = 0; + +uint32_t UART0_TimeoutTimer; + +RXTXTypeDef WLAN = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 57600, + .bytesAvailable = bytesAvailable + +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd; + + HAL.IOs->config->toOutput(&HAL.IOs->pins->MIXED6); + HAL.IOs->config->setLow(&HAL.IOs->pins->MIXED6); + + SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; + + HAL.IOs->pins->WIRELESS_RX.configuration.GPIO_Mode = GPIO_Mode_AF3; + HAL.IOs->pins->WIRELESS_TX.configuration.GPIO_Mode = GPIO_Mode_AF3; + + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_TX); + /* Disable the transmitter and receiver */ + UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + + /* Configure the UART for 8-bit mode, no parity */ + /* We need all default settings, so entire register is cleared */ + UART_C1_REG(UART0_BASE_PTR) = 0; + + ubd = (CPU_BUS_CLK_HZ / 16) / (WLAN.baudRate); + + UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + + /* Enable receiver and transmitter */ + UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + + enable_irq(INT_UART0_RX_TX-16); +} + +static void deInit() +{ + SIM_SCGC4 &= ~(SIM_SCGC4_UART0_MASK); + + HAL.IOs->pins->WIRELESS_RX.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->WIRELESS_TX.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_TX); + + disable_irq(INT_UART0_RX_TX-16); + + clearBuffers(); +} + +void UART0_RX_TX_IRQHandler_WLAN(void) +{ + uint32_t status = UART0_S1; + + if(status & UART_S1_RDRF_MASK) + { + buffers.rx.buffer[buffers.rx.wrote] = UART0_D; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + // reset timeout value + UART0_TimeoutTimer = UART_TIMEOUT_VALUE; + UART0_S1 &= ~(UART_S1_RDRF_MASK); // Zurücksetzen InterruptFlag + } + + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART0_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else // empty buffer -> turn off send interrupt + { + UART0_C2 &= ~UART_C2_TIE_MASK; + } + UART0_S1 &= ~(UART_S1_TDRE_MASK); // Zurücksetzen InterruptFlag + } +} + +// Send without checking for CMD/Data mode +static void rawTx(uint8_t ch) +{ + if(wlanState == WLAN_INIT_CMD_MODE) + return; + + buffers.tx.buffer[buffers.tx.wrote] = ch; + + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; // Move ring buffer index + + // enable send interrupt + UART0_C2 |= UART_C2_TIE_MASK; +} + +// Wrapper for rawTx, will silently fail if we're not in data mode +// todo CHECK ADD 3: Should tx be given a return type in order to report failure to send? (LH) #1 +static void tx(uint8_t ch) +{ + if(checkReadyToSend()) + rawTx(ch); +} + +static uint8_t rawRx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; // Move ring buffer index + available--; + + return 1; +} + +static uint8_t rx(uint8_t *ch) +{ + if(wlanState != WLAN_DATA_MODE) + return 0; + + return rawRx(ch); +} + +// todo CHECK ADD 3: Should txN be given a return type in order to report failure to send? (LH) #2 +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + disable_irq(INT_UART0_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART0_RX_TX-16); +} + +static uint32_t bytesAvailable() +{ + return available; +} + +uint32_t checkReadyToSend() +{ + if(checkCmdModeEnabled()) + { + return false; + } + else + { + return (wlanState == WLAN_INIT_CMD_MODE)? false:true; + } +} + +void enableWLANCommandMode() +{ /* To enable command mode, the escape character (default: $) needs to be sent 3 times. + * Additionally, both before and after that sequence there should be 250ms without data sent to the module + * Since the configuration mode is supposed to be used as a simple testing tool, + * there is no check for the time span before the write. If the switching fails due to that, + * an error will be returned upon attempted command execution, just try to reenter command mode then. + */ + wlanState = WLAN_CMD_MODE; // Block external write sources + + clearBuffers(); + rawTx('$'); // txN doesn't work, as WLAN_CMD_MODE prevents tx (which txN calls) from writing to the buffer) + rawTx('$'); + rawTx('$'); + wlanState = WLAN_INIT_CMD_MODE; // Block all writes + cmdEnabledTime = systick_getTick(); +} + +uint32_t checkCmdModeEnabled() +{ + if(wlanState == WLAN_CMD_MODE) + return true; + else if(wlanState == WLAN_DATA_MODE) + return false; + + uint8_t reply[4] = { 0 }; // expected reply: {'C','M','D'}, we're appending \0 so we have a NULL-terminated string that we can use in strcmp() + if(rxN(reply, 3)) + { + if(strcmp((const char *)reply, "CMD") == 0) + { + wlanState = WLAN_CMD_MODE; + return true; + } + else + { // Unexpected answer - going back to data mode + wlanState = WLAN_DATA_MODE; + return false; + } + } + else + { + if(timeSince(cmdEnabledTime) > 350) // 250 ms from chip spec + 100ms, just to be safe + { // Too much time passed since attempted cmd mode switching happened - assuming it failed + wlanState = WLAN_DATA_MODE; + return false; + } + else + { // Not enough time passed, we're not in command mode yet but we're still giving the chip time + return false; + } + } +} + +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value) +{ + switch(cmd) + { + case BUFFER_CLEAR: + cmdBufferSize = 0; + break; + case BUFFER_WRITE: + while((value & 0xFF) != CMDBUFFER_END_CHAR) + { + if(cmdBufferSize == WLAN_CMD_BUFFER_SIZE) + { + if((value & 0xFF) != 0) // Any value still remaining -> too much data for buffer -> return an error + return 1; + break; + } + cmdBuffer[cmdBufferSize] = value & 0xFF; + value >>= 8; + cmdBufferSize++; + } + break; + case BUFFER_EXECUTE: + // Abort if not in command mode. IDE/User should switch to command mode before executing + if(!checkCmdModeEnabled()) + return 1; + + for(uint32_t i = 0; i < cmdBufferSize; i++) + rawTx(cmdBuffer[i]); // Can't use txN since its blocked from sending while in command mode + rawTx('\r'); // End of command character + + cmdBufferSize = 0; + break; + } + + return 0; +} + +uint32_t getCMDReply() +{ + uint8_t cmdReply; + uint32_t result = 0; + + for(uint8_t i = 0; i < 4; i++) + { + if(rawRx(&cmdReply) == 0) + cmdReply = 0; + // First character is in the smallest byte of result + result |= cmdReply << 24; + result >>= 8; + } + + return result; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld new file mode 100644 index 0000000..30d0f5a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld @@ -0,0 +1,161 @@ +/* +***************************************************************************** +** +** File : gd32f425.ld +** +** Abstract : Linker script for GD32F425VG Device with +** 1024KByte FLASH, 192KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** +** Target : GigaDevice GD32F425 (with TMCM bootloader) +** +** Environment : GCC +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of 192K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 224K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld new file mode 100644 index 0000000..a70030a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld @@ -0,0 +1,152 @@ +/* +***************************************************************************** +** +** File : gd32f425.ld +** +** Abstract : Linker script for GD32F425VG Device with +** 1024KByte FLASH, 192KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** +** Target : GigaDevice GD32F425 +** +** Environment : GCC +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of 192K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h new file mode 100644 index 0000000..f319458 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h @@ -0,0 +1,1790 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h new file mode 100644 index 0000000..bee997e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h new file mode 100644 index 0000000..adb07b5 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h new file mode 100644 index 0000000..624c175 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h new file mode 100644 index 0000000..ca0ff97 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h @@ -0,0 +1,368 @@ +/*! + \file gd32f4xx.h + \brief general definitions for GD32F4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_H +#define GD32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* define GD32F4xx */ +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) + /* #define GD32F450 */ + /* #define GD32F405 */ + /* #define GD32F407 */ + /* #define GD32F470 */ + #define GD32F425 + /* #define GD32F427 */ +#endif /* define GD32F4xx */ + +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) + #error "Please select the target GD32F4xx device in gd32f4xx.h file" +#endif /* undefine GD32F4xx tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined (HXTAL_VALUE) +#define HXTAL_VALUE ((uint32_t)16000000) +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ +#if !defined (IRC16M_VALUE) +#define IRC16M_VALUE ((uint32_t)16000000) +#endif /* internal 16MHz RC oscillator value */ + +/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */ +#if !defined (IRC16M_STARTUP_TIMEOUT) +#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 16MHz RC oscillator startup timeout */ + +/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ +#if !defined (IRC32K_VALUE) +#define IRC32K_VALUE ((uint32_t)32000) +#endif /* internal 32KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* I2S external clock in selection */ +//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U + +/* GD32F4xx firmware library version number V1.0 */ +#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F4xx_STDPERIPH_VERSION_RC)) + +/* configuration of the cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +/* define interrupt number */ +typedef enum IRQn +{ + /* cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ + RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC_IRQn = 18, /*!< ADC interrupt */ + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ + DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ + +#if defined (GD32F450) || defined (GD32F470) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ + UART6_IRQn = 82, /*!< UART6 interrupt */ + UART7_IRQn = 83, /*!< UART7 interrupt */ + SPI3_IRQn = 84, /*!< SPI3 interrupt */ + SPI4_IRQn = 85, /*!< SPI4 interrupt */ + SPI5_IRQn = 86, /*!< SPI5 interrupt */ + TLI_IRQn = 88, /*!< TLI interrupt */ + TLI_ER_IRQn = 89, /*!< TLI error interrupt */ + IPA_IRQn = 90, /*!< IPA interrupt */ +#endif /* GD32F450 and GD32F470 */ + +#if defined (GD32F405) || defined (GD32F425) + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F405 and GD32F425 */ + +#if defined (GD32F407) || defined (GD32F427) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F407 and GD32F427 */ + +} IRQn_Type; + +/* includes */ +#include "core_cm4.h" +#include "system_gd32f4xx.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */ +#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */ + +/* EXMC memory map */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */ + +/* advanced peripheral bus 2 memory map */ +#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */ +#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */ +/* advanced high performance bus 1 memory map */ +#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */ +#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */ +#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */ +#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */ + +/* advanced high performance bus 2 memory map */ +#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */ +#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */ +#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */ +/* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +//#if !defined USE_STDPERIPH_DRIVER +//#define USE_STDPERIPH_DRIVER +//#endif +//#ifdef USE_STDPERIPH_DRIVER +#include "gd32f4xx_libopt.h" +//#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h new file mode 100644 index 0000000..3596924 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h @@ -0,0 +1,516 @@ +/*! + \file gd32f4xx_adc.h + \brief definitions for the ADC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_ADC_H +#define GD32F4XX_ADC_H + +#include "gd32f4xx.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x100U) +#define ADC2 (ADC_BASE + 0x200U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ +#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ +#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */ +#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ +#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */ +#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ +#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */ +#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */ +#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ + +/* ADC_SSTAT */ +#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ +#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ +#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ +#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ +#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ +#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ +#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ +#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ +#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ +#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ +#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ +#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ +#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ +#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ +#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ +#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ +#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ +#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ + +/* ADC_SYNCCTL */ +#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ +#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ +#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ +#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ +#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ +#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ +#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ + +/* ADC_SYNCDATA */ +#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */ + +/* constants definitions */ +/* ADC status flag */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */ +#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* ADC special function definitions */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* temperature sensor channel, internal reference voltage channel, VBAT channel */ +#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ +#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ + +/* ADC synchronization mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */ +#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */ +#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* external trigger mode for routine and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ + +/* ADC external trigger select for routine channel */ +#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ + +/* ADC external trigger select for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ + +/* ADC channel sample time */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +/* ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ + +/* ADC interrupt flag */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ + +/* configure the ADC clock for all the ADCs */ +#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ +#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ +#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ +#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ +#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ +#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ +#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ +#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ + +/* ADC synchronization delay */ +#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ +#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ +#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ +#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ +#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ +#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ +#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ +#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ +#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ +#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ +#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ +#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ +#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ +#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ +#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ +#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ + +/* ADC synchronization DMA mode selection */ +#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ +#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ +#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ + +/* end of conversion mode */ +#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */ +#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(void); +/* configure the ADC clock for all the ADCs */ +void adc_clock_config(uint32_t prescaler); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* configure temperature sensor and internal reference voltage channel or VBAT channel function */ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue); +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); +/* when DMA=1, the DMA engine issues a request at end of each routine conversion */ +void adc_dma_request_after_last_enable(uint32_t adc_periph); +/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ +void adc_dma_request_after_last_disable(uint32_t adc_periph); + +/* routine sequence and inserted sequence config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); +/* configure end of conversion mode */ +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); + +/* get channel data */ +/* read ADC routine data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); + +/* watchdog config */ +/* disable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_disable(uint32_t adc_periph ); +/* enable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); +/* configure ADC analog watchdog sequence */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); + +/* ADC synchronization */ +/* configure the ADC sync mode */ +void adc_sync_mode_config(uint32_t sync_mode); +/* configure the delay between 2 sampling phases in ADC sync modes */ +void adc_sync_delay_config(uint32_t sample_delay); +/* configure ADC sync DMA mode selection */ +void adc_sync_dma_config(uint32_t dma_mode ); +/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */ +void adc_sync_dma_request_after_last_enable(void); +/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ +void adc_sync_dma_request_after_last_disable(void); +/* read ADC sync routine data register */ +uint32_t adc_sync_routine_data_read(void); + +#endif /* GD32F4XX_ADC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h new file mode 100644 index 0000000..897dbc1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h @@ -0,0 +1,750 @@ +/*! + \file gd32f4xx_can.h + \brief definitions for the CAN + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_CAN_H +#define GD32F4XX_CAN_H + +#include "gd32f4xx.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive FIFO mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* constants definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum { + /* flags in STAT register */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + /* flags in TSTAT register */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; + +/* CAN interrupt flags */ +typedef enum { + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ + /* interrupt flags in ERR register */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +} can_interrupt_flag_enum; + +/* CAN initiliaze parameters structure */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode disable */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +} can_parameter_struct; + +/* CAN transmit message structure */ +typedef struct { + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +} can_trasnmit_message_struct; + +/* CAN receive message structure */ +typedef struct { + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters structure */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits */ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +} can_filter_parameter_struct; + +/* CAN errors */ +typedef enum { + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +} can_error_enum; + +/* transmit states */ +typedef enum { + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +typedef enum { + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +} can_struct_type_enum; + +/* CAN baudrate prescaler */ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1 */ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2 */ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width */ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode */ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number */ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier */ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier */ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier */ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) + +/* receive mailbox standard identifier */ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive FIFO */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive FIFO */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN structure */ +void can_struct_para_init(can_struct_type_enum type, void *p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +/* CAN filter initialization */ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); + +/* function configuration */ +/* set can1 filter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release FIFO */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error type */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* interrupt & flag functions */ +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F4XX_CAN_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h new file mode 100644 index 0000000..ef4d3ae --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h @@ -0,0 +1,81 @@ +/*! + \file gd32f4xx_crc.h + \brief definitions for the CRC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_CRC_H +#define GD32F4XX_CRC_H + +#include "gd32f4xx.h" + +/* CRC definitions */ +#define CRC CRC_BASE /*!< CRC base address */ + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F4XX_CRC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h new file mode 100644 index 0000000..0542676 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h @@ -0,0 +1,185 @@ +/*! + \file gd32f4xx_ctc.h + \brief definitions for the CTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_CTC_H +#define GD32F4XX_CTC_H + +#include "gd32f4xx.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ +#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ +#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t hardmode); + +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t reload_value); + +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t int_flag); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); + +#endif /* GD32F4XX_CTC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h new file mode 100644 index 0000000..cf0d7da --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h @@ -0,0 +1,271 @@ +/*! + \file gd32f4xx_dac.h + \brief definitions for the DAC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DAC_H +#define GD32F4XX_DAC_H + +#include "gd32f4xx.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* DAC_STAT */ +#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ +#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +/* enable DAC concurrent interrupt */ +void dac_concurrent_interrupt_enable(void); +/* disable DAC concurrent interrupt */ +void dac_concurrent_interrupt_disable(void); + +/* DAC interrupt configuration */ +/* get the specified DAC flag(DAC DMA underrun flag) */ +FlagStatus dac_flag_get(uint32_t dac_periph); +/* clear the specified DAC flag(DAC DMA underrun flag) */ +void dac_flag_clear(uint32_t dac_periph); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); +/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +FlagStatus dac_interrupt_flag_get(uint32_t dac_periph); +/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +void dac_interrupt_flag_clear(uint32_t dac_periph); + +#endif /* GD32F4XX_DAC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h new file mode 100644 index 0000000..bd50df3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h @@ -0,0 +1,153 @@ +/*! + \file gd32f4xx_dbg.h + \brief definitions for the DBG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DBG_H +#define GD32F4XX_DBG_H + +#include "gd32f4xx.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ +#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ +#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ + +/* DBG_CTL1 */ +#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ +#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */ +#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */ + +/* DBG_CTL2 */ +#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */ +#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +enum dbg_reg_idx +{ + DBG_IDX_CTL0 = 0x04U, + DBG_IDX_CTL1 = 0x08U, + DBG_IDX_CTL2 = 0x0CU +}; + +typedef enum +{ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ + DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ + DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ + DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ + DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ +}dbg_periph_enum; + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); + +#endif /* GD32F4XX_DBG_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h new file mode 100644 index 0000000..4dfc811 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h @@ -0,0 +1,239 @@ +/*! + \file gd32f4xx_dci.h + \brief definitions for the DCI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DCI_H +#define GD32F4XX_DCI_H + +#include "gd32f4xx.h" + +/* DCI definitions */ +#define DCI DCI_BASE + +/* registers definitions */ +#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */ +#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */ +#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */ +#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */ +#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */ +#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */ +#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */ +#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */ +#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */ +#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */ +#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */ + +/* bits definitions */ +/* DCI_CTL */ +#define DCI_CTL_CAP BIT(0) /*!< capture enable */ +#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ +#define DCI_CTL_WDEN BIT(2) /*!< window enable */ +#define DCI_CTL_JM BIT(3) /*!< JPEG mode */ +#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ +#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ +#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ +#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ +#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ +#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ +#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ + +/* DCI_STAT0 */ +#define DCI_STAT0_HS BIT(0) /*!< HS line status */ +#define DCI_STAT0_VS BIT(1) /*!< VS line status */ +#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */ + +/* DCI_STAT1 */ +#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */ +#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */ +#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */ +#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */ +#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */ + +/* DCI_INTEN */ +#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */ +#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */ +#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */ +#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */ +#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */ + +/* DCI_INTF */ +#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */ +#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */ + +/* DCI_INTC */ +#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */ +#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */ +#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */ +#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */ +#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */ + +/* DCI_SC */ +#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */ +#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */ +#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */ +#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */ + +/* DCI_SCUNMSK */ +#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */ + +/* DCI_CWSPOS */ +#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */ +#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */ + +/* DCI_CWSZ */ +#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */ +#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ + +/* constants definitions */ +/* DCI parameter structure definitions */ +typedef struct +{ + uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ + uint32_t clock_polarity; /*!< clock polarity selection */ + uint32_t hsync_polarity; /*!< horizontal polarity selection */ + uint32_t vsync_polarity; /*!< vertical polarity selection */ + uint32_t frame_rate; /*!< frame capture rate */ + uint32_t interface_format; /*!< digital camera interface format */ +}dci_parameter_struct; + +#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ +#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ + +#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */ +#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */ + +#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ +#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */ + +#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ +#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) +#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ +#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ +#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ + +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ + +/* DCI interrupt constants definitions */ +#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ +#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ +#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ +#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ +#define DCI_INT_EL BIT(4) /*!< end of line interrupt */ + +/* DCI interrupt flag definitions */ +#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ +#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ + +/* DCI flag definitions */ +#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ +#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ +#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ +#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ +#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ +#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ +#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ +#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ + +/* function declarations */ +/* initialization functions */ +/* DCI deinit */ +void dci_deinit(void); +/* initialize DCI registers */ +void dci_init(dci_parameter_struct* dci_struct); + +/* enable DCI function */ +void dci_enable(void); +/* disable DCI function */ +void dci_disable(void); +/* enable DCI capture */ +void dci_capture_enable(void); +/* disable DCI capture */ +void dci_capture_disable(void); +/* enable DCI jpeg mode */ +void dci_jpeg_enable(void); +/* disable DCI jpeg mode */ +void dci_jpeg_disable(void); + +/* function configuration */ +/* enable cropping window function */ +void dci_crop_window_enable(void); +/* disable cropping window function */ +void dci_crop_window_disable(void); +/* configure DCI cropping window */ +void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); + +/* enable embedded synchronous mode */ +void dci_embedded_sync_enable(void); +/* disable embedded synchronous mode */ +void dci_embedded_sync_disable(void); +/* configure synchronous codes in embedded synchronous mode */ +void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); +/* configure synchronous codes unmask in embedded synchronous mode */ +void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); + +/* read DCI data register */ +uint32_t dci_data_read(void); + +/* interrupt & flag functions */ +/* get specified flag */ +FlagStatus dci_flag_get(uint32_t flag); +/* enable specified DCI interrupt */ +void dci_interrupt_enable(uint32_t interrupt); +/* disable specified DCI interrupt */ +void dci_interrupt_disable(uint32_t interrupt); + + +/* get specified interrupt flag */ +FlagStatus dci_interrupt_flag_get(uint32_t int_flag); +/* clear specified interrupt flag */ +void dci_interrupt_flag_clear(uint32_t int_flag); + +#endif /* GD32F4XX_DCI_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h new file mode 100644 index 0000000..cffbbf8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h @@ -0,0 +1,428 @@ +/*! + \file gd32f4xx_dma.h + \brief definitions for the DMA + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DMA_H +#define GD32F4XX_DMA_H + +#include "gd32f4xx.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */ +#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */ +#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */ +#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */ +#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */ +#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */ +#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */ +#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */ +#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */ +#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */ +#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */ +#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */ +#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */ +#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */ +#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */ +#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */ +#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */ +#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */ + +#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */ +#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */ +#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */ +#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */ +#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */ +#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */ +#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */ +#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */ +#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */ +#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */ + +/* DMA_INTC */ +#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */ +#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */ +#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */ +#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */ +#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */ + +/* DMA_CHxCTL,x=0..7 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */ +#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */ +#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */ +#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */ +#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */ +#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */ +#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */ +#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */ +#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */ +#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */ +#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */ +#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */ +#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */ +#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */ +#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */ + +/* DMA_CHxCNT,x=0..7 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..7 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxM0ADDR,x=0..7 */ +#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ + +/* DMA_CHxM1ADDR,x=0..7 */ +#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ + +/* DMA_CHxFCTL,x=0..7 */ +#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ +#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */ +#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */ +#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel 0 */ + DMA_CH1, /*!< DMA Channel 1 */ + DMA_CH2, /*!< DMA Channel 2 */ + DMA_CH3, /*!< DMA Channel 3 */ + DMA_CH4, /*!< DMA Channel 4 */ + DMA_CH5, /*!< DMA Channel 5 */ + DMA_CH6, /*!< DMA Channel 6 */ + DMA_CH7 /*!< DMA Channel 7 */ +} dma_channel_enum; + +/* DMA peripheral select */ +typedef enum +{ + DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ + DMA_SUBPERI1, /*!< DMA Peripheral 1 */ + DMA_SUBPERI2, /*!< DMA Peripheral 2 */ + DMA_SUBPERI3, /*!< DMA Peripheral 3 */ + DMA_SUBPERI4, /*!< DMA Peripheral 4 */ + DMA_SUBPERI5, /*!< DMA Peripheral 5 */ + DMA_SUBPERI6, /*!< DMA Peripheral 6 */ + DMA_SUBPERI7 /*!< DMA Peripheral 7 */ +} dma_subperipheral_enum; + +/* DMA multidata mode initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t periph_inc; /*!< peripheral increasing mode */ + + uint32_t memory0_addr; /*!< memory 0 base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t memory_inc; /*!< memory increasing mode */ + + uint32_t memory_burst_width; /*!< multi data mode enable */ + uint32_t periph_burst_width; /*!< multi data mode enable */ + uint32_t critical_value; /*!< FIFO critical */ + + uint32_t circular_mode; /*!< DMA circular mode */ + uint32_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +}dma_multi_data_parameter_struct; + +/* DMA singledata mode initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_inc; /*!< peripheral increasing mode */ + + uint32_t memory0_addr; /*!< memory 0 base address */ + uint32_t memory_inc; /*!< memory increasing mode */ + + uint32_t periph_memory_width; /*!< transfer data size of peripheral */ + + uint32_t circular_mode; /*!< DMA circular mode */ + uint32_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +} dma_single_data_parameter_struct; + +#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */ +#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */ +#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* peripheral select */ +#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25)) +#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */ +#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */ +#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */ +#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */ +#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */ +#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */ +#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */ +#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */ + +/* burst type of memory */ +#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23)) +#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */ +#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */ +#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */ +#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */ + +/* burst type of peripheral */ +#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */ +#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */ +#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */ +#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* transfer data width of memory */ +#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */ + +/* transfer data width of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */ +#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */ +#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */ + +/* channel transfer mode */ +#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */ +#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */ + +/* FIFO counter critical value */ +#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */ +#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */ +#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */ +#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */ + +/* memory select */ +#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */ +#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */ + +/* DMA circular mode */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */ + +/* DMA flow controller select */ +#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */ +#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */ + +/* FIFO status */ +#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */ +#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */ +#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */ +#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */ +#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */ +#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ +#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + +/* flag bits */ +#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the DMA single data mode parameters struct with the default values */ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); +/* initialize the DMA multi data mode parameters struct with the default values */ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); +/* DMA single data mode initialize */ +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); +/* DMA multi data mode initialize */ +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA Memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); + +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); + +/* configure transfer burst beats of memory */ +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); +/* configure transfer burst beats of peripheral */ +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); +/* configure transfer data size of memory */ +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); + +/* configure next address increasement algorithm of memory */ +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); +/* configure next address increasement algorithm of peripheral */ +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); + +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); + +/* DMA switch buffer mode config */ +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); +/* DMA using memory get */ +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA channel peripheral select */ +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); +/* DMA flow controller configure */ +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); +/* DMA flow controller enable */ +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); +/* DMA FIFO status get */ +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* check DMA flag is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); + +#endif /* GD32F4XX_DMA_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h new file mode 100644 index 0000000..4363c43 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h @@ -0,0 +1,1681 @@ +/*! + \file gd32f4xx_enet.h + \brief definitions for the ENET + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_ENET_H +#define GD32F4XX_ENET_H + +#include "gd32f4xx.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +//#define SELECT_DESCRIPTORS_ENHANCED_MODE + +//#define USE_DELAY + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ +#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_DBG */ +#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ +#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ +#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ +#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ +#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ +#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ +#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ +#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ +#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ +#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ +#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ +#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ +#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ +#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ + +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ +#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ +#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ +#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ +#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ +#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ +#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ +#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ +#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ +#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ +#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDAND */ +#define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_PTP_TSF */ +#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ +#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ + +/* ENET_PTP_PPSCTL */ +#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ +#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ + +/* ENET_DMA_RSWDC */ +#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Tx descriptor TDES6 */ +#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES7 */ +#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Rx descriptor RDES4 */ +#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ +#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ +#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ +#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ +#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ +#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ +#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ +#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ +#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ + +/* ENET DMA Rx descriptor RDES6 */ +#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ + +/* ENET DMA Rx descriptor RDES7 */ +#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ + +#define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ + +#define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum +{ + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_PTP_TSF register */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum +{ + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +}enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum +{ + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum +{ + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +}enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum +{ + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +}enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum +{ + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +}enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum +{ + ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +}enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum +{ + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +}enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum +{ + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +}enet_frmrecept_enum; + +/* register group value get */ +typedef enum +{ + ALL_MAC_REG = 0U, /*!< MAC register group */ + ALL_MSC_REG = 22U, /*!< MSC register group */ + ALL_PTP_REG = 33U, /*!< PTP register group */ + ALL_DMA_REG = 44U, /*!< DMA register group */ +}enet_registers_type_enum; + +/* dma direction select */ +typedef enum +{ + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +}enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum +{ + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +}enet_phydirection_enum; + +/* register operation direction select */ +typedef enum +{ + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +}enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum +{ + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +}enet_macaddress_enum; + +/* descriptor information */ +typedef enum +{ + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +}enet_descstate_enum; + +/* MSC counters preset mode */ +typedef enum +{ + ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ + ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ + ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ +}enet_msc_preset_enum; + +typedef enum{ + ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ + ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ + ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ + ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ + ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ + ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ + ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ + ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ + ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ + ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ + ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ + ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ +}enet_ptp_function_enum; + +/* structure for initialization of the ENET */ +typedef struct +{ + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +}enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct +{ + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + uint32_t extended_status; /*!< extended status */ + uint32_t reserved; /*!< reserved */ + uint32_t timestamp_low; /*!< timestamp low */ + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct +{ + uint32_t second; /*!< second of system time */ + uint32_t subsecond; /*!< subsecond of system time */ + uint32_t sign; /*!< sign of system time */ +}enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_dbg register value */ +#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ +#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ +#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ +#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ +#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ +#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ +#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ +#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ +#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ +#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ + +#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ + +#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ + +#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ + +#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ + +#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0)) << 8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4)) << 8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ +#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ +#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ +#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ +#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ +#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* ptp_ppsctl register value */ +#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ +#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ +#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ +#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ +#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ +#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ +#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ +#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ +#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ +#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ +#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ +#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ +#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ +#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ +#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ +#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ +#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ +#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ +#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma_rswdc register value */ +#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ +#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ +#else +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + + + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* get the enet debug status from the debug register */ +uint32_t enet_debug_status_get(uint32_t mac_debug); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + + +/* special enhanced mode function */ +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* get the bit of extended status flag in ENET DMA descriptor */ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); +/* configure descriptor to work in enhanced mode */ +void enet_desc_select_enhanced_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); +/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) + +#else + +/* configure descriptor to work in normal mode */ +void enet_desc_select_normal_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* configure MAC statistics counters preset mode */ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure the PPS output frequency */ +void enet_ptp_pps_output_frequency_config(uint32_t freq); + + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); + + +#endif /* GD32F4XX_ENET_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h new file mode 100644 index 0000000..4b05227 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h @@ -0,0 +1,814 @@ +/*! + \file gd32f4xx_exmc.h + \brief definitions for the EXMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_EXMC_H +#define GD32F4XX_EXMC_H + +#include "gd32f4xx.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ +#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ +#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ +#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ +#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ + +/* SDRAM */ +#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ +#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ + +#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ +#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ + +#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ +#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ +#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ +#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ + +/* SQPI PSRAM */ +#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ +#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ +#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ +#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ +#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ + +/* bits definitions */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1..2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* EXMC_SDCTLx,x=0..1 */ +#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ +#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ +#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ +#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ +#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ +#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ +#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ +#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ +#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ + +/* EXMC_SDTCFGx,x=0..1 */ +#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ +#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ +#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ +#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ +#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ +#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ +#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ + +/* EXMC_SDCMD */ +#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ +#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ +#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ +#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ +#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ + +/* EXMC_SDARI */ +#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ +#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ +#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */ + +/* EXMC_SDSTAT */ +#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ +#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ +#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ +#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ + +/* EXMC_SDRSCTL */ +#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ +#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ +#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ + +/* EXMC_SINIT */ +#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ +#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ +#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ +#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ + +/* EXMC_SRCMD */ +#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ +#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ +#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ +#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ + +/* EXMC_SWCMD */ +#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ +#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ +#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ + +/* EXMC_SIDL */ +#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ + +/* EXMC_SIDH */ +#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize structure */ +typedef struct +{ + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize structure */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + parameters for read if the extendedmode is used. */ + exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ +}exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize structure */ +typedef struct +{ + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +}exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize structure */ +typedef struct +{ + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +}exmc_nand_parameter_struct; + +/* EXMC PC card initialize structure */ +typedef struct +{ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ +}exmc_pccard_parameter_struct; + +/* EXMC SDRAM timing initialize structure */ +typedef struct +{ + uint32_t row_to_column_delay; /*!< configure the row to column delay */ + uint32_t row_precharge_delay; /*!< configure the row precharge delay */ + uint32_t write_recovery_delay; /*!< configure the write recovery delay */ + uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ + uint32_t row_address_select_delay; /*!< configure the row address select delay */ + uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ + uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ +}exmc_sdram_timing_parameter_struct; + +/* EXMC SDRAM initialize structure */ +typedef struct +{ + uint32_t sdram_device; /*!< device of SDRAM */ + uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ + uint32_t burst_read_switch; /*!< enable or disable the burst read */ + uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ + uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ + uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ + uint32_t internal_bank_number; /*!< the number of internal bank */ + uint32_t data_width; /*!< the databus width of SDRAM memory */ + uint32_t row_address_width; /*!< the bit width of a row address */ + uint32_t column_address_width; /*!< the bit width of a column address */ + exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ +}exmc_sdram_parameter_struct; + +/* EXMC SDRAM command initialize structure */ +typedef struct +{ + uint32_t mode_register_content; /*!< the SDRAM mode register content */ + uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */ + uint32_t bank_select; /*!< the bank which command will be sent to */ + uint32_t command; /*!< the commands that will be sent to SDRAM */ +}exmc_sdram_command_parameter_struct; + +/* EXMC SQPISRAM initialize structure */ +typedef struct{ + uint32_t sample_polarity; /*!< read data sample polarity */ + uint32_t id_length; /*!< SPI PSRAM ID length */ + uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */ + uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ +}exmc_sqpipsram_parameter_struct; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ + +#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ +#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ + +/* CRAM page size */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ + +/* SDRAM pipeline delay */ +#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ + +/* SDRAM clock configuration */ +#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) +#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ +#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ +#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ + +/* CAS latency */ +#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) +#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ +#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ +#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ + +/* SDRAM data bus width */ +#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ + +/* SDRAM row address bit width */ +#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ + +/* SDRAM column address bit width */ +#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ +#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ +#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ +#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ + +/* SDRAM number of successive auto-refresh */ +#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ +#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ + +/* SDRAM command selection */ +#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ +#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ +#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ +#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ +#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ +#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ +#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ + +/* SDRAM the delayed sample clock of read data */ +#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ +#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ +#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ +#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ +#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ +#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ +#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ +#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ +#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ +#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ +#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ +#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ +#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ +#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ +#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ +#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ + +/* SPI PSRAM ID length */ +#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) +#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ + +/* SPI PSRAM bit number of address phase */ +#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) +#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ + +/* SPI PSRAM bit number of command phase */ +#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ + +/* SPI PSRAM read command mode */ +#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ + +/* SPI PSRAM write command mode */ +#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC consecutive clock */ +#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ +#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ + +/* EXMC SDRAM bank definition */ +#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ +#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ + +/* EXMC SDRAM internal banks */ +#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ +#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ + +/* SDRAM device0 selection */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */ + +/* SDRAM device1 selection */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */ + +/* SDRAM device status */ +#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ +#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ +#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ + +/* sample cycle of read data */ +#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ + +/* read data sample polarity */ +#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ +#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ + +/* SQPI SRAM command flag */ +#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ +#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ +#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ +#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ +#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ + +/* function declarations */ +/* initialization functions */ +/* NOR/SRAM */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* enable EXMC NOR/SRAM region */ +void exmc_norsram_enable(uint32_t exmc_norsram_region); +/* disable EXMC NOR/SRAM region */ +void exmc_norsram_disable(uint32_t exmc_norsram_region); +/* NAND */ +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize exmc_nand_parameter_struct with the default values */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* enable EXMC NAND bank */ +void exmc_nand_enable(uint32_t exmc_nand_bank); +/* disable EXMC NAND bank */ +void exmc_nand_disable(uint32_t exmc_nand_bank); +/* PC card */ +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize exmc_pccard_parameter_struct with the default values */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* enable EXMC PC card bank */ +void exmc_pccard_enable(void); +/* disable EXMC PC card bank */ +void exmc_pccard_disable(void); +/* SDRAM */ +/* deinitialize EXMC SDRAM device */ +void exmc_sdram_deinit(uint32_t exmc_sdram_device); +/* initialize exmc_sdram_parameter_struct with the default values */ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize EXMC SDRAM device */ +void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); +/* SQPIPSRAM */ +/* deinitialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_deinit(void); +/* initialize exmc_sqpipsram_parameter_struct with the default values */ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* initialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); + +/* function configuration */ +/* NOR/SRAM */ +/* configure consecutive clock */ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); +/* configure CRAM page size */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* NAND */ +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); +/* SDRAM */ +/* enable or disable read sample */ +void exmc_sdram_readsample_enable(ControlStatus newvalue); +/* configure the delayed sample clock of read data */ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); +/* configure the SDRAM memory command */ +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); +/* set auto-refresh interval */ +void exmc_sdram_refresh_count_set(uint32_t exmc_count); +/* set the number of successive auto-refresh command */ +void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); +/* configure the write protection function */ +void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); +/* get the status of SDRAM device0 or device1 */ +uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); +/* SQPIPSRAM */ +/* set the read command */ +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); +/* set the write command */ +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code); +/* send SPI read ID command */ +void exmc_sqpipsram_read_id_command_send(void); +/* send SPI special command which does not have address and data phase */ +void exmc_sqpipsram_write_cmd_send(void); +/* get the EXMC SPI ID low data */ +uint32_t exmc_sqpipsram_low_id_get(void); +/* get the EXMC SPI ID high data */ +uint32_t exmc_sqpipsram_high_id_get(void); +/* get the bit value of EXMC send write command bit or read ID command */ +FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); + +/* interrupt & flag functions */ +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); +/* get EXMC flag status */ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); +/* clear EXMC flag status */ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); +/* get EXMC interrupt flag */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); +/* clear EXMC interrupt flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); + +#endif /* GD32F4XX_EXMC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h new file mode 100644 index 0000000..08a7dc7 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h @@ -0,0 +1,277 @@ +/*! + \file gd32f4xx_exti.h + \brief definitions for the EXTI + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_EXTI_H +#define GD32F4XX_EXTI_H + +#include "gd32f4xx.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ +#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ +#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ +#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< none EXTI edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); +/* EXTI software interrupt event enable */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* EXTI software interrupt event disable */ +void exti_software_interrupt_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32F4XX_EXTI_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h new file mode 100644 index 0000000..aca5a7d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h @@ -0,0 +1,415 @@ +/*! + \file gd32f4xx_fmc.h + \brief definitions for the FMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2020-12-20, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_FMC_H +#define GD32F4XX_FMC_H + +#include "gd32f4xx.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option byte base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */ +#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */ +#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */ +#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ + +#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ +#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ +#define OB_SPC REG32((OB) + 0x00010001U) /*!< option byte security protection value */ +#define OB_WP0 REG32((OB) + 0x00010008U) /*!< option byte write protection 0 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WC_WSCNT BITS(0,3) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte key bits */ + +/* FMC_STAT */ +#define FMC_STAT_END BIT(0) /*!< end of operation flag bit */ +#define FMC_STAT_OPERR BIT(1) /*!< flash operation error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< erase/Program protection error flag bit */ +#define FMC_STAT_PGMERR BIT(6) /*!< program size not match error flag bit */ +#define FMC_STAT_PGSERR BIT(7) /*!< program sequence error flag bit */ +#define FMC_STAT_RDDERR BIT(8) /*!< read D-bus protection error flag bit */ +#define FMC_STAT_BUSY BIT(16) /*!< flash busy flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_SER BIT(1) /*!< main flash sector erase command bit */ +#define FMC_CTL_MER0 BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL_SN BITS(3,7) /*!< select which sector number to be erased */ +#define FMC_CTL_PSZ BITS(8,9) /*!< program size bit */ +#define FMC_CTL_MER1 BIT(15) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL_START BIT(16) /*!< send erase command to FMC bit */ +#define FMC_CTL_ENDIE BIT(24) /*!< end of operation interrupt enable bit */ +#define FMC_CTL_ERRIE BIT(25) /*!< error interrupt enable bit */ +#define FMC_CTL_LK BIT(31) /*!< FMC_CTL lock bit */ + +/* FMC_OBCTL0 */ +#define FMC_OBCTL0_OB_LK BIT(0) /*!< FMC_OBCTL0 lock bit */ +#define FMC_OBCTL0_OB_START BIT(1) /*!< send option byte change command to FMC bit */ +#define FMC_OBCTL0_BOR_TH BITS(2,3) /*!< option byte BOR threshold value */ +#define FMC_OBCTL0_BB BIT(4) /*!< option byte boot bank value */ +#define FMC_OBCTL0_NWDG_HW BIT(5) /*!< option byte watchdog value */ +#define FMC_OBCTL0_NRST_DPSLP BIT(6) /*!< option byte deepsleep reset value */ +#define FMC_OBCTL0_NRST_STDBY BIT(7) /*!< option byte standby reset value */ +#define FMC_OBCTL0_SPC BITS(8,15) /*!< option byte Security Protection code */ +#define FMC_OBCTL0_WP0 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ +#define FMC_OBCTL0_DBS BIT(30) /*!< double banks or single bank selection when flash size is 1M bytes */ +#define FMC_OBCTL0_DRP BIT(31) /*!< D-bus read protection bit */ + +/* FMC_OBCTL1 */ +#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ + +/* FMC_PECFG */ +#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */ +#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */ + +/* FMC_PEKEY */ +#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_RDDERR, /*!< read D-bus protection error */ + FMC_PGSERR, /*!< program sequence error */ + FMC_PGMERR, /*!< program size not match error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_OPERR, /*!< operation error */ + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ +#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */ + +#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ +#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ + +/* option byte write protection */ +#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ +#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ + +/* FMC wait state counter */ +#define WC_WSCNT(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WC_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WC_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WC_WSCNT(2) /*!< FMC 2 wait */ +#define WS_WSCNT_3 WC_WSCNT(3) /*!< FMC 3 wait */ +#define WS_WSCNT_4 WC_WSCNT(4) /*!< FMC 4 wait */ +#define WS_WSCNT_5 WC_WSCNT(5) /*!< FMC 5 wait */ +#define WS_WSCNT_6 WC_WSCNT(6) /*!< FMC 6 wait */ +#define WS_WSCNT_7 WC_WSCNT(7) /*!< FMC 7 wait */ +#define WS_WSCNT_8 WC_WSCNT(8) /*!< FMC 8 wait */ +#define WS_WSCNT_9 WC_WSCNT(9) /*!< FMC 9 wait */ +#define WS_WSCNT_10 WC_WSCNT(10) /*!< FMC 10 wait */ +#define WS_WSCNT_11 WC_WSCNT(11) /*!< FMC 11 wait */ +#define WS_WSCNT_12 WC_WSCNT(12) /*!< FMC 12 wait */ +#define WS_WSCNT_13 WC_WSCNT(13) /*!< FMC 13 wait */ +#define WS_WSCNT_14 WC_WSCNT(14) /*!< FMC 14 wait */ +#define WS_WSCNT_15 WC_WSCNT(15) /*!< FMC 15 wait */ + +/* option byte BOR threshold value */ +#define OBCTL0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval))<< 2) +#define OB_BOR_TH_VALUE3 OBCTL0_BOR_TH(0) /*!< BOR threshold value 3 */ +#define OB_BOR_TH_VALUE2 OBCTL0_BOR_TH(1) /*!< BOR threshold value 2 */ +#define OB_BOR_TH_VALUE1 OBCTL0_BOR_TH(2) /*!< BOR threshold value 1 */ +#define OB_BOR_TH_OFF OBCTL0_BOR_TH(3) /*!< no BOR function */ + +/* option byte boot bank value */ +#define OBCTL0_BB(regval) (BIT(4) & ((uint32_t)(regval)<<4)) +#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ +#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ + +/* option byte software/hardware free watch dog timer */ +#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) +#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ +#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ + +/* option byte reset or not entering deep sleep mode */ +#define OBCTL0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval))<< 6) +#define OB_DEEPSLEEP_NRST OBCTL0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST OBCTL0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */ + +/* option byte reset or not entering standby mode */ +#define OBCTL0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval))<< 7) +#define OB_STDBY_NRST OBCTL0_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST OBCTL0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xAAU) /*!< no security protection */ +#define FMC_LSPC ((uint8_t)0xABU) /*!< low security protection */ +#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */ +#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */ + +/* option bytes D-bus read protection */ +#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */ +#define OB_DRP_1 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 1 */ +#define OB_DRP_2 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 2 */ +#define OB_DRP_3 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 3 */ +#define OB_DRP_4 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 4 */ +#define OB_DRP_5 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 5 */ +#define OB_DRP_6 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 6 */ +#define OB_DRP_7 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 7 */ +#define OB_DRP_8 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 8 */ +#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */ +#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */ +#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */ +#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */ +#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */ +#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */ +#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */ +#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */ +#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */ +#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */ +#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */ +#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */ +#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ +#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ +#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ +#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */ + +/* double banks or single bank selection when flash size is 1M bytes */ +#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U)) +#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ +#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ + +/* option bytes D-bus read protection mode */ +#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U)) +#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ +#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ + +/* FMC sectors */ +#define CTL_SN(regval) (BITS(3,7) & ((uint32_t)(regval))<< 3) +#define CTL_SECTOR_NUMBER_0 CTL_SN(0) /*!< sector 0 */ +#define CTL_SECTOR_NUMBER_1 CTL_SN(1) /*!< sector 1 */ +#define CTL_SECTOR_NUMBER_2 CTL_SN(2) /*!< sector 2 */ +#define CTL_SECTOR_NUMBER_3 CTL_SN(3) /*!< sector 3 */ +#define CTL_SECTOR_NUMBER_4 CTL_SN(4) /*!< sector 4 */ +#define CTL_SECTOR_NUMBER_5 CTL_SN(5) /*!< sector 5 */ +#define CTL_SECTOR_NUMBER_6 CTL_SN(6) /*!< sector 6 */ +#define CTL_SECTOR_NUMBER_7 CTL_SN(7) /*!< sector 7 */ +#define CTL_SECTOR_NUMBER_8 CTL_SN(8) /*!< sector 8 */ +#define CTL_SECTOR_NUMBER_9 CTL_SN(9) /*!< sector 9 */ +#define CTL_SECTOR_NUMBER_10 CTL_SN(10) /*!< sector 10 */ +#define CTL_SECTOR_NUMBER_11 CTL_SN(11) /*!< sector 11 */ +#define CTL_SECTOR_NUMBER_24 CTL_SN(12) /*!< sector 24 */ +#define CTL_SECTOR_NUMBER_25 CTL_SN(13) /*!< sector 25 */ +#define CTL_SECTOR_NUMBER_26 CTL_SN(14) /*!< sector 26 */ +#define CTL_SECTOR_NUMBER_27 CTL_SN(15) /*!< sector 27 */ +#define CTL_SECTOR_NUMBER_12 CTL_SN(16) /*!< sector 12 */ +#define CTL_SECTOR_NUMBER_13 CTL_SN(17) /*!< sector 13 */ +#define CTL_SECTOR_NUMBER_14 CTL_SN(18) /*!< sector 14 */ +#define CTL_SECTOR_NUMBER_15 CTL_SN(19) /*!< sector 15 */ +#define CTL_SECTOR_NUMBER_16 CTL_SN(20) /*!< sector 16 */ +#define CTL_SECTOR_NUMBER_17 CTL_SN(21) /*!< sector 17 */ +#define CTL_SECTOR_NUMBER_18 CTL_SN(22) /*!< sector 18 */ +#define CTL_SECTOR_NUMBER_19 CTL_SN(23) /*!< sector 19 */ +#define CTL_SECTOR_NUMBER_20 CTL_SN(24) /*!< sector 20 */ +#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */ +#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */ +#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ + + +/* FMC program size */ +#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U) +#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ +#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ +#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ + +/* FMC interrupt enable */ +#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ +#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ + +/* FMC flags */ +#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */ +#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */ +#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */ +#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */ +#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ + +/* FMC interrupt flags */ +#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */ +#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */ +#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */ +#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */ +#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */ +#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */ + + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_addr); +#endif +/* FMC erase sector */ +fmc_state_enum fmc_sector_erase(uint32_t fmc_sector); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); +/* FMC program a byte at the corresponding address */ +fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* send option byte change command */ +void ob_start(void); +/* erase option byte */ +void ob_erase(void); +/* enable write protect */ +ErrStatus ob_write_protection_enable(uint32_t ob_wp); +/* disable write protect */ +ErrStatus ob_write_protection_disable(uint32_t ob_wp); +/* enable erase/program protection and D-bus read protection */ +void ob_drp_enable(uint32_t ob_drp); +/* disable erase/program protection and D-bus read protection */ +void ob_drp_disable(void); +/* configure security protection level */ +void ob_security_protection_config(uint8_t ob_spc); +/* program the FMC user option byte */ +void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); +/* program the option byte BOR threshold value */ +void ob_user_bor_threshold(uint32_t ob_bor_th); +/* configure the boot mode */ +void ob_boot_mode_config(uint32_t boot_mode); +/* get the FMC user option byte */ +uint8_t ob_user_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection0_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection1_get(void); +/* get the FMC erase/program protection and D-bus read protection option bytes value */ +uint16_t ob_drp0_get(void); +/* get the FMC erase/program protection and D-bus read protection option bytes value */ +uint16_t ob_drp1_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); +/* get the FMC option byte BOR threshold value */ +uint8_t ob_user_bor_threshold_get(void); + +/* FMC interrupts and flags management functions */ +/* get flag set or reset */ +FlagStatus fmc_flag_get(uint32_t fmc_flag); +/* clear the FMC pending flag */ +void fmc_flag_clear(uint32_t fmc_flag); +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t fmc_int); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t fmc_int); +/* get FMC interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag); +/* clear the FMC interrupt flag */ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag); +/* get the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check whether FMC is ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); + +#endif /* GD32F4XX_FMC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h new file mode 100644 index 0000000..af0a897 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h @@ -0,0 +1,114 @@ +/*! + \file gd32f4xx_fwdgt.h + \brief definitions for the FWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_FWDGT_H +#define GD32F4XX_FWDGT_H + +#include "gd32f4xx.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F4XX_FWDGT_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h new file mode 100644 index 0000000..5a69385 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h @@ -0,0 +1,409 @@ +/*! + \file gd32f4xx_gpio.h + \brief definitions for the GPIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_GPIO_H +#define GD32F4XX_GPIO_H + +#include "gd32f4xx.h" + +/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) +#define GPIOH (GPIO_BASE + 0x00001C00U) +#define GPIOI (GPIO_BASE + 0x00002000U) + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ +#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD */ +#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/ pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) + +/* GPIO pull-up/ pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed level */ +#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ +#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ +#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ +#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ +#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ +#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ +#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ +#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ +#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */ +#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */ +#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */ +#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */ +#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */ +#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32F4XX_GPIO_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h new file mode 100644 index 0000000..2a1a88a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h @@ -0,0 +1,413 @@ +/*! + \file gd32f4xx_i2c.h + \brief definitions for the I2C + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_I2C_H +#define GD32F4XX_I2C_H + +#include "gd32f4xx.h" + +/* I2Cx(x=0,1,2) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */ +#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* I2Cx_FCTL */ +#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ +#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ + +/* I2Cx_SAMCS */ +#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ +#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ +#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ +#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ +#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ +#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ +#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ +#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + /* flags in SAMCS register */ + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ + /* interrupt flags in SAMCS register */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ + /* interrupt in SAMCS register */ + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ +} i2c_interrupt_enum; + +/* the digital noise filter can filter spikes's length */ +typedef enum { + I2C_DF_DISABLE = 0, /*!< disable digital noise filter */ + I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ + I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ + I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ + I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ + I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ + I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ + I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ + I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ + I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ + I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ + I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ + I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ + I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ + I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ + I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ +} i2c_digital_filter_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ + +/* PEC transfer */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ + +/* function declarations */ +/* initialization functions */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); + +/* application function declarations */ +/* select SMBus type */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* configure software reset of I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); +/* disable analog noise filter */ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph); +/* enable analog noise filter */ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph); +/* configure digital noise filter */ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara); +/* enable SAM_V interface */ +void i2c_sam_enable(uint32_t i2c_periph); +/* disable SAM_V interface */ +void i2c_sam_disable(uint32_t i2c_periph); +/* enable SAM_V interface timeout detect */ +void i2c_sam_timeout_enable(uint32_t i2c_periph); +/* disable SAM_V interface timeout detect */ +void i2c_sam_timeout_disable(uint32_t i2c_periph); + +/* interrupt & flag functions */ +/* get I2C flag status */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag status */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* get I2C interrupt flag status */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag status */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32F4XX_I2C_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h new file mode 100644 index 0000000..22e77d1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h @@ -0,0 +1,381 @@ +/*! + \file gd32f4xx_ipa.h + \brief definitions for the IPA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_IPA_H +#define GD32F4XX_IPA_H + +#include "gd32f4xx.h" + +/* TLI definitions */ +#define IPA IPA_BASE /*!< IPA base address */ + +/* bits definitions */ +/* registers definitions */ +#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */ +#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */ +#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */ +#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */ +#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */ +#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */ +#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */ +#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */ +#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */ +#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */ +#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */ +#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */ +#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */ +#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */ +#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */ +#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */ +#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */ +#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */ +#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */ +#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */ + +/* IPA_CTL */ +#define IPA_CTL_TEN BIT(0) /*!< transfer enable */ +#define IPA_CTL_THU BIT(1) /*!< transfer hang up */ +#define IPA_CTL_TST BIT(2) /*!< transfer stop */ +#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */ +#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */ +#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */ +#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */ +#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */ +#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */ +#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */ + +/* IPA_INTF */ +#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */ +#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */ +#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */ +#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */ +#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */ +#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */ + +/* IPA_INTC */ +#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */ +#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */ +#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */ +#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */ +#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */ +#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */ + +/* IPA_FMADDR */ +#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */ + +/* IPA_FLOFF */ +#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */ + +/* IPA_BMADDR */ +#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */ + +/* IPA_BLOFF */ +#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */ + +/* IPA_FPCTL */ +#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */ +#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */ +#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */ +#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */ +#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */ +#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */ + +/* IPA_FPV */ +#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */ +#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */ +#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */ + +/* IPA_BPCTL */ +#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */ +#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */ +#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */ +#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */ +#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */ +#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */ + +/* IPA_BPV */ +#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */ +#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */ +#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */ + +/* IPA_FLMADDR */ +#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */ + +/* IPA_BLMADDR */ +#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */ + +/* IPA_DPCTL */ +#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ + +/* IPA_DPV */ +/* destination pixel format ARGB8888 */ +#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */ + +/* destination pixel format RGB8888 */ +#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */ + +/* destination pixel format RGB565 */ +#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */ + +/* destination pixel format ARGB1555 */ +#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */ + +/* destination pixel format ARGB4444 */ +#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */ + +/* IPA_DMADDR */ +#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */ + +/* IPA_DLOFF */ +#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */ + +/* IPA_IMS */ +#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */ +#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */ + +/* IPA_LM */ +#define IPA_LM_LM BITS(0,15) /*!< line mark */ + +/* IPA_ITCTL */ +#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */ +#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */ + + +/* constants definitions */ +/* IPA foreground parameter struct definitions */ +typedef struct { + uint32_t foreground_memaddr; /*!< foreground memory base address */ + uint32_t foreground_lineoff; /*!< foreground line offset */ + uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ + uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */ + uint32_t foreground_pf; /*!< foreground pixel format */ + uint32_t foreground_prered; /*!< foreground pre-defined red value */ + uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ + uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ +} ipa_foreground_parameter_struct; + +/* IPA background parameter struct definitions */ +typedef struct { + uint32_t background_memaddr; /*!< background memory base address */ + uint32_t background_lineoff; /*!< background line offset */ + uint32_t background_prealpha; /*!< background pre-defined alpha value */ + uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ + uint32_t background_pf; /*!< background pixel format */ + uint32_t background_prered; /*!< background pre-defined red value */ + uint32_t background_pregreen; /*!< background pre-defined green value */ + uint32_t background_preblue; /*!< background pre-defined blue value */ +} ipa_background_parameter_struct; + +/* IPA destination parameter struct definitions */ +typedef struct { + uint32_t destination_memaddr; /*!< destination memory base address */ + uint32_t destination_lineoff; /*!< destination line offset */ + uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ + uint32_t destination_pf; /*!< destination pixel format */ + uint32_t destination_prered; /*!< destination pre-defined red value */ + uint32_t destination_pregreen; /*!< destination pre-defined green value */ + uint32_t destination_preblue; /*!< destination pre-defined blue value */ + uint32_t image_width; /*!< width of the image to be processed */ + uint32_t image_height; /*!< height of the image to be processed */ +} ipa_destination_parameter_struct; + +/* destination pixel format */ +typedef enum { + IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ + IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ + IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ + IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ + IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ +} ipa_dpf_enum; + +/* LUT pixel format */ +#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */ +#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */ + +/* Inter-timer */ +#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */ +#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */ + +/* IPA pixel format convert mode */ +#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */ +#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */ +#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */ +#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */ + +/* foreground alpha value calculation algorithm */ +#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */ +#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */ +#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */ + +/* background alpha value calculation algorithm */ +#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */ +#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */ +#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */ + +/* foreground pixel format */ +#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */ +#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */ +#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */ +#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */ +#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */ +#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */ +#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */ +#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */ +#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */ +#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */ +#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */ + +/* background pixel format */ +#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */ +#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */ +#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */ +#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */ +#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */ +#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */ +#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */ +#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */ +#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */ +#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */ +#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */ + +/* IPA flags */ +#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* IPA interrupt enable or disable */ +#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */ +#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */ +#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */ +#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */ +#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */ +#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */ + +/* IPA interrupt flags */ +#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* function declarations */ +/* functions enable or disable, pixel format convert mode set */ +/* deinitialize IPA */ +void ipa_deinit(void); +/* enable IPA transfer */ +void ipa_transfer_enable(void); +/* enable IPA transfer hang up */ +void ipa_transfer_hangup_enable(void); +/* disable IPA transfer hang up */ +void ipa_transfer_hangup_disable(void); +/* enable IPA transfer stop */ +void ipa_transfer_stop_enable(void); +/* disable IPA transfer stop */ +void ipa_transfer_stop_disable(void); +/* enable IPA foreground LUT loading */ +void ipa_foreground_lut_loading_enable(void); +/* enable IPA background LUT loading */ +void ipa_background_lut_loading_enable(void); +/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm); + +/* structure initialization, foreground, background, destination and LUT initialization */ +/* initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct); +/* initialize foreground parameters */ +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct); +/* initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined */ +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct); +/* initialize background parameters */ +void ipa_background_init(ipa_background_parameter_struct *background_struct); +/* initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined */ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct); +/* initialize destination parameters */ +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct); +/* initialize IPA foreground LUT parameters */ +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); +/* initialize IPA background LUT parameters */ +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr); + +/* configuration functions */ +/* configure IPA line mark */ +void ipa_line_mark_config(uint16_t line_num); +/* inter-timer enable or disable */ +void ipa_inter_timer_config(uint8_t timer_cfg); +/* configure the number of clock cycles interval */ +void ipa_interval_clock_num_config(uint8_t clk_num); + +/* flag and interrupt functions */ +/* get IPA flag status in IPA_INTF register */ +FlagStatus ipa_flag_get(uint32_t flag); +/* clear IPA flag in IPA_INTF register */ +void ipa_flag_clear(uint32_t flag); +/* enable IPA interrupt */ +void ipa_interrupt_enable(uint32_t int_flag); +/* disable IPA interrupt */ +void ipa_interrupt_disable(uint32_t int_flag); +/* get IPA interrupt flag */ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag); +/* clear IPA interrupt flag */ +void ipa_interrupt_flag_clear(uint32_t int_flag); + +#endif /* GD32F4XX_IPA_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h new file mode 100644 index 0000000..1b297a0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h @@ -0,0 +1,187 @@ +/*! + \file gd32f4xx_iref.h + \brief definitions for the IREF + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_IREF_H +#define GD32F4XX_IREF_H + +#include "gd32f4xx.h" + +/* IREF definitions */ +#define IREF IREF_BASE /*!< IREF base address */ + +/* registers definitions */ +#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */ + +/* bits definitions */ +/* IREF_CTL */ +#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ +#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ +#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ +#define IREF_CTL_SSEL BIT(14) /*!< step selection */ +#define IREF_CTL_CREN BIT(15) /*!< current reference enable */ + +/* constants definitions */ +/* IREF current precision trim */ +#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) +#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */ +#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */ +#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */ +#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */ +#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */ +#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */ +#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */ +#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */ +#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */ +#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */ +#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */ +#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */ +#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */ +#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */ +#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */ +#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */ +#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */ +#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */ +#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */ +#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */ +#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */ +#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */ +#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */ +#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */ +#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */ +#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */ +#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */ +#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */ +#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */ +#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */ +#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */ +#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */ + +/* IREF current step */ +#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) +#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */ +#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */ +#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */ +#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */ +#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */ +#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */ +#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */ +#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */ +#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */ +#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */ +#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */ +#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */ +#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */ +#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */ +#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */ +#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */ +#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */ +#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */ +#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */ +#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */ +#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */ +#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */ +#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */ +#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */ +#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */ +#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */ +#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */ +#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */ +#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */ +#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */ +#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */ +#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */ +#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */ +#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */ +#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */ +#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */ +#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */ +#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */ +#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */ +#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */ +#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */ +#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */ +#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */ +#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */ +#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */ +#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */ +#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */ +#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */ +#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */ +#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */ +#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */ +#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */ +#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */ +#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */ +#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */ +#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */ +#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */ +#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */ +#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ +#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ +#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ + +/* IREF mode selection */ +#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) +#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ +#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ + +/* IREF sink current mode*/ +#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ +#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ + +/* function declarations */ +/* deinitialize IREF */ +void iref_deinit(void); +/* enable IREF */ +void iref_enable(void); +/* disable IREF */ +void iref_disable(void); + +/* set IREF mode*/ +void iref_mode_set(uint32_t step); +/* set IREF sink current mode*/ +void iref_sink_set(uint32_t sinkmode); +/* set IREF current precision trim value */ +void iref_precision_trim_value_set(uint32_t precisiontrim); +/* set IREF step data*/ +void iref_step_data_config(uint32_t stepdata); + +#endif /* GD32F4XX_IREF_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h new file mode 100644 index 0000000..8624095 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h @@ -0,0 +1,81 @@ +/*! + \file gd32f4xx_libopt.h + \brief library optional for gd32f4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_LIBOPT_H +#define GD32F4XX_LIBOPT_H + +#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407) || defined (GD32F470) || defined (GD32F425) || defined (GD32F427) +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_adc.h" +#include "gd32f4xx_can.h" +#include "gd32f4xx_crc.h" +#include "gd32f4xx_ctc.h" +#include "gd32f4xx_dac.h" +#include "gd32f4xx_dbg.h" +#include "gd32f4xx_dci.h" +#include "gd32f4xx_dma.h" +#include "gd32f4xx_exti.h" +#include "gd32f4xx_fmc.h" +#include "gd32f4xx_fwdgt.h" +#include "gd32f4xx_gpio.h" +#include "gd32f4xx_syscfg.h" +#include "gd32f4xx_i2c.h" +#include "gd32f4xx_iref.h" +#include "gd32f4xx_pmu.h" +#include "gd32f4xx_rtc.h" +#include "gd32f4xx_sdio.h" +#include "gd32f4xx_spi.h" +#include "gd32f4xx_timer.h" +#include "gd32f4xx_trng.h" +#include "gd32f4xx_usart.h" +#include "gd32f4xx_wwdgt.h" +#include "gd32f4xx_misc.h" +#endif + +#if defined (GD32F450) || defined (GD32F470) +#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#include "gd32f4xx_ipa.h" +#include "gd32f4xx_tli.h" +#endif + +#if defined (GD32F407) || defined (GD32F427) +#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#endif + +#endif /* GD32F4XX_LIBOPT_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h new file mode 100644 index 0000000..278cca6 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h @@ -0,0 +1,93 @@ +/*! + \file gd32f4xx_misc.h + \brief definitions for the MISC + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_MISC_H +#define GD32F4XX_MISC_H + +#include "gd32f4xx.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F4XX_MISC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h new file mode 100644 index 0000000..375dbf0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h @@ -0,0 +1,206 @@ +/*! + \file gd32f4xx_pmu.h + \brief definitions for the PMU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_PMU_H +#define GD32F4XX_PMU_H + +#include "gd32f4xx.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ + +/* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */ + +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU low-driver mode when use low power LDO */ +#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU low-driver mode when use normal power LDO */ +#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + + +/* PMU high-driver mode switch */ +#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ + +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU backup SRAM LDO on or off */ +#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) +#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ +#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* LVD functions */ +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* LDO functions */ +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); + +/* functions of low-driver mode and high-driver mode */ +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* backup SRAM LDO on */ +void pmu_backup_ldo_config(uint32_t bkp_ldo); +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); + +#endif /* GD32F4XX_PMU_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h new file mode 100644 index 0000000..2426374 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h @@ -0,0 +1,1183 @@ +/*! + \file gd32f4xx_rcu.h + \brief definitions for the RCU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_RCU_H +#define GD32F4XX_RCU_H + +#include "gd32f4xx.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */ +#define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */ +#define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */ +#define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */ +#define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */ +#define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */ +#define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */ +#define RCU_AHB1EN REG32(RCU + 0x30U) /*!< AHB1 enable register */ +#define RCU_AHB2EN REG32(RCU + 0x34U) /*!< AHB2 enable register */ +#define RCU_AHB3EN REG32(RCU + 0x38U) /*!< AHB3 enable register */ +#define RCU_APB1EN REG32(RCU + 0x40U) /*!< APB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ +#define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ +#define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ +#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ +#define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ +#define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ +#define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ +#define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ +#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ +#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ +#define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#define RCU_ADDAPB1SPEN REG32(RCU + 0xE8U) /*!< APB1 additional sleep mode enable register */ +#define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL */ +#define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ +#define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ +#define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ +#define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ +#define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ + +/* RCU_PLL */ +#define RCU_PLL_PLLPSC BITS(0,5) /*!< The PLL VCO source clock prescaler */ +#define RCU_PLL_PLLN BITS(6,14) /*!< The PLL VCO clock multi factor */ +#define RCU_PLL_PLLP BITS(16,17) /*!< The PLLP output frequency division factor from PLL VCO clock */ +#define RCU_PLL_PLLSEL BIT(22) /*!< PLL Clock Source Selection */ +#define RCU_PLL_PLLQ BITS(24,27) /*!< The PLL Q output frequency division factor from PLL VCO clock */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(10,12) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(13,15) /*!< APB2 prescaler selection */ +#define RCU_CFG0_RTCDIV BITS(16,20) /*!< RTC clock divider factor */ +#define RCU_CFG0_CKOUT0SEL BITS(21,22) /*!< CKOUT0 Clock Source Selection */ +#define RCU_CFG0_I2SSEL BIT(23) /*!< I2S Clock Source Selection */ +#define RCU_CFG0_CKOUT0DIV BITS(24,26) /*!< The CK_OUT0 divider which the CK_OUT0 frequency can be reduced */ +#define RCU_CFG0_CKOUT1DIV BITS(27,29) /*!< The CK_OUT1 divider which the CK_OUT1 frequency can be reduced */ +#define RCU_CFG0_CKOUT1SEL BITS(30,31) /*!< CKOUT1 Clock Source Selection */ + +/* RCU_INT */ +#define RCU_INT_IRC32KSTBIF BIT(0) /*!< IRC32K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC16MSTBIF BIT(2) /*!< IRC16M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLLI2SSTBIF BIT(5) /*!< PLLI2S stabilization interrupt flag */ +#define RCU_INT_PLLSAISTBIF BIT(6) /*!< PLLSAI stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC32KSTBIE BIT(8) /*!< IRC32K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC16MSTBIE BIT(10) /*!< IRC16M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLLI2SSTBIE BIT(13) /*!< PLLI2S Stabilization Interrupt Enable */ +#define RCU_INT_PLLSAISTBIE BIT(14) /*!< PLLSAI Stabilization Interrupt Enable */ +#define RCU_INT_IRC32KSTBIC BIT(16) /*!< IRC32K Stabilization Interrupt Clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization Interrupt Clear */ +#define RCU_INT_IRC16MSTBIC BIT(18) /*!< IRC16M Stabilization Interrupt Clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization Interrupt Clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization Interrupt Clear */ +#define RCU_INT_PLLI2SSTBIC BIT(21) /*!< PLLI2S stabilization Interrupt Clear */ +#define RCU_INT_PLLSAISTBIC BIT(22) /*!< PLLSAI stabilization Interrupt Clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL Clock Stuck Interrupt Clear */ + +/* RCU_AHB1RST */ +#define RCU_AHB1RST_PARST BIT(0) /*!< GPIO port A reset */ +#define RCU_AHB1RST_PBRST BIT(1) /*!< GPIO port B reset */ +#define RCU_AHB1RST_PCRST BIT(2) /*!< GPIO port C reset */ +#define RCU_AHB1RST_PDRST BIT(3) /*!< GPIO port D reset */ +#define RCU_AHB1RST_PERST BIT(4) /*!< GPIO port E reset */ +#define RCU_AHB1RST_PFRST BIT(5) /*!< GPIO port F reset */ +#define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ +#define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ +#define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ +#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ +#define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ +#define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ +#define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ +#define RCU_AHB1RST_ENETRST BIT(25) /*!< ENET reset */ +#define RCU_AHB1RST_USBHSRST BIT(29) /*!< USBHS reset */ + +/* RCU_AHB2RST */ +#define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ +#define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ +#define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ + +/* RCU_AHB3RST */ +#define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_I2C2RST BIT(23) /*!< I2C2 reset */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ +#define RCU_APB1RST_UART6RST BIT(30) /*!< UART6 reset */ +#define RCU_APB1RST_UART7RST BIT(31) /*!< UART7 reset */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ +#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ +#define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ +#define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_SPI3RST BIT(13) /*!< SPI3 reset */ +#define RCU_APB2RST_SYSCFGRST BIT(14) /*!< SYSCFG reset */ +#define RCU_APB2RST_TIMER8RST BIT(16) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(17) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(18) /*!< TIMER10 reset */ +#define RCU_APB2RST_SPI4RST BIT(20) /*!< SPI4 reset */ +#define RCU_APB2RST_SPI5RST BIT(21) /*!< SPI5 reset */ +#define RCU_APB2RST_TLIRST BIT(26) /*!< TLI reset */ + +/* RCU_AHB1EN */ +#define RCU_AHB1EN_PAEN BIT(0) /*!< GPIO port A clock enable */ +#define RCU_AHB1EN_PBEN BIT(1) /*!< GPIO port B clock enable */ +#define RCU_AHB1EN_PCEN BIT(2) /*!< GPIO port C clock enable */ +#define RCU_AHB1EN_PDEN BIT(3) /*!< GPIO port D clock enable */ +#define RCU_AHB1EN_PEEN BIT(4) /*!< GPIO port E clock enable */ +#define RCU_AHB1EN_PFEN BIT(5) /*!< GPIO port F clock enable */ +#define RCU_AHB1EN_PGEN BIT(6) /*!< GPIO port G clock enable */ +#define RCU_AHB1EN_PHEN BIT(7) /*!< GPIO port H clock enable */ +#define RCU_AHB1EN_PIEN BIT(8) /*!< GPIO port I clock enable */ +#define RCU_AHB1EN_CRCEN BIT(12) /*!< CRC clock enable */ +#define RCU_AHB1EN_BKPSRAMEN BIT(18) /*!< BKPSRAM clock enable */ +#define RCU_AHB1EN_TCMSRAMEN BIT(20) /*!< TCMSRAM clock enable */ +#define RCU_AHB1EN_DMA0EN BIT(21) /*!< DMA0 clock enable */ +#define RCU_AHB1EN_DMA1EN BIT(22) /*!< DMA1 clock enable */ +#define RCU_AHB1EN_IPAEN BIT(23) /*!< IPA clock enable */ +#define RCU_AHB1EN_ENETEN BIT(25) /*!< ENET clock enable */ +#define RCU_AHB1EN_ENETTXEN BIT(26) /*!< Ethernet TX clock enable */ +#define RCU_AHB1EN_ENETRXEN BIT(27) /*!< Ethernet RX clock enable */ +#define RCU_AHB1EN_ENETPTPEN BIT(28) /*!< Ethernet PTP clock enable */ +#define RCU_AHB1EN_USBHSEN BIT(29) /*!< USBHS clock enable */ +#define RCU_AHB1EN_USBHSULPIEN BIT(30) /*!< USBHS ULPI clock enable */ + +/* RCU_AHB2EN */ +#define RCU_AHB2EN_DCIEN BIT(0) /*!< DCI clock enable */ +#define RCU_AHB2EN_TRNGEN BIT(6) /*!< TRNG clock enable */ +#define RCU_AHB2EN_USBFSEN BIT(7) /*!< USBFS clock enable */ + +/* RCU_AHB3EN */ +#define RCU_AHB3EN_EXMCEN BIT(0) /*!< EXMC clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_I2C2EN BIT(23) /*!< I2C2 clock enable */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ +#define RCU_APB1EN_UART6EN BIT(30) /*!< UART6 clock enable */ +#define RCU_APB1EN_UART7EN BIT(31) /*!< UART7 clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_TIMER0EN BIT(0) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(1) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(4) /*!< USART0 clock enable */ +#define RCU_APB2EN_USART5EN BIT(5) /*!< USART5 clock enable */ +#define RCU_APB2EN_ADC0EN BIT(8) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(9) /*!< ADC1 clock enable */ +#define RCU_APB2EN_ADC2EN BIT(10) /*!< ADC2 clock enable */ +#define RCU_APB2EN_SDIOEN BIT(11) /*!< SDIO clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_SPI3EN BIT(13) /*!< SPI3 clock enable */ +#define RCU_APB2EN_SYSCFGEN BIT(14) /*!< SYSCFG clock enable */ +#define RCU_APB2EN_TIMER8EN BIT(16) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(17) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(18) /*!< TIMER10 clock enable */ +#define RCU_APB2EN_SPI4EN BIT(20) /*!< SPI4 clock enable */ +#define RCU_APB2EN_SPI5EN BIT(21) /*!< SPI5 clock enable */ +#define RCU_APB2EN_TLIEN BIT(26) /*!< TLI clock enable */ + +/* RCU_AHB1SPEN */ +#define RCU_AHB1SPEN_PASPEN BIT(0) /*!< GPIO port A clock enable when sleep mode */ +#define RCU_AHB1SPEN_PBSPEN BIT(1) /*!< GPIO port B clock enable when sleep mode */ +#define RCU_AHB1SPEN_PCSPEN BIT(2) /*!< GPIO port C clock enable when sleep mode */ +#define RCU_AHB1SPEN_PDSPEN BIT(3) /*!< GPIO port D clock enable when sleep mode */ +#define RCU_AHB1SPEN_PESPEN BIT(4) /*!< GPIO port E clock enable when sleep mode */ +#define RCU_AHB1SPEN_PFSPEN BIT(5) /*!< GPIO port F clock enable when sleep mode */ +#define RCU_AHB1SPEN_PGSPEN BIT(6) /*!< GPIO port G clock enable when sleep mode */ +#define RCU_AHB1SPEN_PHSPEN BIT(7) /*!< GPIO port H clock enable when sleep mode */ +#define RCU_AHB1SPEN_PISPEN BIT(8) /*!< GPIO port I clock enable when sleep mode */ +#define RCU_AHB1SPEN_CRCSPEN BIT(12) /*!< CRC clock enable when sleep mode */ +#define RCU_AHB1SPEN_FMCSPEN BIT(15) /*!< FMC clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM0SPEN BIT(16) /*!< SRAM0 clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM1SPEN BIT(17) /*!< SRAM1 clock enable when sleep mode */ +#define RCU_AHB1SPEN_BKPSRAMSPEN BIT(18) /*!< BKPSRAM clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM2SPEN BIT(19) /*!< SRAM2 clock enable when sleep mode */ +#define RCU_AHB1SPEN_DMA0SPEN BIT(21) /*!< DMA0 clock when sleep mode enable */ +#define RCU_AHB1SPEN_DMA1SPEN BIT(22) /*!< DMA1 clock when sleep mode enable */ +#define RCU_AHB1SPEN_IPASPEN BIT(23) /*!< IPA clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETSPEN BIT(25) /*!< ENET clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETTXSPEN BIT(26) /*!< Ethernet TX clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETRXSPEN BIT(27) /*!< Ethernet RX clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETPTPSPEN BIT(28) /*!< Ethernet PTP clock enable when sleep mode */ +#define RCU_AHB1SPEN_USBHSSPEN BIT(29) /*!< USBHS clock enable when sleep mode */ +#define RCU_AHB1SPEN_USBHSULPISPEN BIT(30) /*!< USBHS ULPI clock enable when sleep mode */ + +/* RCU_AHB2SPEN */ +#define RCU_AHB2SPEN_DCISPEN BIT(0) /*!< DCI clock enable when sleep mode */ +#define RCU_AHB2SPEN_TRNGSPEN BIT(6) /*!< TRNG clock enable when sleep mode */ +#define RCU_AHB2SPEN_USBFSSPEN BIT(7) /*!< USBFS clock enable when sleep mode */ + +/* RCU_AHB3SPEN */ +#define RCU_AHB3SPEN_EXMCSPEN BIT(0) /*!< EXMC clock enable when sleep mode */ + +/* RCU_APB1SPEN */ +#define RCU_APB1SPEN_TIMER1SPEN BIT(0) /*!< TIMER1 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER2SPEN BIT(1) /*!< TIMER2 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER3SPEN BIT(2) /*!< TIMER3 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER4SPEN BIT(3) /*!< TIMER4 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER5SPEN BIT(4) /*!< TIMER5 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER6SPEN BIT(5) /*!< TIMER6 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER11SPEN BIT(6) /*!< TIMER11 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER12SPEN BIT(7) /*!< TIMER12 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER13SPEN BIT(8) /*!< TIMER13 clock enable when sleep mode */ +#define RCU_APB1SPEN_WWDGTSPEN BIT(11) /*!< WWDGT clock enable when sleep mode */ +#define RCU_APB1SPEN_SPI1SPEN BIT(14) /*!< SPI1 clock enable when sleep mode */ +#define RCU_APB1SPEN_SPI2SPEN BIT(15) /*!< SPI2 clock enable when sleep mode */ +#define RCU_APB1SPEN_USART1SPEN BIT(17) /*!< USART1 clock enable when sleep mode*/ +#define RCU_APB1SPEN_USART2SPEN BIT(18) /*!< USART2 clock enable when sleep mode*/ +#define RCU_APB1SPEN_UART3SPEN BIT(19) /*!< UART3 clock enable when sleep mode*/ +#define RCU_APB1SPEN_UART4SPEN BIT(20) /*!< UART4 clock enable when sleep mode */ +#define RCU_APB1SPEN_I2C0SPEN BIT(21) /*!< I2C0 clock enable when sleep mode */ +#define RCU_APB1SPEN_I2C1SPEN BIT(22) /*!< I2C1 clock enable when sleep mode*/ +#define RCU_APB1SPEN_I2C2SPEN BIT(23) /*!< I2C2 clock enable when sleep mode */ +#define RCU_APB1SPEN_CAN0SPEN BIT(25) /*!< CAN0 clock enable when sleep mode*/ +#define RCU_APB1SPEN_CAN1SPEN BIT(26) /*!< CAN1 clock enable when sleep mode */ +#define RCU_APB1SPEN_PMUSPEN BIT(28) /*!< PMU clock enable when sleep mode */ +#define RCU_APB1SPEN_DACSPEN BIT(29) /*!< DAC clock enable when sleep mode */ +#define RCU_APB1SPEN_UART6SPEN BIT(30) /*!< UART6 clock enable when sleep mode */ +#define RCU_APB1SPEN_UART7SPEN BIT(31) /*!< UART7 clock enable when sleep mode */ + +/* RCU_APB2SPEN */ +#define RCU_APB2SPEN_TIMER0SPEN BIT(0) /*!< TIMER0 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER7SPEN BIT(1) /*!< TIMER7 clock enable when sleep mode */ +#define RCU_APB2SPEN_USART0SPEN BIT(4) /*!< USART0 clock enable when sleep mode */ +#define RCU_APB2SPEN_USART5SPEN BIT(5) /*!< USART5 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC0SPEN BIT(8) /*!< ADC0 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC1SPEN BIT(9) /*!< ADC1 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC2SPEN BIT(10) /*!< ADC2 clock enable when sleep mode */ +#define RCU_APB2SPEN_SDIOSPEN BIT(11) /*!< SDIO clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI0SPEN BIT(12) /*!< SPI0 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI3SPEN BIT(13) /*!< SPI3 clock enable when sleep mode */ +#define RCU_APB2SPEN_SYSCFGSPEN BIT(14) /*!< SYSCFG clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER8SPEN BIT(16) /*!< TIMER8 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER9SPEN BIT(17) /*!< TIMER9 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER10SPEN BIT(18) /*!< TIMER10 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI4SPEN BIT(20) /*!< SPI4 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI5SPEN BIT(21) /*!< SPI5 clock enable when sleep mode */ +#define RCU_APB2SPEN_TLISPEN BIT(26) /*!< TLI clock enable when sleep mode*/ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BIT(3) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC32KEN BIT(0) /*!< IRC32K enable */ +#define RCU_RSTSCK_IRC32KSTB BIT(1) /*!< IRC32K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_BORRSTF BIT(25) /*!< BOR reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_PLLSSCTL */ +#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria + must be met: MODSTEP*MODCNT=215-1 */ +#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria + must be met: MODSTEP*MODCNT=215-1 */ +#define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ +#define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ + +/* RCU_PLLI2S */ +#define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ +#define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ + +/* RCU_PLLSAI */ +#define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ +#define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PLLSAIRDIV BITS(16,17) /*!< the divider factor from PLLSAIR clock */ +#define RCU_CFG1_TIMERSEL BIT(24) /*!< TIMER clock selection */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ +#define RCU_ADDCTL_PLL48MSEL BIT(1) /*!< PLL48M clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ +#define RCU_ADDAPB1RST_IREFRST BIT(31) /*!< IREF reset */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ +#define RCU_ADDAPB1EN_IREFEN BIT(31) /*!< IREF interface clock enable */ + +/* RCU_ADDAPB1SPEN */ +#define RCU_ADDAPB1SPEN_CTCSPEN BIT(27) /*!< CTC clock enable during sleep mode */ +#define RCU_ADDAPB1SPEN_IREFSPEN BIT(31) /*!< IREF interface clock enable during sleep mode */ + +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) /*!< RCU_DSV key register */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +/* define the voltage key unlock value */ +#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) + +/* register offset */ +/* peripherals enable */ +#define AHB1EN_REG_OFFSET 0x30U /*!< AHB1 enable register offset */ +#define AHB2EN_REG_OFFSET 0x34U /*!< AHB2 enable register offset */ +#define AHB3EN_REG_OFFSET 0x38U /*!< AHB3 enable register offset */ +#define APB1EN_REG_OFFSET 0x40U /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x44U /*!< APB2 enable register offset */ +#define AHB1SPEN_REG_OFFSET 0x50U /*!< AHB1 sleep mode enable register offset */ +#define AHB2SPEN_REG_OFFSET 0x54U /*!< AHB2 sleep mode enable register offset */ +#define AHB3SPEN_REG_OFFSET 0x58U /*!< AHB3 sleep mode enable register offset */ +#define APB1SPEN_REG_OFFSET 0x60U /*!< APB1 sleep mode enable register offset */ +#define APB2SPEN_REG_OFFSET 0x64U /*!< APB2 sleep mode enable register offset */ +#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ +#define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ + +/* peripherals reset */ +#define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ +#define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ +#define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ +#define APB1RST_REG_OFFSET 0x20U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x24U /*!< APB2 reset register offset */ +#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ +#define RSTSCK_REG_OFFSET 0x74U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x70U /*!< backup domain control register offset */ +#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x0CU /*!< clock interrupt register offset */ +#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ + +/* configuration register */ +#define PLL_REG_OFFSET 0x04U /*!< PLL register offset */ +#define CFG0_REG_OFFSET 0x08U /*!< clock configuration register 0 offset */ +#define PLLSSCTL_REG_OFFSET 0x80U /*!< PLL clock spread spectrum control register offset */ +#define PLLI2S_REG_OFFSET 0x84U /*!< PLLI2S register offset */ +#define PLLSAI_REG_OFFSET 0x88U /*!< PLLSAI register offset */ +#define CFG1_REG_OFFSET 0x8CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 0U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 1U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 2U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 3U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 4U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 5U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 6U), /*!< GPIOG clock */ + RCU_GPIOH = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 7U), /*!< GPIOH clock */ + RCU_GPIOI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 8U), /*!< GPIOI clock */ + RCU_CRC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 12U), /*!< CRC clock */ + RCU_BKPSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ + RCU_TCMSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 20U), /*!< TCMSRAM clock */ + RCU_DMA0 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 21U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 22U), /*!< DMA1 clock */ + RCU_IPA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 23U), /*!< IPA clock */ + RCU_ENET = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 25U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 26U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 27U), /*!< ENETRX clock */ + RCU_ENETPTP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 28U), /*!< ENETPTP clock */ + RCU_USBHS = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 29U), /*!< USBHS clock */ + RCU_USBHSULPI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ + /* AHB2 peripherals */ + RCU_DCI = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 0U), /*!< DCI clock */ + RCU_TRNG = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 6U), /*!< TRNG clock */ + RCU_USBFS = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 7U), /*!< USBFS clock */ + /* AHB3 peripherals */ + RCU_EXMC = RCU_REGIDX_BIT(AHB3EN_REG_OFFSET, 0U), /*!< EXMC clock */ + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_UART6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 30U), /*!< UART6 clock */ + RCU_UART7 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 31U), /*!< UART7 clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + /* APB2 peripherals */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< TIMER0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< USART0 clock */ + RCU_USART5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< USART5 clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC1 clock */ + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC2 clock */ + RCU_SDIO = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< SDIO clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_SPI3 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< SPI3 clock */ + RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< SYSCFG clock */ + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 16U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 17U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 18U), /*!< TIMER10 clock */ + RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ + RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ + RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ + /* APB1 additional peripherals */ + RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ + RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 0U), /*!< GPIOA clock */ + RCU_GPIOB_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 1U), /*!< GPIOB clock */ + RCU_GPIOC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 2U), /*!< GPIOC clock */ + RCU_GPIOD_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 3U), /*!< GPIOD clock */ + RCU_GPIOE_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 4U), /*!< GPIOE clock */ + RCU_GPIOF_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 5U), /*!< GPIOF clock */ + RCU_GPIOG_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 6U), /*!< GPIOG clock */ + RCU_GPIOH_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 7U), /*!< GPIOH clock */ + RCU_GPIOI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 8U), /*!< GPIOI clock */ + RCU_CRC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 12U), /*!< CRC clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 15U), /*!< FMC clock */ + RCU_SRAM0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 16U), /*!< SRAM0 clock */ + RCU_SRAM1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 17U), /*!< SRAM1 clock */ + RCU_BKPSRAM_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ + RCU_SRAM2_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 19U), /*!< SRAM2 clock */ + RCU_DMA0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 21U), /*!< DMA0 clock */ + RCU_DMA1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 22U), /*!< DMA1 clock */ + RCU_IPA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 23U), /*!< IPA clock */ + RCU_ENET_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 25U), /*!< ENET clock */ + RCU_ENETTX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 26U), /*!< ENETTX clock */ + RCU_ENETRX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 27U), /*!< ENETRX clock */ + RCU_ENETPTP_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 28U), /*!< ENETPTP clock */ + RCU_USBHS_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 29U), /*!< USBHS clock */ + RCU_USBHSULPI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ + /* AHB2 peripherals */ + RCU_DCI_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 0U), /*!< DCI clock */ + RCU_TRNG_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 6U), /*!< TRNG clock */ + RCU_USBFS_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 7U), /*!< USBFS clock */ + /* AHB3 peripherals */ + RCU_EXMC_SLP = RCU_REGIDX_BIT(AHB3SPEN_REG_OFFSET, 0U), /*!< EXMC clock */ + /* APB1 peripherals */ + RCU_TIMER1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_UART6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 30U), /*!< UART6 clock */ + RCU_UART7_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 31U), /*!< UART7 clock */ + /* APB2 peripherals */ + RCU_TIMER0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 0U), /*!< TIMER0 clock */ + RCU_TIMER7_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 1U), /*!< TIMER7 clock */ + RCU_USART0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 4U), /*!< USART0 clock */ + RCU_USART5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 5U), /*!< USART5 clock */ + RCU_ADC0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 8U), /*!< ADC0 clock */ + RCU_ADC1_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 9U), /*!< ADC1 clock */ + RCU_ADC2_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 10U), /*!< ADC2 clock */ + RCU_SDIO_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 11U), /*!< SDIO clock */ + RCU_SPI0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_SPI3_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 13U), /*!< SPI3 clock */ + RCU_SYSCFG_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 14U), /*!< SYSCFG clock */ + RCU_TIMER8_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 16U), /*!< TIMER8 clock */ + RCU_TIMER9_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 17U), /*!< TIMER9 clock */ + RCU_TIMER10_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 18U), /*!< TIMER10 clock */ + RCU_SPI4_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 20U), /*!< SPI4 clock */ + RCU_SPI5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 21U), /*!< SPI5 clock */ + RCU_TLI_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 26U), /*!< TLI clock */ + /* APB1 additional peripherals */ + RCU_CTC_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 27U), /*!< CTC clock */ + RCU_IREF_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 31U), /*!< IREF clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 0U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 1U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 2U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 3U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 4U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 5U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 6U), /*!< GPIOG clock reset */ + RCU_GPIOHRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 7U), /*!< GPIOH clock reset */ + RCU_GPIOIRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 8U), /*!< GPIOI clock reset */ + RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ + RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ + RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ + RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ + RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ + /* AHB2 peripherals */ + RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ + RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 6U), /*!< TRNG clock reset */ + RCU_USBFSRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 7U), /*!< USBFS clock reset */ + /* AHB3 peripherals */ + RCU_EXMCRST = RCU_REGIDX_BIT(AHB3RST_REG_OFFSET, 0U), /*!< EXMC clock reset */ + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ + RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + RCU_UART6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 30U), /*!< UART6 clock reset */ + RCU_UART7RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 31U), /*!< UART7 clock reset */ + /* APB2 peripherals */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< TIMER0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< USART0 clock reset */ + RCU_USART5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< USART5 clock reset */ + RCU_ADCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< ADCs all clock reset */ + RCU_SDIORST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< SDIO clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_SPI3RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< SPI3 clock reset */ + RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< SYSCFG clock reset */ + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 16U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 17U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 18U), /*!< TIMER10 clock reset */ + RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ + RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ + RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ + /* APB1 additional peripherals */ + RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ + RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + /* clock stabilization flags */ + RCU_FLAG_IRC16MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC16M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLLI2S stabilization flags */ + RCU_FLAG_PLLSAISTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLLSAI stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC32KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC32K stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ + /* reset source flags */ + RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< BOR reset flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< External PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< Software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< Low-power reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ + RCU_INT_FLAG_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLLSAI stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC32KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC32K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC16MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC16M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLI2SSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLLI2S stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSAISTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLLSAI stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ + RCU_INT_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLLSAI stabilization interrupt */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ +}rcu_int_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC16M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC16M */ + RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ + RCU_IRC32K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC32K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ + RCU_PLLI2S_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLLI2S */ + RCU_PLLSAI_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLLSAI */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +}rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC16M CFG0_SCS(0) /*!< system clock source select IRC16M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLLP CFG0_SCS(2) /*!< system clock source select PLLP */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC16M CFG0_SCSS(0) /*!< system clock source select IRC16M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLLP CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* RTC clock divider factor from HXTAL clock */ +#define CFG0_RTCDIV(regval) (BITS(16,20) & ((uint32_t)(regval) << 16)) +#define RCU_RTC_HXTAL_NONE CFG0_RTCDIV(0) /*!< no clock for RTC */ +#define RCU_RTC_HXTAL_DIV2 CFG0_RTCDIV(2) /*!< RTCDIV clock select CK_HXTAL/2 */ +#define RCU_RTC_HXTAL_DIV3 CFG0_RTCDIV(3) /*!< RTCDIV clock select CK_HXTAL/3 */ +#define RCU_RTC_HXTAL_DIV4 CFG0_RTCDIV(4) /*!< RTCDIV clock select CK_HXTAL/4 */ +#define RCU_RTC_HXTAL_DIV5 CFG0_RTCDIV(5) /*!< RTCDIV clock select CK_HXTAL/5 */ +#define RCU_RTC_HXTAL_DIV6 CFG0_RTCDIV(6) /*!< RTCDIV clock select CK_HXTAL/6 */ +#define RCU_RTC_HXTAL_DIV7 CFG0_RTCDIV(7) /*!< RTCDIV clock select CK_HXTAL/7 */ +#define RCU_RTC_HXTAL_DIV8 CFG0_RTCDIV(8) /*!< RTCDIV clock select CK_HXTAL/8 */ +#define RCU_RTC_HXTAL_DIV9 CFG0_RTCDIV(9) /*!< RTCDIV clock select CK_HXTAL/9 */ +#define RCU_RTC_HXTAL_DIV10 CFG0_RTCDIV(10) /*!< RTCDIV clock select CK_HXTAL/10 */ +#define RCU_RTC_HXTAL_DIV11 CFG0_RTCDIV(11) /*!< RTCDIV clock select CK_HXTAL/11 */ +#define RCU_RTC_HXTAL_DIV12 CFG0_RTCDIV(12) /*!< RTCDIV clock select CK_HXTAL/12 */ +#define RCU_RTC_HXTAL_DIV13 CFG0_RTCDIV(13) /*!< RTCDIV clock select CK_HXTAL/13 */ +#define RCU_RTC_HXTAL_DIV14 CFG0_RTCDIV(14) /*!< RTCDIV clock select CK_HXTAL/14 */ +#define RCU_RTC_HXTAL_DIV15 CFG0_RTCDIV(15) /*!< RTCDIV clock select CK_HXTAL/15 */ +#define RCU_RTC_HXTAL_DIV16 CFG0_RTCDIV(16) /*!< RTCDIV clock select CK_HXTAL/16 */ +#define RCU_RTC_HXTAL_DIV17 CFG0_RTCDIV(17) /*!< RTCDIV clock select CK_HXTAL/17 */ +#define RCU_RTC_HXTAL_DIV18 CFG0_RTCDIV(18) /*!< RTCDIV clock select CK_HXTAL/18 */ +#define RCU_RTC_HXTAL_DIV19 CFG0_RTCDIV(19) /*!< RTCDIV clock select CK_HXTAL/19 */ +#define RCU_RTC_HXTAL_DIV20 CFG0_RTCDIV(20) /*!< RTCDIV clock select CK_HXTAL/20 */ +#define RCU_RTC_HXTAL_DIV21 CFG0_RTCDIV(21) /*!< RTCDIV clock select CK_HXTAL/21 */ +#define RCU_RTC_HXTAL_DIV22 CFG0_RTCDIV(22) /*!< RTCDIV clock select CK_HXTAL/22 */ +#define RCU_RTC_HXTAL_DIV23 CFG0_RTCDIV(23) /*!< RTCDIV clock select CK_HXTAL/23 */ +#define RCU_RTC_HXTAL_DIV24 CFG0_RTCDIV(24) /*!< RTCDIV clock select CK_HXTAL/24 */ +#define RCU_RTC_HXTAL_DIV25 CFG0_RTCDIV(25) /*!< RTCDIV clock select CK_HXTAL/25 */ +#define RCU_RTC_HXTAL_DIV26 CFG0_RTCDIV(26) /*!< RTCDIV clock select CK_HXTAL/26 */ +#define RCU_RTC_HXTAL_DIV27 CFG0_RTCDIV(27) /*!< RTCDIV clock select CK_HXTAL/27 */ +#define RCU_RTC_HXTAL_DIV28 CFG0_RTCDIV(28) /*!< RTCDIV clock select CK_HXTAL/28 */ +#define RCU_RTC_HXTAL_DIV29 CFG0_RTCDIV(29) /*!< RTCDIV clock select CK_HXTAL/29 */ +#define RCU_RTC_HXTAL_DIV30 CFG0_RTCDIV(30) /*!< RTCDIV clock select CK_HXTAL/30 */ +#define RCU_RTC_HXTAL_DIV31 CFG0_RTCDIV(31) /*!< RTCDIV clock select CK_HXTAL/31 */ + +/* CKOUT0 Clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define RCU_CKOUT0SRC_IRC16M CFG0_CKOUT0SEL(0) /*!< internal 16M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_LXTAL CFG0_CKOUT0SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_PLLP CFG0_CKOUT0SEL(3) /*!< CK_PLLP clock selected */ + +/* I2S Clock source selection */ +#define RCU_I2SSRC_PLLI2S ((uint32_t)0x00000000U) /*!< PLLI2S output clock selected as I2S source clock */ +#define RCU_I2SSRC_I2S_CKIN RCU_CFG0_I2SSEL /*!< external I2S_CKIN pin selected as I2S source clock */ + +/* The CK_OUT0 divider */ +#define CFG0_CKOUT0DIV(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0_DIV1 CFG0_CKOUT0DIV(0) /*!< CK_OUT0 is divided by 1 */ +#define RCU_CKOUT0_DIV2 CFG0_CKOUT0DIV(4) /*!< CK_OUT0 is divided by 2 */ +#define RCU_CKOUT0_DIV3 CFG0_CKOUT0DIV(5) /*!< CK_OUT0 is divided by 3 */ +#define RCU_CKOUT0_DIV4 CFG0_CKOUT0DIV(6) /*!< CK_OUT0 is divided by 4 */ +#define RCU_CKOUT0_DIV5 CFG0_CKOUT0DIV(7) /*!< CK_OUT0 is divided by 5 */ + +/* The CK_OUT1 divider */ +#define CFG0_CKOUT1DIV(regval) (BITS(27,29) & ((uint32_t)(regval) << 27)) +#define RCU_CKOUT1_DIV1 CFG0_CKOUT1DIV(0) /*!< CK_OUT1 is divided by 1 */ +#define RCU_CKOUT1_DIV2 CFG0_CKOUT1DIV(4) /*!< CK_OUT1 is divided by 2 */ +#define RCU_CKOUT1_DIV3 CFG0_CKOUT1DIV(5) /*!< CK_OUT1 is divided by 3 */ +#define RCU_CKOUT1_DIV4 CFG0_CKOUT1DIV(6) /*!< CK_OUT1 is divided by 4 */ +#define RCU_CKOUT1_DIV5 CFG0_CKOUT1DIV(7) /*!< CK_OUT1 is divided by 5 */ + +/* CKOUT1 Clock source selection */ +#define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) +#define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ +#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ +#define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ + +/* RCU_CFG1 register bit define */ +/* the divider factor from PLLI2SQ clock */ +#define CFG1_PLLI2SQDIV(regval) (BITS(0,4) & ((uint32_t)(regval) << 0)) +#define RCU_PLLI2SQ_DIV1 CFG1_PLLI2SQDIV(0) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/1 */ +#define RCU_PLLI2SQ_DIV2 CFG1_PLLI2SQDIV(1) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/2 */ +#define RCU_PLLI2SQ_DIV3 CFG1_PLLI2SQDIV(2) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/3 */ +#define RCU_PLLI2SQ_DIV4 CFG1_PLLI2SQDIV(3) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/4 */ +#define RCU_PLLI2SQ_DIV5 CFG1_PLLI2SQDIV(4) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/5 */ +#define RCU_PLLI2SQ_DIV6 CFG1_PLLI2SQDIV(5) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/6 */ +#define RCU_PLLI2SQ_DIV7 CFG1_PLLI2SQDIV(6) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/7 */ +#define RCU_PLLI2SQ_DIV8 CFG1_PLLI2SQDIV(7) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/8 */ +#define RCU_PLLI2SQ_DIV9 CFG1_PLLI2SQDIV(8) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/9 */ +#define RCU_PLLI2SQ_DIV10 CFG1_PLLI2SQDIV(9) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/10 */ +#define RCU_PLLI2SQ_DIV11 CFG1_PLLI2SQDIV(10) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/11 */ +#define RCU_PLLI2SQ_DIV12 CFG1_PLLI2SQDIV(11) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/12 */ +#define RCU_PLLI2SQ_DIV13 CFG1_PLLI2SQDIV(12) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/13 */ +#define RCU_PLLI2SQ_DIV14 CFG1_PLLI2SQDIV(13) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/14 */ +#define RCU_PLLI2SQ_DIV15 CFG1_PLLI2SQDIV(14) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/15 */ +#define RCU_PLLI2SQ_DIV16 CFG1_PLLI2SQDIV(15) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/16 */ +#define RCU_PLLI2SQ_DIV17 CFG1_PLLI2SQDIV(16) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/17 */ +#define RCU_PLLI2SQ_DIV18 CFG1_PLLI2SQDIV(17) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/18 */ +#define RCU_PLLI2SQ_DIV19 CFG1_PLLI2SQDIV(18) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/19 */ +#define RCU_PLLI2SQ_DIV20 CFG1_PLLI2SQDIV(19) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/20 */ +#define RCU_PLLI2SQ_DIV21 CFG1_PLLI2SQDIV(20) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/21 */ +#define RCU_PLLI2SQ_DIV22 CFG1_PLLI2SQDIV(21) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/22 */ +#define RCU_PLLI2SQ_DIV23 CFG1_PLLI2SQDIV(22) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/23 */ +#define RCU_PLLI2SQ_DIV24 CFG1_PLLI2SQDIV(23) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/24 */ +#define RCU_PLLI2SQ_DIV25 CFG1_PLLI2SQDIV(24) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/25 */ +#define RCU_PLLI2SQ_DIV26 CFG1_PLLI2SQDIV(25) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/26 */ +#define RCU_PLLI2SQ_DIV27 CFG1_PLLI2SQDIV(26) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/27 */ +#define RCU_PLLI2SQ_DIV28 CFG1_PLLI2SQDIV(27) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/28 */ +#define RCU_PLLI2SQ_DIV29 CFG1_PLLI2SQDIV(28) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/29 */ +#define RCU_PLLI2SQ_DIV30 CFG1_PLLI2SQDIV(29) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/30 */ +#define RCU_PLLI2SQ_DIV31 CFG1_PLLI2SQDIV(30) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/31 */ +#define RCU_PLLI2SQ_DIV32 CFG1_PLLI2SQDIV(31) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/32 */ + +/* the divider factor from PLLSAIR clock */ +#define CFG1_PLLSAIRDIV(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define RCU_PLLSAIR_DIV2 CFG1_PLLSAIRDIV(0) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/2 */ +#define RCU_PLLSAIR_DIV4 CFG1_PLLSAIRDIV(1) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/4 */ +#define RCU_PLLSAIR_DIV8 CFG1_PLLSAIRDIV(2) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/8 */ +#define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ + +/* TIMER clock selection */ +#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ +#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ + +/* RCU_PLLSSCTL register bit define */ +/* PLL spread spectrum modulation type select */ +#define RCU_SS_TYPE_CENTER ((uint32_t)0x00000000U) /*!< center type is selected */ +#define RCU_SS_TYPE_DOWN RCU_PLLSSCTL_SS_TYPE /*!< down type is selected */ + +/* RCU_PLL register bit define */ +/* The PLL VCO source clock prescaler */ +#define RCU_PLLPSC_DIV_MIN ((uint32_t)2U) /*!< PLLPSC_DIV min value */ +#define RCU_PLLPSC_DIV_MAX ((uint32_t)63U) /*!< PLLPSC_DIV max value */ + +/* The PLL VCO clock multi factor */ +#define RCU_PLLN_MUL_MIN ((uint32_t)64U) /*!< PLLN_MUL min value */ +#define RCU_PLLN_MUL_MAX ((uint32_t)500U) /*!< PLLN_MUL max value */ +#define RCU_SS_MODULATION_CENTER_INC ((uint32_t)5U) /*!< minimum factor of PLLN in center mode */ +#define RCU_SS_MODULATION_DOWN_INC ((uint32_t)7U) /*!< minimum factor of PLLN in down mode */ + +/* The PLLP output frequency division factor from PLL VCO clock */ +#define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ +#define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ + +/* PLL Clock Source Selection */ +#define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ +#define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ + +/* The PLL Q output frequency division factor from PLL VCO clock */ +#define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ +#define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ + +#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) +#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) +#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) + +/* RCU_BDCTL register bit define */ +/* LXTAL drive capability */ +#define RCU_LXTALDRI_LOWER_DRIVE ((uint32_t)0x00000000) /*!< LXTAL drive capability is selected lower */ +#define RCU_LXTALDRI_HIGHER_DRIVE RCU_BDCTL_LXTALDRI /*!< LXTAL drive capability is selected higher */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC32K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC32K */ +#define RCU_RTCSRC_HXTAL_DIV_RTCDIV BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/RTCDIV */ + +/* RCU_PLLI2S register bit define */ +/* The PLLI2S VCO clock multi factor */ +#define RCU_PLLI2SN_MUL_MIN 50U +#define RCU_PLLI2SN_MUL_MAX 500U + +/* The PLLI2S Q output frequency division factor from PLLI2S VCO clock */ +#define RCU_PLLI2SQ_DIV_MIN 2U +#define RCU_PLLI2SQ_DIV_MAX 15U + +/* The PLLI2S R output frequency division factor from PLLI2S VCO clock */ +#define RCU_PLLI2SR_DIV_MIN 2U +#define RCU_PLLI2SR_DIV_MAX 7U + +/* RCU_PLLSAI register bit define */ +/* The PLLSAI VCO clock multi factor */ +#define RCU_PLLSAIN_MUL_MIN 50U +#define RCU_PLLSAIN_MUL_MAX 500U + +/* The PLLSAI P output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIP_DIV_MIN 2U +#define RCU_PLLSAIP_DIV_MAX 8U + +/* The PLLSAI Q output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIQ_DIV_MIN 2U +#define RCU_PLLSAIQ_DIV_MAX 15U + +/* The PLLSAI R output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIR_DIV_MIN 2U +#define RCU_PLLSAIR_DIV_MAX 7U + +#define CHECK_PLLI2S_PSC_VALID(val) (((val) >= RCU_PLLI2SPSC_DIV_MIN)&&((val) <= RCU_PLLI2SPSC_DIV_MAX)) +#define CHECK_PLLI2S_N_VALID(val) (((val) >= RCU_PLLI2SN_MUL_MIN)&&((val) <= RCU_PLLI2SN_MUL_MAX)) +#define CHECK_PLLI2S_Q_VALID(val) (((val) >= RCU_PLLI2SQ_DIV_MIN)&&((val) <= RCU_PLLI2SQ_DIV_MAX)) +#define CHECK_PLLI2S_R_VALID(val) (((val) >= RCU_PLLI2SR_DIV_MIN)&&((val) <= RCU_PLLI2SR_DIV_MAX)) + +#define CHECK_PLLSAI_N_VALID(val) (((val) >= (RCU_PLLSAIN_MUL_MIN))&&((val) <= RCU_PLLSAIN_MUL_MAX)) +#define CHECK_PLLSAI_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLLSAI_Q_VALID(val) (((val) >= RCU_PLLSAIQ_DIV_MIN)&&((val) <= RCU_PLLSAIQ_DIV_MAX)) +#define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) + +/* RCU_ADDCTL register bit define */ +/* 48MHz clock selection */ +#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ + +/* PLL48M clock selection */ +#define RCU_PLL48MSRC_PLLQ ((uint32_t)0x00000000U) /*!< PLL48M source clock select PLLQ */ +#define RCU_PLL48MSRC_PLLSAIP RCU_ADDCTL_PLL48MSEL /*!< PLL48M source clock select PLLSAIP */ + +/* Deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/ + + +/* function declarations */ +/* peripherals clock configure functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP */ +void rcu_bkp_reset_enable(void); +/* disable the BKP reset */ +void rcu_bkp_reset_disable(void); + +/* system and peripherals clock source, system reset configure functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div); +/* configure the CK_OUT1 clock source and divider */ +void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); +/* configure the PLL clock source selection and PLL multiply factor */ +ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); +/* configure the PLLI2S clock */ +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); +/* configure the PLLSAI clock */ +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ +void rcu_rtc_div_config(uint32_t rtc_div); +/* configure the I2S clock source selection */ +void rcu_i2s_clock_config(uint32_t i2s_clock_source); +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); +/* configure the PLL48M clock selection */ +void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); +/* configure the TIMER clock prescaler selection */ +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); +/* configure the TLI clock division selection */ +void rcu_tli_clock_div_config(uint32_t pllsai_r_div); + +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* set the IRC16M adjust value */ +void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); +/* configure the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); +/* enable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_enable(void); +/* disable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_disable(void); + +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +/* flag & interrupt functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum interrupt); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum interrupt); + +#endif /* GD32F4XX_RCU_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h new file mode 100644 index 0000000..283abc6 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h @@ -0,0 +1,641 @@ +/*! + \file gd32f4xx_rtc.c + \brief definitions for the RTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_RTC_H +#define GD32F4XX_RTC_H + +#include "gd32f4xx.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */ +#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */ +#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */ +#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */ +#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */ +#define RTC_WUT REG32((RTC) + 0x14U) /*!< RTC wakeup timer regiser */ +#define RTC_COSC REG32((RTC) + 0x18U) /*!< RTC coarse calibration register */ +#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */ +#define RTC_ALRM1TD REG32((RTC) + 0x20U) /*!< RTC alarm 1 time and date register */ +#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */ +#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */ +#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */ +#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */ +#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */ +#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */ +#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */ +#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */ +#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */ +#define RTC_ALRM1SS REG32((RTC) + 0x48U) /*!< RTC alarm 1 sub second register */ +#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */ +#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */ +#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */ +#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */ +#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */ +#define RTC_BKP5 REG32((RTC) + 0x64U) /*!< RTC backup register */ +#define RTC_BKP6 REG32((RTC) + 0x68U) /*!< RTC backup register */ +#define RTC_BKP7 REG32((RTC) + 0x6CU) /*!< RTC backup register */ +#define RTC_BKP8 REG32((RTC) + 0x70U) /*!< RTC backup register */ +#define RTC_BKP9 REG32((RTC) + 0x74U) /*!< RTC backup register */ +#define RTC_BKP10 REG32((RTC) + 0x78U) /*!< RTC backup register */ +#define RTC_BKP11 REG32((RTC) + 0x7CU) /*!< RTC backup register */ +#define RTC_BKP12 REG32((RTC) + 0x80U) /*!< RTC backup register */ +#define RTC_BKP13 REG32((RTC) + 0x84U) /*!< RTC backup register */ +#define RTC_BKP14 REG32((RTC) + 0x88U) /*!< RTC backup register */ +#define RTC_BKP15 REG32((RTC) + 0x8CU) /*!< RTC backup register */ +#define RTC_BKP16 REG32((RTC) + 0x90U) /*!< RTC backup register */ +#define RTC_BKP17 REG32((RTC) + 0x94U) /*!< RTC backup register */ +#define RTC_BKP18 REG32((RTC) + 0x98U) /*!< RTC backup register */ +#define RTC_BKP19 REG32((RTC) + 0x9CU) /*!< RTC backup register */ + +/* bits definitions */ +/* RTC_TIME */ +#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DATE */ +#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ +#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ +#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ + +/* RTC_CTL */ +#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */ +#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ +#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ +#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ +#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ +#define RTC_CTL_CCEN BIT(7) /*!< coarse calibration function enable */ +#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */ +#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */ +#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */ +#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ +#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */ +#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */ +#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */ +#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ +#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ +#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ +#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ +#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ +#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ +#define RTC_CTL_OS BITS(21,22) /*!< output selection */ +#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ + +/* RTC_STAT */ +#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */ +#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */ +#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */ +#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ +#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ +#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ +#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ +#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ +#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */ +#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */ +#define RTC_STAT_WTF BIT(10) /*!< wakeup timer occurs flag */ +#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ +#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ +#define RTC_STAT_TP0F BIT(13) /*!< RTC tamper 0 detected flag */ +#define RTC_STAT_TP1F BIT(14) /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCPF BIT(16) /*!< smooth calibration pending flag */ + +/* RTC_PSC */ +#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ +#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ + +/* RTC_WUT */ +#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */ + +/* RTC_COSC */ +#define RTC_COSC_COSS BITS(0,4) /*!< coarse calibration step */ +#define RTC_COSC_COSD BIT(7) /*!< coarse calibration direction */ + +/* RTC_ALRMxTD */ +#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */ +#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */ +#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */ +#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */ +#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour units in BCD code */ +#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */ +#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */ +#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ +#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */ +#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */ +#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */ + +/* RTC_WPK */ +#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ + +/* RTC_SS */ +#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ + +/* RTC_SHIFTCTL */ +#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ +#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ + +/* RTC_TTS */ +#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ +#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DTS */ +#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ + +/* RTC_SSTS */ +#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ + +/* RTC_HRFC */ +#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ +#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ + +/* RTC_TAMP */ +#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ +#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ +#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ +#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ +#define RTC_TAMP_TP1EG BIT(4) /*!< Tamper 1 event trigger edge for RTC tamp 1 input */ +#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ +#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ +#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ +#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ +#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ +#define RTC_TAMP_TP0SEL BIT(16) /*!< Tamper 0 function input mapping selection */ +#define RTC_TAMP_TSSEL BIT(17) /*!< Timestamp input mapping selection */ +#define RTC_TAMP_AOT BIT(18) /*!< RTC_ALARM output Type */ + +/* RTC_ALRM0SS */ +#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */ +#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* RTC_ALRM1SS */ +#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */ +#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* constants definitions */ +/* structure for initialization of the RTC */ +typedef struct +{ + uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ + uint8_t month; /*!< RTC month value */ + uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ + uint8_t day_of_week; /*!< RTC weekday value */ + uint8_t hour; /*!< RTC hour value */ + uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ + uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ + uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ + uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ + uint32_t am_pm; /*!< RTC AM/PM value */ + uint32_t display_format; /*!< RTC time notation */ +}rtc_parameter_struct; + +/* structure for RTC alarm configuration */ +typedef struct +{ + uint32_t alarm_mask; /*!< RTC alarm mask */ + uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */ + uint8_t alarm_day; /*!< RTC alarm date or weekday value*/ + uint8_t alarm_hour; /*!< RTC alarm hour value */ + uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ + uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ + uint32_t am_pm; /*!< RTC alarm AM/PM value */ +}rtc_alarm_struct; + +/* structure for RTC time-stamp configuration */ +typedef struct +{ + uint8_t timestamp_month; /*!< RTC time-stamp month value */ + uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ + uint8_t timestamp_day; /*!< RTC time-stamp weekday value */ + uint8_t timestamp_hour; /*!< RTC time-stamp hour value */ + uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ + uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ + uint32_t am_pm; /*!< RTC time-stamp AM/PM value */ +}rtc_timestamp_struct; + +/* structure for RTC tamper configuration */ +typedef struct +{ + uint32_t tamper_source; /*!< RTC tamper source */ + uint32_t tamper_trigger; /*!< RTC tamper trigger */ + uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ + uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ + ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ + uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ + ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ +}rtc_tamper_struct; + +/* time register value */ +#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ +#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ + +#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */ +#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ + +#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */ +#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ + +#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ +#define RTC_PM RTC_TIME_PM /*!< PM format */ + +/* date register value */ +#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */ +#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ + +#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */ +#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ +#define RTC_JAN ((uint8_t)0x01U) /*!< janurary */ +#define RTC_FEB ((uint8_t)0x02U) /*!< february */ +#define RTC_MAR ((uint8_t)0x03U) /*!< march */ +#define RTC_APR ((uint8_t)0x04U) /*!< april */ +#define RTC_MAY ((uint8_t)0x05U) /*!< may */ +#define RTC_JUN ((uint8_t)0x06U) /*!< june */ +#define RTC_JUL ((uint8_t)0x07U) /*!< july */ +#define RTC_AUG ((uint8_t)0x08U) /*!< august */ +#define RTC_SEP ((uint8_t)0x09U) /*!< september */ +#define RTC_OCT ((uint8_t)0x10U) /*!< october */ +#define RTC_NOV ((uint8_t)0x11U) /*!< november */ +#define RTC_DEC ((uint8_t)0x12U) /*!< december */ + +#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */ +#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ +#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */ +#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */ +#define RTC_WEDSDAY ((uint8_t)0x03) /*!< wednesday */ +#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */ +#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */ +#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */ +#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */ + +#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */ +#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ + +/* ctl register value */ +#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */ +#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ +#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */ +#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */ +#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */ + +#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ +#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ +#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */ +#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/ +#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */ +#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/ +#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */ +#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/ + +#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ +#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ + +#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ +#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ + +/* psc register value */ +#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */ +#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ + +#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */ +#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ + +/* alrmtd register value */ +#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */ +#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */ + +#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */ +#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */ + +#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */ +#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */ + +#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */ +#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */ + +#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ +#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */ +#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */ +#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */ +#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */ +#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */ + +#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ +#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */ + +/* wpk register value */ +#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */ + +/* ss register value */ +#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */ + +/* shiftctl register value */ +#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ + +#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ +#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ + +/* tts register value */ +#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */ +#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ + +#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */ +#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ + +#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */ +#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ + +/* dts register value */ +#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */ +#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ + +#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ + +#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ +#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ + +/* ssts register value */ +#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */ + +/* hrfc register value */ +#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */ + +#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ + +#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ +#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ + +/* tamp register value */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ + +#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */ +#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ +#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ +#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ +#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ + +#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */ +#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ + +#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ +#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ + +#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ +#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ + +#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ + +#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ +#define RTC_ALARM_OUTPUT_PP RTC_TAMP_AOT /*!< RTC alarm output push-pull mode */ + +/* ALRMXSS register value */ +#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */ + +#define ALRMXSS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MASKSSC bit field */ +#define RTC_MASKSSC_0_14 ALRMXSS_MASKSSC(0) /*!< mask alarm subsecond configuration */ +#define RTC_MASKSSC_1_14 ALRMXSS_MASKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */ +#define RTC_MASKSSC_2_14 ALRMXSS_MASKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */ +#define RTC_MASKSSC_3_14 ALRMXSS_MASKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */ +#define RTC_MASKSSC_4_14 ALRMXSS_MASKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */ +#define RTC_MASKSSC_5_14 ALRMXSS_MASKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */ +#define RTC_MASKSSC_6_14 ALRMXSS_MASKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */ +#define RTC_MASKSSC_7_14 ALRMXSS_MASKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_8_14 ALRMXSS_MASKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_9_14 ALRMXSS_MASKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */ +#define RTC_MASKSSC_10_14 ALRMXSS_MASKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */ +#define RTC_MASKSSC_11_14 ALRMXSS_MASKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */ +#define RTC_MASKSSC_12_14 ALRMXSS_MASKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */ +#define RTC_MASKSSC_13_14 ALRMXSS_MASKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */ +#define RTC_MASKSSC_14 ALRMXSS_MASKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */ +#define RTC_MASKSSC_NONE ALRMXSS_MASKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */ + +/* RTC interrupt source */ +#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ +#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */ +#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */ +#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ +#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */ + +/* write protect key */ +#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ +#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ +#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ + +/* registers reset value */ +#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ +#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ +#define RTC_STAT_RESET ((uint32_t)0x00000000U) /*!< RTC_STAT register reset value */ +#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ +#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ + +/* RTC alarm */ +#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ +#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ + +/* RTC coarse calibration direction */ +#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ +#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ + +/* RTC wakeup timer clock */ +#define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) +#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */ +#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */ +#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */ +#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ +#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ +#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ + +/* RTC_AF pin */ +#define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ +#define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ +#define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */ +#define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ + +/* RTC flags */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ +#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ +#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */ +#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */ +#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ +#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ +#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ +#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ +#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ +#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */ + +/* function declarations */ +/* reset most of the RTC registers */ +ErrStatus rtc_deinit(void); +/* initialize RTC registers */ +ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); +/* enter RTC init mode */ +ErrStatus rtc_init_mode_enter(void); +/* exit RTC init mode */ +void rtc_init_mode_exit(void); +/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ +ErrStatus rtc_register_sync_wait(void); + +/* get current time and date */ +void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); +/* get current subsecond value */ +uint32_t rtc_subsecond_get(void); + +/* configure RTC alarm */ +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time); +/* configure subsecond of RTC alarm */ +void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond); +/* get RTC alarm */ +void rtc_alarm_get(uint8_t rtc_alarm,rtc_alarm_struct* rtc_alarm_time); +/* get RTC alarm subsecond */ +uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm); +/* enable RTC alarm */ +void rtc_alarm_enable(uint8_t rtc_alarm); +/* disable RTC alarm */ +ErrStatus rtc_alarm_disable(uint8_t rtc_alarm); + +/* enable RTC time-stamp */ +void rtc_timestamp_enable(uint32_t edge); +/* disable RTC time-stamp */ +void rtc_timestamp_disable(void); +/* get RTC timestamp time and date */ +void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); +/* get RTC time-stamp subsecond */ +uint32_t rtc_timestamp_subsecond_get(void); +/* RTC time-stamp pin map */ +void rtc_timestamp_pin_map(uint32_t rtc_af); + +/* enable RTC tamper */ +void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); +/* disable RTC tamper */ +void rtc_tamper_disable(uint32_t source); +/* RTC tamper0 pin map */ +void rtc_tamper0_pin_map(uint32_t rtc_af); + +/* enable specified RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disble specified RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* check specified flag */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear specified flag */ +void rtc_flag_clear(uint32_t flag); + +/* configure RTC alarm output source */ +void rtc_alarm_output_config(uint32_t source, uint32_t mode); +/* configure RTC calibration output source */ +void rtc_calibration_output_config(uint32_t source); + +/* adjust the daylight saving time by adding or substracting one hour from the current time */ +void rtc_hour_adjust(uint32_t operation); +/* adjust RTC second or subsecond value of current time */ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); + +/* enable RTC bypass shadow registers function */ +void rtc_bypass_shadow_enable(void); +/* disable RTC bypass shadow registers function */ +void rtc_bypass_shadow_disable(void); + +/* enable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_enable(void); +/* disable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_disable(void); + +/* enable RTC wakeup timer */ +void rtc_wakeup_enable(void); +/* disable RTC wakeup timer */ +ErrStatus rtc_wakeup_disable(void); +/* set auto wakeup timer clock */ +ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock); +/* set auto wakeup timer value */ +ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer); +/* get auto wakeup timer value */ +uint16_t rtc_wakeup_timer_get(void); + +/* configure RTC smooth calibration */ +ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); +/* enable RTC coarse calibration */ +ErrStatus rtc_coarse_calibration_enable(void); +/* disable RTC coarse calibration */ +ErrStatus rtc_coarse_calibration_disable(void); +/* configure RTC coarse calibration direction and step */ +ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step); + +#endif /* GD32F4XX_RTC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h new file mode 100644 index 0000000..1d88e45 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h @@ -0,0 +1,434 @@ +/*! + \file gd32f4xx_sdio.h + \brief definitions for the SDIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_SDIO_H +#define GD32F4XX_SDIO_H + +#include "gd32f4xx.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ +#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ +#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ +#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command functions */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t sdio_responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* flag and interrupt functions */ +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* SD I/O card functions */ +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* CE-ATA functions */ +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F4XX_SDIO_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h new file mode 100644 index 0000000..ce96da3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h @@ -0,0 +1,379 @@ +/*! + \file gd32f4xx_spi.h + \brief definitions for the SPI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_SPI_H +#define GD32F4XX_SPI_H + +#include "gd32f4xx.h" + +/* SPIx(x=0,1,2,3,4,5) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) +#define SPI3 (SPI_BASE + 0x0000FC00U) +#define SPI4 (SPI_BASE + 0x00011800U) +#define SPI5 (SPI_BASE + 0x00011C00U) + +/* I2Sx_ADD(x=1,2) definitions */ +#define I2S1_ADD I2S_ADD_BASE +#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ + +/* I2S_ADD registers definitions */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2S_PSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_SPI_QCTL(only SPI5) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct { + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI nss control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +} spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock polarity and phase */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl); +/* configure I2S prescale */ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI nss output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI nss output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI nss pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI nss pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* SPI DMA functions */ +/* enable SPI DMA send or receive */ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma); +/* diable SPI DMA send or receive */ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma); + +/* SPI/I2S transfer configure functions */ +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void spi_quad_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void spi_quad_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void spi_quad_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void spi_quad_read_enable(uint32_t spi_periph); +/* enable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); + +/* flag & interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int); +/* get SPI and I2S interrupt status*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F4XX_SPI_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h new file mode 100644 index 0000000..b3c598e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h @@ -0,0 +1,182 @@ +/*! + \file gd32f4xx_syscfg.h + \brief definitions for the SYSCFG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_SYSCFG_H +#define GD32F4XX_SYSCFG_H + +#include "gd32f4xx.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ +#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U) /*!< system I/O compensation control register */ + +/* SYSCFG_CFG0 bits definitions */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,2) /*!< SYSCFG memory remap config */ +#define SYSCFG_CFG0_FMC_SWP BIT(8) /*!< FMC memory swap config */ +#define SYSCFG_CFG0_EXMC_SWP BITS(10,11) /*!< EXMC memory swap config */ + +/* SYSCFG_CFG1 bits definitions */ +#define SYSCFG_CFG1_ENET_PHY_SEL BIT(23) /*!< Ethernet PHY selection config */ + +/* SYSCFG_EXTISS0 bits definitions */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 bits definitions */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 bits definitions */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 bits definitions */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SYSCFG_CPSCTL bits definitions */ +#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +/* boot mode definitions */ +#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< main flash memory remap */ +#define SYSCFG_BOOTMODE_BOOTLOADER ((uint8_t)0x01U) /*!< boot loader remap */ +#define SYSCFG_BOOTMODE_EXMC_SRAM ((uint8_t)0x02U) /*!< SRAM/NOR 0 and 1 of EXMC remap */ +#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< SRAM0 of on-chip SRAM remap */ +#define SYSCFG_BOOTMODE_EXMC_SDRAM ((uint8_t)0x04U) /*!< SDRAM bank0 of EXMC remap */ + +/* FMC swap definitions */ +#define SYSCFG_FMC_SWP_BANK0 ((uint32_t)0x00000000U) /*!< main flash Bank 0 is mapped at address 0x08000000 */ +#define SYSCFG_FMC_SWP_BANK1 ((uint32_t)0x00000100U) /*!< main flash Bank 1 is mapped at address 0x08000000 */ + +/* EXMC swap enable/disable */ +#define SYSCFG_EXMC_SWP_ENABLE ((uint32_t)0x00000400U) /*!< SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card */ +#define SYSCFG_EXMC_SWP_DISABLE ((uint32_t)0x00000000U) /*!< no memory mapping swap */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select GPIOx pin 0~3 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select GPIOx pin 4~7 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select GPIOx pin 8~11 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ +#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ +#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */ +#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */ +#define EXTI_SOURCE_GPIOI ((uint8_t)0x08U) /*!< EXTI GPIOI configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* ethernet PHY selection */ +#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */ +#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */ + +/* I/O compensation cell enable/disable */ +#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */ +#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */ + +/* function declarations */ +/* initialization functions */ +/* deinit syscfg module */ +void syscfg_deinit(void); + +/* function configuration */ +/* configure the boot mode */ +void syscfg_bootmode_config(uint8_t syscfg_bootmode); +/* configure FMC memory mapping swap */ +void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); +/* configure the EXMC swap */ +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); +/* configure the PHY interface for the ethernet MAC */ +void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface); +/* configure the I/O compensation cell */ +void syscfg_compensation_config(uint32_t syscfg_compensation); + +/* interrupt & flag functions */ +/* check the I/O compensation cell is ready or not */ +FlagStatus syscfg_flag_get(void); + +#endif /* GD32F4XX_SYSCFG_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h new file mode 100644 index 0000000..f83d281 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h @@ -0,0 +1,779 @@ +/*! + \file gd32f4xx_timer.h + \brief definitions for the TIMER + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TIMER_H +#define GD32F4XX_TIMER_H + +#include "gd32f4xx.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00010000U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00010400U) +#define TIMER8 (TIMER_BASE + 0x00014000U) +#define TIMER9 (TIMER_BASE + 0x00014400U) +#define TIMER10 (TIMER_BASE + 0x00014800U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ +#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ +#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ +#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER1_IRMP_ITI1_RMP BITS(10,11) /*!< TIMER1 internal trigger input 1 remap */ +#define TIMER4_IRMP_CI3_RMP BITS(6,7) /*!< TIMER4 channel 3 input remap */ +#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ + +/* timer1 internal trigger input1 remap */ +#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) +#define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ +#define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ +#define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ +#define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ + +/* timer4 channel 3 input remap */ +#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) +#define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ +#define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ +#define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ +#define TIMER4_CI3_RMP_RTC_WAKEUP_INT TIMER4_IRMP(3) /*!< timer4 channel 3 input remap to RTC wakeup interrupt */ + +/* timer10 internal trigger input1 remap */ +#define TIMER10_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER10_ITI1_RMP_GPIO TIMER10_IRMP(0) /*!< timer10 internal trigger input1 remap based on GPIO setting */ +#define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ + +/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* the output value selection */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ + +/* function declarations */ +/* TIMER timebase*/ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* timer DMA and event*/ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +/* TIMER interrupt and flag*/ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); + +#endif /* GD32F4XX_TIMER_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h new file mode 100644 index 0000000..e261acc --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h @@ -0,0 +1,373 @@ +/*! + \file gd32f4xx_tli.h + \brief definitions for the TLI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TLI_H +#define GD32F4XX_TLI_H + +#include "gd32f4xx.h" + +/* TLI definitions */ +#define TLI TLI_BASE /*!< TLI base address */ +/* TLI layer definitions */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */ + +/* registers definitions */ +#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */ +#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */ +#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */ +#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */ +#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */ +#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */ +#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */ +#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */ +#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */ +#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */ +#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */ +#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */ +#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */ +#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */ +#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */ +#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */ +#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */ +#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */ +#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */ +#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */ +#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */ +#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */ +#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */ +#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */ +#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */ + +/* bits definitions */ +/* TLI_SPSZ */ +#define TLI_SPSZ_VPSZ BITS(0,11) /*!< size of the vertical synchronous pulse */ +#define TLI_SPSZ_HPSZ BITS(16,27) /*!< size of the horizontal synchronous pulse */ + +/* TLI_BPSZ */ +#define TLI_BPSZ_VBPSZ BITS(0,11) /*!< size of the vertical back porch plus synchronous pulse */ +#define TLI_BPSZ_HBPSZ BITS(16,27) /*!< size of the horizontal back porch plus synchronous pulse */ + +/* TLI_ASZ */ +#define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */ +#define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */ + +/* TLI_SPSZ */ +#define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */ +#define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */ + +/* TLI_CTL */ +#define TLI_CTL_TLIEN BIT(0) /*!< TLI enable bit */ +#define TLI_CTL_BDB BITS(4,6) /*!< blue channel dither bits number */ +#define TLI_CTL_GDB BITS(8,10) /*!< green channel dither bits number */ +#define TLI_CTL_RDB BITS(12,14) /*!< red channel dither bits number */ +#define TLI_CTL_DFEN BIT(16) /*!< dither function enable */ +#define TLI_CTL_CLKPS BIT(28) /*!< pixel clock polarity selection */ +#define TLI_CTL_DEPS BIT(29) /*!< data enable polarity selection */ +#define TLI_CTL_VPPS BIT(30) /*!< vertical pulse polarity selection */ +#define TLI_CTL_HPPS BIT(31) /*!< horizontal pulse polarity selection */ + +/* TLI_RL */ +#define TLI_RL_RQR BIT(0) /*!< request reload */ +#define TLI_RL_FBR BIT(1) /*!< frame blank reload */ + +/* TLI_BGC */ +#define TLI_BGC_BVB BITS(0,7) /*!< background value blue */ +#define TLI_BGC_BVG BITS(8,15) /*!< background value green */ +#define TLI_BGC_BVR BITS(16,23) /*!< background value red */ + +/* TLI_INTEN */ +#define TLI_INTEN_LMIE BIT(0) /*!< line mark interrupt enable */ +#define TLI_INTEN_FEIE BIT(1) /*!< FIFO error interrupt enable */ +#define TLI_INTEN_TEIE BIT(2) /*!< transaction error interrupt enable */ +#define TLI_INTEN_LCRIE BIT(3) /*!< layer configuration reloaded interrupt enable */ + +/* TLI_INTF */ +#define TLI_INTF_LMF BIT(0) /*!< line mark flag */ +#define TLI_INTF_FEF BIT(1) /*!< FIFO error flag */ +#define TLI_INTF_TEF BIT(2) /*!< transaction error flag */ +#define TLI_INTF_LCRF BIT(3) /*!< layer configuration reloaded flag */ + +/* TLI_INTC */ +#define TLI_INTC_LMC BIT(0) /*!< line mark flag clear */ +#define TLI_INTC_FEC BIT(1) /*!< FIFO error flag clear */ +#define TLI_INTC_TEC BIT(2) /*!< transaction error flag clear */ +#define TLI_INTC_LCRC BIT(3) /*!< layer configuration reloaded flag clear */ + +/* TLI_LM */ +#define TLI_LM_LM BITS(0,10) /*!< line mark value */ + +/* TLI_CPPOS */ +#define TLI_CPPOS_VPOS BITS(0,15) /*!< vertical position */ +#define TLI_CPPOS_HPOS BITS(16,31) /*!< horizontal position */ + +/* TLI_STAT */ +#define TLI_STAT_VDE BIT(0) /*!< current VDE status */ +#define TLI_STAT_HDE BIT(1) /*!< current HDE status */ +#define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */ +#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */ + +/* TLI_LxCTL */ +#define TLI_LxCTL_LEN BIT(0) /*!< layer enable */ +#define TLI_LxCTL_CKEYEN BIT(1) /*!< color keying enable */ +#define TLI_LxCTL_LUTEN BIT(4) /*!< LUT enable */ + +/* TLI_LxHPOS */ +#define TLI_LxHPOS_WLP BITS(0,11) /*!< window left position */ +#define TLI_LxHPOS_WRP BITS(16,27) /*!< window right position */ + +/* TLI_LxVPOS */ +#define TLI_LxVPOS_WTP BITS(0,11) /*!< window top position */ +#define TLI_LxVPOS_WBP BITS(16,27) /*!< window bottom position */ + +/* TLI_LxCKEY */ +#define TLI_LxCKEY_CKEYB BITS(0,7) /*!< color key blue */ +#define TLI_LxCKEY_CKEYG BITS(8,15) /*!< color key green */ +#define TLI_LxCKEY_CKEYR BITS(16,23) /*!< color key red */ + +/* TLI_LxPPF */ +#define TLI_LxPPF_PPF BITS(0,2) /*!< packeted pixel format */ + +/* TLI_LxSA */ +#define TLI_LxSA_SA BITS(0,7) /*!< specified alpha */ + +/* TLI_LxDC */ +#define TLI_LxDC_DCB BITS(0,7) /*!< the default color blue */ +#define TLI_LxDC_DCG BITS(8,15) /*!< the default color green */ +#define TLI_LxDC_DCR BITS(16,23) /*!< the default color red */ +#define TLI_LxDC_DCA BITS(24,31) /*!< the default color alpha */ + +/* TLI_LxBLEND */ +#define TLI_LxBLEND_ACF2 BITS(0,2) /*!< alpha calculation factor 2 of blending method */ +#define TLI_LxBLEND_ACF1 BITS(8,10) /*!< alpha calculation factor 1 of blending method */ + +/* TLI_LxFBADDR */ +#define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */ + +/* TLI_LxFLLEN */ +#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */ +#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */ + +/* TLI_LxFTLN */ +#define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */ + +/* TLI_LxLUT */ +#define TLI_LxLUT_TB BITS(0,7) /*!< blue channel of a LUT entry */ +#define TLI_LxLUT_TG BITS(8,15) /*!< green channel of a LUT entry */ +#define TLI_LxLUT_TR BITS(16,23) /*!< red channel of a LUT entry */ +#define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */ + +/* constants definitions */ +/* TLI parameter struct definitions */ +typedef struct { + uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ + uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ + uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ + uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ + uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ + uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ + uint32_t totalsz_vtsz; /*!< vertical total size of the display */ + uint32_t totalsz_htsz; /*!< horizontal total size of the display */ + uint32_t backcolor_red; /*!< background value red */ + uint32_t backcolor_green; /*!< background value green */ + uint32_t backcolor_blue; /*!< background value blue */ + uint32_t signalpolarity_hs; /*!< horizontal pulse polarity selection */ + uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ + uint32_t signalpolarity_de; /*!< data enable polarity selection */ + uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ +} tli_parameter_struct; + +/* TLI layer parameter struct definitions */ +typedef struct { + uint16_t layer_window_rightpos; /*!< window right position */ + uint16_t layer_window_leftpos; /*!< window left position */ + uint16_t layer_window_bottompos; /*!< window bottom position */ + uint16_t layer_window_toppos; /*!< window top position */ + uint32_t layer_ppf; /*!< packeted pixel format */ + uint8_t layer_sa; /*!< specified alpha */ + uint8_t layer_default_alpha; /*!< the default color alpha */ + uint8_t layer_default_red; /*!< the default color red */ + uint8_t layer_default_green; /*!< the default color green */ + uint8_t layer_default_blue; /*!< the default color blue */ + uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ + uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ + uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ + uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ + uint16_t layer_frame_line_length; /*!< frame line length */ + uint16_t layer_frame_total_line_number; /*!< frame total line number */ +} tli_layer_parameter_struct; + +/* TLI layer LUT parameter struct definitions */ +typedef struct { + uint32_t layer_table_addr; /*!< look up table write address */ + uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ + uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ + uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ +} tli_layer_lut_parameter_struct; + +/* packeted pixel format */ +typedef enum { + LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +} tli_layer_ppf_enum; + +/* TLI flags */ +#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ +#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */ +#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */ +#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */ +#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */ +#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */ +#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */ +#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */ + +/* TLI interrupt enable or disable */ +#define TLI_INT_LM BIT(0) /*!< line mark interrupt */ +#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */ +#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */ +#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */ + +/* TLI interrupt flag */ +#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */ +#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */ +#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */ +#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */ + +/* layer reload configure */ +#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ +#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ + +/* dither function */ +#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ +#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ + +/* horizontal pulse polarity selection */ +#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ +#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ + +/* vertical pulse polarity selection */ +#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ +#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ + +/* pixel clock polarity selection */ +#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ +#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ + +/* data enable polarity selection */ +#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ +#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ + +/* alpha calculation factor 1 of blending method */ +#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) +#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ +#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ + +/* alpha calculation factor 2 of blending method */ +#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ +#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ + +/* function declarations */ +/* initialization functions, TLI enable or disable, TLI reload mode configuration */ +/* deinitialize TLI registers */ +void tli_deinit(void); +/* initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined */ +void tli_struct_para_init(tli_parameter_struct *tli_struct); +/* initialize TLI */ +void tli_init(tli_parameter_struct *tli_struct); +/* configure TLI dither function */ +void tli_dither_config(uint8_t dither_stat); +/* enable TLI */ +void tli_enable(void); +/* disable TLI */ +void tli_disable(void); +/* configurate TLI reload mode */ +void tli_reload_config(uint8_t reload_mod); + +/* TLI layer configuration functions */ +/* initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined */ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); +/* initialize TLI layer */ +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct); +/* reconfigure window position */ +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined */ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer LUT */ +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer color key */ +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey); +/* enable TLI layer */ +void tli_layer_enable(uint32_t layerx); +/* disable TLI layer */ +void tli_layer_disable(uint32_t layerx); +/* enable TLI layer color keying */ +void tli_color_key_enable(uint32_t layerx); +/* disable TLI layer color keying */ +void tli_color_key_disable(uint32_t layerx); +/* enable TLI layer LUT */ +void tli_lut_enable(uint32_t layerx); +/* disable TLI layer LUT */ +void tli_lut_disable(uint32_t layerx); + +/* set line mark value */ +void tli_line_mark_set(uint16_t line_num); +/* get current displayed position */ +uint32_t tli_current_pos_get(void); + +/* flag and interrupt functions */ +/* enable TLI interrupt */ +void tli_interrupt_enable(uint32_t int_flag); +/* disable TLI interrupt */ +void tli_interrupt_disable(uint32_t int_flag); +/* get TLI interrupt flag */ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag); +/* clear TLI interrupt flag */ +void tli_interrupt_flag_clear(uint32_t int_flag); +/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ +FlagStatus tli_flag_get(uint32_t flag); + +#endif /* GD32F4XX_TLI_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h new file mode 100644 index 0000000..5c1ce6e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h @@ -0,0 +1,103 @@ +/*! + \file gd32f4xx_trng.h + \brief definitions for the TRNG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TRNG_H +#define GD32F4XX_TRNG_H + +#include "gd32f4xx.h" + +/* TRNG definitions */ +#define TRNG TRNG_BASE + +/* registers definitions */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ + +/* bits definitions */ +/* TRNG_CTL */ +#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ + +/* TRNG_STAT */ +#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ +#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */ +#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */ +#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */ +#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ + +/* TRNG_DATA */ +#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */ + +/* constants definitions */ +/* TRNG status flag */ +typedef enum { + TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ + TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ + TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ +} trng_flag_enum; + +/* TRNG inerrupt flag */ +typedef enum { + TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ + TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ +} trng_int_flag_enum; + +/* function declarations */ +/* initialization functions */ +/* reset TRNG */ +void trng_deinit(void); +/* enable TRNG */ +void trng_enable(void); +/* disable TRNG */ +void trng_disable(void); +/* get the true random data */ +uint32_t trng_get_true_random_data(void); + +/* interrupt & flag functions */ +/* enable TRNG interrupt */ +void trng_interrupt_enable(void); +/* disable TRNG interrupt */ +void trng_interrupt_disable(void); +/* get TRNG flag status */ +FlagStatus trng_flag_get(trng_flag_enum flag); +/* get TRNG interrupt flag status */ +FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); +/* clear TRNG interrupt flag status */ +void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); + +#endif /* GD32F4XX_TRNG_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h new file mode 100644 index 0000000..9e8fb17 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h @@ -0,0 +1,492 @@ +/*! + \file gd32f4xx_usart.h + \brief definitions for the USART + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_USART_H +#define GD32F4XX_USART_H + +#include "gd32f4xx.h" + +/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ +#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ +#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ +#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */ +#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */ +#define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */ +#define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */ + +/* registers definitions */ +#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ +#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ +#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ +#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ +#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ +#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ + +/* bits definitions */ +/* USARTx_STAT0 */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_CTL3 */ +#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_STAT1 */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ + +/* USARTx_CHC */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ +#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ + +/* USART flags */ +typedef enum { + /* flags in STAT0 register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in STAT1 register */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ + /* flags in CHC register */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ +} usart_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in CTL3 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ +} usart_interrupt_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ +} usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ +} usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversampling mode definitions */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */ +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART one sample bit method configure */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ +#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ + +/* break frame coherence mode */ +#define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */ +#define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */ + +/* USART parity check coherence mode */ +#define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1)) +#define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */ +#define USART_PCM_EN CHC_PCM(1) /*!< check the parity */ + +/* USART hardware flow control coherence mode */ +#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ +#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure usart baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure usart parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure usart word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure usart stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable usart */ +void usart_enable(uint32_t usart_periph); +/* disable usart */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable CK pin in synchronous mode */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* disable CK pin in synchronous mode */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* coherence control */ +/* configure break frame coherence mode */ +void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm); +/* configure parity check coherence mode */ +void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); +/* configure hardware flow control coherence mode */ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); + +/* DMA communication */ +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag & interrupt functions */ +/* get flag in STAT0/STAT1 register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT0/STAT1 register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); + +#endif /* GD32F4XX_USART_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h new file mode 100644 index 0000000..7a7735c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h @@ -0,0 +1,94 @@ +/*! + \file gd32f4xx_wwdgt.h + \brief definitions for the WWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_WWDGT_H +#define GD32F4XX_WWDGT_H + +#include "gd32f4xx.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); + +#endif /* GD32F4XX_WWDGT_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h new file mode 100644 index 0000000..56f64bf --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f4xx.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F4xx Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F4XX_H +#define SYSTEM_GD32F4XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F4XX_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h new file mode 100644 index 0000000..a64d10c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h @@ -0,0 +1,68 @@ +/*! + \file cdc_acm_core.h + \brief the header file of cdc acm driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CDC_ACM_CORE_H +#define __CDC_ACM_CORE_H + +#include "usbd_enum.h" +#include "usb_cdc.h" + +#define USB_CDC_RX_LEN USB_CDC_DATA_PACKET_SIZE + +typedef struct { + uint8_t packet_sent; + uint8_t packet_receive; + + uint8_t data[USB_CDC_RX_LEN]; + uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; + + uint32_t receive_length; + + acm_line line_coding; +} usb_cdc_handler; + +extern usb_desc cdc_desc; +extern usb_class_core cdc_class; + +/* function declarations */ +/* check CDC ACM is ready for data transfer */ +uint8_t cdc_acm_check_ready(usb_dev *udev); +/* send CDC ACM data */ +void cdc_acm_data_send(usb_dev *udev); +/* receive CDC ACM data */ +void cdc_acm_data_receive(usb_dev *udev); + +#endif /* __CDC_ACM_CORE_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h new file mode 100644 index 0000000..fa6bd8e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h @@ -0,0 +1,358 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#ifdef USE_DEVICE_MODE + #include "usbd_conf.h" +#endif /* USE_DEVICE_MODE */ + +#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */ +#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */ + +enum _usb_mode { + DEVICE_MODE = 0U, /*!< device mode */ + HOST_MODE, /*!< host mode */ + OTG_MODE /*!< OTG mode */ +}; + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0U, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0U, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ + uint8_t lpm_enable; /*!< USB link power mode(LPM) */ + uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */ + uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */ + uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */ + uint32_t base_reg; /*!< base register address */ +} usb_core_basic; + +#ifdef USE_DEVICE_MODE + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configure descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */ + uint8_t *qualifier_desc; /*!< qualifier descriptor */ +#endif + + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero length package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet length */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet length */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ + + uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out) (usb_dev *udev); + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_control control; /*!< USB control information */ + usb_desc *desc; /*!< USB descriptors pointer */ + usb_class_core *class_core; /*!< class driver */ + void *class_data[USBD_ITF_MAX_NUM]; /*!< class data pointer */ + void *user_data; /*!< user data pointer */ + void *pdata; /*!< reserved data pointer */ +} usb_perp_dev; + +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + +typedef enum _usb_pipe_status +{ + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_urb_state +{ + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL, + URB_PING +} usb_urb_state; + +typedef struct _usb_pipe +{ + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + __IO uint8_t supp_ping; + __IO uint8_t do_ping; + __IO uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + +typedef struct _usb_host_drv +{ + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; + void *data; +} usb_host_drv; + +#endif /* USE_HOST_MODE */ + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + +#ifdef USE_DEVICE_MODE + usb_perp_dev dev; /*!< USB peripheral device */ +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + usb_host_drv host; +#endif /* USE_HOST_MODE */ +} usb_core_driver; + +/* static inline function definitions */ + +/*! + \brief get the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; +} + +/*! + \brief set USB RX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] size: assigned FIFO size + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size) +{ + usb_regs->gr->GRFLEN = size; +} + +/*! + \brief enable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs) +{ + /* enable USB global interrupt */ + usb_regs->gr->GAHBCS |= GAHBCS_GINTEN; +} + +/*! + \brief disable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) +{ + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; +} + +/* function declarations */ +/* configure core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); +/* set endpoint or channel TX FIFO size */ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); +/* set USB current mode */ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode); + +#endif /* __DRV_USB_CORE_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h new file mode 100644 index 0000000..d891b43 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h @@ -0,0 +1,199 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "usbd_conf.h" +#include "drv_usb_core.h" + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +/* static inline function definitions */ + +/*! + \brief configure the USB device to be disconnected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief configure the USB device to be connected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to USB device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4U; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16U; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + +/*! + \brief set remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/* function declarations */ +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); +/* active the USB endpoint 0 transaction */ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc); +/* active the USB transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); +/* deactivate the USB transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); +/* set the USB transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); +/* clear the USB transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); +/* active remote wakeup signaling */ +void usb_rwkup_active (usb_core_driver *udev); +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); +/* USB device suspend */ +void usb_dev_suspend (usb_core_driver *udev); +/* stop the device and clean up FIFOs */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h new file mode 100644 index 0000000..bd1c89c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h @@ -0,0 +1,64 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* function declarations */ +/* configure USB clock */ +void usb_rcu_config (void); +/* configure USB data line gpio */ +void usb_gpio_config (void); +/* configure USB interrupt */ +void usb_intr_config (void); +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); +/* delay in milliseconds */ +void usb_mdelay (const uint32_t msec); +/* configures system clock after wakeup from STOP mode */ +void system_clk_config_stop(void); +#ifdef USE_HOST_MODE +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h new file mode 100644 index 0000000..4c57347 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h @@ -0,0 +1,664 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ +#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ +#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum +{ + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH, /*!< USB speed high */ +}; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct +{ + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + + +typedef struct +{ + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct +{ + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct +{ + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< device threshold control 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ +} usb_erout; + +typedef struct _usb_regs +{ + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ +#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_DMAER BIT(2) /*!< DMA error */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* host channel-x DMA address register bits definitions */ +#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[2]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x DMA address register bits definitions */ +#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device OUT endpoint-x DMA address register bits definitions */ +#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /* OUT data packet received */ +#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2U /*!< embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ +#define EP4_OUT ((uint8_t)0x04) /*!< endpoint out 4 */ +#define EP4_IN ((uint8_t)0x84) /*!< endpoint in 4 */ +#define EP5_OUT ((uint8_t)0x05) /*!< endpoint out 5 */ +#define EP5_IN ((uint8_t)0x85) /*!< endpoint in 5 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h new file mode 100644 index 0000000..c118785 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h @@ -0,0 +1,54 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +void usbd_isr (usb_core_driver *udev); + +#ifdef USB_HS_DEDICATED_EP1_ENABLED +/* USB dedicated IN endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev); +/* USB dedicated OUT endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev); +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +#endif /* __DRV_USBD_INT_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h new file mode 100644 index 0000000..7301eac --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h @@ -0,0 +1,182 @@ +/*! + \file usb_cdc.h + \brief the header file of communication device class standard + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#include "usb_ch9_std.h" + +/* communications device class code */ +#define USB_CLASS_CDC 0x02U + +/* communications interface class control protocol codes */ +#define USB_CDC_PROTOCOL_NONE 0x00U +#define USB_CDC_PROTOCOL_AT 0x01U +#define USB_CDC_PROTOCOL_VENDOR 0xFFU + +/* data interface class code */ +#define USB_CLASS_DATA 0x0AU + +#define USB_DESCTYPE_CDC_ACM 0x21U +#define USB_DESCTYPE_CS_INTERFACE 0x24U + +#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43U + +/* class-specific notification codes for pstn subclasses */ +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20U + +/* class-specific request codes */ +#define SEND_ENCAPSULATED_COMMAND 0x00U +#define GET_ENCAPSULATED_RESPONSE 0x01U +#define SET_COMM_FEATURE 0x02U +#define GET_COMM_FEATURE 0x03U +#define CLEAR_COMM_FEATURE 0x04U + +#define SET_AUX_LINE_STATE 0x10U +#define SET_HOOK_STATE 0x11U +#define PULSE_SETUP 0x12U +#define SEND_PULSE 0x13U +#define SET_PULSE_TIME 0x14U +#define RING_AUX_JACK 0x15U + +#define SET_LINE_CODING 0x20U +#define GET_LINE_CODING 0x21U +#define SET_CONTROL_LINE_STATE 0x22U +#define SEND_BREAK 0x23U +#define NO_CMD 0xFFU + +#define SET_RINGER_PARMS 0x30U +#define GET_RINGER_PARMS 0x31U +#define SET_OPERATION_PARMS 0x32U +#define GET_OPERATION_PARMS 0x33U +#define SET_LINE_PARMS 0x34U +#define GET_LINE_PARMS 0x35U +#define DIAL_DIGITS 0x36U +#define SET_UNIT_PARAMETER 0x37U +#define GET_UNIT_PARAMETER 0x38U +#define CLEAR_UNIT_PARAMETER 0x39U +#define GET_PROFILE 0x3AU + +#define SET_ETHERNET_MULTICAST_FILTERS 0x40U +#define SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41U +#define GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42U +#define SET_ETHERNET_PACKET_FILTER 0x43U +#define GET_ETHERNET_STATISTIC 0x44U + +#define SET_ATM_DATA_FORMAT 0x50U +#define GET_ATM_DEVICE_STATISTICS 0x51U +#define SET_ATM_DEFAULT_VC 0x52U +#define GET_ATM_VC_STATISTICS 0x53U + +/* wValue for set control line state */ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002U +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000U +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001U +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000U + +/* CDC subclass code */ +enum usb_cdc_subclass { + USB_CDC_SUBCLASS_RESERVED = 0U, /*!< reserved */ + USB_CDC_SUBCLASS_DLCM, /*!< direct line control mode */ + USB_CDC_SUBCLASS_ACM, /*!< abstract control mode */ + USB_CDC_SUBCLASS_TCM, /*!< telephone control mode */ + USB_CDC_SUBCLASS_MCM, /*!< multichannel control model */ + USB_CDC_SUBCLASS_CCM, /*!< CAPI control model */ + USB_CDC_SUBCLASS_ENCM, /*!< ethernet networking control model */ + USB_CDC_SUBCLASS_ANCM /*!< ATM networking control model */ +}; + +#pragma pack(1) + +/* cdc acm line coding structure */ +typedef struct { + uint32_t dwDTERate; /*!< data terminal rate */ + uint8_t bCharFormat; /*!< stop bits */ + uint8_t bParityType; /*!< parity */ + uint8_t bDataBits; /*!< data bits */ +} acm_line; + +/* notification structure */ +typedef struct { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bNotification; /*!< communication interface class notifications */ + uint16_t wValue; /*!< value of notification */ + uint16_t wIndex; /*!< index of interface */ + uint16_t wLength; /*!< length of notification data */ +} acm_notification; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */ + uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */ +} usb_desc_header_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */ + uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */ +} usb_desc_call_managment_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D1 */ +} usb_desc_acm_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union function descriptor */ + uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */ + uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */ +} usb_desc_union_func; + +#pragma pack() + +typedef struct { + usb_desc_config config; + usb_desc_itf cmd_itf; + usb_desc_header_func cdc_header; + usb_desc_call_managment_func cdc_call_managment; + usb_desc_acm_func cdc_acm; + usb_desc_union_func cdc_union; + usb_desc_ep cdc_cmd_endpoint; + usb_desc_itf cdc_data_interface; + usb_desc_ep cdc_out_endpoint; + usb_desc_ep cdc_in_endpoint; +} usb_cdc_desc_config_set; + +#endif /* __USB_CDC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h new file mode 100644 index 0000000..89e6164 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h @@ -0,0 +1,250 @@ +/*! + \file usb_ch9_std.h + \brief USB 2.0 standard defines + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CH9_STD_H +#define __USB_CH9_STD_H + +#include "usb_conf.h" + +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ +#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ +#define USB_IAD_DESC_LEN 0x08U /*!< USB IAD descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ +#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ +#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ +#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ +#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ + +#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ +#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ + +/* bit 4..0 of bmRequestType: recipient type */ +enum _usb_recp_type { + USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ + USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ + USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ + USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ +}; + +/* bRequest value */ +enum _usb_request { + USB_GET_STATUS = 0x0U, /*!< USB get status request */ + USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ + USB_RESERVED2 = 0x2U, + USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ + USB_RESERVED4 = 0x4U, + USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ + USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ + USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ + USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ + USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ + USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ + USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ + USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ +}; + +/* descriptor types of USB specifications */ +enum _usb_desctype { + USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ + USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ + USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ + USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ + USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ + USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualifier descriptor type */ + USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ + USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ + USB_DESCTYPE_IAD = 0xBU, /*!< USB interface association descriptor type */ + USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ +}; + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +/* bits 1..0 : transfer type */ +enum _usbx_type { + USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ + USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ + USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ + USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ +}; + +/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_NOSYNC 0x00U /*!< No Synchronization */ +#define USB_EP_ATTR_ASYNC 0x04U /*!< Asynchronous */ +#define USB_EP_ATTR_ADAPTIVE 0x08U /*!< Adaptive */ +#define USB_EP_ATTR_SYNC 0x0CU /*!< Synchronous */ +#define USB_EP_ATTR_SYNCTYPE 0x0CU /*!< Synchronous type */ + +/* bits 5..4 : usage type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_DATA 0x00U /*!< Data endpoint */ +#define USB_EP_ATTR_FEEDBACK 0x10U /*!< Feedback endpoint */ +#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20U /*!< Implicit feedback Data endpoint */ +#define USB_EP_ATTR_USAGETYPE 0x30U /*!< Usage type */ + +/* endpoint max packet size bits12..11 */ +#define USB_EP_MPS_ADD_0 (0x00 << 11) /*!< None(1 transaction per microframe */ +#define USB_EP_MPS_ADD_1 (0x01 << 11) /*!< 1 additional(2 transaction per microframe */ +#define USB_EP_MPS_ADD_2 (0x02 << 11) /*!< 2 additional(3 transaction per microframe */ + +#define FEATURE_SELECTOR_EP 0x00U /*!< USB endpoint feature selector */ +#define FEATURE_SELECTOR_DEV 0x01U /*!< USB device feature selector */ +#define FEATURE_SELECTOR_REMOTEWAKEUP 0x01U /*!< USB feature selector remote wakeup */ + +#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) +#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DEFAULT_CONFIG 0U + +/* USB classes */ +#define USB_CLASS_HID 0x03U /*!< USB HID class */ +#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ + +/* use the following values when USB host need to get descriptor */ +#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) + +/* as per USB specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#pragma pack(1) + +/* USB standard device request structure */ +typedef struct _usb_req { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ +} usb_req; + +/* USB setup packet define */ +typedef union _usb_setup { + uint8_t data[8]; + + usb_req req; +} usb_setup; + +/* USB descriptor defines */ + +typedef struct _usb_desc_header { + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_desc_header; + +typedef struct _usb_desc_dev { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_desc_dev; + +typedef struct _usb_desc_config { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_desc_config; + +typedef struct _usb_desc_itf { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_desc_itf; + +typedef struct _usb_desc_ep { + usb_desc_header header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_desc_ep; + +typedef struct _usb_desc_LANGID { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +} usb_desc_LANGID; + +typedef struct _usb_desc_str { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t unicode_string[128]; /*!< unicode string data */ +} usb_desc_str; + +#pragma pack() + +/* compute string descriptor length */ +#define USB_STRING_LEN(unicode_chars) (sizeof(usb_desc_header) + ((unicode_chars) << 1U)) + +#endif /* __USB_CH9_STD_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h new file mode 100644 index 0000000..e39a38f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h @@ -0,0 +1,105 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions prototype + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0U, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1U, /*!< default status */ + USBD_ADDRESSED = 2U, /*!< address send status */ + USBD_CONFIGURED = 3U, /*!< configured status */ + USBD_SUSPENDED = 4U /*!< suspended status */ +}; + +/* static inline function definitions */ + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +__STATIC_INLINE void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +__STATIC_INLINE uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return (uint16_t)udev->dev.transc_out[ep_num].xfer_count; +} + +/* function declarations */ +/* initializes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core); +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); +/* device connect */ +void usbd_connect (usb_core_driver *udev); +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +#endif /* __USBD_CORE_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h new file mode 100644 index 0000000..bd83cce --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h @@ -0,0 +1,103 @@ +/*! + \file usbd_enum.h + \brief USB enumeration definitions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_ENUM_H +#define __USBD_ENUM_H + +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +#ifndef NULL + #define NULL 0U +#endif + +typedef enum _usb_reqsta { + REQ_SUPP = 0x0U, /* request support */ + REQ_NOTSUPP = 0x1U, /* request not support */ +} usb_reqsta; + +/* string descriptor index */ +enum _str_index +{ + STR_IDX_LANGID = 0x0U, /* language ID string index */ + STR_IDX_MFC = 0x1U, /* manufacturer string index */ + STR_IDX_PRODUCT = 0x2U, /* product string index */ + STR_IDX_SERIAL = 0x3U, /* serial string index */ + STR_IDX_CONFIG = 0x4U, /* configuration string index */ + STR_IDX_ITF = 0x5U, /* interface string index */ + STR_IDX_MAX = 0xEFU, /* string maximum index */ +}; + +typedef enum _usb_pwrsta { + USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ + USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ +} usb_pwrsta; + +typedef enum _usb_feature +{ + USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ + USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ + USB_FEATURE_TEST_MODE = 0x2U, /* USB has endpoint test mode feature */ +} usb_feature; + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +/* USB device exported macros */ +#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) + +#define DEVICE_ID1 (0x1FFF7A10U) /* device ID1 */ +#define DEVICE_ID2 (0x1FFF7A14U) /* device ID2 */ +#define DEVICE_ID3 (0x1FFF7A18U) /* device ID3 */ + +#define DEVICE_ID (0x40023D00U) + +/* function declarations */ +/* handle USB standard device request */ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req); +/* handle USB device class request */ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req); +/* handle USB vendor request */ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req); +/* handle USB enumeration error */ +void usbd_enum_error (usb_core_driver *udev, usb_req *req); +/* convert hex 32bits value into unicode char */ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len); +/* get serial string */ +void serial_string_get (uint16_t *unicode_str); + +#endif /* __USBD_ENUM_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h new file mode 100644 index 0000000..caba07b --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h @@ -0,0 +1,58 @@ +/*! + \file usbd_transc.h + \brief USB transaction core functions prototype + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_TRANSC_H +#define __USBD_TRANSC_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB send data in the control transaction */ +usbd_status usbd_ctl_send (usb_core_driver *udev); +/* USB receive data in control transaction */ +usbd_status usbd_ctl_recev (usb_core_driver *udev); +/* USB send control transaction status */ +usbd_status usbd_ctl_status_send (usb_core_driver *udev); +/* USB control receive status */ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev); +/* USB setup stage processing */ +uint8_t usbd_setup_transc (usb_core_driver *udev); +/* data out stage processing */ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num); +/* data in stage processing */ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_TRANSC_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c new file mode 100644 index 0000000..be2524f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c @@ -0,0 +1,1203 @@ +/*! + \file gd32f4xx_adc.c + \brief ADC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_adc.h" + +#define ROUTINE_TRIGGER_MODE ((uint32_t)28U) +#define INSERTED_TRIGGER_MODE ((uint32_t)20U) +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC routine channel macro */ +#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) + +/*! + \brief reset ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_deinit(void) +{ + rcu_periph_reset_enable(RCU_ADCRST); + rcu_periph_reset_disable(RCU_ADCRST); +} + +/*! + \brief configure the ADC clock for all the ADCs + \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: + \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 + \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 + \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 + \arg ADC_ADCCK_PCLK2_DIV8: PCLK2 div8 + \arg ADC_ADCCK_HCLK_DIV5: HCLK div5 + \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 + \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 + \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 + \param[out] none + \retval none +*/ +void adc_clock_config(uint32_t prescaler) +{ + ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_ADCCK); + ADC_SYNCCTL |= (uint32_t) prescaler; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + if(0U != (function & ADC_SCAN_MODE)) { + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* enable inserted sequence convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + } else { + if(0U != (function & ADC_SCAN_MODE)) { + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* disable inserted sequence convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment) { + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + } else { + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { + } +} + +/*! + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: + \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 + \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { + /* enable ADC0 Vbat channel */ + ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { + /* enable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; + } + } else { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { + /* disable ADC0 Vbat channel */ + ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { + /* disable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; + } + } +} + +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) +{ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief when DMA=1, the DMA engine issues a request at end of each routine conversion + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); +} + +/*! + \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for routine sequence ,the number has no effect for inserted sequence + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) +{ + /* disable discontinuous mode of routine & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + if((length <= 8U) && (length >= 1U)) { + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + /* enable routine sequence discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted sequence discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of routine & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of routine sequence or inserted sequence + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] length: the length of the channel + routine channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + if((length >= 1U) && (length <= 16U)) { + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + case ADC_INSERTED_CHANNEL: + if((length >= 1U) && (length <= 4U)) { + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + default: + break; + } +} + +/*! + \brief configure ADC routine channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq, sampt; + + /* ADC routine sequence config */ + if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) { + /* the routine sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)); + ADC_RSQ2(adc_periph) = rsq; + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) { + /* the routine sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) { + /* the routine sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + } else { + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the routine sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the routine sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + /* get inserted sequence length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */ + if(rank < 4U) { + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the inserted sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the inserted sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH) { + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source + for routine sequence: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence + for inserted sequence: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC external trigger + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] trigger_mode: external trigger mode + only one parameter can be selected which is shown as below: + \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable + \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger + \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger + \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE); + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE); + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* enable ADC routine sequence software trigger */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; + break; + case ADC_INSERTED_CHANNEL: + /* enable ADC inserted sequence software trigger */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; + break; + default: + break; + } +} + +/*! + \brief configure end of conversion mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] end_selection: end of conversion mode + only one parameter can be selected which is shown as below: + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically. + \param[out] none + \retval none +*/ +void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) +{ + switch(end_selection) { + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of routine conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; + } +} + +/*! + \brief read ADC routine data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_routine_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel) { + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief disable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); +} + +/*! + \brief enable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); + + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; +} + +/*! + \brief configure ADC analog watchdog sequence channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: the sequence use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence + \param[out] none + \retval none +*/ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* routine channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_ROUTINE_INSERTED_CHANNEL: + /* routine and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: the sequence use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence) +{ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* disable ADC analog watchdog routine sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); + break; + case ADC_INSERTED_CHANNEL: + /* disable ADC analog watchdog inserted sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); + break; + case ADC_ROUTINE_INSERTED_CHANNEL: + /* disable ADC analog watchdog routine and inserted sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); + break; + default: + break; + } +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + /* configure ADC analog watchdog low threshold */ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + /* configure ADC analog watchdog high threshold */ + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag) { + reval = SET; + } + return reval; + +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)) { + reval = SET; + } + return reval; +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt) { + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of sequence conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted sequence conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_ROVF: + /* get the ADC routine data register overflow interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; + if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc status flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + switch(adc_interrupt) { + case ADC_INT_WDE: + /* enable analog watchdog interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + break; + case ADC_INT_EOC: + /* enable end of sequence conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + break; + case ADC_INT_EOIC: + /* enable end of inserted sequence conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_ROVFIE; + break; + default: + break; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + switch(adc_interrupt) { + /* select the interrupt source */ + case ADC_INT_WDE: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); + break; + case ADC_INT_EOC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOCIE); + break; + case ADC_INT_EOIC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOICIE); + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ROVFIE); + break; + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] sync_mode: ADC sync mode + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode + \arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode + \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode + \arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode + \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode + \param[out] none + \retval none +*/ +void adc_sync_mode_config(uint32_t sync_mode) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCM); + ADC_SYNCCTL |= sync_mode; +} + +/*! + \brief configure the delay between 2 sampling phases in ADC sync modes + \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles + \param[out] none + \retval none +*/ +void adc_sync_delay_config(uint32_t sample_delay) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDLY); + ADC_SYNCCTL |= sample_delay; +} + +/*! + \brief configure ADC sync DMA mode selection + \param[in] dma_mode: ADC sync DMA mode + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 + \param[out] none + \retval none +*/ +void adc_sync_dma_config(uint32_t dma_mode) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDMA); + ADC_SYNCCTL |= dma_mode; +} + +/*! + \brief configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] none + \param[out] none + \retval none +*/ +void adc_sync_dma_request_after_last_enable(void) +{ + ADC_SYNCCTL |= ADC_SYNCCTL_SYNCDDM; +} + +/*! + \brief configure ADC sync DMA engine issues requests according to the SYNCDMA bits + \param[in] none + \param[out] none + \retval none +*/ +void adc_sync_dma_request_after_last_disable(void) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDDM); +} + +/*! + \brief read ADC sync routine data register + \param[in] none + \param[out] none + \retval sync routine data +*/ +uint32_t adc_sync_routine_data_read(void) +{ + return (uint32_t)ADC_SYNCDATA; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c new file mode 100644 index 0000000..f0ccaf7 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c @@ -0,0 +1,1021 @@ +/*! + \file gd32f4xx_can.c + \brief CAN driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-07-14, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2021-12-28, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_can.h" + +#define CAN_ERROR_HANDLE(s) do{}while(1) + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ + if(CAN0 == can_periph) { + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } else { + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +} + +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[out] p_struct: the pointer of the specific struct + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void *p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type) { + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = ENABLE; + ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = ENABLE; + ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct *)p_struct)->rx_efid = 0U; + ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct *)p_struct)->rx_fi = 0U; + ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x0400 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered) { + CAN_CTL(can_periph) |= CAN_CTL_TTC; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off management */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery) { + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up) { + CAN_CTL(can_periph) |= CAN_CTL_AWU; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode disable */ + if(ENABLE == can_parameter_init->auto_retrans) { + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; + } + /* receive FIFO overwrite mode disable */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + } + /* transmit FIFO order */ + if(ENABLE == can_parameter_init->trans_fifo_order) { + CAN_CTL(can_periph) |= CAN_CTL_TFO; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + /* check exit initialize mode */ + if(0U != timeout) { + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + } else { + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + } else { + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable) { + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 filter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; + + if(CAN0 == can_periph) { + dbg_periph_enable(DBG_CAN0_HOLD); + } else { + dbg_periph_enable(DBG_CAN1_HOLD); + } +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; + + if(CAN0 == can_periph) { + dbg_periph_disable(DBG_CAN0_HOLD); + } else { + dbg_periph_disable(DBG_CAN1_HOLD); + } +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the TTC mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TTC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlen: 0 - 8 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { + mailbox_number = CAN_MAILBOX0; + } else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { + mailbox_number = CAN_MAILBOX1; + } else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { + mailbox_number = CAN_MAILBOX2; + } else { + mailbox_number = CAN_NOMAILBOX; + } + /* return no mailbox empty */ + if(CAN_NOMAILBOX == mailbox_number) { + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff) { + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + } else { + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + /* check selected mailbox state */ + switch(mailbox_number) { + /* mailbox0 */ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + /* mailbox1 */ + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + /* mailbox2 */ + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + + switch(val) { + /* transmit pending */ + case(CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* mailbox0 transmit succeeded */ + case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + /* mailbox1 transmit succeeded */ + case(CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + /* mailbox2 transmit succeeded */ + case(CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + /* transmit failed */ + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { + } + } else if(CAN_MAILBOX1 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { + } + } else if(CAN_MAILBOX2 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { + } + } else { + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlen: 0 - 8 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff) { + /* get standard identifier */ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + } else { + /* get extended identifier */ + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* filtering index */ + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get receive data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else if(CAN_FIFO1 == fifo_number) { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } else { + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number) { + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + } else if(CAN_FIFO1 == fifo_number) { + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + } else { + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_working_mode + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode) { + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if(CAN_MODE_NORMAL == working_mode) { + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if(CAN_MODE_SLEEP == working_mode) { + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else { + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { + timeout--; + } + /* check state */ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_RXL: RX level + \arg CAN_FLAG_LASTRX: last sample value of RX pin + \arg CAN_FLAG_RS: receiving state + \arg CAN_FLAG_TS: transmitting state + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_SLPWS: sleep working state + \arg CAN_FLAG_IWS: initial working state + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO + \arg CAN_FLAG_TME2: transmit mailbox 2 empty + \arg CAN_FLAG_TME1: transmit mailbox 1 empty + \arg CAN_FLAG_TME0: transmit mailbox 0 empty + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + /* get flag and interrupt enable state */ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag + \arg CAN_INT_FLAG_ERRN: error number interrupt flag + \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag + \arg CAN_INT_FLAG_PERR: passive error interrupt flag + \arg CAN_INT_FLAG_WERR: warning error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + /* get the status of interrupt flag */ + if(flag == CAN_INT_FLAG_RFL0) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); + } else if(flag == CAN_INT_FLAG_RFL1) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); + } else if(flag == CAN_INT_FLAG_ERRN) { + ret1 = can_error_get(can_periph); + } else { + ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); + } + /* get the status of interrupt enable bit */ + ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); + if(ret1 && ret2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c new file mode 100644 index 0000000..753d5f2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c @@ -0,0 +1,130 @@ +/*! + \file gd32f4xx_crc.c + \brief CRC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_crc.h" + +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the value of the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the value of the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write data to the free data register + \param[in] free_data: specified 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values + \param[in] size: size of the array + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++) { + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c new file mode 100644 index 0000000..16573b9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c @@ -0,0 +1,391 @@ +/*! + \file gd32f4xx_ctc.c + \brief CTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/* CTC register bit offset */ +#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) +#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) +#define CTC_REFCAP_OFFSET ((uint32_t)16U) +#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \arg 0x00 - 0x3F + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] hardmode: + only one parameter can be selected which is shown as below: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)hardmode; +} + +/*! + \brief configure reference signal source polarity + \param[in] polarity: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)polarity; +} + +/*! + \brief select reference signal source + \param[in] refs: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] prescaler: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00 - 0xFF + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); +} + +/*! + \brief configure CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000 - 0xFFFF + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)reload_value; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t interrupt) +{ + CTC_CTL0 |= (uint32_t)interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t interrupt) +{ + CTC_CTL0 &= (uint32_t)(~interrupt); +} + +/*! + \brief get CTC interrupt flag + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t interrupt_flag = 0U, intenable = 0U; + + /* check whether the interrupt is enabled */ + if(RESET != (int_flag & CTC_FLAG_MASK)) { + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; + } else { + intenable = CTC_CTL0 & int_flag; + } + + /* get interrupt flag status */ + interrupt_flag = CTC_STAT & int_flag; + + if(interrupt_flag && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC interrupt flag + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t int_flag) +{ + if(RESET != (int_flag & CTC_FLAG_MASK)) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= int_flag; + } +} + +/*! + \brief get CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t flag) +{ + if(RESET != (CTC_STAT & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t flag) +{ + if(RESET != (flag & CTC_FLAG_MASK)) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= flag; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c new file mode 100644 index 0000000..cea8620 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c @@ -0,0 +1,678 @@ +/*! + \file gd32f4xx_dac.c + \brief DAC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dac.h" + +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DEN0; + } else { + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DEN0; + } else { + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDMAEN0; + } else { + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDMAEN0; + } else { + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DBOFF0; + } else { + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DBOFF0; + } else { + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph) { + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + } else { + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8 bit alignment + \arg DAC_ALIGN_12B_R: data right 12 bit alignment + \arg DAC_ALIGN_12B_L: data left 12 bit alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph) { + switch(dac_align) { + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + } else { + switch(dac_align) { + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DTEN0; + } else { + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DTEN0; + } else { + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph: DACx(x = 0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + } else { + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_SWT |= DAC_SWT_SWTR0; + } else { + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_SWT &= ~DAC_SWT_SWTR0; + } else { + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] wave_mode: noise wave mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + } else { + /* configure DAC1 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph: DACx(x = 0,1) + \param[in] bit_width: noise wave bit width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + } else { + /* configure DAC1 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + } else { + /* configure DAC1 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] amplitude: triangle amplitude in DAC triangle noise mode + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + } else { + /* configure DAC1 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} + +/*! + \brief enable DAC concurrent interrupt funcution + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_interrupt_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent interrupt funcution + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_interrupt_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; + DAC_CTL &= (~ctl); +} + +/*! + \brief get the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dac_flag_get(uint32_t dac_periph) +{ + FlagStatus temp_flag = RESET; + if(DAC0 == dac_periph) { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)) { + temp_flag = SET; + } + } else { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)) { + temp_flag = SET; + } + } + return temp_flag; +} + +/*! + \brief clear the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_flag_clear(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_STAT |= DAC_STAT_DDUDR0; + } else { + DAC_STAT |= DAC_STAT_DDUDR1; + } +} + +/*! + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDUDRIE0; + } else { + DAC_CTL |= DAC_CTL_DDUDRIE1; + } +} + +/*! + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + } else { + DAC_CTL &= ~DAC_CTL_DDUDRIE1; + } +} + +/*! + \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) +{ + FlagStatus temp_flag = RESET; + uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + + if(DAC0 == dac_periph) { + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { + temp_flag = SET; + } + } else { + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { + temp_flag = SET; + } + } + return temp_flag; +} + +/*! + \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_flag_clear(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_STAT |= DAC_STAT_DDUDR0; + } else { + DAC_STAT |= DAC_STAT_DDUDR1; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c new file mode 100644 index 0000000..c786be2 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c @@ -0,0 +1,183 @@ +/*! + \file gd32f4xx_dbg.c + \brief DBG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dbg.h" + +#define DBG_RESET_VAL 0x00000000U + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c new file mode 100644 index 0000000..2bce769 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c @@ -0,0 +1,346 @@ +/*! + \file gd32f4xx_dci.c + \brief DCI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dci.h" + +/*! + \brief DCI deinit + \param[in] none + \param[out] none + \retval none +*/ +void dci_deinit(void) +{ + rcu_periph_reset_enable(RCU_DCIRST); + rcu_periph_reset_disable(RCU_DCIRST); +} + +/*! + \brief initialize DCI registers + \param[in] dci_struct: DCI parameter initialization structure + members of the structure and the member values are shown as below: + capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT + colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING + hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH + vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH + frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4 + interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS, + DCI_INTERFACE_FORMAT_12BITS, DCI_INTERFACE_FORMAT_14BITS + \param[out] none + \retval none +*/ +void dci_init(dci_parameter_struct *dci_struct) +{ + uint32_t reg = 0U; + /* disable capture function and DCI */ + DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN); + /* configure DCI parameter */ + reg |= dci_struct->capture_mode; + reg |= dci_struct->clock_polarity; + reg |= dci_struct->hsync_polarity; + reg |= dci_struct->vsync_polarity; + reg |= dci_struct->frame_rate; + reg |= dci_struct->interface_format; + + DCI_CTL = reg; +} + +/*! + \brief enable DCI function + \param[in] none + \param[out] none + \retval none +*/ +void dci_enable(void) +{ + DCI_CTL |= DCI_CTL_DCIEN; +} + +/*! + \brief disable DCI function + \param[in] none + \param[out] none + \retval none +*/ +void dci_disable(void) +{ + DCI_CTL &= ~DCI_CTL_DCIEN; +} + +/*! + \brief enable DCI capture + \param[in] none + \param[out] none + \retval none +*/ +void dci_capture_enable(void) +{ + DCI_CTL |= DCI_CTL_CAP; +} + +/*! + \brief disable DCI capture + \param[in] none + \param[out] none + \retval none +*/ +void dci_capture_disable(void) +{ + DCI_CTL &= ~DCI_CTL_CAP; +} + +/*! + \brief enable DCI jpeg mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_jpeg_enable(void) +{ + DCI_CTL |= DCI_CTL_JM; +} + +/*! + \brief disable DCI jpeg mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_jpeg_disable(void) +{ + DCI_CTL &= ~DCI_CTL_JM; +} + +/*! + \brief enable cropping window function + \param[in] none + \param[out] none + \retval none +*/ +void dci_crop_window_enable(void) +{ + DCI_CTL |= DCI_CTL_WDEN; +} + +/*! + \brief disable cropping window function + \param[in] none + \param[out] none + \retval none +*/ +void dci_crop_window_disable(void) +{ + DCI_CTL &= ~DCI_CTL_WDEN; +} + +/*! + \brief configure DCI cropping window + \param[in] start_x: window horizontal start position + \param[in] start_y: window vertical start position + \param[in] size_width: window horizontal size + \param[in] size_height: window vertical size + \param[out] none + \retval none +*/ +void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) +{ + DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16)); + DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16)); +} + +/*! + \brief enable embedded synchronous mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_embedded_sync_enable(void) +{ + DCI_CTL |= DCI_CTL_ESM; +} + +/*! + \brief disble embedded synchronous mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_embedded_sync_disable(void) +{ + DCI_CTL &= ~DCI_CTL_ESM; +} +/*! + \brief config synchronous codes in embedded synchronous mode + \param[in] frame_start: frame start code in embedded synchronous mode + \param[in] line_start: line start code in embedded synchronous mode + \param[in] line_end: line end code in embedded synchronous mode + \param[in] frame_end: frame end code in embedded synchronous mode + \param[out] none + \retval none +*/ +void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) +{ + DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); +} + +/*! + \brief config synchronous codes unmask in embedded synchronous mode + \param[in] frame_start: frame start code unmask bits in embedded synchronous mode + \param[in] line_start: line start code unmask bits in embedded synchronous mode + \param[in] line_end: line end code unmask bits in embedded synchronous mode + \param[in] frame_end: frame end code unmask bits in embedded synchronous mode + \param[out] none + \retval none +*/ +void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) +{ + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); +} + +/*! + \brief read DCI data register + \param[in] none + \param[out] none + \retval data +*/ +uint32_t dci_data_read(void) +{ + return DCI_DATA; +} + +/*! + \brief get specified flag + \param[in] flag: + \arg DCI_FLAG_HS: HS line status + \arg DCI_FLAG_VS: VS line status + \arg DCI_FLAG_FV:FIFO valid + \arg DCI_FLAG_EF: end of frame flag + \arg DCI_FLAG_OVR: FIFO overrun flag + \arg DCI_FLAG_ESE: embedded synchronous error flag + \arg DCI_FLAG_VSYNC: vsync flag + \arg DCI_FLAG_EL: end of line flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_flag_get(uint32_t flag) +{ + uint32_t stat = 0U; + + if(flag >> 31) { + /* get flag status from DCI_STAT1 register */ + stat = DCI_STAT1; + } else { + /* get flag status from DCI_STAT0 register */ + stat = DCI_STAT0; + } + + if(flag & stat) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief enable specified DCI interrupt + \param[in] interrupt: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_enable(uint32_t interrupt) +{ + DCI_INTEN |= interrupt; +} + +/*! + \brief disable specified DCI interrupt + \param[in] interrupt: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_disable(uint32_t interrupt) +{ + DCI_INTEN &= ~interrupt; +} + +/*! + \brief clear specified interrupt flag + \param[in] int_flag: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_flag_clear(uint32_t int_flag) +{ + DCI_INTC |= int_flag; +} + +/*! + \brief get specified interrupt flag + \param[in] int_flag: + \arg DCI_INT_FLAG_EF: end of frame interrupt flag + \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag + \arg DCI_INT_FLAG_EL: end of line interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_interrupt_flag_get(uint32_t int_flag) +{ + if(RESET == (DCI_INTF & int_flag)) { + return RESET; + } else { + return SET; + } +} + + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c new file mode 100644 index 0000000..c5a1f9e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c @@ -0,0 +1,904 @@ +/*! + \file gd32f4xx_dma.c + \brief DMA driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dma.h" + +/* DMA register bit offset */ +#define CHXCTL_PERIEN_OFFSET ((uint32_t)25U) + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE; + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } +} + +/*! + \brief initialize the DMA single data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->periph_memory_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize the DMA multi data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->memory_burst_width = 0U; + init_struct->periph_burst_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA single data mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA_CHx(x=0..7) + \param[in] init_struct: the data needed to initialize DMA single data mode + periph_addr: peripheral base address + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + memory0_addr: memory base address + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct *init_struct) +{ + uint32_t ctl; + + /* select single data mode */ + DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_MDMEN; + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + + /* configure peripheral and memory transfer width,channel priotity,transfer mode */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); + ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure DMA circular mode */ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; + } +} + +/*! + \brief initialize DMA multi data mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA_CHx(x=0..7) + \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode + periph_addr: peripheral base address + periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + memory0_addr: memory0 base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT + periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT + critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct *init_struct) +{ + uint32_t ctl; + + /* select multi data mode and configure FIFO critical value */ + DMA_CHFCTL(dma_periph, channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + + /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); + ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | + init_struct->periph_burst_width); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure DMA circular mode */ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; + } +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + \arg DMA_CHx(x=0..7) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA Memory0 base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set Memory base address + \arg DMA_CHx(x=0..7) + \param[in] memory_flag: DMA_MEMORY_x(x=0,1) + \param[in] address: Memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) +{ + if(memory_flag) { + DMA_CHM1ADDR(dma_periph, channelx) = address; + } else { + DMA_CHM0ADDR(dma_periph, channelx) = address; + } +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(dma_periph, channelx) = number; +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] mbeat: transfer burst beats + \arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst + \arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst + \arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst + \arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_memory_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MBURST; + ctl |= mbeat; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] pbeat: transfer burst beats + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst + \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst + \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst + \arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_periph_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PBURST; + ctl |= pbeat; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= msize; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= psize; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure memory address generation generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode + \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode + \param[out] none + \retval none +*/ +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } +} + +/*! + \brief configure peripheral address generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode + \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode + \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed + \param[out] none + \retval none +*/ +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral + \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_TM; + ctl |= direction; + + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief DMA switch buffer mode config + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] memory1_addr: memory1 base address + \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) +{ + /* configure memory1 base address */ + DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr; + + if(DMA_MEMORY_0 == memory_select) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS; + } +} + +/*! + \brief DMA using memory get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) { + return DMA_MEMORY_1; + } else { + return DMA_MEMORY_0; + } +} + +/*! + \brief DMA channel peripheral select + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] sub_periph: specify DMA channel peripheral + \arg DMA_SUBPERIx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PERIEN; + ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); + + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief DMA flow controller configure + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] controller: specify DMA flow controler + only one parameter can be selected which is shown as below: + \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller + \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller + \param[out] none + \retval none +*/ +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) +{ + if(DMA_FLOW_CONTROLLER_DMA == controller) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_TFCS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_TFCS; + } +} + +/*! + \brief DMA switch buffer mode enable + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + /* switch buffer mode enable */ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_SBMEN; + } else { + /* switch buffer mode disable */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_SBMEN; + } +} + +/*! + \brief DMA FIFO status get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FCNT); +} + +/*! + \brief get DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA_CHx(x=0..7) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + if(channelx < DMA_CH4) { + if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { + return SET; + } else { + return RESET; + } + } else { + channelx -= (dma_channel_enum)4; + if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { + return SET; + } else { + return RESET; + } + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA_CHx(x=0..7) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to enbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) |= source; + } else { + DMA_CHFCTL(dma_periph, channelx) |= source; + } +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to disbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) &= ~source; + } else { + DMA_CHFCTL(dma_periph, channelx) &= ~source; + } +} + +/*! + \brief get DMA interrupt flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get interrupt flag + \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + dma_channel_enum channel_flag_offset = channelx; + if(channelx < DMA_CH4) { + switch(interrupt) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE); + break; + default: + break; + } + } else { + channel_flag_offset -= (dma_channel_enum)4; + switch(interrupt) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + default: + break; + } + } + + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear DMA a channel interrupt flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear interrupt flag + \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) +{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c new file mode 100644 index 0000000..39afe43 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c @@ -0,0 +1,3510 @@ +/*! + \file gd32f4xx_enet.c + \brief ENET driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_enet.h" + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static uint32_t enet_unknow_err = 0U; +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; + +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum + only one parameter can be selected which is shown as below + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX + - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ + ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; + - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE ; + - ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ; + - ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ; + - ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ; + - ENET_ACTIVE_THRESHOLD_1792BYTES ; + - ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ; + - ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ; + - ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ; + - ENET_DEACTIVE_THRESHOLD_1792BYTES . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch(option) { + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + +#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE + para &= ~ENET_ENHANCED_DESCRIPTOR; +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, refer to enet_frmrecept_enum + only one parameter can be selected which is shown as below + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state = ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if(ERROR == enet_phy_config()) { + _ENET_DELAY_(PHY_RESETDELAY); + if(ERROR == enet_phy_config()) { + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { + /* wait for PHY_LINKED_STATUS bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + } while((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { + media_temp = ENET_MODE_FULLDUPLEX; + } else { + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { + media_temp |= ENET_SPEEDMODE_10M; + } else { + media_temp |= ENET_SPEEDMODE_100M; + } + } else { + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); + temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); + temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + + reg_value = ENET_DMA_BCTL; + temp = reg_temp; + /* configure ENET_DMA_BCTL register */ + reg_value &= (~ENET_DMA_BCTL_DFM); + temp &= ENET_DMA_BCTL_DFM; + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do { + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#else + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#endif + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + } else { + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); + } + + } else { + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt,, refer to enet_int_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, refer to enet_int_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if(max > limit) { + max = limit; + } + + for(; offset < max; offset++) { + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief get the enet debug status from the debug register + \param[in] mac_debug: enet debug status + only one parameter can be selected which is shown as below + \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state + \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation + \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status + \arg ENET_RXFIFO_STATE: RxFIFO state + \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state + \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter + \arg ENET_PAUSE_CONDITION_STATUS: pause condition status + \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation + \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty + \arg ENET_TXFIFO_FULL: TxFIFO is full + \param[out] none + \retval value of the status users want to get +*/ +uint32_t enet_debug_status_get(uint32_t mac_debug) +{ + uint32_t temp_state = 0U; + + switch(mac_debug) { + case ENET_RX_ASYNCHRONOUS_FIFO_STATE: + temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_STATE: + temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); + break; + case ENET_MAC_TRANSMITTER_STATUS: + temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); + break; + case ENET_TXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); + break; + default: + if(RESET != (ENET_MAC_DBG & mac_debug)) { + temp_state = 0x1U; + } + break; + } + return temp_state; +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { + reg |= ENET_MDC_HCLK_DIV16; + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { + reg |= ENET_MDC_HCLK_DIV26; + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { + reg |= ENET_MDC_HCLK_DIV42; + } else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) { + reg |= ENET_MDC_HCLK_DIV62; + } else if((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV102; + } else { + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + + /* PHY reset complete */ + if(RESET == (phy_value & PHY_RESET)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0000 - 0x001F + \param[in] phy_reg: 0x0000 - 0x001F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if(ENET_PHY_WRITE == direction) { + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do { + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction) { + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state = ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if(RESET == temp) { + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically + this value must make sure to be less than configured pause time + only one parameter can be selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control + this value should always be less than active flow control value + only one parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control + only one parameter can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if(ENET_DMA_TX == direction) { + ENET_DMA_TPEN = 0U; + } else { + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(RESET == flush_state) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) + (uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(info_get) { + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + if(reval > 4U) { + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { + reval = reval + 4U; + } + } else { + reval = 0U; + } + + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_EXSV: extended status valid + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_TSV: timestamp valid + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if((uint32_t)RESET != (desc->status & desc_flag)) { + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \param[in] desc: the descriptor pointer which users want to configure + \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) + \param[out] none + \retval none +*/ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; + ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } + + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/*! + \brief get the bit of extended status flag in ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get the extended status flag + \param[in] desc_status: the extended status want to get + only one parameter can be selected which is shown as below + \arg ENET_RDES4_IPPLDT: IP frame payload type + \arg ENET_RDES4_IPHERR: IP frame header error + \arg ENET_RDES4_IPPLDERR: IP frame payload error + \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed + \arg ENET_RDES4_IPF4: IP frame in version 4 + \arg ENET_RDES4_IPF6: IP frame in version 6 + \arg ENET_RDES4_PTPMT: PTP message type + \arg ENET_RDES4_PTPOEF: PTP on ethernet frame + \arg ENET_RDES4_PTPVF: PTP version format + \param[out] none + \retval value of extended status +*/ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(desc_status) { + case ENET_RDES4_IPPLDT: + reval = GET_RDES4_IPPLDT(desc->extended_status); + break; + case ENET_RDES4_PTPMT: + reval = GET_RDES4_PTPMT(desc->extended_status); + break; + default: + if((uint32_t)RESET != (desc->extended_status & desc_status)) { + reval = 1U; + } else { + reval = 0U; + } + } + + return reval; +} + +/*! + \brief configure descriptor to work in enhanced mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_enhanced_mode(void) +{ + ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configuration each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + uint32_t timeout = 0U; + uint32_t rdes0_tsv_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + } + } else { + return ERROR; + } + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and + write to the RDES6 and RDES7 */ + do { + rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); + timeout++; + } while((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_RDES0_TSV flag */ + dma_current_rxdesc->status &= ~ENET_RDES0_TSV; + /* get the timestamp value of the received frame */ + timestamp[0] = dma_current_rxdesc->timestamp_low; + timestamp[1] = dma_current_rxdesc->timestamp_high; + } + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* Clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0; + uint32_t dma_tbu_flag, dma_tu_flag; + uint32_t tdes0_ttmss_flag; + uint32_t timeout = 0; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0; offset < length; offset++) { + (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* Clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->timestamp_low; + timestamp[1] = dma_current_txdesc->timestamp_high; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +#else + +/*! + \brief configure descriptor to work in normal mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_normal_mode(void) +{ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + } else { + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum + only one parameter can be selected which is shown as below + \arg ENET_MSC_PRESET_NONE: do not preset MSC counter + \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value + \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value + \param[out] none + \retval none +*/ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode) +{ + ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; + ENET_MSC_CTL |= (uint32_t)mode; +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: the function of PTP timestamp + only one parameter can be selected which is shown as below + \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp + \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp + \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp + \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode + \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode + \arg ENET_SNOOPING_PTP_VERSION_2: version 2 + \arg ENET_SNOOPING_PTP_VERSION_1: version 1 + \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + management and signaling message + \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message + \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch(func) { + case ENET_CKNT_ORDINARY: + case ENET_CKNT_BOUNDARY: + case ENET_CKNT_END_TO_END: + case ENET_CKNT_PEER_TO_PEER: + ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; + ENET_PTP_TSCTL |= (uint32_t)func; + break; + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + subsecond: 0x0 - 0x7FFF FFFF + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure the PPS output frequency + \param[in] freq: PPS output frequency + only one parameter can be selected which is shown as below + \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency + \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency + \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency + \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency + \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency + \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency + \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency + \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency + \param[out] none + \retval none +*/ +void enet_ptp_pps_output_frequency_config(uint32_t freq) +{ + ENET_PTP_PPSCTL = freq; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + __IO uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--) { + } +} +#endif /* USE_DELAY */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c new file mode 100644 index 0000000..0595672 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c @@ -0,0 +1,1252 @@ +/*! + \file gd32f4xx_exmc.c + \brief EXMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL_RESET ((uint32_t)0x000030DAU) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask */ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) + +/* EXMC bank3 register reset mask */ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFFFFFFFFU) + +/* EXMC SDRAM device register reset mask */ +#define SDRAM_DEVICE_SDCTL_RESET ((uint32_t)0x000002D0U) +#define SDRAM_DEVICE_SDTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define SDRAM_DEVICE_SDCMD_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDARI_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDSTAT_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDRSCTL_RESET ((uint32_t)0x00000000U) + +/* EXMC bank0 SQPI-PSRAM register reset mask */ +#define BANK0_SQPI_SINIT_RESET ((uint32_t)0x18010000U) +#define BANK0_SQPI_SRCMD_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SWCMD_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SIDL_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SIDH_RESET ((uint32_t)0x00000000U) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define SDCTL_WPEN_OFFSET ((uint32_t)9U) +#define SDCTL_BRSTRD_OFFSET ((uint32_t)12U) + +#define SDTCFG_XSRD_OFFSET ((uint32_t)4U) +#define SDTCFG_RASD_OFFSET ((uint32_t)8U) +#define SDTCFG_ARFD_OFFSET ((uint32_t)12U) +#define SDTCFG_WRD_OFFSET ((uint32_t)16U) +#define SDTCFG_RPD_OFFSET ((uint32_t)20U) +#define SDTCFG_RCD_OFFSET ((uint32_t)24U) + +#define SDCMD_NARF_OFFSET ((uint32_t)5U) +#define SDCMD_MRC_OFFSET ((uint32_t)9U) + +#define SDARI_ARINTV_OFFSET ((uint32_t)1U) + +#define SDSTAT_STA0_OFFSET ((uint32_t)1U) +#define SDSTAT_STA1_OFFSET ((uint32_t)3U) + +#define SRCMD_RWAITCYCLE_OFFSET ((uint32_t)16U) +#define SWCMD_WWAITCYCLE_OFFSET ((uint32_t)16U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t exmc_norsram_region) +{ + /* reset the registers */ + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; + EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + /* configure the structure with default values */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* configure read/write timing */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* configure write timing, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 + write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE, EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW, EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B, EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM, EXMC_MEMORY_TYPE_PSRAM, EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU + write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WEN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX)); + + /* configure control bits */ + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + /* configure timing */ + sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* enable nor flash access */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* configure extended mode */ + if(ENABLE == exmc_norsram_init_struct->extended_mode) { + snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + } else { + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] exmc_nand_bank: select the bank of NAND + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t exmc_nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + /* configure the structure with default values */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief enable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize exmc_pccard_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the structure with default values */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFFU + holdtime: 0x01U~0xFFU + waittime: 0x02U~0x100U + setuptime: 0x01U~0x100U + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief deinitialize EXMC SDRAM device + \param[in] exmc_sdram_device: select the SRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0, 1) + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sdram_deinit(uint32_t exmc_sdram_device) +{ + /* reset SDRAM registers */ + EXMC_SDCTL(exmc_sdram_device) = SDRAM_DEVICE_SDCTL_RESET; + EXMC_SDTCFG(exmc_sdram_device) = SDRAM_DEVICE_SDTCFG_RESET; + EXMC_SDCMD = SDRAM_DEVICE_SDCMD_RESET; + EXMC_SDARI = SDRAM_DEVICE_SDARI_RESET; + EXMC_SDRSCTL = SDRAM_DEVICE_SDRSCTL_RESET; +} + +/*! + \brief initialize exmc_sdram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) +{ + /* configure the structure with default values */ + exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; + exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; + exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; + exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; + exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; + exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; + exmc_sdram_init_struct->write_protection = ENABLE; + exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; + exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; + + exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; + exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; + exmc_sdram_init_struct->timing->row_address_select_delay = 16U; + exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; + exmc_sdram_init_struct->timing->write_recovery_delay = 16U; + exmc_sdram_init_struct->timing->row_precharge_delay = 16U; + exmc_sdram_init_struct->timing->row_to_column_delay = 16U; +} + +/*! + \brief initialize EXMC SDRAM device + \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter + sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 + pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 + burst_read_switch: ENABLE or DISABLE + sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK + write_protection: ENABLE or DISABLE + cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 + internal_bank_number: EXMC_SDRAM_2_INTER_BANK,EXMC_SDRAM_4_INTER_BANK + data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B + row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 + column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 + timing: exmc_sdram_timing_parameter_struct set the time + row_to_column_delay: 1U~16U + row_precharge_delay: 1U~16U + write_recovery_delay: 1U~16U + auto_refresh_delay: 1U~16U + row_address_select_delay: 1U~16U + exit_selfrefresh_delay: 1U~16U + load_mode_register_delay: 1U~16U + \param[out] none + \retval none +*/ +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) +{ + uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; + + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + /* configure EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + } else { + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* some bits in the EXMC_SDCTL1 register are reserved */ + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); + + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); + + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; + EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; + + /* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + /* some bits in the EXMC_SDTCFG1 register are reserved */ + sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); + + sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET)); + + sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET)); + + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; + EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; + } +} + +/*! + \brief initialize exmc_sdram_struct_command_para_init with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer + \retval none +*/ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; +} + +/*! + \brief deinitialize exmc SQPIPSRAM + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_deinit(void) +{ + /* reset the registers */ + EXMC_SINIT = BANK0_SQPI_SINIT_RESET; + EXMC_SRCMD = BANK0_SQPI_SRCMD_RESET; + EXMC_SWCMD = BANK0_SQPI_SWCMD_RESET; + EXMC_SIDL = BANK0_SQPI_SIDL_RESET; + EXMC_SIDH = BANK0_SQPI_SIDH_RESET; +} + +/*! + \brief initialize exmc_sqpipsram_parameter_struct with the default values + \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) +{ + /* configure the structure with default values */ + exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; + exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; + exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; + exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; +} + +/*! + \brief initialize EXMC SQPIPSRAM + \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter + sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE + id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 + address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 + command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 + \param[out] none + \retval none +*/ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) +{ + /* initialize SQPI controller */ + EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; +} + +/*! + \brief configure consecutive clock + \param[in] clock_mode: specify when the clock is generated + only one parameter can be selected which is shown as below: + \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access + \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally + \param[out] none + \retval none +*/ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) +{ + if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) { + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; + } else { + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; + } +} + +/*! + \brief configure CRAM page size + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + only one parameter can be selected which is shown as below: + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes + \param[out] none + \retval none +*/ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) +{ + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; + } else { + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; + } +} + +/*! + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) +{ + return(EXMC_NECC(exmc_nand_bank)); +} + +/*! + \brief enable or disable read sample + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_enable(ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; + } else { + EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); + } +} + +/*! + \brief configure the delayed sample clock of read data + \param[in] delay_cell: SDRAM the delayed sample clock of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) + \param[in] extra_hclk: sample cycle of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) +{ + uint32_t sdrsctl = 0U; + + /* reset the bits */ + sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); + /* set the bits */ + sdrsctl |= (uint32_t)(delay_cell | extra_hclk); + EXMC_SDRSCTL = sdrsctl; +} + +/*! + \brief configure the SDRAM memory command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + mode_register_content: + auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY + \param[out] none + \retval none +*/ +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure command register */ + EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | + (exmc_sdram_command_init_struct->bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content) << SDCMD_MRC_OFFSET)); +} + +/*! + \brief set auto-refresh interval + \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF + \param[out] none + \retval none +*/ +void exmc_sdram_refresh_count_set(uint32_t exmc_count) +{ + uint32_t sdari; + sdari = EXMC_SDARI & (~EXMC_SDARI_ARINTV); + EXMC_SDARI = sdari | (uint32_t)((exmc_count << SDARI_ARINTV_OFFSET) & EXMC_SDARI_ARINTV); +} + +/*! + \brief set the number of successive auto-refresh command + \param[in] exmc_number: the number of successive Auto-refresh cycles will be send, 1~15 + \param[out] none + \retval none +*/ +void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) +{ + uint32_t sdcmd; + sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); + EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; +} + +/*! + \brief configure the write protection function + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; + } else { + EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); + } + +} + +/*! + \brief get the status of SDRAM device0 or device1 + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[out] none + \retval the status of SDRAM device +*/ +uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) +{ + uint32_t sdstat = 0U; + + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); + } else { + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); + } + + return sdstat; +} + +/*! + \brief set the read command + \param[in] read_command_mode: configure SPI PSRAM read command mode + only one parameter can be selected which is shown as below: + \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_QPI: QPI mode + \param[in] read_wait_cycle: wait cycle number after address phase,0..15 + \param[in] read_command_code: read command for AHB read transfer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code) +{ + uint32_t srcmd; + + srcmd = (uint32_t) read_command_mode | + ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | + ((read_command_code & EXMC_SRCMD_RCMD)); + EXMC_SRCMD = srcmd; +} + +/*! + \brief set the write command + \param[in] write_command_mode: configure SPI PSRAM write command mode + only one parameter can be selected which is shown as below: + \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_QPI: QPI mode + \param[in] write_wait_cycle: wait cycle number after address phase,0..15 + \param[in] write_command_code: read command for AHB read transfer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code) +{ + uint32_t swcmd; + + swcmd = (uint32_t) write_command_mode | + ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | + ((write_command_code & EXMC_SWCMD_WCMD)); + EXMC_SWCMD = swcmd; +} + +/*! + \brief send SPI read ID command + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_read_id_command_send(void) +{ + EXMC_SRCMD |= EXMC_SRCMD_RDID; +} + +/*! + \brief send SPI special command which does not have address and data phase + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_write_cmd_send(void) +{ + EXMC_SWCMD |= EXMC_SWCMD_SC; +} + +/*! + \brief get the EXMC SPI ID low data + \param[in] none + \param[out] none + \retval the ID low data +*/ +uint32_t exmc_sqpipsram_low_id_get(void) +{ + return (EXMC_SIDL); +} + +/*! + \brief get the EXMC SPI ID high data + \param[in] none + \param[out] none + \retval the ID high data +*/ +uint32_t exmc_sqpipsram_high_id_get(void) +{ + return (EXMC_SIDH); +} + +/*! + \brief get the bit value of EXMC send write command bit or read ID command + \param[in] send_command_flag: the send command flag + only one parameter can be selected which is shown as below: + \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit + \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit + \param[out] none + \retval the new value of send command flag +*/ +FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) +{ + uint32_t flag = 0x00000000U; + + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag) { + flag = EXMC_SRCMD; + } else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag) { + flag = EXMC_SWCMD; + } else { + } + + if(flag & send_command_flag) { + /* flag is set */ + return SET; + } else { + /* flag is reset */ + return RESET; + } +} + +/*! + \brief enable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REIE; + } +} + +/*! + \brief disable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~interrupt; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI &= ~EXMC_SDARI_REIE; + } +} + +/*! + \brief get EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag + \arg EXMC_SDRAM_FLAG_NREADY: not ready status + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) +{ + uint32_t status = 0x00000000U; + + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + } else { + /* SDRAM device0 or device1 */ + status = EXMC_SDSTAT; + } + + if((status & flag) != (uint32_t)flag) { + /* flag is reset */ + return RESET; + } else { + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag + \arg EXMC_SDRAM_FLAG_NREADY: not ready status + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~flag; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDSTAT &= ~flag; + } +} + +/*! + \brief get EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) +{ + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; + + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); + } else { + /* SDRAM device0 or device1 */ + status = EXMC_SDARI; + interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); + } + + interrupt_enable = (status & interrupt); + + if((interrupt_enable) && (interrupt_state)) { + /* interrupt flag is set */ + return SET; + } else { + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REC; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c new file mode 100644 index 0000000..93b4688 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c @@ -0,0 +1,256 @@ +/*! + \file gd32f4xx_exti.c + \brief EXTI driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x00000000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, \ + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c new file mode 100644 index 0000000..b1b48a9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c @@ -0,0 +1,1048 @@ +/*! + \file gd32f4xx_fmc.c + \brief FMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_fmc.h" + +/*! + \brief set the FMC wait state counter + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: + \arg WS_WSCNT_0: FMC 0 wait + \arg WS_WSCNT_1: FMC 1 wait + \arg WS_WSCNT_2: FMC 2 wait + \arg WS_WSCNT_3: FMC 3 wait + \arg WS_WSCNT_4: FMC 4 wait + \arg WS_WSCNT_5: FMC 5 wait + \arg WS_WSCNT_6: FMC 6 wait + \arg WS_WSCNT_7: FMC 7 wait + \arg WS_WSCNT_8: FMC 8 wait + \arg WS_WSCNT_9: FMC 9 wait + \arg WS_WSCNT_10: FMC 10 wait + \arg WS_WSCNT_11: FMC 11 wait + \arg WS_WSCNT_12: FMC 12 wait + \arg WS_WSCNT_13: FMC 13 wait + \arg WS_WSCNT_14: FMC 14 wait + \arg WS_WSCNT_15: FMC 15 wait + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WC_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { + /* write the FMC key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit*/ + FMC_CTL |= FMC_CTL_LK; +} + +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) + +/*! + \brief FMC erase page + \param[in] page_addr: the page address to be erased. + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_page_erase(uint32_t page_addr) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* unlock page erase operation */ + FMC_PEKEY = UNLOCK_PE_KEY; + + /* start page erase */ + FMC_PECFG = FMC_PE_EN | page_addr; + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= FMC_CTL_SER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + FMC_PECFG &= ~FMC_PE_EN; + FMC_CTL &= ~FMC_CTL_SER; + } + + /* return the FMC state */ + return fmc_state; +} + +#endif + +/*! + \brief FMC erase sector + \param[in] fmc_sector: select the sector to erase + only one parameter can be selected which is shown as below: + \arg CTL_SECTOR_NUMBER_0: sector 0 + \arg CTL_SECTOR_NUMBER_1: sector 1 + \arg CTL_SECTOR_NUMBER_2: sector 2 + \arg CTL_SECTOR_NUMBER_3: sector 3 + \arg CTL_SECTOR_NUMBER_4: sector 4 + \arg CTL_SECTOR_NUMBER_5: sector 5 + \arg CTL_SECTOR_NUMBER_6: sector 6 + \arg CTL_SECTOR_NUMBER_7: sector 7 + \arg CTL_SECTOR_NUMBER_8: sector 8 + \arg CTL_SECTOR_NUMBER_9: sector 9 + \arg CTL_SECTOR_NUMBER_10: sector 10 + \arg CTL_SECTOR_NUMBER_11: sector 11 + \arg CTL_SECTOR_NUMBER_12: sector 12 + \arg CTL_SECTOR_NUMBER_13: sector 13 + \arg CTL_SECTOR_NUMBER_14: sector 14 + \arg CTL_SECTOR_NUMBER_15: sector 15 + \arg CTL_SECTOR_NUMBER_16: sector 16 + \arg CTL_SECTOR_NUMBER_17: sector 17 + \arg CTL_SECTOR_NUMBER_18: sector 18 + \arg CTL_SECTOR_NUMBER_19: sector 19 + \arg CTL_SECTOR_NUMBER_20: sector 20 + \arg CTL_SECTOR_NUMBER_21: sector 21 + \arg CTL_SECTOR_NUMBER_22: sector 22 + \arg CTL_SECTOR_NUMBER_23: sector 23 + \arg CTL_SECTOR_NUMBER_24: sector 24 + \arg CTL_SECTOR_NUMBER_25: sector 25 + \arg CTL_SECTOR_NUMBER_26: sector 26 + \arg CTL_SECTOR_NUMBER_27: sector 27 + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start sector erase */ + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= (FMC_CTL_SER | fmc_sector); + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the SER bit */ + FMC_CTL &= (~FMC_CTL_SER); + FMC_CTL &= ~FMC_CTL_SN; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief FMC erase whole chip + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start whole chip erase */ + FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bits */ + FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief FMC erase whole bank0 + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start FMC bank0 erase */ + FMC_CTL |= FMC_CTL_MER0; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER0 bit */ + FMC_CTL &= (~FMC_CTL_MER0); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief FMC erase whole bank1 + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start FMC bank1 erase */ + FMC_CTL |= FMC_CTL_MER1; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER1 bit */ + FMC_CTL &= (~FMC_CTL_MER1); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_WORD; + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program(0x0000 - 0xFFFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_HALF_WORD; + FMC_CTL |= FMC_CTL_PG; + + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a byte at the corresponding address + \param[in] address: address to program + \param[in] data: byte to program(0x00 - 0xFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_BYTE; + FMC_CTL |= FMC_CTL_PG; + + REG8(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)) { + /* write the FMC key */ + FMC_OBKEY = OB_UNLOCK_KEY0; + FMC_OBKEY = OB_UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OB_LK bit */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_LK; +} + +/*! + \brief send option byte change command + \param[in] none + \param[out] none + \retval none +*/ +void ob_start(void) +{ + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; +} + +/*! + \brief erase option byte + \param[in] none + \param[out] none + \retval none +*/ +void ob_erase(void) +{ + uint32_t reg, reg1; + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; + + if(FMC_READY == fmc_state) { + + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + /* reset the BOR level */ + reg |= FMC_OBCTL0_BOR_TH; + /* reset option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + /* reset option byte dbs value */ + reg &= ~FMC_OBCTL0_DBS; + + /* reset drp and wp value */ + reg |= FMC_OBCTL0_WP0; + reg &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + FMC_OBCTL0 = reg; + } +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector + \param[out] none + \retval SUCCESS or ERROR +*/ +ErrStatus ob_write_protection_enable(uint32_t ob_wp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; + } + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + reg0 &= (~((uint32_t)ob_wp << 16U)); + reg1 &= (~(ob_wp & 0xFFFF0000U)); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; + } +} + +/*! + \brief disable write protection + \param[in] ob_wp: specify sector to be write protected + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector + \param[out] none + \retval SUCCESS or ERROR +*/ +ErrStatus ob_write_protection_disable(uint32_t ob_wp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; + } + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + reg0 |= ((uint32_t)ob_wp << 16U); + reg1 |= (ob_wp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; + } +} + +/*! + \brief enable erase/program protection and D-bus read protection + \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector + \param[out] none + \retval none +*/ +void ob_drp_enable(uint32_t ob_drp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; + uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; + uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + if(RESET == drp_state) { + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + } + reg0 |= ((uint32_t)ob_drp << 16U); + reg0 |= FMC_OBCTL0_DRP; + reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + } +} + +/*! + \brief disable erase/program protection and D-bus read protection + \param[in] none + \param[out] none + \retval none +*/ +void ob_drp_disable(void) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + if(((uint8_t)(reg0 >> 8U)) == (uint8_t)FMC_NSPC) { + /* security protection should be set as low level protection before disable D-BUS read protection */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_LSPC << 8U); + FMC_OBCTL0 = reg0; + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; + } + + /* it is necessary to disable the security protection at the same time when D-BUS read protection is disabled */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_NSPC << 8U); + reg0 |= FMC_OBCTL0_WP0; + reg0 &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg0; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + } +} + +/*! + \brief configure security protection level + \param[in] ob_spc: specify security protection level + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval none +*/ +void ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + uint32_t reg; + + reg = FMC_OBCTL0; + /* reset the OBCTL0_SPC, set according to ob_spc */ + reg &= ~FMC_OBCTL0_SPC; + reg |= ((uint32_t)ob_spc << 8U); + FMC_OBCTL0 = reg; + } +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + only one parameter can be selected which is shown as below: + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + only one parameter can be selected which is shown as below: + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + only one parameter can be selected which is shown as below: + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[out] none + \retval none +*/ +void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + uint32_t reg; + + reg = FMC_OBCTL0; + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg &= ~(FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + FMC_OBCTL0 = (reg | ob_fwdgt | ob_deepsleep | ob_stdby); + } +} + +/*! + \brief program the option byte BOR threshold value + \param[in] ob_bor_th: user option byte + only one parameter can be selected which is shown as below: + \arg OB_BOR_TH_VALUE3: BOR threshold value 3 + \arg OB_BOR_TH_VALUE2: BOR threshold value 2 + \arg OB_BOR_TH_VALUE1: BOR threshold value 1 + \arg OB_BOR_TH_OFF: no BOR function + \param[out] none + \retval none +*/ +void ob_user_bor_threshold(uint32_t ob_bor_th) +{ + uint32_t reg; + + reg = FMC_OBCTL0; + /* set the BOR level */ + reg &= ~FMC_OBCTL0_BOR_TH; + FMC_OBCTL0 = (reg | ob_bor_th); +} + +/*! + \brief configure the option byte boot bank value + \param[in] boot_mode: specifies the option byte boot bank value + only one parameter can be selected which is shown as below: + \arg OB_BB_DISABLE: boot from bank0 + \arg OB_BB_ENABLE: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval none +*/ +void ob_boot_mode_config(uint32_t boot_mode) +{ + uint32_t reg; + + reg = FMC_OBCTL0; + /* set option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + FMC_OBCTL0 = (reg | boot_mode); +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5U) & 0x07U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint16_t ob_write_protection0_get(void) +{ + /* return the FMC write protection option byte value */ + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint16_t ob_write_protection1_get(void) +{ + /* return the the FMC write protection option byte value */ + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); +} + +/*! + \brief get the FMC erase/program protection and D-bus read protection option bytes value + \param[in] none + \param[out] none + \retval the FMC erase/program protection and D-bus read protection option bytes value +*/ +uint16_t ob_drp0_get(void) +{ + /* return the FMC erase/program protection and D-bus read protection option bytes value */ + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } +} + +/*! + \brief get the FMC erase/program protection and D-bus read protection option bytes value + \param[in] none + \param[out] none + \retval the FMC erase/program protection and D-bus read protection option bytes value +*/ +uint16_t ob_drp1_get(void) +{ + /* return the FMC erase/program protection and D-bus read protection option bytes value */ + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } +} + +/*! + \brief get option byte security protection code value + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(((uint8_t)(FMC_OBCTL0 >> 8U)) != FMC_NSPC) { + spc_state = SET; + } else { + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief get the FMC option byte BOR threshold value + \param[in] none + \param[out] none + \retval the FMC BOR threshold value:OB_BOR_TH_OFF,OB_BOR_TH_VALUE1,OB_BOR_TH_VALUE2,OB_BOR_TH_VALUE3 +*/ +uint8_t ob_user_bor_threshold_get(void) +{ + /* return the FMC BOR threshold value */ + return (uint8_t)((uint8_t)FMC_OBCTL0 & 0x0CU); +} + +/*! + \brief get flag set or reset + \param[in] fmc_flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t fmc_flag) +{ + if(FMC_STAT & fmc_flag) { + return SET; + } + /* return the state of corresponding FMC flag */ + return RESET; +} + +/*! + \brief clear the FMC pending flag + \param[in] FMC_flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t fmc_flag) +{ + /* clear the flags */ + FMC_STAT = fmc_flag; +} + +/*! + \brief enable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t fmc_int) +{ + FMC_CTL |= fmc_int; +} + +/*! + \brief disable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: disable FMC end of program interrupt + \arg FMC_INT_ERR: disable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t fmc_int) +{ + FMC_CTL &= ~(uint32_t)fmc_int; +} + +/*! + \brief get FMC interrupt flag set or reset + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag) +{ + if(FMC_FLAG_END == fmc_int_flag) { + /* end of operation interrupt flag */ + if(FMC_CTL & FMC_CTL_ENDIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } else { + /* error interrupt flags */ + if(FMC_CTL & FMC_CTL_ERRIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } + + return RESET; +} + +/*! + \brief clear the FMC interrupt flag + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag) +{ + /* clear the interrupt flag */ + FMC_STAT = fmc_int_flag; +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error +*/ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + uint32_t temp_val = FMC_STAT; + + if(RESET != (temp_val & FMC_FLAG_BUSY)) { + fmc_state = FMC_BUSY; + } else if(RESET != (temp_val & FMC_FLAG_RDDERR)) { + fmc_state = FMC_RDDERR; + } else if(RESET != (temp_val & FMC_FLAG_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if(RESET != (temp_val & FMC_FLAG_PGMERR)) { + fmc_state = FMC_PGMERR; + } else if(RESET != (temp_val & FMC_FLAG_WPERR)) { + fmc_state = FMC_WPERR; + } else if(RESET != (temp_val & FMC_FLAG_OPERR)) { + fmc_state = FMC_OPERR; + } else { + fmc_state = FMC_READY; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(0U == timeout) { + fmc_state = FMC_TOERR; + } + + /* return the FMC state */ + return fmc_state; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c new file mode 100644 index 0000000..36af0dd --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c @@ -0,0 +1,218 @@ +/*! + \file gd32f4xx_fwdgt.c + \brief FWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(RESET != (FWDGT_STAT & flag)){ + return SET; + } + + return RESET; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c new file mode 100644 index 0000000..ee490f9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c @@ -0,0 +1,434 @@ +/*! + \file gd32f4xx_gpio.c + \brief GPIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + case GPIOH: + /* reset GPIOH */ + rcu_periph_reset_enable(RCU_GPIOHRST); + rcu_periph_reset_disable(RCU_GPIOHRST); + break; + case GPIOI: + /* reset GPIOI */ + rcu_periph_reset_enable(RCU_GPIOIRST); + rcu_periph_reset_disable(RCU_GPIOIRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] mode: GPIO pin mode + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: GPIO pin with pull-up or pull-down resistor + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] otype: GPIO pin output mode + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: GPIO pin output max speed + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_25MHZ: output max speed 25MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeedr; + + if(GPIO_OTYPE_OD == otype) { + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + } else { + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeedr = GPIO_OSPD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin output speed bits */ + ospeedr &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeedr |= GPIO_OSPEED_SET(i, speed); + } + } + GPIO_OSPD(gpio_periph) = ospeedr; +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of GPIO pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval input status of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of GPIO pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval output status of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] alt_func_num: GPIO pin af function + \arg GPIO_AF_0: SYSTEM + \arg GPIO_AF_1: TIMER0, TIMER1 + \arg GPIO_AF_2: TIMER2, TIMER3, TIMER4 + \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 + \arg GPIO_AF_4: I2C0, I2C1, I2C2 + \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 + \arg GPIO_AF_6: SPI2, SPI3, SPI4 + \arg GPIO_AF_7: USART0, USART1, USART2, SPI1, SPI2 + \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13, I2C1, I2C2, CTC + \arg GPIO_AF_10: USB_FS, USB_HS + \arg GPIO_AF_11: ENET + \arg GPIO_AF_12: EXMC, SDIO, USB_HS + \arg GPIO_AF_13: DCI + \arg GPIO_AF_14: TLI + \arg GPIO_AF_15: EVENTOUT + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i, alt_func_num); + } + } + + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c new file mode 100644 index 0000000..e2103b6 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c @@ -0,0 +1,313 @@ +/*! + \file gd32f4xx_hw.c + \brief USB hardware configuration for GD32F4xx + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" + +#define TIM_MSEC_DELAY 0x01U +#define TIM_USEC_DELAY 0x02U + +__IO uint32_t delay_time = 0U; +__IO uint16_t timer_prescaler = 5U; + +/* local function prototypes ('static') */ +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ +#ifdef USE_USB_FS + rcu_pll48m_clock_config(RCU_PLL48MSRC_PLLQ); + rcu_ck48m_clock_config(RCU_CK48MSRC_PLL48M); + + rcu_periph_clock_enable(RCU_USBFS); +#elif defined(USE_USB_HS) + #ifdef USE_EMBEDDED_PHY + rcu_pll48m_clock_config(RCU_PLL48MSRC_PLLQ); + rcu_ck48m_clock_config(RCU_CK48MSRC_PLL48M); + #elif defined(USE_ULPI_PHY) + rcu_periph_clock_enable(RCU_USBHSULPI); + #endif /* USE_EMBEDDED_PHY */ + + rcu_periph_clock_enable(RCU_USBHS); +#endif /* USB_USBFS */ +} + +/*! + \brief configure USB data line GPIO + \param[in] none + \param[out] none + \retval none +*/ +void usb_gpio_config(void) +{ + rcu_periph_clock_enable(RCU_SYSCFG); + +#ifdef USE_USB_FS + + rcu_periph_clock_enable(RCU_GPIOA); + + /* USBFS_DM(PA11) and USBFS_DP(PA12) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11 | GPIO_PIN_12); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11 | GPIO_PIN_12); + + gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_11 | GPIO_PIN_12); + +#elif defined(USE_USB_HS) + + #ifdef USE_ULPI_PHY + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOH); + rcu_periph_clock_enable(RCU_GPIOI); + + /* ULPI_STP(PC0) GPIO pin configuration */ + gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_0); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_0); + + /* ULPI_CK(PA5) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_5); + + /* ULPI_NXT(PH4) GPIO pin configuration */ + gpio_mode_set(GPIOH, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); + gpio_output_options_set(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_4); + + /* ULPI_DIR(PI11) GPIO pin configuration */ + gpio_mode_set(GPIOI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); + gpio_output_options_set(GPIOI, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11); + + /* ULPI_D1(PB0), ULPI_D2(PB1), ULPI_D3(PB10), ULPI_D4(PB11) \ + ULPI_D5(PB12), ULPI_D6(PB13) and ULPI_D7(PB5) GPIO pin configuration */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, \ + GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, \ + GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + + /* ULPI_D0(PA3) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_3); + + gpio_af_set(GPIOC, GPIO_AF_10, GPIO_PIN_0); + gpio_af_set(GPIOH, GPIO_AF_10, GPIO_PIN_4); + gpio_af_set(GPIOI, GPIO_AF_10, GPIO_PIN_11); + gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_5 | GPIO_PIN_3); + gpio_af_set(GPIOB, GPIO_AF_10, GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + #elif defined(USE_EMBEDDED_PHY) + rcu_periph_clock_enable(RCU_GPIOB); + + /* USBHS_DM(PB14) and USBHS_DP(PB15) GPIO pin configuration */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_14 | GPIO_PIN_15); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_14 | GPIO_PIN_15); + gpio_af_set(GPIOB, GPIO_AF_12, GPIO_PIN_14 | GPIO_PIN_15); + #endif /* USE_ULPI_PHY */ + +#endif /* USE_USBFS */ +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ +// nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + +#ifdef USE_USB_FS + nvic_irq_enable((uint8_t)USBFS_IRQn, 2U, 0U); + + #if USBFS_LOW_POWER + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + nvic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 0U, 0U); + #endif /* USBFS_LOW_POWER */ +#elif defined(USE_USB_HS) + nvic_irq_enable((uint8_t)USBHS_IRQn, 2U, 0U); + + #if USBHS_LOW_POWER + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_20); + exti_init(EXTI_20, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_20); + + nvic_irq_enable((uint8_t)USBHS_WKUP_IRQn, 0U, 0U); + #endif /* USBHS_LOW_POWER */ +#endif /* USE_USB_FS */ + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + nvic_irq_enable(USBHS_EP1_Out_IRQn, 1, 0); + nvic_irq_enable(USBHS_EP1_In_IRQn, 1, 0); +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + /* configure the priority group to 2 bits */ + //nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + + /* enable the TIMER6 global interrupt */ + nvic_irq_enable((uint8_t)TIMER6_IRQn, 1U, 0U); + + rcu_periph_clock_enable(RCU_TIMER6); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milliseconds + \param[in] msec: value of delay required in milliseconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief timer base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_interrupt_flag_get(TIMER6, TIMER_INT_FLAG_UP)){ + timer_interrupt_flag_clear(TIMER6, TIMER_INT_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER6); + } + } +} + +/*! + \brief delay routine based on TIMER6 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = milliseconds / microseconds + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER6); +} + +/*! + \brief configures TIMER for delay routine based on Timer2 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_basestructure; + + timer_prescaler = ((rcu_clock_freq_get(CK_APB1)/1000000*2)/12) - 1; + + timer_disable(TIMER6); + timer_interrupt_disable(TIMER6, TIMER_INT_UP); + + if(TIM_USEC_DELAY == unit) { + timer_basestructure.period = 11U; + } else if(TIM_MSEC_DELAY == unit) { + timer_basestructure.period = 11999U; + } else { + /* no operation */ + } + + timer_basestructure.prescaler = timer_prescaler; + timer_basestructure.alignedmode = TIMER_COUNTER_EDGE; + timer_basestructure.counterdirection = TIMER_COUNTER_UP; + timer_basestructure.clockdivision = TIMER_CKDIV_DIV1; + timer_basestructure.repetitioncounter = 0U; + + timer_init(TIMER6, &timer_basestructure); + + timer_interrupt_flag_clear(TIMER6, TIMER_INT_FLAG_UP); + + timer_auto_reload_shadow_enable(TIMER6); + + /* TIMER6 interrupt enable */ + timer_interrupt_enable(TIMER6, TIMER_INT_UP); + + /* TIMER6 enable counter */ + timer_enable(TIMER6); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c new file mode 100644 index 0000000..3b2adfd --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c @@ -0,0 +1,840 @@ +/*! + \file gd32f4xx_i2c.c + \brief I2C driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + case I2C2: + /* reset I2C2 */ + rcu_periph_reset_enable(RCU_I2C2RST); + rcu_periph_reset_disable(RCU_I2C2RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + \param[in] dutycyc: duty cycle in fast mode + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if(400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief select SMBus type + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + uint32_t ctl = 0U; + /* configure I2C POAP position */ + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief configure I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode + \param[out] none + \retval none +*/ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure software reset of I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C PEC calculation + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pecstate: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value + \param[out] none + \retval none +*/ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); +} + +/*! + \brief configure I2C alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* configure smubus alert through SMBA pin */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C ARP protocol in SMBus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief disable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph) +{ + I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; +} + +/*! + \brief enable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph) +{ + I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); +} + +/*! + \brief configure digital noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dfilterpara: refer to i2c_digital_filter_enum + only one parameter can be selected which is shown as below: + \arg I2C_DF_DISABLE: disable digital noise filter + \arg I2C_DF_1PCLK: enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 + \arg I2C_DF_2PCLK: enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 + \arg I2C_DF_3PCLK: enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 + \arg I2C_DF_4PCLK: enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 + \arg I2C_DF_5PCLK: enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 + \arg I2C_DF_6PCLK: enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 + \arg I2C_DF_7PCLK: enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 + \arg I2C_DF_8PCLK: enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 + \arg I2C_DF_9PCLK: enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 + \arg I2C_DF_10PCLK: enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 + \arg I2C_DF_11CLK: enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 + \arg I2C_DF_12CLK: enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 + \arg I2C_DF_13PCLK: enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 + \arg I2C_DF_14PCLK: enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 + \arg I2C_DF_15PCLK: enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 + \param[out] none + \retval none +*/ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara) +{ + I2C_FCTL(i2c_periph) |= dfilterpara; +} + +/*! + \brief enable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; +} + +/*! + \brief disable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); +} + +/*! + \brief enable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; +} + +/*! + \brief disable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); +} + +/*! + \brief get I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition sent out in master mode + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief get I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { + intenable = 1U; + } else { + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c new file mode 100644 index 0000000..02e8e85 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c @@ -0,0 +1,639 @@ +/*! + \file gd32f4xx_ipa.c + \brief IPA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_ipa.h" + +#define IPA_DEFAULT_VALUE 0x00000000U + +/*! + \brief deinitialize IPA registers + \param[in] none + \param[out] none + \retval none +*/ +void ipa_deinit(void) +{ + rcu_periph_reset_enable(RCU_IPARST); + rcu_periph_reset_disable(RCU_IPARST); +} + +/*! + \brief enable IPA transfer + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_enable(void) +{ + IPA_CTL |= IPA_CTL_TEN; +} + +/*! + \brief enable IPA transfer hang up + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_hangup_enable(void) +{ + IPA_CTL |= IPA_CTL_THU; +} + +/*! + \brief disable IPA transfer hang up + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_hangup_disable(void) +{ + IPA_CTL &= ~(IPA_CTL_THU); +} + +/*! + \brief enable IPA transfer stop + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_stop_enable(void) +{ + IPA_CTL |= IPA_CTL_TST; +} + +/*! + \brief disable IPA transfer stop + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_stop_disable(void) +{ + IPA_CTL &= ~(IPA_CTL_TST); +} +/*! + \brief enable IPA foreground LUT loading + \param[in] none + \param[out] none + \retval none +*/ +void ipa_foreground_lut_loading_enable(void) +{ + IPA_FPCTL |= IPA_FPCTL_FLLEN; +} + +/*! + \brief enable IPA background LUT loading + \param[in] none + \param[out] none + \retval none +*/ +void ipa_background_lut_loading_enable(void) +{ + IPA_BPCTL |= IPA_BPCTL_BLLEN; +} + +/*! + \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled + \param[in] pfcm: pixel format convert mode + only one parameter can be selected which is shown as below: + \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert + \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert + \arg IPA_FGBGTODE: blending foreground and background memory to destination memory + \arg IPA_FILL_UP_DE: fill up destination memory with specific color + \param[out] none + \retval none +*/ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm) +{ + IPA_CTL &= ~(IPA_CTL_PFCM); + IPA_CTL |= pfcm; +} + +/*! + \brief initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined + \param[in] none + \param[out] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \retval none +*/ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct) +{ + /* initialize the struct parameters with default values */ + foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; + foreground_struct->foreground_lineoff = IPA_DEFAULT_VALUE; + foreground_struct->foreground_prealpha = IPA_DEFAULT_VALUE; + foreground_struct->foreground_alpha_algorithm = IPA_FG_ALPHA_MODE_0; + foreground_struct->foreground_pf = FOREGROUND_PPF_ARGB8888; + foreground_struct->foreground_prered = IPA_DEFAULT_VALUE; + foreground_struct->foreground_pregreen = IPA_DEFAULT_VALUE; + foreground_struct->foreground_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize foreground parameters + \param[in] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \param[out] none + \retval none +*/ +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* foreground memory base address configuration */ + IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); + IPA_FMADDR = foreground_struct->foreground_memaddr; + /* foreground line offset configuration */ + IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); + IPA_FLOFF = foreground_struct->foreground_lineoff; + /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV | IPA_FPCTL_FAVCA | IPA_FPCTL_FPF); + IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U); + IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; + IPA_FPCTL |= foreground_struct->foreground_pf; + /* foreground pre-defined red green blue configuration */ + IPA_FPV &= ~(IPA_FPV_FPDRV | IPA_FPV_FPDGV | IPA_FPV_FPDBV); + IPA_FPV |= ((foreground_struct->foreground_prered << 16U) | (foreground_struct->foreground_pregreen << 8U) + | (foreground_struct->foreground_preblue)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined + \param[in] none + \param[out] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_BG_ALPHA_MODE_1,IPA_BG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \retval none +*/ +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct) +{ + /* initialize the struct parameters with default values */ + background_struct->background_memaddr = IPA_DEFAULT_VALUE; + background_struct->background_lineoff = IPA_DEFAULT_VALUE; + background_struct->background_prealpha = IPA_DEFAULT_VALUE; + background_struct->background_alpha_algorithm = IPA_BG_ALPHA_MODE_0; + background_struct->background_pf = BACKGROUND_PPF_ARGB8888; + background_struct->background_prered = IPA_DEFAULT_VALUE; + background_struct->background_pregreen = IPA_DEFAULT_VALUE; + background_struct->background_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize background parameters + \param[in] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \param[out] none + \retval none +*/ +void ipa_background_init(ipa_background_parameter_struct *background_struct) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* background memory base address configuration */ + IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); + IPA_BMADDR = background_struct->background_memaddr; + /* background line offset configuration */ + IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); + IPA_BLOFF = background_struct->background_lineoff; + /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF); + IPA_BPCTL |= (background_struct->background_prealpha << 24U); + IPA_BPCTL |= background_struct->background_alpha_algorithm; + IPA_BPCTL |= background_struct->background_pf; + /* background pre-defined red green blue configuration */ + IPA_BPV &= ~(IPA_BPV_BPDRV | IPA_BPV_BPDGV | IPA_BPV_BPDBV); + IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U) + | (background_struct->background_preblue)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined + \param[in] none + \param[out] destination_struct: the data needed to initialize destination parameter + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \retval none +*/ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct) +{ + /* initialize the struct parameters with default values */ + destination_struct->destination_pf = IPA_DPF_ARGB8888; + destination_struct->destination_lineoff = IPA_DEFAULT_VALUE; + destination_struct->destination_prealpha = IPA_DEFAULT_VALUE; + destination_struct->destination_prered = IPA_DEFAULT_VALUE; + destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; + destination_struct->destination_preblue = IPA_DEFAULT_VALUE; + destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; + destination_struct->image_width = IPA_DEFAULT_VALUE; + destination_struct->image_height = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize destination parameters + \param[in] destination_struct: the data needed to initialize destination parameters + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \param[out] none + \retval none +*/ +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct) +{ + uint32_t destination_pixelformat; + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* destination pixel format configuration */ + IPA_DPCTL &= ~(IPA_DPCTL_DPF); + IPA_DPCTL = destination_struct->destination_pf; + destination_pixelformat = destination_struct->destination_pf; + /* destination pixel format ARGB8888 */ + switch(destination_pixelformat) { + case IPA_DPF_ARGB8888: + IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U) + | (destination_struct->destination_prealpha << 24U)); + break; + /* destination pixel format RGB888 */ + case IPA_DPF_RGB888: + IPA_DPV &= ~(IPA_DPV_DPDBV_1 | (IPA_DPV_DPDGV_1) | (IPA_DPV_DPDRV_1)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U)); + break; + /* destination pixel format RGB565 */ + case IPA_DPF_RGB565: + IPA_DPV &= ~(IPA_DPV_DPDBV_2 | (IPA_DPV_DPDGV_2) | (IPA_DPV_DPDRV_2)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 11U)); + break; + /* destination pixel format ARGB1555 */ + case IPA_DPF_ARGB1555: + IPA_DPV &= ~(IPA_DPV_DPDBV_3 | (IPA_DPV_DPDGV_3) | (IPA_DPV_DPDRV_3) | (IPA_DPV_DPDAV_3)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 10U) + | (destination_struct->destination_prealpha << 15U)); + break; + /* destination pixel format ARGB4444 */ + case IPA_DPF_ARGB4444: + IPA_DPV &= ~(IPA_DPV_DPDBV_4 | (IPA_DPV_DPDGV_4) | (IPA_DPV_DPDRV_4) | (IPA_DPV_DPDAV_4)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 4U) + | (destination_struct->destination_prered << 8U) + | (destination_struct->destination_prealpha << 12U)); + break; + default: + break; + } + /* destination memory base address configuration */ + IPA_DMADDR &= ~(IPA_DMADDR_DMADDR); + IPA_DMADDR = destination_struct->destination_memaddr; + /* destination line offset configuration */ + IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); + IPA_DLOFF = destination_struct->destination_lineoff; + /* image size configuration */ + IPA_IMS &= ~(IPA_IMS_HEIGHT | IPA_IMS_WIDTH); + IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize IPA foreground LUT parameters + \param[in] fg_lut_num: foreground LUT number of pixel + \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] fg_lut_addr: foreground LUT memory base address + \param[out] none + \retval none +*/ +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)) { + tempflag = SET; + /* reset the FLLEN in order to configure the following bits */ + IPA_FPCTL &= ~IPA_FPCTL_FLLEN; + } + + /* foreground LUT number of pixel configuration */ + IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U); + /* foreground LUT pixel format configuration */ + if(IPA_LUT_PF_RGB888 == fg_lut_pf) { + IPA_FPCTL |= IPA_FPCTL_FLPF; + } else { + IPA_FPCTL &= ~(IPA_FPCTL_FLPF); + } + /* foreground LUT memory base address configuration */ + IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); + IPA_FLMADDR = fg_lut_addr; + + if(SET == tempflag) { + /* restore the state of FLLEN */ + IPA_FPCTL |= IPA_FPCTL_FLLEN; + } +} + +/*! + \brief initialize IPA background LUT parameters + \param[in] bg_lut_num: background LUT number of pixel + \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] bg_lut_addr: background LUT memory base address + \param[out] none + \retval none +*/ +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)) { + tempflag = SET; + /* reset the BLLEN in order to configure the following bits */ + IPA_BPCTL &= ~IPA_BPCTL_BLLEN; + } + + /* background LUT number of pixel configuration */ + IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U); + /* background LUT pixel format configuration */ + if(IPA_LUT_PF_RGB888 == bg_lut_pf) { + IPA_BPCTL |= IPA_BPCTL_BLPF; + } else { + IPA_BPCTL &= ~(IPA_BPCTL_BLPF); + } + /* background LUT memory base address configuration */ + IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); + IPA_BLMADDR = bg_lut_addr; + + if(SET == tempflag) { + /* restore the state of BLLEN */ + IPA_BPCTL |= IPA_BPCTL_BLLEN; + } +} + +/*! + \brief configure IPA line mark + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void ipa_line_mark_config(uint16_t line_num) +{ + IPA_LM &= ~(IPA_LM_LM); + IPA_LM = line_num; +} + +/*! + \brief inter-timer enable or disable + \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE + \param[out] none + \retval none +*/ +void ipa_inter_timer_config(uint8_t timer_cfg) +{ + if(IPA_INTER_TIMER_ENABLE == timer_cfg) { + IPA_ITCTL |= IPA_ITCTL_ITEN; + } else { + IPA_ITCTL &= ~(IPA_ITCTL_ITEN); + } +} + +/*! + \brief configure the number of clock cycles interval + \param[in] clk_num: the number of clock cycles + \param[out] none + \retval none +*/ +void ipa_interval_clock_num_config(uint8_t clk_num) +{ + /* NCCI[7:0] bits have no meaning if ITEN is '0' */ + IPA_ITCTL &= ~(IPA_ITCTL_NCCI); + IPA_ITCTL |= ((uint32_t)clk_num << 8U); +} + +/*! + \brief get IPA flag status in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_flag_get(uint32_t flag) +{ + if(RESET != (IPA_INTF & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear IPA flag in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +void ipa_flag_clear(uint32_t flag) +{ + IPA_INTC |= (flag); +} + +/*! + \brief enable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_enable(uint32_t int_flag) +{ + IPA_CTL |= (int_flag); +} + +/*! + \brief disable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_disable(uint32_t int_flag) +{ + IPA_CTL &= ~(int_flag); +} + +/*! + \brief get IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) +{ + if(0U != (IPA_INTF & int_flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +void ipa_interrupt_flag_clear(uint32_t int_flag) +{ + IPA_INTC |= (int_flag); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c new file mode 100644 index 0000000..731d4fc --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c @@ -0,0 +1,127 @@ +/*! + \file gd32f4xx_iref.c + \brief IREF driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_iref.h" + +/*! + \brief deinitialize IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_deinit(void) +{ + rcu_periph_reset_enable(RCU_IREFRST); + rcu_periph_reset_disable(RCU_IREFRST); +} + +/*! + \brief enable IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_enable(void) +{ + IREF_CTL |= IREF_CTL_CREN; +} + +/*! + \brief disable IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_disable(void) +{ + IREF_CTL &= ~IREF_CTL_CREN; +} + +/*! + \brief set IREF mode + \param[in] step + \arg IREF_MODE_LOW_POWER: 1uA step + \arg IREF_MODE_HIGH_CURRENT: 8uA step + \param[out] none + \retval none +*/ +void iref_mode_set(uint32_t step) +{ + IREF_CTL &= ~IREF_CTL_SSEL; + IREF_CTL |= step; +} + +/*! + \brief set IREF precision_trim_value + \param[in] precisiontrim + \arg IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)% + \param[out] none + \retval none +*/ +void iref_precision_trim_value_set(uint32_t precisiontrim) +{ + IREF_CTL &= ~IREF_CTL_CPT; + IREF_CTL |= precisiontrim; +} + +/*! + \brief set IREF sink mode + \param[in] sinkmode + \arg IREF_SOURCE_CURRENT : source current. + \arg IREF_SINK_CURRENT: sink current + \param[out] none + \retval none +*/ +void iref_sink_set(uint32_t sinkmode) +{ + IREF_CTL &= ~IREF_CTL_SCMOD; + IREF_CTL |= sinkmode; +} + +/*! + \brief set IREF step data + \param[in] stepdata + \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x + \param[out] none + \retval none +*/ + +void iref_step_data_config(uint32_t stepdata) +{ + IREF_CTL &= ~IREF_CTL_CSDT; + IREF_CTL |= stepdata; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c new file mode 100644 index 0000000..3198d4a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c @@ -0,0 +1,175 @@ +/*! + \file gd32f4xx_misc.c + \brief MISC driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + /* use the priority group value to get the temp_pre and the temp_sub */ + if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) { + temp_pre = 0U; + temp_sub = 0x4U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) { + temp_pre = 1U; + temp_sub = 0x3U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) { + temp_pre = 2U; + temp_sub = 0x2U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) { + temp_pre = 3U; + temp_sub = 0x1U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) { + temp_pre = 4U; + temp_sub = 0x0U; + } else { + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + } + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } else { + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c new file mode 100644 index 0000000..229a557 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c @@ -0,0 +1,412 @@ +/*! + \file gd32f4xx_pmu.c + \brief PMU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_pmu.h" +#include "core_cm4.h" + +/*! + \brief reset PMU registers + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to pmu_lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL + \param[in] ldo_output: + \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode + \arg PMU_LDOVS_MID: mid-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: high-driver mode disable in deep-sleep mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] highdr_switch: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag set */ + while(SET != pmu_flag_get(PMU_FLAG_HDRF)) { + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief enable low-driver mode in deep-sleep + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_LDEN; +} + +/*! + \brief disable low-driver mode in deep-sleep + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief in deep-sleep mode, driver mode when use low power LDO + \param[in] mode: + \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief in deep-sleep mode, driver mode when use normal power LDO + \param[in] mode: + \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work in sleep mode + \param[in] sleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __WFE(); + } +} + +/*! + \brief PMU work in deep-sleep mode + \param[in] ldo + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deep-sleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode + \param[in] deepsleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) +{ + static uint32_t reg_snap[4]; + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* configure low drive mode in deep-sleep mode */ + if(PMU_LOWDRIVER_ENABLE == lowdrive) { + if(PMU_LDO_NORMAL == ldo) { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP); + } else { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP); + } + } + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFF7FF831U; + REG32(0xE000E184U) = 0XBFFFF8FFU; + REG32(0xE000E188U) = 0xFFFFEFFFU; + + /* select WFI or WFE command to enter deep-sleep mode */ + if(WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + + REG32(0xE000E010U) = reg_snap[0]; + REG32(0xE000E100U) = reg_snap[1]; + REG32(0xE000E104U) = reg_snap[2]; + REG32(0xE000E108U) = reg_snap[3]; + + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work in standby mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_to_standbymode(void) +{ + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); +} + +/*! + \brief enable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} + +/*! + \brief backup SRAM LDO on + \param[in] bkp_ldo: + \arg PMU_BLDOON_OFF: backup SRAM LDO closed + \arg PMU_BLDOON_ON: open the backup SRAM LDO + \param[out] none + \retval none +*/ +void pmu_backup_ldo_config(uint32_t bkp_ldo) +{ + PMU_CS &= ~PMU_CS_BLDOON; + PMU_CS |= bkp_ldo; +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag) +{ + switch(flag) { + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c new file mode 100644 index 0000000..6e8dddd --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c @@ -0,0 +1,1332 @@ +/*! + \file gd32f4xx_rcu.c + \brief RCU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_rcu.h" + +/* define clock source */ +#define SEL_IRC16M ((uint16_t)0U) /* IRC16M is selected as CK_SYS */ +#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ +#define SEL_PLLP ((uint16_t)2U) /* PLLP is selected as CK_SYS */ +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000fffffU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0fffffffU) + +/* RCU IRC16M adjust value mask and offset*/ +#define RCU_IRC16M_ADJUST_MASK ((uint8_t)0x1FU) +#define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + rcu_osci_stab_wait(RCU_IRC16M); + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN + | RCU_CTL_PLLSAIEN); + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + /* reset CFG0 register */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | + RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); + /* reset PLL register */ + RCU_PLL = 0x24003010U; + /* reset PLLI2S register */ + RCU_PLLI2S = 0x24003000U; + /* reset PLLSAI register */ + RCU_PLLSAI = 0x24003010U; + /* reset INT register */ + RCU_INT = 0x00000000U; + /* reset CFG1 register */ + RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC: CRC clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_TCMSRAM: TCMSRAM clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_IPA: IPA clock + \arg RCU_ENET: ENET clock + \arg RCU_ENETTX: ENETTX clock + \arg RCU_ENETRX: ENETRX clock + \arg RCU_ENETPTP: ENETPTP clock + \arg RCU_USBHS: USBHS clock + \arg RCU_USBHSULPI: USBHSULPI clock + \arg RCU_DCI: DCI clock + \arg RCU_TRNG: TRNG clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock + \arg RCU_SDIO: SDIO clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_TLI: TLI clock + \arg RCU_CTC: CTC clock + \arg RCU_IREF: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC: CRC clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_TCMSRAM: TCMSRAM clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_IPA: IPA clock + \arg RCU_ENET: ENET clock + \arg RCU_ENETTX: ENETTX clock + \arg RCU_ENETRX: ENETRX clock + \arg RCU_ENETPTP: ENETPTP clock + \arg RCU_USBHS: USBHS clock + \arg RCU_USBHSULPI: USBHSULPI clock + \arg RCU_DCI: DCI clock + \arg RCU_TRNG: TRNG clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock + \arg RCU_SDIO: SDIO clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_TLI: TLI clock + \arg RCU_CTC: CTC clock + \arg RCU_IREF: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC_SLP: CRC clock + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM0_SLP: SRAM0 clock + \arg RCU_SRAM1_SLP: SRAM1 clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_SRAM2_SLP: SRAM2 clock + \arg RCU_DMAx_SLP (x=0,1): DMA clock + \arg RCU_IPA_SLP: IPA clock + \arg RCU_ENET_SLP: ENET clock + \arg RCU_ENETTX_SLP: ENETTX clock + \arg RCU_ENETRX_SLP: ENETRX clock + \arg RCU_ENETPTP_SLP: ENETPTP clock + \arg RCU_USBHS_SLP: USBHS clock + \arg RCU_USBHSULPI_SLP: USBHSULPI clock + \arg RCU_DCI_SLP: DCI clock + \arg RCU_TRNG_SLP: TRNG clock + \arg RCU_USBFS_SLP: USBFS clock + \arg RCU_EXMC_SLP: EXMC clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT_SLP: WWDGT clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock + \arg RCU_PMU_SLP: PMU clock + \arg RCU_DAC_SLP: DAC clock + \arg RCU_RTC_SLP: RTC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock + \arg RCU_SDIO_SLP: SDIO clock + \arg RCU_SYSCFG_SLP: SYSCFG clock + \arg RCU_TLI_SLP: TLI clock + \arg RCU_CTC_SLP: CTC clock + \arg RCU_IREF_SLP: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC_SLP: CRC clock + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM0_SLP: SRAM0 clock + \arg RCU_SRAM1_SLP: SRAM1 clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_SRAM2_SLP: SRAM2 clock + \arg RCU_DMAx_SLP (x=0,1): DMA clock + \arg RCU_IPA_SLP: IPA clock + \arg RCU_ENET_SLP: ENET clock + \arg RCU_ENETTX_SLP: ENETTX clock + \arg RCU_ENETRX_SLP: ENETRX clock + \arg RCU_ENETPTP_SLP: ENETPTP clock + \arg RCU_USBHS_SLP: USBHS clock + \arg RCU_USBHSULPI_SLP: USBHSULPI clock + \arg RCU_DCI_SLP: DCI clock + \arg RCU_TRNG_SLP: TRNG clock + \arg RCU_USBFS_SLP: USBFS clock + \arg RCU_EXMC_SLP: EXMC clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT_SLP: WWDGT clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock + \arg RCU_PMU_SLP: PMU clock + \arg RCU_DAC_SLP: DAC clock + \arg RCU_RTC_SLP: RTC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock + \arg RCU_SDIO_SLP: SDIO clock + \arg RCU_SYSCFG_SLP: SYSCFG clock + \arg RCU_TLI_SLP: TLI clock + \arg RCU_CTC_SLP: CTC clock + \arg RCU_IREF_SLP: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports + \arg RCU_CRCRST: reset CRC + \arg RCU_DMAxRST (x=0,1): reset DMA + \arg RCU_IPARST: reset IPA + \arg RCU_ENETRST: reset ENET + \arg RCU_USBHSRST: reset USBHS + \arg RCU_DCIRST: reset DCI + \arg RCU_TRNGRST: reset TRNG + \arg RCU_USBFSRST: reset USBFS + \arg RCU_EXMCRST: reset EXMC + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC + \arg RCU_SDIORST: reset SDIO + \arg RCU_SYSCFGRST: reset SYSCFG + \arg RCU_TLIRST: reset TLI + \arg RCU_CTCRST: reset CTC + \arg RCU_IREFRST: reset IREF + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports + \arg RCU_CRCRST: reset CRC + \arg RCU_DMAxRST (x=0,1): reset DMA + \arg RCU_IPARST: reset IPA + \arg RCU_ENETRST: reset ENET + \arg RCU_USBHSRST: reset USBHS + \arg RCU_DCIRST: reset DCI + \arg RCU_TRNGRST: reset TRNG + \arg RCU_USBFSRST: reset USBFS + \arg RCU_EXMCRST: reset EXMC + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC + \arg RCU_SDIORST: reset SDIO + \arg RCU_SYSCFGRST: reset SYSCFG + \arg RCU_TLIRST: reset TLI + \arg RCU_CTCRST: reset CTC + \arg RCU_IREFRST: reset IREF + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC16M: select CK_IRC16M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLLP: select CK_PLLP as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC16M: CK_IRC16M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLLP: CK_PLLP is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB / 2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB / 4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB / 8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB / 16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB / 2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB / 4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB / 8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB / 16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source and divider + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_IRC16M: IRC16M selected + \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_PLLP: PLLP selected + \param[in] ckout0_div: CK_OUT0 divider + \arg RCU_CKOUT0_DIVx(x = 1, 2, 3, 4, 5): CK_OUT0 is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ + reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV); + RCU_CFG0 = (reg | ckout0_src | ckout0_div); +} + +/*! + \brief configure the CK_OUT1 clock source and divider + \param[in] ckout1_src: CK_OUT1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected + \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected + \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT1SRC_PLLP: PLLP selected + \param[in] ckout1_div: CK_OUT1 divider + \arg RCU_CKOUT1_DIVx(x = 1, 2, 3, 4, 5): CK_OUT1 is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ + reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); + RCU_CFG0 = (reg | ckout1_src | ckout1_div); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock + \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock + \param[in] pll_psc: the PLL VCO source clock prescaler + \arg this parameter should be selected between 2 and 63 + \param[in] pll_n: the PLL VCO clock multi factor + \arg this parameter should be selected between 64 and 500 + \param[in] pll_p: the PLLP output frequency division factor from PLL VCO clock + \arg this parameter should be selected 2,4,6,8 + \param[in] pll_q: the PLL Q output frequency division factor from PLL VCO clock + \arg this parameter should be selected between 2 and 15 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q) +{ + uint32_t ss_modulation_inc; + uint32_t ss_modulation_reg; + + ss_modulation_inc = 0U; + ss_modulation_reg = RCU_PLLSSCTL; + + /* calculate the minimum factor of PLLN */ + if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON) { + if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN) { + ss_modulation_inc += RCU_SS_MODULATION_DOWN_INC; + } else { + ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; + } + } + + /* check the function parameter */ + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n, ss_modulation_inc) && + CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)) { + RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | + (pll_src) | (pll_q << 24); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the PLLI2S clock + \param[in] plli2s_n: the PLLI2S VCO clock multi factor + \arg this parameter should be selected between 50 and 500 + \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock + \arg this parameter should be selected between 2 and 7 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) +{ + /* check the function parameter */ + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)) { + RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the PLLSAI clock + \param[in] pllsai_n: the PLLSAI VCO clock multi factor + \arg this parameter should be selected between 50 and 500 + \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock + \arg this parameter should be selected 2,4,6,8 + \param[in] pllsai_r: the PLLSAI R output frequency division factor from PLL VCO clock + \arg this parameter should be selected between 2 and 7 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) +{ + /* check the function parameter */ + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)) { + RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL / RTCDIV selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +/*! + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \param[in] rtc_div: RTC clock frequency division + only one parameter can be selected which is shown as below: + \arg RCU_RTC_HXTAL_NONE: no clock for RTC + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL / x, x = 2....31 + \param[out] none + \retval none +*/ +void rcu_rtc_div_config(uint32_t rtc_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the RTCDIV bits and set according to rtc_div value */ + reg &= ~RCU_CFG0_RTCDIV; + RCU_CFG0 = (reg | rtc_div); +} + + +/*! + \brief configure the I2S clock source selection + \param[in] i2s_clock_source: I2S clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2SSRC_PLLI2S: CK_PLLI2S selected as I2S source clock + \arg RCU_I2SSRC_I2S_CKIN: external i2s_ckin pin selected as I2S source clock + \param[out] none + \retval none +*/ +void rcu_i2s_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the I2SSEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG0_I2SSEL; + RCU_CFG0 = (reg | i2s_clock_source); +} + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to i2s_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief configure the PLL48M clock source selection + \param[in] pll48m_clock_source: PLL48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLL48MSRC_PLLQ: CK_PLLQ selected as PLL48M source clock + \arg RCU_PLL48MSRC_PLLSAIP: CK_PLLSAIP selected as PLL48M source clock + \param[out] none + \retval none +*/ +void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ + reg &= ~RCU_ADDCTL_PLL48MSEL; + RCU_ADDCTL = (reg | pll48m_clock_source); +} + +/*! + \brief configure the TIMER clock prescaler selection + \param[in] timer_clock_prescaler: TIMER clock selection + only one parameter can be selected which is shown as below: + \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) + \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) + \param[out] none + \retval none +*/ +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) +{ + /* configure the TIMERSEL bit and select the TIMER clock prescaler */ + if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) { + RCU_CFG1 &= timer_clock_prescaler; + } else { + RCU_CFG1 |= timer_clock_prescaler; + } +} + +/*! + \brief configure the PLLSAIR divider used as input of TLI + \param[in] pllsai_r_div: PLLSAIR divider used as input of TLI + only one parameter can be selected which is shown as below: + \arg RCU_PLLSAIR_DIVx(x=2,4,8,16): PLLSAIR divided x used as input of TLI + \param[out] none + \retval none +*/ +void rcu_tli_clock_div_config(uint32_t pllsai_r_div) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ + reg &= ~RCU_CFG1_PLLSAIRDIV; + RCU_CFG1 = (reg | pllsai_r_div); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTALDRI_LOWER_DRIVE: lower driving capability + \arg RCU_LXTALDRI_HIGHER_DRIVE: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + uint32_t reg; + + reg = RCU_BDCTL; + + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + reg &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL = (reg | lxtal_dricap); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci) { + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC16M stable */ + case RCU_IRC16M: + while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC48M stable */ + case RCU_IRC48M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC32K stable */ + case RCU_IRC32K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) { + reval = SUCCESS; + } + break; + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + /* wait PLLI2S stable */ + case RCU_PLLI2S_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)) { + reval = SUCCESS; + } + break; + /* wait PLLSAI stable */ + case RCU_PLLSAI_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)) { + reval = SUCCESS; + } + break; + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC16M: + case RCU_IRC48M: + case RCU_IRC32K: + case RCU_PLL_CK: + case RCU_PLLI2S_CK: + case RCU_PLLSAI_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC16M: + case RCU_IRC48M: + case RCU_IRC32K: + case RCU_PLL_CK: + case RCU_PLLI2S_CK: + case RCU_PLLSAI_CK: + break; + default: + break; + } +} + +/*! + \brief set the IRC16M adjust value + \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F + \arg 0x00 - 0x1F + \param[out] none + \retval none +*/ +void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC16MADJ bits and set according to irc16m_adjval */ + reg &= ~RCU_CTL_IRC16MADJ; + RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); +} + +/*! + \brief configure the spread spectrum modulation for the main PLL clock + \param[in] spread_spectrum_type: PLL spread spectrum modulation type select + \arg RCU_SS_TYPE_CENTER: center spread type is selected + \arg RCU_SS_TYPE_DOWN: down spread type is selected + \param[in] modstep: configure PLL spread spectrum modulation profile amplitude and frequency + \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 + \param[in] modcnt: configure PLL spread spectrum modulation profile amplitude and frequency + \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) +{ + uint32_t reg; + + reg = RCU_PLLSSCTL; + /* reset the RCU_PLLSSCTL register bits */ + reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); + RCU_PLLSSCTL = (reg | spread_spectrum_type | modstep << 13 | modcnt); +} + +/*! + \brief enable the PLL spread spectrum modulation + \param[in] none + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_enable(void) +{ + RCU_PLLSSCTL |= RCU_PLLSSCTL_SSCGON; +} + +/*! + \brief disable the PLL spread spectrum modulation + \param[in] none + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_disable(void) +{ + RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON; +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; + + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws) { + /* IRC16M is selected as CK_SYS */ + case SEL_IRC16M: + cksys_freq = IRC16M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLLP is selected as CK_SYS */ + case SEL_PLLP: + /* get the value of PLLPSC[5:0] */ + pllpsc = GET_BITS(RCU_PLL, 0U, 5U); + plln = GET_BITS(RCU_PLL, 6U, 14U); + pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; + /* PLL clock source selection, HXTAL or IRC16M/2 */ + pllsel = (RCU_PLL & RCU_PLL_PLLSEL); + if(RCU_PLLSRC_HXTAL == pllsel) { + ck_src = HXTAL_VALUE; + } else { + ck_src = IRC16M_VALUE; + } + cksys_freq = ((ck_src / pllpsc) * plln) / pllp; + break; + /* IRC16M is selected as CK_SYS */ + default: + cksys_freq = IRC16M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 10, 12); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 13, 15); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag + \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flags + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: Power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c new file mode 100644 index 0000000..d965f78 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c @@ -0,0 +1,1294 @@ +/*! + \file gd32f4xx_rtc.c + \brief RTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_rtc.h" + +/* RTC timeout value */ +#define RTC_WTWF_TIMEOUT ((uint32_t)0x00004000U) /*!< wakeup timer can be write flag timeout */ +#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ +#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ +#define RTC_HRFC_TIMEOUT ((uint32_t)0x20000000U) /*!< recalibration pending flag timeout */ +#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ +#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ + +/*! + \brief reset most of the RTC registers + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_deinit(void) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* RTC_TAMP register is not under write protection */ + RTC_TAMP = RTC_REGISTER_RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + /* reset RTC_CTL register, but RTC_CTL[2��0] */ + RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); + /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. + in order to read calendar from shadow register, not the real registers being reset */ + RTC_TIME = RTC_REGISTER_RESET; + RTC_DATE = RTC_DATE_RESET; + + RTC_PSC = RTC_PSC_RESET; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_CTL &= RTC_REGISTER_RESET; + RTC_WUT = RTC_WUT_RESET; + RTC_COSC = RTC_REGISTER_RESET; + /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ + RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM1TD = RTC_REGISTER_RESET; + RTC_ALRM0SS = RTC_REGISTER_RESET; + RTC_ALRM1SS = RTC_REGISTER_RESET; + /* reset RTC_STAT register, also exit init mode. + at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ + RTC_STAT = RTC_STAT_RESET; + /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ + RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_HRFC = RTC_REGISTER_RESET; + error_status = rtc_register_sync_wait(); + } + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief initialize RTC registers + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + year: 0x0 - 0x99(BCD format) + month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + date: 0x1 - 0x31(BCD format) + day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + minute: 0x0 - 0x59(BCD format) + second: 0x0 - 0x59(BCD format) + factor_asyn: 0x0 - 0x7F + factor_syn: 0x0 - 0x7FFF + am_pm: RTC_AM, RTC_PM + display_format: RTC_24HOUR, RTC_12HOUR + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) +{ + ErrStatus error_status = ERROR; + uint32_t reg_time = 0U, reg_date = 0U; + + reg_date = (DATE_YR(rtc_initpara_struct->year) | \ + DATE_DOW(rtc_initpara_struct->day_of_week) | \ + DATE_MON(rtc_initpara_struct->month) | \ + DATE_DAY(rtc_initpara_struct->date)); + + reg_time = (rtc_initpara_struct->am_pm | \ + TIME_HR(rtc_initpara_struct->hour) | \ + TIME_MN(rtc_initpara_struct->minute) | \ + TIME_SC(rtc_initpara_struct->second)); + + /* 1st: disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* 2nd: enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \ + PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); + + RTC_TIME = (uint32_t)reg_time; + RTC_DATE = (uint32_t)reg_date; + + RTC_CTL &= (uint32_t)(~RTC_CTL_CS); + RTC_CTL |= rtc_initpara_struct->display_format; + + /* 3rd: exit init mode */ + rtc_init_mode_exit(); + + /* 4th: wait the RSYNF flag to set */ + error_status = rtc_register_sync_wait(); + } + + /* 5th: enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enter RTC init mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init_mode_enter(void) +{ + volatile uint32_t time_index = RTC_INITM_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + /* check whether it has been in init mode */ + if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { + RTC_STAT |= RTC_STAT_INITM; + + /* wait until the INITF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + } else { + error_status = SUCCESS; + } + return error_status; +} + +/*! + \brief exit RTC init mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_init_mode_exit(void) +{ + RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); +} + +/*! + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + registers are updated + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_register_sync_wait(void) +{ + volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* firstly clear RSYNF flag */ + RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); + + /* wait until RSYNF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_RSYNF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + } else { + error_status = SUCCESS; + } + + return error_status; +} + +/*! + \brief get current time and date + \param[in] none + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + year: 0x0 - 0x99(BCD format) + month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + date: 0x1 - 0x31(BCD format) + day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + minute: 0x0 - 0x59(BCD format) + second: 0x0 - 0x59(BCD format) + factor_asyn: 0x0 - 0x7F + factor_syn: 0x0 - 0x7FFF + am_pm: RTC_AM, RTC_PM + display_format: RTC_24HOUR, RTC_12HOUR + \retval none +*/ +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) +{ + uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; + + temp_tr = (uint32_t)RTC_TIME; + temp_dr = (uint32_t)RTC_DATE; + temp_pscr = (uint32_t)RTC_PSC; + temp_ctlr = (uint32_t)RTC_CTL; + + /* get current time and construct rtc_parameter_struct structure */ + rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); + rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); + rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); + rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); + rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); + rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); + rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); + rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); + rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); + rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); +} + +/*! + \brief get current subsecond value + \param[in] none + \param[out] none + \retval current subsecond value +*/ +uint32_t rtc_subsecond_get(void) +{ + uint32_t reg = 0U; + /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ + reg = (uint32_t)RTC_SS; + /* read RTC_DATE to unlock the 3 shadow registers */ + (void)(RTC_DATE); + + return reg; +} + +/*! + \brief configure RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + alarm_minute: 0x0 - 0x59(BCD format) + alarm_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrmtd = 0U; + + reg_alrmtd = (rtc_alarm_time->alarm_mask | \ + rtc_alarm_time->weekday_or_date | \ + rtc_alarm_time->am_pm | \ + ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ + ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ + ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ + ALRMTD_SC(rtc_alarm_time->alarm_second)); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_ALRM0TD = (uint32_t)reg_alrmtd; + + } else { + RTC_ALRM1TD = (uint32_t)reg_alrmtd; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure subsecond of RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[in] mask_subsecond: alarm subsecond mask + \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration + \arg RTC_MASKSSC_1_14: mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared + \arg RTC_MASKSSC_2_14: mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared + \arg RTC_MASKSSC_3_14: mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared + \arg RTC_MASKSSC_4_14: mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared + \arg RTC_MASKSSC_5_14: mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared + \arg RTC_MASKSSC_6_14: mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared + \arg RTC_MASKSSC_7_14: mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared + \arg RTC_MASKSSC_8_14: mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared + \arg RTC_MASKSSC_9_14: mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared + \arg RTC_MASKSSC_10_14: mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared + \arg RTC_MASKSSC_11_14: mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared + \arg RTC_MASKSSC_12_14: mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared + \arg RTC_MASKSSC_13_14: mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared + \arg RTC_MASKSSC_14: mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared + \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared + \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) + \param[out] none + \retval none +*/ +void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_ALRM0SS = mask_subsecond | subsecond; + } else { + RTC_ALRM1SS = mask_subsecond | subsecond; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + alarm_minute: 0x0 - 0x59(BCD format) + alarm_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrmtd = 0U; + + /* get the value of RTC_ALRM0TD register */ + if(RTC_ALARM0 == rtc_alarm) { + reg_alrmtd = RTC_ALRM0TD; + } else { + reg_alrmtd = RTC_ALRM1TD; + } + /* get alarm parameters and construct the rtc_alarm_struct structure */ + rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; + rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); + rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); + rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); + rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); + rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); + rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); +} + +/*! + \brief get RTC alarm subsecond + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval RTC alarm subsecond value +*/ +uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) +{ + if(RTC_ALARM0 == rtc_alarm) { + return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); + } else { + return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); + } +} + +/*! + \brief enable RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval none +*/ +void rtc_alarm_enable(uint8_t rtc_alarm) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_CTL |= RTC_CTL_ALRM0EN; + } else { + RTC_CTL |= RTC_CTL_ALRM1EN; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) +{ + volatile uint32_t time_index = RTC_ALRMXWF_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the state of alarm */ + if(RTC_ALARM0 == rtc_alarm) { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + /* wait until ALRM0WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM0WF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } else { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); + /* wait until ALRM1WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM1WF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC time-stamp + \param[in] edge: specify which edge to detect of time-stamp + \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event + \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event + \param[out] none + \retval none +*/ +void rtc_timestamp_enable(uint32_t edge) +{ + uint32_t reg_ctl = 0U; + + /* clear the bits to be configured in RTC_CTL */ + reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); + + /* new configuration */ + reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL = (uint32_t)reg_ctl; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC time-stamp + \param[in] none + \param[out] none + \retval none +*/ +void rtc_timestamp_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the TSEN bit */ + RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC timestamp time and date + \param[in] none + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + parameters for RTC time-stamp configuration + members of the structure and the member values are shown as below: + timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + timestamp_date: 0x1 - 0x31(BCD format) + timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + timestamp_minute: 0x0 - 0x59(BCD format) + timestamp_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) +{ + uint32_t temp_tts = 0U, temp_dts = 0U; + + /* get the value of time_stamp registers */ + temp_tts = (uint32_t)RTC_TTS; + temp_dts = (uint32_t)RTC_DTS; + + /* get timestamp time and construct the rtc_timestamp_struct structure */ + rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); + rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); + rtc_timestamp->timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); + rtc_timestamp->timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); + rtc_timestamp->timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); + rtc_timestamp->timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); + rtc_timestamp->timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); +} + +/*! + \brief get RTC time-stamp subsecond + \param[in] none + \param[out] none + \retval RTC time-stamp subsecond value +*/ +uint32_t rtc_timestamp_subsecond_get(void) +{ + return ((uint32_t)RTC_SSTS); +} + +/*! + \brief RTC time-stamp mapping + \param[in] rtc_af: + \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp + \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp + \param[out] none + \retval none +*/ +void rtc_timestamp_pin_map(uint32_t rtc_af) +{ + RTC_TAMP &= ~RTC_TAMP_TSSEL; + RTC_TAMP |= rtc_af; +} + +/*! + \brief enable RTC tamper + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + parameters for RTC tamper configuration + members of the structure and the member values are shown as below: + detecting tamper event can using edge mode or level mode + (1) using edge mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING + tamper_filter: RTC_FLT_EDGE + tamper_with_timestamp: DISABLE, ENABLE + (2) using level mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, + RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, + RTC_FREQ_DIV512, RTC_FREQ_DIV256 + tamper_precharge_enable: DISABLE, ENABLE + tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C + tamper_with_timestamp: DISABLE, ENABLE + \param[out] none + \retval none +*/ +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); + + /* tamper filter must be used when the tamper source is voltage level detection */ + RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; + + /* the tamper source is voltage level detection */ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); + + /* check if the tamper pin need precharge, if need, then configure the precharge time */ + if(DISABLE == rtc_tamper->tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); + } + + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + } else { + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + } + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + if(DISABLE != rtc_tamper->tamper_with_timestamp) { + /* the tamper event also cause a time-stamp event */ + RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; + } + /* enable tamper */ + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); +} + +/*! + \brief disable RTC tamper + \param[in] source: specify which tamper source to be disabled + \arg RTC_TAMPER0 + \arg RTC_TAMPER1 + \param[out] none + \retval none +*/ +void rtc_tamper_disable(uint32_t source) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~source; + +} + +/*! + \brief RTC tamper0 mapping + \param[in] rtc_af: + \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 + \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 + \param[out] none + \retval none +*/ +void rtc_tamper0_pin_map(uint32_t rtc_af) +{ + RTC_TAMP &= ~(RTC_TAMP_TP0EN | RTC_TAMP_TP0SEL); + RTC_TAMP |= rtc_af; +} + +/*! + \brief enable specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be enabled + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM0: alarm0 interrupt + \arg RTC_INT_ALARM1: alarm1 interrupt + \arg RTC_INT_TAMP: tamper detection interrupt + \arg RTC_INT_WAKEUP: wakeup timer interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enable the interrupts in RTC_CTL register */ + RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* enable the interrupts in RTC_TAMP register */ + RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disble specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be disabled + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM0: alarm interrupt + \arg RTC_INT_ALARM1: alarm interrupt + \arg RTC_INT_TAMP: tamper detection interrupt + \arg RTC_INT_WAKEUP: wakeup timer interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* disable the interrupts in RTC_CTL register */ + RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* disable the interrupts in RTC_TAMP register */ + RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief check specified flag + \param[in] flag: specify which flag to check + \arg RTC_STAT_SCP: smooth calibration pending flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_ALRM0: alarm0 occurs flag + \arg RTC_FLAG_ALRM1: alarm1 occurs flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_INIT: initialization state flag + \arg RTC_FLAG_RSYN: register synchronization flag + \arg RTC_FLAG_YCM: year configuration mark status flag + \arg RTC_FLAG_SOP: shift function operation pending flag + \arg RTC_FLAG_ALRM0W: alarm0 configuration can be write flag + \arg RTC_FLAG_ALRM1W: alarm1 configuration can be write flag + \arg RTC_FLAG_WTW: wakeup timer can be write flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + FlagStatus flag_state = RESET; + + if((uint32_t)RESET != (RTC_STAT & flag)) { + flag_state = SET; + } + return flag_state; +} + +/*! + \brief clear specified flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_RSYN: register synchronization flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + RTC_STAT &= (uint32_t)(~flag); +} + +/*! + \brief configure rtc alarm output source + \param[in] source: specify signal to output + \arg RTC_ALARM0_HIGH: when the alarm0 flag is set, the output pin is high + \arg RTC_ALARM0_LOW: when the alarm0 flag is set, the output pin is low + \arg RTC_ALARM1_HIGH: when the alarm1 flag is set, the output pin is high + \arg RTC_ALARM1_LOW: when the alarm1 flag is set, the output pin is low + \arg RTC_WAKEUP_HIGH: when the wakeup flag is set, the output pin is high + \arg RTC_WAKEUP_LOW: when the wakeup flag is set, the output pin is low + \param[in] mode: specify the output pin mode when output alarm signal + \arg RTC_ALARM_OUTPUT_OD: open drain mode + \arg RTC_ALARM_OUTPUT_PP: push pull mode + \param[out] none + \retval none +*/ +void rtc_alarm_output_config(uint32_t source, uint32_t mode) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= ~(RTC_CTL_OS | RTC_CTL_OPOL); + RTC_TAMP &= ~RTC_TAMP_AOT; + + RTC_CTL |= (uint32_t)(source); + /* alarm output */ + RTC_TAMP |= (uint32_t)(mode); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure rtc calibration output source + \param[in] source: specify signal to output + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal + \param[out] none + \retval none +*/ +void rtc_calibration_output_config(uint32_t source) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_COS); + + RTC_CTL |= (uint32_t)(source); + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief adjust the daylight saving time by adding or substracting one hour from the current time + \param[in] operation: hour adjustment operation + \arg RTC_CTL_A1H: add one hour + \arg RTC_CTL_S1H: substract one hour + \param[out] none + \retval none +*/ +void rtc_hour_adjust(uint32_t operation) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint32_t)(operation); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief adjust RTC second or subsecond value of current time + \param[in] add: add 1s to current time or not + \arg RTC_SHIFT_ADD1S_RESET: no effect + \arg RTC_SHIFT_ADD1S_SET: add 1s to current time + \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) +{ + volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + uint32_t temp = 0U; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a shift operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SOPF; + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + /* check if the function of reference clock detection is disabled */ + temp = RTC_CTL & RTC_CTL_REFEN; + if((RESET == flag_status) && (RESET == temp)) { + RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= ~RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_enable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief disable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_disable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC auto wakeup function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_wakeup_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_WTEN; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC auto wakeup function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_disable(void) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + RTC_CTL &= ~RTC_CTL_WTEN; + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief set RTC auto wakeup timer clock + \param[in] wakeup_clock: + \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 + \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 + \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 + \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 + \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre + \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; + RTC_CTL |= (uint32_t)wakeup_clock; + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief set wakeup timer value + \param[in] wakeup_timer: 0x0000-0xffff + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_WUT = (uint32_t)wakeup_timer; + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief get wakeup timer value + \param[in] none + \param[out] none + \retval wakeup timer value +*/ +uint16_t rtc_wakeup_timer_get(void) +{ + return (uint16_t)RTC_WUT; +} + +/*! + \brief configure RTC smooth calibration + \param[in] window: select calibration window + \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz + \param[in] plus: add RTC clock or not + \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock + \arg RTC_CALIBRATION_PLUS_RESET: no effect + \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) +{ + volatile uint32_t time_index = RTC_HRFC_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a smooth calibration operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SCPF; + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET == flag_status) { + RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC coarse calibration + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_enable(void) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_CCEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief disable RTC coarse calibration + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_disable(void) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief config coarse calibration direction and step + \param[in] direction: CALIB_INCREASE or CALIB_DECREASE + \param[in] step: 0x00-0x1F + COSD=0: + 0x00:+0 PPM + 0x01:+4 PPM + 0x02:+8 PPM + .... + 0x1F:+126 PPM + COSD=1: + 0x00:-0 PPM + 0x01:-2 PPM + 0x02:-4 PPM + .... + 0x1F:-63 PPM + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + if(CALIB_DECREASE == direction) { + RTC_COSC |= (uint32_t)RTC_COSC_COSD; + } else { + RTC_COSC &= (uint32_t)~RTC_COSC_COSD; + } + RTC_COSC &= ~RTC_COSC_COSS; + RTC_COSC |= (uint32_t)((uint32_t)step & 0x1FU); + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c new file mode 100644 index 0000000..867e97d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c @@ -0,0 +1,804 @@ +/*! + \file gd32f4xx_sdio.c + \brief SDIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_sdio.h" + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + rcu_periph_reset_enable(RCU_SDIORST); + rcu_periph_reset_disable(RCU_SDIORST); +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 512 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); + /* if the clock division is greater or equal to 256, set the DIV[8] */ + if(clock_division >= 256U) { + clock_config |= SDIO_CLKCTL_DIV8; + clock_division -= 256U; + } + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* disable the CSM */ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] sdio_responsex: SDIO response + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t sdio_responsex) +{ + uint32_t resp_content = 0U; + switch(sdio_responsex) { + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & int_flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if(SDIO_READWAITTYPE_CLK == readwait_type) { + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + } else { + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c new file mode 100644 index 0000000..68daff8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c @@ -0,0 +1,880 @@ +/*! + \file gd32f4xx_spi.c + \brief SPI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_spi.h" +#include "gd32f4xx_rcu.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ +#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */ + +/* default value */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ + +/*! + \brief deinitialize SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph) { + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1,I2S1 and I2S1_ADD */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2,I2S2 and I2S2_ADD */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + case SPI3: + /* reset SPI3 */ + rcu_periph_reset_enable(RCU_SPI3RST); + rcu_periph_reset_disable(RCU_SPI3RST); + break; + case SPI4: + /* reset SPI4 */ + rcu_periph_reset_enable(RCU_SPI4RST); + rcu_periph_reset_disable(RCU_SPI4RST); + break; + case SPI5: + /* reset SPI5 */ + rcu_periph_reset_enable(RCU_SPI5RST); + rcu_periph_reset_disable(RCU_SPI5RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with default values + \param[in] none + \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the structure with default value */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; + spi_struct->endian = SPI_ENDIAN_MSB; +} +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE. + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI nss use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)i2s_mode; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescale + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] i2s_frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] i2s_mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + +#ifndef I2S_EXTERNAL_CLOCK_IN + uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; +#endif /* I2S_EXTERNAL_CLOCK_IN */ + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + +#ifdef I2S_EXTERNAL_CLOCK_IN + rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN); + + /* set the I2S clock to the external clock input value */ + i2sclock = I2S_EXTERNAL_CLOCK_IN; +#else + + /* turn on the oscillator HXTAL */ + rcu_osci_on(RCU_HXTAL); + /* wait for oscillator stabilization flags is SET */ + rcu_osci_stab_wait(RCU_HXTAL); + /* turn on the PLLI2S */ + rcu_osci_on(RCU_PLLI2S_CK); + /* wait for PLLI2S flags is SET */ + rcu_osci_stab_wait(RCU_PLLI2S_CK); + /* configure the I2S clock source selection */ + rcu_i2s_clock_config(RCU_I2SSRC_PLLI2S); + + /* get the RCU_PLL_PLLPSC value */ + plli2sm = (uint32_t)(RCU_PLL & RCU_PLL_PLLPSC); + /* get the RCU_PLLI2S_PLLI2SN value */ + plli2sn = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SN) >> 6); + /* get the RCU_PLLI2S_PLLI2SR value */ + plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28); + + if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); + } else { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); + } +#endif /* I2S_EXTERNAL_CLOCK_IN */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == i2s_mckout) { + clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / i2s_audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / i2s_audiosample); + } + } + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI nss output + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI nss output + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI nss pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI nss pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma) { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + } else { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief diable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma) { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + } else { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc) +{ + if(SPI_CRC_TX == spi_crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief configure i2s full duplex mode + \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) + \param[in] i2s_mode: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[in] i2s_frameformat: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[out] none + \retval none +*/ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, + uint32_t i2s_ckpl, uint32_t i2s_frameformat) +{ + uint32_t reg = 0U, tmp = 0U; + + reg = I2S_ADD_I2SCTL(i2s_add_periph); + reg &= I2S_FULL_DUPLEX_MASK; + + /* get the mode of the extra I2S module I2Sx_ADD */ + if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { + tmp = I2S_MODE_SLAVERX; + } else { + tmp = I2S_MODE_SLAVETX; + } + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)tmp; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + /* configure data frame format */ + reg |= (uint32_t)i2s_frameformat; + + /* write to SPI_I2SCTL register */ + I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt flag status + only one parameter can be selected which are shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE : + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE : + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR : + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR : + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR : + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR : + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR : + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if(reg1 && reg2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) +{ + if(SPI_STAT(spi_periph) & spi_i2s_flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c new file mode 100644 index 0000000..6b11c01 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c @@ -0,0 +1,205 @@ +/*! + \file gd32f4xx_syscfg.c + \brief SYSCFG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_syscfg.h" + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_SYSCFGRST); + rcu_periph_reset_disable(RCU_SYSCFGRST); +} + +/*! + \brief configure the boot mode + \param[in] syscfg_bootmode: selects the memory remapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_SRAM: SRAM0 of on-chip SRAM (0x20000000~0x2001BFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_EXMC_SDRAM: SDRAM bank0 of EXMC (0xC0000000~0xC7FFFFFF) is mapped at address 0x00000000 + \param[out] none + \retval none +*/ +void syscfg_bootmode_config(uint8_t syscfg_bootmode) +{ + /* reset the SYSCFG_CFG0_BOOT_MODE bit and set according to syscfg_bootmode */ + SYSCFG_CFG0 &= ~SYSCFG_CFG0_BOOT_MODE; + SYSCFG_CFG0 |= (uint32_t)syscfg_bootmode; +} + +/*! + \brief FMC memory mapping swap + \param[in] syscfg_fmc_swap: selects the interal flash bank swapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 + \arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000 + \param[out] none + \retval none +*/ +void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) +{ + uint32_t reg; + reg = SYSCFG_CFG0; + /* reset the FMC_SWP bit and set according to syscfg_fmc_swap */ + reg &= ~SYSCFG_CFG0_FMC_SWP; + SYSCFG_CFG0 = (reg | syscfg_fmc_swap); +} + +/*! + \brief EXMC memory mapping swap + \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card + \arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap + \param[out] none + \retval none +*/ +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) +{ + uint32_t reg; + + reg = SYSCFG_CFG0; + /* reset the SYSCFG_CFG0_EXMC_SWP bits and set according to syscfg_exmc_swap */ + reg &= ~SYSCFG_CFG0_EXMC_SWP; + SYSCFG_CFG0 = (reg | syscfg_exmc_swap); +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port + \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP) { + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief configure the PHY interface for the ethernet MAC + \param[in] syscfg_enet_phy_interface: specifies the media interface mode. + only one parameter can be selected which is shown as below: + \arg SYSCFG_ENET_PHY_MII: MII mode is selected + \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected + \param[out] none + \retval none +*/ +void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) +{ + uint32_t reg; + + reg = SYSCFG_CFG1; + /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ + reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; + SYSCFG_CFG1 = (reg | syscfg_enet_phy_interface); +} + +/*! + \brief configure the I/O compensation cell + \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: + \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void syscfg_compensation_config(uint32_t syscfg_compensation) +{ + uint32_t reg; + + reg = SYSCFG_CPSCTL; + /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ + reg &= ~SYSCFG_CPSCTL_CPS_EN; + SYSCFG_CPSCTL = (reg | syscfg_compensation); +} + +/*! + \brief checks whether the I/O compensation cell ready flag is set or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus syscfg_flag_get(void) +{ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) { + return SET; + } else { + return RESET; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c new file mode 100644 index 0000000..a04d72d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c @@ -0,0 +1,2064 @@ +/*! + \file gd32f4xx_timer.c + \brief TIMER driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct *initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,(TIMER1,TIMER4,32 bit) + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value,0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value,0~65535 + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value,0~65535 + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel) { + /* read TIMER channel 0 capture compare register value */ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + /* read TIMER channel 1 capture compare register value */ + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + /* read TIMER channel 2 capture compare register value */ + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + /* read TIMER channel 3 capture compare register value */ + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11)) + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel remap function + \param[in] timer_periph: TIMERx(x=1,4,10) + \param[in] remap: + only one parameter can be selected which is shown as below: + \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO + \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP + \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF + \arg TIMER1_ITI1_RMP_USB_HS_SOF: timer1 internal trigger input1 remap to USB HS SOF + \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin + \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K + \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL + \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt + \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting + \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if(TIMER_CHVSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] outsel: + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if(TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c new file mode 100644 index 0000000..04f9e31 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c @@ -0,0 +1,598 @@ +/*! + \file gd32f4xx_tli.c + \brief TLI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_tli.h" + +#define TLI_DEFAULT_VALUE 0x00000000U +#define TLI_OPAQUE_VALUE 0x000000FFU + +/*! + \brief deinitialize TLI registers + \param[in] none + \param[out] none + \retval none +*/ +void tli_deinit(void) +{ + rcu_periph_reset_enable(RCU_TLIRST); + rcu_periph_reset_disable(RCU_TLIRST); +} + +/*! + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined + \param[in] none + \param[out] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \retval none +*/ +void tli_struct_para_init(tli_parameter_struct *tli_struct) +{ + /* initialize the struct parameters with default values */ + tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; + tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; + tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; + tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; + tli_struct->backcolor_red = TLI_DEFAULT_VALUE; + tli_struct->backcolor_green = TLI_DEFAULT_VALUE; + tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; + tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; + tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; +} + +/*! + \brief initialize TLI display timing parameters + \param[in] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \param[out] none + \retval none +*/ +void tli_init(tli_parameter_struct *tli_struct) +{ + /* synchronous pulse size configuration */ + TLI_SPSZ &= ~(TLI_SPSZ_VPSZ | TLI_SPSZ_HPSZ); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz | ((uint32_t)tli_struct->synpsz_hpsz << 16U)); + /* back-porch size configuration */ + TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); + /* active size configuration */ + TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); + TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); + /* total size configuration */ + TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); + TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); + /* background color configuration */ + TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); + TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); + TLI_CTL &= ~(TLI_CTL_HPPS | TLI_CTL_VPPS | TLI_CTL_DEPS | TLI_CTL_CLKPS); + TLI_CTL |= (tli_struct->signalpolarity_hs | tli_struct->signalpolarity_vs | \ + tli_struct->signalpolarity_de | tli_struct->signalpolarity_pixelck); + +} + +/*! + \brief configure TLI dither function + \param[in] dither_stat + only one parameter can be selected which is shown as below: + \arg TLI_DITHER_ENABLE + \arg TLI_DITHER_DISABLE + \param[out] none + \retval none +*/ +void tli_dither_config(uint8_t dither_stat) +{ + if(TLI_DITHER_ENABLE == dither_stat) { + TLI_CTL |= TLI_CTL_DFEN; + } else { + TLI_CTL &= ~(TLI_CTL_DFEN); + } +} + +/*! + \brief enable TLI + \param[in] none + \param[out] none + \retval none +*/ +void tli_enable(void) +{ + TLI_CTL |= TLI_CTL_TLIEN; +} + +/*! + \brief disable TLI + \param[in] none + \param[out] none + \retval none +*/ +void tli_disable(void) +{ + TLI_CTL &= ~(TLI_CTL_TLIEN); +} + +/*! + \brief configure TLI reload mode + \param[in] reload_mod + only one parameter can be selected which is shown as below: + \arg TLI_FRAME_BLANK_RELOAD_EN + \arg TLI_REQUEST_RELOAD_EN + \param[out] none + \retval none +*/ +void tli_reload_config(uint8_t reload_mod) +{ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod) { + /* the layer configuration will be reloaded at frame blank */ + TLI_RL |= TLI_RL_FBR; + } else { + /* the layer configuration will be reloaded after this bit sets */ + TLI_RL |= TLI_RL_RQR; + } +} + +/*! + \brief initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined + \param[in] none + \param[out] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number + \retval none +*/ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) +{ + /* initialize the struct parameters with default values */ + layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; + layer_struct->layer_ppf = LAYER_PPF_ARGB8888; + layer_struct->layer_sa = TLI_OPAQUE_VALUE; + layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; + layer_struct->layer_default_red = TLI_DEFAULT_VALUE; + layer_struct->layer_default_green = TLI_DEFAULT_VALUE; + layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; + layer_struct->layer_acf1 = LAYER_ACF1_PASA; + layer_struct->layer_acf2 = LAYER_ACF2_PASA; + layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[in] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number + \param[out] none + \retval none +*/ +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct) +{ + /* configure layer window horizontal position */ + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos | ((uint32_t)layer_struct->layer_window_rightpos << 16U)); + /* configure layer window vertical position */ + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos | ((uint32_t)layer_struct->layer_window_bottompos << 16U)); + /* configure layer packeted pixel format */ + TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); + TLI_LxPPF(layerx) = layer_struct->layer_ppf; + /* configure layer specified alpha */ + TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); + TLI_LxSA(layerx) = layer_struct->layer_sa; + /* configure layer default color */ + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB | (TLI_LxDC_DCG) | (TLI_LxDC_DCR) | (TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | ((uint32_t)layer_struct->layer_default_green << 8U) + | ((uint32_t)layer_struct->layer_default_red << 16U) + | ((uint32_t)layer_struct->layer_default_alpha << 24U)); + + /* configure layer alpha calculation factors */ + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2 | (TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2) | (layer_struct->layer_acf1)); + /* configure layer frame buffer base address */ + TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); + TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); + /* configure layer frame line length */ + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL | (TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length | ((uint32_t)layer_struct->layer_frame_buf_stride_offset << 16U)); + /* configure layer frame total line number */ + TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); + TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); + +} + +/*! + \brief reconfigure window position + \param[in] layerx: LAYERx(x=0,1) + \param[in] offset_x: new horizontal offset + \param[in] offset_y: new vertical offset + \param[out] none + \retval none +*/ +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y) +{ + /* configure window start position */ + uint32_t layer_ppf, line_num, hstart, vstart; + uint32_t line_length = 0U; + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x + (((TLI_BPSZ & TLI_BPSZ_HBPSZ) >> 16U) + 1U); + vstart = (uint32_t)offset_y + ((TLI_BPSZ & TLI_BPSZ_VBPSZ) + 1U); + line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); + layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); + /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ + switch(layer_ppf) { + case LAYER_PPF_ARGB8888: + /* each pixel includes 4bytes, when pixel format is ARGB8888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 4U); + break; + case LAYER_PPF_RGB888: + /* each pixel includes 3bytes, when pixel format is RGB888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 3U); + break; + case LAYER_PPF_RGB565: + case LAYER_PPF_ARGB1555: + case LAYER_PPF_ARGB4444: + case LAYER_PPF_AL88: + /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 2U); + break; + case LAYER_PPF_L8: + case LAYER_PPF_AL44: + /* each pixel includes 1byte, when pixel format is L8 or AL44 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U)); + break; + default: + break; + } + /* reconfigure window position */ + TLI_LxHPOS(layerx) = (hstart | ((hstart + line_length - 1U) << 16U)); + TLI_LxVPOS(layerx) = (vstart | ((vstart + line_num - 1U) << 16U)); +} + +/*! + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined + \param[in] none + \param[out] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \retval none +*/ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) +{ + /* initialize the struct parameters with default values */ + lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[in] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \param[out] none + \retval none +*/ +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct) +{ + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) + | ((uint32_t)lut_struct->layer_lut_channel_red << 16U + | ((uint32_t)lut_struct->layer_table_addr << 24U))); +} + +/*! + \brief initialize TLI layer color key + \param[in] layerx: LAYERx(x=0,1) + \param[in] redkey: color key red + \param[in] greenkey: color key green + \param[in] bluekey: color key blue + \param[out] none + \retval none +*/ +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey) +{ + TLI_LxCKEY(layerx) = (((uint32_t)bluekey) | ((uint32_t)greenkey << 8U) | ((uint32_t)redkey << 16U)); +} + +/*! + \brief enable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; +} + +/*! + \brief disable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); +} + +/*! + \brief enable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; +} + +/*! + \brief disable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); +} + +/*! + \brief enable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; +} + +/*! + \brief disable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); +} + +/*! + \brief set line mark value + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void tli_line_mark_set(uint16_t line_num) +{ + TLI_LM &= ~(TLI_LM_LM); + TLI_LM = (uint32_t)line_num; +} + +/*! + \brief get current displayed position + \param[in] none + \param[out] none + \retval position of current pixel +*/ +uint32_t tli_current_pos_get(void) +{ + return TLI_CPPOS; +} + +/*! + \brief enable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_enable(uint32_t int_flag) +{ + TLI_INTEN |= (int_flag); +} + +/*! + \brief disable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_disable(uint32_t int_flag) +{ + TLI_INTEN &= ~(int_flag); +} + +/*! + \brief get TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state; + state = TLI_INTF; + if(state & int_flag) { + state = TLI_INTEN; + if(state & int_flag) { + return SET; + } + } + return RESET; +} + +/*! + \brief clear TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval none +*/ +void tli_interrupt_flag_clear(uint32_t int_flag) +{ + TLI_INTC |= (int_flag); +} + +/*! + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \param[in] flag: TLI flags or states + only one parameter can be selected which is shown as below: + \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_HDE: current HDE state + \arg TLI_FLAG_VS: current VS status of the TLI + \arg TLI_FLAG_HS: current HS status of the TLI + \arg TLI_FLAG_LM: line mark interrupt flag + \arg TLI_FLAG_FE: FIFO error interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_flag_get(uint32_t flag) +{ + uint32_t stat; + /* choose which register to get flag or state */ + if(flag >> 31U) { + stat = TLI_INTF; + } else { + stat = TLI_STAT; + } + if(flag & stat) { + return SET; + } else { + return RESET; + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c new file mode 100644 index 0000000..8330a57 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c @@ -0,0 +1,156 @@ +/*! + \file gd32f4xx_trng.c + \brief TRNG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_trng.h" + +/*! + \brief reset TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_deinit(void) +{ + rcu_periph_reset_enable(RCU_TRNGRST); + rcu_periph_reset_disable(RCU_TRNGRST); +} + +/*! + \brief enable TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_enable(void) +{ + TRNG_CTL |= TRNG_CTL_TRNGEN; +} + +/*! + \brief disable TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_disable(void) +{ + TRNG_CTL &= ~TRNG_CTL_TRNGEN; +} + +/*! + \brief get the true random data + \param[in] none + \param[out] none + \retval uint32_t: 0x0-0xFFFFFFFF +*/ +uint32_t trng_get_true_random_data(void) +{ + return (TRNG_DATA); +} + +/*! + \brief enable TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_enable(void) +{ + TRNG_CTL |= TRNG_CTL_TRNGIE; +} + +/*! + \brief disable TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_disable(void) +{ + TRNG_CTL &= ~TRNG_CTL_TRNGIE; +} + +/*! + \brief get TRNG flag status + \param[in] flag: TRNG flag + only one parameter can be selected which is shown as below: + \arg TRNG_FLAG_DRDY: random Data ready status + \arg TRNG_FLAG_CECS: clock error current status + \arg TRNG_FLAG_SECS: seed error current status + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus trng_flag_get(trng_flag_enum flag) +{ + if(RESET != (TRNG_STAT & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag + only one parameter can be selected which is shown as below: + \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) +{ + if(RESET != (TRNG_STAT & int_flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag + only one parameter can be selected which is shown as below: + \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag + \param[out] none + \retval none +*/ +void trng_interrupt_flag_clear(trng_int_flag_enum int_flag) +{ + TRNG_STAT &= ~(uint32_t)int_flag; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c new file mode 100644 index 0000000..d7fc2bc --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c @@ -0,0 +1,1009 @@ +/*! + \file gd32f4xx_usart.c + \brief USART driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_usart.h" + +/* USART register bit offset */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph) { + case USART0: + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case USART5: + rcu_periph_reset_enable(RCU_USART5RST); + rcu_periph_reset_disable(RCU_USART5RST); + break; + case UART3: + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + case UART6: + rcu_periph_reset_enable(RCU_UART6RST); + rcu_periph_reset_disable(RCU_UART6RST); + break; + case UART7: + rcu_periph_reset_enable(RCU_UART7RST); + rcu_periph_reset_disable(RCU_UART7RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ + case USART0: + uclk = rcu_clock_freq_get(CK_APB2); + break; + case USART5: + uclk = rcu_clock_freq_get(CK_APB2); + break; + case USART1: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case USART2: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART3: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART4: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART6: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART7: + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { + /* when oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U * uclk) + baudval / 2U) / baudval; + intdiv = udiv & 0xfff0U; + fradiv = (udiv >> 1U) & 0x7U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } else { + /* when oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; + intdiv = udiv & 0xfff0U; + fradiv = udiv & 0xfU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_EVEN: even parity + \arg USART_PM_ODD: odd parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN Bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL3(usart_periph); + ctl &= ~(USART_CTL3_MSBF); + ctl |= msbf; + /* configure data transmitted/received mode */ + USART_CTL3(usart_periph) = ctl; +} + +/*! + \brief configure USART inversion + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] invertpara: refer to enum USART_INVERT_CONFIG + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + /* inverted or not the specified siginal */ + switch(invertpara) { + case USART_DINV_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_DINV; + break; + case USART_TXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_TINV; + break; + case USART_RXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_RINV; + break; + case USART_DINV_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); + break; + case USART_TXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); + break; + case USART_RXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); + break; + default: + break; + } +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: 8 bits + \arg USART_OVSMOD_16: 16 bits + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure sample bit method + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] obsm: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1bit: 1 bit + \arg USART_OSB_3bit: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= obsm; +} + +/*! + \brief enable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) |= USART_CTL3_RTEN; +} + +/*! + \brief disable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); +} + +/*! + \brief set the receiver timeout threshold of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] rtimeout: 0-0x00FFFFFF + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] wmehtod: two method be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmehtod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] clen: CK length + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] guat: guard time value, 0-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] scrtnum: smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << CTL3_SCRTNUM_OFFSET)); +} + +/*! + \brief configure block length in Smartcard T=1 reception + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] bl: block length + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] psc: 0-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure break frame coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] bcm: + only one parameter can be selected which is shown as below: + \arg USART_BCM_NONE: no parity error is detected + \arg USART_BCM_EN: parity error is detected + \param[out] none + \retval none +*/ +void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_BCM); + USART_CHC(usart_periph) |= (USART_CHC_BCM & bcm); +} + +/*! + \brief configure parity check coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] pcm: + only one parameter can be selected which is shown as below: + \arg USART_PCM_NONE: not check parity + \arg USART_PCM_EN: check the parity + \param[out] none + \retval none +*/ +void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_PCM); + USART_CHC(usart_periph) |= (USART_CHC_PCM & pcm); +} + +/*! + \brief configure hardware flow control coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] hcm: + only one parameter can be selected which is shown as below: + \arg USART_HCM_NONE: nRTS signal equals to the rxne status register + \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled + \param[out] none + \retval none +*/ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_HCM); + USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT0/STAT1/CHC register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag in STAT0/STAT1/CHC register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag + \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c new file mode 100644 index 0000000..8b85c68 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c @@ -0,0 +1,129 @@ +/*! + \file gd32f4xx_wwdgt.c + \brief WWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_wwdgt.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + /* configure WIN and PSC bits, configure CNT bit */ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT = (uint32_t)(RESET); +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s new file mode 100644 index 0000000..4e08f72 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s @@ -0,0 +1,423 @@ +;/*! +; \file startup_gd32f405_425.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD 0 ; 64:Reserved + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD 0 ; 77:Reserved + DCD 0 ; 78:Reserved + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT DMA0_Channel7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT USBHS_EP1_Out_IRQHandler [WEAK] + EXPORT USBHS_EP1_In_IRQHandler [WEAK] + EXPORT USBHS_WKUP_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT DCI_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +DMA0_Channel7_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_DAC_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +USART5_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +USBHS_EP1_Out_IRQHandler +USBHS_EP1_In_IRQHandler +USBHS_WKUP_IRQHandler +USBHS_IRQHandler +DCI_IRQHandler +TRNG_IRQHandler +FPU_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S new file mode 100644 index 0000000..f5a8ba1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S @@ -0,0 +1,522 @@ +/** \file startup_gd32f405_425_gas.S *************************************** + * + * Startup code for GD32F405 / GD32F425 + * To be used with GCC / GNU Assembler + * and linker scripts gd32f425.ld / gd32f425-tmcm.ld. + * + * Revision History: + * 2023_01_05 Rev 1.00 Olav Kahlbaum File created + * + * -------------------------------------------------------------------- */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + + .global g_pfnVectors + + .word _sidata + .word _sdata + .word _edata + .word _sbss + .word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* top of stack */ + .word Reset_Handler /* Reset Handler */ + .word NMI_Handler /* NMI Handler */ + .word HardFault_Handler /* Hard Fault Handler */ + .word MemManage_Handler /* MPU Fault Handler */ + .word BusFault_Handler /* Bus Fault Handler */ + .word UsageFault_Handler /* Usage Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* SVCall Handler */ + .word DebugMon_Handler /* Debug Monitor Handler */ + .word 0 /* Reserved */ + .word PendSV_Handler /* PendSV Handler */ + .word SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */ + .word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */ + .word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp Interrupt */ + .word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */ + .word FMC_IRQHandler /* Vector Number 20,FMC */ + .word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC*/ + .word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */ + .word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */ + .word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */ + .word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */ + .word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */ + .word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel 0 */ + .word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel 1 */ + .word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel 2 */ + .word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel 3 */ + .word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel 4 */ + .word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel 5 */ + .word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel 6 */ + .word ADC_IRQHandler /* Vector Number 34,ADC0 and ADC1 */ + .word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */ + .word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */ + .word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */ + .word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */ + .word EXTI5_9_IRQHandler /* Vector Number 39,EXTI Line 5 to EXTI Line 9 */ + .word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 global */ + .word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 global */ + .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global */ + .word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */ + .word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */ + .word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */ + .word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */ + .word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */ + .word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */ + .word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */ + .word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */ + .word SPI0_IRQHandler /* Vector Number 51,SPI0 */ + .word SPI1_IRQHandler /* Vector Number 52,SPI1 */ + .word USART0_IRQHandler /* Vector Number 53,USART0 */ + .word USART1_IRQHandler /* Vector Number 54,USART1 */ + .word USART2_IRQHandler /* Vector Number 55,USART2 */ + .word EXTI10_15_IRQHandler /* Vector Number 56,EXTI Line 10 to EXTI Line 15 */ + .word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm through EXTI Line */ + .word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS WakeUp from suspend through EXTI Line */ + .word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break Interrupt and TIMER11 global */ + .word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update Interrupt and TIMER12 global */ + .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 */ + .word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */ + .word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */ + .word 0 /* Vector Number 64,Reserverd */ + .word SDIO_IRQHandler /* Vector Number 65,SDIO */ + .word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */ + .word SPI2_IRQHandler /* Vector Number 67,SPI2 */ + .word UART3_IRQHandler /* Vector Number 68,UART3 */ + .word UART4_IRQHandler /* Vector Number 69,UART4 */ + .word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC */ + .word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */ + .word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */ + .word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */ + .word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */ + .word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */ + .word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */ + .word 0 /* Vector Number 77,Reserved */ + .word 0 /* Vector Number 78,Reserved */ + .word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */ + .word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX 0*/ + .word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */ + .word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */ + .word USBFS_IRQHandler /* Vector Number 83,USBFS */ + .word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */ + .word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */ + .word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */ + .word USART5_IRQHandler /* Vector Number 87,USART5 */ + .word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */ + .word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */ + .word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */ + .word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 In */ + .word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through ETXI Line */ + .word USBHS_IRQHandler /* Vector Number 93,USBHS */ + .word DCI_IRQHandler /* Vector Number 94,DCI */ + .word 0 /* Vector Number 95,Reserved */ + .word TRNG_IRQHandler /* Vector Number 96,TRNG */ + .word FPU_IRQHandler /* Vector Number 97,FPU */ + +/************************************ + * Default interrupt handlers. +*************************************/ + + .weak NMI_Handler +NMI_Handler: + b NMI_Handler + + .weak HardFault_Handler +HardFault_Handler: + b HardFault_Handler + + .weak MemManage_Handler +MemManage_Handler: + b MemManage_Handler + + .weak BusFault_Handler +BusFault_Handler: + b BusFault_Handler + + .weak UsageFault_Handler +UsageFault_Handler: + b UsageFault_Handler + + .weak SVC_Handler +SVC_Handler: + b SVC_Handler + + .weak DebugMon_Handler +DebugMon_Handler: + b DebugMon_Handler + + .weak PendSV_Handler +PendSV_Handler: + b PendSV_Handler + + .weak SysTick_Handler +SysTick_Handler: + b SysTick_Handler + + .weak WWDGT_IRQHandler +WWDGT_IRQHandler: + b WWDGT_IRQHandler + + .weak LVD_IRQHandler +LVD_IRQHandler: + b LVD_IRQHandler + + .weak TAMPER_STAMP_IRQHandler +TAMPER__STAMP_IRQHandler: + b TAMPER_STAMP_IRQHandler + + .weak RTC_WKUP_IRQHandler +RTC_WKUP_IRQHandler: + b RTC_WKUP_IRQHandler + + .weak FMC_IRQHandler +FMC_IRQHandler: + b FMC_IRQHandler + + .weak RCU_CTC_IRQHandler +RCU_CTC_IRQHandler: + b RCU_CTC_IRQHandler + + .weak EXTI0_IRQHandler +EXTI0_IRQHandler: + b EXTI0_IRQHandler + + .weak EXTI1_IRQHandler +EXTI1_IRQHandler: + b EXTI1_IRQHandler + + .weak EXTI2_IRQHandler +EXTI2_IRQHandler: + b EXTI2_IRQHandler + + .weak EXTI3_IRQHandler +EXTI3_IRQHandler: + b EXTI3_IRQHandler + + .weak EXTI4_IRQHandler +EXTI4_IRQHandler: + b EXTI4_IRQHandler + + .weak DMA0_Channel0_IRQHandler +DMA0_Channel0_IRQHandler: + b DMA0_Channel0_IRQHandler + + .weak DMA0_Channel1_IRQHandler +DMA0_Channel1_IRQHandler: + b DMA0_Channel1_IRQHandler + + .weak DMA0_Channel2_IRQHandler +DMA0_Channel2_IRQHandler: + b DMA0_Channel2_IRQHandler + + .weak DMA0_Channel3_IRQHandler +DMA0_Channel3_IRQHandler: + b DMA0_Channel3_IRQHandler + + .weak DMA0_Channel4_IRQHandler +DMA0_Channel4_IRQHandler: + b DMA0_Channel4_IRQHandler + + .weak DMA0_Channel5_IRQHandler +DMA0_Channel5_IRQHandler: + b DMA0_Channel5_IRQHandler + + .weak DMA0_Channel6_IRQHandler +DMA0_Channel6_IRQHandler: + b DMA0_Channel6_IRQHandler + + .weak ADC_IRQHandler +ADC_IRQHandler: + b ADC_IRQHandler + + .weak CAN0_TX_IRQHandler +CAN0_TX_IRQHandler: + b CAN0_TX_IRQHandler + + .weak CAN0_RX0_IRQHandler +CAN0_RX0_IRQHandler: + b CAN0_RX0_IRQHandler + + .weak CAN0_RX1_IRQHandler +CAN0_RX1_IRQHandler: + b CAN0_RX1_IRQHandler + + .weak CAN0_EWMC_IRQHandler +CAN0_EWMC_IRQHandler: + b CAN0_EWMC_IRQHandler + + .weak EXTI5_9_IRQHandler +EXTI5_9_IRQHandler: + b EXTI5_9_IRQHandler + + .weak TIMER0_BRK_TIMER8_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler: + b TIMER0_BRK_TIMER8_IRQHandler + + .weak TIMER0_UP_TIMER9_IRQHandler +TIMER0_UP_TIMER9_IRQHandler: + b TIMER0_UP_TIMER9_IRQHandler + + .weak TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler: + b TIMER0_TRG_CMT_TIMER10_IRQHandler + + .weak TIMER0_Channel_IRQHandler +TIMER0_Channel_IRQHandler: + b TIMER0_Channel_IRQHandler + + .weak TIMER1_IRQHandler +TIMER1_IRQHandler: + b TIMER1_IRQHandler + + .weak TIMER2_IRQHandler +TIMER2_IRQHandler: + b TIMER2_IRQHandler + + .weak TIMER3_IRQHandler +TIMER3_IRQHandler: + b TIMER3_IRQHandler + + .weak I2C0_EV_IRQHandler +I2C0_EV_IRQHandler: + b I2C0_EV_IRQHandler + + .weak I2C0_ER_IRQHandler +I2C0_ER_IRQHandler: + b I2C0_ER_IRQHandler + + .weak I2C1_EV_IRQHandler +I2C1_EV_IRQHandler: + b I2C1_EV_IRQHandler + + .weak I2C1_ER_IRQHandler +I2C1_ER_IRQHandler: + b I2C1_ER_IRQHandler + + .weak SPI0_IRQHandler +SPI0_IRQHandler: + b SPI0_IRQHandler + + .weak SPI1_IRQHandler +SPI1_IRQHandler: + b SPI1_IRQHandler + + .weak USART0_IRQHandler +USART0_IRQHandler: + b USART0_IRQHandler + + .weak USART1_IRQHandler +USART1_IRQHandler: + b USART1_IRQHandler + + .weak USART2_IRQHandler +USART2_IRQHandler: + b USART2_IRQHandler + + .weak EXTI10_15_IRQHandler +EXTI10_15_IRQHandler: + b EXTI10_15_IRQHandler + + .weak RTC_Alarm_IRQHandler +RTC_Alarm_IRQHandler: + b RTC_Alarm_IRQHandler + + .weak USBFS_WKUP_IRQHandler +USBFS_WKUP_IRQHandler: + b USBFS_WKUP_IRQHandler + + .weak TIMER7_BRK_TIMER11_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler: + b TIMER7_BRK_TIMER11_IRQHandler + + .weak TIMER7_UP_TIMER12_IRQHandler +TIMER7_UP_TIMER12_IRQHandler: + b TIMER7_UP_TIMER12_IRQHandler + + .weak TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler: + b TIMER7_TRG_CMT_TIMER13_IRQHandler + + .weak TIMER7_Channel_IRQHandler +TIMER7_Channel_IRQHandler: + b TIMER7_Channel_IRQHandler + + .weak DMA0_Channel7_IRQHandler +DMA0_Channel7_IRQHandler: + b DMA0_Channel7_IRQHandler + + .weak SDIO_IRQHandler +SDIO_IRQHandler: + b SDIO_IRQHandler + + .weak TIMER4_IRQHandler +TIMER4_IRQHandler: + b TIMER4_IRQHandler + + .weak SPI2_IRQHandler +SPI2_IRQHandler: + b SPI2_IRQHandler + + .weak UART3_IRQHandler +UART3_IRQHandler: + b UART3_IRQHandler + + .weak UART4_IRQHandler +UART4_IRQHandler: + b UART4_IRQHandler + + .weak TIMER5_DAC_IRQHandler +TIMER5_DAC_IRQHandler: + b TIMER5_DAC_IRQHandler + + .weak TIMER6_IRQHandler +TIMER6_IRQHandler: + b TIMER6_IRQHandler + + .weak DMA1_Channel0_IRQHandler +DMA1_Channel0_IRQHandler: + b DMA1_Channel0_IRQHandler + + .weak DMA1_Channel1_IRQHandler +DMA1_Channel1_IRQHandler: + b DMA1_Channel1_IRQHandler + + .weak DMA1_Channel2_IRQHandler +DMA1_Channel2_IRQHandler: + b DMA1_Channel2_IRQHandler + + .weak DMA1_Channel3_IRQHandler +DMA1_Channel3_IRQHandler: + b DMA1_Channel3_IRQHandler + + .weak DMA1_Channel4_IRQHandler +DMA1_Channel4_IRQHandler: + b DMA1_Channel4_IRQHandler + + .weak CAN1_TX_IRQHandler +CAN1_TX_IRQHandler: + b CAN1_TX_IRQHandler + + .weak CAN1_RX0_IRQHandler +CAN1_RX0_IRQHandler: + b CAN1_RX0_IRQHandler + + .weak CAN1_RX1_IRQHandler +CAN1_RX1_IRQHandler: + b CAN1_RX1_IRQHandler + + .weak CAN1_EWMC_IRQHandler +CAN1_EWMC_IRQHandler: + b CAN1_EWMC_IRQHandler + + .weak USBFS_IRQHandler +USBFS_IRQHandler: + b USBFS_IRQHandler + + .weak DMA1_Channel5_IRQHandler +DMA1_Channel5_IRQHandler: + b DMA1_Channel5_IRQHandler + + .weak DMA1_Channel6_IRQHandler +DMA1_Channel6_IRQHandler: + b DMA1_Channel6_IRQHandler + + .weak DMA1_Channel7_IRQHandler +DMA1_Channel7_IRQHandler: + b DMA1_Channel7_IRQHandler + + .weak USART5_IRQHandler +USART5_IRQHandler: + b USART5_IRQHandler + + .weak I2C2_EV_IRQHandler +I2C2_EV_IRQHandler: + b I2C2_EV_IRQHandler + + .weak I2C2_ER_IRQHandler +I2C2_ER_IRQHandler: + b I2C2_ER_IRQHandler + + .weak USBHS_EP1_Out_IRQHandler +USBHS_EP1_Out_IRQHandler: + b USBHS_EP1_Out_IRQHandler + + .weak USBHS_EP1_In_IRQHandler +USBHS_EP1_In_IRQHandler: + b USBHS_EP1_In_IRQHandler + + .weak USBHS_WKUP_IRQHandler +USBHS_WKUP_IRQHandler: + b USBHS_WKUP_IRQHandler + + .weak USBHS_IRQHandler +USBHS_IRQHandler: + b USBHS_IRQHandler + + .weak DCI_IRQHandler +DCI_IRQHandler: + b DCI_IRQHandler + + .weak TRNG_IRQHandler +TRNG_IRQHandler: + b TRNG_IRQHandler + + .weak FPU_IRQHandler +FPU_IRQHandler: + b FPU_IRQHandler diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c new file mode 100644 index 0000000..712cf2a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c @@ -0,0 +1,1450 @@ +/*! + \file system_gd32f4xx.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F4xx Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f4xx.h" + +/* system frequency define */ +#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M) +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_16M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_16M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_16M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_240M_PLL_IRC16M (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000) +#define __SYSTEM_CLOCK_240M_PLL_16M_HXTAL (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) + +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + +#define SEL_IRC16M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLLP 0x02U + +extern uint32_t g_pfnVectors; + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_IRC16M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M; +static void system_clock_16m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M; +static void system_clock_120m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL; +static void system_clock_120m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_16M_HXTAL; +static void system_clock_120m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL; +static void system_clock_120m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M; +static void system_clock_168m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL; +static void system_clock_168m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_16M_HXTAL; +static void system_clock_168m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL; +static void system_clock_168m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M; +static void system_clock_200m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL; +static void system_clock_200m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_16M_HXTAL; +static void system_clock_200m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL; +static void system_clock_200m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_IRC16M; +static void system_clock_240m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_8M_HXTAL; +static void system_clock_240m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_16M_HXTAL; +static void system_clock_240m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_25M_HXTAL; +static void system_clock_240m_25m_hxtal(void); + +#endif /* __SYSTEM_CLOCK_IRC16M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ + SCB->VTOR=(uint32_t) &g_pfnVectors; + + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCU clock configuration to the default reset state */ + /* Set IRC16MEN bit */ + RCU_CTL |= RCU_CTL_IRC16MEN; + while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + } + RCU_MODIFY(0x50); + + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* Reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + + /* Reset HSEBYP bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* Reset CFG0 register */ + RCU_CFG0 = 0x00000000U; + + /* wait until IRC16M is selected as system clock */ + while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ + } + + /* Reset PLLCFGR register */ + RCU_PLL = 0x24003010U; + + /* Disable all interrupts */ + RCU_INT = 0x00000000U; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + system_clock_config(); + SystemCoreClockUpdate(); +} +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_IRC16M + system_clock_16m_irc16m(); +#elif defined (__SYSTEM_CLOCK_HXTAL) + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) + system_clock_120m_irc16m(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) + system_clock_120m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) + system_clock_120m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) + system_clock_120m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) + system_clock_168m_irc16m(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) + system_clock_168m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) + system_clock_168m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) + system_clock_168m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) + system_clock_200m_irc16m(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) + system_clock_200m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) + system_clock_200m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) + system_clock_200m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) + system_clock_240m_irc16m(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) + system_clock_240m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) + system_clock_240m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) + system_clock_240m_25m_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC16M */ +} + +#ifdef __SYSTEM_CLOCK_IRC16M +/*! + \brief configure the system clock to 16M by IRC16M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_16m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC16M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; + + /* wait until IRC16M is selected as system clock */ + while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ + } +} + +#elif defined (__SYSTEM_CLOCK_HXTAL) +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) +/*! + \brief configure the system clock to 120M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) +/*! + \brief configure the system clock to 168M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (7U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){ + } + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7 << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(16M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){ + } + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (16U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7 << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) +/*! + \brief configure the system clock to 200M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +/*! + \brief configure the system clock to 240M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (8U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (25U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} +#endif /* __SYSTEM_CLOCK_IRC16M */ +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t sws; + uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; + + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC16M is selected as CK_SYS */ + case SEL_IRC16M: + SystemCoreClock = IRC16M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLLP is selected as CK_SYS */ + case SEL_PLLP: + /* get the value of PLLPSC[5:0] */ + pllpsc = GET_BITS(RCU_PLL, 0U, 5U); + plln = GET_BITS(RCU_PLL, 6U, 14U); + pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_PLL & RCU_PLL_PLLSEL); + if (RCU_PLLSRC_HXTAL == pllsel) { + ck_src = HXTAL_VALUE; + } else { + ck_src = IRC16M_VALUE; + } + SystemCoreClock = ((ck_src / pllpsc) * plln) / pllp; + break; + /* IRC16M is selected as CK_SYS */ + default: + SystemCoreClock = IRC16M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock = SystemCoreClock >> clk_exp; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c new file mode 100644 index 0000000..e301175 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c @@ -0,0 +1,532 @@ +/*! + \file cdc_acm_core.c + \brief CDC ACM driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "cdc_acm_core.h" + +#define USBD_VID 0x2A3CU //Trinamic +#define USBD_PID 0x0700U //Evaluation Device + +/* note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev cdc_dev_desc __ALIGN_END = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +__ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .cmd_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0x00U + }, + + .cdc_header = + { + .header = + { + .bLength = sizeof(usb_desc_header_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x00U, + .bcdCDC = 0x0110U + }, + + .cdc_call_managment = + { + .header = + { + .bLength = sizeof(usb_desc_call_managment_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bmCapabilities = 0x00U, + .bDataInterface = 0x01U + }, + + .cdc_acm = + { + .header = + { + .bLength = sizeof(usb_desc_acm_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bmCapabilities = 0x02U, + }, + + .cdc_union = + { + .header = + { + .bLength = sizeof(usb_desc_union_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x06U, + .bMasterInterface = 0x00U, + .bSlaveInterface0 = 0x01U, + }, + + .cdc_cmd_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = USB_CDC_CMD_PACKET_SIZE, + .bInterval = 0x0AU + }, + + .cdc_data_interface = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = USB_CDC_PROTOCOL_NONE, + .iInterface = 0x00U + }, + + .cdc_out_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_DATA_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + }, + + .cdc_in_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_DATA_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID Descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(23), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'T', 'r', 'i', 'n', 'a', 'm', 'i', 'c', ' ', 'M', 'o', 't', 'i', 'o', 'n', ' ', 'C', 'o', 'n', 't', 'r', 'o', 'l'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(17), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'E', 'v', 'a', 'l', 'u', 'a', 't', 'i', 'o', 'n', ' ', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(7), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'T','M','C','E','V','A','L'} +}; + +/* USB string descriptor set */ +void *const usbd_cdc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc cdc_desc = +{ + .dev_desc = (uint8_t *) &cdc_dev_desc, + .config_desc = (uint8_t *) &cdc_config_desc, + .strings = usbd_cdc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req); +static uint8_t cdc_acm_ctlx_out (usb_dev *udev); +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num); + +/* USB CDC device class callbacks structure */ +usb_class_core cdc_class = +{ + .command = NO_CMD, + .alter_set = 0U, + + .init = cdc_acm_init, + .deinit = cdc_acm_deinit, + .req_proc = cdc_acm_req, + .ctlx_out = cdc_acm_ctlx_out, + .data_in = cdc_acm_in, + .data_out = cdc_acm_out +}; + +/*! + \brief check CDC ACM is ready for data transfer + \param[in] udev: pointer to USB device instance + \param[out] none + \retval 0 if CDC is ready, 5 else +*/ +uint8_t cdc_acm_check_ready(usb_dev *udev) +{ + if (udev->dev.class_data[CDC_COM_INTERFACE] != NULL) { + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) { + return 0U; + } + } + + return 1U; +} + +/*! + \brief send CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_send (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (0U != cdc->receive_length) { + cdc->packet_sent = 0U; + + usbd_ep_send (udev, CDC_DATA_IN_EP, (uint8_t*)(cdc->data), cdc->receive_length); + + cdc->receive_length = 0U; + } +} + +/*! + \brief receive CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_receive (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 0U; + cdc->packet_sent = 0U; + + usbd_ep_recev (udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); +} + +/*! + \brief initialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) +{ + static __ALIGN_BEGIN usb_cdc_handler cdc_handler __ALIGN_END; + + /* initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_in_endpoint)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_out_endpoint)); + + /* initialize the command Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_cmd_endpoint)); + + /* initialize CDC handler structure */ + cdc_handler.packet_receive = 1U; + cdc_handler.packet_sent = 1U; + cdc_handler.receive_length = 0U; + + cdc_handler.line_coding = (acm_line){ + .dwDTERate = 115200U, + .bCharFormat = 0U, + .bParityType = 0U, + .bDataBits = 0x08U + }; + + udev->dev.class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler; + + return USBD_OK; +} + +/*! + \brief deinitialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear (udev, CDC_DATA_IN_EP); + usbd_ep_clear (udev, CDC_DATA_OUT_EP); + + /* deinitialize the command Tx endpoint */ + usbd_ep_clear (udev, CDC_CMD_EP); + + return USBD_OK; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + usb_transc *transc = NULL; + + switch (req->bRequest) { + case SEND_ENCAPSULATED_COMMAND: + /* no operation for this driver */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* no operation for this driver */ + break; + + case SET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case GET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case CLEAR_COMM_FEATURE: + /* no operation for this driver */ + break; + + case SET_LINE_CODING: + transc = &udev->dev.transc_out[0]; + + /* set the value of the current command to be processed */ + udev->dev.class_core->alter_set = req->bRequest; + + /* enable EP0 prepare to receive command data packet */ + transc->remain_len = req->wLength; + transc->xfer_buf = cdc->cmd; + break; + + case GET_LINE_CODING: + transc = &udev->dev.transc_in[0]; + + cdc->cmd[0] = (uint8_t)(cdc->line_coding.dwDTERate); + cdc->cmd[1] = (uint8_t)(cdc->line_coding.dwDTERate >> 8); + cdc->cmd[2] = (uint8_t)(cdc->line_coding.dwDTERate >> 16); + cdc->cmd[3] = (uint8_t)(cdc->line_coding.dwDTERate >> 24); + cdc->cmd[4] = cdc->line_coding.bCharFormat; + cdc->cmd[5] = cdc->line_coding.bParityType; + cdc->cmd[6] = cdc->line_coding.bDataBits; + + transc->xfer_buf = cdc->cmd; + transc->remain_len = 7U; + break; + + case SET_CONTROL_LINE_STATE: + /* no operation for this driver */ + break; + + case SEND_BREAK: + /* no operation for this driver */ + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief command data received on control endpoint + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_ctlx_out (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (udev->dev.class_core->alter_set != NO_CMD) { + /* process the command data */ + cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | + ((uint32_t)cdc->cmd[1] << 8U) | + ((uint32_t)cdc->cmd[2] << 16U) | + ((uint32_t)cdc->cmd[3] << 24U)); + + cdc->line_coding.bCharFormat = cdc->cmd[4]; + cdc->line_coding.bParityType = cdc->cmd[5]; + cdc->line_coding.bDataBits = cdc->cmd[6]; + + udev->dev.class_core->alter_set = NO_CMD; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data in + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) { + usbd_ep_send (udev, ep_num, NULL, 0U); + } else { + cdc->packet_sent = 1U; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data out + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 1U; + cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; + + return USBD_OK; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c new file mode 100644 index 0000000..0382fbe --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c @@ -0,0 +1,374 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/* local function prototypes ('static') */ +static void usb_core_reset (usb_core_regs *usb_regs); + +/*! + \brief configure USB core basic + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + /* configure USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = (uint8_t)USB_SPEED_FULL; + + usb_basic->core_enum = (uint8_t)usb_core; + + switch (usb_core) { + case USB_CORE_ENUM_HS: + usb_basic->base_reg = (uint32_t)USBHS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBHS_MAX_EP_COUNT; + +#ifdef USB_ULPI_PHY_ENABLED + usb_basic->phy_itf = USB_ULPI_PHY; +#else + usb_basic->phy_itf = USB_EMBEDDED_PHY; +#endif /* USB_ULPI_PHY_ENABLED */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + usb_basic->transfer_mode = USB_USE_DMA; +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ + +#ifdef USB_HS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBHS_SOF_OUTPUT; + usb_basic->low_power = USBHS_LOW_POWER; +#endif /* USB_HS_CORE */ + break; + + case USB_CORE_ENUM_FS: + usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + +#ifdef USB_FS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBFS_SOF_OUTPUT; + usb_basic->low_power = USBFS_LOW_POWER; +#endif /* USB_FS_CORE */ + break; + + default: + return USB_FAIL; + } + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (uint8_t i = 0U; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + if (USB_ULPI_PHY == usb_basic.phy_itf) { + usb_regs->gr->GCCFG &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + /* initialize the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif /* USBHS_EXTERNAL_VBUS_ENABLED */ + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable VBUS sensing */ + usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + usb_regs->gr->GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + usb_mdelay(20U); + } + + if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0U) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0U) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks*/ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks */ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief set endpoint or channel TX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo: TX FIFO number + \param[in] size: assigned TX FIFO size + \param[out] none + \retval none +*/ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) +{ + uint32_t tx_offset; + + tx_offset = usb_regs->gr->GRFLEN; + + if(0U == fifo) { + usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; + + for (uint8_t i = 0U; i < (fifo - 1U); i++) { + tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16); + } + + /* multiply Tx_Size by 2 to get higher performance */ + usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } +} + +/*! + \brief set USB current mode + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode) +{ + usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + + if (DEVICE_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FDM; + } else if (HOST_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FHM; + } else { + /* OTG mode and other mode can not be here! */ + } +} + +/*! + \brief configure USB core to soft reset + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) { + /* no operation */ + } + + /* wait for additional 3 PHY clocks */ + usb_udelay(3U); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c new file mode 100644 index 0000000..2998f80 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c @@ -0,0 +1,666 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#endif /* USBFS_CORE */ + +#ifdef USB_HS_CORE + +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_HS_SIZE, + (uint16_t)TX1_FIFO_HS_SIZE, + (uint16_t)TX2_FIFO_HS_SIZE, + (uint16_t)TX3_FIFO_HS_SIZE, + (uint16_t)TX4_FIFO_HS_SIZE, + (uint16_t)TX5_FIFO_HS_SIZE +}; + +#endif /* USBHS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint8_t i; + + /* restart the PHY clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* configure periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); + + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ + for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + if (udev->bp.core_enum == USB_CORE_ENUM_HS) { + if (udev->bp.phy_itf == USB_ULPI_PHY) { + udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; + } else {/* set High speed PHY in Full speed mode */ + udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; + } + + /* Set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_HS_SIZE); + + /* Set endpoint 0 to 6's TX FIFO length and RAM address */ + for (i = 0; i < USBHS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBHS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + (void)usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush entire Rx FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0U; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN; + + (void)usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + return USB_OK; +} + +/*! + \brief active the USB endpoint0 transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB endpoint0 transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + if (ep_num) { + /* not endpoint 0 */ + return USB_FAIL; + } + + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[0]->DIEPCTL; + } else { + reg_addr = &udev->regs.er_out[0]->DOEPCTL; + } + + /* endpoint 0 is activated after USB clock is enabled */ + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint 0 maximum packet length */ + *reg_addr |= EP0_MAXLEN[enum_speed]; + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + + return USB_OK; +} + +/*! + \brief active the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + uint32_t epinten = 0U; + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1U << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1U << (16U + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[enum_speed]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN |= epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + } + + return USB_OK; +} + +/*! + \brief deactivate the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1U << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1U << (ep_num + 16U); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN &= ~epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + } + + return USB_OK; +} + +/*! + \brief configure USB transaction to start IN transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB IN transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1U << 19U; + } else { + eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) { + epctl |= DEPCTL_SEVNFRM; + } else { + epctl |= DEPCTL_SODDFRM; + } + } + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0U) { + udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; + } + } else { + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len); + } + } + + return status; +} + +/*! + \brief configure USB transaction to start OUT transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len; + + eplen |= packet_count << 19U; + eplen |= packet_count * transc->max_len; + +#ifdef INT_HIGH_BW + if (transc->ep_type == (uint8_t)USB_EPTYPE_INTR) { + eplen |= DIEPLEN_MCNT & (3U << 29U); + } +#endif /* INT_HIGH_BW */ + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt value +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask, commonintmask; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief active remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5U); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* ungate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief USB device suspend + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); + } +} + +/*! + \brief stop the device and clean up FIFOs + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1U; + + /* clear all interrupt flag and enable bits */ + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + (void)usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c new file mode 100644 index 0000000..309f712 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c @@ -0,0 +1,590 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +/* local function prototypes ('static') */ +static uint32_t usbd_int_epout (usb_core_driver *udev); +static uint32_t usbd_int_epin (usb_core_driver *udev); +static uint32_t usbd_int_rxfifo (usb_core_driver *udev); +static uint32_t usbd_int_reset (usb_core_driver *udev); +static uint32_t usbd_int_enumfinish (usb_core_driver *udev); +static uint32_t usbd_int_suspend (usb_core_driver *udev); +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_isr (usb_core_driver *udev) +{ + if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if (!intr) { + return; + } + + /* OUT endpoints interrupts */ + if (intr & GINTF_OEPIF) { + (void)usbd_int_epout (udev); + } + + /* IN endpoints interrupts */ + if (intr & GINTF_IEPIF) { + (void)usbd_int_epin (udev); + } + + /* suspend interrupt */ + if (intr & GINTF_SP) { + (void)usbd_int_suspend (udev); + } + + /* wakeup interrupt */ + if (intr & GINTF_WKUPIF) { + /* inform upper layer by the resume event */ + udev->dev.cur_status = USBD_CONFIGURED; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* start of frame interrupt */ + if (intr & GINTF_SOF) { + if (udev->dev.class_core->SOF) { + (void)udev->dev.class_core->SOF(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if (intr & GINTF_RXFNEIF) { + (void)usbd_int_rxfifo (udev); + } + + /* USB reset interrupt */ + if (intr & GINTF_RST) { + (void)usbd_int_reset (udev); + } + + /* enumeration has been done interrupt */ + if (intr & GINTF_ENUMFIF) { + (void)usbd_int_enumfinish (udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if (intr & GINTF_ISOINCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_in) { + (void)udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if (intr & GINTF_ISOONCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_out) { + (void)udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if (intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif /* VBUS_SENSING_ENABLED */ + } +} + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + +/*! + \brief USB dedicated OUT endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev) +{ + uint32_t oepintr = 0U; + uint32_t oeplen = 0U; + + oepintr = udev->regs.er_out[1]->DOEPINTF; + oepintr &= udev->regs.dr->DOEP1INTEN; + + /* transfer complete */ + if(oepintr & DOEPINTF_TF){ + /* clear the bit in DOEPINTn for this interrupt */ + udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; + + if(USB_USE_DMA == udev->bp.transfer_mode){ + oeplen = udev->regs.er_out[1]->DOEPLEN; + + /* to do : handle more than one single max packet size packet */ + udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].max_len - \ + (oeplen & DEPLEN_TLEN); + } + + /* rx complete */ + usbd_out_transc (udev, 1U); + } + + return 1U; +} + +/*! + \brief USB dedicated IN endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev) +{ + uint32_t inten, intr, emptyen; + + inten = udev->regs.dr->DIEP1INTEN; + emptyen = udev->regs.dr->DIEPFEINTEN; + + inten |= ((emptyen >> 1 ) & 0x1) << 7; + + intr = udev->regs.er_in[1]->DIEPINTF & inten; + + if(intr & DIEPINTF_TF){ + udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF; + + /* TX complete */ + usbd_in_transc (udev, 1); + } + + if(intr & DIEPINTF_TXFE){ + usbd_emptytxfifo_write(udev, 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE; + } + + return 1; +} + +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x01U) { + __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num); + + /* transfer complete interrupt */ + if (oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ + (eplen & DEPLEN_TLEN); + } + + /* inform upper layer: data ready */ + (void)usbd_out_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + /* setup phase finished interrupt (control endpoints) */ + if (oepintr & DOEPINTF_STPF) { + /* inform the upper layer that a setup packet is available */ + (void)usbd_setup_transc (udev); + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + } + } + } + + return 1U; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num); + + if (iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmission is completed */ + (void)usbd_in_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + if (iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write (udev, (uint32_t)ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1U; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo (usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0U; + uint32_t bcount = 0U; + + __IO uint32_t devrxstat = 0U; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM); + + transc = &udev->dev.transc_out[ep_num]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; + data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + #ifndef USE_450Z_EVAL + /* ensure no-DMA mode can work */ + if (0U == (udev->regs.er_out[ep_num]->DOEPLEN & DEPLEN_PCNT)) { + uint32_t devepctl = udev->regs.er_out[ep_num]->DOEPCTL; + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + udev->regs.er_out[ep_num]->DOEPCTL = devepctl; + } + #endif /* USE_450Z_EVAL */ +#endif /* USE_USB_HS && USE_ULPI_PHY */ + + switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if (bcount > 0U) { + (void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + (void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount); + + transc->xfer_count += bcount; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset (usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + (void)usb_txfifo_flush (&udev->regs, 0U); + + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16U); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DIEP1INTEN = DIEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout (udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1U + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_in[0]); + + /* upon reset call user call back */ + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + + return 1U; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish (usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) { + udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09U << 10U; + } else { + udev->bp.core_speed = (uint8_t)USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05U << 10U; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1U; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend (usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the OTG clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num) +{ + uint32_t len; + uint32_t word_count; + + usb_transc *transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if (len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3U) / 4U; + + while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if (len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3U) / 4U; + + /* write the FIFO */ + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if (transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num); + } + } + + return 1U; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c new file mode 100644 index 0000000..d904084 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c @@ -0,0 +1,324 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_enum.h" +#include "drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = (uint32_t)USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = (uint32_t)USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = (uint32_t)USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = (uint32_t)USB_EPTYPE_ISOC +}; + +/*! + \brief initializes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: USB core type + \param[in] desc: pointer to USB descriptor + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core) +{ + udev->dev.desc = desc; + + /* class callbacks */ + udev->dev.class_core = class_core; + +#if USB_USE_UNIQUE_SERIAL_NUMBER + /* create serial string */ + serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]); +#endif + + /* configure USB capabilities */ + (void)usb_basic_init (&udev->bp, &udev->regs, core); + + usb_globalint_disable(&udev->regs); + + /* initializes the USB core*/ + (void)usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + +#ifndef USE_OTG_MODE + usb_curmode_set(&udev->regs, DEVICE_MODE); +#endif /* USE_OTG_MODE */ + + /* initializes device mode */ + (void)usb_devcore_init (udev); + + usb_globalint_enable(&udev->regs); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint16_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = (uint8_t)ep_type[ep_desc->bmAttributes & (uint8_t)USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + (void)usb_transc_active (udev, transc); + + return 0U; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactivate USB endpoint function */ + (void)usb_transc_deactivate (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_outxfer (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_inxfer (udev, transc); + + return 0U; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1U; + + (void)usb_transc_stall (udev, transc); + + return (0U); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0U; + + (void)usb_transc_clrstall (udev, transc); + + return (0U); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + (void)usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + (void)usb_rxfifo_flush (&udev->regs); + } + + return (0U); +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c new file mode 100644 index 0000000..95718bb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c @@ -0,0 +1,820 @@ +/*! + \file usbd_enum.c + \brief USB enumeration function + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +#ifdef WINUSB_EXEMPT_DRIVER + +extern usbd_status usbd_OEM_req(usb_dev *udev, usb_req *req); + +#endif /* WINUSB_EXEMPT_DRIVER */ + +/* local function prototypes ('static') */ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#endif +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); + +static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = +{ + [USB_GET_STATUS] = _usb_std_getstatus, + [USB_CLEAR_FEATURE] = _usb_std_clearfeature, + [USB_RESERVED2] = _usb_std_reserved, + [USB_SET_FEATURE] = _usb_std_setfeature, + [USB_RESERVED4] = _usb_std_reserved, + [USB_SET_ADDRESS] = _usb_std_setaddress, + [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, + [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, + [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, + [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, + [USB_GET_INTERFACE] = _usb_std_getinterface, + [USB_SET_INTERFACE] = _usb_std_setinterface, + [USB_SYNCH_FRAME] = _usb_std_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { + [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, + [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, + [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get, +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + [(uint8_t)USB_DESCTYPE_DEV_QUALIFIER - 3U] = _usb_qualifier_desc_get, + [(uint8_t)USB_DESCTYPE_OTHER_SPD_CONFIG - 3U] = _usb_other_speed_config_desc_get, +#endif +}; + +/*! + \brief handle USB standard device request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req) +{ + return (*_std_dev_req[req->bRequest])(udev, req); +} + +/*! + \brief handle USB device class request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req) +{ + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + return (usb_reqsta)udev->dev.class_core->req_proc(udev, req); + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB vendor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* added by user... */ +#ifdef WINUSB_EXEMPT_DRIVER + usbd_OEM_req(udev, req); +#endif + + return REQ_SUPP; +} + +/*! + \brief handle USB enumeration error + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + (void)usbd_ep_stall (udev, 0x80U); + (void)usbd_ep_stall (udev, 0x00U); + + usb_ctlep_startout(udev); +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] value: hex 32bits value + \param[in] pbuf: buffer pointer to store unicode char + \param[in] len: value length + \param[out] none + \retval none +*/ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len) +{ + uint8_t index; + + for (index = 0U; index < len; index++) { + if ((value >> 28U) < 0x0AU) { + pbuf[2U * index] = (uint8_t)((value >> 28U) + '0'); + } else { + pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); + } + + value = value << 4U; + + pbuf[2U * index + 1U] = 0U; + } +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] unicode_str: pointer to unicode string + \param[out] none + \retval none +*/ +void serial_string_get (uint16_t *unicode_str) +{ + if ((unicode_str[0] & 0x00FFU) != 6U) { + uint32_t DeviceSerial0, DeviceSerial1, DeviceSerial2; + + DeviceSerial0 = *(uint32_t*)DEVICE_ID1; + DeviceSerial1 = *(uint32_t*)DEVICE_ID2; + DeviceSerial2 = *(uint32_t*)DEVICE_ID3; + + DeviceSerial0 += DeviceSerial2; + + if (0U != DeviceSerial0) { + int_to_unicode(DeviceSerial0, (uint8_t*)&(unicode_str[1]), 8U); + int_to_unicode(DeviceSerial1, (uint8_t*)&(unicode_str[9]), 4U); + } + } else { + uint32_t device_serial = *(uint32_t*)DEVICE_ID; + + if(0U != device_serial) { + unicode_str[1] = (uint16_t)(device_serial & 0x0000FFFFU); + unicode_str[2] = (uint16_t)((device_serial & 0xFFFF0000U) >> 16U); + + } + } +} + +/*! + \brief no operation, just for reserved + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no operation... */ + + return REQ_NOTSUPP; +} + +/*! + \brief get the device descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->dev_desc[0]; + + return udev->dev.desc->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->config_desc[2] | (udev->dev.desc->config_desc[3]<< 8U); + + return udev->dev.desc->config_desc; +} + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->other_speed_config_desc[2]; + + return udev->dev.desc->other_speed_config_desc; +} + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->qualifier_desc[0]; + + return udev->dev.desc->qualifier_desc; +} + +#endif /* USE_USB_HS && USE_ULPI_PHY */ + +/*! + \brief get the BOS descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->bos_desc[2]; + + return udev->dev.desc->bos_desc; +} + +/*! + \brief get string descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] len: pointer to string length + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + uint8_t *desc = udev->dev.desc->strings[index]; + + *len = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req) +{ + uint8_t recp = BYTE_LOW(req->wIndex); + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + static uint8_t status[2] = {0}; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + if (udev->dev.pm.power_mode) { + status[0] = USB_STATUS_SELF_POWERED; + } else { + status[0] = 0U; + } + + if (udev->dev.pm.dev_remote_wakeup) { + status[0] |= USB_STATUS_REMOTE_WAKEUP; + } else { + status[0] = 0U; + } + + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + if (((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_EP: + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (0x80U == (recp & 0x80U)) { + status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; + } else { + status[0] = udev->dev.transc_out[recp].ep_stall; + } + + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = status; + transc->remain_len = 2U; + } + + return req_status; +} + +/*! + \brief handle USB Clear_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + /* clear device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 0U; + + return REQ_SUPP; + } + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* clear endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall_clear (udev, ep); + + (void)udev->dev.class_core->req_proc (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch (req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + /* set device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 1U; + } + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* set endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall (udev, ep); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Address request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (udev->dev.cur_status != (uint8_t)USBD_CONFIGURED) { + usbd_addr_set (udev, udev->dev.dev_addr); + + if (udev->dev.dev_addr) { + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else { + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + } + + return REQ_SUPP; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) +{ + uint8_t desc_type = 0U; + uint8_t desc_index = 0U; + + usb_reqsta status = REQ_NOTSUPP; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* get device standard descriptor */ + switch (req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + desc_type = BYTE_HIGH(req->wValue); + desc_index = BYTE_LOW(req->wValue); + + switch (desc_type) { + case USB_DESCTYPE_DEV: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + + if (64U == req->wLength) { + transc->remain_len = 8U; + } + break; + + case USB_DESCTYPE_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_STR: + if (desc_index < (uint8_t)STR_IDX_MAX) { + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + } + break; + + case USB_DESCTYPE_ITF: + case USB_DESCTYPE_EP: + break; + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + case USB_DESCTYPE_DEV_QUALIFIER: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_OTHER_SPD_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; +#endif + + case USB_DESCTYPE_ITF_POWER: + break; + + case USB_DESCTYPE_BOS: + transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + default: + break; + } + break; + + case USB_RECPTYPE_ITF: + /* get device class special descriptor */ + status = (usb_reqsta)(udev->dev.class_core->req_proc(udev, req)); + break; + + case USB_RECPTYPE_EP: + break; + + default: + break; + } + + if ((0U != transc->remain_len) && (0U != req->wLength)) { + if (transc->remain_len < req->wLength) { + if ((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { + udev->dev.control.ctl_zlp = 1U; + } + } else { + transc->remain_len = req->wLength; + } + + status = REQ_SUPP; + } + + return status; +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB Get_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (USB_DEFAULT_CONFIG == udev->dev.config) { + req_status = REQ_SUPP; + } + break; + + case USBD_CONFIGURED: + if (udev->dev.config != USB_DEFAULT_CONFIG) { + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + } + + return req_status; +} + +/*! + \brief handle USB Set_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req) +{ + static uint8_t config; + usb_reqsta status = REQ_NOTSUPP; + + config = (uint8_t)(req->wValue); + + if (config <= USBD_CFG_MAX_NUM) { + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (config){ + (void)udev->dev.class_core->init(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_CONFIGURED; + } + + status = REQ_SUPP; + break; + + case USBD_CONFIGURED: + if (USB_DEFAULT_CONFIG == config) { + (void)udev->dev.class_core->deinit(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else if (config != udev->dev.config) { + /* clear old configuration */ + (void)udev->dev.class_core->deinit(udev, config); + + /* set new configuration */ + udev->dev.config = config; + + (void)udev->dev.class_core->init(udev, config); + } else { + /* no operation */ + } + + status = REQ_SUPP; + break; + + case USBD_DEFAULT: + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief handle USB Get_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + usb_transc *transc = &udev->dev.transc_in[0]; + + transc->xfer_buf = &(udev->dev.class_core->alter_set); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != udev->dev.class_core->set_intf) { + (void)udev->dev.class_core->set_intf (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB SynchFrame request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle */ + return REQ_SUPP; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c new file mode 100644 index 0000000..c8e7adb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c @@ -0,0 +1,266 @@ +/*! + \file usbd_transc.c + \brief USB transaction core functions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_transc.h" + +/*! + \brief USB send data in the control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_send (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + (void)usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_IN; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_IN; + } + + return USBD_OK; +} + +/*! + \brief USB receive data in control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_recev (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + + (void)usbd_ep_recev (udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_OUT; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_OUT; + } + + return USBD_OK; +} + +/*! + \brief USB send control transaction status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_send (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_IN; + + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB control receive status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_OUT; + + (void)usbd_ep_recev (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB setup stage processing + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_setup_transc (usb_core_driver *udev) +{ + usb_reqsta reqstat = REQ_NOTSUPP; + + usb_req req = udev->dev.control.req; + + switch (req.bmRequestType & USB_REQTYPE_MASK) { + /* standard device request */ + case USB_REQTYPE_STRD: + reqstat = usbd_standard_request (udev, &req); + break; + + /* device class request */ + case USB_REQTYPE_CLASS: + reqstat = usbd_class_request (udev, &req); + break; + + /* vendor defined request */ + case USB_REQTYPE_VENDOR: + reqstat = usbd_vendor_request (udev, &req); + break; + + default: + break; + } + + if (REQ_SUPP == reqstat) { + if (0U == req.wLength) { + (void)usbd_ctl_status_send (udev); + } else { + if (req.bmRequestType & 0x80U) { + (void)usbd_ctl_send (udev); + } else { + (void)usbd_ctl_recev (udev); + } + } + } else { + usbd_enum_error (udev, &req); + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_out[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_OUT: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_recev (udev); + break; + + case USB_CTL_LAST_DATA_OUT: + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_out != NULL) { + (void)udev->dev.class_core->ctlx_out (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_send (udev); + break; + + default: + break; + } + } else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)) { + (void)udev->dev.class_core->data_out (udev, ep_num); + } else { + /* no operation */ + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_IN: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_send (udev); + break; + + case USB_CTL_LAST_DATA_IN: + /* last packet is MPS multiple, so send ZLP packet */ + if (udev->dev.control.ctl_zlp) { + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + udev->dev.control.ctl_zlp = 0U; + } else { + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_in != NULL) { + (void)udev->dev.class_core->ctlx_in (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_recev (udev); + } + break; + + default: + break; + } + } else { + if ((udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { + (void)udev->dev.class_core->data_in (udev, ep_num); + } + } + + return (uint8_t)USBD_OK; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h new file mode 100644 index 0000000..de7218d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h @@ -0,0 +1,9 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef LandungsbrueckeV3 + #define LandungsbrueckeV3 +#endif diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c new file mode 100644 index 0000000..aadc75e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include +#include "hal/HAL.h" +#include "hal/ADCs.h" + +#define ADC1_DR_ADDRESS ((uint32_t)0x4001204C) + +static void init(void); +static void deInit(void); + +ADCTypeDef ADCs = +{ + .AIN0 = &ADCValue[0], + .AIN1 = &ADCValue[1], + .AIN2 = &ADCValue[2], + .DIO4 = &ADCValue[3], + .DIO5 = &ADCValue[4], + .VM = &ADCValue[5], + .AIN_EXT = &ADCValue[6], + .init = init, + .deInit = deInit, +}; + +void init(void) +{ + adc_deinit(); + + rcu_periph_clock_enable(RCU_DMA1); + rcu_periph_clock_enable(RCU_ADC0); + + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->ADC_VM); + + dma_deinit(DMA1, DMA_CH0); + + dma_multi_data_parameter_struct dma_init_struct; + dma_multi_data_para_struct_init(&dma_init_struct); + dma_init_struct.periph_addr = (uint32_t) (ADC0 + 0x4CU); + dma_init_struct.periph_width = DMA_PERIPH_WIDTH_16BIT; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory0_addr = (uint32_t)&ADCValue[0]; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_burst_width = DMA_MEMORY_BURST_SINGLE; + dma_init_struct.periph_burst_width = DMA_PERIPH_BURST_SINGLE; + dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_ENABLE; + dma_init_struct.direction = DMA_PERIPH_TO_MEMORY; + dma_init_struct.number = N_O_ADC_CHANNELS; + dma_init_struct.critical_value = DMA_FIFO_2_WORD; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_multi_data_mode_init(DMA1, DMA_CH0, &dma_init_struct); + + dma_channel_enable(DMA1, DMA_CH0); + + adc_clock_config(ADC_ADCCK_PCLK2_DIV2); + adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT); + adc_sync_delay_config(ADC_SYNC_DELAY_5CYCLE); + adc_resolution_config(ADC0, ADC_RESOLUTION_12B); + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE); + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(ADC0, ADC_ROUTINE_CHANNEL, N_O_ADC_CHANNELS); + adc_dma_mode_enable(ADC0); + + adc_routine_channel_config(ADC0, 0, ADC_CHANNEL_14, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 1, ADC_CHANNEL_15, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 2, ADC_CHANNEL_8, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 3, ADC_CHANNEL_0, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 4, ADC_CHANNEL_1, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 5, ADC_CHANNEL_3, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 6, ADC_CHANNEL_2, ADC_SAMPLETIME_15); + + adc_dma_request_after_last_enable(ADC0); + + adc_enable(ADC0); + + adc_calibration_enable(ADC0); + + adc_software_trigger_enable(ADC0, ADC_ROUTINE_CHANNEL); +} + +static void deInit(void) +{ + adc_deinit(); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c new file mode 100644 index 0000000..ae93397 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c @@ -0,0 +1,101 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/derivative.h" +#include "hal/HAL.h" + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +static void init(void); +static void reset(uint8_t ResetPeripherals); +static void NVIC_DeInit(void); + +uint8_t hwid = 0; + +static const IOsFunctionsTypeDef IOFunctions = +{ + .config = &IOs, + .pins = &IOMap, +}; + +const HALTypeDef HAL = +{ + .init = init, + .reset = reset, + .NVIC_DeInit = NVIC_DeInit, + .SPI = &SPI, + .USB = &USB, + .LEDs = &LEDs, + .ADCs = &ADCs, + .IOs = &IOFunctions, + .RS232 = &RS232, + .WLAN = &WLAN, + .Timer = &Timer, + .UART = &UART +}; + +static void init(void) +{ + nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0); + __enable_irq(); + + systick_init(); + wait(100); + + IOs.init(); + IOMap.init(); + USB.init(); + SPI.init(); + RS232.init(); + LEDs.init(); + ADCs.init(); + WLAN.init(); +} + +static void __attribute((noreturn)) reset(uint8_t ResetPeripherals) +{ + // Disable interrupts + __disable_irq(); + + if(ResetPeripherals) + SCB->AIRCR = AIRCR_VECTKEY_MASK | SCB_AIRCR_SYSRESETREQ_Msk; + else + SCB->AIRCR = AIRCR_VECTKEY_MASK | SCB_AIRCR_VECTRESET_Msk; + + // SYSRESETREQ does not happen instantly since peripheral reset timing is not specified. + // Trap execution here so nothing else happens until the reset completes. + while(1); +} + +static void NVIC_DeInit(void) +{ + uint32_t index; + + for(index=0; index<8; index++) + { + NVIC->ICER[index] = 0xFFFFFFFF; + NVIC->ICPR[index] = 0xFFFFFFFF; + } + + for(index = 0; index < 240; index++) + { + NVIC->IP[index] = 0x00000000; + } +} + +void _exit(int32_t i) // function has the attribute noreturn per default +{ + UNUSED(i); + while(1) {}; +} + +void _kill(void) +{ +} + +void _getpid(void) +{ +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c new file mode 100644 index 0000000..4de6cbd --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c @@ -0,0 +1,1208 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/IOMap.h" +#include "hal/HAL.h" + +static void init(); + +static IOPinTypeDef *_pins[] = +{ + &IOMap.ID_CLK, // 0 + &IOMap.ID_CH0, // 1 + &IOMap.ID_CH1, // 2 + &IOMap.DIO0, // 3 + &IOMap.DIO1, // 4 + &IOMap.DIO2, // 5 + &IOMap.DIO3, // 6 + &IOMap.DIO4, // 7 + &IOMap.DIO5, // 8 + &IOMap.DIO6, // 9 + &IOMap.DIO7, // 10 + &IOMap.DIO8, // 11 + &IOMap.DIO9, // 12 + &IOMap.DIO10, // 13 + &IOMap.DIO10_PWM_WL, // 14 + &IOMap.DIO10_UART_TX, // 15 + &IOMap.DIO11, // 16 + &IOMap.DIO11_PWM_WH, // 17 + &IOMap.DIO11_UART_RX, // 18 + &IOMap.SW_UART_PWM, // 19 + &IOMap.CLK16, // 20 + &IOMap.SPI2_CSN0, // 21 + &IOMap.SPI2_CSN1, // 22 + &IOMap.SPI2_CSN2, // 23 + &IOMap.SPI2_SCK, // 24 + &IOMap.SPI2_SDO, // 25 + &IOMap.SPI2_SDI, // 26 + &IOMap.SPI1_CSN, // 27 + &IOMap.SPI1_SCK, // 28 + &IOMap.SPI1_SDI, // 29 + &IOMap.SPI1_SDO, // 30 + &IOMap.DIO12, // 31 + &IOMap.DIO13, // 32 + &IOMap.DIO14, // 33 + &IOMap.DIO15, // 34 + &IOMap.DIO16, // 35 + &IOMap.DIO17, // 36 + &IOMap.DIO18, // 37 + &IOMap.DIO19, // 38 + &IOMap.RS232_TX, // 39 + &IOMap.RS232_RX, // 40 + &IOMap.USB_V_BUS, // 41 + &IOMap.USB_V_DM, // 42 + &IOMap.USB_V_DP, // 43 + &IOMap.LED_STAT, // 44 + &IOMap.LED_ERROR, // 45 + &IOMap.EXT0, // 46 + &IOMap.EXT1, // 47 + &IOMap.EXT2, // 48 + &IOMap.EXT3, // 49 + &IOMap.EXT4, // 50 + &IOMap.EEPROM_SCK, // 51 + &IOMap.EEPROM_SI, // 52 + &IOMap.EEPROM_SO, // 53 + &IOMap.EEPROM_NCS, // 54 + &IOMap.ADC_VM, // 56 + &IOMap.AIN0, // 57 + &IOMap.AIN1, // 58 + &IOMap.AIN2, // 59 + &IOMap.WIFI_EN, // 60 + &IOMap.WIFI_RST, // 61 + &IOMap.WIFI_TX, // 62 + &IOMap.WIFI_RX, // 63 + &IOMap.BUTTON, // 64 + &IOMap.DUMMY, // 65 +}; +IOPinMapTypeDef IOMap = +{ + .init = init, + .pins = &_pins[0], + .ID_CLK = // IOPinTypeDef ID_CLK + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ID_CH0 = // IOPinTypeDef ID_CH0 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ID_CH1 = // IOPinTypeDef ID_CH1 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO0 = // IOPinTypeDef DIO0 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 2, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO1 = // IOPinTypeDef DIO1 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO2 = // IOPinTypeDef + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO3 = // IOPinTypeDef DIO3 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO4 = // IOPinTypeDef DIO4 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO5 = // IOPinTypeDef DIO5 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO6 = // IOPinTypeDef DIO6 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO7 = // IOPinTypeDef DIO7 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO8 = // IOPinTypeDef DIO8 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO9 = // IOPinTypeDef DIO9 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO10 = // IOPinTypeDef DIO10 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO10_PWM_WL = // IOPinTypeDef DIO10_PWM_WL + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO10_UART_TX = // IOPinTypeDef DIO10_UART_TX + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO11 = // IOPinTypeDef DIO11 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO11_PWM_WH = // IOPinTypeDef DIO11_PWM_WH + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_13, // uint32_t pinBitWeight + .bit = 13, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO11_UART_RX = // IOPinTypeDef DIO11_UART_RX + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .SW_UART_PWM = // IOPinTypeDef SW_UART_PWM + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 2, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .CLK16 = // IOPinTypeDef CLK16 + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN0 = // IOPinTypeDef SPI2_CSN0 + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN1 = // IOPinTypeDef SPI2_CSN1 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_14, // uint32_t pinBitWeight + .bit = 14, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN2 = // IOPinTypeDef SPI2_CSN2 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SCK = // IOPinTypeDef SPI2_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SDO = // IOPinTypeDef SPI2_SDO + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SDI = // IOPinTypeDef SPI2_SDI + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_CSN = // IOPinTypeDef SPI1_CSN + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SCK = // IOPinTypeDef SPI1_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_13, // uint32_t pinBitWeight + .bit = 13, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SDI = // IOPinTypeDef SPI1_SDI + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SDO = // IOPinTypeDef SPI1_SDO + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_14, // uint32_t pinBitWeight + .bit = 14, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO12 = // IOPinTypeDef DIO12 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO13 = // IOPinTypeDef DIO13 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO14 = // IOPinTypeDef DIO14 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO15 = // IOPinTypeDef DIO15 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO16 = // IOPinTypeDef DIO016 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO17 = // IOPinTypeDef DIO017 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO18 = // IOPinTypeDef DIO18 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO19 = // IOPinTypeDef DIO19 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .RS232_TX = // IOPinTypeDef RS232_TX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .RS232_RX = // IOPinTypeDef RS232_RX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_BUS = // IOPinTypeDef USB_V_BUS + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_DM = // IOPinTypeDef USB_V_DM + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_DP = // IOPinTypeDef USB_V_DP + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .LED_STAT = // IOPinTypeDef LED_STAT + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .LED_ERROR = // IOPinTypeDef LED_ERROR + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT0 = // IOPinTypeDef EXT0 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT1 = // IOPinTypeDef EXT1 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT2 = // IOPinTypeDef EXT2 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT3 = // IOPinTypeDef EXT3 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT4 = // IOPinTypeDef EXT4 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SCK = // IOPinTypeDef EEPROM_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SI = // IOPinTypeDef EEPROM_SI + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SO = // IOPinTypeDef EEPROM_SO + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_NCS = // IOPinTypeDef EEPROM_NCS + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ADC_VM = // IOPinTypeDef ADC_VM + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN0 = // IOPinTypeDef AIN0 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN1 = // IOPinTypeDef AIN1 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN2 = // IOPinTypeDef AIN2 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN_EXT = // IOPinTypeDef AIN_EXT + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_EN = // IOPinTypeDef WIFI_EN + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_RST = // IOPinTypeDef WIFI_RST + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_TX = // IOPinTypeDef WIFI_TX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_RX = // IOPinTypeDef WIFI_RX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .BUTTON = // IOPinTypeDef BUTTON + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd - There is an external pull-down connected. + } + }, + + .DUMMY = // IOPinTypeDef + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // invalid + .bit = -1, // invalid + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + } +}; + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CLK); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO0); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO3); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO4); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO5); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO6); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO7); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO8); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO9); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_PWM_WL); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_UART_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_PWM_WH); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_UART_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->SW_UART_PWM); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO12); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO13); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO14); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO15); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO16); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO19); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_BUS); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DM); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DP); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT0); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT1); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT2); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT3); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT4); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->reset(&HAL.IOs->pins->ADC_VM); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN_EXT); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_EN); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_RST); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->CLK16); + gpio_af_set(HAL.IOs->pins->CLK16.port, GPIO_AF_0, HAL.IOs->pins->CLK16.bitWeight); + // By default DIO10 and DIO11 are connected to DIO10_PWM_WL and DIO11_PWM_WH respectively. + *HAL.IOs->pins->SW_UART_PWM.setBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c new file mode 100644 index 0000000..a913e24 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c @@ -0,0 +1,172 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/IOs.h" + + +static void init(); +static void setPinConfiguration(IOPinTypeDef *pin); +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef*to); +static void resetPinConfiguration(IOPinTypeDef *pin); +static void setPin2Output(IOPinTypeDef *pin); +static void setPin2Input(IOPinTypeDef *pin); +static void setPinHigh(IOPinTypeDef *pin); +static void setPinLow(IOPinTypeDef *pin); +static void setPinState(IOPinTypeDef *pin, IO_States state); +static IO_States getPinState(IOPinTypeDef *pin); +static unsigned char isPinHigh(IOPinTypeDef *pin); + +IOsTypeDef IOs = +{ + .init = init, + .set = setPinConfiguration, + .reset = resetPinConfiguration, + .copy = copyPinConfiguration, + .toOutput = setPin2Output, + .toInput = setPin2Input, + .setHigh = setPinHigh, + .setLow = setPinLow, + .setToState = setPinState, + .getState = getPinState, + .isHigh = isPinHigh, + .HIGH_LEVEL_FUNCTIONS = + { + .DEFAULT = IO_DEFAULT, + .DI = IO_DI, + .AI = IO_AI, + .DO = IO_DO, + .PWM = IO_PWM, + .SD = IO_SD, + .CLK16 = IO_CLK16, + .SPI = IO_SPI + } +}; + +static void init() +{ + + rcu_periph_clock_enable(RCU_SYSCFG); + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + rcu_ckout0_config(RCU_CKOUT0SRC_HXTAL, RCU_CKOUT0_DIV1); + +} + +static void setPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + gpio_mode_set(pin->port, pin->configuration.GPIO_Mode, pin->configuration.GPIO_PuPd, pin->bitWeight); + gpio_output_options_set(pin->port, pin->configuration.GPIO_OType, pin->configuration.GPIO_Speed, pin->bitWeight); + +} + +static void setPin2Output(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + setPinConfiguration(pin); +} + +static void setPin2Input(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_MODE_INPUT; + setPinConfiguration(pin); +} + +static void setPinState(IOPinTypeDef *pin, IO_States state) +{ + if(IS_DUMMY_PIN(pin)) + return; + switch(state) + { + case IOS_LOW: + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + *pin->resetBitRegister = pin->bitWeight; + break; + case IOS_HIGH: + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + *pin->setBitRegister = pin->bitWeight; + break; + case IOS_OPEN: + pin->configuration.GPIO_Mode = GPIO_MODE_ANALOG; + break; + default: + break; + } + + setPinConfiguration(pin); +} + +static IO_States getPinState(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return IOS_OPEN; + + if(pin->configuration.GPIO_Mode == GPIO_MODE_INPUT) + pin->state = (GPIO_ISTAT(pin->port) & pin->bitWeight) ? IOS_HIGH : IOS_LOW; + else if(pin->configuration.GPIO_Mode == GPIO_MODE_OUTPUT) + pin->state = (GPIO_OCTL(pin->port) & pin->bitWeight) ? IOS_HIGH : IOS_LOW; + else + pin->state = IOS_OPEN; + + return pin->state; +} + +static void setPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->setBitRegister = pin->bitWeight; +} + +static void setPinLow(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->resetBitRegister = pin->bitWeight; +} + +static unsigned char isPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return -1; + + return (GPIO_ISTAT(pin->port) & pin->bitWeight)? 1 : 0; +} + +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef *to) +{ + if(IS_DUMMY_PIN(to)) + return; + + to->configuration.GPIO_Mode = from->GPIO_Mode; + to->configuration.GPIO_OType = from->GPIO_OType; + to->configuration.GPIO_PuPd = from->GPIO_PuPd; + to->configuration.GPIO_Speed = from->GPIO_Speed; + setPinConfiguration(to); +} + +static void resetPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + copyPinConfiguration(&(pin->resetConfiguration), pin); + pin->highLevelFunction = IOs.HIGH_LEVEL_FUNCTIONS.DEFAULT; +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c new file mode 100644 index 0000000..e399e2e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c @@ -0,0 +1,72 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include +#include "hal/HAL.h" +#include "hal/LEDs.h" + +static void init(); +static void onStat(); +static void onError(); +static void offStat(); +static void offError(); +static void toggleStat(); +static void toggleError(); + +LEDsTypeDef LEDs = +{ + .init = init, + .stat = + { + .on = onStat, + .off = offStat, + .toggle = toggleStat, + }, + .error = + { + .on = onError, + .off = offError, + .toggle = toggleError, + }, +}; + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + LED_OFF(); + LED_ERROR_OFF(); +} + +static void onStat() +{ + LED_ON(); +} + +static void onError() +{ + LED_ERROR_ON(); +} + +static void offStat() +{ + LED_OFF(); +} + +static void offError() +{ + LED_ERROR_OFF(); +} + +static void toggleStat() +{ + LED_TOGGLE(); +} + +static void toggleError() +{ + LED_ERROR_TOGGLE(); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c new file mode 100644 index 0000000..e0bee27 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c @@ -0,0 +1,106 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static uint32_t available = 0; + +RXTXTypeDef RS232 = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART6_IRQHandler(void); + +static void init() +{ + +} + +static void deInit() +{ + +} + +void USART6_IRQHandler(void) +{ + +} + +static void tx(uint8_t ch) +{ + +} + +static uint8_t rx(uint8_t *ch) +{ +return 0; +} + +static void txN(uint8_t *str, unsigned char number) +{ + +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + return 0; + +} + +static void clearBuffers(void) +{ + +} + +static uint32_t bytesAvailable() +{ + return 0; + +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c new file mode 100644 index 0000000..a4ab307 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c @@ -0,0 +1,11 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/RXTX.h" +#include "hal/WLAN.h" +#include "hal/UART.h" + + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c new file mode 100644 index 0000000..810cb13 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c @@ -0,0 +1,303 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/SPI.h" + +static void init(void); +static void reset_ch1(); +static void reset_ch2(); + +static unsigned char readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); +static unsigned char spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer); +static unsigned char spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer); +static void spi_ch1_readWriteArray(uint8_t *data, size_t length); +static void spi_ch2_readWriteArray(uint8_t *data, size_t length); + +SPIChannelTypeDef *SPIChannel_1_default; +SPIChannelTypeDef *SPIChannel_2_default; + +static uint16_t SPI_PSC_Factor[16] = { 2, 4, 8, 16, 32, 64, 128, 256}; + +static IOPinTypeDef IODummy = { .bitWeight = DUMMY_BITWEIGHT }; + +SPITypeDef SPI= +{ + .ch1 = + { + .periphery = SPI1, + .CSN = &IODummy, + .readWrite = spi_ch1_readWrite, + .readWriteArray = spi_ch1_readWriteArray, + .reset = reset_ch1 + }, + + .ch2 = + { + .periphery = SPI0, + .CSN = &IODummy, + .readWrite = spi_ch2_readWrite, + .readWriteArray = spi_ch2_readWriteArray, + .reset = reset_ch2 + }, + .init = init +}; + + +static void init(void) +{ + rcu_periph_clock_enable(RCU_SPI1); + rcu_periph_clock_enable(RCU_SPI0); + + // Config + spi_parameter_struct params; + + params.device_mode = SPI_MASTER; + params.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + params.frame_size = SPI_FRAMESIZE_8BIT; + params.nss = SPI_NSS_SOFT; + params.endian = SPI_ENDIAN_MSB; + params.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + params.prescale = SPI_PSC_16; // PCLK for SPI1 is 60MHz => SPI1 freq = 60/16 = 3,75MHz + + spi_init(SPI.ch1.periphery, ¶ms); + + params.prescale = SPI_PSC_32; // PCLK for SPI0 is 120MHz => SPI0 freq = 120/32 = 3,75MHz + + spi_init(SPI.ch2.periphery, ¶ms); + + // Enable + spi_enable(SPI.ch1.periphery); + spi_enable(SPI.ch2.periphery); + + // Set pin AFs + + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_15); + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_14); + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_13); + + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_7); + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_6); + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_5); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN2); + + reset_ch1(); + reset_ch2(); + + // configure default SPI channel_1 + SPIChannel_1_default = &HAL.SPI->ch1; + SPIChannel_1_default->CSN = &HAL.IOs->pins->SPI1_CSN; + // configure default SPI channel_2 + SPIChannel_2_default = &HAL.SPI->ch2; + SPIChannel_2_default->CSN = &HAL.IOs->pins->SPI2_CSN0; + +} + +static void reset_ch1() +{ + SPI.ch1.CSN = &IODummy; + SPI.ch1.periphery = SPI1; + SPI.ch1.readWrite = spi_ch1_readWrite; +} + +static void reset_ch2() +{ + SPI.ch2.CSN = &IODummy; + SPI.ch2.periphery = SPI0; + SPI.ch2.readWrite = spi_ch2_readWrite; +} + +uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel) +{ + uint32_t PCLK; + if(SPIChannel->periphery == SPI1 || SPIChannel->periphery == SPI2) + { + PCLK = rcu_clock_freq_get(CK_APB1); + } + else + { + PCLK = rcu_clock_freq_get(CK_APB2); + } + uint8_t PSC_Val = (SPI_CTL0(SPIChannel->periphery) & SPI_CTL0_PSC)>>3; + return PCLK/SPI_PSC_Factor[PSC_Val]; +} + +// Set the SPI frequency to the next-best available frequency (rounding down). +// Returns the actual frequency set or 0 if no suitable frequency was found. +uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency) +{ + uint32_t PCLK; + if(SPIChannel->periphery == SPI1 || SPIChannel->periphery == SPI2) + { + PCLK = rcu_clock_freq_get(CK_APB1); + } + else + { + PCLK = rcu_clock_freq_get(CK_APB2); + } + + uint32_t prescaler; + if(desiredFrequency > 0) + { + prescaler = PCLK/desiredFrequency; + } + else{ + + return 0; + } + + if(prescaler == 1) + { + return PCLK; + } + else if(prescaler>1) + { + // Find the highest frequency that is lower or equal to the desired frequency + for(int32_t i=0; iperiphery) = ( SPI_CTL0(SPIChannel->periphery) & (~SPI_CTL0_PSC) ) | PSC_Val; + return PCLK/prescaler; + } + } + } + // The requested frequency was too small -> do not update the frequency + return 0; +} + +uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel) +{ + if (!SPIChannel) + return 0; + + uint32_t tmp = SPI_CTL0(SPIChannel->periphery); + uint8_t cpol = (tmp & SPI_CTL0_CKPL) != 0; + uint8_t cpha = (tmp & SPI_CTL0_CKPH) != 0; + + return (cpol << 1) | cpha; +} + +bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode) +{ + if (!SPIChannel) + return false; + + if (mode > 3) + return false; + + uint8_t cpol = (mode>>1) & 1; + uint8_t cpha = mode & 1; + + uint32_t tmp = SPI_CTL0(SPIChannel->periphery); + tmp &= ~(SPI_CTL0_CKPL | SPI_CTL0_CKPH); + tmp |= cpol ? SPI_CTL0_CKPL : 0; + tmp |= cpha ? SPI_CTL0_CKPH : 0; + SPI_CTL0(SPIChannel->periphery) = tmp; + + return true; +} + +int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address) +{ + // clear write bit + address &= 0x7F; + + SPIChannel->readWrite(address, false); + int32_t value = SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, true); + + return value; +} + +int32_t spi_ch1_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_1_default, address); +} + +int32_t spi_ch2_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_2_default, address); +} + +void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value) +{ + SPIChannel->readWrite(address | 0x80, false); + SPIChannel->readWrite(0xFF & (value>>24), false); + SPIChannel->readWrite(0xFF & (value>>16), false); + SPIChannel->readWrite(0xFF & (value>>8), false); + SPIChannel->readWrite(0xFF & (value>>0), true); +} + +void spi_ch1_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_1_default, address, value); +} + +void spi_ch2_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_2_default, address, value); +} + +static unsigned char spi_ch1_readWrite(unsigned char data, unsigned char lastTransfer) +{ + return readWrite(&SPI.ch1, data, lastTransfer); +} + +static unsigned char spi_ch2_readWrite(unsigned char data, unsigned char lastTransfer) +{ + return readWrite(&SPI.ch2, data,lastTransfer); +} + +static void spi_ch1_readWriteArray(uint8_t *data, size_t length) +{ + for(uint32_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch1, data[i], (i == (length - 1))? true:false); + } +} + +static void spi_ch2_readWriteArray(uint8_t *data, size_t length) +{ + for(uint32_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch2, data[i], (i == (length - 1))? true:false); + } +} + +uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(SPIChannel_1_default, data, lastTransfer); +} + +uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + return SPIChannel->readWrite(data, lastTransfer); +} + +static unsigned char readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + if(IS_DUMMY_PIN(SPIChannel->CSN)) + return 0; + + HAL.IOs->config->setLow(SPIChannel->CSN); + + while(spi_i2s_flag_get(SPIChannel->periphery, SPI_FLAG_TBE) == RESET); + spi_i2s_data_transmit(SPIChannel->periphery, data); + while(spi_i2s_flag_get(SPIChannel->periphery, SPI_FLAG_RBNE) == RESET); + if(lastTransfer) + HAL.IOs->config->setHigh(SPIChannel->CSN); + + return spi_i2s_data_receive(SPIChannel->periphery); +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c new file mode 100644 index 0000000..071bc68 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "gd32f4xx.h" +#include "hal/HAL.h" +#include "hal/SysTick.h" + +volatile uint32_t systick = 0; + +#define SYSTICK_PRE_EMPTION_PRIORITY 3 + +void systick_init(void) +{ + SysTick_Config(SystemCoreClock/(1000)); + NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRE_EMPTION_PRIORITY); + + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CYCCNT = 0; + // Enable the DWT CYCCNT for the µs counter + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; +} + + +void SysTick_Handler(void) +{ + systick++; +} + +uint32_t systick_getMicrosecondTick() +{ + // 240 MHz CYCCNT / 240 -> µs counter + return DWT->CYCCNT / 240; +} + +uint32_t systick_getTick(void) +{ + return systick; +} + +void wait(uint32_t delay) // wait for [delay] ms/systicks +{ + uint32_t startTick = systick; + while((systick-startTick) <= delay) {} +} + +uint32_t timeSince(uint32_t tick) // time difference since the [tick] timestamp in ms/systicks +{ + return timeDiff(systick, tick); +} + +uint32_t timeDiff(uint32_t newTick, uint32_t oldTick) // Time difference between newTick and oldTick timestamps +{ + uint32_t tickDiff = newTick - oldTick; + + // Prevent subtraction underflow - saturate to 0 instead + if(tickDiff != 0) + return tickDiff - 1; + else + return 0; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c new file mode 100644 index 0000000..42d9bb6 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c @@ -0,0 +1,331 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/Timer.h" + +/* +HAL Timer channels + +TIMER_CHANNEL_1 = TIMER 0 Channel 2, PWM output DIO11 +TIMER_CHANNEL_2 = TIMER 3 Channel 0, RAMDebug +TIMER_CHANNEL_3 = TIMER 4 Channel 0 +TIMER_CHANNEL_4 = TIMER 0 Channel 1, PWM output DIO9 +TIMER_CHANNEL_5 = TIMER 0 Channel 0, PWM output DIO7 +*/ + +#define TIMER_BASE_CLK 240000000 + +static void init(void); +static void deInit(void); +static void setDuty(timer_channel channel, float duty); +static float getDuty(timer_channel channel); +static void setPeriod(timer_channel channel, uint16_t period); +static uint16_t getPeriod(timer_channel channel); +static void setPeriodMin(timer_channel channel, uint16_t period_min); +static void setFrequency(timer_channel channel, float freq); +static void setFrequencyMin(timer_channel channel, float freq_min); + +static uint16_t period_min_buf[] = { 0, 0, 0 }; +static float freq_min_buf[] = { 0.0f, 0.0f, 0.0f }; + +TimerTypeDef Timer = +{ + .initialized = false, + .init = init, + .deInit = deInit, + .setDuty = setDuty, + .getDuty = getDuty, + .setPeriod = setPeriod, + .getPeriod = getPeriod, + .setPeriodMin = setPeriodMin, + .setFrequency = setFrequency, + .setFrequencyMin = setFrequencyMin, + .overflow_callback = NULL +}; + +static void init(void) +{ + rcu_periph_clock_enable(RCU_TIMER0); + rcu_periph_clock_enable(RCU_TIMER3); + rcu_periph_clock_enable(RCU_TIMER4); + timer_deinit(TIMER0); + timer_deinit(TIMER3); + timer_deinit(TIMER4); + + timer_parameter_struct params; + timer_oc_parameter_struct oc_params; + + // TIMER_CHANNEL_1 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER0, ¶ms); + + timer_channel_output_struct_para_init(&oc_params); + oc_params.ocpolarity = TIMER_OC_POLARITY_HIGH; + oc_params.outputstate = TIMER_CCX_ENABLE; + oc_params.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + oc_params.outputnstate = TIMER_CCXN_DISABLE; + oc_params.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + oc_params.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER0, TIMER_CH_2, &oc_params); + // TIMER_CHANNEL_4 + timer_channel_output_config(TIMER0, TIMER_CH_1, &oc_params); + // TIMER_CHANNEL_5 + timer_channel_output_config(TIMER0, TIMER_CH_0, &oc_params); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + // TIMER_CHANNEL_4 + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + // TIMER_CHANNEL_5 + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + timer_primary_output_config(TIMER0, ENABLE); + + timer_auto_reload_shadow_enable(TIMER0); + + timer_enable(TIMER0); + + // TIMER_CHANNEL_2 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER3, ¶ms); + + timer_interrupt_enable(TIMER3, TIMER_INT_UP); + nvic_irq_enable(TIMER3_IRQn, 0, 1); + timer_interrupt_flag_clear(TIMER3, TIMER_INT_FLAG_UP); + timer_auto_reload_shadow_enable(TIMER3); + + timer_enable(TIMER3); + + // TIMER_CHANNEL_3 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER4, ¶ms); + + timer_auto_reload_shadow_enable(TIMER4); + + timer_enable(TIMER4); + + Timer.initialized = true; +} + +static void deInit(void) +{ + timer_deinit(TIMER0); + timer_deinit(TIMER3); + timer_deinit(TIMER4); +} + +static void setDuty(timer_channel channel, float duty) +{ + duty = (duty < 0.0f) ? 0.0f : duty; + duty = (duty > 1.0f) ? 1.0f : duty; + + switch(channel) { + case TIMER_CHANNEL_1: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, duty * TIMER_CAR(TIMER0)); + break; + case TIMER_CHANNEL_2: + timer_channel_output_pulse_value_config(TIMER3, TIMER_CH_0, duty * TIMER_CAR(TIMER3)); + break; + case TIMER_CHANNEL_3: + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, duty * TIMER_CAR(TIMER4)); + break; + case TIMER_CHANNEL_4: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, duty * TIMER_CAR(TIMER0)); + break; + case TIMER_CHANNEL_5: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, duty * TIMER_CAR(TIMER0)); + break; + } +} + +static float getDuty(timer_channel channel) +{ + switch(channel) { + case TIMER_CHANNEL_1: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_2)) / TIMER_CAR(TIMER0)); + case TIMER_CHANNEL_2: + return (((float) timer_channel_capture_value_register_read(TIMER3, TIMER_CH_0)) / TIMER_CAR(TIMER3)); + case TIMER_CHANNEL_3: + return (((float) timer_channel_capture_value_register_read(TIMER4, TIMER_CH_0)) / TIMER_CAR(TIMER4)); + case TIMER_CHANNEL_4: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_1)) / TIMER_CAR(TIMER0)); + case TIMER_CHANNEL_5: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_0)) / TIMER_CAR(TIMER0)); + } +} + +static void setPeriod(timer_channel channel, uint16_t period) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + timer_autoreload_value_config(TIMER0, period); + break; + case TIMER_CHANNEL_2: + timer_autoreload_value_config(TIMER3, period); + break; + case TIMER_CHANNEL_3: + timer_autoreload_value_config(TIMER4, period); + break; + } +} + +static uint16_t getPeriod(timer_channel channel) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + return TIMER_CAR(TIMER0); + case TIMER_CHANNEL_2: + return TIMER_CAR(TIMER3); + case TIMER_CHANNEL_3: + return TIMER_CAR(TIMER4); + } +} + +static void setPeriodMin(timer_channel channel, uint16_t period_min) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + period_min_buf[0] = period_min; + break; + case TIMER_CHANNEL_2: + period_min_buf[1] = period_min; + break; + case TIMER_CHANNEL_3: + period_min_buf[2] = period_min; + break; + } +} + +static void setFrequencyMin(timer_channel channel, float freq_min) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + freq_min_buf[0] = freq_min; + break; + case TIMER_CHANNEL_2: + freq_min_buf[1] = freq_min; + break; + case TIMER_CHANNEL_3: + freq_min_buf[2] = freq_min; + break; + } +} + +static void setFrequency(timer_channel channel, float freq) +{ + float freq_min; + uint16_t period_min; + uint32_t timer; + uint32_t timer_ch; + IRQn_Type irq; + + switch(channel) { + case TIMER_CHANNEL_1: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_2; + irq = TIMER0_Channel_IRQn; + break; + case TIMER_CHANNEL_2: + freq_min = freq_min_buf[1]; + period_min = period_min_buf[1]; + timer = TIMER3; + timer_ch = TIMER_CH_0; + irq = TIMER3_IRQn; + break; + case TIMER_CHANNEL_3: + freq_min = freq_min_buf[2]; + period_min = period_min_buf[2]; + timer = TIMER4; + timer_ch = TIMER_CH_0; + irq = TIMER4_IRQn; + break; + case TIMER_CHANNEL_4: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_1; + irq = TIMER0_Channel_IRQn; + break; + case TIMER_CHANNEL_5: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_0; + irq = TIMER0_Channel_IRQn; + break; + } + + uint16_t prescaler = 0; + uint16_t period = 0xFFFF; + + if(freq < ((float)TIMER_BASE_CLK / (0x0000FFFF * 0x0000FFFF))) + return; + + if(freq > (float)TIMER_BASE_CLK) + return; + + for(; prescaler < 0xFFFF; prescaler++) + { + if(freq > ((float)TIMER_BASE_CLK / ((prescaler + 1) * period))) + { + period = (float)TIMER_BASE_CLK / ((prescaler + 1) * freq); + if(period < period_min) + period = (float)TIMER_BASE_CLK / (prescaler * freq); + break; + } + } + + timer_prescaler_config(timer, prescaler, TIMER_PSC_RELOAD_NOW); + timer_autoreload_value_config(timer, period); +} + +void TIMER3_IRQHandler(void) +{ + if(timer_flag_get(TIMER3, TIMER_FLAG_UP) == SET) + { + if(Timer.overflow_callback) + Timer.overflow_callback(TIMER_CHANNEL_2); + timer_flag_clear(TIMER3, TIMER_FLAG_UP); + } +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c new file mode 100644 index 0000000..cd33ac3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c @@ -0,0 +1,448 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/UART.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static uint8_t UARTSendFlag; + +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; +static volatile uint32_t usart_periph; +uint8_t volatile nvic_irq; + +static volatile uint32_t available = 0; + +UART_Config UART = +{ + .mode = UART_MODE_DUAL_WIRE, + .pinout = UART_PINS_1, + .rxtx = + { + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable + } +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART2_IRQHandler(void); +void __attribute__ ((interrupt)) UART3_IRQHandler(void); + + +static void init() +{ + + switch(UART.pinout) { + case UART_PINS_2: + //Set MUX_1 and MUX_2 to zero to connect DIO10 and DIO11 to UART pins DIO10_UART_TX and DIO11_UART_RX respectively. + *HAL.IOs->pins->SW_UART_PWM.resetBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + + usart_periph = UART3; + usart_deinit(usart_periph); + //DIO10_UART_TX(TxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + + //DIO11_UART_RX(RxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_AF_8, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_AF_8, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + rcu_periph_clock_enable(RCU_UART3); + nvic_irq = UART3_IRQn; + break; + case UART_PINS_1: + usart_periph = USART2; + usart_deinit(usart_periph); + //DIO17(TxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO17.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO17.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO17.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO17.bitWeight); + + //DIO18(RxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO18.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO18.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO18.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO18.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO17.port, GPIO_AF_7, HAL.IOs->pins->DIO17.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO18.port, GPIO_AF_7, HAL.IOs->pins->DIO18.bitWeight); + rcu_periph_clock_enable(RCU_USART2); + usart_hardware_flow_rts_config(usart_periph, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(usart_periph, USART_CTS_DISABLE); + nvic_irq = USART2_IRQn; + break; + } + + + usart_baudrate_set(usart_periph, 115200); + usart_word_length_set(usart_periph, USART_WL_8BIT); + usart_stop_bit_set(usart_periph, USART_STB_1BIT); + usart_parity_config(usart_periph, USART_PM_NONE); + usart_receive_config(usart_periph, USART_RECEIVE_ENABLE); + usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE); + usart_enable(usart_periph); + usart_interrupt_enable(usart_periph, USART_INT_TBE); + usart_interrupt_enable(usart_periph, USART_INT_TC); + usart_interrupt_enable(usart_periph, USART_INT_RBNE); + + nvic_irq_enable(nvic_irq, INTR_PRI, 0); + + usart_flag_clear(usart_periph, USART_FLAG_CTS); + usart_flag_clear(usart_periph, USART_FLAG_LBD); + usart_flag_clear(usart_periph, USART_FLAG_TBE); + usart_flag_clear(usart_periph, USART_FLAG_TC); + usart_flag_clear(usart_periph, USART_FLAG_RBNE); + usart_flag_clear(usart_periph, USART_FLAG_IDLE); + usart_flag_clear(usart_periph, USART_FLAG_ORERR); + usart_flag_clear(usart_periph, USART_FLAG_NERR); + usart_flag_clear(usart_periph, USART_FLAG_FERR); + usart_flag_clear(usart_periph, USART_FLAG_PERR); + +} + +static void deInit() +{ + usart_disable(usart_periph); + nvic_irq_disable(nvic_irq); + + usart_flag_clear(usart_periph, USART_FLAG_CTS); + usart_flag_clear(usart_periph, USART_FLAG_LBD); + usart_flag_clear(usart_periph, USART_FLAG_TBE); + usart_flag_clear(usart_periph, USART_FLAG_TC); + usart_flag_clear(usart_periph, USART_FLAG_RBNE); + usart_flag_clear(usart_periph, USART_FLAG_IDLE); + usart_flag_clear(usart_periph, USART_FLAG_ORERR); + usart_flag_clear(usart_periph, USART_FLAG_NERR); + usart_flag_clear(usart_periph, USART_FLAG_FERR); + usart_flag_clear(usart_periph, USART_FLAG_PERR); + + clearBuffers(); +} + +void USART2_IRQHandler(void) +{ + uint8_t byte; + usart_periph = USART2; + // Receive interrupt + if(USART_STAT0(usart_periph) & USART_STAT0_RBNE) + { + // One-wire UART communication: + // Ignore received byte when a byte has just been sent (echo). + byte = USART_DATA(usart_periph); + + if(!UARTSendFlag) + { // not sending, received real data instead of echo -> advance ring buffer index and available counter + buffers.rx.buffer[buffers.rx.wrote]=byte; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UARTSendFlag = true; + USART_DATA(usart_periph) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { + usart_interrupt_disable(usart_periph, USART_INT_TBE); + + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TC) + { + //Only if there are no more bytes left in the transmit buffer + if(buffers.tx.read == buffers.tx.wrote) + { + byte = USART_DATA(usart_periph); //Ignore spurios echos of the last sent byte that sometimes occur. + UARTSendFlag = false; + } +// USART_ClearITPendingBit(USART2, USART_IT_TC); + usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); + + } +} + +void UART3_IRQHandler(void) +{ + uint8_t byte; + usart_periph = UART3; + // Receive interrupt + if(USART_STAT0(usart_periph) & USART_STAT0_RBNE) + { + // One-wire UART communication: + // Ignore received byte when a byte has just been sent (echo). + byte = USART_DATA(usart_periph); + + if(!UARTSendFlag) + { // not sending, received real data instead of echo -> advance ring buffer index and available counter + buffers.rx.buffer[buffers.rx.wrote]=byte; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UARTSendFlag = true; + USART_DATA(usart_periph) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { + usart_interrupt_disable(usart_periph, USART_INT_TBE); + + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TC) + { + //Only if there are no more bytes left in the transmit buffer + if(buffers.tx.read == buffers.tx.wrote) + { + byte = USART_DATA(usart_periph); //Ignore spurios echos of the last sent byte that sometimes occur. + UARTSendFlag = false; + } +// USART_ClearITPendingBit(USART2, USART_IT_TC); + usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); + + } +} + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(2); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = systick_getTick(); + while(uart->rxtx.bytesAvailable() < readLength) + { + if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + { + // Abort on timeout + return -1; + } + } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value) +{ + uint8_t readData[8], dataRequest[4]; + uint32_t timeout; + + dataRequest[0] = 0x05; // Sync byte + dataRequest[1] = slave; // Slave address + dataRequest[2] = address; // Register address + dataRequest[3] = tmc_CRC8(dataRequest, 3, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + channel->rxtx.txN(dataRequest, ARRAY_SIZE(dataRequest)); + + // Wait for reply with timeout limit + timeout = systick_getTick(); + while(channel->rxtx.bytesAvailable() < ARRAY_SIZE(readData)) + if(timeSince(timeout) > UART_TIMEOUT_VALUE) // Timeout + return; + + channel->rxtx.rxN(readData, ARRAY_SIZE(readData)); + // Check if the received data is correct (CRC, Sync, Slave address, Register address) + // todo CHECK 2: Only keep CRC check? Should be sufficient for wrong transmissions (LH) #1 + if(readData[7] != tmc_CRC8(readData, 7, 1) || readData[0] != 0x05 || readData[1] != 0xFF || readData[2] != address) + return; + + *value = readData[3] << 24 | readData[4] << 16 | readData[5] << 8 | readData[6]; + return; +} + +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value) +{ + uint8_t writeData[8]; + + writeData[0] = 0x05; // Sync byte + writeData[1] = slave; // Slave address + writeData[2] = address | TMC_WRITE_BIT; // Register address with write bit set + writeData[3] = value >> 24; // Register Data + writeData[4] = value >> 16; // Register Data + writeData[5] = value >> 8; // Register Data + writeData[6] = value & 0xFF; // Register Data + writeData[7] = tmc_CRC8(writeData, 7, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + for(uint32_t i = 0; i < ARRAY_SIZE(writeData); i++) + channel->rxtx.tx(writeData[i]); + + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(2); +} + +void UART_setEnabled(UART_Config *channel, uint8_t enabled) +{ + UNUSED(channel); + switch(channel->pinout) + { + case UART_PINS_2: + if (enabled) + { + + //TxD as open drain output + gpio_mode_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + + //RxD with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_AF_8, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_AF_8, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + } + else{ + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_UART_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_UART_RX); + } + break; + case UART_PINS_1: + if (enabled) + { + //TxD as open drain output + gpio_mode_set(HAL.IOs->pins->DIO17.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO17.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO17.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO17.bitWeight); + + //RxD with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO18.port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, HAL.IOs->pins->DIO18.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO18.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO18.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO17.port, GPIO_AF_7, HAL.IOs->pins->DIO17.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO18.port, GPIO_AF_7, HAL.IOs->pins->DIO18.bitWeight); + } + else{ + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + } + break; + } + +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + usart_interrupt_enable(usart_periph, USART_INT_TBE); + +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, unsigned char number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + if(bytesAvailable() < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + __disable_irq(); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + __enable_irq(); +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c new file mode 100644 index 0000000..5b546dc --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c @@ -0,0 +1,245 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "gd32f4xx.h" +#include "usb/drv_usbd_int.h" +#include "usb/drv_usb_hw.h" +#include "usb/cdc_acm_core.h" +#include "hal/HAL.h" + +#define BUFFER_SIZE 2048 // KEEP THIS SIZE AS IT MATCHES BUFFERSIZE OF usbd_cdc_core.c + +// Specific functions +static void USBSendData(uint8_t *Buffer, uint32_t Size); +static uint32_t USBGetData(uint8_t *Buffer, size_t amount); +static uint8_t GetUSBCmd(uint8_t *Cmd); +static void InitUSB(void); +static void DetachUSB(void); + +// Interface functions +static void init(void); +static void deInit(void); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *str, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(void); + +static usb_core_driver cdc_acm; +static uint8_t USBDataTxBuffer[256]; +static volatile uint32_t available = 0; + +// static RXTXBufferingTypeDef buffers = +// { +// .rx = +// { +// .read = 0, +// .wrote = 0, +// .buffer = rxBuffer +// }, + +// .tx = +// { +// .read = 0, +// .wrote = 0, +// .buffer = APP_Rx_Buffer +// } +// }; + +RXTXTypeDef USB = +{ + .init = init, + .deInit = deInit, + .rx = NULL, + .tx = NULL, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +void usb_timer_irq (void); + +void TIMER6_IRQHandler(void) +{ + usb_timer_irq(); +} + +void USBFS_IRQHandler(void) +{ + usbd_isr(&cdc_acm); +} + +static void InitUSB(void) +{ + usb_gpio_config(); + usb_rcu_config(); + usb_timer_init(); + usbd_init(&cdc_acm, USB_CORE_ENUM_FS, &cdc_desc, &cdc_class); + usb_intr_config(); +} + +static void DetachUSB(void) +{ + usb_dev_stop(&cdc_acm); +} + +/******************************************************************* + Funktion: USBSendData() + Parameter: Buffer: Array mit den zu sendenden Daten + Size: Anzahl der zu sendenden Bytes + + R�ckgabewert: --- + + Zweck: Senden von Daten �ber USB. +********************************************************************/ +static void USBSendData(uint8_t *Buffer, uint32_t Size) +{ + uint32_t i; + + for(i=0; idev.class_data[CDC_COM_INTERFACE]; + + i=0; + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length >= amount) + { + for(i=0; i < amount; i++) Buffer[i]=cdc->data[i]; + flag = TRUE; + } + cdc->packet_receive = 0; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + return flag; +} + + +/******************************************************************* + Funktion: GetUSBCmd() + Parameter: Cmd: Array (9 Bytes) f�r den TMCL-Befehl. + + R�ckgabewert: TRUE bei Erfolg + FALSE wenn kein Befehl vorhanden + + Zweck: Abholen eines TMCL-Befehls �ber USB. +********************************************************************/ +static uint8_t GetUSBCmd(uint8_t *Cmd) +{ + uint8_t flag; + uint32_t i; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + + flag=FALSE; + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length>=9) + { + for(i=0; i<9; i++) Cmd[i]=cdc->data[i]; + flag=TRUE; + } + cdc->packet_receive=0; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + return flag; +} + +static void init(void) +{ + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DM); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DP); + + InitUSB(); +} + +static void tx(uint8_t ch) +{ + //buffers.tx.buffer[buffers.tx.wrote] = ch; + //buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + usbd_ep_send((usb_dev *) &cdc_acm, CDC_DATA_IN_EP, &ch, 1); +} + +static uint8_t rx(uint8_t *ch) +{ + uint8_t data = 0; + uint8_t i = 0; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length > 0) + { + data = cdc->data[0]; + i = 1; + } + cdc->packet_receive--; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + + return i; +} + +static void txN(uint8_t *str, unsigned char number) +{ + USBSendData(str, number); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + return USBGetData(str, number); +} + +static void clearBuffers(void) +{ + // __disable_irq(); + // available = 0; + // buffers.rx.read = 0; + // buffers.rx.wrote = 0; + + // buffers.tx.read = 0; + // buffers.tx.wrote = 0; + // __enable_irq(); +} + +static uint32_t bytesAvailable(void) +{ + return available; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + return cdc->receive_length; +} + +static void deInit(void) +{ + +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c new file mode 100644 index 0000000..40d174e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c @@ -0,0 +1,360 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" +#include "hal/WLAN.h" +#include "hal/RXTX.h" +#include + + +#define BUFFER_SIZE 1024 +#define WLAN_CMD_BUFFER_SIZE 128 // ascii command string buffer + +#define INTR_PRI 6 + +#define CMDBUFFER_END_CHAR '\0' + + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; + +static int8_t cmdBuffer[WLAN_CMD_BUFFER_SIZE]; +static uint32_t cmdBufferSize = 0; +static uint32_t cmdEnabledTime; // systick timestamp when command mode sequence has been sent + + +static WLANStateTypedef wlanState = WLAN_DATA_MODE; + + +static volatile uint32_t available = 0; + +RXTXTypeDef WLAN = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART1_IRQHandler(void); + + +static void init() +{ + usart_deinit(RCU_USART1); + + HAL.IOs->pins->WIFI_RX.configuration.GPIO_Mode = GPIO_AF_7; + HAL.IOs->pins->WIFI_TX.configuration.GPIO_Mode = GPIO_AF_7; + + HAL.IOs->config->set(&HAL.IOs->pins->WIFI_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIFI_TX); + gpio_af_set(HAL.IOs->pins->WIFI_RX.port, GPIO_AF_7, HAL.IOs->pins->WIFI_RX.bitWeight); + gpio_af_set(HAL.IOs->pins->WIFI_TX.port, GPIO_AF_7, HAL.IOs->pins->WIFI_TX.bitWeight); + + rcu_periph_clock_enable(RCU_USART1); + + usart_hardware_flow_rts_config(RCU_USART1, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(RCU_USART1, USART_CTS_DISABLE); + + usart_baudrate_set(RCU_USART1, 115200); + usart_word_length_set(RCU_USART1, USART_WL_8BIT); + usart_stop_bit_set(RCU_USART1, USART_STB_1BIT); + usart_parity_config(RCU_USART1, USART_PM_NONE); + usart_receive_config(RCU_USART1, USART_RECEIVE_ENABLE); + usart_transmit_config(RCU_USART1, USART_TRANSMIT_ENABLE); + usart_enable(RCU_USART1); + usart_interrupt_enable(RCU_USART1, USART_INT_TBE); + usart_interrupt_enable(RCU_USART1, USART_INT_TC); + usart_interrupt_enable(RCU_USART1, USART_INT_RBNE); + + nvic_irq_enable(USART1_IRQn, INTR_PRI, 0); + + usart_flag_clear(RCU_USART1, USART_FLAG_CTS); + usart_flag_clear(RCU_USART1, USART_FLAG_LBD); + usart_flag_clear(RCU_USART1, USART_FLAG_TBE); + usart_flag_clear(RCU_USART1, USART_FLAG_TC); + usart_flag_clear(RCU_USART1, USART_FLAG_RBNE); + usart_flag_clear(RCU_USART1, USART_FLAG_IDLE); + usart_flag_clear(RCU_USART1, USART_FLAG_ORERR); + usart_flag_clear(RCU_USART1, USART_FLAG_NERR); + usart_flag_clear(RCU_USART1, USART_FLAG_FERR); + usart_flag_clear(RCU_USART1, USART_FLAG_PERR); + +} + +static void deInit() +{ + usart_disable(RCU_USART1); + nvic_irq_disable(USART1_IRQn); + + usart_flag_clear(RCU_USART1, USART_FLAG_CTS); + usart_flag_clear(RCU_USART1, USART_FLAG_LBD); + usart_flag_clear(RCU_USART1, USART_FLAG_TBE); + usart_flag_clear(RCU_USART1, USART_FLAG_TC); + usart_flag_clear(RCU_USART1, USART_FLAG_RBNE); + usart_flag_clear(RCU_USART1, USART_FLAG_IDLE); + usart_flag_clear(RCU_USART1, USART_FLAG_ORERR); + usart_flag_clear(RCU_USART1, USART_FLAG_NERR); + usart_flag_clear(RCU_USART1, USART_FLAG_FERR); + usart_flag_clear(RCU_USART1, USART_FLAG_PERR); + + clearBuffers(); +} + + +void USART1_IRQHandler(void) +{ + // Receive interrupt + if(USART_STAT0(RCU_USART1) & USART_STAT0_RBNE) + { + buffers.rx.buffer[buffers.rx.wrote] = USART_DATA(RCU_USART1); + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + } + + if(USART_STAT0(RCU_USART1) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + USART_DATA(RCU_USART1) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else // empty buffer -> turn off send interrupt + { + usart_interrupt_disable(RCU_USART1, USART_INT_TBE); + } + } + + if(USART_STAT0(RCU_USART1) & USART_STAT0_TC) + { + usart_interrupt_flag_clear(RCU_USART1, USART_INT_FLAG_TC); + + } +} + + +// Send without checking for CMD/Data mode +static void rawTx(uint8_t ch) +{ + if(wlanState == WLAN_INIT_CMD_MODE) + return; + + buffers.tx.buffer[buffers.tx.wrote] = ch; + + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; // Move ring buffer index + + // enable send interrupt + usart_interrupt_enable(RCU_USART1, USART_INT_TBE); +} + +static void tx(uint8_t ch) +{ + if(checkReadyToSend()) + rawTx(ch); +} + +static uint8_t rawRx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; // Move ring buffer index + available--; + + return 1; +} + +static uint8_t rx(uint8_t *ch) +{ + if(wlanState != WLAN_DATA_MODE) + return 0; + + return rawRx(ch);} + +static void txN(uint8_t *str, unsigned char number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + if(bytesAvailable() < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + nvic_irq_disable(USART1_IRQn); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + nvic_irq_enable(USART1_IRQn, INTR_PRI, 0); +} + +static uint32_t bytesAvailable() +{ + return available; +} + +uint32_t checkReadyToSend() { + + if(checkCmdModeEnabled()) + { + return false; + } + else + { + return (wlanState == WLAN_INIT_CMD_MODE)? false:true; + } +} +void enableWLANCommandMode() +{ /* To enable command mode, the escape character (default: $) needs to be sent 3 times. + * Additionally, both before and after that sequence there should be 250ms without data sent to the module + * Since the configuration mode is supposed to be used as a simple testing tool, + * there is no check for the time span before the write. If the switching fails due to that, + * an error will be returned upon attempted command execution, just try to reenter command mode then. + */ + wlanState = WLAN_CMD_MODE; // Block external write sources + + clearBuffers(); + rawTx('$'); // txN doesn't work, as WLAN_CMD_MODE prevents tx (which txN calls) from writing to the buffer) + rawTx('$'); + rawTx('$'); + wlanState = WLAN_INIT_CMD_MODE; // Block all writes + cmdEnabledTime = systick_getTick(); +} + +uint32_t checkCmdModeEnabled() +{ + if(wlanState == WLAN_CMD_MODE) + return true; + else if(wlanState == WLAN_DATA_MODE) + return false; + + uint8_t reply[4] = { 0 }; // expected reply: {'C','M','D'}, we're appending \0 so we have a NULL-terminated string that we can use in strcmp() + if(rxN(reply, 3)) + { + if(strcmp((const char *)reply, "CMD") == 0) + { + wlanState = WLAN_CMD_MODE; + return true; + } + else + { // Unexpected answer - going back to data mode + wlanState = WLAN_DATA_MODE; + return false; + } + } + else + { + if(timeSince(cmdEnabledTime) > 350) // 250 ms from chip spec + 100ms, just to be safe + { // Too much time passed since attempted cmd mode switching happened - assuming it failed + wlanState = WLAN_DATA_MODE; + return false; + } + else + { // Not enough time passed, we're not in command mode yet but we're still giving the chip time + return false; + } + } +} + +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value) +{ + switch(cmd) + { + case BUFFER_CLEAR: + cmdBufferSize = 0; + break; + case BUFFER_WRITE: + while((value & 0xFF) != CMDBUFFER_END_CHAR) + { + if(cmdBufferSize == WLAN_CMD_BUFFER_SIZE) + { + if((value & 0xFF) != 0) // Any value still remaining -> too much data for buffer -> return an error + return 1; + break; + } + cmdBuffer[cmdBufferSize] = value & 0xFF; + value >>= 8; + cmdBufferSize++; + } + break; + case BUFFER_EXECUTE: + // Abort if not in command mode. IDE/User should switch to command mode before executing + if(!checkCmdModeEnabled()) + return 1; + + for(uint32_t i = 0; i < cmdBufferSize; i++) + rawTx(cmdBuffer[i]); // Can't use txN since its blocked from sending while in command mode + rawTx('\r'); // End of command character + + cmdBufferSize = 0; + break; + } + + return 0; +} + +uint32_t getCMDReply() +{ + uint8_t cmdReply; + uint32_t result = 0; + + for(uint8_t i = 0; i < 4; i++) + { + if(rawRx(&cmdReply) == 0) + cmdReply = 0; + // First character is in the smallest byte of result + result |= cmdReply << 24; + result >>= 8; + } + + return result; +} diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h new file mode 100644 index 0000000..fd4783a --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h @@ -0,0 +1,191 @@ +/*! + \file usb_conf.h + \brief USB core driver basic configuration + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include +#include "gd32f4xx.h" + +#define USE_USB_FS + +/* USB Core and PHY interface configuration */ + +/****************** USB FS PHY CONFIGURATION ******************************* + * The USB FS Core supports one on-chip Full Speed PHY. + * The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor + * when FS core is used. +*******************************************************************************/ + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif /* USE_USB_FS */ + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif /* USE_USB_HS */ + +/******************************************************************************* + * FIFO Size Configuration in Device mode + * + * (i) Receive data FIFO size = RAM for setup packets + + * OUT endpoint control information + + * data OUT packets + miscellaneous + * Space = ONE 32-bits words + * --> RAM for setup packets = 10 spaces + * (n is the nbr of CTRL EPs the device core supports) + * --> OUT EP CTRL info = 1 space + * (one space for status information written to the FIFO along with each + * received packet) + * --> Data OUT packets = (Largest Packet Size / 4) + 1 spaces + * (MINIMUM to receive packets) + * --> OR data OUT packets = at least 2* (Largest Packet Size / 4) + 1 spaces + * (if high-bandwidth EP is enabled or multiple isochronous EPs) + * --> Miscellaneous = 1 space per OUT EP + * (one space for transfer complete status information also pushed to the + * FIFO with each endpoint's last packet) + * + * (ii) MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for + * that particular IN EP. More space allocated in the IN EP Tx FIFO results + * in a better performance on the USB and can hide latencies on the AHB. + * + * (iii) TXn min size = 16 words. (n:Transmit FIFO index) + * + * (iv) When a TxFIFO is not used, the Configuration should be as follows: + * case 1: n > m and Txn is not used (n,m:Transmit FIFO indexes) + * --> Txm can use the space allocated for Txn. + * case 2: n < m and Txn is not used (n,m:Transmit FIFO indexes) + * --> Txn should be configured with the minimum space of 16 words + * + * (v) The FIFO is used optimally when used TxFIFOs are allocated in the top + * of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + * + * (vi) In HS case12 FIFO locations should be reserved for internal DMA registers + * so total FIFO size should be 1012 Only instead of 1024 +*******************************************************************************/ + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 64 + #define TX2_FIFO_FS_SIZE 64 + #define TX3_FIFO_FS_SIZE 0 + + #define USBFS_SOF_OUTPUT 0 + #define USBFS_LOW_POWER 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 128 + #define TX2_FIFO_HS_SIZE 128 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_EMBEDDED_PHY_ENABLED + #endif + +// #define USB_HS_INTERNAL_DMA_ENABLED +// #define USB_HS_DEDICATED_EP1_ENABLED + + #define USBHS_SOF_OUTPUT 0 + #define USBHS_LOW_POWER 0 +#endif /* USB_HS_CORE */ + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined!" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined!" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined!" + #endif +#endif + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN + #else + #define __ALIGN_END + + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__)/* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __packed + #define __packed __attribute__ ((__packed__)) + #endif +#elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned +#endif /* __CC_ARM */ + +#endif /* __USB_CONF_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h new file mode 100644 index 0000000..d70a738 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h @@ -0,0 +1,74 @@ +/*! + \file usbd_conf.h + \brief the header file of USB device configuration + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CONF_H +#define __USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 + +#define CDC_COM_INTERFACE 0 + +#define USB_STR_DESC_MAX_SIZE 255 + +#define CDC_DATA_IN_EP EP1_IN /* EP1 for data IN */ +#define CDC_DATA_OUT_EP EP3_OUT /* EP3 for data OUT */ +#define CDC_CMD_EP EP2_IN /* EP2 for CDC commands */ + +#define USB_STRING_COUNT 4 + +#define USB_CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ + +#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer: + APP_RX_DATA_SIZE*8 / MAX_BAUDARATE * 1000 should be > CDC_IN_FRAME_INTERVAL*8 */ + +/* CDC endpoints parameters: you can fine tune these values depending on the needed baud rate and performance */ +#ifdef USE_USB_HS + #ifdef USE_ULPI_PHY + #define USB_CDC_DATA_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 40 /* Number of micro-frames between IN transfers */ + #else + #define USB_CDC_DATA_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ + #endif +#else + #define USB_CDC_DATA_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ +#endif /* USE_USB_HS */ + +#endif /* __USBD_CONF_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/RS232.h b/Clean_TMC2209/lib/tmc/hal/RS232.h new file mode 100644 index 0000000..26956e3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/RS232.h @@ -0,0 +1,17 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __RS232_H_ + #define __RS232_H_ + + #include "RXTX.h" + + extern RXTXTypeDef RS232; + +#endif /* __RS232_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/RXTX.h b/Clean_TMC2209/lib/tmc/hal/RXTX.h new file mode 100644 index 0000000..d697ddd --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/RXTX.h @@ -0,0 +1,49 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef RXTX_H_ +#define RXTX_H_ + +#include "tmc/helpers/API_Header.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +typedef enum { + UART0_INTERRUPT_UART, + UART0_INTERRUPT_WLAN +} UART0_Interrupt; +extern UART0_Interrupt uart0_interrupt; +#endif + +typedef struct +{ + void (*init)(); + void (*deInit)(void); + void (*tx)(uint8_t ch); + uint8_t (*rx)(uint8_t *ch); + void (*txN)(uint8_t *ch, unsigned char number); + uint8_t (*rxN)(uint8_t *ch, unsigned char number); + void (*clearBuffers)(void); + uint32_t (*bytesAvailable)(void); + uint32_t baudRate; +} RXTXTypeDef; + +typedef struct +{ + uint32_t read; + uint32_t wrote; + volatile uint8_t *buffer; +} BufferingTypeDef; + +typedef struct +{ + BufferingTypeDef tx; + BufferingTypeDef rx; +} RXTXBufferingTypeDef; + +#endif /* RXTX_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/SPI.h b/Clean_TMC2209/lib/tmc/hal/SPI.h new file mode 100644 index 0000000..1bc50d1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/SPI.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SPI_H +#define SPI_H + + #include "derivative.h" + #include "IOs.h" + + typedef struct + { + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + SPI_MemMapPtr periphery; // pointer to freescale SPI memory base pointer + #elif defined(LandungsbrueckeV3) + uint32_t periphery; // GD32 SPI parameters + #endif + + IOPinTypeDef *CSN; + unsigned char (*readWrite) (unsigned char data, unsigned char lastTransfer); + void (*readWriteArray) (uint8_t *data, size_t length); + void (*reset) (void); + } SPIChannelTypeDef; + + typedef struct + { + SPIChannelTypeDef ch1; + SPIChannelTypeDef ch2; + void (*init) (void); + } SPITypeDef; + + extern SPITypeDef SPI; + + uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel); + uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency); + + uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel); + bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode); + + // read/write 32 bit value at address + int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address); + void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value); + + // for default channels + uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer); + // for TM02 + uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); + + + int32_t spi_ch1_readInt(uint8_t address); + void spi_ch1_writeInt(uint8_t address, int32_t value); + + int32_t spi_ch2_readInt(uint8_t address); + void spi_ch2_writeInt(uint8_t address, int32_t value); + +#endif /* SPI_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/SysTick.h b/Clean_TMC2209/lib/tmc/hal/SysTick.h new file mode 100644 index 0000000..a496f94 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/SysTick.h @@ -0,0 +1,25 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SysTick_H +#define SysTick_H + + #include "tmc/helpers/API_Header.h" + + void systick_init(); + uint32_t systick_getTick(); + void wait(uint32_t delay); + uint32_t timeSince(uint32_t tick); + uint32_t timeDiff(uint32_t newTick, uint32_t oldTick); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + uint32_t systick_getMicrosecondTick(); +#endif + +#endif /* SysTick_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/Timer.h b/Clean_TMC2209/lib/tmc/hal/Timer.h new file mode 100644 index 0000000..c8385f8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/Timer.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TIMER_H_ +#define TIMER_H_ + +#include "derivative.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +#define TIMER_MAX 8000 +#elif defined(LandungsbrueckeV3) +#define TIMER_MAX 65535 +#endif + +typedef enum { + TIMER_CHANNEL_1, + TIMER_CHANNEL_2, + TIMER_CHANNEL_3, + TIMER_CHANNEL_4, + TIMER_CHANNEL_5 +} timer_channel; + +typedef struct +{ + bool initialized; + void (*init) (void); + void (*deInit) (void); + void (*setDuty) (timer_channel channel, float duty); + float (*getDuty) (timer_channel channel); + void (*setPeriod) (timer_channel channel, uint16_t period); + uint16_t (*getPeriod) (timer_channel channel); + void (*setPeriodMin) (timer_channel channel, uint16_t period_min); + void (*setFrequency) (timer_channel channel, float freq); + void (*setFrequencyMin) (timer_channel channel, float freq_min); + void (*overflow_callback) (timer_channel channel); +} TimerTypeDef; + +extern TimerTypeDef Timer; + +#endif /* TIMER_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/UART.h b/Clean_TMC2209/lib/tmc/hal/UART.h new file mode 100644 index 0000000..3a168bb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/UART.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __UART_H_ +#define __UART_H_ + +#include "RXTX.h" + +// Switchable UART pin configuration due to pinout changes in TMC2208 v1.2 -> TMC2208 v1.3 aswell as TMC2209 +typedef enum { + UART_PINS_1, // Default UART pinout (<= TMC2208 v1.2, UART_TXD = DIO17, UART_RXD = DIO18) + UART_PINS_2 // Alternate UART pinout (>= TMC2208 v1.3, UART_TXD = DIO10, UART_RXD = DIO11) +} UART_Pins; + +typedef enum { + UART_MODE_DUAL_WIRE, + UART_MODE_SINGLE_WIRE, + UART_MODE_DUAL_WIRE_PushPull, // Use PushPull for TX instead of OpenDrain +} UART_Mode; + +typedef struct { + UART_Pins pinout; + UART_Mode mode; + RXTXTypeDef rxtx; +} UART_Config; + +extern UART_Config UART; + +void UART0_RX_TX_IRQHandler_UART(void); +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength); +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value); +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value); +void UART_setEnabled(UART_Config *channel, uint8_t enabled); + +#endif /* __UART_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/USB.h b/Clean_TMC2209/lib/tmc/hal/USB.h new file mode 100644 index 0000000..1378ff9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/USB.h @@ -0,0 +1,16 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __USB_H + #define __USB_H + + #include "RXTX.h" + extern RXTXTypeDef USB; + +#endif /* __USB_H */ diff --git a/Clean_TMC2209/lib/tmc/hal/WLAN.h b/Clean_TMC2209/lib/tmc/hal/WLAN.h new file mode 100644 index 0000000..5133e98 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/WLAN.h @@ -0,0 +1,38 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __WLAN_H_ +#define __WLAN_H_ + +#include "RXTX.h" + +extern RXTXTypeDef WLAN; + +typedef enum +{ + BUFFER_CLEAR, + BUFFER_WRITE, + BUFFER_EXECUTE +} BufferCommandTypedef; + +typedef enum +{ + WLAN_INIT_CMD_MODE, // wait time inbetween sending $$$ and entering command mode - writing is disabled completely. rx doesn't read out data - we enter this mode only after a clearBuffer() anyways + WLAN_CMD_MODE, // Command mode - writing is disabled for the HAL tx function, rawTx still writes. rx doesn't read out data, rawRx does + WLAN_DATA_MODE // Data mode - HAL tx/rx functions works normally +} WLANStateTypedef; + +void UART0_RX_TX_IRQHandler_WLAN(void); +uint32_t checkReadyToSend(); +void enableWLANCommandMode(); +uint32_t checkCmdModeEnabled(); +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value); +uint32_t getCMDReply(); + +#endif /* __WLAN_H_ */ diff --git a/Clean_TMC2209/lib/tmc/hal/derivative.h b/Clean_TMC2209/lib/tmc/hal/derivative.h new file mode 100644 index 0000000..d1a7094 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/hal/derivative.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _DERIVATIVE_H_ + #define _DERIVATIVE_H_ + +/* This is purely for the Eclipse parsing. + * while working on Board-specific code you can + * select one of the two boards here. + * The Build process already selects one via makefile & makeFor.h files, + * this choice will therefore not influence the build process. + */ +#if !defined(Landungsbruecke) && !defined(LandungsbrueckeV3) && !defined(LandungsbrueckeSmall) +#warning "No Board selected by makefile, defining one for debug purposes" +//#define Landungsbruecke +// #define LandungsbrueckeV3 +//#define LandungsbrueckeSmall +#endif + + #include "tmc/helpers/API_Header.h" + + #if defined(Landungsbruecke) + #define MODULE_ID "0012" + #include + #include "hal/Landungsbruecke/freescale/Cpu.h" + #include "hal/Landungsbruecke/freescale/nvic.h" + #define CPU_LITTLE_ENDIAN + #define __MK_xxx_H__ + #elif defined(LandungsbrueckeV3) + #define MODULE_ID "0026" + #include "gd32f4xx.h" + #elif defined(LandungsbrueckeSmall) + // The Landungsbruecke (Small) is a normal Landungsbruecke but with a MK20DX256VLL10 µC instead. + // This other µC has less memory. We assign a different module ID, otherwise the functionality + // is identical to the normal Landungsbruecke. + #define MODULE_ID "0016" + #include + #include "hal/Landungsbruecke/freescale/Cpu.h" + #include "hal/Landungsbruecke/freescale/nvic.h" + #define CPU_LITTLE_ENDIAN + #define __MK_xxx_H__ + #else + #error "No Board selected" + #endif + +#endif /* _DERIVATIVE_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/API_Header.h b/Clean_TMC2209/lib/tmc/helpers/API_Header.h new file mode 100644 index 0000000..03c3619 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/API_Header.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_API_HEADER_H_ +#define TMC_API_HEADER_H_ + +#include "Config.h" +#include "Macros.h" +#include "Constants.h" +#include "Bits.h" +#include "CRC.h" +#include "RegisterAccess.h" +#include +#include "Types.h" + +// TODO: Restructure these. +/* + * Goal: Just give these values here as status back to the IDE when used with EvalSystem. + * Currently, this is obtained by just leaving out implementation specific error bits here. + */ +typedef enum { + TMC_ERROR_NONE = 0x00, + TMC_ERROR_GENERIC = 0x01, + TMC_ERROR_FUNCTION = 0x02, + TMC_ERROR_MOTOR = 0x08, + TMC_ERROR_VALUE = 0x10, + TMC_ERROR_CHIP = 0x40 +} TMCError; + +typedef enum { + TMC_COMM_DEFAULT, + TMC_COMM_SPI, + TMC_COMM_UART +} TMC_Comm_Mode; + +#endif /* TMC_API_HEADER_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Bits.h b/Clean_TMC2209/lib/tmc/helpers/Bits.h new file mode 100644 index 0000000..c5be24c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Bits.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +// BIT DEFINITION +#ifndef TMC_BITS_H_ +#define TMC_BITS_H_ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define BYTE0_MASK 0x00000000000000FF +#define BYTE0_SHIFT 0 +#define BYTE1_MASK 0x000000000000FF00 +#define BYTE1_SHIFT 8 +#define BYTE2_MASK 0x0000000000FF0000 +#define BYTE2_SHIFT 16 +#define BYTE3_MASK 0x00000000FF000000 +#define BYTE3_SHIFT 24 +#define BYTE4_MASK 0x000000FF00000000 +#define BYTE4_SHIFT 32 +#define BYTE5_MASK 0x0000FF0000000000 +#define BYTE5_SHIFT 40 +#define BYTE6_MASK 0x00FF000000000000 +#define BYTE6_SHIFT 48 +#define BYTE7_MASK 0xFF00000000000000 +#define BYTE7_SHIFT 56 + +#define SHORT0_MASK (BYTE0_MASK|BYTE1_MASK) +#define SHORT0_SHIFT BYTE0_SHIFT +#define SHORT1_MASK (BYTE2_MASK|BYTE3_MASK) +#define SHORT1_SHIFT BYTE2_SHIFT +#define SHORT2_MASK (BYTE4_MASK|BYTE5_MASK) +#define SHORT2_SHIFT BYTE4_SHIFT +#define SHORT3_MASK (BYTE6_MASK|BYTE7_MASK) +#define SHORT3_SHIFT BYTE6_SHIFT + +#define WORD0_MASK (SHORT0_MASK|SHORT1_MASK) +#define WORD0_SHIFT SHORT0_SHIFT +#define WORD1_MASK (SHORT2_MASK|SHORT3_MASK) +#define WORD1_SHIFT SHORT2_SHIFT + +#define NIBBLE(value, n) (((value) >> ((n) << 2)) & 0x0F) +#define BYTE(value, n) (((value) >> ((n) << 3)) & 0xFF) +#define SHORT(value, n) (((value) >> ((n) << 4)) & 0xFFFF) +#define WORD(value, n) (((value) >> ((n) << 5)) & 0xFFFFFFFF) + +#define _8_16(__1, __0) (((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) + +#define _8_32(__3, __2, __1, __0) (((__3) << BYTE3_SHIFT) | ((__2) << BYTE2_SHIFT) | ((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) +#define _16_32(__1, __0) (((__1) << SHORT1_SHIFT) | ((__0) << SHORT0_SHIFT)) + +#define _8_64(__7, __6, __5, __4, __3, __2, __1, __0) (((__7) << BYTE7_SHIFT) | ((__6) << BYTE6_SHIFT) | ((__5) << BYTE5_SHIFT) | ((__4) << BYTE4_SHIFT) | ((__3) << BYTE3_SHIFT) | ((__2) << BYTE2_SHIFT) | ((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) +#define _16_64(__3, __2, __1, __0) (((__3) << SHORT3_SHIFT) | ((__2) << SHORT2_SHIFT) | ((__1) << SHORT1_SHIFT) | ((__0) << SHORT0_SHIFT)) +#define _32_64(__1, __0) (((__1) << WORD1_SHIFT) | ((__0) << WORD0_SHIFT)) + +#endif /* TMC_BITS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/CRC.c b/Clean_TMC2209/lib/tmc/helpers/CRC.c new file mode 100644 index 0000000..c796ff9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/CRC.c @@ -0,0 +1,214 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * This is a generic implementation for a CRC8 generator supporting + * both compile-time (1) and run-time initialized Lookup tables for efficient CRC8 calculation. + * You can store multiple tables for different polynomials and (non-)reflected CRCs. + * The different tables are referenced by an index, with an upper limit set at compile time (CRC_TABLE_COUNT). + * + * To generate CRCs you must first generate the Lookup-table by calling fillCRCTable() + * with any index. CRCs can then be generated from any data buffer by calling CRC() + * with the same index previously given to fillCRCTable(). + * + * The table generation has been optimized for speed so that the runtime + * table generation can even be done during normal operation if required. + * However, as long as the required polynomials are known on initialization, + * the table generation should be done at that time. + * On the Landungsbruecke the initialization of a CRC table takes ~250µs. (2) + * Should your application still have problems with the table calculation time, + * this algorithm could probably be speed up by preparing a 2- or 4-bit lookup table + * to speed up the actual table generation. + * + * (1): For compile-time CRC tables, just fill the table(s) by initializing CRCTables[] to the proper values. + * (2): Tested by toggling a GPIO pin, generating a table in-between and measuring the GPIO pulse width. + */ + +#include "CRC.h" + +typedef struct { + uint8_t table[256]; + uint8_t polynomial; + bool isReflected; +} CRCTypeDef; + +CRCTypeDef CRCTables[CRC_TABLE_COUNT] = { 0 }; + +static uint8_t flipByte(uint8_t value); +static uint32_t flipBitsInBytes(uint32_t value); + +/* This function generates the Lookup table used for CRC calculations. + * + * Arguments: + * uint8_t polynomial: The CRC polynomial for which the table will be generated. + * bool isReflected: Indicator whether the CRC table will be reflected or not. + * uint8_t index: The index of the table to be filled. + * + * How it works: + * A CRC calculation of a byte can be done by taking the byte to be CRC'd, + * shifting it left by one (appending a 0) and - if a 1 has been shifted out - + * XOR-ing in the CRC polynomial. After 8 iterations the result will be the + * CRC of the Byte. + * + * The function below does this in a compact way, by using all 4 bytes of a + * uint32_t to do 4 separate CRC bytes at once. + * For this to work without the Byte shifting interfering with adjacent bytes, + * the polynomial has the 8th bit (0x100) set. That way, if the shifted-out bit + * is 1, the following XOR-ing with the CRC polynomial will set that 1 to a 0, + * resulting in the shifted-in 0 for the adjacent byte. + * This process will go from the the lowest to the highest byte, resulting in + * fully independent byte-wise CRC calculations. For the highest byte, the value + * of the shifted-out byte needs to be stored before shifting the bytes (isMSBSet). + * + * The for-loop that iterates over all uint8_t values starts out with the + * uint8_t values 3 to 0 stored in one uint32_t: 0x03020100 + * for each iteration each uint8_t value will increase by 4.. + * 0 -> 4 -> 8 -> C -> ... + * 1 -> 5 -> 9 -> D -> ... + * 2 -> 6 -> A -> E -> ... + * 3 -> 7 -> B -> F -> ... + * ..resulting in an increase of the uint32_t by 0x04040404: + * 0x03020100 -> 0x07060504 -> 0x0B0A0908 -> 0x0F0E0D0C -> ... + * The loop ends as soon as we have iterated over all uint8_t values. + * We detect that by looking for the byte-wise overflow into the next byte: + * 0xFFFEFDFC <- last uint32_t value to be calculated + * 0xFF, 0xFE, 0xFD, 0xFC <- the corresponding uint8_t values + * 0x103, 0x102, 0x101, 0x100 <- incremented uint8_t values (overflow into the next byte!) + * 0x04030200 <- uint32_t value with the overflowed bytes + * + * We have the lower uint8_t values at the lower bytes of the uint32_t. + * This allows us to simply store the lowest byte of the uint32_t, + * right-shift the uint32_t by 8 and increment the table pointer. + * After 4 iterations of that all 4 bytes of the uint32_t are stored in the table. + */ +uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index) +{ + uint32_t CRCdata; + // Helper pointer for traversing the result table + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + CRCTables[index].polynomial = polynomial; + CRCTables[index].isReflected = isReflected; + table = &CRCTables[index].table[0]; + + // Extend the polynomial to correct byte MSBs shifting into next bytes + uint32_t poly = (uint32_t) polynomial | 0x0100; + + // Iterate over all 256 possible uint8_t values, compressed into a uint32_t (see detailed explanation above) + uint32_t i; + for(i = 0x03020100; i != 0x04030200; i+=0x04040404) + { + // For reflected table: Flip the bits of each input byte + CRCdata = (isReflected)? flipBitsInBytes(i) : i; + + // Iterate over 8 Bits + int j; + for(j = 0; j < 8; j++) + { + // Store value of soon-to-be shifted out byte + uint8_t isMSBSet = (CRCdata & 0x80000000)? 1:0; + + // CRC Shift + CRCdata <<= 1; + + // XOR the bytes when required, lowest to highest + CRCdata ^= (CRCdata & 0x00000100)? (poly ) : 0; + CRCdata ^= (CRCdata & 0x00010000)? (poly << 8 ) : 0; + CRCdata ^= (CRCdata & 0x01000000)? (poly << 16) : 0; + CRCdata ^= (isMSBSet)? (poly << 24) : 0; + } + + // For reflected table: Flip the bits of each output byte + CRCdata = (isReflected)? flipBitsInBytes(CRCdata) : CRCdata; + // Store the CRC result bytes in the table array + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + } + + return 1; +} + +/* This function calculates the CRC from a data buffer + * + * Arguments: + * uint8_t *data: A pointer to the data that will be CRC'd. + * uint32_t bytes: The length of the data buffer. + * uint8_t index: The index of the CRC table to be used. + */ +uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index) +{ + uint8_t result = 0; + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + table = &CRCTables[index].table[0]; + + while(bytes--) + result = table[result ^ *data++]; + + return (CRCTables[index].isReflected)? flipByte(result) : result; +} + +uint8_t tmc_tableGetPolynomial(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return 0; + + return CRCTables[index].polynomial; +} + +bool tmc_tableIsReflected(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return false; + + return CRCTables[index].isReflected; +} + +// Helper functions +static uint8_t flipByte(uint8_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55) | ((value & 0x55) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33) | ((value & 0x33) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F) | ((value & 0x0F) << 4); + + return value; +} + +/* This helper function switches all bits within each byte. + * The byte order remains the same: + * [b31 b30 b29 b28 b27 b26 b25 b24 .. b7 b6 b5 b4 b3 b2 b1 b0] + * || + * \||/ + * \/ + * [b24 b25 b26 b27 b28 b29 b30 b31 .. b0 b1 b2 b3 b4 b5 b6 b7] + */ +static uint32_t flipBitsInBytes(uint32_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55555555) | ((value & 0x55555555) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33333333) | ((value & 0x33333333) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F0F0F0F) | ((value & 0x0F0F0F0F) << 4); + + return value; +} diff --git a/Clean_TMC2209/lib/tmc/helpers/CRC.h b/Clean_TMC2209/lib/tmc/helpers/CRC.h new file mode 100644 index 0000000..21988d9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/CRC.h @@ -0,0 +1,25 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CRC_H_ +#define TMC_HELPERS_CRC_H_ + + #include "Types.h" + + // Amount of CRC tables available + // Each table takes ~260 bytes (257 bytes, one bool and structure padding) + #define CRC_TABLE_COUNT 2 + + uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index); + uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index); + + uint8_t tmc_tableGetPolynomial(uint8_t index); + bool tmc_tableIsReflected(uint8_t index); + +#endif /* TMC_HELPERS_CRC_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Config.h b/Clean_TMC2209/lib/tmc/helpers/Config.h new file mode 100644 index 0000000..156d9f5 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Config.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CONFIG_H_ +#define TMC_HELPERS_CONFIG_H_ + +#include "Constants.h" +#include "Types.h" + +// Callback functions have IC-dependent parameters +// To store the function pointers we use this dummy type, which is never +// called without casting it to the IC-specific type first. +// (Casting between function pointers is allowed by the C standard) +typedef void (*tmc_callback_config)(void); + +// States of a configuration +typedef enum { + CONFIG_READY, + CONFIG_RESET, + CONFIG_RESTORE +} ConfigState; + +// structure for configuration mechanism +typedef struct +{ + ConfigState state; + uint8_t configIndex; + int32_t shadowRegister[TMC_REGISTER_COUNT]; + uint8_t (*reset) (void); + uint8_t (*restore) (void); + tmc_callback_config callback; + uint8_t channel; +} ConfigurationTypeDef; + +#endif /* TMC_HELPERS_CONFIG_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Constants.h b/Clean_TMC2209/lib/tmc/helpers/Constants.h new file mode 100644 index 0000000..fdcd776 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Constants.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CONSTANTS_H_ +#define TMC_HELPERS_CONSTANTS_H_ + +#define TMC_WRITE_BIT 0x80 + +#define TMC_ADDRESS_MASK 0x7F + +#define TMC_DEFAULT_MOTOR 0 + +//#define TMC_DIRECTION_RIGHT TRUE +//#define TMC_DIRECTION_LEFT FALSE + +#define TMC_REGISTER_COUNT 128 // Default register count + +#endif /* TMC_HELPERS_CONSTANTS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Functions.c b/Clean_TMC2209/lib/tmc/helpers/Functions.c new file mode 100644 index 0000000..764102e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Functions.c @@ -0,0 +1,173 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Functions.h" + +int32_t tmc_limitInt(int32_t value, int32_t min, int32_t max) +{ + if (value > max) + return max; + else if (value < min) + return min; + else + return value; +} + +int64_t tmc_limitS64(int64_t value, int64_t min, int64_t max) +{ + if (value > max) + return max; + else if (value < min) + return min; + else + return value; +} + +/* lookup table for square root function */ +static const unsigned char sqrttable[256] = +{ + 0, 16, 22, 27, 32, 35, 39, 42, 45, 48, 50, 53, 55, 57, 59, 61, + 64, 65, 67, 69, 71, 73, 75, 76, 78, 80, 81, 83, 84, 86, 87, 89, + 90, 91, 93, 94, 96, 97, 98, 99, 101, 102, 103, 104, 106, 107, 108, 109, + 110, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, + 128, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, + 143, 144, 144, 145, 146, 147, 148, 149, 150, 150, 151, 152, 153, 154, 155, 155, + 156, 157, 158, 159, 160, 160, 161, 162, 163, 163, 164, 165, 166, 167, 167, 168, + 169, 170, 170, 171, 172, 173, 173, 174, 175, 176, 176, 177, 178, 178, 179, 180, + 181, 181, 182, 183, 183, 184, 185, 185, 186, 187, 187, 188, 189, 189, 190, 191, + 192, 192, 193, 193, 194, 195, 195, 196, 197, 197, 198, 199, 199, 200, 201, 201, + 202, 203, 203, 204, 204, 205, 206, 206, 207, 208, 208, 209, 209, 210, 211, 211, + 212, 212, 213, 214, 214, 215, 215, 216, 217, 217, 218, 218, 219, 219, 220, 221, + 221, 222, 222, 223, 224, 224, 225, 225, 226, 226, 227, 227, 228, 229, 229, 230, + 230, 231, 231, 232, 232, 233, 234, 234, 235, 235, 236, 236, 237, 237, 238, 238, + 239, 240, 240, 241, 241, 242, 242, 243, 243, 244, 244, 245, 245, 246, 246, 247, + 247, 248, 248, 249, 249, 250, 250, 251, 251, 252, 252, 253, 253, 254, 254, 255 +}; + +int32_t tmc_sqrti(int32_t x) +{ + int32_t xn; + + // Negative parameter? + if (x < 0) + return -1; + + if (x < 0x0100) + return (int32_t) sqrttable[x] >> 4; + + if (x >= 0x00010000) + { + if (x >= 0x01000000) + { + if (x >= 0x10000000) + { + if (x >= 0x40000000) + { + // 0x40000000 <= x < 0x7FFFFFFF + xn = (int32_t) sqrttable[x >> 24] << 8; + } + else + { + // 0x10000000 <= x < 0x40000000 + xn = (int32_t) sqrttable[x >> 22] << 7; + } + } + else + { + if (x >= 0x04000000) + { + // 0x04000000 <= x < 0x10000000 + xn = (int32_t) sqrttable[x >> 20] << 6; + } + else + { + // 0x01000000 <= x < 0x04000000 + xn = (int32_t) sqrttable[x >> 18] << 5; + } + } + + // Two steps of the babylonian method + xn = (xn + 1 + (x / xn)) >> 1; + xn = (xn + 1 + (x / xn)) >> 1; + } + else + { + if (x >= 0x00100000) + { + if (x >= 0x00400000) + { + // 0x00400000 <= x < 0x01000000 + xn = (int32_t) sqrttable[x >> 16] << 4; + } + else + { + // 0x00100000 <= x < 0x00400000 + xn = (int32_t) sqrttable[x >> 14] << 3; + } + } + else + { + if (x >= 0x00040000) + { + // 0x00040000 <= x < 0x00100000 + xn = (int32_t) sqrttable[x >> 12] << 2; + } + else + { + // 0x00010000 <= x < 0x00040000 + xn = (int32_t) sqrttable[x >> 10] << 1; + } + } + + // One step of the babylonian method + xn = (xn + 1 + (x / xn)) >> 1; + } + } + else + { + if (x >= 0x1000) + { + if (x >= 0x4000) + { + // 0x4000 <= x < 0x00010000 + xn = (int32_t) (sqrttable[x >> 8] ) + 1; + } + else + { + // 0x1000 <= x < 0x4000 + xn = (int32_t) (sqrttable[x >> 6] >> 1) + 1; + } + } + else + { + if (x >= 0x0400) + { + // 0x0400 <= x < 0x1000 + xn = (int32_t) (sqrttable[x >> 4] >> 2) + 1; + } + else + { + // 0x0100 <= x < 0x0400 + xn = (int32_t) (sqrttable[x >> 2] >> 3) + 1; + } + } + } + + // Make sure that our result is floored + if ((xn * xn) > x) + xn--; + + return xn; +} + +int32_t tmc_filterPT1(int64_t *akku, int32_t newValue, int32_t lastValue, uint8_t actualFilter, uint8_t maxFilter) +{ + *akku += (newValue-lastValue) << (maxFilter-actualFilter); + return *akku >> maxFilter; +} diff --git a/Clean_TMC2209/lib/tmc/helpers/Functions.h b/Clean_TMC2209/lib/tmc/helpers/Functions.h new file mode 100644 index 0000000..af92303 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Functions.h @@ -0,0 +1,20 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_FUNCTIONS_H_ +#define TMC_FUNCTIONS_H_ + +#include "API_Header.h" + +int32_t tmc_limitInt(int32_t value, int32_t min, int32_t max); +int64_t tmc_limitS64(int64_t value, int64_t min, int64_t max); +int32_t tmc_sqrti(int32_t x); +int32_t tmc_filterPT1(int64_t *akku, int32_t newValue, int32_t lastValue, uint8_t actualFilter, uint8_t maxFilter); + +#endif /* TMC_FUNCTIONS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Macros.h b/Clean_TMC2209/lib/tmc/helpers/Macros.h new file mode 100644 index 0000000..2914237 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Macros.h @@ -0,0 +1,59 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_MACROS_H_ +#define TMC_MACROS_H_ + +/* Cast a n bit signed int to a 32 bit signed int + * This is done by checking the MSB of the signed int (Bit n). + * If it is 1, the value is negative and the Bits 32 to n+1 are set to 1 + * If it is 0, the value remains unchanged + */ +#define CAST_Sn_TO_S32(value, n) ((value) | (((value) & ((uint32_t)1<<((n)-1)))? ~(((uint32_t)1<<(n))-1) : 0 )) + +// Min/Max macros +#ifndef MIN + #define MIN(a,b) (((a)<(b)) ? (a) : (b)) +#endif +#ifndef MAX + #define MAX(a,b) (((a)>(b)) ? (a) : (b)) +#endif + +// Static Array length +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#endif + +// Generic mask/shift macros +#define FIELD_GET(data, mask, shift) \ + (((data) & (mask)) >> (shift)) +#define FIELD_SET(data, mask, shift, value) \ + (((data) & (~(mask))) | (((value) << (shift)) & (mask))) + +// Register read/write/update macros using Mask/Shift: +#define FIELD_READ(read, motor, address, mask, shift) \ + FIELD_GET(read(motor, address), mask, shift) +#define FIELD_WRITE(write, motor, address, mask, shift, value) \ + (write(motor, address, ((value)<<(shift)) & (mask))) +#define FIELD_UPDATE(read, write, motor, address, mask, shift, value) \ + (write(motor, address, FIELD_SET(read(motor, address), mask, shift, value))) + +// Macro to surpress unused parameter warnings +#ifndef UNUSED + #define UNUSED(x) (void)(x) +#endif + +// Memory access helpers +// Force the compiler to access a location exactly once +#define ACCESS_ONCE(x) *((volatile typeof(x) *) (&x)) + +// Macro to remove write bit for shadow register array access +#define TMC_ADDRESS(x) ((x) & (TMC_ADDRESS_MASK)) + +#endif /* TMC_MACROS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/helpers/RegisterAccess.h b/Clean_TMC2209/lib/tmc/helpers/RegisterAccess.h new file mode 100644 index 0000000..e0167b3 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/RegisterAccess.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * The permission system aims to allow a general-purpose implementation for + * all common hardware register usages. This includes: + * - Trivial Cases: Read, Write, Read & Write + * + * - Read & Write accesses that route to different values/functions of a chip. + * (e.g. serial communication, where read/write corresponds to RX/TX) + * - Read to clear, write to clear. This does not directly affect the access, + * but can be used to implement a software shadow register for flags + * (ORing the read value into a shadow register instead of overwriting). + * - Registers with default values that are not known (e.g. Factory configuration + * values that should not be overwritten by default). + */ + +#ifndef TMC_HELPERS_REGISTERACCESS_H +#define TMC_HELPERS_REGISTERACCESS_H + +// Register access bits +/* Lower nibble is used for read/write, higher nibble is used for + * special case registers. This makes it easy to identify the read/write + * part of the permissions in a hexadecimal permission number. + * The dirty bit will only ever be set at runtime, so we keep the easily + * readable lower nibble. + */ +#define TMC_ACCESS_NONE 0x00 + +#define TMC_ACCESS_READ 0x01 +#define TMC_ACCESS_WRITE 0x02 + // 0x04 is currently unused +#define TMC_ACCESS_DIRTY 0x08 // Register has been written since reset -> shadow register is valid for restore + +// Special Register bits +#define TMC_ACCESS_RW_SPECIAL 0x10 // Read and write are independent - different values and/or different functions +#define TMC_ACCESS_FLAGS 0x20 // Register has read or write to clear flags. +#define TMC_ACCESS_HW_PRESET 0x40 // Register has hardware presets (e.g. Factory calibrations) - do not write a default value + // 0x80 is currently unused + +// Permission combinations +#define TMC_ACCESS_RW (TMC_ACCESS_READ | TMC_ACCESS_WRITE) // 0x03 - Read and write +#define TMC_ACCESS_RW_SEPARATE (TMC_ACCESS_RW | TMC_ACCESS_RW_SPECIAL) // 0x13 - Read and write, with separate values/functions +#define TMC_ACCESS_R_FLAGS (TMC_ACCESS_READ | TMC_ACCESS_FLAGS) // 0x21 - Read, has flags (read to clear) +#define TMC_ACCESS_RW_FLAGS (TMC_ACCESS_RW | TMC_ACCESS_FLAGS) // 0x23 - Read and write, has flags (read or write to clear) +#define TMC_ACCESS_W_PRESET (TMC_ACCESS_WRITE | TMC_ACCESS_HW_PRESET) // 0x42 - Write, has hardware preset - skipped in reset routine +#define TMC_ACCESS_RW_PRESET (TMC_ACCESS_RW | TMC_ACCESS_HW_PRESET) // 0x43 - Read and write, has hardware presets - skipped in reset routine + +// Helper macros +#define TMC_IS_READABLE(x) ((x) & TMC_ACCESS_READ) +#define TMC_IS_WRITABLE(x) ((x) & TMC_ACCESS_WRITE) +#define TMC_IS_DIRTY(x) ((x) & TMC_ACCESS_DIRTY) +#define TMC_IS_PRESET(x) ((x) & TMC_ACCESS_HW_PRESET) +#define TMC_IS_RESETTABLE(x) (((x) & (TMC_ACCESS_W_PRESET)) == TMC_ACCESS_WRITE) // Write bit set, Hardware preset bit not set +#define TMC_IS_RESTORABLE(x) (((x) & TMC_ACCESS_WRITE) && (!(x & TMC_ACCESS_HW_PRESET) || (x & TMC_ACCESS_DIRTY))) // Write bit set, if it's a hardware preset register, it needs to be dirty + +// Struct for listing registers that have constant contents which we cannot +// obtain by reading them due to the register not being read-back. +typedef struct +{ + uint8_t address; + uint32_t value; +} TMCRegisterConstant; + +// Helper define: +// Most register permission arrays are initialized with 128 values. +// In those fields its quite hard to have an easy overview of available +// registers. For that, ____ is defined to 0, since 4 underscores are +// very easy to distinguish from the 2-digit hexadecimal values. +// This way, the used registers (permission != ACCESS_NONE) are easily spotted +// amongst unused (permission == ACCESS_NONE) registers. +#define ____ 0x00 + +// Helper define: +// Default reset values are not used if the corresponding register has a +// hardware preset. Since this is not directly visible in the default +// register reset values array, N_A is used as an indicator for a preset +// value, where any value will be ignored anyways (N_A: not available). +#define N_A 0 + +#endif /* TMC_HELPERS_REGISTERACCESS_H */ diff --git a/Clean_TMC2209/lib/tmc/helpers/Types.h b/Clean_TMC2209/lib/tmc/helpers/Types.h new file mode 100644 index 0000000..fccb079 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/helpers/Types.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +// Turn off the integer typedefs by uncommenting the following two defines. +// If your IDE (e.g. Arduino IDE) already defines these types, deactivating +// these typedefs will fix errors and/or warnings. +//#define TMC_SKIP_UINT_TYPEDEFS // Disable u8, u16, u32, uint8, uint16 and uint32 typedefs +//#define TMC_SKIP_INT_TYPEDEFS // Disable s8, s16, s32, int8, int16 and int32 typedefs + +#ifndef TMC_TYPES_H_ +#define TMC_TYPES_H_ + +#include +#include +#include + +#ifndef TMC_TYPES_INTEGERS +#define TMC_TYPES_INTEGERS + +// todo: change to standard ISO C99 types (ED) + +// www.open-std.org/JTC1/SC22/WG14/www/docs/n1256.pdf +// ISO C99: 7.18 Integer types 8, 16, 32, or 64 bits +// intN_t = two’s complement signed integer type with width N, no padding bits. +// uintN_t = an unsigned integer type with width N. +// floatN_t = N bit IEE 754 float. +// INT8_MIN, INT8_MAX, INT16_MIN, INT16_MAX, INT32_MIN, INT32_MAX, .... UINT32_MAX + +typedef float float32_t; +typedef double float64_t; + +#ifndef TMC_TYPES_INTEGERS_UNSIGNED +#define TMC_TYPES_INTEGERS_UNSIGNED + +#ifndef TMC_SKIP_UINT_TYPEDEFS +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +typedef uint8_t uint8; +typedef uint16_t uint16; +typedef uint32_t uint32; +#endif /* TMC_SKIP_UINT_TYPEDEFS */ + +#define u8_MAX (uint8_t) 255 +#define u10_MAX (uint16_t) 1023 +#define u12_MAX (uint16_t) 4095 +#define u15_MAX (uint16_t) 32767 +#define u16_MAX (uint16_t) 65535 +#define u18_MAX (uint32_t) 262143uL +#define u20_MAX (uint32_t) 1048575uL +#define u22_MAX (uint32_t) 4194303uL +#define u24_MAX (uint32_t) 16777215uL +#define u32_MAX (uint32_t) 4294967295uL + +#endif /* TMC_TYPES_INTEGERS_UNSIGNED */ + +#ifndef TMC_TYPES_INTEGERS_SIGNED +#define TMC_TYPES_INTEGERS_SIGNED + +#ifndef TMC_SKIP_INT_TYPEDEFS +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; + +typedef int8_t int8; +typedef int16_t int16; +typedef int32_t int32; +#endif /* TMC_SKIP_INT_TYPEDEFS */ + +#define s8_MAX (int8_t) 127 +#define s8_MIN (int8_t) -128 +#define s16_MAX (int16_t) 32767 +#define s16_MIN (int16_t) -32768 +#define s24_MAX (int32_t) 8388607 +#define s24_MIN (int32_t) -8388608 +#define s32_MAX (int32_t) 2147483647 +#define s32_MIN (int32_t) -2147483648 + +#endif /* TMC_TYPES_INTEGERS_SIGNED */ + +#endif /* TMC_TYPES_INTEGERS */ + +#ifndef TMC_TYPES_NULL +#define TMC_TYPES_NULL + +#ifndef NULL +#define NULL ((void *) 0) +#endif /* NULL */ + +#ifndef FALSE +#define FALSE false +#endif + +#ifndef TRUE +#define TRUE true +#endif + +#endif /* TMC_TYPES_NULL */ + +#endif /* TMC_TYPES_H_ */ diff --git a/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.c b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.c new file mode 100644 index 0000000..7143558 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.c @@ -0,0 +1,492 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMC2209.h" +#include "tmc/hal/UART.h" +#include "tmc/helpers/CRC.h" + + + + + + + + + + +typedef struct { + uint8_t table[256]; + uint8_t polynomial; + bool isReflected; +} CRCTypeDef; + +CRCTypeDef CRCTables[CRC_TABLE_COUNT] = { 0 }; + +static uint8_t flipByte(uint8_t value); +static uint32_t flipBitsInBytes(uint32_t value); + +/* This function generates the Lookup table used for CRC calculations. + * + * Arguments: + * uint8_t polynomial: The CRC polynomial for which the table will be generated. + * bool isReflected: Indicator whether the CRC table will be reflected or not. + * uint8_t index: The index of the table to be filled. + * + * How it works: + * A CRC calculation of a byte can be done by taking the byte to be CRC'd, + * shifting it left by one (appending a 0) and - if a 1 has been shifted out - + * XOR-ing in the CRC polynomial. After 8 iterations the result will be the + * CRC of the Byte. + * + * The function below does this in a compact way, by using all 4 bytes of a + * uint32_t to do 4 separate CRC bytes at once. + * For this to work without the Byte shifting interfering with adjacent bytes, + * the polynomial has the 8th bit (0x100) set. That way, if the shifted-out bit + * is 1, the following XOR-ing with the CRC polynomial will set that 1 to a 0, + * resulting in the shifted-in 0 for the adjacent byte. + * This process will go from the the lowest to the highest byte, resulting in + * fully independent byte-wise CRC calculations. For the highest byte, the value + * of the shifted-out byte needs to be stored before shifting the bytes (isMSBSet). + * + * The for-loop that iterates over all uint8_t values starts out with the + * uint8_t values 3 to 0 stored in one uint32_t: 0x03020100 + * for each iteration each uint8_t value will increase by 4.. + * 0 -> 4 -> 8 -> C -> ... + * 1 -> 5 -> 9 -> D -> ... + * 2 -> 6 -> A -> E -> ... + * 3 -> 7 -> B -> F -> ... + * ..resulting in an increase of the uint32_t by 0x04040404: + * 0x03020100 -> 0x07060504 -> 0x0B0A0908 -> 0x0F0E0D0C -> ... + * The loop ends as soon as we have iterated over all uint8_t values. + * We detect that by looking for the byte-wise overflow into the next byte: + * 0xFFFEFDFC <- last uint32_t value to be calculated + * 0xFF, 0xFE, 0xFD, 0xFC <- the corresponding uint8_t values + * 0x103, 0x102, 0x101, 0x100 <- incremented uint8_t values (overflow into the next byte!) + * 0x04030200 <- uint32_t value with the overflowed bytes + * + * We have the lower uint8_t values at the lower bytes of the uint32_t. + * This allows us to simply store the lowest byte of the uint32_t, + * right-shift the uint32_t by 8 and increment the table pointer. + * After 4 iterations of that all 4 bytes of the uint32_t are stored in the table. + */ +uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index) +{ + uint32_t CRCdata; + // Helper pointer for traversing the result table + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + CRCTables[index].polynomial = polynomial; + CRCTables[index].isReflected = isReflected; + table = &CRCTables[index].table[0]; + + // Extend the polynomial to correct byte MSBs shifting into next bytes + uint32_t poly = (uint32_t) polynomial | 0x0100; + + // Iterate over all 256 possible uint8_t values, compressed into a uint32_t (see detailed explanation above) + uint32_t i; + for(i = 0x03020100; i != 0x04030200; i+=0x04040404) + { + // For reflected table: Flip the bits of each input byte + CRCdata = (isReflected)? flipBitsInBytes(i) : i; + + // Iterate over 8 Bits + int j; + for(j = 0; j < 8; j++) + { + // Store value of soon-to-be shifted out byte + uint8_t isMSBSet = (CRCdata & 0x80000000)? 1:0; + + // CRC Shift + CRCdata <<= 1; + + // XOR the bytes when required, lowest to highest + CRCdata ^= (CRCdata & 0x00000100)? (poly ) : 0; + CRCdata ^= (CRCdata & 0x00010000)? (poly << 8 ) : 0; + CRCdata ^= (CRCdata & 0x01000000)? (poly << 16) : 0; + CRCdata ^= (isMSBSet)? (poly << 24) : 0; + } + + // For reflected table: Flip the bits of each output byte + CRCdata = (isReflected)? flipBitsInBytes(CRCdata) : CRCdata; + // Store the CRC result bytes in the table array + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + } + + return 1; +} + +/* This function calculates the CRC from a data buffer + * + * Arguments: + * uint8_t *data: A pointer to the data that will be CRC'd. + * uint32_t bytes: The length of the data buffer. + * uint8_t index: The index of the CRC table to be used. + */ +uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index) +{ + uint8_t result = 0; + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + table = &CRCTables[index].table[0]; + + while(bytes--) + result = table[result ^ *data++]; + + return (CRCTables[index].isReflected)? flipByte(result) : result; +} + +uint8_t tmc_tableGetPolynomial(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return 0; + + return CRCTables[index].polynomial; +} + +bool tmc_tableIsReflected(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return false; + + return CRCTables[index].isReflected; +} + +// Helper functions +static uint8_t flipByte(uint8_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55) | ((value & 0x55) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33) | ((value & 0x33) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F) | ((value & 0x0F) << 4); + + return value; +} + +/* This helper function switches all bits within each byte. + * The byte order remains the same: + * [b31 b30 b29 b28 b27 b26 b25 b24 .. b7 b6 b5 b4 b3 b2 b1 b0] + * || + * \||/ + * \/ + * [b24 b25 b26 b27 b28 b29 b30 b31 .. b0 b1 b2 b3 b4 b5 b6 b7] + */ +static uint32_t flipBitsInBytes(uint32_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55555555) | ((value & 0x55555555) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33333333) | ((value & 0x33333333) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F0F0F0F) | ((value & 0x0F0F0F0F) << 4); + + return value; +} + + + + + + + + + + + + + + + + + + + + +typedef union { + TMC2209TypeDef tmc2209; +} DriverBoards; + +DriverBoards driverBoards; +#define TMC2209_CRC(data, length) tmc_CRC8(data, length, 1) + +#define TMC2209 (driverBoards.tmc2209) +#define BUFFER_SIZE 32 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 +#define WRITE_READ_DELAY 10 +// #include "tmc/boards/Board.h" +// #include "tmc/tmc/StepDir.h" +// // => UART wrapper +// extern void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength); +// // <= UART wrapper + +// // => CRC wrapper +// extern uint8_t tmc2209_CRC8(uint8_t *data, size_t length); +// // <= CRC wrapper + +static UART_Config *TMC2209_UARTChannel; + +static inline TMC2209TypeDef *motorToIC(uint8_t motor) +{ + UNUSED(motor); + + return &TMC2209; +} + +static inline UART_Config *channelToUART(uint8_t channel) +{ + UNUSED(channel); + + return TMC2209_UARTChannel; +} + +// => UART wrapper + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = 0; + // while(uart->rxtx.bytesAvailable() < readLength) + // { + // if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + // { + // Abort on timeout + // return -1; + // } + // } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength) +{ + UART_readWrite(channelToUART(channel), data, writeLength, readLength); +} +// <= UART wrapper + +// => CRC wrapper +// Return the CRC8 of [length] bytes of data stored in the [data] array. +uint8_t tmc2209_CRC8(uint8_t *data, size_t length) +{ + return TMC2209_CRC(data, length); +} +// <= CRC wrapper + +void tmc2209_writeRegister(uint8_t motor, uint16_t address, int32_t value) +{ + tmc2209_writeInt(motorToIC(motor), (uint8_t) address, value); + +} + +void tmc2209_readRegister(uint8_t motor, uint16_t address, int32_t *value) +{ + *value = tmc2209_readInt(motorToIC(motor), (uint8_t) address); +} + + +void tmc2209_writeInt(TMC2209TypeDef *tmc2209, uint8_t address, int32_t value) +{ + uint8_t data[8]; + + data[0] = 0x05; + data[1] = tmc2209->slaveAddress; + data[2] = address | TMC_WRITE_BIT; + data[3] = (value >> 24) & 0xFF; + data[4] = (value >> 16) & 0xFF; + data[5] = (value >> 8 ) & 0xFF; + data[6] = (value ) & 0xFF; + data[7] = tmc2209_CRC8(data, 7); + + tmc2209_readWriteArray(tmc2209->config->channel, &data[0], 8, 0); + + // Write to the shadow register and mark the register dirty + address = TMC_ADDRESS(address); + tmc2209->config->shadowRegister[address] = value; + tmc2209->registerAccess[address] |= TMC_ACCESS_DIRTY; +} + +int32_t tmc2209_readInt(TMC2209TypeDef *tmc2209, uint8_t address) +{ + uint8_t data[8] = { 0 }; + + address = TMC_ADDRESS(address); + + if (!TMC_IS_READABLE(tmc2209->registerAccess[address])) + return tmc2209->config->shadowRegister[address]; + + data[0] = 0x05; + data[1] = tmc2209->slaveAddress; + data[2] = address; + data[3] = tmc2209_CRC8(data, 3); + + tmc2209_readWriteArray(tmc2209->config->channel, data, 4, 8); + + // Byte 0: Sync nibble correct? + if (data[0] != 0x05) + return 0; + + // Byte 1: Master address correct? + if (data[1] != 0xFF) + return 0; + + // Byte 2: Address correct? + if (data[2] != address) + return 0; + + // Byte 7: CRC correct? + if (data[7] != tmc2209_CRC8(data, 7)) + return 0; + + return ((uint32_t)data[3] << 24) | ((uint32_t)data[4] << 16) | (data[5] << 8) | data[6]; +} + +void tmc2209_init(TMC2209TypeDef *tmc2209, uint8_t channel, uint8_t slaveAddress, ConfigurationTypeDef *tmc2209_config, const int32_t *registerResetState) +{ + tmc2209->slaveAddress = slaveAddress; + + tmc2209->config = tmc2209_config; + tmc2209->config->callback = NULL; + tmc2209->config->channel = channel; + tmc2209->config->configIndex = 0; + tmc2209->config->state = CONFIG_READY; + + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + { + tmc2209->registerAccess[i] = tmc2209_defaultRegisterAccess[i]; + tmc2209->registerResetState[i] = registerResetState[i]; + } +} + +static void writeConfiguration(TMC2209TypeDef *tmc2209) +{ + uint8_t *ptr = &tmc2209->config->configIndex; + const int32_t *settings; + + if(tmc2209->config->state == CONFIG_RESTORE) + { + settings = tmc2209->config->shadowRegister; + // Find the next restorable register + while((*ptr < TMC2209_REGISTER_COUNT) && !TMC_IS_RESTORABLE(tmc2209->registerAccess[*ptr])) + { + (*ptr)++; + } + } + else + { + settings = tmc2209->registerResetState; + // Find the next resettable register + while((*ptr < TMC2209_REGISTER_COUNT) && !TMC_IS_RESETTABLE(tmc2209->registerAccess[*ptr])) + { + (*ptr)++; + } + } + + if(*ptr < TMC2209_REGISTER_COUNT) + { + tmc2209_writeInt(tmc2209, *ptr, settings[*ptr]); + (*ptr)++; + } + else // Finished configuration + { + if(tmc2209->config->callback) + { + ((tmc2209_callback)tmc2209->config->callback)(tmc2209, tmc2209->config->state); + } + + tmc2209->config->state = CONFIG_READY; + } +} + +void tmc2209_periodicJob(TMC2209TypeDef *tmc2209, uint32_t tick) +{ + UNUSED(tick); + + if(tmc2209->config->state != CONFIG_READY) + { + writeConfiguration(tmc2209); + return; + } +} + +void tmc2209_setRegisterResetState(TMC2209TypeDef *tmc2209, const int32_t *resetState) +{ + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + tmc2209->registerResetState[i] = resetState[i]; +} + +void tmc2209_setCallback(TMC2209TypeDef *tmc2209, tmc2209_callback callback) +{ + tmc2209->config->callback = (tmc_callback_config) callback; +} + +uint8_t tmc2209_reset(TMC2209TypeDef *tmc2209) +{ + if(tmc2209->config->state != CONFIG_READY) + return false; + + // Reset the dirty bits and wipe the shadow registers + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + { + tmc2209->registerAccess[i] &= ~TMC_ACCESS_DIRTY; + tmc2209->config->shadowRegister[i] = 0; + } + + tmc2209->config->state = CONFIG_RESET; + tmc2209->config->configIndex = 0; + + return true; +} + +uint8_t tmc2209_restore(TMC2209TypeDef *tmc2209) +{ + if(tmc2209->config->state != CONFIG_READY) + return false; + + tmc2209->config->state = CONFIG_RESTORE; + tmc2209->config->configIndex = 0; + + return true; +} + +uint8_t tmc2209_get_slave(TMC2209TypeDef *tmc2209) +{ + return tmc2209->slaveAddress; +} + +void tmc2209_set_slave(TMC2209TypeDef *tmc2209, uint8_t slaveAddress) +{ + tmc2209->slaveAddress = slaveAddress; +} diff --git a/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.h b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.h new file mode 100644 index 0000000..d9bdc0e --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_IC_TMC2209_H_ +#define TMC_IC_TMC2209_H_ + +#include "tmc/helpers/Constants.h" +#include "tmc/helpers/API_Header.h" +#include "TMC2209_Register.h" +#include "TMC2209_Constants.h" +#include "TMC2209_Fields.h" + +// Helper macros +#define TMC2209_FIELD_READ(tdef, address, mask, shift) \ + FIELD_GET(tmc2209_readInt(tdef, address), mask, shift) +#define TMC2209_FIELD_UPDATE(tdef, address, mask, shift, value) \ + (tmc2209_writeInt(tdef, address, FIELD_SET(tmc2209_readInt(tdef, address), mask, shift, value))) + +// Usage note: use 1 TypeDef per IC +typedef struct { + ConfigurationTypeDef *config; + + int32_t registerResetState[TMC2209_REGISTER_COUNT]; + uint8_t registerAccess[TMC2209_REGISTER_COUNT]; + + uint8_t slaveAddress; +} TMC2209TypeDef; + +typedef void (*tmc2209_callback)(TMC2209TypeDef*, ConfigState); + +// Default Register values +#define R00 0x00000040 // GCONF +#define R10 0x00071703 // IHOLD_IRUN +#define R11 0x00000014 // TPOWERDOWN +#define R6C 0x10000053 // CHOPCONF +#define R70 0xC10D0024 // PWMCONF + +// Register access permissions: +// 0x00: none (reserved) +// 0x01: read +// 0x02: write +// 0x03: read/write +// 0x13: read/write, separate functions/values for reading or writing +// 0x23: read/write, flag register (write to clear) +// 0x42: write, has hardware presets on reset +static const uint8_t tmc2209_defaultRegisterAccess[TMC2209_REGISTER_COUNT] = +{ +// 0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x03, 0x23, 0x01, 0x02, 0x02, 0x01, 0x01, 0x03, ____, ____, ____, ____, ____, ____, ____, ____, // 0x00 - 0x0F + 0x02, 0x02, 0x01, 0x02, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x10 - 0x1F + ____, ____, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x20 - 0x2F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x30 - 0x3F + 0x02, 0x01, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x40 - 0x4F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x50 - 0x5F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, 0x01, 0x01, 0x03, ____, ____, 0x01, // 0x60 - 0x6F + 0x03, 0x01, 0x01, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____ // 0x70 - 0x7F +}; + +static const int32_t tmc2209_defaultRegisterResetState[TMC2209_REGISTER_COUNT] = +{ +// 0 1 2 3 4 5 6 7 8 9 A B C D E F + R00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x00 - 0x0F + R10, R11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x10 - 0x1F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x20 - 0x2F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x30 - 0x3F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x40 - 0x4F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x50 - 0x5F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R6C, 0, 0, 0, // 0x60 - 0x6F + R70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 // 0x70 - 0x7F +}; + +// Undefine the default register values. +// This prevents warnings in case multiple TMC-API chip headers are included at once +#undef R00 +#undef R10 +#undef R11 +#undef R6C +#undef R70 + +// Communication +void tmc2209_writeInt(TMC2209TypeDef *tmc2209, uint8_t address, int32_t value); +int32_t tmc2209_readInt(TMC2209TypeDef *tmc2209, uint8_t address); + +void tmc2209_init(TMC2209TypeDef *tmc2209, uint8_t channel, uint8_t slaveAddress, ConfigurationTypeDef *tmc2209_config, const int32_t *registerResetState); +uint8_t tmc2209_reset(TMC2209TypeDef *tmc2209); +uint8_t tmc2209_restore(TMC2209TypeDef *tmc2209); +void tmc2209_setRegisterResetState(TMC2209TypeDef *tmc2209, const int32_t *resetState); +void tmc2209_setCallback(TMC2209TypeDef *tmc2209, tmc2209_callback callback); +void tmc2209_periodicJob(TMC2209TypeDef *tmc2209, uint32_t tick); + +uint8_t tmc2209_get_slave(TMC2209TypeDef *tmc2209); +void tmc2209_set_slave(TMC2209TypeDef *tmc2209, uint8_t slaveAddress); + +#endif /* TMC_IC_TMC2209_H_ */ diff --git a/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h new file mode 100644 index 0000000..950dae0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h @@ -0,0 +1,20 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ +#define TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ + +#define TMC2209_MOTORS 1 +#define TMC2209_REGISTER_COUNT TMC_REGISTER_COUNT +#define TMC2209_WRITE_BIT TMC_WRITE_BIT +#define TMC2209_ADDRESS_MASK TMC_ADDRESS_MASK +#define TMC2209_MAX_VELOCITY s32_MAX +#define TMC2209_MAX_ACCELERATION u24_MAX + +#endif /* TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ */ diff --git a/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h new file mode 100644 index 0000000..946c977 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h @@ -0,0 +1,182 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC2209_FIELDS_H +#define TMC2209_FIELDS_H + +#define TMC2209_I_SCALE_ANALOG_MASK 0x01 // GCONF // I_scale_analog (Reset default=1) +#define TMC2209_I_SCALE_ANALOG_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_INTERNAL_RSENSE_MASK 0x02 // GCONF // internal_Rsense (Reset default: OTP) +#define TMC2209_INTERNAL_RSENSE_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_EN_SPREADCYCLE_MASK 0x04 // GCONF // en_spreadCycle (Reset default: OTP) +#define TMC2209_EN_SPREADCYCLE_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_SHAFT_MASK 0x08 // GCONF // controls motor direction +#define TMC2209_SHAFT_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_INDEX_OTPW_MASK 0x10 // GCONF // index_otpw +#define TMC2209_INDEX_OTPW_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_INDEX_STEP_MASK 0x20 // GCONF // index_step +#define TMC2209_INDEX_STEP_SHIFT 5 // min.: 0, max.: 1, default: 0 +#define TMC2209_PDN_DISABLE_MASK 0x40 // GCONF // pdn_disable +#define TMC2209_PDN_DISABLE_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_MSTEP_REG_SELECT_MASK 0x80 // GCONF // mstep_reg_select +#define TMC2209_MSTEP_REG_SELECT_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_MULTISTEP_FILT_MASK 0x0100 // GCONF // multistep_filt (Reset default=1) +#define TMC2209_MULTISTEP_FILT_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_TEST_MODE_MASK 0x0200 // GCONF // test_mode 0 +#define TMC2209_TEST_MODE_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_RESET_MASK 0x01 // GSTAT // reset +#define TMC2209_RESET_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_DRV_ERR_MASK 0x02 // GSTAT // drv_err +#define TMC2209_DRV_ERR_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_UV_CP_MASK 0x04 // GSTAT // uv_cp +#define TMC2209_UV_CP_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_IFCNT_MASK 0xFF // IFCNT // Interface transmission counter. This register becomes incremented with each successful UART interface write access. Read out to check the serial transmission for lost data. Read accesses do not change the content. The counter wraps around from 255 to 0. +#define TMC2209_IFCNT_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_SLAVECONF_MASK 0x0F00 // SLAVECONF // SENDDELAY for read access (time until reply is sent): 0, 1: 8 bit times 2, 3: 3*8 bit times 4, 5: 5*8 bit times 6, 7: 7*8 bit times 8, 9: 9*8 bit times 10, 11: 11*8 bit times 12, 13: 13*8 bit times 14, 15: 15*8 bit times +#define TMC2209_SLAVECONF_SHIFT 8 // min.: 0, max.: 15, default: 0 +#define TMC2209_OTPBIT_MASK 0x07 // OTP_PROG // Selection of OTP bit to be programmed to the selected byte location (n=0..7: programs bit n to a logic 1) +#define TMC2209_OTPBIT_SHIFT 0 // min.: 0, max.: 7, default: 0 +#define TMC2209_OTPBYTE_MASK 0x30 // OTP_PROG // Selection of OTP programming location (0, 1 or 2) +#define TMC2209_OTPBYTE_SHIFT 4 // min.: 0, max.: 3, default: 0 +#define TMC2209_OTPMAGIC_MASK 0xFF00 // OTP_PROG // Set to 0xBD to enable programming. A programming time of minimum 10ms per bit is recommended (check by reading OTP_READ). +#define TMC2209_OTPMAGIC_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP0_BYTE_0_READ_DATA_MASK 0x01 // OTP_READ // to be detailed +#define TMC2209_OTP0_BYTE_0_READ_DATA_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP1_BYTE_1_READ_DATA_MASK 0x02 // OTP_READ // to be detailed +#define TMC2209_OTP1_BYTE_1_READ_DATA_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP2_BYTE_2_READ_DATA_MASK 0x04 // OTP_READ // to be detailed +#define TMC2209_OTP2_BYTE_2_READ_DATA_SHIFT 16 // min.: 0, max.: 255, default: 0 +#define TMC2209_ENN_MASK 0x01 // IOIN // +#define TMC2209_ENN_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_MS1_MASK 0x04 // IOIN // +#define TMC2209_MS1_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_MS2_MASK 0x08 // IOIN // +#define TMC2209_MS2_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_DIAG_MASK 0x10 // IOIN // +#define TMC2209_DIAG_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_PDN_UART_MASK 0x40 // IOIN // +#define TMC2209_PDN_UART_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_STEP_MASK 0x80 // IOIN // +#define TMC2209_STEP_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_SEL_A_MASK 0x0100 // IOIN // Driver type +#define TMC2209_SEL_A_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_DIR_MASK 0x0200 // IOIN // +#define TMC2209_DIR_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_VERSION_MASK 0xFF000000 // IOIN // VERSION: 0x20=first version of the IC Identical numbers mean full digital compatibility. +#define TMC2209_VERSION_SHIFT 24 // min.: 0, max.: 255, default: 0 +#define TMC2209_FCLKTRIM_MASK 0x1F // FACTORY_CONF // FCLKTRIM (Reset default: OTP) 0-31: Lowest to highest clock frequency. Check at charge pump output. The frequency span is not guaranteed, but it is tested, that tuning to 12MHz internal clock is possible. The devices come preset to 12MHz clock frequency by OTP programming. +#define TMC2209_FCLKTRIM_SHIFT 0 // min.: 0, max.: 31, default: 0 +#define TMC2209_OTTRIM_MASK 0x30 // FACTORY_CONF // OTTRIM (Default: OTP) %00: OT=143°C, OTPW=120°C %01: OT=150°C, OTPW=120°C %10: OT=150°C, OTPW=143°C %11: OT=157°C, OTPW=143°C +#define TMC2209_OTTRIM_SHIFT 8 // min.: 0, max.: 3, default: 0 +#define TMC2209_IHOLD_MASK 0x1F // IHOLD_IRUN // IHOLD (Reset default: OTP) Standstill current (0=1/32...31=32/32) In combination with stealthChop mode, setting IHOLD=0 allows to choose freewheeling or coil short circuit (passive braking) for motor stand still. +#define TMC2209_IHOLD_SHIFT 0 // min.: 0, max.: 31, default: 0 +#define TMC2209_IRUN_MASK 0x1F00 // IHOLD_IRUN // IRUN (Reset default=31) Motor run current (0=1/32...31=32/32) Hint: Choose sense resistors in a way, that normal IRUN is 16 to 31 for best microstep performance. +#define TMC2209_IRUN_SHIFT 8 // min.: 0, max.: 31, default: 0 +#define TMC2209_IHOLDDELAY_MASK 0x0F0000 // IHOLD_IRUN // IHOLDDELAY (Reset default: OTP) Controls the number of clock cycles for motor power down after standstill is detected (stst=1) and TPOWERDOWN has expired. The smooth transition avoids a motor jerk upon power down. 0: instant power down 1..15: Delay per current reduction step in multiple of 2^18 clocks +#define TMC2209_IHOLDDELAY_SHIFT 16 // min.: 0, max.: 15, default: 0 +#define TMC2209_TPOWERDOWN_MASK 0xFF // TPOWERDOWN // (Reset default=20) Sets the delay time from stand still (stst) detection to motor current power down. Time range is about 0 to 5.6 seconds. 0...((2^8)-1) * 2^18 tclk Attention: A minimum setting of 2 is required to allow automatic tuning of stealthChop PWM_OFFS_AUTO. +#define TMC2209_TPOWERDOWN_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_TSTEP_MASK 0x0FFFFF // TSTEP // Actual measured time between two 1/256 microsteps derived from the step input frequency in units of 1/fCLK. Measured value is (2^20)-1 in case of overflow or stand still. The TSTEP related threshold uses a hysteresis of 1/16 of the compare value to compensate for jitter in the clock or the step frequency: (Txxx*15/16)-1 is the lower compare value for each TSTEP based comparison. This means, that the lower switching velocity equals the calculated setting, but the upper switching velocity is higher as defined by the hysteresis setting. +#define TMC2209_TSTEP_SHIFT 0 // min.: 0, max.: 1048575, default: 0 +#define TMC2209_TPWMTHRS_MASK 0x0FFFFF // TPWMTHRS // Sets the upper velocity for stealthChop voltage PWM mode. For TSTEP = TPWMTHRS, stealthChop PWM mode is enabled, if configured. When the velocity exceeds the limit set by TPWMTHRS, the driver switches to spreadCycle. 0 = Disabled +#define TMC2209_TPWMTHRS_SHIFT 0 // min.: 0, max.: 1048575, default: 0 +#define TMC2209_VACTUAL_MASK 0xFFFFFF // VACTUAL // VACTUAL allows moving the motor by UART control. It gives the motor velocity in +-(2^23)-1 [µsteps / t] 0: Normal operation. Driver reacts to STEP input. /=0: Motor moves with the velocity given by VACTUAL. Step pulses can be monitored via INDEX output. The motor direction is controlled by the sign of VACTUAL. +#define TMC2209_VACTUAL_SHIFT 0 // min.: -8388608, max.: 8388607, default: 0 +#define TMC2209_SEMIN_MASK 0x0000000F +#define TMC2209_SEMIN_SHIFT 0 +#define TMC2209_SEUP_MASK 0x00000060 +#define TMC2209_SEUP_SHIFT 5 +#define TMC2209_SEMAX_MASK 0x00000F00 +#define TMC2209_SEMAX_SHIFT 8 +#define TMC2209_SEDN_MASK 0x00006000 +#define TMC2209_SEDN_SHIFT 13 +#define TMC2209_SEIMIN_MASK 0x00008000 +#define TMC2209_SEIMIN_SHIFT 15 +#define TMC2209_MSCNT_MASK 0x03FF // MSCNT // Microstep counter. Indicates actual position in the microstep table for CUR_A. CUR_B uses an offset of 256 into the table. Reading out MSCNT allows determination of the motor position within the electrical wave. +#define TMC2209_MSCNT_SHIFT 0 // min.: 0, max.: 1023, default: 0 +#define TMC2209_CUR_A_MASK 0x01FF // MSCURACT // (signed) Actual microstep current for motor phase A as read from the internal sine wave table (not scaled by current setting) +#define TMC2209_CUR_A_SHIFT 0 // min.: -255, max.: 255, default: 0 +#define TMC2209_CUR_B_MASK 0x01FF0000 // MSCURACT // (signed) Actual microstep current for motor phase B as read from the internal sine wave table (not scaled by current setting) +#define TMC2209_CUR_B_SHIFT 16 // min.: -255, max.: 255, default: 0 +#define TMC2209_TOFF_MASK 0x0F // CHOPCONF // chopper off time and driver enable, Off time setting controls duration of slow decay phase (Nclk = 12 + 32*Toff), %0000: Driver disable, all bridges off %0001: 1 - use only with TBL = 2 %0010 ... %1111: 2 - 15 (Default: OTP, resp. 3 in stealthChop mode) +#define TMC2209_TOFF_SHIFT 0 // min.: 0, max.: 7, default: 0 +#define TMC2209_HSTRT_MASK 0x70 // CHOPCONF // hysteresis start value added to HEND, %000 - %111: Add 1, 2, ..., 8 to hysteresis low value HEND (1/512 of this setting adds to current setting) Attention: Effective HEND+HSTRT <= 16. Hint: Hysteresis decrement is done each 16 clocks. (Default: OTP, resp. 0 in stealthChop mode) +#define TMC2209_HSTRT_SHIFT 4 // min.: 0, max.: 7, default: 0 +#define TMC2209_HEND_MASK 0x0780 // CHOPCONF // hysteresis low value OFFSET sine wave offset, %0000 - %1111: Hysteresis is -3, -2, -1, 0, 1, ..., 12 (1/512 of this setting adds to current setting) This is the hysteresis value which becomes used for the hysteresis chopper. (Default: OTP, resp. 5 in stealthChop mode) +#define TMC2209_HEND_SHIFT 7 // min.: 0, max.: 255, default: 0 +#define TMC2209_TBL_MASK 0x018000 // CHOPCONF // blank time select, %00 - %11: Set comparator blank time to 16, 24, 32 or 40 clocks Hint: %00 or %01 is recommended for most applications (Default: OTP) +#define TMC2209_TBL_SHIFT 15 // min.: 0, max.: 255, default: 0 +#define TMC2209_VSENSE_MASK 0x020000 // CHOPCONF // sense resistor voltage based current scaling +#define TMC2209_VSENSE_SHIFT 17 // min.: 0, max.: 1, default: 0 +#define TMC2209_MRES_MASK 0x0F000000 // CHOPCONF // MRES micro step resolution, %0000: Native 256 microstep setting. %0001 - %1000: 128, 64, 32, 16, 8, 4, 2, FULLSTEP: Reduced microstep resolution. The resolution gives the number of microstep entries per sine quarter wave. When choosing a lower microstep resolution, the driver automatically uses microstep positions which result in a symmetrical wave. Number of microsteps per step pulse = 2^MRES (Selection by pins unless disabled by GCONF. mstep_reg_select) +#define TMC2209_MRES_SHIFT 24 // min.: 0, max.: 255, default: 0 +#define TMC2209_INTPOL_MASK 0x10000000 // CHOPCONF // interpolation to 256 microsteps +#define TMC2209_INTPOL_SHIFT 28 // min.: 0, max.: 1, default: 0 +#define TMC2209_DEDGE_MASK 0x20000000 // CHOPCONF // enable double edge step pulses +#define TMC2209_DEDGE_SHIFT 29 // min.: 0, max.: 1, default: 0 +#define TMC2209_DISS2G_MASK 0x40000000 // CHOPCONF // short to GND protection disable +#define TMC2209_DISS2G_SHIFT 30 // min.: 0, max.: 1, default: 0 +#define TMC2209_DISS2VS_MASK 0x80000000 // CHOPCONF // Low side short protection disable +#define TMC2209_DISS2VS_SHIFT 31 // min.: 0, max.: 1, default: 0 +#define TMC2209_OTPW_MASK 0x01 // DRV_STATUS // overtemperature prewarning flag +#define TMC2209_OTPW_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_OT_MASK 0x02 // DRV_STATUS // overtemperature flag +#define TMC2209_OT_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2GA_MASK 0x04 // DRV_STATUS // short to ground indicator phase A +#define TMC2209_S2GA_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2GB_MASK 0x08 // DRV_STATUS // short to ground indicator phase B +#define TMC2209_S2GB_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2VSA_MASK 0x10 // DRV_STATUS // low side short indicator phase A +#define TMC2209_S2VSA_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2VSB_MASK 0x20 // DRV_STATUS // low side short indicator phase B +#define TMC2209_S2VSB_SHIFT 5 // min.: 0, max.: 1, default: 0 +#define TMC2209_OLA_MASK 0x40 // DRV_STATUS // open load indicator phase A +#define TMC2209_OLA_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_OLB_MASK 0x80 // DRV_STATUS // open load indicator phase B +#define TMC2209_OLB_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_T120_MASK 0x0100 // DRV_STATUS // 120°C comparator +#define TMC2209_T120_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_T143_MASK 0x0200 // DRV_STATUS // 143°C comparator +#define TMC2209_T143_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_T150_MASK 0x0400 // DRV_STATUS // 150°C comparator +#define TMC2209_T150_SHIFT 10 // min.: 0, max.: 1, default: 0 +#define TMC2209_T157_MASK 0x0800 // DRV_STATUS // 157°C comparator +#define TMC2209_T157_SHIFT 11 // min.: 0, max.: 1, default: 0 +#define TMC2209_CS_ACTUAL_MASK 0x1F0000 // DRV_STATUS // actual motor current +#define TMC2209_CS_ACTUAL_SHIFT 16 // min.: 0, max.: 31, default: 0 +#define TMC2209_STEALTH_MASK 0x40000000 // DRV_STATUS // stealthChop indicator +#define TMC2209_STEALTH_SHIFT 30 // min.: 0, max.: 1, default: 0 +#define TMC2209_STST_MASK 0x80000000 // DRV_STATUS // standstill indicator +#define TMC2209_STST_SHIFT 31 // min.: 0, max.: 1, default: 0 +#define TMC2209_PWM_OFS_MASK 0xFF // PWMCONF // User defined PWM amplitude offset (0-255) related to full motor current (CS_ACTUAL=31) in stand still. (Reset default=36) When using automatic scaling (pwm_autoscale=1) the value is used for initialization, only. The autoscale function starts with PWM_SCALE_AUTO=PWM_OFS and finds the required offset to yield the target current automatically. PWM_OFS = 0 will disable scaling down motor current below a motor specific lower measurement threshold. This setting should only be used under certain conditions, i.e. when the power supply voltage can vary up and down by a factor of two or more. It prevents the motor going out of regulation, but it also prevents power down below the regulation limit. PWM_OFS > 0 allows automatic scaling to low PWM duty cycles even below the lower regulation threshold. This allows low (standstill) current settings based on the actual (hold) current scale (register IHOLD_IRUN). +#define TMC2209_PWM_OFS_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_GRAD_MASK 0xFF00 // PWMCONF // Velocity dependent gradient for PWM amplitude: PWM_GRAD * 256 / TSTEP This value is added to PWM_AMPL to compensate for the velocity-dependent motor back-EMF. With automatic scaling (pwm_autoscale=1) the value is used for first initialization, only. Set PWM_GRAD to the application specific value (it can be read out from PWM_GRAD_AUTO) to speed up the automatic tuning process. An approximate value can be stored to OTP by programming OTP_PWM_GRAD. +#define TMC2209_PWM_GRAD_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_FREQ_MASK 0x030000 // PWMCONF // %00: fPWM=2/1024 fCLK %01: fPWM=2/683 fCLK %10: fPWM=2/512 fCLK %11: fPWM=2/410 fCLK +#define TMC2209_PWM_FREQ_SHIFT 16 // min.: 0, max.: 3, default: 0 +#define TMC2209_PWM_AUTOSCALE_MASK 0x040000 // PWMCONF // +#define TMC2209_PWM_AUTOSCALE_SHIFT 18 // min.: 0, max.: 1, default: 0 +#define TMC2209_PWM_AUTOGRAD_MASK 0x080000 // PWMCONF // +#define TMC2209_PWM_AUTOGRAD_SHIFT 19 // min.: 0, max.: 1, default: 0 +#define TMC2209_FREEWHEEL_MASK 0x300000 // PWMCONF // Stand still option when motor current setting is zero (I_HOLD=0). %00: Normal operation %01: Freewheeling %10: Coil shorted using LS drivers %11: Coil shorted using HS drivers +#define TMC2209_FREEWHEEL_SHIFT 20 // min.: 0, max.: 3, default: 0 +#define TMC2209_PWM_REG_MASK 0x0F000000 // PWMCONF // User defined maximum PWM amplitude change per half wave when using pwm_autoscale=1. (1...15): 1: 0.5 increments (slowest regulation) 2: 1 increment (default with OTP2.1=1) 3: 1.5 increments 4: 2 increments ... 8: 4 increments (default with OTP2.1=0) ... 15: 7.5 increments (fastest regulation) +#define TMC2209_PWM_REG_SHIFT 24 // min.: 0, max.: 25, default: 0 +#define TMC2209_PWM_LIM_MASK 0xF0000000 // PWMCONF // Limit for PWM_SCALE_AUTO when switching back from spreadCycle to stealthChop. This value defines the upper limit for bits 7 to 4 of the automatic current control when switching back. It can be set to reduce the current jerk during mode change back to stealthChop. It does not limit PWM_GRAD or PWM_GRAD_AUTO offset. (Default = 12) +#define TMC2209_PWM_LIM_SHIFT 28 // min.: 0, max.: 15, default: 0 +#define TMC2209_PWM_SCALE_SUM_MASK 0xFF // PWM_SCALE // Actual PWM duty cycle. This value is used for scaling the values CUR_A and CUR_B read from the sine wave table. +#define TMC2209_PWM_SCALE_SUM_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_SCALE_AUTO_MASK 0x01FF0000 // PWM_SCALE // 9 Bit signed offset added to the calculated PWM duty cycle. This is the result of the automatic amplitude regulation based on current measurement. +#define TMC2209_PWM_SCALE_AUTO_SHIFT 16 // min.: -255, max.: 255, default: 0 +#define TMC2209_PWM_OFS_AUTO_MASK 0xFF // PWM_AUTO // Automatically determined offset value +#define TMC2209_PWM_OFS_AUTO_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_GRAD_AUTO_MASK 0xFF0000 // PWM_AUTO // Automatically determined gradient value +#define TMC2209_PWM_GRAD_AUTO_SHIFT 16 // min.: 0, max.: 255, default: 0 + +#endif /* TMC2209_FIELDS_H */ diff --git a/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h new file mode 100644 index 0000000..427a3a5 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC2209_REGISTER_H +#define TMC2209_REGISTER_H + +// ===== TMC2209 & 2202 & TMC2209 & 2220 & 2225 "Donkey Kong" family register set ===== + +#define TMC2209_GCONF 0x00 +#define TMC2209_GSTAT 0x01 +#define TMC2209_IFCNT 0x02 +#define TMC2209_SLAVECONF 0x03 +#define TMC2209_OTP_PROG 0x04 +#define TMC2209_OTP_READ 0x05 +#define TMC2209_IOIN 0x06 +#define TMC2209_FACTORY_CONF 0x07 + +#define TMC2209_IHOLD_IRUN 0x10 +#define TMC2209_TPOWERDOWN 0x11 +#define TMC2209_TSTEP 0x12 +#define TMC2209_TPWMTHRS 0x13 +#define TMC2209_TCOOLTHRS 0x14 + +#define TMC2209_VACTUAL 0x22 + +#define TMC2209_SGTHRS 0x40 +#define TMC2209_SG_RESULT 0x41 +#define TMC2209_COOLCONF 0x42 + +#define TMC2209_MSCNT 0x6A +#define TMC2209_MSCURACT 0x6B +#define TMC2209_CHOPCONF 0x6C +#define TMC2209_DRVSTATUS 0x6F +#define TMC2209_PWMCONF 0x70 +#define TMC2209_PWMSCALE 0x71 +#define TMC2209_PWM_AUTO 0x72 + +#endif /* TMC2209_Register */ diff --git a/Clean_TMC2209/lib/tmc/ramp/LinearRamp.c b/Clean_TMC2209/lib/tmc/ramp/LinearRamp.c new file mode 100644 index 0000000..24eb0c4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/LinearRamp.c @@ -0,0 +1,165 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * This is a basic proof-of-concept implementation of a linear motion ramp + * generator. It is designed to run with 1 calculation / ms. + * + * + */ +#include "LinearRamp.h" + +void tmc_linearRamp_init(TMC_LinearRamp *linearRamp) +{ + linearRamp->maxVelocity = 0; + linearRamp->targetPosition = 0; + linearRamp->targetVelocity = 0; + linearRamp->rampVelocity = 0; + linearRamp->acceleration = 0; + linearRamp->encoderSteps = u16_MAX; + linearRamp->lastdVRest = 0; + linearRamp->lastdXRest = 0; + linearRamp->rampEnabled = false; +} + +void tmc_linearRamp_computeRampVelocity(TMC_LinearRamp *linearRamp) +{ + if (linearRamp->rampEnabled) + { + // update target velocity according actual set acceleration + // (scaling pre-factor of 1000 used for 1ms velocity ramp handling) + + int32_t dV = linearRamp->acceleration; + + // to ensure that small velocity changes at high set acceleration are also possible + int32_t maxDTV = abs(linearRamp->targetVelocity - linearRamp->rampVelocity); + if (maxDTV < (dV/1000)) + dV = maxDTV*1000; + + dV += linearRamp->lastdVRest; + linearRamp->lastdVRest = dV % 1000; + + if (linearRamp->rampVelocity < linearRamp->targetVelocity) + { + // accelerate motor + linearRamp->rampVelocity += dV/1000; // divide with pre-factor + } + else if (linearRamp->rampVelocity > linearRamp->targetVelocity) + { + // decelerate motor + linearRamp->rampVelocity -= dV/1000; // divide with pre-factor + } + } + else + { + // use target velocity directly + linearRamp->rampVelocity = linearRamp->targetVelocity; + } + + // limit ramp velocity + linearRamp->rampVelocity = tmc_limitInt(linearRamp->rampVelocity, -linearRamp->maxVelocity, linearRamp->maxVelocity); +} + +void tmc_linearRamp_computeRampPosition(TMC_LinearRamp *linearRamp) +{ + if (linearRamp->rampEnabled) + { + // update target position according actual set acceleration and max velocity + // (scaling pre-factor of 1000 used for 1ms position ramp handling) + + // limit position difference for further computations + int32_t targetPositionsDifference = linearRamp->targetPosition-linearRamp->rampPosition; + + // limit the sqrti value in case of high position differences + int64_t sqrtiValue = tmc_limitS64(((int64_t)120 * (int64_t)linearRamp->acceleration * (int64_t)(abs(targetPositionsDifference))) / (int64_t)linearRamp->encoderSteps, 0, (int64_t)linearRamp->maxVelocity*(int64_t)linearRamp->maxVelocity); + + // compute max allowed ramp velocity to ramp down to target + int32_t maxRampStop = tmc_sqrti(sqrtiValue); + + // compute max allowed ramp velocity + int32_t maxRampTargetVelocity = 0; + if (targetPositionsDifference > 0) + { + maxRampTargetVelocity = tmc_limitInt(maxRampStop, 0, (int32_t)linearRamp->maxVelocity); + } + else if (targetPositionsDifference < 0) + { + maxRampTargetVelocity = tmc_limitInt(-maxRampStop, -(int32_t)linearRamp->maxVelocity, 0); + } + else + { + //maxRampTargetVelocity = 0; + } + + int32_t dV = linearRamp->acceleration; // pre-factor ~ 1/1000 + + // to ensure that small velocity changes at high set acceleration are also possible + int32_t maxDTV = abs(maxRampTargetVelocity - linearRamp->rampVelocity); + if (maxDTV < (dV / 1000)) + dV = maxDTV * 1000; + + dV += linearRamp->lastdVRest; + linearRamp->lastdVRest = dV % 1000; + + // do velocity ramping + if (maxRampTargetVelocity > linearRamp->rampVelocity) + { + linearRamp->rampVelocity += dV / 1000; + } + else if (maxRampTargetVelocity < linearRamp->rampVelocity) + { + linearRamp->rampVelocity -= dV / 1000; + } + + // limit positionRampTargetVelocity to maxRampTargetVelocity + //linearRamp->rampVelocity = tmc_limitInt(linearRamp->rampVelocity, -abs(maxRampTargetVelocity), abs(maxRampTargetVelocity)); + + // do position ramping using actual ramp velocity to update dX + int64_t dX = ((int64_t)linearRamp->rampVelocity * (int64_t)linearRamp->encoderSteps) / ((int64_t)60) + linearRamp->lastdXRest; + + // scale actual target position + int64_t tempActualTargetPosition = (int64_t)linearRamp->rampPosition * 1000; + + // reset helper variables if ramp position reached target position + if (abs(linearRamp->targetPosition - linearRamp->rampPosition) <= 10) /*abs(dX)*/ + { + // sync ramp position with target position on small deviations + linearRamp->rampPosition = linearRamp->targetPosition; + + // update actual target position + tempActualTargetPosition = (int64_t)linearRamp->rampPosition * 1000; + + dX = 0; + linearRamp->lastdXRest = 0; + linearRamp->rampVelocity = 0; + } + else + { + // update actual target position + tempActualTargetPosition += dX; + } + + int64_t absTempActualTargetPosition = (tempActualTargetPosition >= 0) ? tempActualTargetPosition : -tempActualTargetPosition; + + if (tempActualTargetPosition >= 0) + linearRamp->lastdXRest = (absTempActualTargetPosition % 1000); + else if (tempActualTargetPosition < 0) + linearRamp->lastdXRest = -(absTempActualTargetPosition % 1000); + + // scale actual target position back + linearRamp->rampPosition = tempActualTargetPosition / 1000; + } + else + { + // use target position directly + linearRamp->rampPosition = linearRamp->targetPosition; + + // hold ramp velocity in reset + linearRamp->rampVelocity = 0; + } +} diff --git a/Clean_TMC2209/lib/tmc/ramp/LinearRamp.h b/Clean_TMC2209/lib/tmc/ramp/LinearRamp.h new file mode 100644 index 0000000..928ab44 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/LinearRamp.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_LINEAR_RAMP_H_ +#define TMC_LINEAR_RAMP_H_ + + #include "tmc/helpers/API_Header.h" + #include "tmc/helpers/Functions.h" + + typedef struct + { + uint32_t maxVelocity; + int32_t targetPosition; + int32_t rampPosition; + int32_t targetVelocity; + int32_t rampVelocity; + int32_t acceleration; + uint16_t encoderSteps; + int32_t lastdVRest; + int32_t lastdXRest; + uint8_t rampEnabled; + } TMC_LinearRamp; + + void tmc_linearRamp_init(TMC_LinearRamp *linearRamp); + void tmc_linearRamp_computeRampVelocity(TMC_LinearRamp *linearRamp); + void tmc_linearRamp_computeRampPosition(TMC_LinearRamp *linearRamp); + +#endif /* TMC_LINEAR_RAMP_H_ */ diff --git a/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.c b/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.c new file mode 100644 index 0000000..0f4c41f --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.c @@ -0,0 +1,303 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "LinearRamp1.h" +#include "tmc/helpers/Functions.h" + +void tmc_ramp_linear_init(TMC_LinearRamp *linearRamp) +{ + linearRamp->maxVelocity = 0; + linearRamp->targetPosition = 0; + linearRamp->targetVelocity = 0; + linearRamp->rampVelocity = 0; + linearRamp->rampPosition = 0; + linearRamp->acceleration = 0; + linearRamp->rampEnabled = true; + linearRamp->accumulatorVelocity = 0; + linearRamp->accumulatorPosition = 0; + linearRamp->rampMode = TMC_RAMP_LINEAR_MODE_VELOCITY; + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + linearRamp->precision = TMC_RAMP_LINEAR_DEFAULT_PRECISION; + linearRamp->homingDistance = TMC_RAMP_LINEAR_DEFAULT_HOMING_DISTANCE; + linearRamp->stopVelocity = TMC_RAMP_LINEAR_DEFAULT_STOP_VELOCITY; +} + +void tmc_ramp_linear_set_enabled(TMC_LinearRamp *linearRamp, bool enabled) +{ + linearRamp->rampEnabled = enabled; +} + +void tmc_ramp_linear_set_maxVelocity(TMC_LinearRamp *linearRamp, uint32_t maxVelocity) +{ + linearRamp->maxVelocity = maxVelocity; +} + +void tmc_ramp_linear_set_targetPosition(TMC_LinearRamp *linearRamp, int32_t targetPosition) +{ + linearRamp->targetPosition = targetPosition; +} + +void tmc_ramp_linear_set_rampPosition(TMC_LinearRamp *linearRamp, int32_t rampPosition) +{ + linearRamp->rampPosition = rampPosition; +} + +void tmc_ramp_linear_set_targetVelocity(TMC_LinearRamp *linearRamp, int32_t targetVelocity) +{ + linearRamp->targetVelocity = targetVelocity; +} + +void tmc_ramp_linear_set_rampVelocity(TMC_LinearRamp *linearRamp, int32_t rampVelocity) +{ + linearRamp->rampVelocity = rampVelocity; +} + +void tmc_ramp_linear_set_acceleration(TMC_LinearRamp *linearRamp, int32_t acceleration) +{ + linearRamp->acceleration = acceleration; +} + +void tmc_ramp_linear_set_mode(TMC_LinearRamp *linearRamp, TMC_LinearRamp_Mode mode) +{ + linearRamp->rampMode = mode; +} + +void tmc_ramp_linear_set_precision(TMC_LinearRamp * linearRamp, uint32_t precision) +{ + linearRamp->precision = precision; +} + +void tmc_ramp_linear_set_homingDistance(TMC_LinearRamp *linearRamp, uint32_t homingDistance) +{ + linearRamp->homingDistance = homingDistance; +} + +void tmc_ramp_linear_set_stopVelocity(TMC_LinearRamp *linearRamp, uint32_t stopVelocity) +{ + linearRamp->stopVelocity = stopVelocity; +} + +bool tmc_ramp_linear_get_enabled(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampEnabled; +} + +uint32_t tmc_ramp_linear_get_maxVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->maxVelocity; +} + +int32_t tmc_ramp_linear_get_targetPosition(TMC_LinearRamp *linearRamp) +{ + return linearRamp->targetPosition; +} + +int32_t tmc_ramp_linear_get_rampPosition(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampPosition; +} + +int32_t tmc_ramp_linear_get_targetVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->targetVelocity; +} + +int32_t tmc_ramp_linear_get_rampVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampVelocity; +} + +int32_t tmc_ramp_linear_get_acceleration(TMC_LinearRamp *linearRamp) +{ + return linearRamp->acceleration; +} + +TMC_LinearRamp_State tmc_ramp_linear_get_state(TMC_LinearRamp *linearRamp) +{ + return linearRamp->state; +} + +TMC_LinearRamp_Mode tmc_ramp_linear_get_mode(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampMode; +} + +uint32_t tmc_ramp_linear_get_precision(TMC_LinearRamp *linearRamp) +{ + return linearRamp->precision; +} + +// The maximum acceleration depends on the precision value +uint32_t tmc_ramp_linear_get_acceleration_limit(TMC_LinearRamp *linearRamp) +{ + return (0xFFFFFFFFu / linearRamp->precision) * linearRamp->precision; +} + +uint32_t tmc_ramp_linear_get_velocity_limit(TMC_LinearRamp *linearRamp) +{ + return linearRamp->precision; +} + +uint32_t tmc_ramp_linear_get_homingDistance(TMC_LinearRamp *linearRamp) +{ + return linearRamp->homingDistance; +} + +uint32_t tmc_ramp_linear_get_stopVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->stopVelocity; +} + +int32_t tmc_ramp_linear_compute(TMC_LinearRamp *linearRamp) +{ + tmc_ramp_linear_compute_position(linearRamp); + return tmc_ramp_linear_compute_velocity(linearRamp); +} + +int32_t tmc_ramp_linear_compute_velocity(TMC_LinearRamp *linearRamp) +{ + bool accelerating = linearRamp->rampVelocity != linearRamp->targetVelocity; + + if (linearRamp->rampEnabled) + { + // Add current acceleration to accumulator + linearRamp->accumulatorVelocity += linearRamp->acceleration; + + // Calculate the velocity delta value and keep the remainder of the velocity accumulator + int32_t dv = linearRamp->accumulatorVelocity / linearRamp->precision; + linearRamp->accumulatorVelocity = linearRamp->accumulatorVelocity % linearRamp->precision; + + // Add dv to rampVelocity, and regulate to target velocity + if(linearRamp->rampVelocity < linearRamp->targetVelocity) + linearRamp->rampVelocity = MIN(linearRamp->rampVelocity + dv, linearRamp->targetVelocity); + else if(linearRamp->rampVelocity > linearRamp->targetVelocity) + linearRamp->rampVelocity = MAX(linearRamp->rampVelocity - dv, linearRamp->targetVelocity); + } + else + { + // use target velocity directly + linearRamp->rampVelocity = linearRamp->targetVelocity; + // Reset accumulator + linearRamp->accumulatorVelocity = 0; + } + + // Calculate the velocity delta value and keep the remainder of the position accumulator + linearRamp->accumulatorPosition += linearRamp->rampVelocity; + int32_t dx = linearRamp->accumulatorPosition / (int32_t) linearRamp->precision; + linearRamp->accumulatorPosition = linearRamp->accumulatorPosition % (int32_t) linearRamp->precision; + + if(dx == 0) + return dx; + + // Change actual position determined by position change + linearRamp->rampPosition += (dx < 0) ? (-1) : (1); + + // Count acceleration steps needed for decelerating later + linearRamp->accelerationSteps += (abs(linearRamp->rampVelocity) < abs(linearRamp->targetVelocity)) ? accelerating : -accelerating; + if (linearRamp->accelerationSteps < 0) + linearRamp->accelerationSteps = 0; + + return dx; +} + +void tmc_ramp_linear_compute_position(TMC_LinearRamp *linearRamp) +{ + if (!linearRamp->rampEnabled) + return; + + if (linearRamp->rampMode != TMC_RAMP_LINEAR_MODE_POSITION) + return; + + // Calculate steps needed to target + int32_t diffx = 0; + + switch(linearRamp->state) { + case TMC_RAMP_LINEAR_STATE_IDLE: + if(linearRamp->rampVelocity == 0) + linearRamp->accelerationSteps = 0; + + if(linearRamp->rampPosition == linearRamp->targetPosition) + break; + + linearRamp->state = TMC_RAMP_LINEAR_STATE_DRIVING; + break; + case TMC_RAMP_LINEAR_STATE_DRIVING: + // Calculate distance to target (positive = driving towards target) + if(linearRamp->rampVelocity > 0) + diffx = linearRamp->targetPosition - linearRamp->rampPosition; + else if(linearRamp->rampVelocity < 0) + diffx = -(linearRamp->targetPosition - linearRamp->rampPosition); + else + diffx = abs(linearRamp->targetPosition - linearRamp->rampPosition); + + // Steps left required for braking? + // (+ 1 to compensate rounding (flooring) errors of the position accumulator) + if(linearRamp->accelerationSteps + 1 >= diffx) + { + linearRamp->targetVelocity = 0; + linearRamp->state = TMC_RAMP_LINEAR_STATE_BRAKING; + } + else + { // Driving - apply VMAX (this also allows mid-ramp VMAX changes) + linearRamp->targetVelocity = (linearRamp->targetPosition > linearRamp->rampPosition) ? linearRamp->maxVelocity : -linearRamp->maxVelocity; + } + break; + case TMC_RAMP_LINEAR_STATE_BRAKING: + if(linearRamp->targetPosition == linearRamp->rampPosition) + { + if(abs(linearRamp->rampVelocity) <= linearRamp->stopVelocity) + { // Position reached, velocity within cutoff threshold (or zero) + linearRamp->rampVelocity = 0; + linearRamp->targetVelocity = 0; + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + } + else + { + // We're still too fast, we're going to miss the target position + // Let the deceleration continue until velocity is zero, then either + // home when within homing distance or start a new ramp (RAMP_DRIVING) + // towards the target. + } + } + else + { // We're not at the target position + if(linearRamp->rampVelocity != 0) + { // Still decelerating + + // Calculate distance to target (positive = driving towards target) + if(linearRamp->rampVelocity > 0) + diffx = linearRamp->targetPosition - linearRamp->rampPosition; + else if(linearRamp->rampVelocity < 0) + diffx = -(linearRamp->targetPosition - linearRamp->rampPosition); + else + diffx = abs(linearRamp->targetPosition - linearRamp->rampPosition); + + // Enough space to accelerate again? + // (+ 1 to compensate rounding (flooring) errors of the position accumulator) + if(linearRamp->accelerationSteps + 1 < diffx) + { + linearRamp->state = TMC_RAMP_LINEAR_STATE_DRIVING; + } + } + else + { // Standing still (not at the target position) + if(abs(linearRamp->targetPosition - linearRamp->rampPosition) <= linearRamp->homingDistance) + { // Within homing distance - drive with stop velocity + linearRamp->targetVelocity = (linearRamp->targetPosition > linearRamp->rampPosition)? linearRamp->stopVelocity : -linearRamp->stopVelocity; + } + else + { // Not within homing distance - start a new motion by switching to RAMP_IDLE + // Since (targetPosition != actualPosition) a new ramp will be started. + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + } + } + } + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.h b/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.h new file mode 100644 index 0000000..de41e98 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/LinearRamp1.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_RAMP_LINEARRAMP1_H_ +#define TMC_RAMP_LINEARRAMP1_H_ + +#include "tmc/helpers/API_Header.h" +#include "Ramp.h" + +// Default precision of the calculations. Internal calculations use a precision +// of 1/TMC_RAMP_LINEAR_PRECISION for acceleration and velocity. +// When using 2**N as precision, this results in N digits of precision. +#define TMC_RAMP_LINEAR_DEFAULT_PRECISION ((uint32_t)1<<17) + +// Position mode: When hitting the target position a velocity below the V_STOP threshold will be cut off to velocity 0 +#define TMC_RAMP_LINEAR_DEFAULT_HOMING_DISTANCE 5 + +// Position mode: When barely missing the target position by HOMING_DISTANCE or less, the remainder will be driven with V_STOP velocity +#define TMC_RAMP_LINEAR_DEFAULT_STOP_VELOCITY 5 + +typedef enum { + TMC_RAMP_LINEAR_MODE_VELOCITY, + TMC_RAMP_LINEAR_MODE_POSITION +} TMC_LinearRamp_Mode; + +typedef enum { + TMC_RAMP_LINEAR_STATE_IDLE, + TMC_RAMP_LINEAR_STATE_DRIVING, + TMC_RAMP_LINEAR_STATE_BRAKING +} TMC_LinearRamp_State; + +typedef struct +{ + uint32_t maxVelocity; + int32_t targetPosition; + int32_t rampPosition; + int32_t targetVelocity; + int32_t rampVelocity; + int32_t acceleration; + bool rampEnabled; + int32_t accumulatorVelocity; + int32_t accumulatorPosition; + TMC_LinearRamp_Mode rampMode; + TMC_LinearRamp_State state; + int32_t accelerationSteps; + uint32_t precision; + uint32_t homingDistance; + uint32_t stopVelocity; +} TMC_LinearRamp; + +void tmc_ramp_linear_init(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_compute(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_compute_velocity(TMC_LinearRamp *linearRamp); +void tmc_ramp_linear_compute_position(TMC_LinearRamp *linearRamp); + +void tmc_ramp_linear_set_enabled(TMC_LinearRamp *linearRamp, bool enabled); +void tmc_ramp_linear_set_maxVelocity(TMC_LinearRamp *linearRamp, uint32_t maxVelocity); +void tmc_ramp_linear_set_targetPosition(TMC_LinearRamp *linearRamp, int32_t targetPosition); +void tmc_ramp_linear_set_rampPosition(TMC_LinearRamp *linearRamp, int32_t rampPosition); +void tmc_ramp_linear_set_targetVelocity(TMC_LinearRamp *linearRamp, int32_t targetVelocity); +void tmc_ramp_linear_set_rampVelocity(TMC_LinearRamp *linearRamp, int32_t rampVelocity); +void tmc_ramp_linear_set_acceleration(TMC_LinearRamp *linearRamp, int32_t acceleration); +void tmc_ramp_linear_set_mode(TMC_LinearRamp *linearRamp, TMC_LinearRamp_Mode mode); +void tmc_ramp_linear_set_precision(TMC_LinearRamp * linearRamp, uint32_t precision); +void tmc_ramp_linear_set_homingDistance(TMC_LinearRamp *linearRamp, uint32_t homingDistance); +void tmc_ramp_linear_set_stopVelocity(TMC_LinearRamp *linearRamp, uint32_t stopVelocity); + +bool tmc_ramp_linear_get_enabled(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_maxVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_targetPosition(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_rampPosition(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_targetVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_rampVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_acceleration(TMC_LinearRamp *linearRamp); +TMC_LinearRamp_State tmc_ramp_linear_get_state(TMC_LinearRamp *linearRamp); +TMC_LinearRamp_Mode tmc_ramp_linear_get_mode(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_precision(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_acceleration_limit(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_velocity_limit(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_homingDistance(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_stopVelocity(TMC_LinearRamp *linearRamp); + +#endif /* TMC_RAMP_LINEARRAMP1_H_ */ diff --git a/Clean_TMC2209/lib/tmc/ramp/Ramp.c b/Clean_TMC2209/lib/tmc/ramp/Ramp.c new file mode 100644 index 0000000..7fbf726 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/Ramp.c @@ -0,0 +1,91 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Ramp.h" + +void tmc_ramp_init(void *ramp, TMC_RampType type) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_init((TMC_LinearRamp *)ramp); + break; + } +} + +int32_t tmc_ramp_compute(void *ramp, TMC_RampType type, uint32_t delta) +{ + uint32_t i; + int32_t dxSum = 0; + + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + for (i = 0; i < delta; i++) + { + dxSum += tmc_ramp_linear_compute((TMC_LinearRamp *)ramp); + } + break; + } + + return dxSum; +} + +int32_t tmc_ramp_get_rampVelocity(void *ramp, TMC_RampType type) +{ + int32_t v = 0; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + v = tmc_ramp_linear_get_rampVelocity((TMC_LinearRamp *)ramp); + break; + } + return v; +} + +int32_t tmc_ramp_get_rampPosition(void *ramp, TMC_RampType type) +{ + int32_t x = 0; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + x = tmc_ramp_linear_get_rampPosition((TMC_LinearRamp *)ramp); + break; + } + return x; +} + +bool tmc_ramp_get_enabled(void *ramp, TMC_RampType type) +{ + bool enabled = false; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + enabled = tmc_ramp_linear_get_enabled((TMC_LinearRamp *)ramp); + break; + } + return enabled; +} + +void tmc_ramp_set_enabled(void *ramp, TMC_RampType type, bool enabled) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_set_enabled((TMC_LinearRamp *)ramp, enabled); + break; + } +} + +void tmc_ramp_toggle_enabled(void *ramp, TMC_RampType type) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_set_enabled((TMC_LinearRamp *)ramp, !tmc_ramp_get_enabled(ramp, type)); + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/ramp/Ramp.h b/Clean_TMC2209/lib/tmc/ramp/Ramp.h new file mode 100644 index 0000000..e7cc6a0 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/ramp/Ramp.h @@ -0,0 +1,40 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_RAMP_RAMP_H_ +#define TMC_RAMP_RAMP_H_ + +#include "LinearRamp1.h" + +typedef enum { + TMC_RAMP_TYPE_LINEAR +} TMC_RampType; + +// Initializes ramp parameters for given type +void tmc_ramp_init(void *ramp, TMC_RampType type); + +// Computes new ramp state after delta ticks have passed +// Note: To call this function periodically with a fixed delta-time, use delta = 1 and +// define the units of acceleration as v/delta-time. If you want to specify a different unit, +// change delta to your preference. +// Returns the position difference of the calculation. +int32_t tmc_ramp_compute(void *ramp, TMC_RampType type, uint32_t delta); + +// Returns the current ramp velocity computed by the given ramp +int32_t tmc_ramp_get_rampVelocity(void *ramp, TMC_RampType type); + +// Returns the current ramp position computed by the given ramp +int32_t tmc_ramp_get_rampPosition(void *ramp, TMC_RampType type); + +// Enable/disable ramps +bool tmc_ramp_get_enabled(void *ramp, TMC_RampType type); +void tmc_ramp_set_enabled(void *ramp, TMC_RampType type, bool enabled); +void tmc_ramp_toggle_enabled(void *ramp, TMC_RampType type); + +#endif /* TMC_RAMP_RAMP_H_ */ diff --git a/Clean_TMC2209/lib/tmc/tmc/BLDC.h b/Clean_TMC2209/lib/tmc/tmc/BLDC.h new file mode 100644 index 0000000..0b0e942 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/BLDC.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_BLDC_H_ +#define TMC_BLDC_H_ + +#include "tmc/helpers/API_Header.h" +#include "hal/derivative.h" +#include "hal/HAL.h" + +typedef enum { + MEASURE_ONE_PHASE, + MEASURE_THREE_PHASES, +} BLDCMeasurementType; + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW); +void timer_callback(void); + +void BLDC_calibrateADCs(); + +void BLDC_enablePWM(uint8_t enable); +uint8_t BLDC_isPWMenabled(); + +void BLDC_setTargetPWM(int16_t pwm); +int16_t BLDC_getTargetPWM(); + +int32_t BLDC_getMeasuredCurrent(); + +typedef enum { + BLDC_OPENLOOP, + BLDC_HALL, +} BLDCMode; + +void BLDC_setCommutationMode(BLDCMode mode); +BLDCMode BLDC_getCommutationMode(); + +void BLDC_setPolePairs(uint8 polePairs); +uint8_t BLDC_getPolePairs(); + +void BLDC_setOpenloopStepTime(uint16_t stepTime); +uint16_t BLDC_getOpenloopStepTime(); + +int32_t BLDC_getTargetAngle(); +int32_t BLDC_getHallAngle(); + +void BLDC_setTargetOpenloopVelocity(uint32_t velocity); +uint32_t BLDC_getTargetOpenloopVelocity(); +int32_t BLDC_getActualOpenloopVelocity(); +int32_t BLDC_getActualHallVelocity(); + +void BLDC_setHallOrder(uint8_t order); +uint8_t BLDC_getHallOrder(); + +void BLDC_setHallInvert(uint8_t invert); +uint8_t BLDC_getHallInvert(); + +void BLDC_setBBMTime(uint8_t time); +uint8_t BLDC_getBBMTime(); + +#endif /* TMC_BLDC_H_ */ diff --git a/Clean_TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c b/Clean_TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c new file mode 100644 index 0000000..8eb2f92 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c @@ -0,0 +1,746 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "BLDC.h" +#include "hal/HAL.h" +#include "hal/Timer.h" + +// FTM0_OUTMASK: 0-normal 1-inactive +#define PWM_PHASE_U_ENABLED 0x00 +#define PWM_PHASE_U_DISABLED 0x03 +#define PWM_PHASE_V_ENABLED 0x00 +#define PWM_PHASE_V_DISABLED 0x30 +#define PWM_PHASE_W_ENABLED 0x00 +#define PWM_PHASE_W_DISABLED 0xC0 + +#define VELOCITY_CALC_FREQ 10 // in Hz +#define PWM_FREQ 20000 // in Hz +#define PWM_PERIOD (48000000 / PWM_FREQ) // 48MHz/2*20kHz = 2500 + +typedef enum { + ADC_PHASE_U, + ADC_PHASE_V, + ADC_PHASE_W, +} ADC_Channel; + +uint8_t adcPhases[3] = { 0 }; +uint8_t adcCount = 3; +volatile ADC_Channel adc = ADC_PHASE_U; + +int16_t targetPWM = 0; +uint32_t openloopVelocity = 60; // mechanical RPM +uint16_t openloopStepTime = 0; // Calculate on init +BLDCMode commutationMode = BLDC_OPENLOOP; +uint8_t pwmEnabled = 0; +uint8_t bbmTime = 50; +uint8_t motorPolePairs = 1; + +int32_t targetAngle = 0; +int32_t hallAngle = 0; + +int32_t actualHallVelocity = 0; // electrical RPM + +volatile int32_t adcSamples[8] = { 0 }; +uint8_t adcSampleIndex = 0; + +int32_t adcOffset[3] = { 0 }; +uint32_t sampleCount[3] = { 0 }; + +int32_t currentScalingFactor = 256; // u24q8 format + +#define ADC_SAMPLES 100 + +typedef enum { + HALL_INVALID_0 = 0, + + HALL_001 = 1, + HALL_010 = 2, + HALL_011 = 3, + HALL_100 = 4, + HALL_101 = 5, + HALL_110 = 6, + + HALL_INVALID_1 = 7, +} HallStates; + +static int16_t hallStateToAngle(HallStates hallState); +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2); + +// Hall parameters +uint8_t hallOrder = 0; +uint8_t hallInvert = 0; + +volatile enum { + ADC_INIT, + ADC_READY +} adcState[3] = { ADC_INIT, ADC_INIT, ADC_INIT }; + +typedef struct +{ + IOPinTypeDef *HALL_U; + IOPinTypeDef *HALL_V; + IOPinTypeDef *HALL_W; + IOPinTypeDef *PWM_UL; + IOPinTypeDef *PWM_UH; + IOPinTypeDef *PWM_VL; + IOPinTypeDef *PWM_VH; + IOPinTypeDef *PWM_WL; + IOPinTypeDef *PWM_WH; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2) +{ + uint8_t tmp; + HallStates retVal = HALL_INVALID_0; + + if (hallInvert) + { + // Swap in_1 and in_2 + tmp = in_1; + in_1 = in_2; + in_2 = tmp; + } + + switch(hallOrder) + { + case 0: // U/V/W + retVal = in_0 << 0 + | in_1 << 1 + | in_2 << 2; + break; + case 1: // V/W/U + retVal = in_0 << 1 + | in_1 << 2 + | in_2 << 0; + break; + case 2: // W/U/V + retVal = in_0 << 2 + | in_1 << 0 + | in_2 << 1; + break; + } + + return retVal; +} + +static int16_t hallStateToAngle(HallStates hallState) +{ + switch (hallState) + { + case HALL_001: + return 0; + break; + case HALL_011: + return 60; + break; + case HALL_010: + return 120; + break; + case HALL_110: + return 180; + break; + case HALL_100: + return 240; + break; + case HALL_101: + return 300; + break; + default: + break; + } + + return 0; +} + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW) +{ + if (type == MEASURE_THREE_PHASES) + { + // Three phase measurement + adcCount = 3; + adcPhases[0] = ADC_SC1_ADCH(1); // ADC1_DP1 = AIN0 + adcPhases[1] = ADC_SC1_ADCH(3); // ADC1_DP3 = AIN1 + adcPhases[2] = ADC_SC1_ADCH(0); // ADC1_DP0 = AIN2 + } + else if (type == MEASURE_ONE_PHASE) + { + // One phase measurement + adcCount = 1; + adcPhases[0] = ADC_SC1_ADCH(0); // ADC1_DP0 = AIN2 + } + + Pins.PWM_UL = &HAL.IOs->pins->DIO6; + Pins.PWM_UH = &HAL.IOs->pins->DIO7; + Pins.PWM_VL = &HAL.IOs->pins->DIO8; + Pins.PWM_VH = &HAL.IOs->pins->DIO9; + Pins.PWM_WL = &HAL.IOs->pins->DIO10; + Pins.PWM_WH = &HAL.IOs->pins->DIO11; + + currentScalingFactor = currentScaling; + + Pins.HALL_U = hallU; + Pins.HALL_V = hallV; + Pins.HALL_W = hallW; + + HAL.IOs->config->toInput(Pins.HALL_U); + HAL.IOs->config->toInput(Pins.HALL_V); + HAL.IOs->config->toInput(Pins.HALL_W); + + // Calculate the openloop step time by setting the velocity + BLDC_setTargetOpenloopVelocity(openloopVelocity); + + // --- PDB --- + // Enable clock for programmable delay block (PDB) + SIM_SCGC6 |= SIM_SCGC6_PDB_MASK; + + PDB0_MOD = PWM_PERIOD - 10; + + PDB0_CH1C1 = PDB_C1_TOS(0x01) + | PDB_C1_EN(0x01); + + PDB0_CH1DLY0 = 0; + + PDB0_SC = PDB_SC_LDMOD(3) + | PDB_SC_PDBEN_MASK // enable PDB + | PDB_SC_TRGSEL(0x08) // 0x08 = FTM0 + | PDB_SC_LDOK_MASK + | PDB_SC_PDBEIE_MASK; + + enable_irq(INT_PDB0 - 16); + + // --- ADC --- + // Enable clock for ADC1 + SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK; + + // Input DADP1 + ADC1_SC1A = adcPhases[adc] | ADC_SC1_AIEN_MASK; + + // Single-ended 16 bit conversion, ADCK = Bus Clock/2 + ADC1_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + + ADC1_CFG2 = ADC_CFG2_ADHSC_MASK; + + // Hardware trigger + ADC1_SC2 = ADC_SC2_ADTRG_MASK; + + ADC1_SC3 = ADC_SC3_CAL_MASK; + while(ADC1_SC3 & ADC_SC3_CAL_MASK); + + // set ADC1 interrupt handler + enable_irq(INT_ADC1-16); + + // --- FTM --- + // Deinitialize the timer, as we're going to take FTM0 over + Timer.deInit(); + + // enable clock for FTM0 + SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; + + // disable write protection + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + + FTM0_CONF |= FTM_CONF_BDMMODE(3); // let counter run in BDM mode + + // FAULTM = 11 - Fault control is enabled for all channels (automatic fault clearing) + // FTMEN = 1 - all registers are available for use with no restrictions + FTM0_MODE |= FTM_MODE_FAULTM_MASK | FTM_MODE_FTMEN_MASK; + + // setting for Center Aligned PWM in Combine Mode + FTM0_MOD = PWM_PERIOD-1; + FTM0_CNTIN = 0x00; + FTM0_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; // set enhanced PWM sync mode + + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; // use FTM0_MOD as max loading point + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; // use software trigger as pwm synchronization trigger + + // disable all channels outputs + FTM0_OUTMASK = FTM_OUTMASK_CH7OM_MASK | FTM_OUTMASK_CH6OM_MASK | + FTM_OUTMASK_CH5OM_MASK | FTM_OUTMASK_CH4OM_MASK | + FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK; + + // COMBINE = 1 - combine mode set, COMP = 1 - complementary PWM set, + // DTEN = 1 - deadtime enabled, SYNCEN = 1 - PWM update synchronization enabled, + // FAULTEN = 1 - fault control enabled + FTM0_COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DTEN0_MASK + | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_COMBINE0_MASK + | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_DTEN2_MASK + | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_COMBINE2_MASK + | FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_DTEN3_MASK + | FTM_COMBINE_COMP3_MASK | FTM_COMBINE_COMBINE3_MASK + | FTM_COMBINE_FAULTEN0_MASK | FTM_COMBINE_FAULTEN2_MASK | FTM_COMBINE_FAULTEN3_MASK; + + // set dead time prescaler (divisor 1) and dead time + FTM0_DEADTIME = FTM_DEADTIME_DTPS(0) | FTM_DEADTIME_DTVAL(bbmTime); + + /* Initial setting of value registers */ + FTM0_C0V = 0; + FTM0_C1V = 0; + FTM0_C4V = 0; + FTM0_C5V = 0; + FTM0_C6V = 0; + FTM0_C7V = 0; + + // set channel mode to generate positive PWM + FTM0_C0SC |= FTM_CnSC_ELSB_MASK; + FTM0_C1SC |= FTM_CnSC_ELSB_MASK; + FTM0_C4SC |= FTM_CnSC_ELSB_MASK; + FTM0_C5SC |= FTM_CnSC_ELSB_MASK; + FTM0_C6SC |= FTM_CnSC_ELSB_MASK; + FTM0_C7SC |= FTM_CnSC_ELSB_MASK; + + // enable loading of the MOD, CNTIN, and CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + // enable the generation of the trigger when the FTM counter is equal to the CNTIN register + FTM0_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK; + FTM0_MODE |= FTM_MODE_INIT_MASK; + + // set system clock as source for FTM0 (CLKS[1:0] = 01) + FTM0_SC |= FTM_SC_CLKS(1); + + // enable all PWM output channels of FTM0 + FTM0_OUTMASK = 0; + + // enable FTM0 interrupt + FTM0_SC |= (uint32_t)(FTM_SC_TOIE_MASK); + + // set FTM0 interrupt handler + Timer.overflow_callback = timer_callback; + enable_irq(INT_FTM0-16); +} + +void BLDC_calibrateADCs() +{ + // Only do the offset compensation if PWM is off + if (targetPWM != 0) + return; + + // Temporarily disable the FTM interrupt to prevent it from overriding + // the adc phase selection + disable_irq(INT_FTM0-16); + + for (uint8_t myadc = 0; myadc < adcCount; myadc++) + { + adc = myadc % 3; + // Select the ADC phase for offset compensation + ADC1_SC1A = (ADC1_SC1A & (~ADC_SC1_ADCH_MASK)) | adcPhases[adc]; + + // Reset the ADC state + adcOffset[adc] = 0; + adcState[adc] = ADC_INIT; + + // Wait until the ADC is initialized again + while (adcState[adc] == ADC_INIT); + } + + enable_irq(INT_FTM0-16); +} + +void PDB0_IRQHandler() +{ + PDB0_CH1S &= ~PDB_S_ERR_MASK; + + // Re-enable the pre-trigger to clear the hardware lock + // Refer to 37.4.1: "PDB pre-trigger and trigger outputs" of the K20P100M100SF2V2RM manual + PDB0_CH1C1 &= ~PDB_C1_EN(1); + PDB0_CH1C1 |= PDB_C1_EN(1); +} + +void ADC1_IRQHandler() +{ + int32_t tmp = ADC1_RA; + static ADC_Channel lastChannel = ADC_PHASE_U; + + switch(adcState[lastChannel]) + { + case ADC_INIT: + if (sampleCount[lastChannel] < ADC_SAMPLES) + { + // Store a calibration sample + adcOffset[lastChannel] += tmp; + + sampleCount[lastChannel]++; + } + else + { + // Finished collection of calibration samples + // Calculate offset + adcOffset[lastChannel] /= ADC_SAMPLES; + + adcState[lastChannel] = ADC_READY; + sampleCount[lastChannel] = 0; + } + break; + case ADC_READY: + adcSamples[adcSampleIndex] = (tmp - adcOffset[lastChannel]) * currentScalingFactor / 65536; + adcSampleIndex = (adcSampleIndex + 1) % ARRAY_SIZE(adcSamples); + + break; + } + + if (lastChannel != adc) + { + // Update the channel + lastChannel = adc; + ADC1_SC1A = (ADC1_SC1A & (~ADC_SC1_ADCH_MASK)) | adcPhases[adc]; + } +} + +void timer_callback(void) +{ + // clear timer overflow flag + //FTM0_SC &= ~FTM_SC_TOF_MASK; + + static int32_t commutationCounter = 0; + static int32_t velocityCounter = 0; + + static int32_t lastHallAngle = 0; + static int32_t hallAngleDiffAccu = 0; + + // Measure the hall sensor + HallStates actualHallState = inputToHallState(HAL.IOs->config->isHigh(Pins.HALL_U), HAL.IOs->config->isHigh(Pins.HALL_V), HAL.IOs->config->isHigh(Pins.HALL_W)); + hallAngle = hallStateToAngle(actualHallState); + + // Calculate the hall angle difference + int32_t hallAngleDiff = (hallAngle - lastHallAngle); // [-300 ; +360) + hallAngleDiff = (hallAngleDiff + 360) % 360; // [ 0 ; +360) + hallAngleDiff = ((hallAngleDiff + 180) % 360) - 180; // [-180 ; +180) + lastHallAngle = hallAngle; + + // Accumulate the hall angle for velocity measurement + hallAngleDiffAccu += hallAngleDiff; + + // Calculate the velocity + if (++velocityCounter >= PWM_FREQ / VELOCITY_CALC_FREQ) + { + actualHallVelocity = hallAngleDiffAccu * 60 * VELOCITY_CALC_FREQ / 360; // electrical rotations per minute + + hallAngleDiffAccu = 0; + velocityCounter = 0; + } + + if (commutationMode == BLDC_OPENLOOP) + { + // open loop mode + if (openloopStepTime) + { + if (++commutationCounter >= openloopStepTime) + { + if (targetPWM > 0) + targetAngle = (targetAngle + 60) % 360; + else if (targetPWM < 0) + targetAngle = (targetAngle - 60 + 360) % 360; + + commutationCounter = 0; + } + } + } + else if (commutationMode == BLDC_HALL) + { + if (targetPWM > 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + targetAngle = ((hallAngle + 30) + 90) % 360; + } + else if (targetPWM < 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + // The +360 are to prevent a negative operand for the modulo. + targetAngle = ((hallAngle + 30) - 90 + 360) % 360; + } + else + { + targetAngle = hallAngle; + } + } + + // update commutation step + int16_t duty = ((int32_t)targetPWM * ((int32_t)PWM_PERIOD-1))/(int32_t)s16_MAX; + + if (duty < 0) + duty = -duty; + + switch (targetAngle % 360) + { + case 0: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | // off + PWM_PHASE_V_ENABLED | // high with pwm + PWM_PHASE_W_ENABLED; // low + + FTM0_C1V = 0; + FTM0_C5V = duty; + FTM0_C7V = 0; + + adc = ADC_PHASE_W; + break; + case 60: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // low + PWM_PHASE_V_ENABLED | // high with pwm + PWM_PHASE_W_DISABLED; // off + + FTM0_C1V = 0; + FTM0_C5V = duty; + FTM0_C7V = 0; + + adc = ADC_PHASE_U; + break; + case 120: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // low + PWM_PHASE_V_DISABLED | // off + PWM_PHASE_W_ENABLED; // high with pwm + + FTM0_C1V = 0; + FTM0_C5V = 0; + FTM0_C7V = duty; + + adc = ADC_PHASE_U; + break; + case 180: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | // off + PWM_PHASE_V_ENABLED | // low + PWM_PHASE_W_ENABLED; // high with pwm + + FTM0_C1V = 0; + FTM0_C5V = 0; + FTM0_C7V = duty; + + adc = ADC_PHASE_V; + break; + case 240: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // high with pwm + PWM_PHASE_V_ENABLED | // low + PWM_PHASE_W_DISABLED; // off + + FTM0_C1V = duty; + FTM0_C5V = 0; + FTM0_C7V = 0; + + adc = ADC_PHASE_V; + break; + case 300: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // high with pwm + PWM_PHASE_V_DISABLED | // off + PWM_PHASE_W_ENABLED; // low + + FTM0_C1V = duty; + FTM0_C5V = 0; + FTM0_C7V = 0; + + adc = ADC_PHASE_W; + break; + default: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | PWM_PHASE_V_DISABLED | PWM_PHASE_W_DISABLED; + break; + } + + // For one-phase measurement always use the same phase + if (adcCount == 1) + { + adc = ADC_PHASE_U; + } + + // Update PDB timing + if (duty < PWM_PERIOD/2) + { + PDB0_CH1DLY0 = duty + (PWM_PERIOD-duty)/2; + } + else + { + PDB0_CH1DLY0 = duty/2; + } + + // Update PDB and FTM registers + PDB0_SC |= PDB_SC_LDOK_MASK; + FTM0_SYNC |= FTM_SYNC_REINIT_MASK; + + // LOAD Enable: enables the loading of the MOD, CNTIN, and + // CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +void BLDC_enablePWM(uint8_t enable) +{ + if (enable) + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_Mode_AF4; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OType_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + HAL.IOs->config->set(Pins.PWM_UH); + + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 1; + } + else + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_Mode_IN; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OType_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PuPd_DOWN; + + HAL.IOs->config->set(Pins.PWM_UH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 0; + } +} + +uint8_t BLDC_isPWMenabled() +{ + return pwmEnabled; +} + +void BLDC_setTargetPWM(int16_t pwm) +{ + targetPWM = pwm; +} + +int16_t BLDC_getTargetPWM() +{ + return targetPWM; +} + +int32_t BLDC_getMeasuredCurrent() +{ + int32_t sum = 0; + for (uint8_t i = 0; i < ARRAY_SIZE(adcSamples); i++) + { + sum += adcSamples[i]; + } + + return sum / (int32_t) ARRAY_SIZE(adcSamples); +} + +void BLDC_setCommutationMode(BLDCMode mode) +{ + commutationMode = mode; +} + +BLDCMode BLDC_getCommutationMode() +{ + return commutationMode; +} + +void BLDC_setPolePairs(uint8 polePairs) +{ + if (polePairs == 0) + return; + + motorPolePairs = polePairs; +} + +uint8_t BLDC_getPolePairs() +{ + return motorPolePairs; +} + +void BLDC_setOpenloopStepTime(uint16_t stepTime) +{ + openloopStepTime = stepTime; +} + +uint16_t BLDC_getOpenloopStepTime() +{ + return openloopStepTime; +} + +int32_t BLDC_getTargetAngle() +{ + return targetAngle; +} + +int32_t BLDC_getHallAngle() +{ + return hallAngle; +} + +// Set the open loop velocity in RPM +void BLDC_setTargetOpenloopVelocity(uint32_t velocity) +{ + // 1 [RPM] = polePairs [eRPM] + // [eRPM] = [1/60 eRPS] = 6/60 [steps/s] + // steps/s = fpwm / openloopStepTime + // + // openloopStepTime = fpwm * 60 / 6 / velocity / polePairs + openloopStepTime = PWM_FREQ * 10 / velocity / motorPolePairs; + + // Store the requested velocity for accurate reading + // Otherwise we see rounding errors when reading back. + openloopVelocity = velocity; +} + +uint32_t BLDC_getTargetOpenloopVelocity() +{ + return openloopVelocity; +} + +int32_t BLDC_getActualOpenloopVelocity() +{ + if (commutationMode != BLDC_OPENLOOP) + return 0; + + if (targetPWM > 0) + return openloopVelocity; + else if (targetPWM < 0) + return -openloopVelocity; + else + return 0; +} + +// Velocity measured by hall in RPM +int32_t BLDC_getActualHallVelocity() +{ + return actualHallVelocity / motorPolePairs; +} + +void BLDC_setHallOrder(uint8_t order) +{ + if (order < 3) + { + hallOrder = order; + } +} + +uint8_t BLDC_getHallOrder() +{ + return hallOrder; +} + +void BLDC_setHallInvert(uint8_t invert) +{ + hallInvert = (invert)? 1:0; +} + +uint8_t BLDC_getHallInvert() +{ + return hallInvert; +} + +void BLDC_setBBMTime(uint8_t time) +{ + // Clip to the maximum value instead of overflowing + bbmTime = MIN(time, 63); + + // Set dead time prescaler (divisor 1) and dead time + FTM0_DEADTIME = FTM_DEADTIME_DTPS(0) | FTM_DEADTIME_DTVAL(bbmTime); +} + +uint8_t BLDC_getBBMTime() +{ + return bbmTime; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c b/Clean_TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c new file mode 100644 index 0000000..a9933de --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c @@ -0,0 +1,760 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "BLDC.h" +#include "hal/HAL.h" +#include "hal/Timer.h" +#include "hal/ADCs.h" + +#define VELOCITY_CALC_FREQ 10 // in Hz +#define PWM_FREQ 20000 // in Hz + + /* Timer0 Frequency: + * + * CK_TIMER0 = 2 x CK_APB2 = 240MHz (APB1PSC/APB2PSC in RCU_CFG0 register is 0b101) + * + * CLK_TIMER 240MHz + * ----------- = ----- = 80MHz + * Prescaler 3 + * + */ +#define PWM_PERIOD (80000000 / PWM_FREQ)-1 + +typedef enum { + PWM_PHASE_U = TIMER_CH_0, + PWM_PHASE_V = TIMER_CH_1, + PWM_PHASE_W = TIMER_CH_2, +} PWM_Phase; + +typedef enum { + ADC_PHASE_U, + ADC_PHASE_V, + ADC_PHASE_W, +} ADC_Channel; + +uint8_t adcPhases[3] = { 0 }; +uint8_t adcCount = 3; +volatile ADC_Channel adc = ADC_PHASE_U; + +int16_t targetPWM = 0; +uint32_t openloopVelocity = 60; // mechanical RPM +uint16_t openloopStepTime = 0; // Calculate on init +BLDCMode commutationMode = BLDC_OPENLOOP; +uint8_t pwmEnabled = 0; +uint8_t bbmTime = 50; +uint8_t motorPolePairs = 1; + +int32_t targetAngle = 0; +int32_t hallAngle = 0; + +int32_t actualHallVelocity = 0; // electrical RPM + +volatile int32_t adcSamples[8] = { 0 }; +uint8_t adcSampleIndex = 0; + +int32_t adcOffset[3] = { 0 }; +uint32_t sampleCount[3] = { 0 }; + +int32_t currentScalingFactor = 256; // u24q8 format + +#define ADC_SAMPLES 100 + +typedef enum { + HALL_INVALID_0 = 0, + + HALL_001 = 1, + HALL_010 = 2, + HALL_011 = 3, + HALL_100 = 4, + HALL_101 = 5, + HALL_110 = 6, + + HALL_INVALID_1 = 7, +} HallStates; + +static int16_t hallStateToAngle(HallStates hallState); +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2); + +// Hall parameters +uint8_t hallOrder = 0; +uint8_t hallInvert = 0; + +volatile enum { + ADC_INIT, + ADC_READY +} adcState[3] = { ADC_INIT, ADC_INIT, ADC_INIT }; + +typedef struct +{ + IOPinTypeDef *HALL_U; + IOPinTypeDef *HALL_V; + IOPinTypeDef *HALL_W; + IOPinTypeDef *PWM_UL; + IOPinTypeDef *PWM_UH; + IOPinTypeDef *PWM_VL; + IOPinTypeDef *PWM_VH; + IOPinTypeDef *PWM_WL; + IOPinTypeDef *PWM_WH; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2) +{ + uint8_t tmp; + HallStates retVal = HALL_INVALID_0; + + if (hallInvert) + { + // Swap in_1 and in_2 + tmp = in_1; + in_1 = in_2; + in_2 = tmp; + } + + switch(hallOrder) + { + case 0: // U/V/W + retVal = in_0 << 0 + | in_1 << 1 + | in_2 << 2; + break; + case 1: // V/W/U + retVal = in_0 << 1 + | in_1 << 2 + | in_2 << 0; + break; + case 2: // W/U/V + retVal = in_0 << 2 + | in_1 << 0 + | in_2 << 1; + break; + } + + return retVal; +} + +static int16_t hallStateToAngle(HallStates hallState) +{ + switch (hallState) + { + case HALL_001: + return 0; + break; + case HALL_011: + return 60; + break; + case HALL_010: + return 120; + break; + case HALL_110: + return 180; + break; + case HALL_100: + return 240; + break; + case HALL_101: + return 300; + break; + default: + break; + } + + return 0; +} + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW) +{ + if (type == MEASURE_THREE_PHASES) + { + // Three phase measurement + adcCount = 3; + adcPhases[0] = ADC_CHANNEL_14; // AIN0 + adcPhases[1] = ADC_CHANNEL_15; // AIN1 + adcPhases[2] = ADC_CHANNEL_8; // AIN2 + } + else if (type == MEASURE_ONE_PHASE) + { + // One phase measurement + adcCount = 1; + adcPhases[0] = ADC_CHANNEL_8; // AIN2 + } + + //Set MUX_1 and MUX_2 to one to connect DIO10 and DIO11 to PWM pins DIO10_A and DIO11_A respectively. +// *HAL.IOs->pins->SW_UART_PWM.setBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + HAL.IOs->config->toOutput(&HAL.IOs->pins->SW_UART_PWM); + + HAL.IOs->config->setHigh(&HAL.IOs->pins->SW_UART_PWM); + + + Pins.PWM_UL = &HAL.IOs->pins->DIO6; + Pins.PWM_UH = &HAL.IOs->pins->DIO7; + Pins.PWM_VL = &HAL.IOs->pins->DIO8; + Pins.PWM_VH = &HAL.IOs->pins->DIO9; + Pins.PWM_WL = &HAL.IOs->pins->DIO10_PWM_WL; + Pins.PWM_WH = &HAL.IOs->pins->DIO11_PWM_WH; + + currentScalingFactor = currentScaling; + + Pins.HALL_U = hallU; + Pins.HALL_V = hallV; + Pins.HALL_W = hallW; + + HAL.IOs->config->toInput(Pins.HALL_U); + HAL.IOs->config->toInput(Pins.HALL_V); + HAL.IOs->config->toInput(Pins.HALL_W); + + // Calculate the openloop step time by setting the velocity + BLDC_setTargetOpenloopVelocity(openloopVelocity); + + // ADC + // Operation mode: Continuous mode on single selected channel + + rcu_periph_clock_enable(RCU_ADC1); + + adc_clock_config(ADC_ADCCK_PCLK2_DIV2); + adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT); + adc_sync_delay_config(ADC_SYNC_DELAY_5CYCLE); + adc_resolution_config(ADC1, ADC_RESOLUTION_12B); + adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE); + adc_external_trigger_config(ADC1, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE); + adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(ADC1, ADC_ROUTINE_CHANNEL, 1); + + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + + adc_interrupt_enable(ADC1, ADC_INT_EOC); + nvic_irq_enable(ADC_IRQn, 0, 1); + + adc_enable(ADC1); + + adc_calibration_enable(ADC1); + + adc_software_trigger_enable(ADC1, ADC_ROUTINE_CHANNEL); + + // Timer + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_parameter_struct params; + timer_oc_parameter_struct oc_params; + timer_break_parameter_struct break_params; + timer_deinit(TIMER0); + + timer_struct_para_init(¶ms); + params.prescaler = 2; // Divides the timer freq by (prescaler + 1) => 3 + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = PWM_PERIOD; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 1; + timer_init(TIMER0, ¶ms); + + + + timer_channel_output_struct_para_init(&oc_params); + oc_params.ocpolarity = TIMER_OC_POLARITY_HIGH; + oc_params.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + oc_params.outputstate = TIMER_CCX_ENABLE; + oc_params.outputnstate = TIMER_CCXN_ENABLE; + oc_params.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + oc_params.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; + timer_channel_output_config(TIMER0, TIMER_CH_0, &oc_params); + timer_channel_output_config(TIMER0, TIMER_CH_1, &oc_params); + timer_channel_output_config(TIMER0, TIMER_CH_2, &oc_params); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_break_struct_para_init(&break_params); + break_params.runoffstate = TIMER_ROS_STATE_ENABLE; + break_params.ideloffstate = TIMER_IOS_STATE_ENABLE; + break_params.deadtime = bbmTime; + break_params.breakpolarity = TIMER_BREAK_POLARITY_HIGH; + break_params.outputautostate = TIMER_OUTAUTO_ENABLE; + break_params.breakstate = TIMER_BREAK_DISABLE; + timer_break_config(TIMER0, &break_params); + + + timer_primary_output_config(TIMER0, ENABLE); + + timer_auto_reload_shadow_enable(TIMER0); + + timer_interrupt_enable(TIMER0, TIMER_INT_UP); + timer_update_event_enable(TIMER0); + nvic_irq_enable(TIMER0_UP_TIMER9_IRQn, 0, 1); + timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP); + + timer_enable(TIMER0); +} + +void BLDC_calibrateADCs() +{ + // Only do the offset compensation if PWM is off + if (targetPWM != 0) + return; + + // Temporarily disable the FTM interrupt to prevent it from overriding + // the adc phase selection + nvic_irq_disable(TIMER0_UP_TIMER9_IRQn); + + for (uint8_t myadc = 0; myadc < adcCount; myadc++) + { + adc = myadc % 3; + // Select the ADC phase for offset compensation + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + + // Reset the ADC state + adcOffset[adc] = 0; + adcState[adc] = ADC_INIT; + + // Wait until the ADC is initialized again + while (adcState[adc] == ADC_INIT); + } + + nvic_irq_enable(TIMER0_UP_TIMER9_IRQn, 0, 1); +} + +void ADC_IRQHandler() +{ + if(adc_interrupt_flag_get(ADC1, ADC_INT_FLAG_EOC) == SET) + { + uint16_t tmp = adc_routine_data_read(ADC1); + static ADC_Channel lastChannel = ADC_PHASE_U; + + switch(adcState[lastChannel]) + { + case ADC_INIT: + if (sampleCount[lastChannel] < ADC_SAMPLES) + { + // Store a calibration sample + adcOffset[lastChannel] += tmp; + + sampleCount[lastChannel]++; + } + else + { + // Finished collection of calibration samples + // Calculate offset + adcOffset[lastChannel] /= ADC_SAMPLES; + + adcState[lastChannel] = ADC_READY; + sampleCount[lastChannel] = 0; + } + break; + case ADC_READY: + adcSamples[adcSampleIndex] = (tmp - adcOffset[lastChannel]) * currentScalingFactor / 65536; + adcSampleIndex = (adcSampleIndex + 1) % ARRAY_SIZE(adcSamples); + + break; + } + + if (lastChannel != adc) + { + // Update the channel + lastChannel = adc; + + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + } + + adc_interrupt_flag_clear(ADC1, ADC_INT_FLAG_EOC); + } +} + +void TIMER0_UP_TIMER9_IRQHandler(void) +{ + if(timer_interrupt_flag_get(TIMER0, TIMER_INT_FLAG_UP) == SET) + { + static int32_t commutationCounter = 0; + static int32_t velocityCounter = 0; + + static int32_t lastHallAngle = 0; + static int32_t hallAngleDiffAccu = 0; + + // Measure the hall sensor + HallStates actualHallState = inputToHallState(HAL.IOs->config->isHigh(Pins.HALL_U), HAL.IOs->config->isHigh(Pins.HALL_V), HAL.IOs->config->isHigh(Pins.HALL_W)); + hallAngle = hallStateToAngle(actualHallState); + + // Calculate the hall angle difference + int32_t hallAngleDiff = (hallAngle - lastHallAngle); // [-300 ; +360) + hallAngleDiff = (hallAngleDiff + 360) % 360; // [ 0 ; +360) + hallAngleDiff = ((hallAngleDiff + 180) % 360) - 180; // [-180 ; +180) + lastHallAngle = hallAngle; + + // Accumulate the hall angle for velocity measurement + hallAngleDiffAccu += hallAngleDiff; + + // Calculate the velocity + if (++velocityCounter >= PWM_FREQ / VELOCITY_CALC_FREQ) + { + actualHallVelocity = hallAngleDiffAccu * 60 * VELOCITY_CALC_FREQ / 360; // electrical rotations per minute + + hallAngleDiffAccu = 0; + velocityCounter = 0; + } + + if (commutationMode == BLDC_OPENLOOP) + { + // open loop mode + if (openloopStepTime) + { + if (++commutationCounter >= openloopStepTime) + { + if (targetPWM > 0) + targetAngle = (targetAngle + 60) % 360; + else if (targetPWM < 0) + targetAngle = (targetAngle - 60 + 360) % 360; + + commutationCounter = 0; + } + } + } + else if (commutationMode == BLDC_HALL) + { + if (targetPWM > 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + targetAngle = ((hallAngle + 30) + 90) % 360; + } + else if (targetPWM < 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + // The +360 are to prevent a negative operand for the modulo. + targetAngle = ((hallAngle + 30) - 90 + 360) % 360; + } + else + { + targetAngle = hallAngle; + } + } + + // update commutation step + int16_t duty = ((int32_t)targetPWM * ((int32_t)PWM_PERIOD))/(int32_t)s16_MAX; + + if (duty < 0) + duty = -duty; + + switch (targetAngle % 360) + { + case 0: + // U: Disabled + // V: PWM + // W: GND + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_W; + break; + case 60: + // U: GND + // V: PWM + // W: Disabled + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_U; + break; + case 120: + // U: GND + // V: Disabled + // W: PWM + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, duty); + + adc = ADC_PHASE_U; + break; + case 180: + // U: Disabled + // V: GND + // W: PWM + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, duty); + + adc = ADC_PHASE_V; + break; + case 240: + // U: PWM + // V: GND + // W: Disabled + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_V; + break; + case 300: + // U: PWM + // V: Disabled + // W: GND + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_W; + break; + default: + // Disable all phases + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + break; + } + + // For one-phase measurement always use the same phase + if (adcCount == 1) + { + adc = ADC_PHASE_U; + } + + timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP); + } +} + +void BLDC_enablePWM(uint8_t enable) +{ + if (enable) + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_MODE_AF; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OTYPE_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PUPD_NONE; + gpio_af_set(Pins.PWM_UH->port, GPIO_AF_1, Pins.PWM_UH->bitWeight); + HAL.IOs->config->set(Pins.PWM_UH); + + gpio_af_set(Pins.PWM_UL->port, GPIO_AF_1, Pins.PWM_UL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + gpio_af_set(Pins.PWM_VH->port, GPIO_AF_1, Pins.PWM_VH->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + gpio_af_set(Pins.PWM_VL->port, GPIO_AF_1, Pins.PWM_VL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + gpio_af_set(Pins.PWM_WH->port, GPIO_AF_1, Pins.PWM_WH->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + gpio_af_set(Pins.PWM_WL->port, GPIO_AF_1, Pins.PWM_WL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 1; + } + else + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_MODE_INPUT; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OTYPE_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PUPD_PULLDOWN; + + HAL.IOs->config->set(Pins.PWM_UH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 0; + } +} + +uint8_t BLDC_isPWMenabled() +{ + return pwmEnabled; +} + +void BLDC_setTargetPWM(int16_t pwm) +{ + targetPWM = pwm; +} + +int16_t BLDC_getTargetPWM() +{ + return targetPWM; +} + +int32_t BLDC_getMeasuredCurrent() +{ + int32_t sum = 0; + for (uint8_t i = 0; i < ARRAY_SIZE(adcSamples); i++) + { + sum += adcSamples[i]; + } + + return sum / (int32_t) ARRAY_SIZE(adcSamples); +} + +void BLDC_setCommutationMode(BLDCMode mode) +{ + commutationMode = mode; +} + +BLDCMode BLDC_getCommutationMode() +{ + return commutationMode; +} + +void BLDC_setPolePairs(uint8 polePairs) +{ + if (polePairs == 0) + return; + + motorPolePairs = polePairs; +} + +uint8_t BLDC_getPolePairs() +{ + return motorPolePairs; +} + +void BLDC_setOpenloopStepTime(uint16_t stepTime) +{ + openloopStepTime = stepTime; +} + +uint16_t BLDC_getOpenloopStepTime() +{ + return openloopStepTime; +} + +int32_t BLDC_getTargetAngle() +{ + return targetAngle; +} + +int32_t BLDC_getHallAngle() +{ + return hallAngle; +} + +// Set the open loop velocity in RPM +void BLDC_setTargetOpenloopVelocity(uint32_t velocity) +{ + // 1 [RPM] = polePairs [eRPM] + // [eRPM] = [1/60 eRPS] = 6/60 [steps/s] + // steps/s = fpwm / openloopStepTime + // + // openloopStepTime = fpwm * 60 / 6 / velocity / polePairs + openloopStepTime = PWM_FREQ * 10 / velocity / motorPolePairs; + + // Store the requested velocity for accurate reading + // Otherwise we see rounding errors when reading back. + openloopVelocity = velocity; +} + +uint32_t BLDC_getTargetOpenloopVelocity() +{ + return openloopVelocity; +} + +int32_t BLDC_getActualOpenloopVelocity() +{ + if (commutationMode != BLDC_OPENLOOP) + return 0; + + if (targetPWM > 0) + return openloopVelocity; + else if (targetPWM < 0) + return -openloopVelocity; + else + return 0; +} + +// Velocity measured by hall in RPM +int32_t BLDC_getActualHallVelocity() +{ + return actualHallVelocity / motorPolePairs; +} + +void BLDC_setHallOrder(uint8_t order) +{ + if (order < 3) + { + hallOrder = order; + } +} + +uint8_t BLDC_getHallOrder() +{ + return hallOrder; +} + +void BLDC_setHallInvert(uint8_t invert) +{ + hallInvert = (invert)? 1:0; +} + +uint8_t BLDC_getHallInvert() +{ + return hallInvert; +} + +void BLDC_setBBMTime(uint8_t time) +{ + // Clip to the maximum value instead of overflowing + bbmTime = MAX(127, time); + + TIMER_CCHP(TIMER0) = (TIMER_CCHP(TIMER0) & (~(uint32_t)TIMER_CCHP_DTCFG)) | + (((uint32_t)TIMER_CCHP_DTCFG) & bbmTime); +} + +uint8_t BLDC_getBBMTime() +{ + return bbmTime; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.c b/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.c new file mode 100644 index 0000000..33bcb14 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.c @@ -0,0 +1,193 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/derivative.h" +#include "hal/HAL.h" + +#include "TMCL.h" +#include "IdDetection.h" +#include "EEPROM.h" +#include "BoardAssignment.h" + +static uint8_t assignCh1(uint8_t id, uint8_t justCheck); +static uint8_t assignCh2(uint8_t id, uint8_t justCheck); +static void hookDriverSPI(IdAssignmentTypeDef *ids); +static void unassign(IdAssignmentTypeDef *ids); + +int32_t Board_assign(IdAssignmentTypeDef *ids) +{ + int32_t out = 0; + + // Test mode // todo REM 2: still needed? (LH) + if((ids->ch1.id == 0xFF) || (ids->ch2.id == 0xFF)) + { + if((Evalboards.ch1.id != 0) || (Evalboards.ch2.id != 0) || (ids->ch1.id != ids->ch2.id)) + { + ids->ch1.state = ID_STATE_NOT_IN_FW; + ids->ch2.state = ID_STATE_NOT_IN_FW; + out |= ids->ch2.state << 24; + out |= ids->ch2.id << 16; + out |= ids->ch1.state << 8; + out |= ids->ch1.id << 0; + return out; + } + } + + // Assign motion controller + if((Evalboards.ch1.id == ids->ch1.id) && (ids->ch1.id != 0)) + { // todo CHECK 2: Evalboards.ch_.id only gets written at the end of this function - so the only way we can reach this case by calling this function multiple times. + // Therefor, the else case always runs before, which means any information returned by the justCheck = true call here would have already been + // given by the previous call of this function. This entire ID detection procedure is kinda messy, maybe we can actually completely rework it (LH) + ids->ch1.state = assignCh1(ids->ch1.id, true); + } + else + { + Evalboards.ch1.deInit(); // todo REM 2: Hot-Unplugging is not maintained currently, should probably be removed (LH) #1 + if(ids->ch1.state == ID_STATE_DONE) + ids->ch1.state = assignCh1(ids->ch1.id, false); + Evalboards.ch1.config->reset(); + } + + // Assign driver + if((Evalboards.ch2.id == ids->ch2.id) && (ids->ch2.id != 0)) + { + ids->ch2.state = assignCh2(ids->ch2.id, true); + } + else + { + Evalboards.ch2.deInit(); // todo REM 2: Hot-Unplugging is not maintained currently, should probably be removed (LH) #2 + if(ids->ch2.state == ID_STATE_DONE) + ids->ch2.state = assignCh2(ids->ch2.id, false); + Evalboards.ch2.config->reset(); + } + + // Reroute SPI 2 (that the driver uses) to run through the motion controller if required + // This allows the chaining of a motion controller and a driver. + // Note that the motion controller has to invoke reset() or restore() of the driver + // in order to have settings sent through the hooked SPI. + // This is currently done on completed motion controller reset/restore + hookDriverSPI(ids); + + Evalboards.ch1.id = ids->ch1.id; + Evalboards.ch2.id = ids->ch2.id; + + out |= (ids->ch2.state << 24) & 0xFF; + out |= (ids->ch2.id << 16) & 0xFF; + out |= (ids->ch1.state << 8) & 0xFF; + out |= (ids->ch1.id << 0) & 0xFF; + + return out; +} + +int32_t Board_supported(IdAssignmentTypeDef *ids) +{ + int32_t out = 0; + + ids->ch1.state = assignCh1(ids->ch1.id, true); + ids->ch2.state = assignCh2(ids->ch2.id, true); + + out |= ids->ch2.state << 24; + out |= ids->ch2.id << 16; + out |= ids->ch1.state << 8; + out |= ids->ch1.id << 0; + + return out; +} + +static uint8_t assignCh1(uint8_t id, uint8_t justCheck) +{ + uint8_t ok = ID_STATE_NOT_IN_FW; + if(!justCheck) + tmcmotioncontroller_init(); + + for(size_t i = 0, sz = ARRAY_SIZE(init_ch1); i < sz; i++) + { + if(init_ch1[i].id == id) + { + if(!justCheck) + init_ch1[i].init(); + ok = ID_STATE_DONE; + break; + } + } + + return ok; +} + +static uint8_t assignCh2(uint8_t id, uint8_t justCheck) +{ + uint8_t ok = ID_STATE_NOT_IN_FW; + +// if(!justCheck) +// tmcdriver_init(); + + for(size_t i = 0, sz = ARRAY_SIZE(init_ch2); i < sz; i++) + { + if(init_ch2[i].id == id) + { + if(!justCheck) + init_ch2[i].init(); + ok = ID_STATE_DONE; + break; + } + } + + return ok; +} + +// Reroute the driver's SPI to run through the motion controller if required +// This also handles special case logic for the motion controller + driver chain (different pins etc.) +static void hookDriverSPI(IdAssignmentTypeDef *ids) +{ + if(ids->ch1.id == ID_TMC4361A) + { + // Redirect ch2 SPI to the SPI cover function of the TMC43XX Board + HAL.SPI->ch2.readWrite = Evalboards.ch1.cover; + + if(ids->ch2.id == ID_TMC2660) + { + // TMC2660: Disable the continuous mode via userFunction + int32_t value = 1; + Evalboards.ch2.userFunction(0, 0, &value); + } + } + + + if (ids->ch1.id == ID_TMC4361A) + { + if (ids->ch2.id == ID_TMC2130) + { + Evalboards.ch2.userFunction(6, 0, NULL); + } + } +} + +static void unassign(IdAssignmentTypeDef *ids) +{ + UNUSED(ids); +} + +void periodicJob(uint32_t tick) +{ + UNUSED(tick); +} + +void deInit(void) +{ + IdAssignmentTypeDef ids; + Evalboards.ch1.deInit(); + Evalboards.ch2.deInit(); + + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + unassign(&ids); + + tmcdriver_init(); + tmcmotioncontroller_init(); +} diff --git a/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.h b/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.h new file mode 100644 index 0000000..1421c65 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/BoardAssignment.h @@ -0,0 +1,187 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef BOARD_ASSIGNMENT_H +#define BOARD_ASSIGNMENT_H + +#include "boards/Board.h" + +typedef enum { + FOUND_BY_NONE, + FOUND_BY_MONOFLOP, + FOUND_BY_EEPROM +} IDFinder; + +typedef struct +{ + uint8_t state; // detection state of this board + uint8_t id; // id of board + IDFinder detectedBy; // Holds the method used to detect the ID (Monoflop or EEPROM) + uint32_t counter_1; // Timer cycles elapsed on ID pulse rising edge + uint32_t counter_2; // Timer cycles elapsed on ID pulse falling edge + uint32_t timer_1; // Current timer value on ID pulse rising edge + uint32_t timer_2; // Current timer value on ID pulse falling edge +} IdStateTypeDef; // interface for id and detection state of a board + +typedef struct +{ + IdStateTypeDef ch1; // interface for id and detection state for the driver board + IdStateTypeDef ch2; // interface for id and detection state for the motion controller board +} IdAssignmentTypeDef; // interface for id and detection state of driver and motion controller board + +extern IdAssignmentTypeDef IdState; + +int32_t Board_assign(IdAssignmentTypeDef *ids); // ids and states of assigned driver and motion controller board +int32_t Board_supported(IdAssignmentTypeDef *ids); // ids and states of supported driver and motion controller board + +#include "boards/SelfTest.h" + +// ids for channel 0 +#define ID_ERROR 0 +#define ID_TMC5031 2 +#define ID_TMC5130 5 +#define ID_TMC5041 6 +#define ID_TMC5072 7 +#define ID_TMC4361A 11 +#define ID_TMC4671 13 +#define ID_TMC5160 16 +#define ID_TMC5062 25 +#define ID_TMC8460 8 +#define ID_TMC8461 26 +#define ID_TMC8462 27 +#define ID_TMC5240 28 +#define ID_TMC5272 29 +#define ID_TMC5271 31 +#define ID_TMC2130_TQFP48 0xFE +#define ID_SELFTEST 255 + +// ids for channel 1 +#define ID_TMC2660 1 +#define ID_TMC2130 3 +#define ID_TMC2100 4 +#define ID_TMC2208 6 +#define ID_TMC2224 7 +#define ID_TMC6200 10 +#define ID_TMC2160 11 +#define ID_TMC2240 28 +#define ID_TMC7300 12 +#define ID_TMC2590 13 +#define ID_TMC6100 19 +#define ID_TMC6100_BOB 25 // For the TMC4671+TMC6100-BOB +#define ID_TMC2210 29 +#define ID_TMC2209 8 +#define ID_TMC2225 18 +#define ID_TMC2300 14 +#define ID_TMC2226 22 +#define ID_MAX22216_EVAL 30 +#define ID_MAX22216_BOB 31 +#define ID_MAX22204_EVAL 32 +#define ID_MAX22210_EVAL 33 +#define ID_TMC6300 21 +#define ID_TMC6140 23 +#define ID_TMC8100 34 + + +// init() functions for all boards - function definitions are in the respective _eval file of a chip +extern void MAX22216_init(); +extern void MAX22204_init(); +extern void MAX22210_init(); +extern void TMC2100_init(); +extern void TMC2130_init(); +extern void TMC2160_init(); +extern void TMC2208_init(); +extern void TMC2209_init(); +extern void TMC2210_init(); +extern void TMC2224_init(); +extern void TMC2225_init(); +extern void TMC2226_init(); +extern void TMC2240_init(); +extern void TMC2300_init(); +extern void TMC2590_init(); +extern void TMC2660_init(); +extern void TMC4361A_init(); +extern void TMC4671_init(); +extern void TMC5031_init(); +extern void TMC5041_init(); +extern void TMC5062_init(); +extern void TMC5072_init(); +extern void TMC5130_init(); +extern void TMC5160_init(); +extern void TMC5240_init(); +extern void TMC5271_init(); +extern void TMC5272_init(); +extern void TMC6100_init(); +extern void TMC6100_BOB_init(); +extern void TMC6140_init(); +extern void TMC6200_init(); +extern void TMC6300_init(); +extern void TMC7300_init(); +extern void TMC8100_init(); +extern void TMC8461_init_ch1(); +extern void TMC8461_init_ch2(); +extern void TMC8462_init_ch1(); +extern void TMC8462_init_ch2(); +extern void SelfTest_init(); + +#if defined(LandungsbrueckeV3) + extern void PD8_IRQHandler(); +#endif + +typedef struct { + uint16_t id; + void (*init)(void); +} init_assignment; + +static const init_assignment init_ch1[] = +{ + { .id = ID_TMC5031, .init = TMC5031_init }, + { .id = ID_TMC5130, .init = TMC5130_init }, + { .id = ID_TMC5041, .init = TMC5041_init }, + { .id = ID_TMC5072, .init = TMC5072_init }, + { .id = ID_TMC4361A, .init = TMC4361A_init }, + { .id = ID_TMC4671, .init = TMC4671_init }, + { .id = ID_TMC5160, .init = TMC5160_init }, + { .id = ID_TMC5240, .init = TMC5240_init }, + { .id = ID_TMC5271, .init = TMC5271_init }, + { .id = ID_TMC5272, .init = TMC5272_init }, + { .id = ID_TMC5062, .init = TMC5062_init }, + { .id = ID_TMC8461, .init = TMC8461_init_ch1 }, + { .id = ID_TMC8462, .init = TMC8462_init_ch1 }, + { .id = ID_SELFTEST, .init = SelfTest_init } +}; + +static const init_assignment init_ch2[] = +{ + { .id = ID_TMC2660, .init = TMC2660_init }, + { .id = ID_TMC2130, .init = TMC2130_init }, + { .id = ID_TMC2100, .init = TMC2100_init }, + { .id = ID_TMC2208, .init = TMC2208_init }, + { .id = ID_TMC2224, .init = TMC2224_init }, + { .id = ID_TMC2240, .init = TMC2240_init }, + { .id = ID_TMC2590, .init = TMC2590_init }, + { .id = ID_TMC6100, .init = TMC6100_init }, + { .id = ID_TMC6100_BOB, .init = TMC6100_BOB_init }, + { .id = ID_TMC6200, .init = TMC6200_init }, + { .id = ID_TMC7300, .init = TMC7300_init }, + { .id = ID_TMC2160, .init = TMC2160_init }, + { .id = ID_TMC2210, .init = TMC2210_init }, + { .id = ID_MAX22216_EVAL, .init = MAX22216_init }, + { .id = ID_MAX22216_BOB, .init = MAX22216_init }, + { .id = ID_MAX22204_EVAL, .init = MAX22204_init }, + { .id = ID_MAX22210_EVAL, .init = MAX22210_init }, + { .id = ID_TMC2209, .init = TMC2209_init }, + { .id = ID_TMC2225, .init = TMC2225_init }, + { .id = ID_TMC2226, .init = TMC2226_init }, + { .id = ID_TMC2300, .init = TMC2300_init }, + { .id = ID_TMC6300, .init = TMC6300_init }, + { .id = ID_TMC6140, .init = TMC6140_init }, + { .id = ID_TMC8100, .init = TMC8100_init }, +}; + +#endif /* BOARD_ASSIGNMENT_H */ diff --git a/Clean_TMC2209/lib/tmc/tmc/EEPROM.c b/Clean_TMC2209/lib/tmc/tmc/EEPROM.c new file mode 100644 index 0000000..19dc666 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/EEPROM.c @@ -0,0 +1,322 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "EEPROM.h" +#include + +EEPROM_Channels EEPROM = +{ + .ch1 = + { + .init = false, + .name = { 0 }, + .id = 0, + .hw = 0, + .magic = 0 + }, + .ch2 = + { + .init = false, + .name = { 0 }, + .id = 0, + .hw = 0, + .magic = 0 + } +}; + +// Perform initial scan and store to struct +void eeprom_init(SPIChannelTypeDef *SPIChannel) +{ + uint8_t buffer[EEPROM_SIZE_META] = { 0 }; + EEPROM_Data *eep = (SPIChannel == &SPI.ch1) ? &EEPROM.ch1 : &EEPROM.ch2; + eeprom_read_array(SPIChannel, EEPROM_ADDR_META, buffer, EEPROM_SIZE_META); + memcpy(eep->name, &buffer[EEPROM_ADDR_NAME - EEPROM_ADDR_META], EEPROM_SIZE_NAME); + eep->id = _8_16(buffer[EEPROM_ADDR_ID - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_ID + 1) - EEPROM_ADDR_META]); + eep->hw = _8_16(buffer[EEPROM_ADDR_HW - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_HW + 1) - EEPROM_ADDR_META]); + eep->magic = _8_16(buffer[EEPROM_ADDR_MAGIC - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_MAGIC + 1) - EEPROM_ADDR_META]); + eep->init = true; +// eeprom_read_array(&SPI.ch2, EEPROM_ADDR_META, buffer, EEPROM_SIZE_META); +// memcpy(EEPROM.ch2.name, &buffer[EEPROM_ADDR_NAME - EEPROM_ADDR_META], EEPROM_SIZE_NAME); +// EEPROM.ch2.id = _8_16(buffer[EEPROM_ADDR_ID - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_ID + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.hw = _8_16(buffer[EEPROM_ADDR_HW - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_HW + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.magic = _8_16(buffer[EEPROM_ADDR_MAGIC - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_MAGIC + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.init = true; +} + +/******************************************************************* + Function: eeprom_check + Parameters: SPI channel the Eeprom should be checked on + + Returns: false when an Eeprom has been successfully detected and is in ready status + The status of the eeprom otherwise + + Purpose: checking whether Eeprom is connected and ready +********************************************************************/ +uint8_t eeprom_check(SPIChannelTypeDef *SPIChannel) +{ + // Prüfen, ob der SPI-Bus schon funktioniert: Im Status-Register des EEPROMs + // müssen Bit 6, 5, 4 und 0 auf jedem Fall 0 sein und nicht 1. + // Watchdog darf an dieser Stelle ruhig zuschlagen. + + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + uint8_t out = SPIChannel->readWrite(0x00, true); + // check whether bits 6, 5, 4 and 0 are cleared + if((out & 0x71) != 0) + goto end; + + out = 0; + + //check for magic number in eeprom + uint8_t number[2]; + + eeprom_read_array(SPIChannel, EEPROM_ADDR_MAGIC, number, 2); + + if(number[0] != MAGICNUMBER_LOW || number[1] != MAGICNUMBER_HIGH) + { + out = ID_CHECKERROR_MAGICNUMBER; + } + + end: + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; + + if(out && ((SPIChannel == &SPI.ch1 && !EEPROM.ch1.init) + || (SPIChannel == &SPI.ch2 && !EEPROM.ch2.init))) { + eeprom_init(SPIChannel); + } + + return out; +} + + +/******************************************************************* + Funktion: eeprom_write_byte + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + value: der zu schreibende Wert + + Rückgabewert: --- + + Zweck: Schreiben eines Bytes in das EEPROM auf dem Evalboard. +********************************************************************/ +void eeprom_write_byte(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t value) +{ + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + EEPROM.ch1.init = false; + } else { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + EEPROM.ch2.init = false; + } + + IOs.toOutput(SPIChannel->CSN); + + // Schreiben erlauben + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) == 0x00); // Warte bis "Write Enable"-Bit gesetzt ist + + // Eigentliches Schreiben + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + SPIChannel->readWrite(value, true); + + // Warten bis Schreibvorgang beendet ist + do + { + SPIChannel->readWrite(0x05, false); //Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + //block writing + SPIChannel->readWrite(0x04, true); //Befehl "Write Disable" + do + { + SPIChannel->readWrite(0x05, false); //Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) != 0x00); //Warte bis "Write Enable"-Bit zurückgesetzt wird + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} + + +/******************************************************************* + Funktion: eeprom_write_array + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + data: Startadresse des zu schreibenden Blocks + size: Länge des Blocks in Bytes + + Rückgabewert: --- + + Zweck: Schreiben mehrerer Bytes in das EEPROM auf dem Evalboard. + Dabei können beliebig viele Bytes (also auch das gesamte EEPROM + beschrieben werden (die speziellen Eigenschaften des 25128 werden + dabei beachtet). +********************************************************************/ +void eeprom_write_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size) +{ + uint16_t i; + + //select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + EEPROM.ch1.init = false; + } else { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + EEPROM.ch2.init = false; + } + + IOs.toOutput(SPIChannel->CSN); + + // Schreiben erlauben + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite( 0x05, false); //Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02)==0x00); //Warte bis "Write Enable"-Bit gesetzt + + // Schreibvorgang (Startadresse) + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + // Eigentliches Schreiben der Daten + for(i = 0; i < size; i++) + { + // Adresse mitzählen und bei Ãœberlauf der untersten sechs Bits das EEPROM deselektieren + // und neuen Write-Befehl senden (bzw. beim letzten Datenbyte einfach nur EEPROM + // deselektieren). + // Dies ist erforderlich, da beim Beschreiben im 25128 nur die untersten sechs Bits der + // Adresse hochgezählt werden (anders als beim Lesen). + address++; + SPIChannel->readWrite(*(data+i), (address & 0x0000003F)==0 || i==size-1); + if((address & 0x0000003F)==0 && ireadWrite(0x05, false); // Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + // Neuer "Write Enable"-Befehl + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02)==0x00); //Warte bis "Write Enable"-Bit gesetzt + + // Neuer "Write"-Befehl (mit der nächsten Adresse) + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + } + } + + // Warte bis Schreibvorgang beendet + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + // block writing + SPIChannel->readWrite(0x04, true); // Befehl "Write Disable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) != 0x00); // Warte bis "Write Enable"-Bit zurückgesetzt wird + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} + + +/******************************************************************* + Funktion: eeprom_read_byte + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + + Rückgabewert: der gelesene Wert + + Zweck: Lesen eines Bytes aus dem EEPROM des Evalboards. +********************************************************************/ +uint8_t eeprom_read_byte(SPIChannelTypeDef *SPIChannel, uint16_t address) +{ + //select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x03, false); //Befehl "Read" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + uint8_t out = SPIChannel->readWrite(0, true); + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; + + return out; +} + + +/******************************************************************* + Funktion: eeprom_read_array + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + data: Startadresse des zu lesenden Blocks + size: Länge des Blocks in Bytes + + Rückgabewert: --- + + Zweck: Lesen mehrerer Bytes aus dem Konfigurations-EEPROM. + Dabei dürfen ab beliebiger Adresse beliebig viele Bytes gelesen + werden. +********************************************************************/ +void eeprom_read_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size) +{ + uint16_t i; + + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x03, false); // Befehl "Read" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + for(i = 0; i < size; i++) + *(data+i) = SPIChannel->readWrite(0, i == size-1); // beim letzten Byte EEPROM deselektieren + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/EEPROM.h b/Clean_TMC2209/lib/tmc/tmc/EEPROM.h new file mode 100644 index 0000000..f9a23b4 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/EEPROM.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_EEPROM_H_ +#define TMC_EEPROM_H_ + +#include "tmc/helpers/API_Header.h" + +#include "hal/SPI.h" +#include "hal/HAL.h" + +#define EEPROM_ADDR_NAME 0 +#define EEPROM_ADDR_ID 16 +#define EEPROM_ADDR_HW 18 +#define EEPROM_ADDR_MAGIC 20 +#define EEPROM_ADDR_META 0 + +#define EEPROM_SIZE_NAME 16 +#define EEPROM_SIZE_ID 2 +#define EEPROM_SIZE_HW 2 +#define EEPROM_SIZE_MAGIC 2 +#define EEPROM_SIZE_META (EEPROM_SIZE_NAME + EEPROM_SIZE_ID + EEPROM_SIZE_HW + EEPROM_SIZE_MAGIC) + +#define MAGICNUMBER_LOW 0x12 +#define MAGICNUMBER_HIGH 0x34 + +#define ID_CHECKERROR_MAGICNUMBER 2 + +typedef struct { + bool init; + uint8_t name[EEPROM_SIZE_NAME]; + uint16_t id; + uint16_t hw; + uint16_t magic; +} EEPROM_Data; + +typedef struct { + EEPROM_Data ch1; + EEPROM_Data ch2; +} EEPROM_Channels; + +extern EEPROM_Channels EEPROM; + +void eeprom_init(SPIChannelTypeDef *SPIChannel); + +uint8_t eeprom_check(SPIChannelTypeDef *SPIChannel); + +void eeprom_write_byte(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t value); +void eeprom_write_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size); + +uint8_t eeprom_read_byte(SPIChannelTypeDef *SPIChannel, uint16_t address); +void eeprom_read_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *block, uint16_t size); + +#endif /* TMC_EEPROM_H_ */ diff --git a/Clean_TMC2209/lib/tmc/tmc/IdDetection.h b/Clean_TMC2209/lib/tmc/tmc/IdDetection.h new file mode 100644 index 0000000..22e1b4c --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/IdDetection.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef ID_DETECTION_H +#define ID_DETECTION_H + + #include "BoardAssignment.h" + + // id detection state definitions + #define ID_STATE_WAIT_LOW 0 // id detection waiting for first edge (currently low) + #define ID_STATE_WAIT_HIGH 1 // id detection waiting for second edge (currently high) + #define ID_STATE_DONE 2 // id detection finished successfully + #define ID_STATE_INVALID 3 // id detection failed - we got an answer, but no corresponding ID (invalid ID pulse length) + #define ID_STATE_NO_ANSWER 4 // id detection failed - board doesn't answer + #define ID_STATE_TIMEOUT 5 // id detection failed - board id pulse went high but not low + #define ID_STATE_NOT_IN_FW 6 // id detection detected a valid id that is not supported in this firmware + + void IDDetection_init(void); + void IDDetection_deInit(void); + uint8_t IDDetection_detect(IdAssignmentTypeDef *out); + void IDDetection_initialScan(IdAssignmentTypeDef *ids); + +#endif /* ID_DETECTION_H */ diff --git a/Clean_TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c b/Clean_TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c new file mode 100644 index 0000000..883b643 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c @@ -0,0 +1,415 @@ +/******************************************************************************* +* Copyright © 2013 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * Calling IDDetection_detect(IdAssignmentTypeDef *result) will start the ID detection process. + * The function returns the ID Results through the IdAssignmentTypeDef struct result points to. + * The detection will be done by monoflop pulse duration measurement or via EEPROM readout. + * While this process is still ongoing the function will return ID_STATE_WAIT_HIGH. Once the + * ID detection of both channels has been finished, ID_STATE_DONE will be returned. + * + * Calling the function again after the detection has finished will start another scan. + */ + +#include "tmc/helpers/API_Header.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "BoardAssignment.h" +#include "EEPROM.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "TMCL.h" + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids); +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids); + +// Helper macros +#define ID_CLK_LOW() HAL.IOs->config->setLow(&HAL.IOs->pins->ID_CLK); // set id clk signal to low +#define ID_CLK_HIGH() HAL.IOs->config->setHigh(&HAL.IOs->pins->ID_CLK); // set id clk signal to high +#define IDSTATE_SCAN_DONE(ID_STATE) \ + ( \ + (ID_STATE.ch1.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch1.state != ID_STATE_WAIT_HIGH) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_HIGH) \ + ) + +static uint8_t assign(uint32_t pulse); + +typedef enum { + MONOFLOP_INIT, + MONOFLOP_SCANNING, + MONOFLOP_DONE, + + MONOFLOP_END +} State_MonoflopDetection; + +State_MonoflopDetection monoflopState = MONOFLOP_INIT; + +/* Timer Frequency: + * System Clock 48MHz + * ------------ = ----- = 6MHz + * Prescaler 8 + * + * Calculate time interval (t_id) in 0.1µs from the timer tick difference (ticks): + * 0.1s 10s + * t_id * 0.1µs = ---- = ticks * 6MHz * --- <--- Tick Conversion factor: 10/6 + * 10^6 6 + */ +#define TICK_FACTOR 10/6 + +IdAssignmentTypeDef IdState = { 0 }; + +// Interrupt: Edge on GPIO Port B +void PORTB_IRQHandler(void) +{ + // Store the timing values + uint32_t timerVal = FTM2_CNT; + + // Store the interrupt flag state and then reset the flags + uint32_t interruptFlags = PORTB_ISFR; + PORTB_ISFR = PORT_ISFR_ISF_MASK; + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + // ======== CH0 ========== + // Check if Pin ID_CH0 generated the interrupt + if(interruptFlags & PORT_ISFR_ISF(HAL.IOs->pins->ID_CH0.bitWeight)) + { + if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Second ID pulse edge - store timer values -> state DONE + IdState.ch1.timer_2 = timerVal; + IdState.ch1.counter_2 = 0; + IdState.ch1.state = ID_STATE_DONE; + } + else + { // First ID pulse edge - store timer values -> state WAIT_HIGH + IdState.ch1.timer_1 = timerVal; + IdState.ch1.counter_1 = 0; + IdState.ch1.state = ID_STATE_WAIT_HIGH; + } + } + + // ======== CH1 ========== + // Check if Pin ID_CH1 generated the interrupt + if(interruptFlags & PORT_ISFR_ISF(HAL.IOs->pins->ID_CH1.bitWeight)) + { + if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Second ID pulse edge - store timer values -> state DONE + IdState.ch2.timer_2 = timerVal; + IdState.ch2.counter_2 = 0; + IdState.ch2.state = ID_STATE_DONE; + } + else + { // First ID pulse edge - store timer values -> state WAIT_HIGH + IdState.ch2.timer_1 = timerVal; + IdState.ch2.counter_1 = 0; + IdState.ch2.state = ID_STATE_WAIT_HIGH; + } + } +} + +void FTM2_IRQHandler() +{ + // clear timer overflow flag + FTM2_SC &= ~FTM_SC_TOF_MASK; + + // Stop the timer + FTM2_SC &= ~FTM_SC_CLKS_MASK; + + // Abort if we're not scanning + if(monoflopState == MONOFLOP_SCANNING) + { + monoflopState = MONOFLOP_DONE; + return; + } +} + +void IDDetection_init(void) +{ + monoflopState = MONOFLOP_INIT; + + + // ====== Timer initialisation ======= + // Enable clock for FTM2 + SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; + + // Disable write protection, FTM specific registers are available + FTM2_MODE |= FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK | FTM_MODE_FAULTM_MASK; + + // Clear the CLKS field to avoid buffered write issues for MOD + FTM2_SC &= ~FTM_SC_CLKS_MASK; + + // Use the full time period available + FTM2_MOD = 0xFFFF; + FTM2_CNTIN = 0; + FTM2_CNT = 0; + + // Clock source: System Clock (48 MHz), Prescaler: 8 -> 6 MHz Timer clock + FTM2_SC |= FTM_SC_CLKS(1) | FTM_SC_PS(3); + + // The TOF bit is set for each counter overflow + FTM2_CONF |= FTM_CONF_NUMTOF(0); + + // Edge-Aligned PWM (EPWM) mode + FTM2_C0SC |= FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK; + + // Enable FTM2 Timer Overflow interrupt + FTM2_SC |= FTM_SC_TOIE_MASK; + + // Set FTM2 interrupt handler + enable_irq(INT_FTM2 - 16); + + // ====== Pin initialisation ====== + // Enable Clock gating on port B + SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; + + // Configure Pin + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CLK); + + // Enable GPIO, edge-triggered interrupt, and PullUp + PORT_PCR_REG(HAL.IOs->pins->ID_CH0.portBase, HAL.IOs->pins->ID_CH0.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + PORT_PCR_REG(HAL.IOs->pins->ID_CH1.portBase, HAL.IOs->pins->ID_CH1.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + + // Clear interrupt flags + PORTB_ISFR = -1; + + // Enable interrupt + enable_irq(INT_PORTB - 16); +} + +void IDDetection_deInit() +{ + disable_irq(INT_FTM2 - 16); + FTM2_SC &= ~FTM_SC_CLKS_MASK; + FTM2_SC &= ~FTM_SC_TOF_MASK; + + disable_irq(INT_PORTB - 16); + PORTB_ISFR = -1; +} + +//returns ID assigned to given pulse (length in 0.1us) +static uint8_t assign(uint32_t pulse) +{ + if( pulse < 5 ) return 0; // error + else if(pulse < 110 ) return 1; + else if(pulse < 135 ) return 2; + else if(pulse < 165 ) return 3; + else if(pulse < 200 ) return 4; + else if(pulse < 245 ) return 5; + else if(pulse < 300 ) return 6; + else if(pulse < 360 ) return 7; + else if(pulse < 430 ) return 8; + else if(pulse < 515 ) return 9; + else if(pulse < 620 ) return 10; + else if(pulse < 750 ) return 11; + else if(pulse < 910 ) return 12; + else if(pulse < 1100 ) return 13; + else if(pulse < 1350 ) return 14; + else if(pulse < 1650 ) return 15; + else if(pulse < 2000 ) return 16; + else if(pulse < 2450 ) return 17; + else if(pulse < 3000 ) return 18; + else if(pulse < 3600 ) return 19; + else if(pulse < 4300 ) return 20; + else if(pulse < 5150 ) return 21; + else if(pulse < 6200 ) return 22; + else if(pulse < 7500 ) return 23; + else if(pulse < 9100 ) return 24; + else if(pulse < 11000 ) return 25; + else if(pulse < 13500 ) return 26; + else if(pulse < 16500 ) return 27; + else if(pulse < 20000 ) return 28; + else if(pulse < 24500 ) return 29; + else if(pulse < 30000 ) return 30; + else if(pulse < 36000 ) return 31; + else if(pulse < 43000 ) return 32; + else if(pulse < 51500 ) return 33; + else if(pulse < 62000 ) return 34; + else if(pulse < 75000 ) return 35; + else if(pulse < 91000 ) return 36; + + return 0; // error +} + +// Detect IDs of attached boards - returns true when done +uint8_t IDDetection_detect(IdAssignmentTypeDef *out) +{ + // Try to identify the IDs via monoflop pulse duration + if (!detectID_Monoflop(out)) + return false; + + // Try to identify the IDs via EEPROM readout + detectID_EEPROM(out); + + // Detection finished + return true; +} + +void IDDetection_initialScan(IdAssignmentTypeDef *ids) +{ + while(!IDDetection_detect(ids)) + { + vitalsignsmonitor_checkVitalSigns(); + tmcl_process(); + } +} + + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids) +{ + switch (monoflopState) + { + case MONOFLOP_INIT: + FTM2_SC &= ~FTM_SC_CLKS_MASK; // stop timer + FTM2_CNT = 0; // clear counter + + IdState.ch1.state = ID_STATE_WAIT_LOW; + IdState.ch1.detectedBy = FOUND_BY_NONE; + IdState.ch2.state = ID_STATE_WAIT_LOW; + IdState.ch2.detectedBy = FOUND_BY_NONE; + + // Update the monoflop state before activating the timer. Otherwise bad + // luck with other unrelated interrupts might cause enough delay to + // trigger the timer overflow after starting the timer before updating + // this state - which results in the timeout no longer working. + monoflopState = MONOFLOP_SCANNING; + + FTM2_SC |= FTM_SC_CLKS(1); // start timer + ID_CLK_HIGH(); + break; + case MONOFLOP_SCANNING: + if(IDSTATE_SCAN_DONE(IdState)) + { + monoflopState = MONOFLOP_DONE; + } + break; + case MONOFLOP_DONE: + // Scan complete + ID_CLK_LOW(); + FTM2_SC &= ~FTM_SC_CLKS_MASK; // stop timer + + // ======== CH0 ========== + // Assign ID detection state for this channel + ids->ch1.state = IdState.ch1.state; + + if(IdState.ch1.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + uint32_t tickDiff = IdState.ch1.timer_2 - IdState.ch1.timer_1; + ids->ch1.id = assign(tickDiff * TICK_FACTOR); + + if(ids->ch1.id) + IdState.ch1.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch1.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + ids->ch1.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch1.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + ids->ch1.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch1.id = 0; + } + + // ======== CH1 ========== + // Assign ID detection state for this channel + ids->ch2.state = IdState.ch2.state; + + if(IdState.ch2.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + uint32_t tickDiff = IdState.ch2.timer_2 - IdState.ch2.timer_1; + ids->ch2.id = assign(tickDiff * TICK_FACTOR); + + if(ids->ch2.id) + IdState.ch2.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch2.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + ids->ch2.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch2.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + ids->ch2.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch2.id = 0; + } + + monoflopState = MONOFLOP_INIT; + return true; + break; + default: + break; + } + + return false; +} + +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids) +{ + // ====== EEPROM Check ====== + // EEPROM spec reserves 2 bytes for the ID buffer. + // Currently we only use one byte for IDs, both here in the firmware + // and in the IDE - once we deplete that ID pool, this needs to be extended + // (uint8_t to uint16_t and change EEPROM read to read two bytes instead of one) + uint8_t idBuffer[2]; + // ====== CH1 ====== + if(ids->ch1.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch1)) + { + eeprom_read_array(&SPI.ch1, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch1.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch1.id) + { + ids->ch1.state = ID_STATE_DONE; + IdState.ch1.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH0 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #1 + PORT_PCR_REG(HAL.IOs->pins->ID_CH0.portBase, HAL.IOs->pins->ID_CH0.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + } + + // ====== CH2 ====== + if(ids->ch2.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch2)) + { + eeprom_read_array(&SPI.ch2, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch2.id = idBuffer[0]; + //id was correctly detected via EEPROM + if(ids->ch2.id) + { + ids->ch2.state = ID_STATE_DONE; + IdState.ch2.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH1 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #2 + PORT_PCR_REG(HAL.IOs->pins->ID_CH1.portBase, HAL.IOs->pins->ID_CH1.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + } + + return true; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c b/Clean_TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c new file mode 100644 index 0000000..647c2bb --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c @@ -0,0 +1,446 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * Calling IDDetection_detect(IdAssignmentTypeDef *result) will start the ID detection process. + * The function returns the ID Results through the IdAssignmentTypeDef struct result points to. + * The detection will be done by monoflop pulse duration measurement or via EEPROM readout. + * While this process is still ongoing the function will return ID_STATE_WAIT_HIGH. Once the + * ID detection of both channels has been finished, ID_STATE_DONE will be returned. + * + * Calling the function again after the detection has finished will start another scan. + */ + +#include "IdDetection.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "BoardAssignment.h" +#include "EEPROM.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "TMCL.h" + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids); +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids); + +// Helper macros +#define ID_CLK_LOW() HAL.IOs->config->setLow(&HAL.IOs->pins->ID_CLK) // set id clk signal to low +#define ID_CLK_HIGH() HAL.IOs->config->setHigh(&HAL.IOs->pins->ID_CLK) // set id clk signal to high +#define ID_CLK_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CLK) == IOS_HIGH) // get id clk signal level +#define ID_CH0_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CH0) == IOS_HIGH) // get id signal level for this channel +#define ID_CH1_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CH1) == IOS_HIGH) // get id signal level for this channel +#define IDSTATE_SCAN_DONE(ID_STATE) \ + ( \ + (ID_STATE.ch1.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch1.state != ID_STATE_WAIT_HIGH) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_HIGH) \ + ) + +static uint8_t assign(uint32_t pulse); + +typedef enum { + MONOFLOP_INIT, + MONOFLOP_SCANNING, + MONOFLOP_DONE, + + MONOFLOP_END +} State_MonoflopDetection; + +State_MonoflopDetection monoflopState = MONOFLOP_INIT; + +IdAssignmentTypeDef IdState = { 0 }; + +/* pin changed interrupt to detect edges of ID pulse for both channels */ +void PC7_8_IRQHandler(void) +{ + // Abort if the EXTI line isn't set + if((exti_flag_get(EXTI_8) != SET) && (exti_flag_get(EXTI_7) != SET)){ + return; + } + + if(exti_flag_get(EXTI_8) == SET) + { + exti_flag_clear(EXTI_8); + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + if(ID_CH0_STATE) // Capture time of rising edge on ID_CH0 + { + TIMER_SWEVG(TIMER1) |= TIMER_SWEVG_CH0G; + IdState.ch1.state = ID_STATE_WAIT_HIGH; + } + else // Capture time of falling edge on ID_CH0 + { + TIMER_SWEVG(TIMER1) |= TIMER_SWEVG_CH1G; + IdState.ch1.state = ID_STATE_DONE; + } + } + else if(exti_flag_get(EXTI_7) == SET) + { + exti_flag_clear(EXTI_7); + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + if(ID_CH1_STATE) // Capture time of rising edge on ID_CH1 + { + TIMER_SWEVG(TIMER1) = TIMER_SWEVG_CH2G; + IdState.ch2.state = ID_STATE_WAIT_HIGH; + } + else // Capture time of falling edge on ID_CH1 + { + TIMER_SWEVG(TIMER1) = TIMER_SWEVG_CH3G; + IdState.ch2.state = ID_STATE_DONE; + } + } + + + +} + +void __attribute__ ((interrupt)) EXTI5_9_IRQHandler(void) +{ + + if(GET_BITS(SYSCFG_EXTISS2,0,3) == 3){ + PD8_IRQHandler(); // For TMC6140-eval diagnostics + } + else if(GET_BITS(SYSCFG_EXTISS2,0,3) == 2 || GET_BITS(SYSCFG_EXTISS1,12,15) == 2){ + PC7_8_IRQHandler(); // For idDetection + } +} + +/* timer interrupt to determine timeout on ID detection (missing boards, errors) */ +void TIMER1_IRQHandler(void) +{ + // Abort if the interrupt isn't set + if(timer_flag_get(TIMER1, TIMER_FLAG_UP) != SET) + return; + + timer_flag_clear(TIMER1, TIMER_FLAG_UP); + + if(monoflopState == MONOFLOP_SCANNING) + { + monoflopState = MONOFLOP_DONE; + return; + } +} + +/* Initialise timer and GPIO edge-triggered interrupts */ +void IDDetection_init(void) +{ + monoflopState = MONOFLOP_INIT; + + // ====== Pin initialisation ====== + // Pin ID_CLK + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CLK); + + // Pin ID_CH0 + gpio_mode_set(HAL.IOs->pins->ID_CH0.port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, HAL.IOs->pins->ID_CH0.bitWeight); + + + syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN8); + + exti_init(EXTI_8, EXTI_INTERRUPT, EXTI_TRIG_BOTH); + nvic_irq_enable(EXTI5_9_IRQn, 0, 1); + exti_interrupt_flag_clear(EXTI_8); + + // Pin ID_CH1 + gpio_mode_set(HAL.IOs->pins->ID_CH1.port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, HAL.IOs->pins->ID_CH1.bitWeight); + syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN7); + + exti_init(EXTI_7, EXTI_INTERRUPT, EXTI_TRIG_BOTH); + nvic_irq_enable(EXTI5_9_IRQn, 0, 1); + exti_interrupt_flag_clear(EXTI_7); + + // ====== Timer initialisation + + /* Timer Frequency: + * CLK_TIMER 120MHz + * ----------- = ----- = 10MHz = 0.1us <= COUNTER_CLK + * Prescaler 12 + * + */ + + rcu_periph_clock_enable(RCU_TIMER1); + rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL2); // CK_TIMER1 = 2 x CK_APB1 + timer_internal_clock_config(TIMER1); + timer_deinit(TIMER1); + + timer_counter_value_config(TIMER1, 0); + + + + timer_ic_parameter_struct *icpara_rising; + timer_ic_parameter_struct *icpara_falling; + + icpara_rising->icpolarity = TIMER_IC_POLARITY_RISING; + icpara_rising->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara_rising->icprescaler = TIMER_IC_PSC_DIV1; + icpara_rising->icfilter = 0U; + + icpara_falling->icpolarity = TIMER_IC_POLARITY_FALLING; + icpara_falling->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara_falling->icprescaler = TIMER_IC_PSC_DIV1; + icpara_falling->icfilter = 0U; + + timer_input_capture_config(TIMER1, TIMER_CH_0, icpara_rising); + timer_input_capture_config(TIMER1, TIMER_CH_1, icpara_falling); + timer_input_capture_config(TIMER1, TIMER_CH_2, icpara_rising); + timer_input_capture_config(TIMER1, TIMER_CH_3, icpara_falling); + + // Setting the prescaler i.e 11 + timer_prescaler_config(TIMER1, 11, TIMER_PSC_RELOAD_NOW); // Divides the timer freq by (prescaler + 1) + + timer_autoreload_value_config(TIMER1,100000); // timeout -> 10ms --TIM auto-reload register + + + timer_update_event_enable(TIMER1); + TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG; //generate update event + + timer_interrupt_enable(TIMER1, TIMER_INT_UP); + + // Enable timer interrupt + nvic_irq_enable(TIMER1_IRQn, 0xF, 0xF); + + +} + +void IDDetection_deInit() +{ + + nvic_irq_disable(TIMER1_IRQn); + nvic_irq_disable(EXTI5_9_IRQn); + timer_deinit(TIMER1); + exti_deinit(); +} + +// Returns ID assigned to given pulse (length in 0.1us) +static uint8_t assign(uint32_t pulse) +{ + if( pulse < 5) return 0; // error + else if(pulse < 110) return 1; + else if(pulse < 135) return 2; + else if(pulse < 165) return 3; + else if(pulse < 200) return 4; + else if(pulse < 245) return 5; + else if(pulse < 300) return 6; + else if(pulse < 360) return 7; + else if(pulse < 430) return 8; + else if(pulse < 515) return 9; + else if(pulse < 620) return 10; + else if(pulse < 750) return 11; + else if(pulse < 910) return 12; + else if(pulse < 1100) return 13; + else if(pulse < 1350) return 14; + else if(pulse < 1650) return 15; + else if(pulse < 2000) return 16; + else if(pulse < 2450) return 17; + else if(pulse < 3000) return 18; + else if(pulse < 3600) return 19; + else if(pulse < 4300) return 20; + else if(pulse < 5150) return 21; + else if(pulse < 6200) return 22; + else if(pulse < 7500) return 23; + else if(pulse < 9100) return 24; + else if(pulse < 11000) return 25; + else if(pulse < 13500) return 26; + else if(pulse < 16500) return 27; + else if(pulse < 20000) return 28; + else if(pulse < 24500) return 29; + else if(pulse < 30000) return 30; + else if(pulse < 36000) return 31; + else if(pulse < 43000) return 32; + else if(pulse < 51500) return 33; + else if(pulse < 62000) return 34; + else if(pulse < 75000) return 35; + else if(pulse < 91000) return 36; + + return 0; // error +} + +// Detect IDs of attached boards - returns true when done +uint8_t IDDetection_detect(IdAssignmentTypeDef *ids) +{ + // Change the exti source back to PC8 (It could be changed by TMC6140-eval to PD8) +// syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN8); + + // Try to identify the IDs via monoflop pulse duration + if (!detectID_Monoflop(ids)) + return false; + + // Try to identify the IDs via EEPROM readout + detectID_EEPROM(ids); + + // Detection finished + return true; + +} + +void IDDetection_initialScan(IdAssignmentTypeDef *ids) +{ + while(!IDDetection_detect(ids)) + { + vitalsignsmonitor_checkVitalSigns(); + tmcl_process(); + } + +} + +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids) +{ + switch(monoflopState) + { + case MONOFLOP_INIT: + timer_disable(TIMER1); // stop the timer + timer_counter_value_config(TIMER1, 0); // clear counter + + IdState.ch1.state = ID_STATE_WAIT_LOW; + IdState.ch1.detectedBy = FOUND_BY_NONE; + IdState.ch2.state = ID_STATE_WAIT_LOW; + IdState.ch2.detectedBy = FOUND_BY_NONE; + + // Update the monoflop state before activating the timer. Otherwise bad + // luck with other unrelated interrupts might cause enough delay to + // trigger the timer overflow after starting the timer before updating + // this state - which results in the timeout no longer working. + monoflopState = MONOFLOP_SCANNING; + + timer_enable(TIMER1); // start timer + ID_CLK_HIGH(); + break; + case MONOFLOP_SCANNING: + if (IDSTATE_SCAN_DONE(IdState)) + { + monoflopState = MONOFLOP_DONE; + } + break; + case MONOFLOP_DONE: + // Scan complete, disable ID_CLK and the timer + ID_CLK_LOW(); + timer_disable(TIMER1); + + // ======== CH1 ========== + // Assign ID detection state for this channel + ids->ch1.state = IdState.ch1.state; + + if(IdState.ch1.state == ID_STATE_DONE) + { + uint32_t pulse=timer_channel_capture_value_register_read(TIMER1, TIMER_CH_1) - timer_channel_capture_value_register_read(TIMER1, TIMER_CH_0); + + // Assign the ID derived from the ID pulse duration + ids->ch1.id = assign(pulse); + + + if(ids->ch1.id) + IdState.ch1.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch1.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + IdState.ch1.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch1.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + IdState.ch1.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch1.id = 0; + } + + + + // ======== CH2 ========== + // Assign ID detection state for this channel + ids->ch2.state = IdState.ch2.state; + + if(IdState.ch2.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + ids->ch2.id = assign(timer_channel_capture_value_register_read(TIMER1, TIMER_CH_3) - timer_channel_capture_value_register_read(TIMER1, TIMER_CH_2)); + + if(ids->ch2.id) + IdState.ch2.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch2.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + IdState.ch2.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch2.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + IdState.ch2.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch2.id = 0; + } + + monoflopState = MONOFLOP_INIT; + return true; + break; + default: + break; + } + + return false; +} + +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids) +{ + // ====== EEPROM Check ====== + // EEPROM spec reserves 2 bytes for the ID buffer. + // Currently we only use one byte for IDs, both here in the firmware + // and in the IDE - once we deplete that ID pool, this needs to be extended + // (uint8_t to uint16_t and change EEPROM read to read two bytes instead of one) + uint8_t idBuffer[2]; + // ====== CH1 ====== + if(ids->ch1.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch1)) + { + eeprom_read_array(&SPI.ch1, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch1.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch1.id) + { + ids->ch1.state = ID_STATE_DONE; + IdState.ch1.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH0 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #3 + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CH0); + } + + // ====== CH2 ====== + if(ids->ch2.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch2)) + { + eeprom_read_array(&SPI.ch2, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch2.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch2.id) + { + ids->ch2.state = ID_STATE_DONE; + IdState.ch2.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH1 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #4 + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CH1); + } + + return true; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/RAMDebug.c b/Clean_TMC2209/lib/tmc/tmc/RAMDebug.c new file mode 100644 index 0000000..427a229 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/RAMDebug.c @@ -0,0 +1,631 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "RAMDebug.h" + +#include "boards/Board.h" +#include "hal/SysTick.h" +#include "hal/HAL.h" + +#include + +// === RAM debugging =========================================================== + +// Debug parameters +#define RAMDEBUG_MAX_CHANNELS 4 +#define RAMDEBUG_BUFFER_SIZE 32768 +#define RAMDEBUG_BUFFER_ELEMENTS (RAMDEBUG_BUFFER_SIZE / 4) + +bool captureEnabled = false; + +// Sample Buffer +uint32_t debug_buffer[RAMDEBUG_BUFFER_ELEMENTS] = { 0 }; +uint32_t debug_write_index = 0; +uint32_t debug_read_index = 0; +uint32_t pre_index = 0; + +RAMDebugState state = RAMDEBUG_IDLE; + +static bool global_enable = false; +static bool processing = false; +static bool use_next_process = true; +static bool next_process = false; + +// Sampling options +static uint32_t prescaler = 1; +static uint32_t frequency = RAMDEBUG_FREQUENCY; +static uint32_t sampleCount = RAMDEBUG_BUFFER_ELEMENTS; +static uint32_t sampleCountPre = 0; + +typedef struct { + RAMDebugSource type; + uint8_t eval_channel; + uint32_t address; +} Channel; + +Channel channels[RAMDEBUG_MAX_CHANNELS]; + +typedef struct { + Channel channel; + RAMDebugTrigger type; + uint32_t threshold; + uint32_t mask; + uint8_t shift; +} Trigger; + +Trigger trigger; + +// Store whether the last sampling point was above or below the trigger threshold +static bool wasAboveSigned = 0; +static bool wasAboveUnsigned = 0; + +// Function declarations +static uint32_t readChannel(Channel channel); + +// === Capture and trigger logic =============================================== + +// This function only gets called by the interrupt handler. +void handleTriggering() +{ + // Abort if not in the right state + if (state != RAMDEBUG_TRIGGER) + return; + + // Read the trigger channel value and apply mask/shift values + uint32_t value_raw = readChannel(trigger.channel); + value_raw = (value_raw & trigger.mask) >> trigger.shift; + + // Create a signed version of the trigger value + int32_t value = value_raw; + // Create a mask with only the highest bit of the trigger channel mask set + uint32_t msbMask = (trigger.mask>>trigger.shift) ^ (trigger.mask>>(trigger.shift+1)); + // Check if our value has that bit set. + if (value_raw & msbMask) + { + // If yes, sign-extend it + value |= ~(trigger.mask>>trigger.shift); + } + + bool isAboveSigned = value > (int32_t) trigger.threshold; + bool isAboveUnsigned = value_raw > (uint32_t) trigger.threshold; + + switch(trigger.type) + { + case TRIGGER_UNCONDITIONAL: + state = RAMDEBUG_CAPTURE; + break; + case TRIGGER_RISING_EDGE_SIGNED: + if (!wasAboveSigned && isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_FALLING_EDGE_SIGNED: + if (wasAboveSigned && !isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_DUAL_EDGE_SIGNED: + if (wasAboveSigned != isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_RISING_EDGE_UNSIGNED: + if (!wasAboveUnsigned && isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_FALLING_EDGE_UNSIGNED: + if (wasAboveUnsigned && !isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_DUAL_EDGE_UNSIGNED: + if (wasAboveUnsigned != isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + default: + break; + } + + // Store the last threshold comparison value + wasAboveSigned = isAboveSigned; + wasAboveUnsigned = isAboveUnsigned; +} + +// This function only gets called by the interrupt handler. +void handleDebugging() +{ + int32_t i; + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type == CAPTURE_DISABLED) + continue; + + if(state == RAMDEBUG_CAPTURE) + { + // Add the sample value to the buffer + debug_buffer[debug_write_index++] = readChannel(channels[i]); + + if (debug_write_index >= sampleCount) + { + // End the capture + state = RAMDEBUG_COMPLETE; + captureEnabled = false; + break; + } + } + else if((state != RAMDEBUG_COMPLETE) && (sampleCountPre > 0)) + { + debug_buffer[pre_index] = readChannel(channels[i]); + pre_index = (pre_index + 1) % sampleCountPre; + } + } +} + +void debug_process() +{ + static uint32_t prescalerCount = 0; + + if(!global_enable) + return; + + if(processing) + return; + + if(use_next_process && (!next_process)) + return; + + next_process = false; + + if (captureEnabled == false) + return; + + handleTriggering(); + + // Increment and check the prescaler counter + if (++prescalerCount < prescaler) + return; + + processing = true; + + // Reset the prescaler counter + prescalerCount = 0; + + handleDebugging(); + processing = false; +} + +static inline uint32_t readChannel(Channel channel) +{ + uint32_t sample = 0; + + switch (channel.type) + { + case CAPTURE_PARAMETER: + { + uint8_t motor = (channel.address >> 24) & 0xFF; + uint8_t type = (channel.address >> 0) & 0xFF; + + ((channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1))->GAP(type, motor, (int32_t *)&sample); + + break; + } + case CAPTURE_REGISTER: + { + uint8_t motor = channel.address >> 24; + + ((channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1))->readRegister(motor, channel.address, (int32_t *)&sample); + + break; + } + case CAPTURE_STACKED_REGISTER: + { + uint8_t motor = channel.address >> 24; + uint8_t stackedRegisterValue = channel.address >> 16; + uint8_t stackedRegisterAddress = channel.address >> 8; + uint8_t dataRegisterAddress = channel.address >> 0; + + EvalboardFunctionsTypeDef *ch = (channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1); + + // Backup the stacked address + uint32_t oldAddress = 0; + ch->readRegister(motor, stackedRegisterAddress, (int32_t *)&oldAddress); + + // Write the new stacked address + ch->writeRegister(motor, stackedRegisterAddress, stackedRegisterValue); + + // Read the stacked data register + ch->readRegister(motor, dataRegisterAddress, (int32_t *)&sample); + + // Restore the stacked address + ch->writeRegister(motor, stackedRegisterAddress, oldAddress); + break; + } + case CAPTURE_SYSTICK: + sample = systick_getTick();//systick_getTimer10ms(); + break; + case CAPTURE_ANALOG_INPUT: + // Use same indices as in TMCL.c GetInput() + switch(channel.address) { + case 0: + sample = *HAL.ADCs->AIN0; + break; + case 1: + sample = *HAL.ADCs->AIN1; + break; + case 2: + sample = *HAL.ADCs->AIN2; + break; + case 3: + sample = *HAL.ADCs->DIO4; + break; + case 4: + sample = *HAL.ADCs->DIO5; + break; + case 6: + sample = *HAL.ADCs->VM; + break; + } + break; + default: + sample = 0; + break; + } + + return sample; +} + +// === Interfacing with the debugger =========================================== +void debug_init() +{ + int32_t i; + + // Disable data capture before changing the configuration + captureEnabled = false; + + // Reset the RAMDebug state + state = RAMDEBUG_IDLE; + + // Wipe the RAM debug buffer + for (i = 0; i < RAMDEBUG_BUFFER_ELEMENTS; i++) + { + debug_buffer[i] = 0; + } + debug_read_index = 0; + debug_write_index = 0; + + // Set default values for the capture configuration + prescaler = 1; + sampleCount = RAMDEBUG_BUFFER_ELEMENTS; + sampleCountPre = 0; + + // Reset the channel configuration + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + channels[i].type = CAPTURE_DISABLED; + channels[i].eval_channel = 0; + channels[i].address = 0; + } + + // Reset the trigger + trigger.channel.type = CAPTURE_DISABLED; + trigger.channel.address = 0; + trigger.mask = 0xFFFFFFFF; + trigger.shift = 0; + + global_enable = true; +} + +bool debug_setChannel(uint8_t type, uint32_t channel_value) +{ + return ( + debug_setEvalChannel((channel_value >> 16) & 0x01) && + debug_setAddress(channel_value) && + debug_setType(type) + ); +} + +bool debug_setTriggerChannel(uint8_t type, uint32_t channel_value) +{ + return ( + debug_setTriggerType(type) && + debug_setTriggerEvalChannel((channel_value >> 16) & 0x01) && + debug_setTriggerAddress(channel_value) + ); +} + +bool debug_setType(uint8_t type) +{ + int32_t i; + + if (type >= CAPTURE_END) + return false; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].type = type; + + return true; + } + + return false; +} + +bool debug_setEvalChannel(uint8_t eval_channel) +{ + int32_t i; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].eval_channel = eval_channel; + + return true; + } + + return false; +} + +bool debug_setAddress(uint32_t address) +{ + int32_t i; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].address = address; + + return true; + } + + return false; +} + +int32_t debug_getChannelType(uint8_t index, uint8_t *type) +{ + if (index == 0xFF) + { + *type = trigger.channel.type; + return 1; + } + + if (index >= RAMDEBUG_MAX_CHANNELS) + return 0; + + *type = channels[index].type; + + return 1; +} + +int32_t debug_getChannelAddress(uint8_t index, uint32_t *address) +{ + if (index == 0xFF) + { + *address = trigger.channel.address; + return 1; + } + + if (index >= RAMDEBUG_MAX_CHANNELS) + return 0; + + *address = channels[index].address; + + return 1; +} + +bool debug_setTriggerType(uint8_t type) +{ + if (type >= CAPTURE_END) + return false; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.type = type; + + return true; +} + +bool debug_setTriggerEvalChannel(uint8_t eval_channel) +{ + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.eval_channel = eval_channel; + + return true; +} + +bool debug_setTriggerAddress(uint32_t address) +{ + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.address = address; + + return true; +} + +void debug_setTriggerMaskShift(uint32_t mask, uint8_t shift) +{ + trigger.mask = mask; + trigger.shift = shift; +} + +int32_t debug_enableTrigger(uint8_t type, uint32_t threshold) +{ + // Parameter validation + if (type >= TRIGGER_END) + return 0; + + if (state != RAMDEBUG_IDLE) + return 0; + + // Do not allow the edge triggers with channel still missing + if (type != TRIGGER_UNCONDITIONAL && trigger.channel.type == CAPTURE_DISABLED) + return 0; + + // Store the trigger configuration + trigger.type = type; + trigger.threshold = threshold; + + // Initialize the trigger helper variable + // Read out the trigger value and apply the mask/shift + int32_t triggerValue = (readChannel(trigger.channel) & trigger.mask) >> trigger.shift; + wasAboveSigned = (int32_t) triggerValue > (int32_t) trigger.threshold; + wasAboveUnsigned = (uint32_t) triggerValue > (uint32_t) trigger.threshold; + + // Enable the trigger + state = RAMDEBUG_TRIGGER; + + // Enable the capturing IRQ + captureEnabled = true; + + return 1; +} + +void debug_setPrescaler(uint32_t divider) +{ + prescaler = divider; +} + +void debug_setSampleCount(uint32_t count) +{ + if (count > RAMDEBUG_BUFFER_ELEMENTS) + count = RAMDEBUG_BUFFER_ELEMENTS; + + sampleCount = count; +} + +uint32_t debug_getSampleCount() +{ + return sampleCount; +} + +void debug_setPretriggerSampleCount(uint32_t count) +{ + if (count > sampleCount) + count = sampleCount; + + sampleCountPre = count; + debug_write_index = count; +} + +uint32_t debug_getPretriggerSampleCount() +{ + return sampleCountPre; +} + +int32_t debug_getSample(uint32_t index, uint32_t *value) +{ + if (index >= debug_write_index) + return 0; + + if(index < sampleCountPre) + { + *value = debug_buffer[(pre_index + index) % sampleCountPre]; + } + else + { + *value = debug_buffer[index]; + } + + return 1; +} + +void debug_updateFrequency(uint32_t freq) +{ + frequency = freq; +} + +int32_t debug_getState(void) +{ + return state; +} + +int32_t debug_getInfo(uint32_t type) +{ + switch(type) + { + case 0: + return RAMDEBUG_MAX_CHANNELS; + break; + case 1: + return RAMDEBUG_BUFFER_ELEMENTS; + break; + case 2: + // PWM/Sampling Frequency + return frequency; // RAMDEBUG_FREQUENCY; + break; + case 3: + return debug_write_index; + break; + default: + break; + } + + return -1; +} + +void debug_useNextProcess(bool enable) +{ + use_next_process = enable; +} + +void debug_nextProcess(void) +{ + next_process = true; +} + +void debug_setGlobalEnable(bool enable) +{ + global_enable = enable; +} diff --git a/Clean_TMC2209/lib/tmc/tmc/RAMDebug.h b/Clean_TMC2209/lib/tmc/tmc/RAMDebug.h new file mode 100644 index 0000000..792be99 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/RAMDebug.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef RAMDEBUG_H +#define RAMDEBUG_H + +#include +#include + +#define RAMDEBUG_FREQUENCY 1000/*0*/ + +// Capture state +typedef enum { + RAMDEBUG_IDLE = 0, + RAMDEBUG_TRIGGER = 1, + RAMDEBUG_CAPTURE = 2, + RAMDEBUG_COMPLETE = 3 +} RAMDebugState; + +// Capture channel configuration +typedef enum { + CAPTURE_DISABLED = 0, + + CAPTURE_PARAMETER = 1, + CAPTURE_REGISTER = 2, + CAPTURE_STACKED_REGISTER = 3, + CAPTURE_SYSTICK = 4, + CAPTURE_RAMDEBUG_PARAMETER = 5, // For modules that do not support registers + CAPTURE_ANALOG_INPUT = 6, + + CAPTURE_END +} RAMDebugSource; + +// Trigger configuration +typedef enum { + TRIGGER_UNCONDITIONAL = 0, + TRIGGER_RISING_EDGE_SIGNED = 1, + TRIGGER_FALLING_EDGE_SIGNED = 2, + TRIGGER_DUAL_EDGE_SIGNED = 3, + TRIGGER_RISING_EDGE_UNSIGNED = 4, + TRIGGER_FALLING_EDGE_UNSIGNED = 5, + TRIGGER_DUAL_EDGE_UNSIGNED = 6, + + TRIGGER_END +} RAMDebugTrigger; + +void debug_init(); +void debug_process(); +bool debug_setChannel(uint8_t type, uint32_t channel_value); +bool debug_setTriggerChannel(uint8_t type, uint32_t channel_value); +bool debug_setType(uint8_t type); +bool debug_setEvalChannel(uint8_t eval_channel); +bool debug_setAddress(uint32_t address); +int32_t debug_getChannelType(uint8_t index, uint8_t *type); +int32_t debug_getChannelAddress(uint8_t index, uint32_t *address); + +bool debug_setTriggerType(uint8_t type); +bool debug_setTriggerEvalChannel(uint8_t eval_channel); +bool debug_setTriggerAddress(uint32_t address); +void debug_setTriggerMaskShift(uint32_t mask, uint8_t shift); +int32_t debug_enableTrigger(uint8_t type, uint32_t threshold); + +void debug_setPrescaler(uint32_t divider); +void debug_setSampleCount(uint32_t count); +uint32_t debug_getSampleCount(); +void debug_setPretriggerSampleCount(uint32_t count); +uint32_t debug_getPretriggerSampleCount(); + +int32_t debug_getSample(uint32_t index, uint32_t *value); +void debug_updateFrequency(uint32_t freq); +int32_t debug_getState(void); +int32_t debug_getInfo(uint32_t type); + +void debug_useNextProcess(bool enable); +void debug_nextProcess(void); +void debug_setGlobalEnable(bool enable); + +#endif /* RAMDEBUG_H */ diff --git a/Clean_TMC2209/lib/tmc/tmc/StepDir.c b/Clean_TMC2209/lib/tmc/tmc/StepDir.c new file mode 100644 index 0000000..a85cc4d --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/StepDir.c @@ -0,0 +1,763 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * StepDir.c + * + * This is a basic implementation of a StepDir generator, capable of generating + * velocity (reaching a target velocity with linear acceleration) and position + * (reach a target position with linear acc-/decceleration and a maximum velocity) + * ramps. + * + * ***** HOW IT WORKS ***** + * + * General: + * A high frequency (2^17 Hz) Interrupt calculates acceleration, velocity and + * position. Position and velocity are calculated with 17 binary decimal places + * of precision. + * + * Velocity mode: + * In velocity mode, the generator will accelerate towards a target velocity. + * Acceleration and velocity can be changed at any point of the ramp. The position + * is tracked and resettable (useful for setting a reference point via a switch). + * + * Position mode: + * In position mode, a linearly accelerated ramp is used to reach the position. + * Parameters for the ramp are acceleration and maximum velocity. The generator + * will always increase the velocity towards the maximum velocity until the + * remaining distance to the target is required for the deceleration ramp. + * Acceleration, maximum velocity and target position can all be changed during + * the ramp. Note that decreasing acceleration or changing target position may + * lead to overshooting the target. In that case the generator will start a new + * ramp to the target, while always staying within the bounds of acceleration and + * velocity. + * + * Due to imprecision in the deceleration distance calculations, a small tolerance + * window is used, where the motor will set the velocity to zero if the velocity is + * small enough and the position is reached (V_STOP). If the position is barely + * missed (HOMING_DISTANCE) and the velocity is zero, the generator will home in + * towards the target position at a low velocity (V_STOP). + * Changing the actual position value is not possible while in position mode + * the generator is not idle (target position reached, velocity zero). + * Changing the acceleration to zero is not possible in position mode. + * Acceleration value changes require a recalculation of the braking distance. + * This can result in more frequent near-misses of the target position, which the + * generator will compensate with starting new ramps or homing in (see above). + * + * If overshooting the target by any step is not permitted, it is recommended to + * drive to the target without changing parameters during the ramp. Alternatively, + * driving to a point shortly before the actual target point and then starting + * another small ramp allows for parameter changes during the first ramp, only + * requiring a small distance drive with 'locked' parameters. + * + * Overshooting from calculation errors is mostly limited to single digit + * position differences. Decreasing acceleration or moving the target position + * towards the actual position might result in bigger misses of the target. + * + * StallGuard: + * The StepDir generator supports the StallGuard feature, either by a input pin + * signal or with external monitoring. The function periodicJob() will check, + * whether the velocity is above the set StallGuard threshold velocity, set a + * status flag (usable for external StallGuard monitoring) and - if present - + * check the input pin for indicated stalls. + * Make sure that periodicJob() is called frequently to allow quick stall + * detection. The function can also be called by an interrupt to guarantee + * quick detection [1]. The interrupt should have a lower priority than the + * Step-Generator interrupt. + * + * When using external monitoring, for example by checking a chip register, + * you can use the STATUS_STALLGUARD_ACTIVE bit of getStatus() to see if + * StallGuard is active. In case of a stall, calling stop(STOP_STALL) will + * trigger the stall mechanism, shutting down the generator without loosing + * further steps. + * Clearing a stall condition is done by setting the stall velocity threshold + * to any value. + * Position mode will start a new ramp towards the target after a stall. + * + * Emergency Stop: + * The stop function implements an emergency stop. This will result in the + * channel immediately stopping any movements. No parameters are updated to + * allow for diagnostics. The only way to clear the emergency stop event is + * to init() the StepDir generator again [2]. + * + * ***** LIMITATIONS ***** + * + * The frequency of the StepDir generator is limited by the processor. On the + * Landungsbrücke, the worst case of two motors/channels (TMC2041) is able to + * still run at 2^17 Hz. Since the bulk of the calculation is per-motor/channel, + * using a chip with only one motor/channel would allow a frequency of 2^18 Hz. + * (Note that quite a few calculations have to divide by the frequency, so + * choosing a power of two simplifies those to right-shifts.) + * + * The limit on Step pulses is one generated pulse per interrupt. + * The maximum velocity therefore is equal to the interrupt frequency: + * Max Velocity: 2^17 pps = 131072 pps + * + * Each tick the acceleration value gets added to the velocity accumulator + * variable (uint32_t). The upper 15 digits are added to the velocity, the lower + * 17 digits are kept in the accumulator between ticks. The maximum + * acceleration will result in the upper 15 digits being 1 each tick, increasing + * the velocity by 32767 (0x7FFF) per tick. The accumulator digits stay unchanged, + * otherwise the overflow of the lower 17 accumulator digits into the upper 15 + * digits would cause the uint32_t to overflow, loosing an acceleration tick. + * In other words: The upper 15 digits are 1, the lower 17 digits are 0: + * Max Acceleration: 0xFFFE0000 = 4294836224 pps^2 + * + * A change from lowest to highest (or vice-versa) velocity would take 9 ticks at + * maximum acceleration: + * ceil( (VMAX- (-VMAX)) / AMAX) = ceil(8,000244) = 9 + * + * ***** Side notes ****** + * [1]: Technically periodicJob() is not interrupt-safe, since it updates the + * haltingCondition bitfield. Read-Modify-Write cycles of the main code + * could result in the changes of interrupts to the bitfield to be lost. + * In practice, the interrupt should just rewrite the stall bit on the next + * check though due to the nature of StallGuard. + * [2]: Emergency stop does not have a graceful recovery method by design. + * Clearing the emergency stop via init() will result in all channels + * being reset. + */ + +#include "StepDir.h" +#include "hal/derivative.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define TIMER_INTERRUPT FTM1_IRQHandler +#elif defined(LandungsbrueckeV3) + #define TIMER_INTERRUPT TIMER2_IRQHandler +#endif + +#define STEP_DIR_CHANNELS 2 + +// Reset value for stallguard threshold. Since Stallguard is motor/application-specific we can't choose a good value here, +// so this value is rather randomly chosen. Leaving it at zero means stall detection turned off. +#define STALLGUARD_THRESHOLD 0 + +StepDirectionTypedef StepDir[STEP_DIR_CHANNELS]; + +IOPinTypeDef DummyPin = { .bitWeight = DUMMY_BITWEIGHT }; + +// Helper functions +static int32_t calculateStepDifference(int32_t velocity, uint32_t oldAccel, uint32_t newAccel); +// These helper functions are for optimizing the interrupt without duplicating +// logic for both interrupt and main loop. We save time in them by omitting +// safety checks needed only for the main loop in these functions. +// The main loop then uses functions that wrap these functions together with the +// necessary safety checks. +static inline void checkStallguard(StepDirectionTypedef *channel, bool stallSignalActive); +static inline void stop(StepDirectionTypedef *channel, StepDirStop stopType); + +void TIMER_INTERRUPT() +{ +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + FTM1_SC &= ~FTM_SC_TOF_MASK; // clear timer overflow flag +#elif defined(LandungsbrueckeV3) + if(timer_interrupt_flag_get(TIMER2, TIMER_INT_FLAG_UP) == RESET) + return; + timer_interrupt_flag_clear(TIMER2, TIMER_INT_FLAG_UP); +#endif + + for (uint8_t ch = 0; ch < STEP_DIR_CHANNELS; ch++) + { + // Temporary variable for the current channel + StepDirectionTypedef *currCh = &StepDir[ch]; + + // If any halting condition is present, abort immediately + if (currCh->haltingCondition) + continue; + + // Reset step output (falling edge of last pulse) + + //*currCh->stepPin->resetBitRegister = currCh->stepPin->bitWeight; + HAL.IOs->config->setLow(currCh->stepPin); + + // Check if StallGuard pin is high + // Note: If no stall pin is registered, isStallSignalHigh becomes FALSE + // and checkStallguard won't do anything. +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + bool isStallSignalHigh = (GPIO_PDIR_REG(currCh->stallGuardPin->GPIOBase) & currCh->stallGuardPin->bitWeight) != 0; +#elif defined(LandungsbrueckeV3) + bool isStallSignalHigh = HAL.IOs->config->isHigh(currCh->stallGuardPin); +#endif + checkStallguard(currCh, isStallSignalHigh); + + // Compute ramp + int32_t dx = tmc_ramp_linear_compute(&currCh->ramp); + + // Step + if (dx == 0) // No change in position -> skip step generation + goto skipStep; + + // Direction + *((dx > 0) ? currCh->dirPin->resetBitRegister : currCh->dirPin->setBitRegister) = currCh->dirPin->bitWeight; + + // Set step output (rising edge of step pulse) + *currCh->stepPin->setBitRegister = currCh->stepPin->bitWeight; + +skipStep: + // Synchronised Acceleration update + switch(currCh->syncFlag) + { + case SYNC_SNAPSHOT_REQUESTED: + // Apply the new acceleration + tmc_ramp_linear_set_acceleration(&currCh->ramp, currCh->newAcceleration); + // Save a snapshot of the velocity + currCh->oldVelocity = tmc_ramp_linear_get_rampVelocity(&currCh->ramp); + + currCh->syncFlag = SYNC_SNAPSHOT_SAVED; + break; + case SYNC_UPDATE_DATA: + currCh->ramp.accelerationSteps += currCh->stepDifference; + currCh->syncFlag = SYNC_IDLE; + break; + default: + break; + } + } +} + +void StepDir_rotate(uint8_t channel, int32_t velocity) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + // Set the rampmode first - other way around might cause issues + tmc_ramp_linear_set_mode(&StepDir[channel].ramp, TMC_RAMP_LINEAR_MODE_VELOCITY); + switch(StepDir[channel].mode) { + case STEPDIR_INTERNAL: + tmc_ramp_linear_set_targetVelocity(&StepDir[channel].ramp, MIN(STEPDIR_MAX_VELOCITY, velocity)); + break; + case STEPDIR_EXTERNAL: + default: + tmc_ramp_linear_set_targetVelocity(&StepDir[channel].ramp, velocity); + break; + } +} + +void StepDir_moveTo(uint8_t channel, int32_t position) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_mode(&StepDir[channel].ramp, TMC_RAMP_LINEAR_MODE_POSITION); + tmc_ramp_linear_set_targetPosition(&StepDir[channel].ramp, position); +} + +void StepDir_periodicJob(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + // Check stallguard velocity threshold + if ((StepDir[channel].stallGuardThreshold != 0) && (abs(tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp)) >= StepDir[channel].stallGuardThreshold)) + { + StepDir[channel].stallGuardActive = true; + } + else + { + StepDir[channel].stallGuardActive = false; + } +} + +void StepDir_stop(uint8_t channel, StepDirStop stopType) +{ + stop(&StepDir[channel], stopType); +} + +uint8_t StepDir_getStatus(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + uint8_t status = StepDir[channel].haltingCondition; + + int32_t targetPosition = tmc_ramp_linear_get_targetPosition(&StepDir[channel].ramp); + int32_t actualPosition = tmc_ramp_linear_get_rampPosition(&StepDir[channel].ramp); + + status |= (targetPosition == actualPosition) ? STATUS_TARGET_REACHED : 0; + status |= (StepDir[channel].stallGuardActive) ? STATUS_STALLGUARD_ACTIVE : 0; + status |= (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_VELOCITY) ? STATUS_MODE : 0; + + return status; +} + +// Register the pins to be used by a StepDir channel. NULL will leave the pin unchanged +void StepDir_setPins(uint8_t channel, IOPinTypeDef *stepPin, IOPinTypeDef *dirPin, IOPinTypeDef *stallPin) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (stepPin) + { + if (IS_DUMMY_PIN(stepPin)) + { + // Set the halting condition before changing the pin + StepDir[channel].haltingCondition |= STATUS_NO_STEP_PIN; + } + StepDir[channel].stepPin = stepPin; + if (!IS_DUMMY_PIN(stepPin)) + { + // Clear the halting condition after setting the pin + StepDir[channel].haltingCondition &= ~STATUS_NO_STEP_PIN; + } + } + + if (dirPin) + { + if (IS_DUMMY_PIN(dirPin)) + { + // Set the halting condition before changing the pin + StepDir[channel].haltingCondition |= STATUS_NO_DIR_PIN; + } + StepDir[channel].dirPin = dirPin; + if (!IS_DUMMY_PIN(dirPin)) + { + // Clear the halting condition after setting the pin + StepDir[channel].haltingCondition &= ~STATUS_NO_DIR_PIN; + } + } + + if (stallPin) + { + StepDir[channel].stallGuardPin = stallPin; + } +} + +void StepDir_stallGuard(uint8_t channel, bool stall) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + checkStallguard(&StepDir[channel], stall); +} + +// ===== Setters ===== +// The setters are responsible to access their respective variables while keeping the ramp generation stable + +// Set actual and target position (Not during an active position ramp) +void StepDir_setActualPosition(uint8_t channel, int32_t actualPosition) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_POSITION) + { + // In position mode: If we're not idle -> abort +// if ((StepDir[channel].actualVelocity != 0) || +// (StepDir[channel].actualPosition != StepDir[channel].targetPosition)) +// { +// return; +// } + + // todo CHECK 2: Use a haltingCondition to prevent movement instead of VMAX? (LH) + // Temporarity set VMAX to 0 to prevent movement between setting actualPosition and targetPosition +// uint32_t tmp = StepDir[channel].velocityMax; +// StepDir[channel].velocityMax = 0; + + // Also update target position to prevent movement + tmc_ramp_linear_set_targetPosition(&StepDir[channel].ramp, actualPosition); + tmc_ramp_linear_set_rampPosition(&StepDir[channel].ramp, actualPosition); + + // Restore VMAX +// StepDir[channel].velocityMax = tmp; + } + else + { + // In velocity mode the position is not relevant so we can just update it without precautions + tmc_ramp_linear_set_rampPosition(&StepDir[channel].ramp, actualPosition); + } +} + +void StepDir_setAcceleration(uint8_t channel, uint32_t acceleration) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_VELOCITY) + { // Velocity mode does not require any special actions + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + return; + } + + // Position mode does not allow acceleration 0 + if (acceleration == 0) + return; + + // Store the old acceleration + uint32_t oldAcceleration = tmc_ramp_linear_get_acceleration(&StepDir[channel].ramp); + + // Update the acceleration + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + + // If the channel is not halted we need to synchronise with the interrupt + if (StepDir[channel].haltingCondition == 0) + { + // Sync mechanism: store the new acceleration value and request + // a snapshot from the interrupt + StepDir[channel].newAcceleration = acceleration; + StepDir[channel].syncFlag = SYNC_SNAPSHOT_REQUESTED; + // Wait for the flag update from the interrupt. + while (ACCESS_ONCE(StepDir[channel].syncFlag) != SYNC_SNAPSHOT_SAVED); // todo CHECK 2: Timeout to prevent deadlock? (LH) #1 + } + else + { // Channel is halted -> access data directly without sync mechanism + //StepDir[channel].acceleration = acceleration; + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + StepDir[channel].oldVelocity = tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp); + } + + int32_t stepDifference = calculateStepDifference(StepDir[channel].oldVelocity, oldAcceleration, acceleration); + + if (StepDir[channel].haltingCondition == 0) + { + StepDir[channel].stepDifference = stepDifference; + StepDir[channel].syncFlag = SYNC_UPDATE_DATA; + + // Wait for interrupt to set flag to SYNC_IDLE + while (ACCESS_ONCE(StepDir[channel].syncFlag) != SYNC_IDLE); // todo CHECK 2: Timeout to prevent deadlock? (LH) #2 + } + else + { // Channel is halted -> access data directly without sync mechanism + StepDir[channel].ramp.accelerationSteps += stepDifference; + } +} + +void StepDir_setVelocityMax(uint8_t channel, int32_t velocityMax) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_maxVelocity(&StepDir[channel].ramp, velocityMax); +} + +// Set the velocity threshold for active StallGuard. Also reset the stall flag +void StepDir_setStallGuardThreshold(uint8_t channel, int32_t stallGuardThreshold) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].stallGuardThreshold = stallGuardThreshold; + StepDir[channel].haltingCondition &= ~STATUS_STALLED; +} + +void StepDir_setMode(uint8_t channel, StepDirMode mode) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].mode = mode; + + if (mode == STEPDIR_INTERNAL) + { + StepDir_setFrequency(channel, STEPDIR_FREQUENCY); + } +} + +void StepDir_setFrequency(uint8_t channel, uint32_t frequency) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].frequency = frequency; +} + +void StepDir_setPrecision(uint8_t channel, uint32_t precision) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_precision(&StepDir[channel].ramp, precision); +} + +// ===== Getters ===== +int32_t StepDir_getActualPosition(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_rampPosition(&StepDir[channel].ramp); +} + +int32_t StepDir_getTargetPosition(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_targetPosition(&StepDir[channel].ramp); +} + +int32_t StepDir_getActualVelocity(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp); +} + +int32_t StepDir_getTargetVelocity(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_targetVelocity(&StepDir[channel].ramp); +} + +uint32_t StepDir_getAcceleration(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_acceleration(&StepDir[channel].ramp); +} + +int32_t StepDir_getVelocityMax(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_maxVelocity(&StepDir[channel].ramp); +} + +int32_t StepDir_getStallGuardThreshold(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].stallGuardThreshold; +} + +StepDirMode StepDir_getMode(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].mode; +} + +uint32_t StepDir_getFrequency(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].frequency; +} + +uint32_t StepDir_getPrecision(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return 0; + + return tmc_ramp_linear_get_precision(&StepDir[channel].ramp); +} + +int32_t StepDir_getMaxAcceleration(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + if (StepDir[channel].mode == STEPDIR_INTERNAL) + return STEPDIR_MAX_ACCELERATION; + + // STEPDIR_EXTERNAL -> no limitation from this generator + return s32_MAX; +} + +// =================== + +void StepDir_init(uint32_t precision) +{ + if (precision == 0) + { + // Use default precision + precision = STEPDIR_FREQUENCY; + } + + // StepDir Channel initialisation + for (uint8_t i = 0; i < STEP_DIR_CHANNELS; i++) + { + StepDir[i].oldVelAccu = 0; + StepDir[i].oldVelocity = 0; + StepDir[i].newAcceleration = 0; + + // Set the no-pin halting conditions before changing the pins + // to avoid a race condition with the interrupt + StepDir[i].haltingCondition = STATUS_NO_STEP_PIN | STATUS_NO_DIR_PIN; + StepDir[i].stallGuardPin = &DummyPin; + StepDir[i].stepPin = &DummyPin; + StepDir[i].dirPin = &DummyPin; + + StepDir[i].stallGuardThreshold = STALLGUARD_THRESHOLD; + + StepDir[i].mode = STEPDIR_INTERNAL; + StepDir[i].frequency = precision; + + tmc_ramp_linear_init(&StepDir[i].ramp); + tmc_ramp_linear_set_precision(&StepDir[i].ramp, precision); + tmc_ramp_linear_set_maxVelocity(&StepDir[i].ramp, STEPDIR_DEFAULT_VELOCITY); + tmc_ramp_linear_set_acceleration(&StepDir[i].ramp, STEPDIR_DEFAULT_ACCELERATION); + } + + // Chip-specific hardware peripheral initialisation + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // enable clock for FTM1 + SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; + + FTM1_MODE |= FTM_MODE_WPDIS_MASK; // disable write protection, FTM specific register are available + + FTM1_MODE |= FTM_MODE_FTMEN_MASK | FTM_MODE_FAULTM_MASK; //enable interrupt and select all faults + + // Timer frequency = Bus clk frequency / (MOD - CNTIN + 1) + // => MOD = (f_bus / f_timer) + CNTIN - 1 + // The datasheet documents the FTM using the system/core clock, but it's + // actually using the bus clock + FTM1_CNTIN = 0; + FTM1_MOD = (48000000 / precision) - 1; + + // Select Bus clock as clock source, set prescaler divisor to 2^0 = 1, + // enable timer overflow interrupt + FTM1_SC |= FTM_SC_CLKS(1) | FTM_SC_PS(0) | FTM_SC_TOIE_MASK; + + // set FTM1 interrupt handler + enable_irq(INT_FTM1-16); + #elif defined(LandungsbrueckeV3) + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + timer_parameter_struct tps; + timer_struct_para_init(&tps); + + tps.period = 914; + + timer_init(TIMER2, &tps); + timer_interrupt_enable(TIMER2, TIMER_INT_UP); + timer_update_event_enable(TIMER2); + timer_enable(TIMER2); + + nvic_irq_enable(TIMER2_IRQn, 1, 1); + #endif +} + +void StepDir_deInit() +{ + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // Only disable the module if it has been enabled before + if (SIM_SCGC6 & SIM_SCGC6_FTM1_MASK) + { + // Disable interrupt in FTM module + FTM1_SC &= ~FTM_SC_TOIE_MASK; + + // Disable the FTM module + FTM1_MODE &= ~FTM_MODE_FTMEN_MASK; + + // Disable the interrupt + disable_irq(INT_FTM1-16); + + // Ensure that the module is disabled BEFORE clock gating gets disabled. + // Without this the processor can crash under heavy FTM interrupt load. + asm volatile("DMB"); + + // Disable clock gating for the FTM module + SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; + SIM_SCGC6 &= ~SIM_SCGC6_FTM1_MASK; + } + #endif +} + +// ===== Helper function ===== +/* The required calculation to do is the difference of the required + * amount of steps to reach a given velocity, using two different + * given accelerations with an evenly accelerated ramp. + * + * Calculation: + * v1: Start velocity + * v2: Target velocity + * a: Acceleration + * t: Time required to reach the target velocity + * s: distance traveled while accelerating + * + * t = (v2 - v1) / a + * The distance can be calculated with the average velocity v_avrg: + * v_avrg = (v2 + v1) / 2 + * s = v_avrg * t + * = (v2 + v1) / 2 * (v2 - v1) / a + * = (v2 + v1) * (v2 - v1) / (2*a) + * = (v2^2 - v1^2) / (2*a) + * + * Our calculation assumes that the starting velocity v1 is zero: + * v1 := 0 + * s = (v2^2 - 0^2) / (2*a) + * = v2^2 / (2*a) + * + * Calculating velocities with an accumulator results in the velocity + * being equal or up to 1 below the theoretical velocity (distributed evenly). + * To reduce the maximum error in the result of the step calculation, + * the velocity will be increased by 0.5, so that the velocity error + * will be within [0.5, -0.5). + * s = (v+0.5)^2 / (2*a) + * Change to using integer math: + * s = ((v+0.5)*2/2)^2 / (2*a) + * = ((v*2 + 1)/2)^2 / (2*a) + * = (v*2 + 1)^2 / 2^2 / (2*a) + * = (v*2 + 1)^2 / (8a) + * + * The result we need is the difference s2 - s1, using a2 and a1 respectively. + * Only changing the acceleration allows us to reuse most of the calculation: + * We define + * x := (v*2 + 1)^2 / 8 + * so that + * s = x/a + * + * Variables <=> Formula: + * oldAccel: a2 + * newAccel: a1 + * velocity: v + * oldSteps: s1 + * newSteps: s2 + */ +static int32_t calculateStepDifference(int32_t velocity, uint32_t oldAccel, uint32_t newAccel) +{ + int64_t tmp = velocity; + tmp = tmp * 2 + 1; + tmp = (tmp * tmp) / 4; + tmp = tmp / 2; + uint32_t oldSteps = tmp / oldAccel; + uint32_t newSteps = tmp / newAccel; + + return newSteps - oldSteps; +} + +// This helper function implements stallguard logic that is used both in the +// interrupt and main loop code. It is used to optimize the interrupt case. +static inline void checkStallguard(StepDirectionTypedef *channel, bool stallSignalActive) +{ + if (channel->stallGuardActive && stallSignalActive) + { + stop(channel, STOP_STALL); + } +} + +static inline void stop(StepDirectionTypedef *channel, StepDirStop stopType) +{ + switch(stopType) + { + case STOP_NORMAL: + tmc_ramp_linear_set_targetVelocity(&channel->ramp, 0); + tmc_ramp_linear_set_mode(&channel->ramp, TMC_RAMP_LINEAR_MODE_VELOCITY); + break; + case STOP_EMERGENCY: + channel->haltingCondition |= STATUS_EMERGENCY_STOP; + break; + case STOP_STALL: + channel->haltingCondition |= STATUS_STALLED; + tmc_ramp_linear_set_rampVelocity(&channel->ramp, 0); + channel->ramp.accumulatorVelocity = 0; + tmc_ramp_linear_set_targetVelocity(&channel->ramp, 0); + channel->ramp.accelerationSteps = 0; + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/tmc/StepDir.h b/Clean_TMC2209/lib/tmc/tmc/StepDir.h new file mode 100644 index 0000000..bf64ae1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/StepDir.h @@ -0,0 +1,110 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef STEP_DIR_H_ +#define STEP_DIR_H_ + + #include "tmc/helpers/API_Header.h" + #include "tmc/ramp/LinearRamp1.h" + + #include "tmc/hal/HAL.h" + + #define STEPDIR_FREQUENCY (1 << 17) + #define STEPDIR_MAX_VELOCITY STEPDIR_FREQUENCY // Limit: 1 Step per interrupt (2^17 Hz) -> 2^17 pps + #define STEPDIR_MAX_ACCELERATION 2147418111 // Limit: Highest value above accumulator digits (0xFFFE0000). + // Any value above would lead to acceleration overflow whenever the accumulator digits overflow + + #define STEPDIR_DEFAULT_ACCELERATION 100000 + #define STEPDIR_DEFAULT_VELOCITY STEPDIR_MAX_VELOCITY + + typedef enum { + STEPDIR_INTERNAL = 0, + STEPDIR_EXTERNAL = 1 + } StepDirMode; // Has to be set explicitly here because IDE relies on this number. + + typedef enum { + STOP_NORMAL, + STOP_EMERGENCY, + STOP_STALL + } StepDirStop; + + typedef enum { + SYNC_IDLE, // Sync mechanism not running + SYNC_SNAPSHOT_REQUESTED, // Main code saved the new acceleration and is waiting for the interrupt to save the velocity and apply the acceleration (atomically, from the StepDir generator perspective). + SYNC_SNAPSHOT_SAVED, // Interrupt saved the velocity + SYNC_UPDATE_DATA // Main code calculated an accelerationSteps difference which the interrupt needs to apply. + } StepDirSync; + + // StepDir status bits + #define STATUS_EMERGENCY_STOP 0x01 // Halting condition - Emergency Off + #define STATUS_NO_STEP_PIN 0x02 // Halting condition - No pin set for Step output + #define STATUS_NO_DIR_PIN 0x04 // Halting condition - No pin set for Direction output + #define STATUS_STALLED 0x08 // Halting condition - Stall detected (while Stallguard is enabled) + #define STATUS_TARGET_REACHED 0x10 // Position mode status - target reached + #define STATUS_STALLGUARD_ACTIVE 0x20 // Stallguard status - Velocity threshold reached, Stallguard enabled + #define STATUS_MODE 0x40 // 0: Positioning mode, 1: Velocity mode + + typedef struct + { // Generic parameters + uint8_t haltingCondition; + // StallGuard + bool stallGuardActive; + int32_t stallGuardThreshold; + IOPinTypeDef *stallGuardPin; + // StepDir Pins + IOPinTypeDef *stepPin; + IOPinTypeDef *dirPin; + // Acceleration updating sync mechanism (see acceleration setter for details) + StepDirSync syncFlag; // Synchronisation flag between main code & interrupt + // Snapshot data + // Interrupt -> main code + int32_t oldVelocity; + int32_t oldVelAccu; + // Main code -> interrupt + uint32_t newAcceleration; + int32_t stepDifference; + StepDirMode mode; + uint32_t frequency; + + TMC_LinearRamp ramp; + } StepDirectionTypedef; + + void StepDir_rotate(uint8_t channel, int32_t velocity); + void StepDir_moveTo(uint8_t channel, int32_t position); + void StepDir_periodicJob(uint8_t channel); + void StepDir_stop(uint8_t channel, StepDirStop stopType); + uint8_t StepDir_getStatus(uint8_t channel); + void StepDir_setPins(uint8_t channel, IOPinTypeDef *stepPin, IOPinTypeDef *dirPin, IOPinTypeDef *stallPin); + void StepDir_stallGuard(uint8_t channel, bool stall); + + // ===== Setters ===== + void StepDir_setActualPosition(uint8_t channel, int32_t actualPosition); + void StepDir_setAcceleration(uint8_t channel, uint32_t actualAcceleration); + void StepDir_setVelocityMax(uint8_t channel, int32_t velocityMax); + void StepDir_setStallGuardThreshold(uint8_t channel, int32_t stallGuardThreshold); + void StepDir_setMode(uint8_t channel, StepDirMode mode); + void StepDir_setFrequency(uint8_t channel, uint32_t frequency); + void StepDir_setPrecision(uint8_t channel, uint32_t precision); + // ===== Getters ===== + int32_t StepDir_getActualPosition(uint8_t channel); + int32_t StepDir_getTargetPosition(uint8_t channel); + int32_t StepDir_getActualVelocity(uint8_t channel); + int32_t StepDir_getTargetVelocity(uint8_t channel); + uint32_t StepDir_getAcceleration(uint8_t channel); + int32_t StepDir_getVelocityMax(uint8_t channel); + int32_t StepDir_getStallGuardThreshold(uint8_t channel); + StepDirMode StepDir_getMode(uint8_t channel); + uint32_t StepDir_getFrequency(uint8_t channel); + uint32_t StepDir_getPrecision(uint8_t channel); + int32_t StepDir_getMaxAcceleration(uint8_t channel); + + void StepDir_init(uint32_t precision); + void StepDir_deInit(void); + +#endif /* STEP_DIR_H_ */ diff --git a/Clean_TMC2209/lib/tmc/tmc/TMCL.c b/Clean_TMC2209/lib/tmc/tmc/TMCL.c new file mode 100644 index 0000000..450b0e9 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/TMCL.c @@ -0,0 +1,1171 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCL.h" +#include "BoardAssignment.h" +#include "hal/derivative.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "tmc/StepDir.h" +#include "EEPROM.h" +#include "RAMDebug.h" +#include "hal/Timer.h" + +// these addresses are fixed +#define SERIAL_MODULE_ADDRESS 1 +#define SERIAL_HOST_ADDRESS 2 + +// todo CHECK 2: these are unused - delete? (LH) #11 +// tmcl interpreter states +#define TM_IDLE 0 +#define TM_RUN 1 +#define TM_STEP 2 +#define TM_RESET 3 // unused +#define TM_DOWNLOAD 4 +#define TM_DEBUG 5 // wie TM_IDLE, es wird jedoch der Akku nicht modifiziert bei GAP etc. + +// todo CHECK 2: these are unused - delete? (LH) #12 +#define TCS_IDLE 0 +#define TCS_CAN7 1 +#define TCS_CAN8 2 +#define TCS_UART 3 +#define TCS_UART_ERROR 4 +#define TCS_UART_II 5 +#define TCS_UART_II_ERROR 6 +#define TCS_USB 7 +#define TCS_USB_ERROR 8 +#define TCS_MEM 9 + +// TMCL commands +#define TMCL_ROR 1 +#define TMCL_ROL 2 +#define TMCL_MST 3 +#define TMCL_MVP 4 +#define TMCL_SAP 5 +#define TMCL_GAP 6 +#define TMCL_STAP 7 +#define TMCL_RSAP 8 +#define TMCL_SGP 9 +#define TMCL_GGP 10 +#define TMCL_STGP 11 +#define TMCL_RSGP 12 +#define TMCL_RFS 13 +#define TMCL_SIO 14 +#define TMCL_GIO 15 +#define TMCL_CALC 19 +#define TMCL_COMP 20 +#define TMCL_JC 21 +#define TMCL_JA 22 +#define TMCL_CSUB 23 +#define TMCL_RSUB 24 +#define TMCL_EI 25 +#define TMCL_DI 26 +#define TMCL_WAIT 27 +#define TMCL_STOP 28 +#define TMCL_SAC 29 +#define TMCL_SCO 30 +#define TMCL_GCO 31 +#define TMCL_CCO 32 +#define TMCL_CALCX 33 +#define TMCL_AAP 34 +#define TMCL_AGP 35 +#define TMCL_CLE 36 +#define TMCL_VECT 37 +#define TMCL_RETI 38 +#define TMCL_ACO 39 + +#define TMCL_UF0 64 +#define TMCL_UF1 65 +#define TMCL_UF2 66 +#define TMCL_UF3 67 +#define TMCL_UF4 68 +#define TMCL_UF5 69 +#define TMCL_UF6 70 +#define TMCL_UF7 71 +#define TMCL_UF8 72 + +#define TMCL_ApplStop 128 +#define TMCL_ApplRun 129 +#define TMCL_ApplStep 130 +#define TMCL_ApplReset 131 +#define TMCL_DownloadStart 132 +#define TMCL_DownloadEnd 133 +#define TMCL_ReadMem 134 +#define TMCL_GetStatus 135 +#define TMCL_GetVersion 136 +#define TMCL_FactoryDefault 137 +#define TMCL_SetEvent 138 +#define TMCL_SetASCII 139 +#define TMCL_SecurityCode 140 +#define TMCL_Breakpoint 141 +#define TMCL_RamDebug 142 +#define TMCL_GetIds 143 +#define TMCL_UF_CH1 144 +#define TMCL_UF_CH2 145 +#define TMCL_writeRegisterChannel_1 146 +#define TMCL_writeRegisterChannel_2 147 +#define TMCL_readRegisterChannel_1 148 +#define TMCL_readRegisterChannel_2 149 + +#define TMCL_BoardMeasuredSpeed 150 +#define TMCL_BoardError 151 +#define TMCL_BoardReset 152 + +#define TMCL_WLAN 160 +#define TMCL_WLAN_CMD 160 +#define TMCL_WLAN_IS_RTS 161 +#define TMCL_WLAN_CMDMODE_EN 162 +#define TMCL_WLAN_IS_CMDMODE 163 + +#define TMCL_MIN 170 +#define TMCL_MAX 171 +#define TMCL_OTP 172 + +#define TMCL_Boot 242 +#define TMCL_SoftwareReset 255 + +// Command type variants +#define MVP_ABS 0 +#define MVP_REL 1 +#define MVP_PRF 2 + +// GetVersion() Format types +#define VERSION_FORMAT_ASCII 0 +#define VERSION_FORMAT_BINARY 1 +#define VERSION_BOOTLOADER 2 // todo CHECK 2: implemented this way in IDE - probably means getting the bootloader version. Not implemented in firmware (LH) +#define VERSION_SIGNATURE 3 // todo CHECK 2: implemented under "Signature" in IDE. Not sure what to return for that. Not implemented in firmware (LH) +#define VERSION_BOARD_DETECT_SRC 4 // todo CHECK 2: This doesn't really fit under GetVersion, but its implemented there in the IDE - change or leave this way? (LH) +#define VERSION_BUILD 5 + +//Statuscodes +#define REPLY_OK 100 +#define REPLY_CMD_LOADED 101 +#define REPLY_CHKERR 1 +#define REPLY_INVALID_CMD 2 +#define REPLY_INVALID_TYPE 3 +#define REPLY_INVALID_VALUE 4 +#define REPLY_EEPROM_LOCKED 5 +#define REPLY_CMD_NOT_AVAILABLE 6 +#define REPLY_CMD_LOAD_ERROR 7 +#define REPLY_WRITE_PROTECTED 8 +#define REPLY_MAX_EXCEEDED 9 +#define REPLY_DOWNLOAD_NOT_POSSIBLE 10 +#define REPLY_CHIP_READ_FAILED 11 +#define REPLY_DELAYED 128 +#define REPLY_ACTIVE_COMM 129 + +// TMCL communication status +#define TMCL_RX_ERROR_NONE 0 +#define TMCL_RX_ERROR_NODATA 1 +#define TMCL_RX_ERROR_CHECKSUM 2 + +extern const char *VersionString; + +// TMCL request +typedef struct +{ + uint8_t Opcode; + uint8_t Type; + uint8_t Motor; + uint32_t Error; + union + { + uint8_t Byte[4]; + uint32_t UInt32; + int32_t Int32; + float32_t Float32; + } Value; +} TMCLCommandTypeDef; + +// TMCL reply +typedef struct +{ + uint8_t Status; + uint8_t Opcode; + union + { + uint8_t Byte[4]; + uint32_t UInt32; + int32_t Int32; + float32_t Float32; + } Value; + + uint8_t Special[9]; + uint8_t IsSpecial; // next transfer will not use the serial address and the checksum bytes - instead the whole datagram is filled with data (used to transmit ASCII version string) +} TMCLReplyTypeDef; + +void ExecuteActualCommand(); +uint8_t setTMCLStatus(uint8_t evalError); +void rx(RXTXTypeDef *RXTX); +void tx(RXTXTypeDef *RXTX); + +static uint16_t getExtendedAddress(TMCLCommandTypeDef *tmclCommand) +{ + return (((uint16_t) tmclCommand->Motor >> 4) << 8) | tmclCommand->Type; +} + +// Helper functions - used to prevent ExecuteActualCommand() from getting too big. +// No parameters or return value are used. +static void readIdEeprom(void); +static void writeIdEeprom(void); +static void SetGlobalParameter(void); +static void GetGlobalParameter(void); +static void boardAssignment(void); +static void boardsErrors(void); +static void boardsReset(void); +static void boardsMeasuredSpeed(void); +static void setDriversEnable(void); +static void checkIDs(void); +static void SoftwareReset(void); +static void GetVersion(void); +static void GetInput(void); +static void HandleWlanCommand(void); +static void handleRamDebug(void); +static void handleOTP(void); + +TMCLCommandTypeDef ActualCommand; +TMCLReplyTypeDef ActualReply; +RXTXTypeDef interfaces[4]; +uint32_t numberOfInterfaces; +uint32_t resetRequest = 0; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // ToDo: Remove the duplicate declaration of the struct here and in main.c + struct BootloaderConfig { + uint32_t BLMagic; + uint32_t drvEnableResetValue; + }; + + extern struct BootloaderConfig BLConfig; +#elif defined(LandungsbrueckeV3) + // ToDo: Remove the duplicate declaration of the struct here and in main.c + struct BootloaderConfig { + uint32_t BLMagic; + }; + + extern struct BootloaderConfig BLConfig; +#endif + +// Sets TMCL status from Evalboard error. Returns the parameter given to allow for compact error handling +uint8_t setTMCLStatus(uint8_t evalError) +{ + if(evalError == TMC_ERROR_NONE) ActualReply.Status = REPLY_OK; + else if(evalError & TMC_ERROR_FUNCTION) ActualReply.Status = REPLY_INVALID_CMD; + else if(evalError & TMC_ERROR_TYPE) ActualReply.Status = REPLY_INVALID_TYPE; + else if(evalError & TMC_ERROR_MOTOR) ActualReply.Status = REPLY_INVALID_TYPE; // todo CHECK ADD 2: Different errors for Evalboard type/motor errors? (LH) #1 + else if(evalError & TMC_ERROR_VALUE) ActualReply.Status = REPLY_INVALID_VALUE; + else if(evalError & TMC_ERROR_NOT_DONE) ActualReply.Status = REPLY_DELAYED; + else if(evalError & TMC_ERROR_CHIP) ActualReply.Status = REPLY_EEPROM_LOCKED; + return evalError; +} + +void ExecuteActualCommand() +{ + ActualReply.Opcode = ActualCommand.Opcode; + ActualReply.Status = REPLY_OK; + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + + if(ActualCommand.Error == TMCL_RX_ERROR_CHECKSUM) + { + ActualReply.Value.Int32 = 0; + ActualReply.Status = REPLY_CHKERR; + return; + } + + switch(ActualCommand.Opcode) + { + case TMCL_ROR: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.right(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.right(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_ROL: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.left(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.left(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_MST: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.stop(ActualCommand.Motor)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.stop(ActualCommand.Motor)); + } + break; + case TMCL_MVP: + // if function doesn't exist for ch1 try ch2 + switch(ActualCommand.Type) + { + case MVP_ABS: // move absolute + if(setTMCLStatus(Evalboards.ch1.moveTo(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveTo(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case MVP_REL: // move relative + if(setTMCLStatus(Evalboards.ch1.moveBy(ActualCommand.Motor, &ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveBy(ActualCommand.Motor, &ActualCommand.Value.Int32)); + } + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case MVP_PRF: + if(setTMCLStatus(Evalboards.ch1.moveProfile(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveProfile(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } + break; + case TMCL_SAP: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.SAP(ActualCommand.Type, ActualCommand.Motor, ActualCommand.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.SAP(ActualCommand.Type, ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_GAP: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.GAP(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.GAP(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_SGP: + SetGlobalParameter(); + break; + case TMCL_GGP: + GetGlobalParameter(); + break; + case TMCL_GIO: + GetInput(); + break; + case TMCL_UF0: + setDriversEnable(); + break; + case TMCL_UF1: + readIdEeprom(); + break; + case TMCL_UF2: + writeIdEeprom(); + break; + case TMCL_UF4: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_UF5: + // if function doesn't exist for ch1 try ch2 // todo CHECK REM 2: We have TMCL_writeRegisterChannel_1, we dont need this. Make sure it isnt used in IDE (LH) #1 + Evalboards.ch1.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_UF6: + // if function doesn't exist for ch1 try ch2 // todo CHECK REM 2: We have TMCL_readRegisterChannel_1, we dont need this. Make sure it isnt used in IDE (LH) #2 + Evalboards.ch1.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + break; + case TMCL_UF8: + // user function for reading Motor0_XActual and Motor1_XActual + Evalboards.ch1.userFunction(ActualCommand.Type, 0, &ActualCommand.Value.Int32); + int32_t m0XActual = ActualCommand.Value.Int32; + Evalboards.ch1.userFunction(ActualCommand.Type, 1, &ActualCommand.Value.Int32); + int32_t m1XActual = ActualCommand.Value.Int32; + ActualReply.Value.Byte[0]= m1XActual & 0xFF; + ActualReply.Value.Byte[1]= (m1XActual & 0xFF00)>>8; + ActualReply.Value.Byte[2]= (m1XActual & 0xFF0000)>>16; + ActualReply.Value.Byte[3]= m0XActual & 0xFF; + ActualReply.Opcode= (m0XActual & 0xFF00)>>8; + ActualReply.Status= (m0XActual & 0xFF0000)>>16; + break; + case TMCL_GetVersion: + GetVersion(); + break; + case TMCL_GetIds: + boardAssignment(); + break; + case TMCL_UF_CH1: + // user function for motionController board + setTMCLStatus(Evalboards.ch1.userFunction(ActualCommand.Type, ActualCommand.Motor, &ActualCommand.Value.Int32)); + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case TMCL_UF_CH2: + // user function for driver board + setTMCLStatus(Evalboards.ch2.userFunction(ActualCommand.Type, ActualCommand.Motor, &ActualCommand.Value.Int32)); + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case TMCL_writeRegisterChannel_1: + Evalboards.ch1.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_writeRegisterChannel_2: + Evalboards.ch2.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_readRegisterChannel_1: + // Do not allow reads during brownout to prevent garbage data being used + // in read-modify-write operations. Bypass this safety with motor = 255 + if ((VitalSignsMonitor.brownOut & VSM_ERRORS_BROWNOUT_CH1) && ActualCommand.Motor != 255) + { + ActualReply.Status = REPLY_CHIP_READ_FAILED; + } + else + { + Evalboards.ch1.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + } + break; + case TMCL_readRegisterChannel_2: + // Do not allow reads during brownout to prevent garbage data being used + // in read-modify-write operations. Bypass this safety with motor = 255 + if ((VitalSignsMonitor.brownOut & VSM_ERRORS_BROWNOUT_CH2) && ActualCommand.Motor != 255) + ActualReply.Status = REPLY_CHIP_READ_FAILED; + else + Evalboards.ch2.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + break; + case TMCL_BoardMeasuredSpeed: + // measured speed from motionController board or driver board depending on type + boardsMeasuredSpeed(); + break; + case TMCL_BoardError: + // errors of motionController board or driver board depending on type + boardsErrors(); + break; + case TMCL_BoardReset: + // reset of motionController board or driver board depending on type + boardsReset(); + break; + case TMCL_WLAN: + HandleWlanCommand(); + break; + case TMCL_RamDebug: + handleRamDebug(); + break; + case TMCL_OTP: + handleOTP(); + break; + case TMCL_MIN: + if(setTMCLStatus(Evalboards.ch1.getMin(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.getMin(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_MAX: + if(setTMCLStatus(Evalboards.ch1.getMax(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.getMax(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_Boot: + if(ActualCommand.Type != 0x81) break; + if(ActualCommand.Motor != 0x92) break; + if(ActualCommand.Value.Byte[3] != 0xA3) break; + if(ActualCommand.Value.Byte[2] != 0xB4) break; + if(ActualCommand.Value.Byte[1] != 0xC5) break; + if(ActualCommand.Value.Byte[0] != 0xD6) break; + tmcl_boot(); + break; + case TMCL_SoftwareReset: + SoftwareReset(); + break; + default: + ActualReply.Status = REPLY_INVALID_CMD; + break; + } +} + +void tmcl_init() +{ + ActualCommand.Error = TMCL_RX_ERROR_NODATA; + interfaces[0] = *HAL.USB; + interfaces[1] = *HAL.RS232; + interfaces[2] = *HAL.WLAN; + numberOfInterfaces = 3; +} + +void tmcl_process() +{ + static int32_t currentInterface = 0; + + if(ActualCommand.Error != TMCL_RX_ERROR_NODATA) + tx(&interfaces[currentInterface]); + + if(resetRequest) + HAL.reset(true); + + ActualReply.IsSpecial = 0; + + for(uint32_t i = 0; i < numberOfInterfaces; i++) + { + rx(&interfaces[i]); + if(ActualCommand.Error != TMCL_RX_ERROR_NODATA) + { + currentInterface = i; + ExecuteActualCommand(); + return; + } + } +} + +void tx(RXTXTypeDef *RXTX) +{ + uint8_t checkSum = 0; + + uint8_t reply[9]; + + if(ActualReply.IsSpecial) + { + for(uint8_t i = 0; i < 9; i++) + reply[i] = ActualReply.Special[i]; + } + else + { + checkSum += SERIAL_HOST_ADDRESS; + checkSum += SERIAL_MODULE_ADDRESS; + checkSum += ActualReply.Status; + checkSum += ActualReply.Opcode; + checkSum += ActualReply.Value.Byte[3]; + checkSum += ActualReply.Value.Byte[2]; + checkSum += ActualReply.Value.Byte[1]; + checkSum += ActualReply.Value.Byte[0]; + + reply[0] = SERIAL_HOST_ADDRESS; + reply[1] = SERIAL_MODULE_ADDRESS; + reply[2] = ActualReply.Status; + reply[3] = ActualReply.Opcode; + reply[4] = ActualReply.Value.Byte[3]; + reply[5] = ActualReply.Value.Byte[2]; + reply[6] = ActualReply.Value.Byte[1]; + reply[7] = ActualReply.Value.Byte[0]; + reply[8] = checkSum; + } + + RXTX->txN(reply, 9); +} + +void rx(RXTXTypeDef *RXTX) +{ + uint8_t checkSum = 0; + uint8_t cmd[9]; + + if(!RXTX->rxN(cmd, 9)) + { + ActualCommand.Error = TMCL_RX_ERROR_NODATA; + return; + } + + // todo ADD CHECK 2: check for SERIAL_MODULE_ADDRESS byte ( cmd[0] ) ? (LH) + + for(uint8_t i = 0; i < 8; i++) + checkSum += cmd[i]; + + if(checkSum != cmd[8]) + { + ActualCommand.Error = TMCL_RX_ERROR_CHECKSUM; + return; + } + + ActualCommand.Opcode = cmd[1]; + ActualCommand.Type = cmd[2]; + ActualCommand.Motor = cmd[3]; + ActualCommand.Value.Byte[3] = cmd[4]; + ActualCommand.Value.Byte[2] = cmd[5]; + ActualCommand.Value.Byte[1] = cmd[6]; + ActualCommand.Value.Byte[0] = cmd[7]; + ActualCommand.Error = TMCL_RX_ERROR_NONE; +} + +void tmcl_boot() +{ +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + if(Evalboards.ch1.id == ID_TMC4671) + { + // Driver Enable has to be set low by the bootloader for these ICs + BLConfig.drvEnableResetValue = 0; + } + else + { + // Default: Driver Enable is set to high + BLConfig.drvEnableResetValue = 1; + } +#endif + Evalboards.driverEnable = DRIVER_DISABLE; + Evalboards.ch1.enableDriver(DRIVER_DISABLE); // todo CHECK 2: the ch1/2 deInit() calls should already disable the drivers - keep this driver disabling to be sure or remove it and leave the disabling to deInit? (LH) + Evalboards.ch2.enableDriver(DRIVER_DISABLE); + + Evalboards.ch1.deInit(); + Evalboards.ch2.deInit(); + + HAL.USB->deInit(); + + wait(500); + + HAL.Timer->deInit(); + HAL.RS232->deInit(); + HAL.WLAN->deInit(); + HAL.ADCs->deInit(); + + // todo: CHECK 2: Muss api_deInit hier dazu? (ED) + StepDir_deInit(); + + IDDetection_deInit(); + + HAL.NVIC_DeInit(); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) || defined(LandungsbrueckeV3) + BLConfig.BLMagic = 0x12345678; + HAL.reset(true); +#endif +} + +/* + * Reads four bytes from the eeprom. + * + * @param channel Id of SPI channel to be used with 1 = SPI.ch1 and 2 = SPI.ch2 + * @param address Address the byte should be read from. + * + * @return The bytes read with byte0 = lowest byte or 0 if reading went unsuccessful + */ +static void readIdEeprom(void) +{ + SPIChannelTypeDef *spi; + if(ActualCommand.Type == 1) + spi = &SPI.ch1; + else if(ActualCommand.Type == 2) + spi = &SPI.ch2; + else + { + ActualReply.Status = REPLY_INVALID_TYPE; + return; + } + + uint8_t array[4]; + eeprom_read_array(spi, ActualCommand.Value.Int32, array, 4); + ActualReply.Value.Int32 = array[3] << 24 | array[2] << 16 | array[1] << 8 | array[0]; +} + +/* + * Writes one byte into the eeprom for id detection. + * + * @param channel Id of SPI channel to be used with 1 = SPI.ch1 and 2 = SPI.ch2 + * @param address Address the byte should be written to. + * @param bytes Pointer to byte array that are to be written. The first byte is always written + * following bytes are written as long as they are not null. + * + * @return false if everything went successful + * 1 if selected channel is not available + * the status bits of the eeprom if eeprom is not ready + */ +static void writeIdEeprom(void) +{ + SPIChannelTypeDef *spi; + if(ActualCommand.Type == 1) + spi = &SPI.ch1; + else if(ActualCommand.Type == 2) + spi = &SPI.ch2; + else + { + ActualReply.Status = REPLY_INVALID_TYPE; + return; + } + + uint8_t out = eeprom_check(spi); + // ignore when check did not find magic number, quit on other errors + if(out != ID_CHECKERROR_MAGICNUMBER && out != 0) + { + ActualReply.Status = REPLY_EEPROM_LOCKED; // todo CHECK 2: Not sure which error to send here, this one sounded ok (LH) + return; + } + + eeprom_write_byte(spi, ActualCommand.Value.Int32, ActualCommand.Motor); + + return; +} + +static void SetGlobalParameter() +{ + switch(ActualCommand.Type) + { + case 1: + VitalSignsMonitor.errorMask = ActualCommand.Value.Int32; + break; + case 2: + setDriversEnable(); + break; + case 3: + switch(ActualCommand.Value.Int32) + { + case 0: // normal operation + VitalSignsMonitor.debugMode = 0; + break; + case 1: // FREE ERROR LED + VitalSignsMonitor.debugMode = 1; + HAL.LEDs->error.off(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } + break; + case 6: + if(Evalboards.ch1.onPinChange(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32) + && Evalboards.ch2.onPinChange(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32)) + HAL.IOs->config->setToState(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32); + break; + case 7: + ActualReply.Value.UInt32 = spi_setFrequency(&HAL.SPI->ch1, ActualCommand.Value.UInt32); + break; + case 8: + ActualReply.Value.UInt32 = spi_setFrequency(&HAL.SPI->ch2, ActualCommand.Value.UInt32); + break; + case 9: + if (!spi_setMode(&HAL.SPI->ch1, ActualCommand.Value.UInt32)) + { + ActualReply.Status = REPLY_INVALID_VALUE; + break; + } + break; + case 10: + if (!spi_setMode(&HAL.SPI->ch2, ActualCommand.Value.UInt32)) + { + ActualReply.Status = REPLY_INVALID_VALUE; + break; + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void GetGlobalParameter() +{ + switch(ActualCommand.Type) + { + case 1: + ActualReply.Value.Int32 = VitalSignsMonitor.errors; + break; + case 2: + ActualReply.Value.Int32 = (Evalboards.driverEnable == DRIVER_ENABLE)? 1:0; + break; + case 3: + ActualReply.Value.Int32 = VitalSignsMonitor.debugMode; + break; + case 4: + { + IdAssignmentTypeDef ids; + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + ActualReply.Value.Int32 = Board_supported(&ids); + } + break; + case 5: // Get hardware ID + ActualReply.Value.Int32 = hwid; + break; + case 6: + ActualReply.Value.UInt32 = HAL.IOs->config->getState(HAL.IOs->pins->pins[ActualCommand.Motor]); + break; + case 7: + ActualReply.Value.UInt32 = spi_getFrequency(&HAL.SPI->ch1); + break; + case 8: + ActualReply.Value.UInt32 = spi_getFrequency(&HAL.SPI->ch2); + break; + case 9: + ActualReply.Value.UInt32 = spi_getMode(&HAL.SPI->ch1); + break; + case 10: + ActualReply.Value.UInt32 = spi_getMode(&HAL.SPI->ch2); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardAssignment(void) +{ + uint8_t testOnly = 0; + + IdAssignmentTypeDef ids; + ids.ch1.id = (ActualCommand.Value.Int32 >> 0) & 0xFF; + ids.ch1.state = (ActualCommand.Value.Int32 >> 8) & 0xFF; + ids.ch2.id = (ActualCommand.Value.Int32 >> 16) & 0xFF; + ids.ch2.state = (ActualCommand.Value.Int32 >> 24) & 0xFF; + + switch(ActualCommand.Type) + { + case 0: // auto detect and assign + checkIDs(); + return; + break; + case 1: // id for channel 2 not changed, reset maybe + ids.ch2.id = Evalboards.ch2.id; + ids.ch2.state = ID_STATE_WAIT_LOW; + break; + case 2: // id for channel 1 not changed, reset maybe + ids.ch2.id = (ActualCommand.Value.Int32 >> 0) & 0xFF; + ids.ch2.state = (ActualCommand.Value.Int32 >> 8) & 0xFF; + ids.ch1.id = Evalboards.ch1.id; + ids.ch1.state = ID_STATE_WAIT_LOW; + break; + case 3: // id for both channels + break; + case 4: // test if ids are in firmware + testOnly = 1; + if(ActualReply.Value.Int32 == 0) + { + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + return; + break; + } + + IdAssignmentTypeDef ids_buff; + ids_buff.ch1.id = ids.ch1.id; + ids_buff.ch1.state = ID_STATE_DONE; + ids_buff.ch2.id = ids.ch2.id; + ids_buff.ch2.state = ID_STATE_DONE; + + if(!testOnly) + ActualReply.Value.Int32 = Board_assign(&ids_buff); + else + ActualReply.Value.Int32 = Board_supported(&ids_buff); +} + +static void boardsErrors(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = Evalboards.ch1.errors; + break; + case 1: + ActualReply.Value.Int32 = Evalboards.ch2.errors; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardsReset(void) +{ + switch(ActualCommand.Type) + { + case 0: + if(!Evalboards.ch1.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + case 1: + if(!Evalboards.ch2.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + case 2: + if(!Evalboards.ch1.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + if(!Evalboards.ch2.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardsMeasuredSpeed(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Status = Evalboards.ch1.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32); + break; + case 1: + ActualReply.Status = Evalboards.ch2.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void setDriversEnable() +{ + vitalsignsmonitor_clearOvervoltageErrors(); + + Evalboards.driverEnable = (ActualCommand.Value.Int32) ? DRIVER_ENABLE : DRIVER_DISABLE; + Evalboards.ch1.enableDriver(DRIVER_USE_GLOBAL_ENABLE); + Evalboards.ch2.enableDriver(DRIVER_USE_GLOBAL_ENABLE); +} + +static void checkIDs(void) +{ + IdAssignmentTypeDef ids = { 0 }; + + if(IDDetection_detect(&ids)) + { + ActualReply.Value.Int32 = (uint32_t) + ( + (ids.ch1.id) + | (ids.ch1.state << 8) + | (ids.ch2.id << 16) + | (ids.ch2.state << 24) + ); + + Board_assign(&ids); + } + else + { + ActualReply.Status = REPLY_DELAYED; + } +} + +static void SoftwareReset(void) +{ + if(ActualCommand.Value.Int32 == 1234) + resetRequest = true; +} + +static void GetVersion(void) +{ + if(ActualCommand.Type == VERSION_FORMAT_ASCII) + { + ActualReply.IsSpecial = 1; + ActualReply.Special[0] = SERIAL_HOST_ADDRESS; + + for(uint8_t i = 0; i < 8; i++) + ActualReply.Special[i+1] = VersionString[i]; + } + else if(ActualCommand.Type == VERSION_FORMAT_BINARY) + { + uint8_t tmpVal; + + // module version high + tmpVal = (uint8_t) VersionString[0] - '0'; // Ascii digit - '0' = digit value + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[1] - '0'; + ActualReply.Value.Byte[3] = tmpVal; + + // module version low + tmpVal = (uint8_t) VersionString[2] - '0'; + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[3] - '0'; + ActualReply.Value.Byte[2] = tmpVal; + + // fw version high + ActualReply.Value.Byte[1] = (uint8_t) VersionString[5] - '0'; + + // fw version low + tmpVal = (uint8_t) VersionString[6] - '0'; + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[7] - '0'; + ActualReply.Value.Byte[0] = tmpVal; + } + //how were the boards detected? // todo CHECK 2: Doesn't fit into GetVersion. Move somewhere else? Or maybe change GetVersion to GetBoardInfo or something (LH) + else if(ActualCommand.Type == VERSION_BOARD_DETECT_SRC) + { + ActualReply.Value.Byte[0] = IdState.ch1.detectedBy; + ActualReply.Value.Byte[1] = IdState.ch2.detectedBy; + } + else if(ActualCommand.Type == VERSION_BUILD) { + ActualReply.Value.UInt32 = BUILD_VERSION; + } +} + +static void GetInput(void) +{ + if((Evalboards.ch1.GIO(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32) == TMC_ERROR_NONE) + || (Evalboards.ch2.GIO(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32) == TMC_ERROR_NONE)) + return; + + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = *HAL.ADCs->AIN0; + break; + case 1: + ActualReply.Value.Int32 = *HAL.ADCs->AIN1; + break; + case 2: + ActualReply.Value.Int32 = *HAL.ADCs->AIN2; + break; + case 3: + ActualReply.Value.Int32 = *HAL.ADCs->DIO4; + break; + case 4: + ActualReply.Value.Int32 = *HAL.ADCs->DIO5; + break; + case 5: + ActualReply.Value.Int32 = VitalSignsMonitor.VM; + break; + case 6: // Raw VM ADC value, no scaling calculation done // todo QOL 2: Switch this case with case 5? That way we have the raw Values from 0-5, then 6 for scaled VM value. Requires IDE changes (LH) + ActualReply.Value.Int32 = *HAL.ADCs->VM; + break; + case 7: + ActualReply.Value.Int32 = *HAL.ADCs->AIN_EXT; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void HandleWlanCommand(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = handleWLANCommand(ActualCommand.Motor, ActualCommand.Value.Int32); + break; + case 1: + enableWLANCommandMode(); + break; + case 2: + ActualReply.Value.Int32 = checkReadyToSend(); + break; + case 3: + ActualReply.Value.Int32 = checkCmdModeEnabled(); + break; + case 4: + ActualReply.Value.Int32 = getCMDReply(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void handleRamDebug(void) +{ + switch (ActualCommand.Type) + { + case 0: + debug_init(); + break; + case 1: + debug_setSampleCount(ActualCommand.Value.Int32); + break; + case 2: + /* Placeholder: Set sampling time reference*/ + if (ActualCommand.Value.Int32 != 0) + ActualReply.Status = REPLY_INVALID_VALUE; + break; + case 3: + // RAMDebug expects a divisor value where 1 is original capture frequency, + // 2 is halved capture frequency etc. + // The TMCL-IDE sends prescaling values that are one lower than that. + debug_setPrescaler(ActualCommand.Value.Int32 + 1); + break; + case 4: + if (!debug_setChannel(ActualCommand.Motor, ActualCommand.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 5: + if (!debug_setTriggerChannel(ActualCommand.Motor, ActualCommand.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 6: + debug_setTriggerMaskShift(ActualCommand.Value.Int32, ActualCommand.Motor); + break; + case 7: + debug_enableTrigger(ActualCommand.Motor, ActualCommand.Value.Int32); + break; + case 8: + ActualReply.Value.Int32 = debug_getState(); + break; + case 9: + if (!debug_getSample(ActualCommand.Value.Int32, (uint32_t *)&ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 10: + ActualReply.Value.Int32 = debug_getInfo(ActualCommand.Value.Int32); + break; + case 11: + if (!debug_getChannelType(ActualCommand.Motor, (uint8_t *) &ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 12: + if (!debug_getChannelAddress(ActualCommand.Motor, (uint32_t *) &ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 13: + debug_setPretriggerSampleCount(ActualCommand.Value.UInt32); + break; + case 14: + ActualReply.Value.UInt32 = debug_getPretriggerSampleCount(); + break; + case 15: + if(Timer.initialized) { + Timer.setFrequency(TIMER_CHANNEL_2, ActualCommand.Value.UInt32); + ActualReply.Value.UInt32 = Timer.getPeriod(TIMER_CHANNEL_2); + } + break; + case 16: + if (!debug_setType(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 17: + if (!debug_setEvalChannel(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 18: + if (!debug_setAddress(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 19: + if (!debug_setTriggerType(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 20: + if (!debug_setTriggerEvalChannel(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 21: + if (!debug_setTriggerAddress(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void handleOTP(void) +{ + switch (ActualCommand.Type) + { + case 0: // OTP_INIT + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_init(); + break; + case 1: // OTP_ADDRESS + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_address(ActualCommand.Value.UInt32); + break; + case 2: // OTP_VALUE + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_value(ActualCommand.Value.UInt32); + break; + case 3: // OTP_PROGRAM + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_program(); + break; + case 4: // OTP_LOCK + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_lock(); + break; + case 5: // OTP_STATUS + ActualReply.Value.UInt32 = ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_status(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} diff --git a/Clean_TMC2209/lib/tmc/tmc/TMCL.h b/Clean_TMC2209/lib/tmc/tmc/TMCL.h new file mode 100644 index 0000000..3bd6bd1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/TMCL.h @@ -0,0 +1,19 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCL_H +#define TMCL_H + +#include "tmc/helpers/API_Header.h" + +void tmcl_init(); +void tmcl_process(); +void tmcl_boot(); + +#endif /* TMCL_H */ diff --git a/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.c b/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.c new file mode 100644 index 0000000..b7092f8 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "VitalSignsMonitor.h" + +#include "hal/derivative.h" +#include "boards/Board.h" +#include "hal/HAL.h" + +#define VM_MIN_INTERFACE_BOARD 70 // minimum motor supply voltage for system in [100mV] +#define VM_MAX_INTERFACE_BOARD 700 // maximum motor supply voltage for system in [100mV] + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +#define VM_FACTOR 713 // ADC reaches limit at VM = 71.3V => VM Factor (in 100mV) = 713 +#elif defined(LandungsbrueckeV3) +#define VM_FACTOR 744 +#endif + + +// Status LED frequencies +// Values are time in ms between LED toggles +#define VSM_HEARTRATE_NORMAL 500 // Normal: 1 Hz +#define VSM_HEARTRATE_FAST 50 // Busy: 10 Hz + +#define VSM_BROWNOUT_DELAY 100 // Delay (in 10ms) between voltage (re-)application and configuration restoration + +VitalSignsMonitorTypeDef VitalSignsMonitor = +{ + .brownOut = 0, // motor supply to low + .VM = 0, // actual measured motor supply VM + .heartRate = VSM_HEARTRATE_NORMAL, // status LED blinking frequency + .errorMask = 0xFFFFFFFF, // error mask, each bit stands for one error bit, 1 means error will be reported + .busy = 0, // if module is busy, status LED is blinking fast + .debugMode = 0, // debug mode e.g. releases error LED for debug purpose + .errors = 0 // actual error bits +}; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define ADC_VM_RES 65535 +#elif defined(LandungsbrueckeV3) + #define ADC_VM_RES 4095 +#endif + +// Make the status LED blink +// Frequency informs about normal operation or busy state +void heartBeat(uint32_t tick) +{ + static uint32_t lastTick = 0; + + if(VitalSignsMonitor.heartRate == 0) + return; + + if((tick - lastTick) > VitalSignsMonitor.heartRate) + { + LED_TOGGLE(); + lastTick = tick; + } +} + +// Check for over/undervoltage of motor supply VM +void checkVM() +{ + int32_t VM; + static uint8_t stable = VSM_BROWNOUT_DELAY + 1; // delay value + 1 is the state during normal voltage levels - set here to prevent restore shortly after boot + static uint8_t vio_state = 1; + + VM = *HAL.ADCs->VM; // read ADC value for motor supply VM + VM = (VM*VM_FACTOR)/ADC_VM_RES; // calculate voltage from ADC value + + VitalSignsMonitor.VM = VM; // write to interface + VitalSignsMonitor.overVoltage = 0; // reset overvoltage status + VitalSignsMonitor.brownOut = 0; // reset undervoltage status + + // check for over/undervoltage and set according status if necessary + if(VM > VM_MAX_INTERFACE_BOARD) VitalSignsMonitor.overVoltage |= VSM_CHX; + if(VM > Evalboards.ch1.VMMax) VitalSignsMonitor.overVoltage |= VSM_CHX | VSM_CH1; + if(VM > Evalboards.ch2.VMMax) VitalSignsMonitor.overVoltage |= VSM_CHX | VSM_CH2; + + // check for over/undervoltage and set according status if necessary + if (Evalboards.ch1.VMMin > 0) + if(VM < Evalboards.ch1.VMMin) VitalSignsMonitor.brownOut |= VSM_CHX | VSM_CH1; + if (Evalboards.ch2.VMMin > 0) + if(VM < Evalboards.ch2.VMMin) VitalSignsMonitor.brownOut |= VSM_CHX | VSM_CH2; + // Global minimum voltage check (skipped if a minimum voltage of 0 is set by a board) + if(Evalboards.ch1.VMMin && Evalboards.ch2.VMMin) + if(VM < VM_MIN_INTERFACE_BOARD) VitalSignsMonitor.brownOut |= VSM_CHX; + + if((VitalSignsMonitor.errors & VSM_ERRORS_CH1) || (VitalSignsMonitor.errors & VSM_ERRORS_CH2)) // VIO low in CH1 + { + if((Evalboards.ch1.errors & VSM_ERRORS_VIO_LOW) || (Evalboards.ch2.errors & VSM_ERRORS_VIO_LOW)) + { + vio_state = 0; + } + } + else if(vio_state == 0) // VIO high + { + Evalboards.ch2.config->reset(); + Evalboards.ch1.config->reset(); + vio_state = 1; + } + + // after brownout all settings are restored to the boards + // this happens after supply was stable for a set delay (checkVM() is called every 10 ms/systicks) + if(VitalSignsMonitor.brownOut) + { + stable = 0; + } + else + { + if(stable < VSM_BROWNOUT_DELAY) + { + stable++; + } + else if(stable == VSM_BROWNOUT_DELAY) + { + Evalboards.ch2.config->restore(); + Evalboards.ch1.config->restore(); + + stable++; + } + } +} + +/* Routine to frequently check system for errors */ +void vitalsignsmonitor_checkVitalSigns() +{ + int32_t errors = 0; + static uint32_t lastTick = 0; + uint32_t tick; + + tick = systick_getTick(); + + // Check motor supply VM every 10ms + if((tick - lastTick) >= 10) + { + checkVM(); + lastTick = tick; + } + + // Check for board errors + Evalboards.ch2.checkErrors(tick); + Evalboards.ch1.checkErrors(tick); + + // Status LED + heartBeat(tick); + + // reset all error bits but not the voltage errors + errors = VitalSignsMonitor.errors & (VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2); + + // collect errors from board channels + if(Evalboards.ch1.errors) + errors |= VSM_ERRORS_CH1; + if(Evalboards.ch2.errors) + errors |= VSM_ERRORS_CH2; + + if(VitalSignsMonitor.busy) + errors |= VSM_BUSY; + if(Evalboards.ch1.config->state != CONFIG_READY) + errors |= VSM_BUSY | VSM_BUSY_CH1; + if(Evalboards.ch2.config->state != CONFIG_READY) + errors |= VSM_BUSY | VSM_BUSY_CH2; + + if(VitalSignsMonitor.brownOut) + errors |= VSM_WARNING_CPU_SUPPLY_LOW; + if(VitalSignsMonitor.brownOut & VSM_CH1 ) + errors |= VSM_ERRORS_VM | VSM_ERRORS_BROWNOUT_CH1; + if(VitalSignsMonitor.brownOut & VSM_CH2 ) + errors |= VSM_ERRORS_VM | VSM_ERRORS_BROWNOUT_CH2; + + if(VitalSignsMonitor.overVoltage) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE; + if(VitalSignsMonitor.overVoltage & VSM_CH1) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1; + if(VitalSignsMonitor.overVoltage & VSM_CH2) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH2; + + VitalSignsMonitor.errors = errors & VitalSignsMonitor.errorMask; // write collected errors to interface + + // disable drivers on overvoltage + if(errors & (VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2)) + { + Evalboards.driverEnable = DRIVER_DISABLE; // set global driver enable to disabled + Evalboards.ch1.enableDriver(DRIVER_DISABLE); // disable driver for motion controller board + Evalboards.ch2.enableDriver(DRIVER_DISABLE); // disable driver for driver + } + + // set debug LED if not in debug mode + // set status LED if not in debug mode + if(!VitalSignsMonitor.debugMode) + { + if(VitalSignsMonitor.errors & (~(VSM_BUSY | VSM_BUSY_CH1 | VSM_BUSY_CH2 | VSM_WARNING_CPU_SUPPLY_LOW))) + HAL.LEDs->error.on(); + else + HAL.LEDs->error.off(); + + if(VitalSignsMonitor.errors & (VSM_BUSY | VSM_BUSY_CH1 | VSM_BUSY_CH2)) + VitalSignsMonitor.heartRate = VSM_HEARTRATE_FAST; + else + VitalSignsMonitor.heartRate = VSM_HEARTRATE_NORMAL; + } +} + +void vitalsignsmonitor_clearOvervoltageErrors() +{ + VitalSignsMonitor.errors &= ~(VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2); +} diff --git a/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.h b/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.h new file mode 100644 index 0000000..7829fb1 --- /dev/null +++ b/Clean_TMC2209/lib/tmc/tmc/VitalSignsMonitor.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef VITAL_SIGNS_MONITOR_H +#define VITAL_SIGNS_MONITOR_H + +#include "tmc/helpers/API_Header.h" + +typedef struct +{ + int8_t debugMode; // while debugMode is set, the error LED does not get set by VSM and status LED heartrate does not get updated + int8_t busy; // if module is busy, the status LED is blinking fast + uint8_t brownOut; // Undervoltage condition flags + uint8_t overVoltage; // Overvoltage condition flags + int32_t errorMask; // error mask, each bit stands for one error bit, 1 means error will be reported + int32_t errors; // actual error bits + uint32_t heartRate; // status LED blinking frequency + uint32_t VM; // actual measured motor supply VM +} VitalSignsMonitorTypeDef; + +extern VitalSignsMonitorTypeDef VitalSignsMonitor; // global implementation of interface for system + +// error bits +#define VSM_CHX (1<<0) // any errors on the evalboards +#define VSM_CH1 (1<<1) // any errors on motion controller board +#define VSM_CH2 (1<<2) // any errors on driver board + +#define VSM_ERRORS_VM (1<<0) // something's wrong with the motor supply VM for any board +#define VSM_ERRORS_CH1 (1<<1) // something's wrong with the motor supply VM for motion controller board +#define VSM_ERRORS_CH2 (1<<2) // something's wrong with the motor supply VM for driver board +#define VSM_BUSY (1<<3) // any board is busy +#define VSM_BUSY_CH1 (1<<4) // motion controller board is busy +#define VSM_BUSY_CH2 (1<<5) // driver board is busy +#define VSM_WARNING_CPU_SUPPLY_LOW (1<<6) // motor supply VM is to low for the processor -> Supply over USB needed +#define VSM_ERRORS_BROWNOUT_CH1 (1<<7) // motor supply VM is to low for motion controller board +#define VSM_ERRORS_BROWNOUT_CH2 (1<<8) // motor supply VM is to low for driver board +#define VSM_ERRORS_OVERVOLTAGE (1<<9) // motor supply VM is to high for any board +#define VSM_ERRORS_OVERVOLTAGE_CH1 (1<<10) // motor supply VM is to high for motion controller board +#define VSM_ERRORS_OVERVOLTAGE_CH2 (1<<11) // motor supply VM is to high for driver board + +#define VSM_ERRORS_VIO_LOW (1 << 1) + +void vitalsignsmonitor_checkVitalSigns(); +void vitalsignsmonitor_clearOvervoltageErrors(); + +#endif /* VITAL_SIGNS_MONITOR_H */ diff --git a/Clean_TMC2209/main.c b/Clean_TMC2209/main.c new file mode 100644 index 0000000..4258628 --- /dev/null +++ b/Clean_TMC2209/main.c @@ -0,0 +1,218 @@ + + +#include +#include "pico/stdlib.h" +#include "hardware/uart.h" +#include "hardware/irq.h" // Inclure le fichier d'en-tête pour les interruptions +#include "Tmc_uart.h" +#include "Tmc2209.h" + +#include "hardware/gpio.h" +#include "unistd.h" + + +TMC_UART uart_instance; +TMC2209 Tmc2209; + + + +void test_movement(){ + const uint LED_PIN = 7; + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + gpio_put(LED_PIN, 0); + + sleep_ms(1000); + int max = 1600; + for (int i = 100; i <= max; i += 100) { + set_vactual(&Tmc2209,i*256); + sleep_us(1); + int stg = get_stallguard(&Tmc2209); + printf("Stg : %d \n",stg); + } + + uint32_t start_time = time_us_32(); + uint32_t current_time = start_time; + + while (current_time - start_time < 10000000) { // 10 secondes en microsecondes + int stg = get_stallguard(&Tmc2209); + printf("Stg : %d \n",stg); + current_time = time_us_32(); + + } + + + + for (int i = max; i >= 100; i -= 100) { + set_vactual(&Tmc2209,i*256); + sleep_us(1); + int stg = get_stallguard(&Tmc2209); + printf("Stg : %d \n",stg); + } + set_vactual(&Tmc2209,0); + + // sleep_ms(10000); + gpio_put(LED_PIN, 1); + +} + + +void setup(){ + clear_general_stat(&Tmc2209); + // sleep_ms(2000); + set_voltage_sense(&Tmc2209, false); + // sleep_ms(2000); + set_current_flow(&Tmc2209, 100, 0.5, 10, 5.4); + // sleep_ms(2000); + set_iscale_analog(&Tmc2209, false); + // sleep_ms(2000); + set_interpolation(&Tmc2209, true); + // sleep_ms(2000); + set_internal_resistor_sense(&Tmc2209, false); + // sleep_ms(2000); + set_spread_cycle(&Tmc2209, true); + // sleep_ms(2000); + set_microstepping_resolution(&Tmc2209,256); + // sleep_ms(2000); + set_microstep_resolution_regselect(&Tmc2209, true); + int32_t resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution begin : %ld\n", resolution); +} + +void test_direction(){ + int direction = get_direction_shart(&Tmc2209); + printf("Direction 1 : %d\n", direction); + sleep_ms(1000); + + set_direction_shart(&Tmc2209,false); + sleep_ms(1000); + + direction = get_direction_shart(&Tmc2209); + printf("Direction 2 (false): %d\n", direction); + sleep_ms(1000); + + set_direction_shart(&Tmc2209,true); + sleep_ms(1000); + + direction = get_direction_shart(&Tmc2209); + printf("Direction 3 (true): %d\n", direction); +} + + +void test_ustep(){ + int32_t resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution begin : %ld\n", resolution); + sleep_ms(1000); + set_microstepping_resolution(&Tmc2209,256); + sleep_ms(1000); + resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution after new go to 1/256: %ld\n", resolution); + sleep_ms(1000); + set_microstepping_resolution(&Tmc2209,16); + sleep_ms(10); + resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution after renew go to 1/16: %ld\n", resolution); + printf(get_microstepping_resolution(&Tmc2209)); +} + +void test_iscale(){ + int iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 1 : %d\n", iscale); + sleep_ms(1000); + set_iscale_analog(&Tmc2209,false); + sleep_ms(1000); + iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 2 (false): %d\n", iscale); + sleep_ms(1000); + set_iscale_analog(&Tmc2209,true); + sleep_ms(1000); + iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 3 (true): %d\n", iscale); +} + +void test_interpolation(){ + int interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 1 : %d\n", interpolation); + sleep_ms(1000); + set_interpolation(&Tmc2209,false); + sleep_ms(1000); + interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 2 (false): %d\n", interpolation); + sleep_ms(1000); + set_interpolation(&Tmc2209,true); + sleep_ms(1000); + interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 3 (true): %d\n", interpolation); +} + +void test_internal_resistor_sense(){ + int resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 1 : %d\n", resistor); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,false); + sleep_ms(1000); + resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 2 (false): %d\n", resistor); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,true); + sleep_ms(1000); + resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 3 (true): %d\n", resistor); +} + +void test_spread_cycle(){ + int spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 1 : %d\n", spread_cycle); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,false); + sleep_ms(1000); + spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 2 (false): %d\n", spread_cycle); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,true); + sleep_ms(1000); + spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 3 (true): %d\n", spread_cycle); +} + + +int main() { + stdio_init_all(); + + + // Initialisation de l'UART avec les paramètres par défaut + + tmc_Uart_Init(&uart_instance, uart1, -1, -1, -1); + + + TMC2209_Init(&Tmc2209,&uart_instance); + + + + sleep_ms(4000); + + + // clear_general_stat(&uart_instance); + printf("UART initialisé avec succès\n"); + + // driver_status(&Tmc2209); + // general_config(&Tmc2209); + // general_stat(&Tmc2209); + + setup(); + + // test_iscale(); + // test_interpolation(); + // test_internal_resistor_sense(); + // test_spread_cycle(); + + // test_direction(); + + // test_ustep(); + + test_movement(); + + + return 0; +} + diff --git a/Gino_code/beone b/Gino_code/beone new file mode 160000 index 0000000..09ac0bb --- /dev/null +++ b/Gino_code/beone @@ -0,0 +1 @@ +Subproject commit 09ac0bbef990a411a5dbf51997f6f98155e2ac97 diff --git a/Motor_encod/AS5600L.c b/Motor_encod/AS5600L.c new file mode 100644 index 0000000..3bfe825 --- /dev/null +++ b/Motor_encod/AS5600L.c @@ -0,0 +1,93 @@ +#include "AS5600L.h" + +void as560x_init(AS5600L* as5600l, i2c_inst_t *I2C_ID, int frq , int sda, int scl ) { + i2c_init(I2C_ID, frq); + gpio_set_function(sda, GPIO_FUNC_I2C); + gpio_set_function(scl, GPIO_FUNC_I2C); + gpio_pull_up(sda); + gpio_pull_up(scl); + + AS5600L_I2C instance_i2c; + instance_i2c.I2C_PORT = I2C_ID; + instance_i2c.FREQUENCE = frq; + instance_i2c.I2C_SDA_PIN = sda; + instance_i2c.I2C_SCL_PIN = scl; + + as5600l->serial_instance = instance_i2c; + as5600l->abs_pos = 0; + as5600l->curr_angle = 0; + as5600l->last_angle = 0; + as5600l->start_pos = 0; + + + as5600l->start_pos = as560xReadAngle(as5600l); + as5600l->abs_pos = 0 - as5600l->start_pos; +} + +int update_pos(AS5600L* as5600l){ + // sensorData(); + as5600l->curr_angle = as560xReadAngle(as5600l); + + if(as5600l->last_angle > ENCODER_RESOLUTION/2 & as5600l->curr_angle < (as5600l->last_angle - ENCODER_RESOLUTION/2)){ + as5600l->abs_pos = as5600l->abs_pos + ENCODER_RESOLUTION - as5600l->last_angle + as5600l->curr_angle; + }else if(as5600l->curr_angle > ENCODER_RESOLUTION/2 & as5600l->last_angle < (as5600l->curr_angle - ENCODER_RESOLUTION/2) ){ + as5600l->abs_pos = as5600l->abs_pos -ENCODER_RESOLUTION - as5600l->last_angle + as5600l->curr_angle; + }else{ + as5600l->abs_pos = as5600l->abs_pos - as5600l->last_angle + as5600l->curr_angle; + } + + as5600l->last_angle = as5600l->curr_angle; + return as5600l->abs_pos; +} + +int __bswap16(int value) { + return (value >> 8) | (value << 8); +} + +void i2cError() { + printf("I2C Error\n"); +} + +int as560xReadReg(AS5600L* as5600l,int addr, bool wide, int mask) { + int buf; + int result = i2c_write_timeout_us(as5600l->serial_instance.I2C_PORT, AS5600L_ADDRESS, (uint8_t *)&addr, 1, true, I2C_TIMEOUT_US); + if (result <= 0) { + i2cError(); + } + result = i2c_read_timeout_us(as5600l->serial_instance.I2C_PORT, AS5600L_ADDRESS, (uint8_t *)&buf, (wide ? 2 : 1), false, I2C_TIMEOUT_US); + if (result <= 0) { + i2cError(); + } + if (wide) { + return __bswap16(buf) & mask; + } else { + return buf & mask; + } +} + +void AS560x_print_reg16(AS5600L* as5600l,const char *formatStr, int addr, int mask) { + int result = as560xReadReg(as5600l,addr, true, mask); + printf(formatStr, result & mask); +} + +void AS560x_print_reg8(AS5600L* as5600l,const char *formatStr, int addr, uint8_t mask) { + uint8_t result = (uint8_t)as560xReadReg(as5600l,addr, false, mask); + printf(formatStr, result & mask); +} + + +int as560xReadAngle(AS5600L* as5600l) { + return as560xReadReg(as5600l,AS560x_RAW_ANGLE_REG, true, 0xFFF) ; +} + +uint8_t as560xGetStatus(AS5600L* as5600l) { + return (uint8_t)as560xReadReg(as5600l,AS560x_STATUS_REG, false, 0x38); +} + +void sensorData(AS5600L* as5600l) { + AS560x_print_reg8(as5600l,"Status: %02x; ", AS560x_STATUS_REG, 0x38); + AS560x_print_reg8(as5600l,"AGC: %3x; ", 0x1a, 0xff); + AS560x_print_reg16(as5600l,"Angle: %d\n\r", AS560x_RAW_ANGLE_REG, 0xFFF); +} + + diff --git a/Motor_encod/AS5600L.h b/Motor_encod/AS5600L.h new file mode 100644 index 0000000..ab6833e --- /dev/null +++ b/Motor_encod/AS5600L.h @@ -0,0 +1,47 @@ +#ifndef AS5600L_H +#define AS5600L_H + +#include "hardware/i2c.h" +#include "pico/stdlib.h" +#include "pico/time.h" +#include +#include +#include + +#define I2C_TIMEOUT_US (100000) + +#define AS560x_STATUS_REG (0x0B) +#define AS560x_RAW_ANGLE_REG (0x0C) +#define AS5600L_ADDRESS 0x40 +#define ENCODER_RESOLUTION 4096 + + + +typedef struct { + i2c_inst_t *I2C_PORT; + int FREQUENCE; + int I2C_SDA_PIN; + int I2C_SCL_PIN; +} AS5600L_I2C; + +typedef struct { + AS5600L_I2C serial_instance; + int last_angle; + int curr_angle ; + int abs_pos ; + int start_pos; +} AS5600L; + + +void as560x_init(AS5600L* as5600l, i2c_inst_t *I2C_ID, int frq , int sda, int scl); +int update_pos(AS5600L* as5600l); +int __bswap16(int value); +void i2cError(); +int as560xReadReg(AS5600L* as5600l,int addr, bool wide, int mask); +void AS560x_print_reg16(AS5600L* as5600l,const char *formatStr, int addr, int mask); +void AS560x_print_reg8(AS5600L* as5600l,const char *formatStr, int addr, uint8_t mask); +int as560xReadAngle(AS5600L* as5600l); +uint8_t as560xGetStatus(AS5600L* as5600l); +void sensorData(AS5600L* as5600l); + +#endif /* AS5600L_H */ diff --git a/Motor_encod/CMakeLists.txt b/Motor_encod/CMakeLists.txt new file mode 100644 index 0000000..b94a734 --- /dev/null +++ b/Motor_encod/CMakeLists.txt @@ -0,0 +1,34 @@ +cmake_minimum_required(VERSION 3.12) + +set(PROJECT_NAME "Motor_test") +set(PICO_SDK_PATH "E:/Beyon_Motion/pico-sdk") +set(PICO_TOOLCHAIN_PATH "C:/Users/spide/scoop/apps/gcc-arm-none-eabi/current/bin") +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +include(${PICO_SDK_PATH}/external/pico_sdk_import.cmake) + +project(${PROJECT_NAME} C CXX ASM) # Ajout de CXX ici + +pico_sdk_init() + +add_executable(${PROJECT_NAME} + main.c + Tmc2209.c + Tmc_uart.c + AS5600L.c + AS5600L.h +) + + +target_link_libraries(${PROJECT_NAME} + pico_stdlib + hardware_i2c + hardware_uart + hardware_dma +) + +pico_enable_stdio_usb(${PROJECT_NAME} 1) +pico_enable_stdio_uart(${PROJECT_NAME} 0) + +pico_add_extra_outputs(${PROJECT_NAME}) diff --git a/Motor_encod/Tmc2209.c b/Motor_encod/Tmc2209.c new file mode 100644 index 0000000..73aee0a --- /dev/null +++ b/Motor_encod/Tmc2209.c @@ -0,0 +1,627 @@ +// Tmc2209.c +#include "Tmc2209.h" + + +#define portMAX_DELAY 10 +#define UART_BUFFER_SIZE 64 // Taille du tampon UART, à ajuster selon vos besoins + +// Adresses des registres +#define GCONF 0x00 +#define GSTAT 0x01 +#define IFCNT 0x02 +#define IOIN 0x06 +#define IHOLD_IRUN 0x10 +#define TSTEP 0x12 +#define TCOOLTHRS 0x14 +#define SGTHRS 0x40 +#define SG_RESULT 0x41 +#define MSCNT 0x6A +#define CHOPCONF 0x6C +#define DRVSTATUS 0x6F +#define VACTUAL 0x22 + +// Bits associés à GCONF +#define I_SCALE_ANALOG (1 << 0) +#define INTERNAL_RSENSE (1 << 1) +#define EN_SPREADCYCLE (1 << 2) +#define SHAFT (1 << 3) +#define INDEX_OTPW (1 << 4) +#define INDEX_STEP (1 << 5) +#define MSTEP_REG_SELECT (1 << 7) + +// Bits associés à GSTAT +#define RESET (1 << 0) +#define DRV_ERR (1 << 1) +#define UV_CP (1 << 2) + +// Bits associés à CHOPCONF +#define VSENSE (1 << 17) +#define MSRES0 (1 << 24) +#define MSRES1 (1 << 25) +#define MSRES2 (1 << 26) +#define MSRES3 (1 << 27) +#define INTPOL (1 << 28) + +// Bits associés à IOIN +#define IO_ENN (1 << 0) +#define IO_STEP (1 << 7) +#define IO_SPREAD (1 << 8) +#define IO_DIR (1 << 9) + +// Bits associés à DRVSTATUS +#define STST (1U << 31) +#define STEALTH (1U << 30) +#define CS_ACTUAL (31U << 16) +#define T157 (1 << 11) +#define T150 (1 << 10) +#define T143 (1 << 9) +#define T120 (1 << 8) +#define OLB (1 << 7) +#define OLA (1 << 6) +#define S2VSB (1 << 5) +#define S2VSA (1 << 4) +#define S2GB (1 << 3) +#define S2GA (1 << 2) +#define OT (1 << 1) +#define OTPW (1 << 0) + +// Bits associés à IHOLD_IRUN +#define IHOLD (31 << 0) +#define IRUN (31 << 8) +#define IHOLDDELAY (15 << 16) + +// Bits associés à SGTHRS +#define SGTHRS_VAL (255 << 0) + +// Autres constantes +#define MRES_256 0 +#define MRES_128 1 +#define MRES_64 2 +#define MRES_32 3 +#define MRES_16 4 +#define MRES_8 5 +#define MRES_4 6 +#define MRES_2 7 +#define MRES_1 8 + + + + +void TMC2209_Init(TMC2209* tmc2209,TMC_UART* serial_instance) { + + tmc2209->serial_instance = serial_instance; + + tmc2209->mtr_id = 0; + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = 0; + tmc2209->rFrame[2] = 0; + tmc2209->rFrame[3] = 0; + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = 0; + tmc2209->wFrame[2] = 0; + tmc2209->wFrame[3] = 0; + tmc2209->wFrame[4] = 0; + tmc2209->wFrame[5] = 0; + tmc2209->wFrame[6] = 0; + tmc2209->wFrame[7] = 0; + tmc2209->result[0] = 0; + tmc2209->result[1] = 0; + tmc2209->result[2] = 0; + tmc2209->result[3] = 0; + + // return true; +} + +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value) { + uint8_t crc = initial_value; + + size_t i; + int j; + for (i = 0; i < length; i++) { + uint8_t byte = datagram[i]; + for (j = 0; j < 8; j++) { + if ((crc >> 7) ^ (byte & 0x01)) { + crc = ((crc << 1) ^ 0x07) & 0xFF; + } else { + crc = (crc << 1) & 0xFF; + } + byte >>= 1; + } + } + return crc; +} + + + +uint64_t *read_reg(TMC2209* tmc2209, int reg) { + + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = tmc2209->mtr_id; + tmc2209->rFrame[2] = reg; + tmc2209->rFrame[3] = compute_crc8_atm(tmc2209->rFrame, 3, 0); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[3]); + + uint64_t temp_result[12] = {0x00}; + + int i = 0; + uint32_t start_time = time_us_32(); // Temps de départ en microsecondes + while (time_us_32() - start_time < 2000 && i < 12) { // Lire pendant 2 ms + if (uart_is_readable(tmc2209->serial_instance->UART_ID)) { + uint64_t tempchar = uart_getc(tmc2209->serial_instance->UART_ID); + temp_result[i] = tempchar; + i++; + } + } + + if (temp_result[11] == 0 ){ + tmc2209->result[0] = temp_result[6]; + tmc2209->result[1] = temp_result[7]; + tmc2209->result[2] = temp_result[8]; + tmc2209->result[3] = temp_result[9]; + }else{ + tmc2209->result[0] = temp_result[7]; + tmc2209->result[1] = temp_result[8]; + tmc2209->result[2] = temp_result[9]; + tmc2209->result[3] = temp_result[10]; + } + + sleep_ms(3); + return tmc2209->result; +} + + +uint32_t read_int(TMC2209* tmc2209, int reg) { + uint8_t data[4]; // Array to store the 4-byte response + + for (int tries = 0; tries < 10; tries++) { + uint64_t* rtn = read_reg(tmc2209, reg); + + if (rtn == NULL) { + printf("TMC2209: read_reg failed to return data\n"); + continue; + } + + if (sizeof(*rtn) >= sizeof(data)) { + for (int i = 0; i < sizeof(data); i++) { + data[i] = (uint8_t)(*rtn >> (8 * (sizeof(*rtn) - i - 1))); + } + } else { + printf("TMC2209: expected at least 4 bytes, got %zu Bytes\n", sizeof(*rtn)); + continue; + } + + uint32_t result_int = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; + + if (!(result_int & 0x80000000)) { + return result_int; + } else { + printf("TMC2209: error in register response: 0x%08X\n", result_int); + } + } + + printf("TMC2209: failed to read register after 10 tries\n"); + printf("TMC2209: is Stepper Powersupply switched on?\n"); + exit(EXIT_FAILURE); +} + + +bool write_reg(TMC2209* tmc2209, int reg, int val) { + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = tmc2209->mtr_id; + tmc2209->wFrame[2] = reg | 0x80; + tmc2209->wFrame[3] = (val >> 24) & 0xFF; + tmc2209->wFrame[4] = (val >> 16) & 0xFF; + tmc2209->wFrame[5] = (val >> 8) & 0xFF; + tmc2209->wFrame[6] = val & 0xFF; + tmc2209->wFrame[7] = compute_crc8_atm(tmc2209->wFrame, sizeof(tmc2209->wFrame) - 1, 0); + // printf("val : %d\n",val); + // printf("Frames :"); + // for (int i = 0; i < 8; i++) { + // printf("%d ", tmc2209->wFrame[i]); + // } + // printf("\n"); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[3]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[4]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[5]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[6]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[7]); + + sleep_ms(3); + + return true; +} + +bool write_reg_check(TMC2209* tmc2209, int reg, int val) { + + int ifcnt12 = read_int(tmc2209, IFCNT); + unsigned int ifcnt1 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + write_reg(tmc2209, reg, val); + + int ifcnt22 = read_int(tmc2209, IFCNT); + unsigned int ifcnt2 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (ifcnt1 >= ifcnt2) { + printf("TMC2209: writing not successful!\n"); + printf("reg: %X val: %d\n", reg, val); + printf("ifcnt: %d %d\n", ifcnt1, ifcnt2); + return false; + } + + return true; +} + +void TMC2209_destroy(TMC2209* tmc2209) { + // free(tmc2209); +} + + + + + +void driver_status(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: DRIVER STATUS:\n"); + read_int(tmc2209, DRVSTATUS); + unsigned int drvstatus = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (drvstatus & STST) { + printf("TMC2209: Info: motor is standing still\n"); + } else { + printf("TMC2209: Info: motor is running\n"); + } + + if (drvstatus & STEALTH) { + printf("TMC2209: Info: motor is running on StealthChop\n"); + } else { + printf("TMC2209: Info: motor is running on SpreadCycle\n"); + } + + int cs_act = drvstatus & CS_ACTUAL; + cs_act >>= 16; + printf("TMC2209: CS actual: %d\n", cs_act); + + if (drvstatus & OLB) { + printf("TMC2209: Warning: Open load detected on phase B\n"); + } + if (drvstatus & OLA) { + printf("TMC2209: Warning: Open load detected on phase A\n"); + } + if (drvstatus & S2VSB) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase B. The driver becomes disabled\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase A. The driver becomes disabled\n"); + } + if (drvstatus & S2GB) { + printf("TMC2209: Error: Short to GND detected on phase B. The driver becomes disabled.\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short to GND detected on phase A. The driver becomes disabled.\n"); + } + if (drvstatus & OT) { + printf("TMC2209: Error: Driver Overheating!\n"); + } + if (drvstatus & OTPW) { + printf("TMC2209: Warning: Driver Overheating Prewarning!\n"); + } + printf("end"); + + +} + +// Fonction general_config +void general_config(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL CONFIG\n"); + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (gconf & I_SCALE_ANALOG) { + printf("TMC2209: Driver is using voltage supplied to VREF as current reference\n"); + } else { + printf("TMC2209: Driver is using internal reference derived from 5VOUT\n"); + } + + if (gconf & INTERNAL_RSENSE) { + printf("TMC2209: Internal sense resistors. Use current supplied into VREF as reference.\n"); + printf("TMC2209: VREF pin internally is driven to GND in this mode.\n"); + printf("TMC2209: This will most likely destroy your driver!!!\n"); + exit(EXIT_FAILURE); + } else { + printf("TMC2209: Operation with external sense resistors\n"); + } + + if (gconf & EN_SPREADCYCLE) { + printf("TMC2209: SpreadCycle mode enabled\n"); + } else { + printf("TMC2209: StealthChop PWM mode enabled\n"); + } + + if (gconf & SHAFT) { + printf("TMC2209: Inverse motor direction\n"); + } else { + printf("TMC2209: normal motor direction\n"); + } + + if (gconf & INDEX_OTPW) { + printf("TMC2209: INDEX pin outputs overtemperature prewarning flag\n"); + } else { + printf("TMC2209: INDEX shows the first microstep position of sequencer\n"); + } + + if (gconf & INDEX_STEP) { + printf("TMC2209: INDEX output shows step pulses from internal pulse generator\n"); + } else { + printf("TMC2209: INDEX output as selected by index_otpw\n"); + } +} + +// Fonction general_stat +void general_stat(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL STAT\n"); + read_int(tmc2209, GSTAT); + unsigned int gstat = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (gstat & RESET) { + printf("TMC2209: The Driver has been reset since the last read access to GSTAT\n"); + } + + if (gstat & DRV_ERR) { + printf("TMC2209: The driver has been shut down due to overtemperature or short circuit detection since the last read access\n"); + } + + if (gstat & UV_CP) { + printf("TMC2209: Undervoltage on the charge pump. The driver is disabled in this case\n"); + } +} + +bool set_vactual(TMC2209* tmc2209, int value) { + return write_reg_check(tmc2209, VACTUAL, value); +} + + + +unsigned int set_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value | bit; + return temp; +} + + +// Fonction pour définir un bit spécifique à 0 +unsigned int clear_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value & ~(1 << bit); + return temp; +} + + +void clear_general_stat(TMC2209* tmc2209) { + read_int(tmc2209, GSTAT); + unsigned int gstat= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + gstat = set_bit(gstat, RESET); + gstat = set_bit(gstat, DRV_ERR); + write_reg_check(tmc2209, GSTAT, gstat); +} + + + +void set_voltage_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); // Lire la valeur actuelle du registre CHOPCONF + unsigned int chopconf= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf |= VSENSE; + } else { + chopconf &= ~VSENSE; + } + + // Écrire la nouvelle valeur dans le registre CHOPCONF + if (!write_reg_check(tmc2209, CHOPCONF, chopconf)) { + printf("Erreur lors de l'écriture de la valeur dans le registre CHOPCONF\n"); + } +} + +bool get_voltage_sense(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + return (chopconf & VSENSE) != 0; +} + + +void set_current_flow(TMC2209* tmc2209,double run_current, double hold_current_multiplier, int hold_current_delay, double Vref) { + double CS_IRun = 0.0; + double Rsense = 0.11; + double Vfs = 0.0; + Vref = 5.4; + hold_current_multiplier = 0.5; + hold_current_delay = 10; + run_current = 1800; + + int voltage_sense = get_voltage_sense(tmc2209); + + if (voltage_sense) { + Vfs = 0.180 * Vref / 2.5; + } else { + Vfs = 0.325 * Vref / 2.5; + } + + CS_IRun = 32.0 * 1.41421 * run_current / 1000.0 * (Rsense + 0.02) / Vfs - 1; + CS_IRun = fmin(CS_IRun, 31); + CS_IRun = fmax(CS_IRun, 0); + double CS_IHold = hold_current_multiplier * CS_IRun; + CS_IRun = round(CS_IRun); + CS_IHold = round(CS_IHold); + + // printf("CS_IHold_rounded %.3f, CS_IRun_rounded %.3f, hold_current_delay %d\n" , CS_IHold, CS_IRun, hold_current_delay); + + set_irun_ihold(tmc2209,CS_IHold, CS_IRun, hold_current_delay); +} + + +void set_iscale_analog(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, I_SCALE_ANALOG); + } else { + + gconf = clear_bit(gconf, I_SCALE_ANALOG); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +void set_interpolation(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf = set_bit(chopconf, INTPOL); + } else { + chopconf = clear_bit(chopconf, INTPOL); + } + + + printf("chopconf : %d\n",chopconf); + + write_reg_check(tmc2209, CHOPCONF, chopconf); +} + +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, INTERNAL_RSENSE); + } else { + + gconf = clear_bit(gconf, INTERNAL_RSENSE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +void set_spread_cycle(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, EN_SPREADCYCLE); + } else { + + gconf = clear_bit(gconf, EN_SPREADCYCLE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +void set_microstepping_resolution(TMC2209* tmc2209, int msres) { + + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + // printf("chopconf %d \n",chopconf); + + int msresdezimal = 8 - (int)log2(msres); + chopconf &= 4043309055; + chopconf |= msresdezimal << 24; + write_reg_check(tmc2209, CHOPCONF, chopconf); + set_microstep_resolution_regselect(tmc2209, true); +} + +int get_microstepping_resolution(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + + // printf("chopconf : %d\n", chopconf); + int msresdezimal = chopconf & (MSRES0 | MSRES1 | MSRES2 | MSRES3); + msresdezimal = msresdezimal >> 24; + msresdezimal = 8 - msresdezimal; + int micro_stepping_resolution = (int)pow(2, msresdezimal); + + return micro_stepping_resolution; +} + +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + gconf = set_bit(gconf, MSTEP_REG_SELECT); + } else { + gconf = clear_bit(gconf, MSTEP_REG_SELECT); + } + // printf("gconf : %d \n",gconf); + + write_reg_check(tmc2209, GCONF, gconf); +} + + +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay) { + // Convertir les valeurs doubles en entiers + int ihold_irun = 0; + int ih = (int)IHold; + int ir = (int)IRun; + + ihold_irun |= ih << 0; + printf("ihold_irun1 : %d\n",ihold_irun); + + ihold_irun |= ir << 8; + printf("ihold_irun2 : %d\n",ihold_irun); + + ihold_irun |= IHoldDelay << 16; + + printf("ihold_irun3 : %d\n",ihold_irun); + + write_reg_check(tmc2209, IHOLD_IRUN, ihold_irun); +} + diff --git a/Motor_encod/Tmc2209.h b/Motor_encod/Tmc2209.h new file mode 100644 index 0000000..2e9cd7a --- /dev/null +++ b/Motor_encod/Tmc2209.h @@ -0,0 +1,47 @@ +// Tmc2209.h +#ifndef TMC2209_H +#define TMC2209_H + +#include "pico/stdlib.h" +#include "Tmc_uart.h" +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + TMC_UART* serial_instance; + int mtr_id; + uint8_t rFrame[4]; + uint8_t wFrame[8]; + uint64_t result[4]; +} TMC2209; + +void TMC2209_Init(TMC2209* tmc2209,TMC_UART* serial_instance); //ok +void TMC2209_Destroy(TMC2209* tmc2209); //idk +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value); //ok +uint64_t* read_reg(TMC2209* tmc2209, int reg) ; //ok +uint32_t read_int(TMC2209* tmc2209, int reg); //ok +bool write_reg(TMC2209* tmc2209, int reg, int val); //ok +bool write_reg_check(TMC2209* tmc2209, int reg, int val) ; //ok +void general_stat(TMC2209* tmc2209) ; //idk +void general_config(TMC2209* tmc2209); //idk +void driver_status(TMC2209* tmc2209); //idk +bool set_vactual(TMC2209* tmc2209, int value) ; //ok + +void set_voltage_sense(TMC2209* tmc2209, bool enabled); //ok +bool get_voltage_sense(TMC2209* tmc2209); //ok +void set_current_flow(TMC2209* tmc2209, double run_current, double hold_current_multiplier, int hold_current_delay, double Vref);//averif +void set_iscale_analog(TMC2209* tmc2209, bool enabled); //ok +void set_interpolation(TMC2209* tmc2209, bool enabled); +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled); +void set_spread_cycle(TMC2209* tmc2209, bool enabled); +void set_microstepping_resolution(TMC2209* tmc2209, int msres); //ok +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled); //ok +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay); //ok +void clear_general_stat(TMC2209* tmc2209); //ok +int get_microstepping_resolution(TMC2209* tmc2209); //ok +#endif diff --git a/Motor_encod/Tmc_uart.c b/Motor_encod/Tmc_uart.c new file mode 100644 index 0000000..6b1f142 --- /dev/null +++ b/Motor_encod/Tmc_uart.c @@ -0,0 +1,36 @@ +// TMC_UART.c +#include "TMC_uart.h" + + +#define DEFAULT_UART_ID uart1 +#define DEFAULT_BAUD_RATE 115200 +#define DEFAULT_MOTOR_TX_PIN 4 +#define DEFAULT_MOTOR_RX_PIN 5 + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN) { + + if (BAUD_RATE == -1) BAUD_RATE = DEFAULT_BAUD_RATE; + if (MOTOR_TX_PIN == -1) MOTOR_TX_PIN = DEFAULT_MOTOR_TX_PIN; + if (MOTOR_RX_PIN == -1) MOTOR_RX_PIN = DEFAULT_MOTOR_RX_PIN; + + uart_init(UART_ID, BAUD_RATE); + gpio_set_function(MOTOR_TX_PIN, GPIO_FUNC_UART); + gpio_set_function(MOTOR_RX_PIN, GPIO_FUNC_UART); + uart_set_hw_flow(UART_ID, false, false); + uart_set_format(UART_ID, 8, 1, UART_PARITY_NONE); + uart_set_fifo_enabled(UART_ID, false); + + tmc_uart->UART_ID = UART_ID; + tmc_uart->BAUD_RATE = BAUD_RATE; + tmc_uart->MOTOR_TX_PIN = MOTOR_TX_PIN; + tmc_uart->MOTOR_RX_PIN = MOTOR_RX_PIN; + return tmc_uart; +} + +void TMC_UART_Write(TMC_UART* tmc_uart, int data) { + uart_putc(tmc_uart->UART_ID, data); +} + +void TMC_UART_Destroy(TMC_UART* tmc_uart) { + // Aucune opération nécessaire +} diff --git a/Motor_encod/Tmc_uart.h b/Motor_encod/Tmc_uart.h new file mode 100644 index 0000000..b7d2d5d --- /dev/null +++ b/Motor_encod/Tmc_uart.h @@ -0,0 +1,18 @@ +// TMC_UART.h +#ifndef TMC_UART_H +#define TMC_UART_H + +#include +#include "pico/stdlib.h" + +typedef struct { + uart_inst_t *UART_ID; + int BAUD_RATE; + int MOTOR_TX_PIN; + int MOTOR_RX_PIN; +} TMC_UART; + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN); +void tmc_Uart_Destroy(TMC_UART* TMC_UART); + +#endif diff --git a/Motor_encod/main.c b/Motor_encod/main.c new file mode 100644 index 0000000..7933d5a --- /dev/null +++ b/Motor_encod/main.c @@ -0,0 +1,148 @@ + + +#include +#include "pico/stdlib.h" +#include "pico/time.h" + +#include "hardware/uart.h" +#include "hardware/irq.h" // Inclure le fichier d'en-tête pour les interruptions +#include "hardware/gpio.h" +#include "hardware/i2c.h" + +#include "Tmc_uart.h" +#include "Tmc2209.h" + +#include "AS5600L.h" + +#include "unistd.h" + +#define I2C_PORT i2c0 +#define I2C_SDA_PIN 8 +#define I2C_SCL_PIN 9 + + +int main() { + stdio_init_all(); + + TMC_UART uart_instance; + TMC2209 Tmc2209; + AS5600L as5600l; + + // Initialisation de l'UART avec les paramètres par défaut + + tmc_Uart_Init(&uart_instance, uart1, -1, -1, -1); + + TMC2209_Init(&Tmc2209,&uart_instance); + as560x_init(&as5600l,I2C_PORT,100000,I2C_SDA_PIN,I2C_SCL_PIN); + + int abs = 0; + abs = update_pos; + sleep_ms(4000); + + + + // driver_status(&uart_instance); + // general_config(&uart_instance); + + // clear_general_stat(&uart_instance); + printf("UART initialisé avec succès\n"); + int32_t resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution begin : %ld\n", resolution); + sleep_ms(10); + set_microstepping_resolution(&Tmc2209,256); + sleep_ms(10); + resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution after new go to 1/256: %ld\n", resolution); + sleep_ms(10); + // set_microstepping_resolution(&Tmc2209,16); + // sleep_ms(10); + // resolution = get_microstepping_resolution(&Tmc2209); + // printf("Microstepping resolution after renew go to 1/16: %ld\n", resolution); + // printf(get_microstepping_resolution(&Tmc2209)); + // clear_general_stat(&Tmc2209); + // sleep_ms(2000); + // set_voltage_sense(&Tmc2209, false); + // sleep_ms(2000); + + // set_current_flow(&Tmc2209, 1800, 0.5, 10, 5.4); + + // sleep_ms(2000); + // set_iscale_analog(&Tmc2209, false); + // sleep_ms(2000); + // set_interpolation(&Tmc2209, true); + // sleep_ms(2000); + // set_internal_resistor_sense(&Tmc2209, false); + // sleep_ms(2000); + // set_spread_cycle(&Tmc2209, true); + // sleep_ms(2000); + // set_microstepping_resolution(&Tmc2209,256); + // sleep_ms(2000); + // set_microstep_resolution_regselect(&Tmc2209, true); + // int32_t resolution = get_microstepping_resolution(&Tmc2209); + // printf("Microstepping resolution begin : %ld\n", resolution); + const uint LED_PIN = 7; + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + gpio_put(LED_PIN, 0); + + sleep_ms(1000); + int max = 1600; + for (int i = 100; i <= max; i += 100) { + set_vactual(&Tmc2209,i*256); + abs = update_pos(&as5600l); + printf("Position absolue : %d\n",abs); + } + + uint32_t start_time = time_us_32(); + uint32_t current_time = start_time; + + while (current_time - start_time < 10000000) { // 10 secondes en microsecondes + abs = update_pos(&as5600l); + printf("Position absolue : %d\n", abs); + + // Mise à jour du temps actuel + current_time = time_us_32(); + } + + for (int i = max; i >= 100; i -= 100) { + set_vactual(&Tmc2209,i*256); + abs = update_pos(&as5600l); + printf("Position absolue : %d\n",abs); + } + set_vactual(&Tmc2209,0); + + sleep_ms(10000); + gpio_put(LED_PIN, 1); + // int32_t resolution; + // general_config(&Tmc2209); + + // while (true) { + + // } + + + // for (int i = 1000; i <= 200000; i += 10) { + // set_vactual(&Tmc2209, i); + // sleep_ms(2); + // } + + // for (int i = 20000; i >= 10000; i -= 10) { + // set_vactual(&Tmc2209, i); + // sleep_ms(2); + // } + + // sleep_ms(1000); + // printf("end\n"); + // // read_reg(&Tmc2209,0x6C); + // printf(driver_status(&Tmc2209)); + // sleep_ms(1000); + + // // char data[] = "Hello, UART!\n"; + // // for (int i = 0; data[i] != '\0'; ++i) { + // // TMC_UART_Write(&Tmc2209, data[i]); + // // } + // } + + return 0; +} + diff --git a/Stepper-Locking-System_firmware b/Stepper-Locking-System_firmware new file mode 160000 index 0000000..cada33b --- /dev/null +++ b/Stepper-Locking-System_firmware @@ -0,0 +1 @@ +Subproject commit cada33b0b8c79398f86fb12b50bf9a25eda710d3 diff --git a/TMC-API b/TMC-API new file mode 160000 index 0000000..8e53c85 --- /dev/null +++ b/TMC-API @@ -0,0 +1 @@ +Subproject commit 8e53c85679a7ed8b047c77e97282e7f9d8e62fcd diff --git a/TMC-EvalSystem b/TMC-EvalSystem new file mode 160000 index 0000000..d7f9986 --- /dev/null +++ b/TMC-EvalSystem @@ -0,0 +1 @@ +Subproject commit d7f9986b9a00dc7ccbdab1e5f40b40cee22e3f91 diff --git a/TMC2209/CMakeLists.txt b/TMC2209/CMakeLists.txt new file mode 100644 index 0000000..ddc6b17 --- /dev/null +++ b/TMC2209/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.12) + +set(PROJECT_NAME "Uart_TMC2209_test") +set(PICO_SDK_PATH "E:/Beyon_Motion/pico-sdk") +set(PICO_TOOLCHAIN_PATH "C:/Users/spide/scoop/apps/gcc-arm-none-eabi/current/bin") +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +include(${PICO_SDK_PATH}/external/pico_sdk_import.cmake) + +project(${PROJECT_NAME} C CXX ASM) # Ajout de CXX ici + +pico_sdk_init() + +add_executable(${PROJECT_NAME} + main.c + Tmc2209.c + Tmc_uart.c +) + + +target_link_libraries(${PROJECT_NAME} + pico_stdlib + hardware_i2c + hardware_uart + hardware_dma + # TMC2209 +) + +pico_enable_stdio_usb(${PROJECT_NAME} 1) +pico_enable_stdio_uart(${PROJECT_NAME} 0) + +pico_add_extra_outputs(${PROJECT_NAME}) diff --git a/TMC2209/Tmc2209.c b/TMC2209/Tmc2209.c new file mode 100644 index 0000000..93eb608 --- /dev/null +++ b/TMC2209/Tmc2209.c @@ -0,0 +1,835 @@ +// Tmc2209.c +#include "Tmc2209.h" + + +#define portMAX_DELAY 10 +#define UART_BUFFER_SIZE 64 // Taille du tampon UART, à ajuster selon vos besoins + +// Adresses des registres +#define GCONF 0x00 +#define GSTAT 0x01 +#define IFCNT 0x02 +#define IOIN 0x06 +#define IHOLD_IRUN 0x10 +#define TSTEP 0x12 +#define TCOOLTHRS 0x14 +#define SGTHRS 0x40 +#define SG_RESULT 0x41 +#define MSCNT 0x6A +#define CHOPCONF 0x6C +#define DRVSTATUS 0x6F +#define VACTUAL 0x22 + +// Bits associés à GCONF +#define I_SCALE_ANALOG (1 << 0) +#define INTERNAL_RSENSE (1 << 1) +#define EN_SPREADCYCLE (1 << 2) +#define SHAFT (1 << 3) +#define INDEX_OTPW (1 << 4) +#define INDEX_STEP (1 << 5) +#define MSTEP_REG_SELECT (1 << 7) + +// Bits associés à GSTAT +#define RESET (1 << 0) +#define DRV_ERR (1 << 1) +#define UV_CP (1 << 2) + +// Bits associés à CHOPCONF +#define VSENSE (1 << 17) +#define MSRES0 (1 << 24) +#define MSRES1 (1 << 25) +#define MSRES2 (1 << 26) +#define MSRES3 (1 << 27) +#define INTPOL (1 << 28) + +// Bits associés à IOIN +#define IO_ENN (1 << 0) +#define IO_STEP (1 << 7) +#define IO_SPREAD (1 << 8) +#define IO_DIR (1 << 9) + +// Bits associés à DRVSTATUS +#define STST (1U << 31) +#define STEALTH (1U << 30) +#define CS_ACTUAL (31U << 16) +#define T157 (1 << 11) +#define T150 (1 << 10) +#define T143 (1 << 9) +#define T120 (1 << 8) +#define OLB (1 << 7) +#define OLA (1 << 6) +#define S2VSB (1 << 5) +#define S2VSA (1 << 4) +#define S2GB (1 << 3) +#define S2GA (1 << 2) +#define OT (1 << 1) +#define OTPW (1 << 0) + +// Bits associés à IHOLD_IRUN +#define IHOLD (31 << 0) +#define IRUN (31 << 8) +#define IHOLDDELAY (15 << 16) + +// Bits associés à SGTHRS +#define SGTHRS_VAL (255 << 0) + +// Autres constantes +#define MRES_256 0 +#define MRES_128 1 +#define MRES_64 2 +#define MRES_32 3 +#define MRES_16 4 +#define MRES_8 5 +#define MRES_4 6 +#define MRES_2 7 +#define MRES_1 8 + + + + +void TMC2209_Init(TMC2209* tmc2209,TMC_UART* serial_instance) { + + tmc2209->serial_instance = serial_instance; + tmc2209->mtr_id = 0x00; + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = 0x00; + tmc2209->rFrame[2] = 0x00; + tmc2209->rFrame[3] = 0x00; + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = 0x00; + tmc2209->wFrame[2] = 0x00; + tmc2209->wFrame[3] = 0x00; + tmc2209->wFrame[4] = 0x00; + tmc2209->wFrame[5] = 0x00; + tmc2209->wFrame[6] = 0x00; + tmc2209->wFrame[7] = 0x00; + tmc2209->result[0] = 0x00; + tmc2209->result[1] = 0x00; + tmc2209->result[2] = 0x00; + tmc2209->result[3] = 0x00; + + // return true; +} + +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value) { + uint8_t crc = initial_value; + + size_t i; + int j; + for (i = 0; i < length; i++) { + uint8_t byte = datagram[i]; + for (j = 0; j < 8; j++) { + if ((crc >> 7) ^ (byte & 0x01)) { + crc = ((crc << 1) ^ 0x07) & 0xFF; + } else { + crc = (crc << 1) & 0xFF; + } + byte >>= 1; + } + } + return crc; +} + + + +uint64_t *read_reg(TMC2209* tmc2209, int reg) { + + TMC_uart_read_datagram_t datagram; + TMC_uart_write_datagram_t *res; + + + + tmc2209->rFrame[0] = 0x55; + tmc2209->rFrame[1] = tmc2209->mtr_id; + tmc2209->rFrame[2] = reg; + tmc2209->rFrame[3] = compute_crc8_atm(tmc2209->rFrame, 3, 0); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->rFrame[3]); + + uint64_t temp_result[12] = {0x00}; + + int i = 0; + uint32_t start_time = time_us_32(); // Temps de départ en microsecondes + while (time_us_32() - start_time < 2000 && i < 12) { // Lire pendant 2 ms + if (uart_is_readable(tmc2209->serial_instance->UART_ID)) { + uint64_t tempchar = uart_getc(tmc2209->serial_instance->UART_ID); + temp_result[i] = tempchar; + i++; + } + } + + if (temp_result[11] == 0 ){ + tmc2209->result[0] = temp_result[6]; + tmc2209->result[1] = temp_result[7]; + tmc2209->result[2] = temp_result[8]; + tmc2209->result[3] = temp_result[9]; + }else{ + tmc2209->result[0] = temp_result[7]; + tmc2209->result[1] = temp_result[8]; + tmc2209->result[2] = temp_result[9]; + tmc2209->result[3] = temp_result[10]; + } + + sleep_ms(3); + return tmc2209->result; +} + + +uint32_t read_int(TMC2209* tmc2209, int reg) { + uint8_t data[4]; // Array to store the 4-byte response + + for (int tries = 0; tries < 10; tries++) { + uint64_t* rtn = read_reg(tmc2209, reg); + + if (rtn == NULL) { + printf("TMC2209: read_reg failed to return data\n"); + continue; + } + + if (sizeof(*rtn) >= sizeof(data)) { + for (int i = 0; i < sizeof(data); i++) { + data[i] = (uint8_t)(*rtn >> (8 * (sizeof(*rtn) - i - 1))); + } + } else { + printf("TMC2209: expected at least 4 bytes, got %zu Bytes\n", sizeof(*rtn)); + continue; + } + + uint32_t result_int = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; + + if (!(result_int & 0x80000000)) { + return result_int; + } else { + printf("TMC2209: error in register response: 0x%08X\n", result_int); + } + } + + printf("TMC2209: failed to read register after 10 tries\n"); + printf("TMC2209: is Stepper Powersupply switched on?\n"); + exit(EXIT_FAILURE); +} + + +bool write_reg(TMC2209* tmc2209, int reg, int val) { + tmc2209->wFrame[0] = 0x55; + tmc2209->wFrame[1] = tmc2209->mtr_id; + tmc2209->wFrame[2] = reg | 0x80; + tmc2209->wFrame[3] = (val >> 24) & 0xFF; + tmc2209->wFrame[4] = (val >> 16) & 0xFF; + tmc2209->wFrame[5] = (val >> 8) & 0xFF; + tmc2209->wFrame[6] = val & 0xFF; + tmc2209->wFrame[7] = compute_crc8_atm(tmc2209->wFrame, sizeof(tmc2209->wFrame) - 1, 0); + + // printf("val : %d\n",val); + + // printf("Frames :"); + // for (int i = 0; i < 8; i++) { + // printf("%X ", tmc2209->wFrame[i]); + // } + // printf("\n"); + + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[0]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[1]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[2]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[3]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[4]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[5]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[6]); + uart_putc(tmc2209->serial_instance->UART_ID, tmc2209->wFrame[7]); + + sleep_ms(3); + + return true; +} + +bool write_reg_check(TMC2209* tmc2209, int reg, int val) { + + int ifcnt12 = read_int(tmc2209, IFCNT); + unsigned int ifcnt1 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + write_reg(tmc2209, reg, val); + + int ifcnt22 = read_int(tmc2209, IFCNT); + unsigned int ifcnt2 = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (ifcnt1 >= ifcnt2) { + printf("TMC2209: writing not successful!\n"); + printf("reg: %X val: %d\n", reg, val); + printf("ifcnt: %d %d\n", ifcnt1, ifcnt2); + return false; + } + + return true; +} + +void TMC2209_destroy(TMC2209* tmc2209) { + // free(tmc2209); +} + + + + + +void driver_status(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: DRIVER STATUS:\n"); + read_int(tmc2209, DRVSTATUS); + unsigned int drvstatus = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Drvstatus : %d \n",drvstatus); + + if (drvstatus & STST) { + printf("TMC2209: Info: motor is standing still\n"); + } else { + printf("TMC2209: Info: motor is running\n"); + } + + if (drvstatus & STEALTH) { + printf("TMC2209: Info: motor is running on StealthChop\n"); + } else { + printf("TMC2209: Info: motor is running on SpreadCycle\n"); + } + + int cs_act = drvstatus & CS_ACTUAL; + cs_act >>= 16; + printf("TMC2209: CS actual: %d\n", cs_act); + + if (drvstatus & OLB) { + printf("TMC2209: Warning: Open load detected on phase B\n"); + } + if (drvstatus & OLA) { + printf("TMC2209: Warning: Open load detected on phase A\n"); + } + if (drvstatus & S2VSB) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase B. The driver becomes disabled\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short on low-side MOSFET detected on phase A. The driver becomes disabled\n"); + } + if (drvstatus & S2GB) { + printf("TMC2209: Error: Short to GND detected on phase B. The driver becomes disabled.\n"); + } + if (drvstatus & S2GA) { + printf("TMC2209: Error: Short to GND detected on phase A. The driver becomes disabled.\n"); + } + if (drvstatus & OT) { + printf("TMC2209: Error: Driver Overheating!\n"); + } + if (drvstatus & OTPW) { + printf("TMC2209: Warning: Driver Overheating Prewarning!\n"); + } +} + +// Fonction general_config +void general_config(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL CONFIG\n"); + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Gconf : %d \n",gconf); + + if (gconf & I_SCALE_ANALOG) { + printf("TMC2209: Driver is using voltage supplied to VREF as current reference\n"); + } else { + printf("TMC2209: Driver is using internal reference derived from 5VOUT\n"); + } + + if (gconf & INTERNAL_RSENSE) { + printf("TMC2209: Internal sense resistors. Use current supplied into VREF as reference.\n"); + printf("TMC2209: VREF pin internally is driven to GND in this mode.\n"); + printf("TMC2209: This will most likely destroy your driver!!!\n"); + exit(EXIT_FAILURE); + } else { + printf("TMC2209: Operation with external sense resistors\n"); + } + + if (gconf & EN_SPREADCYCLE) { + printf("TMC2209: SpreadCycle mode enabled\n"); + } else { + printf("TMC2209: StealthChop PWM mode enabled\n"); + } + + if (gconf & SHAFT) { + printf("TMC2209: Inverse motor direction\n"); + } else { + printf("TMC2209: normal motor direction\n"); + } + + if (gconf & INDEX_OTPW) { + printf("TMC2209: INDEX pin outputs overtemperature prewarning flag\n"); + } else { + printf("TMC2209: INDEX shows the first microstep position of sequencer\n"); + } + + if (gconf & INDEX_STEP) { + printf("TMC2209: INDEX output shows step pulses from internal pulse generator\n"); + } else { + printf("TMC2209: INDEX output as selected by index_otpw\n"); + } +} + +// Fonction general_stat +void general_stat(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: GENERAL STAT\n"); + read_int(tmc2209, GSTAT); + unsigned int gstat = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + printf("Gstat : %d \n",gstat); + if (gstat & RESET) { + printf("TMC2209: The driver has been reset since the last read access to GSTAT\n"); + } else { + printf("TMC2209: The driver has not been reset since the last read access to GSTAT\n"); + } + + if (gstat & DRV_ERR) { + printf("TMC2209: The driver has been shut down due to overtemperature or short circuit detection since the last read access\n"); + } else { + printf("TMC2209: The driver has not been shut down due to overtemperature or short circuit detection since the last read access\n"); + } + + if (gstat & UV_CP) { + printf("TMC2209: Undervoltage detected on the charge pump. The driver is disabled in this case\n"); + } else { + printf("TMC2209: No undervoltage detected on the charge pump. The driver is not disabled in this case\n"); + } + + + printf("end Gstat\n"); +} + + +bool set_vactual(TMC2209* tmc2209, int value) { + return write_reg_check(tmc2209, VACTUAL, value); +} + + + +unsigned int set_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value | bit; + // printf("value %d ,set_bit temp : %d\n" ,value,temp); + return temp; +} + + +// Fonction pour définir un bit spécifique à 0 +unsigned int clear_bit(unsigned int value, unsigned int bit) { + unsigned int temp = value & ~(bit); + // printf("value %d ,clear_bit temp : %d\n" ,value,temp); + return temp; +} + + +void clear_general_stat(TMC2209* tmc2209) { + read_int(tmc2209, GSTAT); + unsigned int gstat= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + gstat = set_bit(gstat, RESET); + gstat = set_bit(gstat, DRV_ERR); + write_reg_check(tmc2209, GSTAT, gstat); +} + + + +void set_voltage_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); // Lire la valeur actuelle du registre CHOPCONF + unsigned int chopconf= (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf |= VSENSE; + } else { + chopconf &= ~VSENSE; + } + + if (!write_reg_check(tmc2209, CHOPCONF, chopconf)) { + printf("Erreur lors de l'écriture de la valeur dans le registre CHOPCONF\n"); + } +} + +bool get_voltage_sense(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + return (chopconf & VSENSE) != 0; +} + + +void set_current_flow(TMC2209* tmc2209,double run_current, double hold_current_multiplier, int hold_current_delay, double Vref) { + double CS_IRun = 0.0; + double Rsense = 0.11; + double Vfs = 0.0; + Vref = 5.4; + hold_current_multiplier = 0.5; + hold_current_delay = 10; + run_current = 1800; + + int voltage_sense = get_voltage_sense(tmc2209); + + if (voltage_sense) { + Vfs = 0.180 * Vref / 2.5; + } else { + Vfs = 0.325 * Vref / 2.5; + } + + CS_IRun = 32.0 * 1.41421 * run_current / 1000.0 * (Rsense + 0.02) / Vfs - 1; + CS_IRun = fmin(CS_IRun, 31); + CS_IRun = fmax(CS_IRun, 0); + double CS_IHold = hold_current_multiplier * CS_IRun; + CS_IRun = round(CS_IRun); + CS_IHold = round(CS_IHold); + + // printf("CS_IHold_rounded %.3f, CS_IRun_rounded %.3f, hold_current_delay %d\n" , CS_IHold, CS_IRun, hold_current_delay); + + set_irun_ihold(tmc2209,CS_IHold, CS_IRun, hold_current_delay); +} + +int get_iscale_analog(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & I_SCALE_ANALOG) ; +} + +void set_iscale_analog(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (enabled) { + gconf = set_bit(gconf, I_SCALE_ANALOG); + } else { + + gconf = clear_bit(gconf, I_SCALE_ANALOG); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +int get_interpolation(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (chopconf & INTPOL) ; +} + +void set_interpolation(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + chopconf = set_bit(chopconf, INTPOL); + } else { + chopconf = clear_bit(chopconf, INTPOL); + } + + write_reg_check(tmc2209, CHOPCONF, chopconf); +} + +int get_internal_resistor_sense(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & INTERNAL_RSENSE) ; +} + + +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, INTERNAL_RSENSE); + } else { + + gconf = clear_bit(gconf, INTERNAL_RSENSE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +int get_spread_cycle(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & EN_SPREADCYCLE) ; +} + + +void set_spread_cycle(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + + gconf = set_bit(gconf, EN_SPREADCYCLE); + } else { + + gconf = clear_bit(gconf, EN_SPREADCYCLE); + } + + write_reg_check(tmc2209, GCONF, gconf); +} + +void set_microstepping_resolution(TMC2209* tmc2209, int msres) { + + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + // printf("chopconf %d \n",chopconf); + + int msresdezimal = 8 - (int)log2(msres); + chopconf &= 4043309055; + chopconf |= msresdezimal << 24; + write_reg_check(tmc2209, CHOPCONF, chopconf); + set_microstep_resolution_regselect(tmc2209, true); +} + +int get_microstepping_resolution(TMC2209* tmc2209) { + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + + // printf("chopconf : %d\n", chopconf); + int msresdezimal = chopconf & (MSRES0 | MSRES1 | MSRES2 | MSRES3); + msresdezimal = msresdezimal >> 24; + msresdezimal = 8 - msresdezimal; + int micro_stepping_resolution = (int)pow(2, msresdezimal); + + return micro_stepping_resolution; +} + +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + if (enabled) { + gconf = set_bit(gconf, MSTEP_REG_SELECT); + } else { + gconf = clear_bit(gconf, MSTEP_REG_SELECT); + } + // printf("gconf : %d \n",gconf); + + write_reg_check(tmc2209, GCONF, gconf); +} + + +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay) { + // Convertir les valeurs doubles en entiers + int ihold_irun = 0; + int ih = (int)IHold; + int ir = (int)IRun; + + ihold_irun |= ih << 0; + // printf("ihold_irun1 : %d\n",ihold_irun); + + ihold_irun |= ir << 8; + // printf("ihold_irun2 : %d\n",ihold_irun); + + ihold_irun |= IHoldDelay << 16; + + // printf("ihold_irun3 : %d\n",ihold_irun); + + write_reg_check(tmc2209, IHOLD_IRUN, ihold_irun); +} + +int get_direction_shart(TMC2209* tmc2209) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return (gconf & SHAFT) ; +} + + + + +void ioin(TMC2209* tmc2209) { + printf("TMC2209: ---\n"); + printf("TMC2209: INPUTS\n"); + read_int(tmc2209, IOIN); + unsigned int ioin = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + + if (ioin & IO_SPREAD) { + printf("TMC2209: spread is high\n"); + } else { + printf("TMC2209: spread is low\n"); + } + + if (ioin & IO_DIR) { + printf("TMC2209: dir is high\n"); + } else { + printf("TMC2209: dir is low\n"); + } + + if (ioin & IO_STEP) { + printf("TMC2209: step is high\n"); + } else { + printf("TMC2209: step is low\n"); + } + + if (ioin & IO_ENN) { + printf("TMC2209: en is high\n"); + } else { + printf("TMC2209: en is low\n"); + } +} + + + +void chopper_control(TMC2209* tmc2209, int direction) { + printf("TMC2209: ---\n"); + printf("TMC2209: CHOPPER CONTROL\n"); + read_int(tmc2209, CHOPCONF); + unsigned int chopconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (chopconf & INTPOL) { + printf("TMC2209: interpolation to 256 microsteps\n"); + } + + if (chopconf & VSENSE) { + printf("TMC2209: 1: High sensitivity, low sense resistor voltage\n"); + } else { + printf("TMC2209: 0: Low sensitivity, high sense resistor voltage\n"); + } +} + +void set_direction_shart(TMC2209* tmc2209, int direction) { + read_int(tmc2209, GCONF); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + int dir = get_direction_shart(tmc2209); + // printf("dir : %d , dir 8 : %d\n",dir,dir / 8); + if ((dir / 8) != direction) { + if (direction) { + gconf = set_bit(gconf, SHAFT); + } else { + gconf = clear_bit(gconf, SHAFT); + } + // printf("gconf : %d \n",gconf); + + write_reg_check(tmc2209, GCONF, gconf); + sleep_us(100); + } +} + + +int get_stallguard(TMC2209* tmc2209) { + read_int(tmc2209, SG_RESULT); + unsigned int stg = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return stg ; +} + + +void set_stallguard_threshold(TMC2209* tmc2209, int threshold){ + write_reg_check(tmc2209,SGTHRS, threshold); +} + +void set_coolstep_threshold(TMC2209* tmc2209, int threshold){ + write_reg_check(tmc2209,TCOOLTHRS, threshold); +} + + +void set_stallguard_callback(TMC2209* tmc2209, int stallguard_pin, int threshold, int callback, int min_speed){ + set_stallguard_threshold(tmc2209,threshold); + set_coolstep_threshold(tmc2209,min_speed); + + gpio_set_function(stallguard_pin, GPIO_FUNC_SIO); + gpio_pull_up(stallguard_pin); + + gpio_set_irq_enabled_with_callback(stallguard_pin, GPIO_IRQ_EDGE_RISE, true, callback); + +} + +int get_tstep(TMC2209* tmc2209) { + read_int(tmc2209, TSTEP); + unsigned int gconf = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + return gconf ; +} + + +int get_microstep_counter(TMC2209* tmc2209, bool in_steps, int offset) { + read_int(tmc2209, MSCNT); + unsigned int mscnt = (unsigned int)tmc2209->result[0] << 24 | + (unsigned int)tmc2209->result[1] << 16 | + (unsigned int)tmc2209->result[2] << 8 | + (unsigned int)tmc2209->result[3]; + + if (!in_steps) { + return mscnt; + } + + int micro_stepping_resolution = get_microstepping_resolution(tmc2209); // Remplacez par la résolution réelle du micro-pas + return round((4 * micro_stepping_resolution) - ((mscnt - 64) * (micro_stepping_resolution * 4) / 1024) - 1) + offset; +} diff --git a/TMC2209/Tmc2209.h b/TMC2209/Tmc2209.h new file mode 100644 index 0000000..11ac849 --- /dev/null +++ b/TMC2209/Tmc2209.h @@ -0,0 +1,695 @@ +// Tmc2209.h +#ifndef TMC2209_H +#define TMC2209_H + +#include "pico/stdlib.h" +#include "Tmc_uart.h" +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + TMC_UART* serial_instance; + int mtr_id; + uint8_t rFrame[4]; + uint8_t wFrame[8]; + uint64_t result[4]; +} TMC2209; + + +//====================================================================================== +// New def of reg, not use +//====================================================================================== + +typedef union { + uint8_t data[8]; + struct { + uint8_t adrress; + uint8_t mtr_id; + uint8_t reg; + uint8_t payload; + uint8_t crc; + } msg; +} TMC_uart_write_datagram_t; + +typedef union { + uint8_t data[4]; + struct { + uint8_t adrress; + uint8_t mtr_id; + uint8_t reg; + uint8_t crc8; + } msg; +} TMC_uart_read_datagram_t; + + +enum tmc2209_regaddr_t { + GCONF = 0x00, + GSTAT = 0x01, + IFCNT = 0x02, + SLAVECONF = 0x03, + OTP_PROG = 0x04, + OTP_READ = 0x05, + IOIN = 0x06, + FACTORY_CONF = 0x07, + + IHOLD_IRUN = 0x10, + TPOWERDOWN = 0x11, + TSTEP = 0x12, + TPWMTHRS = 0x13, + VACTUAL = 0x22, + TCOOLTHRS = 0x14, + SGTHRS = 0x40, + SG_RESULT = 0x41, + COOLCONF = 0x42, + + MSCNT = 0x6A, + MSCURACT = 0x6B, + CHOPCONF = 0x6C, + DRV_STATUS = 0x6F, + PWMCONF = 0x70, + PWM_SCALE = 0x71, + PWM_AUTO = 0x72, + LAST_ADDR = PWM_AUTO +}; + + + + + +typedef union { + uint8_t value; + struct { + uint8_t + reset_flag :1, + driver_error :1, + sg2 :1, + standstill :1, + unused :4; + }; +} TMC2209_status_t; + +// --- register definitions --- + +// GCONF : RW +typedef union { + uint32_t value; + struct { + uint32_t + I_scale_analog :1, + internal_Rsense :1, + en_spreadcycle :1, + shaft :1, + index_otpw :1, + index_step :1, + pdn_disable :1, + mstep_reg_select :1, + multistep_filt :1, + test_mode :1, + reserved :22; + }; +} TMC2209_gconf_reg_t; + +// GSTAT : R+C +typedef union { + uint32_t value; + struct { + uint32_t + reset :1, + drv_err :1, + uv_cp :1, + reserved :29; + }; +} TMC2209_gstat_reg_t; + +// IFCNT : R +typedef union { + uint32_t value; + struct { + uint32_t + count :8, + reserved :24; + }; +} TMC2209_ifcnt_reg_t; + +// SLAVECONF : W +typedef union { + uint32_t value; + struct { + uint32_t + reserved0 :8, + conf :4, + reserved1 :20; + }; +} TMC2209_slaveconf_reg_t; + +// OTP_PROG : W +typedef union { + uint32_t value; + struct { + uint32_t + otpbit :2, + otpbyte :2, + otpmagic :28; + }; +} TMC2209_otp_prog_reg_t; + +// OTP_READ : R +typedef union { + uint32_t value; + struct { + uint32_t + otp0_0_4 :5, + otp0_5 :1, + otp0_6 :1, + otp0_7 :1, + otp1_0_3 :4, + otp1_4 :1, + otp1_5_7 :3, + otp2_0 :1, + otp2_1 :1, + otp2_2 :1, + otp2_3_4 :2, + otp2_5_6 :2, + otp2_7 :1, + reserved :8; + }; +} TMC2209_otp_read_reg_t; + +// IOIN : R +typedef union { + uint32_t value; + struct { + uint32_t + enn :1, + unused0 :1, + ms1 :1, + ms2 :1, + diag :1, + unused1 :1, + pdn_uart :1, + step :1, + spread_en :1, + dir :1, + reserved :14, + version :8; + }; +} TMC2209_ioin_reg_t; + +// FACTORY_CONF : RW +typedef union { + uint32_t value; + struct { + uint32_t + fclktrim :4, + reserved1 :3, + ottrim :2, + reserved :23; + }; +} TMC2209_factory_conf_reg_t; + +// IHOLD_IRUN : R +typedef union { + uint32_t value; + struct { + uint32_t + ihold :5, + reserved1 :3, + irun :5, + reserved2 :3, + iholddelay :4, + reserved3 :12; + }; +} TMC2209_ihold_irun_reg_t; + +// TPOWERDOWN : W +typedef union { + uint32_t value; + struct { + uint32_t + tpowerdown :8, + reserved :24; + }; +} TMC2209_tpowerdown_reg_t; + +// TSTEP : R +typedef union { + uint32_t value; + struct { + uint32_t + tstep :20, + reserved :12; + }; +} TMC2209_tstep_reg_t; + +// TPWMTHRS : W +typedef union { + uint32_t value; + struct { + uint32_t + tpwmthrs :20, + reserved :12; + }; +} TMC2209_tpwmthrs_reg_t; + +// TCOOLTHRS : W +typedef union { + uint32_t value; + struct { + uint32_t + tcoolthrs :20, + reserved :12; + }; +} TMC2209_tcoolthrs_reg_t; + +// VACTUAL : W +typedef union { + uint32_t value; + struct { + uint32_t + actual :24, + reserved :8; + }; +} TMC2209_vactual_reg_t; + +// SGTHRS : W +typedef union { + uint32_t value; + struct { + uint32_t + threshold :8, + reserved :24; + }; +} TMC2209_sgthrs_reg_t; + +// SG_RESULT : R +typedef union { + uint32_t value; + struct { + uint32_t + result :10, + reserved :22; + }; +} TMC2209_sg_result_reg_t; + +// MSCNT : R +typedef union { + uint32_t value; + struct { + uint32_t + mscnt :10, + reserved :22; + }; +} TMC2209_mscnt_reg_t; + +// MSCURACT : R +typedef union { + uint32_t value; + struct { + uint32_t + cur_a :9, + reserved1 :7, + cur_b :9, + reserved2 :7; + }; +} TMC2209_mscuract_reg_t; + +// CHOPCONF : RW +typedef union { + uint32_t value; + struct { + uint32_t + toff :4, + hstrt :3, + hend :4, + reserved0 :4, + tbl :2, + vsense :1, + reserved1 :6, + mres :4, + intpol :1, + dedge :1, + diss2g :1, + diss2vs :1; + }; +} TMC2209_chopconf_reg_t; + +// DRV_STATUS : R +typedef union { + uint32_t value; + struct { + uint32_t + otpw :1, + ot :1, + s2ga :1, + s2gb :1, + s2vsa :1, + s2vsb :1, + ola :1, + olb :1, + t120 :1, + t143 :1, + t150 :1, + t157 :1, + reserved1 :4, + cs_actual :5, + reserved2 :3, + reserved3 :6, + stealth :1, + stst :1; + }; +} TMC2209_drv_status_reg_t; + +// COOLCONF : W +typedef union { + uint32_t value; + struct { + uint32_t + semin :4, + reserved1 :1, + seup :2, + reserved2 :1, + semax :4, + reserved3 :1, + sedn :2, + seimin :1, + reserved5 :16; + }; +} TMC2209_coolconf_reg_t; + +// PWMCONF : W +typedef union { + uint32_t value; + struct { + uint32_t + pwm_ofs :8, + pwm_grad :8, + pwm_freq :2, + pwm_autoscale :1, + pwm_autograd :1, + freewheel :2, + reserved :2, + pwm_reg :4, + pwm_lim :4; + }; +} TMC2209_pwmconf_reg_t; + +// PWM_SCALE : R +typedef union { + uint32_t value; + struct { + uint32_t + pwm_scale_sum :8, + reserved1 :8, + pwm_scale_auto :9, + reserved2 :7; + }; +} TMC2209_pwm_scale_reg_t; + +// PWM_AUTO : R +typedef union { + uint32_t value; + struct { + uint32_t + pwm_ofs_auto :8, + unused0 :8, + pwm_grad_auto :8, + unused1 :8; + }; +} TMC2209_pwm_auto_ctrl_reg_t; + +// --- end of register definitions --- + +typedef union { + // tmc2209_regaddr_t reg; + uint8_t value; + struct { + uint8_t + idx :7, + write :1; + }; +} TMC2209_addr_t; + +// --- datagrams --- + +typedef struct { + TMC2209_addr_t addr; + TMC2209_gconf_reg_t reg; +} TMC2209_gconf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_gstat_reg_t reg; +} TMC2209_gstat_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_tpowerdown_reg_t reg; +} TMC2209_tpowerdown_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_ifcnt_reg_t reg; +} TMC2209_ifcnt_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_slaveconf_reg_t reg; +} TMC2209_slaveconf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_otp_prog_reg_t reg; +} TMC2209_otp_prog_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_otp_read_reg_t reg; +} TMC2209_otp_read_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_ioin_reg_t reg; +} TMC2209_ioin_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_factory_conf_reg_t reg; +} TMC2209_factory_conf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_ihold_irun_reg_t reg; +} TMC2209_ihold_irun_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_tstep_reg_t reg; +} TMC2209_tstep_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_tpwmthrs_reg_t reg; +} TMC2209_tpwmthrs_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_tcoolthrs_reg_t reg; +} TMC2209_tcoolthrs_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_vactual_reg_t reg; +} TMC2209_vactual_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_sgthrs_reg_t reg; +} TMC2209_sgthrs_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_sg_result_reg_t reg; +} TMC2209_sg_result_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_mscnt_reg_t reg; +} TMC2209_mscnt_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_mscuract_reg_t reg; +} TMC2209_mscuract_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_chopconf_reg_t reg; +} TMC2209_chopconf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_drv_status_reg_t reg; +} TMC2209_drv_status_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_coolconf_reg_t reg; +} TMC2209_coolconf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_pwmconf_reg_t reg; +} TMC2209_pwmconf_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_pwm_scale_reg_t reg; +} TMC2209_pwm_scale_dgr_t; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_pwm_auto_ctrl_reg_t reg; +} TMC2209_pwm_auto_ctrl_dgr_t; + +// -- end of datagrams + +typedef union { + uint32_t value; + uint8_t data[4]; + TMC2209_gconf_reg_t gconf; + TMC2209_gstat_reg_t gstat; + TMC2209_ifcnt_reg_t ifcnt; + TMC2209_slaveconf_reg_t slaveconf; + TMC2209_otp_prog_reg_t otp_prog; + TMC2209_otp_read_reg_t otp_read; + TMC2209_ioin_reg_t ioin; + TMC2209_factory_conf_reg_t factory_conf; + TMC2209_ihold_irun_reg_t ihold_irun; + TMC2209_tpowerdown_reg_t tpowerdown; + TMC2209_tstep_reg_t tstep; + TMC2209_tpwmthrs_reg_t tpwmthrs; + TMC2209_tcoolthrs_reg_t tcoolthrs; + TMC2209_vactual_reg_t vactual; + TMC2209_sgthrs_reg_t sgthrs; + TMC2209_sg_result_reg_t sg_result; + TMC2209_coolconf_reg_t coolconf; + TMC2209_mscnt_reg_t mscnt; + TMC2209_mscuract_reg_t mscuract; + TMC2209_chopconf_reg_t chopconf; + TMC2209_drv_status_reg_t drv_status; + TMC2209_pwmconf_reg_t pwmconf; + TMC2209_pwm_scale_reg_t pwm_scale; + TMC2209_pwm_auto_ctrl_reg_t pwm_auto_ctrl; +} TMC2209_payload; + +typedef struct { + TMC2209_addr_t addr; + TMC2209_payload payload; +} TMC2209_datagram_t; + +typedef union { + uint8_t data[8]; + struct { + uint8_t sync; + uint8_t slave; + TMC2209_addr_t addr; + TMC2209_payload payload; + uint8_t crc; + } msg; +} TMC2209_write_datagram_t; + +typedef union { + uint8_t data[4]; + struct { + uint8_t sync; + uint8_t slave; + TMC2209_addr_t addr; + uint8_t crc; + } msg; +} TMC2209_read_datagram_t; + +typedef struct { + // driver registers + TMC2209_gconf_dgr_t gconf; + TMC2209_gstat_dgr_t gstat; + TMC2209_ifcnt_dgr_t ifcnt; + TMC2209_slaveconf_dgr_t slaveconf; + TMC2209_otp_prog_dgr_t otp_prog; + TMC2209_otp_read_dgr_t otp_read; + TMC2209_ioin_dgr_t ioin; + TMC2209_factory_conf_dgr_t factory_conf; + TMC2209_ihold_irun_dgr_t ihold_irun; + TMC2209_tpowerdown_dgr_t tpowerdown; + TMC2209_tstep_dgr_t tstep; + TMC2209_tpwmthrs_dgr_t tpwmthrs; + TMC2209_tcoolthrs_dgr_t tcoolthrs; + TMC2209_vactual_dgr_t vactual; + TMC2209_sgthrs_dgr_t sgthrs; + TMC2209_sg_result_dgr_t sg_result; + TMC2209_coolconf_dgr_t coolconf; + TMC2209_mscnt_dgr_t mscnt; + TMC2209_mscuract_dgr_t mscuract; + TMC2209_chopconf_dgr_t chopconf; + TMC2209_drv_status_dgr_t drv_status; + TMC2209_pwmconf_dgr_t pwmconf; + TMC2209_pwm_scale_dgr_t pwm_scale; + TMC2209_pwm_auto_ctrl_dgr_t pwm_auto; + + TMC2209_status_t driver_status; + + // trinamic_config_t config; +} TMC2209_t; + +//====================================================================================== + + + +void TMC2209_Init(TMC2209* tmc2209, TMC_UART* serial_instance); //ok +void TMC2209_destroy(TMC2209* tmc2209); //TODO +uint8_t compute_crc8_atm(const uint8_t *datagram, size_t length, uint8_t initial_value); //ok +uint64_t* read_reg(TMC2209* tmc2209, int reg) ; //ok +uint32_t read_int(TMC2209* tmc2209, int reg); //ok +bool write_reg(TMC2209* tmc2209, int reg, int val); //ok +bool write_reg_check(TMC2209* tmc2209, int reg, int val) ; //ok + +void driver_status(TMC2209* tmc2209); //NotWork +void general_config(TMC2209* tmc2209); //NotWork +void general_stat(TMC2209* tmc2209); //NotWork + +bool set_vactual(TMC2209* tmc2209, int value); //ok +void set_voltage_sense(TMC2209* tmc2209, bool enabled); //ok +bool get_voltage_sense(TMC2209* tmc2209); //ok +void set_current_flow(TMC2209* tmc2209, double run_current, double hold_current_multiplier, int hold_current_delay, double Vref);//averif NotWork + +int get_iscale_analog(TMC2209* tmc2209); //ok +void set_iscale_analog(TMC2209* tmc2209, bool enabled); //ok +int get_interpolation(TMC2209* tmc2209); //ok +void set_interpolation(TMC2209* tmc2209, bool enabled); //ok +int get_internal_resistor_sense(TMC2209* tmc2209); //ok +void set_internal_resistor_sense(TMC2209* tmc2209, bool enabled); //ok +int get_spread_cycle(TMC2209* tmc2209); //NotWork +void set_spread_cycle(TMC2209* tmc2209, bool enabled); //NotWork + +void set_microstepping_resolution(TMC2209* tmc2209, int msres); //ok +int get_microstepping_resolution(TMC2209* tmc2209); //ok +void set_microstep_resolution_regselect(TMC2209* tmc2209, bool enabled); //ok +void set_irun_ihold(TMC2209* tmc2209, double IHold, double IRun, int IHoldDelay); //ok + +int get_direction_shart(TMC2209* tmc2209); //ok +void ioin(TMC2209* tmc2209); +void clear_general_stat(TMC2209* tmc2209); //ok +void set_direction_shart(TMC2209* tmc2209, int direction); //ok + +int get_stallguard(TMC2209* tmc2209); +void set_stallguard_threshold(TMC2209* tmc2209, int threshold); +void set_coolstep_threshold(TMC2209* tmc2209, int threshold); +void set_stallguard_callback(TMC2209* tmc2209, int stallguard_pin, int threshold, int callback, int min_speed); +int get_tstep(TMC2209* tmc2209); +int get_microstep_counter(TMC2209* tmc2209, bool in_steps, int offset); + +#endif diff --git a/TMC2209/Tmc_uart.c b/TMC2209/Tmc_uart.c new file mode 100644 index 0000000..6b1f142 --- /dev/null +++ b/TMC2209/Tmc_uart.c @@ -0,0 +1,36 @@ +// TMC_UART.c +#include "TMC_uart.h" + + +#define DEFAULT_UART_ID uart1 +#define DEFAULT_BAUD_RATE 115200 +#define DEFAULT_MOTOR_TX_PIN 4 +#define DEFAULT_MOTOR_RX_PIN 5 + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN) { + + if (BAUD_RATE == -1) BAUD_RATE = DEFAULT_BAUD_RATE; + if (MOTOR_TX_PIN == -1) MOTOR_TX_PIN = DEFAULT_MOTOR_TX_PIN; + if (MOTOR_RX_PIN == -1) MOTOR_RX_PIN = DEFAULT_MOTOR_RX_PIN; + + uart_init(UART_ID, BAUD_RATE); + gpio_set_function(MOTOR_TX_PIN, GPIO_FUNC_UART); + gpio_set_function(MOTOR_RX_PIN, GPIO_FUNC_UART); + uart_set_hw_flow(UART_ID, false, false); + uart_set_format(UART_ID, 8, 1, UART_PARITY_NONE); + uart_set_fifo_enabled(UART_ID, false); + + tmc_uart->UART_ID = UART_ID; + tmc_uart->BAUD_RATE = BAUD_RATE; + tmc_uart->MOTOR_TX_PIN = MOTOR_TX_PIN; + tmc_uart->MOTOR_RX_PIN = MOTOR_RX_PIN; + return tmc_uart; +} + +void TMC_UART_Write(TMC_UART* tmc_uart, int data) { + uart_putc(tmc_uart->UART_ID, data); +} + +void TMC_UART_Destroy(TMC_UART* tmc_uart) { + // Aucune opération nécessaire +} diff --git a/TMC2209/Tmc_uart.h b/TMC2209/Tmc_uart.h new file mode 100644 index 0000000..b7d2d5d --- /dev/null +++ b/TMC2209/Tmc_uart.h @@ -0,0 +1,18 @@ +// TMC_UART.h +#ifndef TMC_UART_H +#define TMC_UART_H + +#include +#include "pico/stdlib.h" + +typedef struct { + uart_inst_t *UART_ID; + int BAUD_RATE; + int MOTOR_TX_PIN; + int MOTOR_RX_PIN; +} TMC_UART; + +TMC_UART* tmc_Uart_Init(TMC_UART* tmc_uart, uart_inst_t *UART_ID, int BAUD_RATE, int MOTOR_TX_PIN, int MOTOR_RX_PIN); +void tmc_Uart_Destroy(TMC_UART* TMC_UART); + +#endif diff --git a/TMC2209/lib/tmc/boards/Board.c b/TMC2209/lib/tmc/boards/Board.c new file mode 100644 index 0000000..a80f290 --- /dev/null +++ b/TMC2209/lib/tmc/boards/Board.c @@ -0,0 +1,172 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Board.h" + +MotionControllerBoards motionControllerBoards; +DriverBoards driverBoards; + +static void deInit(void) {} + +// Evalboard channel function dummies +static uint32_t dummy_Motor(uint8_t motor) +{ + UNUSED(motor); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_MotorValue(uint8_t motor, int32_t value) +{ + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static void dummy_AddressRef(uint8_t motor, uint16_t address, int32_t *value) +{ + UNUSED(motor); + UNUSED(address); + UNUSED(value); +} + +static void dummy_AddressValue(uint8_t motor, uint16_t address, int32_t value) +{ + UNUSED(motor); + UNUSED(address); + UNUSED(value); +} + +static uint32_t dummy_MotorRef(uint8_t motor, int32_t *value) +{ + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_TypeMotorValue(uint8_t type, uint8_t motor, int32_t value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_TypeMotorRef(uint8_t type, uint8_t motor, int32_t *value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint32_t dummy_getLimit(uint8_t type, uint8_t motor, int32_t *value) +{ + UNUSED(type); + UNUSED(motor); + UNUSED(value); + return TMC_ERROR_FUNCTION; +} + +static uint8_t dummy_onPinChange(IOPinTypeDef *pin, IO_States state) +{ + UNUSED(pin); + UNUSED(state); + return 1; +} + +static void dummy_OTP_init(void) +{ + return; +} + +static void dummy_OTP_address(uint32_t address) +{ + UNUSED(address); + return; +} + +static void dummy_OTP_value(uint32_t value) +{ + UNUSED(value); + return; +} + +static void dummy_OTP_program(void) +{ + return; +} + +static void dummy_OTP_lock(void) +{ + return; +} + +static OTP_Status dummy_OTP_status(void) +{ + return OTP_STATUS_IDLE; +} + +static uint8_t delegationReturn(void) +{ + return 1; +} + +static void enableDriver(DriverState state) +{ + UNUSED(state); +} + +static void periodicJob(uint32_t tick) +{ + UNUSED(tick); +} + +void board_setDummyFunctions(EvalboardFunctionsTypeDef *channel) +{ + channel->config->reset = delegationReturn; + channel->config->restore = delegationReturn; + + channel->deInit = deInit; + channel->periodicJob = periodicJob; + channel->left = dummy_MotorValue; + channel->stop = dummy_Motor; + channel->moveTo = dummy_MotorValue; + channel->moveBy = dummy_MotorRef; + channel->moveProfile = dummy_MotorValue; + channel->right = dummy_MotorValue; + channel->GAP = dummy_TypeMotorRef; + channel->readRegister = dummy_AddressRef; + channel->writeRegister = dummy_AddressValue; + channel->SAP = dummy_TypeMotorValue; + channel->SIO = dummy_TypeMotorValue; + channel->GIO = dummy_TypeMotorRef; + channel->STAP = dummy_TypeMotorValue; + channel->RSAP = dummy_TypeMotorValue; + channel->userFunction = dummy_TypeMotorRef; + channel->getMeasuredSpeed = dummy_MotorRef; + channel->checkErrors = periodicJob; + channel->enableDriver = enableDriver; + + channel->fullCover = NULL; + channel->getMin = dummy_getLimit; + channel->getMax = dummy_getLimit; + channel->onPinChange = dummy_onPinChange; + + channel->OTP_init = dummy_OTP_init; + channel->OTP_address = dummy_OTP_address; + channel->OTP_value = dummy_OTP_value; + channel->OTP_program = dummy_OTP_program; + channel->OTP_status = dummy_OTP_status; + channel->OTP_lock = dummy_OTP_lock; +} + +void periodicJobDummy(uint32_t tick) +{ + UNUSED(tick); +} diff --git a/TMC2209/lib/tmc/boards/Board.h b/TMC2209/lib/tmc/boards/Board.h new file mode 100644 index 0000000..79ddfaf --- /dev/null +++ b/TMC2209/lib/tmc/boards/Board.h @@ -0,0 +1,197 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef BOARD_H +#define BOARD_H + +#include "tmc/helpers/API_Header.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "tmc/VitalSignsMonitor.h" + +#include "tmc/ic/TMC2130/TMC2130.h" +#include "tmc/ic/TMC2160/TMC2160.h" +#include "tmc/ic/TMC2208/TMC2208.h" +#include "tmc/ic/TMC2224/TMC2224.h" +#include "tmc/ic/TMC2590/TMC2590.h" +#include "tmc/ic/TMC2660/TMC2660.h" +#include "tmc/ic/TMC6100/TMC6100.h" +#include "tmc/ic/TMC6200/TMC6200.h" +#include "tmc/ic/TMC7300/TMC7300.h" + + +#include "tmc/ic/TMC2209/TMC2209.h" +#include "tmc/ic/TMC2225/TMC2225.h" +#include "tmc/ic/TMC2226/TMC2226.h" +#include "tmc/ic/TMC2300/TMC2300.h" +#include "tmc/ic/MAX22216/MAX22216.h" +#include "tmc/ic/TMC4361A/TMC4361A.h" +#include "tmc/ic/TMC5031/TMC5031.h" +#include "tmc/ic/TMC5041/TMC5041.h" +#include "tmc/ic/TMC5062/TMC5062.h" +#include "tmc/ic/TMC5072/TMC5072.h" +#include "tmc/ic/TMC5130/TMC5130.h" +#include "tmc/ic/TMC5160/TMC5160.h" +#include "tmc/ic/TMC8461/TMC8461.h" +#include "tmc/ic/TMC8462/TMC8462.h" + +// parameter access (for axis parameters) +#define READ 0 +#define WRITE 1 + +typedef enum { + LIMIT_MIN, + LIMIT_MAX +} AxisParameterLimit; + +typedef enum { + DRIVER_DISABLE, + DRIVER_ENABLE, + DRIVER_USE_GLOBAL_ENABLE +} DriverState; + +typedef enum { + OTP_STATUS_IDLE = 0, + OTP_STATUS_PROGRAMMING = 1, + OTP_STATUS_DONE = 2, + OTP_STATUS_FAILED = 3 +} OTP_Status; + +// Evalboard channel struct +typedef struct +{ + void *type; + uint8_t id; + uint32_t errors; + int32_t VMMax; + int32_t VMMin; + unsigned char numberOfMotors; + ConfigurationTypeDef *config; + uint32_t (*left) (uint8_t motor, int32_t velocity); // move left with velocity + uint32_t (*right) (uint8_t motor, int32_t velocity); // move right with velocity + uint32_t (*rotate) (uint8_t motor, int32_t velocity); // move right with velocity + uint32_t (*stop) (uint8_t motor); // stop motor + uint32_t (*moveTo) (uint8_t motor, int32_t position); // move to position + uint32_t (*moveBy) (uint8_t motor, int32_t *ticks); // move by , changes ticks to absolute target + uint32_t (*moveProfile) (uint8_t motor, int32_t position); // move profile + uint32_t (*SAP) (uint8_t type, uint8_t motor, int32_t value); // set axis parameter -> TMCL conformance + uint32_t (*GAP) (uint8_t type, uint8_t motor, int32_t *value); // get axis parameter -> TMCL conformance + uint32_t (*STAP) (uint8_t type, uint8_t motor, int32_t value); // store axis parameter -> TMCL conformance + uint32_t (*RSAP) (uint8_t type, uint8_t motor, int32_t value); // restore axis parameter -> TMCL conformance + uint32_t (*SIO) (uint8_t type, uint8_t motor, int32_t value); + uint32_t (*GIO) (uint8_t type, uint8_t motor, int32_t *value); + void (*readRegister) (uint8_t motor, uint16_t address, int32_t *value); // Motor needed since some chips utilize it as a switch between low and high values + void (*writeRegister) (uint8_t motor, uint16_t address, int32_t value); // Motor needed since some chips utilize it as a switch between low and high values + uint32_t (*getMeasuredSpeed) (uint8_t motor, int32_t *value); + uint32_t (*userFunction) (uint8_t type, uint8_t motor, int32_t *value); + + void (*periodicJob) (uint32_t tick); + void (*deInit) (void); + + void (*checkErrors) (uint32_t tick); + void (*enableDriver) (DriverState state); + + uint8_t (*cover) (uint8_t data, uint8_t lastTransfer); + void (*fullCover) (uint8_t *data, size_t length); + + uint32_t (*getMin) (uint8_t type, uint8_t motor, int32_t *value); + uint32_t (*getMax) (uint8_t type, uint8_t motor, int32_t *value); + + uint8_t (*onPinChange)(IOPinTypeDef *pin, IO_States state); + + void (*OTP_init)(void); + void (*OTP_address)(uint32_t address); + void (*OTP_value)(uint32_t value); + void (*OTP_program)(void); + void (*OTP_lock)(void); + OTP_Status (*OTP_status)(void); +} EvalboardFunctionsTypeDef; + + +// "hash" function to resolve API error <=> Map index +inline uint8_t error_index(uint8_t error) +{ + uint8_t i = 0; + for(; error != 1; i++) + error >>= 1; + return i; +} + +// Evalboard errors +// TODO: Extends API Error bits. For more information, see comment in TMCError typedef. +typedef enum { + TMC_ERROR_TYPE = 0x04, + TMC_ERROR_ADDRESS = 0x04, + TMC_ERROR_NOT_DONE = 0x20 +} EvalboardErrorBit; + +// Channel identifiers required to switch between channels in readWrite +typedef enum { + CHANNEL_1, + CHANNEL_2 +} EvalboardChannels; + +// struct for our Evalsystem, with two available Evalboard channels +typedef struct +{ + EvalboardFunctionsTypeDef ch1; + EvalboardFunctionsTypeDef ch2; + DriverState driverEnable; // global driver status +} EvalboardsTypeDef; + +extern EvalboardsTypeDef Evalboards; + +typedef enum { + TMC_BOARD_COMM_DEFAULT, + TMC_BOARD_COMM_SPI, + TMC_BOARD_COMM_UART, + TMC_BOARD_COMM_WLAN +} TMC_Board_Comm_Mode; + +// Group all the motion controller chip objects into a single union to save memory, +// since we will only ever use one driver at a time +typedef union { + TMC4361ATypeDef tmc4361A; + TMC5031TypeDef tmc5031; + TMC5041TypeDef tmc5041; + TMC5062TypeDef tmc5062; + TMC5072TypeDef tmc5072; + TMC5130TypeDef tmc5130; + TMC5160TypeDef tmc5160; + TMC8461TypeDef tmc8461; + TMC8462TypeDef tmc8462; +} MotionControllerBoards; +extern MotionControllerBoards motionControllerBoards; + +// Group all the driver chip objects into a single union to save memory, +// since we will only ever use one motion controller at a time +typedef union { + TMC2130TypeDef tmc2130; + TMC2160TypeDef tmc2160; + TMC2208TypeDef tmc2208; + TMC2224TypeDef tmc2224; + TMC2590TypeDef tmc2590; + TMC2660TypeDef tmc2660; + TMC7300TypeDef tmc7300; + TMC2209TypeDef tmc2209; + TMC2225TypeDef tmc2225; + TMC2226TypeDef tmc2226; + TMC2300TypeDef tmc2300; + MAX22216TypeDef max22216; +} DriverBoards; +extern DriverBoards driverBoards; + +void periodicJobDummy(uint32_t tick); +void board_setDummyFunctions(EvalboardFunctionsTypeDef *channel); + +#include "TMCDriver.h" +#include "TMCMotionController.h" + +#endif /* BOARD_H */ diff --git a/TMC2209/lib/tmc/boards/SelfTest.h b/TMC2209/lib/tmc/boards/SelfTest.h new file mode 100644 index 0000000..9d0447a --- /dev/null +++ b/TMC2209/lib/tmc/boards/SelfTest.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SELF_TEST_H +#define SELF_TEST_H + + #define SELF_TEST_PINS_PER_GROUP 17 + #define SELF_TEST_LEAVE 1 + #define SELF_TEST_A_OUT_B_IN 2 + #define SELF_TEST_A_IN_B_OUT 3 + #define SELF_TEST_READ_AN 4 + #define SELF_TEST_SET_AN 5 + #define SELF_TEST_SET_AN_2 6 + #define SELF_TEST_SET_MIXED 7 + #define SELF_TEST_SET_EXTIO 8 + +#endif /* SELF_TEST_H */ diff --git a/TMC2209/lib/tmc/boards/TMC2209_eval.c b/TMC2209/lib/tmc/boards/TMC2209_eval.c new file mode 100644 index 0000000..2dea26e --- /dev/null +++ b/TMC2209/lib/tmc/boards/TMC2209_eval.c @@ -0,0 +1,790 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Board.h" +#include "tmc/ic/TMC2209/TMC2209.h" +#include "tmc/StepDir.h" + +#undef TMC2209_MAX_VELOCITY +#define TMC2209_MAX_VELOCITY STEPDIR_MAX_VELOCITY + +// Stepdir precision: 2^17 -> 17 digits of precision +#define STEPDIR_PRECISION 131072 + +#define ERRORS_VM (1<<0) +#define ERRORS_VM_UNDER (1<<1) +#define ERRORS_VM_OVER (1<<2) + +#define VM_MIN 50 // VM[V/10] min +#define VM_MAX 390 // VM[V/10] max + +#define MOTORS 1 + +#define VREF_FULLSCALE 2100 // mV // with R308 achievable Vref_max is ~2100mV +//#define VREF_FULLSCALE 3300 // mV // without R308 achievable Vref_max is ~2500mV + + +static uint32_t right(uint8_t motor, int32_t velocity); +static uint32_t left(uint8_t motor, int32_t velocity); +static uint32_t rotate(uint8_t motor, int32_t velocity); +static uint32_t stop(uint8_t motor); +static uint32_t moveTo(uint8_t motor, int32_t position); +static uint32_t moveBy(uint8_t motor, int32_t *ticks); +static uint32_t GAP(uint8_t type, uint8_t motor, int32_t *value); +static uint32_t SAP(uint8_t type, uint8_t motor, int32_t value); + +static void checkErrors (uint32_t tick); +static void deInit(void); +static uint32_t userFunction(uint8_t type, uint8_t motor, int32_t *value); + +static void periodicJob(uint32_t tick); +static uint8_t reset(void); +static uint8_t restore(void); +static void enableDriver(DriverState state); + +static UART_Config *TMC2209_UARTChannel; +static ConfigurationTypeDef *TMC2209_config; + +static uint16_t vref; // mV +static int32_t thigh; + +static timer_channel timerChannel; +// Helper macro - Access the chip object in the driver boards union +#define TMC2209 (driverBoards.tmc2209) + +// Helper macro - index is always 1 here (channel 1 <-> index 0, channel 2 <-> index 1) +#define TMC2209_CRC(data, length) tmc_CRC8(data, length, 1) + +typedef struct +{ + IOPinTypeDef *ENN; + IOPinTypeDef *SPREAD; + IOPinTypeDef *STEP; + IOPinTypeDef *DIR; + IOPinTypeDef *MS1_AD0; + IOPinTypeDef *MS2_AD1; + IOPinTypeDef *DIAG; + IOPinTypeDef *INDEX; + IOPinTypeDef *UC_PWM; + IOPinTypeDef *STDBY; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static inline TMC2209TypeDef *motorToIC(uint8_t motor) +{ + UNUSED(motor); + + return &TMC2209; +} + +static inline UART_Config *channelToUART(uint8_t channel) +{ + UNUSED(channel); + + return TMC2209_UARTChannel; +} + +// => UART wrapper +// Write [writeLength] bytes from the [data] array. +// If [readLength] is greater than zero, read [readLength] bytes from the +// [data] array. +void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength) +{ + UART_readWrite(channelToUART(channel), data, writeLength, readLength); +} +// <= UART wrapper + +// => CRC wrapper +// Return the CRC8 of [length] bytes of data stored in the [data] array. +uint8_t tmc2209_CRC8(uint8_t *data, size_t length) +{ + return TMC2209_CRC(data, length); +} +// <= CRC wrapper + +void tmc2209_writeRegister(uint8_t motor, uint16_t address, int32_t value) +{ + tmc2209_writeInt(motorToIC(motor), (uint8_t) address, value); + +} + +void tmc2209_readRegister(uint8_t motor, uint16_t address, int32_t *value) +{ + *value = tmc2209_readInt(motorToIC(motor), (uint8_t) address); +} + +static uint32_t rotate(uint8_t motor, int32_t velocity) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + StepDir_rotate(motor, velocity); + + return TMC_ERROR_NONE; +} + +static uint32_t right(uint8_t motor, int32_t velocity) +{ + return rotate(motor, velocity); +} + +static uint32_t left(uint8_t motor, int32_t velocity) +{ + return rotate(motor, -velocity); +} + +static uint32_t stop(uint8_t motor) +{ + return rotate(motor, 0); +} + +static uint32_t moveTo(uint8_t motor, int32_t position) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + StepDir_moveTo(motor, position); + + return TMC_ERROR_NONE; +} + +static uint32_t moveBy(uint8_t motor, int32_t *ticks) +{ + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + // determine actual position and add numbers of ticks to move + *ticks += StepDir_getActualPosition(motor); + + return moveTo(motor, *ticks); +} + +static uint32_t handleParameter(uint8_t readWrite, uint8_t motor, uint8_t type, int32_t *value) +{ + uint32_t errors = TMC_ERROR_NONE; + int32_t buffer = 0; + + if(motor >= MOTORS) + return TMC_ERROR_MOTOR; + + switch(type) + { + case 0: + // Target position + if(readWrite == READ) { + *value = StepDir_getTargetPosition(motor); + } else if(readWrite == WRITE) { + StepDir_moveTo(motor, *value); + } + break; + case 1: + // Actual position + if(readWrite == READ) { + *value = StepDir_getActualPosition(motor); + } else if(readWrite == WRITE) { + StepDir_setActualPosition(motor, *value); + } + break; + case 2: + // Target speed + if(readWrite == READ) { + *value = StepDir_getTargetVelocity(motor); + } else if(readWrite == WRITE) { + StepDir_rotate(motor, *value); + } + break; + case 3: + // Actual speed + if(readWrite == READ) { + *value = StepDir_getActualVelocity(motor); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 4: + // Maximum speed + if(readWrite == READ) { + *value = StepDir_getVelocityMax(motor); + } else if(readWrite == WRITE) { + StepDir_setVelocityMax(motor, abs(*value)); + } + break; + case 5: + // Maximum acceleration + if(readWrite == READ) { + *value = StepDir_getAcceleration(motor); + } else if(readWrite == WRITE) { + StepDir_setAcceleration(motor, *value); + } + break; + case 6: + // Maximum current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IRUN_MASK, TMC2209_IRUN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IRUN_MASK, TMC2209_IRUN_SHIFT, *value); + } + break; + case 7: + // Standby current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IHOLD_MASK, TMC2209_IHOLD_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_IHOLD_IRUN, TMC2209_IHOLD_MASK, TMC2209_IHOLD_SHIFT, *value); + } + break; + case 8: + // Position reached flag + if(readWrite == READ) { + *value = (StepDir_getStatus(motor) & STATUS_TARGET_REACHED)? 1:0; + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 9: + // VREF + if (readWrite == READ) { + *value = vref; + } else { + if ((uint32_t) *value < VREF_FULLSCALE) { + vref = *value; + Timer.setDuty(timerChannel, ((float)vref) / VREF_FULLSCALE); + } else { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 23: + // Speed threshold for high speed mode + if(readWrite == READ) { + buffer = thigh; + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + thigh = *value; + } + break; + case 28: + // Internal RSense + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_GCONF, TMC2209_INTERNAL_RSENSE_MASK, TMC2209_INTERNAL_RSENSE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_GCONF, TMC2209_INTERNAL_RSENSE_MASK, TMC2209_INTERNAL_RSENSE_SHIFT, *value); + } + break; + case 29: + // Measured Speed + if(readWrite == READ) { + buffer = (int32_t)(((int64_t)StepDir_getFrequency(motor) * (int64_t)122) / (int64_t)TMC2209_FIELD_READ(motorToIC(motor), TMC2209_TSTEP, TMC2209_TSTEP_MASK, TMC2209_TSTEP_SHIFT)); + *value = (abs(buffer) < 20) ? 0 : buffer; + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 50: // StepDir internal(0)/external(1) + if(readWrite == READ) { + *value = StepDir_getMode(motor); + } else if(readWrite == WRITE) { + StepDir_setMode(motor, *value); + } + break; + case 51: // StepDir interrupt frequency + if(readWrite == READ) { + *value = StepDir_getFrequency(motor); + } else if(readWrite == WRITE) { + StepDir_setFrequency(motor, *value); + } + break; + case 140: + // Microstep Resolution + if(readWrite == READ) { + *value = 256 >> TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_MRES_MASK, TMC2209_MRES_SHIFT); + } else if(readWrite == WRITE) { + switch(*value) + { + case 1: *value = 8; break; + case 2: *value = 7; break; + case 4: *value = 6; break; + case 8: *value = 5; break; + case 16: *value = 4; break; + case 32: *value = 3; break; + case 64: *value = 2; break; + case 128: *value = 1; break; + case 256: *value = 0; break; + default: *value = -1; break; + } + + if(*value != -1) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_MRES_MASK, TMC2209_MRES_SHIFT, *value); + } + else + { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 162: + // Chopper blank time + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TBL_MASK, TMC2209_TBL_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TBL_MASK, TMC2209_TBL_SHIFT, *value); + } + break; + case 165: + // Chopper hysteresis end / fast decay time + if(readWrite == READ) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HEND_MASK, TMC2209_HEND_SHIFT); + } + else + { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF); + *value = (tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) >> 4) & 0x07; + if(buffer & (1<<11)) + *value |= 1<<3; + } + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 166: + // Chopper hysteresis start / sine wave offset + if(readWrite == READ) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HSTRT_MASK, TMC2209_HSTRT_SHIFT); + } + else + { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF); + *value = (tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) >> 7) & 0x0F; + if(buffer & (1<<11)) + *value |= 1<<3; + } + } else if(readWrite == WRITE) { + if(tmc2209_readInt(motorToIC(motor), TMC2209_CHOPCONF) & (1<<14)) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HSTRT_MASK, TMC2209_HSTRT_SHIFT, *value); + } + else + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_HEND_MASK, TMC2209_HEND_SHIFT, *value); + } + } + break; + case 167: + // Chopper off time + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TOFF_MASK, TMC2209_TOFF_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_TOFF_MASK, TMC2209_TOFF_SHIFT, *value); + } + break; + case 168: + // smartEnergy current minimum (SEIMIN) + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEIMIN_MASK, TMC2209_SEIMIN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEIMIN_MASK, TMC2209_SEIMIN_SHIFT, *value); + } + break; + case 169: + // smartEnergy current down step + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEDN_MASK, TMC2209_SEDN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEDN_MASK, TMC2209_SEDN_SHIFT, *value); + } + break; + case 170: + // smartEnergy hysteresis + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMAX_MASK, TMC2209_SEMAX_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMAX_MASK, TMC2209_SEMAX_SHIFT, *value); + } + break; + case 171: + // smartEnergy current up step + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEUP_MASK, TMC2209_SEUP_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEUP_MASK, TMC2209_SEUP_SHIFT, *value); + } + break; + case 172: + // smartEnergy hysteresis start + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMIN_MASK, TMC2209_SEMIN_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_COOLCONF, TMC2209_SEMIN_MASK, TMC2209_SEMIN_SHIFT, *value); + } + break; + case 174: + // stallGuard2 threshold + if(readWrite == READ) { + *value = tmc2209_readInt(motorToIC(motor), TMC2209_SGTHRS); + } else if(readWrite == WRITE) { + tmc2209_writeInt(motorToIC(motor), TMC2209_SGTHRS, *value); + } + break; + case 179: + // VSense + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_VSENSE_MASK, TMC2209_VSENSE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_CHOPCONF, TMC2209_VSENSE_MASK, TMC2209_VSENSE_SHIFT, *value); + } + break; + case 180: + // smartEnergy actual current + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_DRVSTATUS, TMC2209_CS_ACTUAL_MASK, TMC2209_CS_ACTUAL_SHIFT); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + case 181: + // smartEnergy stall velocity + if(readWrite == READ) { + *value = StepDir_getStallGuardThreshold(motor); + } else if(readWrite == WRITE) { + // Store the threshold value in the internal StepDir generator + StepDir_setStallGuardThreshold(motor, *value); + + // Convert the value for the TCOOLTHRS register + // The IC only sends out Stallguard errors while TCOOLTHRS >= TSTEP >= TPWMTHRS + // The TSTEP value is measured. To prevent measurement inaccuracies hiding + // a stall signal, we decrease the needed velocity by roughly 12% before converting it. + *value -= (*value) >> 3; + if (*value) + { + *value = MIN(0x000FFFFF, (1<<24) / (*value)); + } + else + { + *value = 0x000FFFFF; + } + tmc2209_writeInt(motorToIC(motor), TMC2209_TCOOLTHRS, *value); + } + break; + case 182: + // smartEnergy threshold speed + if(readWrite == READ) { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_TCOOLTHRS); + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + tmc2209_writeInt(motorToIC(motor), TMC2209_TCOOLTHRS, *value); + } + break; + case 186: + // PWM threshold speed + if(readWrite == READ) { + buffer = tmc2209_readInt(motorToIC(motor), TMC2209_TPWMTHRS); + *value = MIN(0xFFFFF, (1<<24) / ((buffer) ? buffer : 1)); + } else if(readWrite == WRITE) { + *value = MIN(0xFFFFF, (1<<24) / ((*value) ? *value : 1)); + tmc2209_writeInt(motorToIC(motor), TMC2209_TPWMTHRS, *value); + } + break; + case 187: + // PWM gradient + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_GRAD_MASK, TMC2209_PWM_GRAD_SHIFT); + } else if(readWrite == WRITE) { + // Set gradient + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_GRAD_MASK, TMC2209_PWM_GRAD_SHIFT, *value); + + // Enable/disable stealthChop accordingly + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_GCONF, TMC2209_EN_SPREADCYCLE_MASK, TMC2209_EN_SPREADCYCLE_SHIFT, (*value > 0) ? 0 : 1); + } + break; + case 191: + // PWM frequency + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_FREQ_MASK, TMC2209_PWM_FREQ_SHIFT); + } else if(readWrite == WRITE) { + if(*value >= 0 && *value < 4) + { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_FREQ_MASK, TMC2209_PWM_FREQ_SHIFT, *value); + } + else + { + errors |= TMC_ERROR_VALUE; + } + } + break; + case 192: + // PWM autoscale + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_AUTOSCALE_MASK, TMC2209_PWM_AUTOSCALE_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_PWM_AUTOSCALE_MASK, TMC2209_PWM_AUTOSCALE_SHIFT, (*value)? 1:0); + } + break; + case 204: + // Freewheeling mode + if(readWrite == READ) { + *value = TMC2209_FIELD_READ(motorToIC(motor), TMC2209_PWMCONF, TMC2209_FREEWHEEL_MASK, TMC2209_FREEWHEEL_SHIFT); + } else if(readWrite == WRITE) { + TMC2209_FIELD_UPDATE(motorToIC(motor), TMC2209_PWMCONF, TMC2209_FREEWHEEL_MASK, TMC2209_FREEWHEEL_SHIFT, *value); + } + break; + case 206: + // Load value + if(readWrite == READ) { + *value = tmc2209_readInt(motorToIC(motor), TMC2209_SG_RESULT); + } else if(readWrite == WRITE) { + errors |= TMC_ERROR_TYPE; + } + break; + default: + errors |= TMC_ERROR_TYPE; + break; + } + + return errors; +} + +static uint32_t SAP(uint8_t type, uint8_t motor, int32_t value) +{ + return handleParameter(WRITE, motor, type, &value); +} + +static uint32_t GAP(uint8_t type, uint8_t motor, int32_t *value) +{ + return handleParameter(READ, motor, type, value); +} + +static void checkErrors(uint32_t tick) +{ + UNUSED(tick); + Evalboards.ch2.errors = 0; +} + +static uint32_t userFunction(uint8_t type, uint8_t motor, int32_t *value) +{ + uint32_t errors = 0; + uint8_t state; + IOPinTypeDef *pin; + + switch(type) + { + case 0: // Read StepDir status bits + *value = StepDir_getStatus(motor); + break; + case 1: + tmc2209_set_slave(motorToIC(motor), (*value) & 0xFF); + break; + case 2: + *value = tmc2209_get_slave(motorToIC(motor)); + break; + case 3: + *value = Timer.getDuty(timerChannel) * 100 / TIMER_MAX; + break; + case 4: + Timer.setDuty(timerChannel, ((float)*value) / 100); + break; + case 5: // Set pin state + state = (*value) & 0x03; + pin = Pins.ENN; + switch(motor) { + case 0: + pin = Pins.ENN; + break; + case 1: + pin = Pins.SPREAD; + break; + case 2: + pin = Pins.MS1_AD0; + break; + case 3: + pin = Pins.MS2_AD1; + break; + case 4: + pin = Pins.UC_PWM; + break; + case 5: + pin = Pins.STDBY; + break; + } + HAL.IOs->config->setToState(pin, state); + break; + case 6: // Get pin state + pin = Pins.ENN; + switch(motor) { + case 0: + pin = Pins.ENN; + break; + case 1: + pin = Pins.SPREAD; + break; + case 2: + pin = Pins.MS1_AD0; + break; + case 3: + pin = Pins.MS2_AD1; + break; + case 4: + pin = Pins.UC_PWM; + break; + case 5: + pin = Pins.STDBY; + break; + } + *value = (uint32_t) HAL.IOs->config->getState(pin); + break; + default: + errors |= TMC_ERROR_TYPE; + break; + } + + return errors; +} + +static void deInit(void) +{ + enableDriver(DRIVER_DISABLE); + HAL.IOs->config->reset(Pins.ENN); + HAL.IOs->config->reset(Pins.SPREAD); + HAL.IOs->config->reset(Pins.STEP); + HAL.IOs->config->reset(Pins.DIR); + HAL.IOs->config->reset(Pins.MS1_AD0); + HAL.IOs->config->reset(Pins.MS2_AD1); + HAL.IOs->config->reset(Pins.DIAG); + HAL.IOs->config->reset(Pins.INDEX); + HAL.IOs->config->reset(Pins.STDBY); + HAL.IOs->config->reset(Pins.UC_PWM); + + StepDir_deInit(); + Timer.deInit(); +} + +static uint8_t reset() +{ + StepDir_init(STEPDIR_PRECISION); + StepDir_setPins(0, Pins.STEP, Pins.DIR, Pins.DIAG); + + return tmc2209_reset(&TMC2209); +} + +static uint8_t restore() +{ + return tmc2209_restore(&TMC2209); +} + +static void enableDriver(DriverState state) +{ + if(state == DRIVER_USE_GLOBAL_ENABLE) + state = Evalboards.driverEnable; + + if(state == DRIVER_DISABLE) + HAL.IOs->config->setHigh(Pins.ENN); + else if((state == DRIVER_ENABLE) && (Evalboards.driverEnable == DRIVER_ENABLE)) + HAL.IOs->config->setLow(Pins.ENN); +} + +static void periodicJob(uint32_t tick) +{ + tmc2209_periodicJob(&TMC2209, tick); + StepDir_periodicJob(0); +} + +void TMC2209_init(void) +{ + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + timerChannel = TIMER_CHANNEL_3; + +#elif defined(LandungsbrueckeV3) + timerChannel = TIMER_CHANNEL_4; +#endif + tmc_fillCRC8Table(0x07, true, 1); + thigh = 0; + + Pins.ENN = &HAL.IOs->pins->DIO0; + Pins.SPREAD = &HAL.IOs->pins->DIO8; + Pins.STEP = &HAL.IOs->pins->DIO6; + Pins.DIR = &HAL.IOs->pins->DIO7; + Pins.MS1_AD0 = &HAL.IOs->pins->DIO3; + Pins.MS2_AD1 = &HAL.IOs->pins->DIO4; + Pins.DIAG = &HAL.IOs->pins->DIO1; + Pins.INDEX = &HAL.IOs->pins->DIO2; + Pins.UC_PWM = &HAL.IOs->pins->DIO9; + Pins.STDBY = &HAL.IOs->pins->DIO0; + + HAL.IOs->config->toOutput(Pins.ENN); + HAL.IOs->config->toOutput(Pins.SPREAD); + HAL.IOs->config->toOutput(Pins.STEP); + HAL.IOs->config->toOutput(Pins.DIR); + HAL.IOs->config->toOutput(Pins.MS1_AD0); + HAL.IOs->config->toOutput(Pins.MS2_AD1); + HAL.IOs->config->toInput(Pins.DIAG); + HAL.IOs->config->toInput(Pins.INDEX); + + HAL.IOs->config->setLow(Pins.MS1_AD0); + HAL.IOs->config->setLow(Pins.MS2_AD1); + + TMC2209_UARTChannel = HAL.UART; + TMC2209_UARTChannel->pinout = UART_PINS_2; + TMC2209_UARTChannel->rxtx.init(); + + TMC2209_config = Evalboards.ch2.config; + + Evalboards.ch2.config->reset = reset; + Evalboards.ch2.config->restore = restore; + + Evalboards.ch2.rotate = rotate; + Evalboards.ch2.right = right; + Evalboards.ch2.left = left; + Evalboards.ch2.stop = stop; + Evalboards.ch2.GAP = GAP; + Evalboards.ch2.SAP = SAP; + Evalboards.ch2.moveTo = moveTo; + Evalboards.ch2.moveBy = moveBy; + Evalboards.ch2.writeRegister = tmc2209_writeRegister; + Evalboards.ch2.readRegister = tmc2209_readRegister; + Evalboards.ch2.userFunction = userFunction; + Evalboards.ch2.enableDriver = enableDriver; + Evalboards.ch2.checkErrors = checkErrors; + Evalboards.ch2.numberOfMotors = MOTORS; + Evalboards.ch2.VMMin = VM_MIN; + Evalboards.ch2.VMMax = VM_MAX; + Evalboards.ch2.deInit = deInit; + Evalboards.ch2.periodicJob = periodicJob; + + tmc2209_init(&TMC2209, 0, 0, TMC2209_config, &tmc2209_defaultRegisterResetState[0]); + + StepDir_init(STEPDIR_PRECISION); + StepDir_setPins(0, Pins.STEP, Pins.DIR, Pins.DIAG); + StepDir_setVelocityMax(0, 51200); + StepDir_setAcceleration(0, 51200); + + HAL.IOs->config->toOutput(Pins.UC_PWM); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + Pins.UC_PWM->configuration.GPIO_Mode = GPIO_Mode_AF4; +#elif defined(LandungsbrueckeV3) + Pins.UC_PWM->configuration.GPIO_Mode = GPIO_MODE_AF; + gpio_af_set(Pins.UC_PWM->port, GPIO_AF_1, Pins.UC_PWM->bitWeight); + +#endif + + vref = 2000; + HAL.IOs->config->set(Pins.UC_PWM); + Timer.init(); + Timer.setDuty(timerChannel, ((float)vref) / VREF_FULLSCALE); + + enableDriver(DRIVER_ENABLE); +}; diff --git a/TMC2209/lib/tmc/boards/TMCDriver.c b/TMC2209/lib/tmc/boards/TMCDriver.c new file mode 100644 index 0000000..d46ac91 --- /dev/null +++ b/TMC2209/lib/tmc/boards/TMCDriver.c @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCDriver.h" + +EvalBoardDriverTypeDef TMCDriver = +{ + .config = + { + .state = CONFIG_READY, + .configIndex = 0, + .shadowRegister = { 0 } + } +}; + +void tmcdriver_init() +{ + Evalboards.ch2.config = &TMCDriver.config; + Evalboards.ch2.config->state = CONFIG_READY; + Evalboards.ch2.config->configIndex = 0; + + // A value of 0 indicates the Evalboard not connecting the VM line, + // resulting in skipped global minimum voltage checks. + // A negative value indicates no board being connected, which skips the + // minimum voltage check for that channel + Evalboards.ch2.VMMin = -1; + Evalboards.ch2.VMMax = s32_MAX; + + Evalboards.ch2.numberOfMotors = 0; + Evalboards.ch2.errors = 0; + + Evalboards.ch2.config->channel = CHANNEL_2; + + board_setDummyFunctions(&Evalboards.ch2); +} diff --git a/TMC2209/lib/tmc/boards/TMCDriver.h b/TMC2209/lib/tmc/boards/TMCDriver.h new file mode 100644 index 0000000..b837ea4 --- /dev/null +++ b/TMC2209/lib/tmc/boards/TMCDriver.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCDRIVER_H_ +#define TMCDRIVER_H_ + + #include "Board.h" + + typedef struct + { + ConfigurationTypeDef config; + } EvalBoardDriverTypeDef; + + extern EvalBoardDriverTypeDef TMCDriver; + + void tmcdriver_init(); + +#endif /* TMCDRIVER_H_ */ diff --git a/TMC2209/lib/tmc/boards/TMCMotionController.c b/TMC2209/lib/tmc/boards/TMCMotionController.c new file mode 100644 index 0000000..fca7bce --- /dev/null +++ b/TMC2209/lib/tmc/boards/TMCMotionController.c @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCMotionController.h" + +EvalBoardMotionControllerTypeDef TMCMotionController = +{ + .config = + { + .state = CONFIG_READY, + .configIndex = 0, + .shadowRegister = { 0 } + } +}; + +void tmcmotioncontroller_init() +{ + Evalboards.ch1.config = &TMCMotionController.config; + Evalboards.ch1.config->state = CONFIG_READY; + Evalboards.ch1.config->configIndex = 0; + + // A value of 0 indicates the Evalboard not connecting the VM line, + // resulting in skipped global minimum voltage checks. + // A negative value indicates no board being connected, which skips the + // minimum voltage check for that channel + Evalboards.ch1.VMMin = -1; + Evalboards.ch1.VMMax = s32_MAX; + + Evalboards.ch1.numberOfMotors = 0; + Evalboards.ch1.errors = 0; + + Evalboards.ch1.config->channel = CHANNEL_1; + + board_setDummyFunctions(&Evalboards.ch1); +} diff --git a/TMC2209/lib/tmc/boards/TMCMotionController.h b/TMC2209/lib/tmc/boards/TMCMotionController.h new file mode 100644 index 0000000..a6df4d2 --- /dev/null +++ b/TMC2209/lib/tmc/boards/TMCMotionController.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCMOTIONCONTROLLER_H_ +#define TMCMOTIONCONTROLLER_H_ + + #include "Board.h" + + typedef struct + { + ConfigurationTypeDef config; + } EvalBoardMotionControllerTypeDef; + + extern EvalBoardMotionControllerTypeDef TMCMotionController; + + void tmcmotioncontroller_init(); + +#endif /* TMCMOTIONCONTROLLER_H_ */ diff --git a/TMC2209/lib/tmc/hal/ADCs.h b/TMC2209/lib/tmc/hal/ADCs.h new file mode 100644 index 0000000..3feb9c4 --- /dev/null +++ b/TMC2209/lib/tmc/hal/ADCs.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef ADC_H +#define ADC_H + +#include + +#define N_O_ADC_CHANNELS 7 + +static volatile uint16_t ADCValue[N_O_ADC_CHANNELS]; + +typedef struct +{ + volatile uint16_t *AIN0; + volatile uint16_t *AIN1; + volatile uint16_t *AIN2; + volatile uint16_t *DIO4; + volatile uint16_t *DIO5; + volatile uint16_t *VM; + volatile uint16_t *AIN_EXT; // Only LB_V3 + void (*init)(); + void (*deInit)(); +} ADCTypeDef; + +extern ADCTypeDef ADCs; + +#endif /* ADC_H */ diff --git a/TMC2209/lib/tmc/hal/HAL.h b/TMC2209/lib/tmc/hal/HAL.h new file mode 100644 index 0000000..d7e7100 --- /dev/null +++ b/TMC2209/lib/tmc/hal/HAL.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _HAL_H_ +#define _HAL_H_ + +#include "derivative.h" +#include "IOs.h" +#include "IOMap.h" +#include "SPI.h" +#include "ADCs.h" +#include "USB.h" +#include "LEDs.h" +#include "RS232.h" +#include "WLAN.h" +#include "Timer.h" +#include "SysTick.h" +#include "UART.h" + +typedef struct +{ + IOsTypeDef *config; + IOPinMapTypeDef *pins; +} IOsFunctionsTypeDef; + +typedef struct +{ + void (*init) (void); + void (*reset) (uint8_t ResetPeripherals); + void (*NVIC_DeInit)(void); + const IOsFunctionsTypeDef *IOs; + SPITypeDef *SPI; + RXTXTypeDef *USB; + LEDsTypeDef *LEDs; + ADCTypeDef *ADCs; + RXTXTypeDef *RS232; + RXTXTypeDef *WLAN; + TimerTypeDef *Timer; + UART_Config *UART; +} HALTypeDef; + +extern const HALTypeDef HAL; + +extern uint8_t hwid; + +#endif /* _HAL_H_ */ diff --git a/TMC2209/lib/tmc/hal/IOMap.h b/TMC2209/lib/tmc/hal/IOMap.h new file mode 100644 index 0000000..d5c806b --- /dev/null +++ b/TMC2209/lib/tmc/hal/IOMap.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _IO_PIN_MAP_H_ +#define _IO_PIN_MAP_H_ + +#include "IOs.h" + +typedef struct +{ + void (*init) (void); + + IOPinTypeDef **pins; // Map Pin ID <=> Pin + + IOPinTypeDef ID_CLK; + IOPinTypeDef ID_CH0; + IOPinTypeDef ID_CH1; + + IOPinTypeDef DIO0; + IOPinTypeDef DIO1; + IOPinTypeDef DIO2; + IOPinTypeDef DIO3; + IOPinTypeDef DIO4; + IOPinTypeDef DIO5; + IOPinTypeDef DIO6; + IOPinTypeDef DIO7; + IOPinTypeDef DIO8; + IOPinTypeDef DIO9; + IOPinTypeDef DIO10; + IOPinTypeDef DIO11; + IOPinTypeDef CLK16; + IOPinTypeDef SPI2_CSN0; + IOPinTypeDef SPI2_CSN1; + IOPinTypeDef SPI2_CSN2; + IOPinTypeDef SPI2_SCK; + IOPinTypeDef SPI2_SDO; + IOPinTypeDef SPI2_SDI; + + IOPinTypeDef SPI1_CSN; + IOPinTypeDef SPI1_SCK; + IOPinTypeDef SPI1_SDI; + IOPinTypeDef SPI1_SDO; + + IOPinTypeDef DIO12; + IOPinTypeDef DIO13; + IOPinTypeDef DIO14; + IOPinTypeDef DIO15; + IOPinTypeDef DIO16; + IOPinTypeDef DIO17; + IOPinTypeDef DIO18; + IOPinTypeDef DIO19; + + IOPinTypeDef RS232_TX; + IOPinTypeDef RS232_RX; + + IOPinTypeDef USB_V_BUS; + IOPinTypeDef USB_V_DM; + IOPinTypeDef USB_V_DP; + + IOPinTypeDef LED_STAT; + IOPinTypeDef LED_ERROR; + + IOPinTypeDef EEPROM_SCK; + IOPinTypeDef EEPROM_SI; + IOPinTypeDef EEPROM_SO; + IOPinTypeDef EEPROM_NCS; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + IOPinTypeDef WIRELESS_TX; + IOPinTypeDef WIRELESS_RX; + IOPinTypeDef WIRELESS_NRST; + IOPinTypeDef MIXED0; + IOPinTypeDef MIXED1; + IOPinTypeDef MIXED2; + IOPinTypeDef MIXED3; + IOPinTypeDef MIXED4; + IOPinTypeDef MIXED5; + IOPinTypeDef MIXED6; + IOPinTypeDef ID_HW_0; + IOPinTypeDef ID_HW_1; + IOPinTypeDef ID_HW_2; + IOPinTypeDef EXTIO_2; + IOPinTypeDef EXTIO_3; + IOPinTypeDef EXTIO_4; + IOPinTypeDef EXTIO_5; + IOPinTypeDef EXTIO_6; + IOPinTypeDef EXTIO_7; +#endif + +#if defined(LandungsbrueckeV3) + IOPinTypeDef DIO10_PWM_WL; + IOPinTypeDef DIO10_UART_TX; + IOPinTypeDef DIO11_PWM_WH; + IOPinTypeDef DIO11_UART_RX; + IOPinTypeDef SW_UART_PWM; + IOPinTypeDef EXT0; + IOPinTypeDef EXT1; + IOPinTypeDef EXT2; + IOPinTypeDef EXT3; + IOPinTypeDef EXT4; + IOPinTypeDef ADC_VM; + IOPinTypeDef AIN0; + IOPinTypeDef AIN1; + IOPinTypeDef AIN2; + IOPinTypeDef AIN_EXT; + IOPinTypeDef WIFI_EN; + IOPinTypeDef WIFI_RST; + IOPinTypeDef WIFI_TX; + IOPinTypeDef WIFI_RX; + IOPinTypeDef BUTTON; +#endif + + IOPinTypeDef DUMMY; +} IOPinMapTypeDef; + +extern IOPinMapTypeDef IOMap; + +#endif /* _IO_PIN_MAP_H_ */ diff --git a/TMC2209/lib/tmc/hal/IOs.h b/TMC2209/lib/tmc/hal/IOs.h new file mode 100644 index 0000000..00d6e58 --- /dev/null +++ b/TMC2209/lib/tmc/hal/IOs.h @@ -0,0 +1,164 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _IO_H_ +#define _IO_H_ + +// #include "derivative.h" + +typedef enum { // Give bits explicitly, because IDE relies on it. + IOS_LOW = 0b00, + IOS_HIGH = 0b01, + IOS_OPEN = 0b10, + IOS_NOCHANGE = 0b11 +} IO_States; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // use ST like configuration structures also for Landungsbruecke + + typedef enum + { + GPIO_Mode_AN = 0x00, /*!< GPIO Analog Mode, Pin disabled */ + GPIO_Mode_AF1 = 0x01, /*!< GPIO Alternate function Mode GPIO*/ + GPIO_Mode_AF2 = 0x02, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF3 = 0x03, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF4 = 0x04, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF5 = 0x05, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF6 = 0x06, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_AF7 = 0x07, /*!< GPIO Alternate function Mode*/ + GPIO_Mode_IN = 0x08, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x09 /*!< GPIO Output Mode */ + } GPIOMode_TypeDef; + + typedef enum + { + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 + } GPIOOType_TypeDef; + + typedef enum + { + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 + } GPIOPuPd_TypeDef; + + typedef enum + { + GPIO_Speed_2MHz = 0x00, /*!< Low speed */ + GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ + GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ + GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + } GPIOSpeed_TypeDef; + + #include "hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h" +#elif defined(LandungsbrueckeV3) +// typedef enum +// { +// GPIO_MODE_INPUT = 0x00, /*!< GPIO Input Mode */ +// GPIO_MODE_OUTPUT = 0x01, /*!< GPIO Output Mode */ +// GPIO_MODE_AF = 0x02, /*!< GPIO Alternate function Mode*/ +// GPIO_MODE_ANALOG = 0x03, /*!< GPIO Analog Mode*/ +// } GPIOMode_TypeDef; +// +// typedef enum +// { +// GPIO_OTYPE_PP = 0x00, +// GPIO_OTYPE_OD = 0x01 +// } GPIOOType_TypeDef; +// +// typedef enum +// { +// GPIO_PUPD_NONE = 0x00, +// GPIO_PUPD_PULLUP = 0x01, +// GPIO_PUPD_PULLDOWN = 0x02 +// } GPIOPuPd_TypeDef; +// +// typedef enum +// { +// GPIO_OSPEED_2MHZ = 0x00, /*!< Low speed */ +// GPIO_OSPEED_25MHZ = 0x01, /*!< Medium speed */ +// GPIO_OSPEED_50MHZ = 0x02, /*!< Fast speed */ +// GPIO_OSPEED_MAX = 0x03 /*!< GPIO very high output speed, max speed more than 50MHz */ +// } GPIOSpeed_TypeDef; + typedef uint32_t GPIOMode_TypeDef; + typedef uint32_t GPIOOType_TypeDef; + typedef uint32_t GPIOPuPd_TypeDef; + typedef uint32_t GPIOSpeed_TypeDef; + + +#endif + + +enum IOsHighLevelFunctions { IO_DEFAULT, IO_DI, IO_AI, IO_DO, IO_PWM, IO_SD, IO_CLK16, IO_SPI }; + +typedef struct +{ + const uint8_t DEFAULT; + const uint8_t DI; + const uint8_t AI; + const uint8_t DO; + const uint8_t PWM; + const uint8_t SD; + const uint8_t CLK16; + const uint8_t SPI; +} IOsHighLevelFunctionTypeDef; + +typedef struct +{ + GPIOMode_TypeDef GPIO_Mode; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOOType_TypeDef GPIO_OType; + GPIOPuPd_TypeDef GPIO_PuPd; +} IOPinInitTypeDef; + +typedef struct +{ + #if defined(LandungsbrueckeV3) + uint32_t port; + volatile uint32_t *setBitRegister; + volatile uint32_t *resetBitRegister; + #elif defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + PORT_MemMapPtr portBase; + GPIO_MemMapPtr GPIOBase; + volatile uint32_t *setBitRegister; + volatile uint32_t *resetBitRegister; + #endif + uint32_t bitWeight; + unsigned char bit; + IOPinInitTypeDef configuration; + IOPinInitTypeDef resetConfiguration; + enum IOsHighLevelFunctions highLevelFunction; + IO_States state; +} IOPinTypeDef; + +typedef struct +{ + void (*set)(IOPinTypeDef *pin); + void (*copy)(IOPinInitTypeDef *from, IOPinTypeDef*to); + void (*reset)(IOPinTypeDef *pin); + void (*toOutput)(IOPinTypeDef *pin); + void (*toInput)(IOPinTypeDef *pin); + + void (*setHigh)(IOPinTypeDef *pin); + void (*setLow)(IOPinTypeDef *pin); + void (*setToState)(IOPinTypeDef *pin, IO_States state); + IO_States (*getState)(IOPinTypeDef *pin); + unsigned char (*isHigh)(IOPinTypeDef *pin); + void (*init)(void); + IOsHighLevelFunctionTypeDef HIGH_LEVEL_FUNCTIONS; +} IOsTypeDef; + +extern IOsTypeDef IOs; + +// A bit weight of 0 is used to indicate a nonexistent pin +#define DUMMY_BITWEIGHT 0 +#define IS_DUMMY_PIN(pin) (pin->bitWeight == DUMMY_BITWEIGHT) + +#endif /* _IO_H_ */ diff --git a/TMC2209/lib/tmc/hal/LEDs.h b/TMC2209/lib/tmc/hal/LEDs.h new file mode 100644 index 0000000..87dc536 --- /dev/null +++ b/TMC2209/lib/tmc/hal/LEDs.h @@ -0,0 +1,49 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef LEDS_H_ +#define LEDS_H_ + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define LED_ON() *HAL.IOs->pins->LED_STAT.resetBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_OFF() *HAL.IOs->pins->LED_STAT.setBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_TOGGLE() HAL.IOs->pins->LED_STAT.GPIOBase->PTOR ^= GPIO_PTOR_PTTO(HAL.IOs->pins->LED_STAT.bitWeight) + + #define LED_ERROR_ON() *HAL.IOs->pins->LED_ERROR.resetBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_OFF() *HAL.IOs->pins->LED_ERROR.setBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_TOGGLE() HAL.IOs->pins->LED_ERROR.GPIOBase->PTOR ^= GPIO_PTOR_PTTO(HAL.IOs->pins->LED_ERROR.bitWeight) +#elif defined(LandungsbrueckeV3) + #define LED_ON() *HAL.IOs->pins->LED_STAT.resetBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_OFF() *HAL.IOs->pins->LED_STAT.setBitRegister = HAL.IOs->pins->LED_STAT.bitWeight + #define LED_TOGGLE() GPIO_TG(HAL.IOs->pins->LED_STAT.port) = HAL.IOs->pins->LED_STAT.bitWeight + + #define LED_ERROR_ON() *HAL.IOs->pins->LED_ERROR.resetBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_OFF() *HAL.IOs->pins->LED_ERROR.setBitRegister = HAL.IOs->pins->LED_ERROR.bitWeight + #define LED_ERROR_TOGGLE() GPIO_TG(HAL.IOs->pins->LED_ERROR.port) = HAL.IOs->pins->LED_ERROR.bitWeight +#endif + + #include "IOs.h" + + typedef struct + { + void (*on)(void); + void (*off)(void); + void (*toggle)(void); + } LEDTypeDef; + + typedef struct + { + void (*init)(void); + LEDTypeDef stat; + LEDTypeDef error; + } LEDsTypeDef; + + extern LEDsTypeDef LEDs; + +#endif /* LEDS_H_ */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c new file mode 100644 index 0000000..52a35ee --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.c @@ -0,0 +1,295 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.c +** Project : FS_TC_Test +** Processor : MK20DN512VLL10 +** Component : MK20DN512LL10 +** Version : Component 01.000, Driver 01.04, CPU db: 3.00.000 +** Datasheet : K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Compiler : GNU C Compiler +** Date/Time : 2014-12-22, 13:39, # CodeGen: 7 +** Abstract : +** +** Settings : +** +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file Cpu.c +** @version 01.04 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +/* MODULE Cpu. */ + +/* {Default RTOS Adapter} No RTOS includes */ + +#include "hal/derivative.h" +#include "Cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Global variables */ +volatile uint8 SR_reg; /* Current value of the FAULTMASK register */ +volatile uint8 SR_lock = 0x00U; /* Lock */ + +void LowLevelInit(void); +void InitClocks(void); + + +CpuTypeDef Cpu = +{ + .initClocks = InitClocks, + .initLowLevel = LowLevelInit, +}; + +/* +** =================================================================== +** Method : Cpu_SetBASEPRI (component MK20DN512LL10) +** +** Description : +** This method sets the BASEPRI core register. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void Cpu_SetBASEPRI(uint32 Level); + +/* +** =================================================================== +** Method : Cpu_INT_NMIInterrupt (component MK20DN512LL10) +** +** Description : +** This ISR services the Non Maskable Interrupt interrupt. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void __attribute__ ((interrupt)) Cpu_INT_NMIInterrupt(void) +{ + +} + +/* +** =================================================================== +** Method : Cpu_Cpu_Interrupt (component MK20DN512LL10) +** +** Description : +** This ISR services an unused interrupt/exception vector. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void __attribute__ ((interrupt)) Cpu_Interrupt(void) +{ + /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */ + PE_DEBUGHALT(); +} + + +/***************************************************************//** + \fn InitClocks(void) + \brief Initialize the clock PLL + + This function inializes the PLL to 96MHz (with 16MHz crystal + freqeuncy) and then switches to PLL clock. + So the following frequencies are used: + Core: 96MHz + Bus: 48MHz + FlexBus: 48MHz + Flash: 24MHz + + This routine has been generated by ProcessorExpert and cleaned + up manually. +********************************************************************/ +void InitClocks(void) +{ + //Turn on clocking for all ports to enable pin routing + SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK + | SIM_SCGC5_PORTB_MASK + | SIM_SCGC5_PORTC_MASK + | SIM_SCGC5_PORTD_MASK + | SIM_SCGC5_PORTE_MASK ); + + //PLL already selected by bootloader? => exit + if((MCG_S & 0x0C)==0x0C) return; + + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | + SIM_CLKDIV1_OUTDIV2(0x01) | + SIM_CLKDIV1_OUTDIV3(0x03) | + SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ + + if((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) + { + /* PMC_REGSC: ACKISO=1 */ + PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ + } + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | + SIM_CLKDIV1_OUTDIV2(0x01) | + SIM_CLKDIV1_OUTDIV3(0x01) | + SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */ + /* SIM_SOPT2: PLLFLLSEL=1 */ + SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK|SIM_SOPT2_CLKOUTSEL(6); /* Select PLL as a clock source for various peripherals */ + /* SIM_SOPT1: OSC32KSEL=3 */ + SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ + /* Switch to FBE Mode */ + /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ + MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK); + /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC_CR = OSC_CR_ERCLKEN_MASK; + /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); + /* MCG_C4: DMX32=0,DRST_DRS=0 */ + MCG_C4 &= (uint8)~(uint8)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); + /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ + MCG_C5 = MCG_C5_PRDIV0(0x03); + /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ + MCG_C6 = MCG_C6_VDIV0(0x00); + while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U); /* Check that the oscillator is running */ + while((MCG_S & MCG_S_IREFST_MASK) != 0x00U); /* Check that the source of the FLL reference clock is the external reference clock. */ + while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */ + /* Switch to PBE Mode */ + /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ + MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); + while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */ + while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ + /* Switch to PEE Mode */ + /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); + while((MCG_S & 0x0CU) != 0x0CU); /* Wait until output of the PLL is selected */ +} + +/* +** =================================================================== +** Method : Cpu_SetBASEPRI (component MK20DN512LL10) +** +** Description : +** This method sets the BASEPRI core register. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +/*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */ +#ifdef _lint + #define Cpu_SetBASEPRI(Level) /* empty */ +#else +void Cpu_SetBASEPRI(uint32 Level) { + __asm ("msr basepri, %[input]"::[input] "r" (Level):); +} +#endif +/*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + + + +/***************************************************************//** + \fn LowLevelInit(void) + \brief Low level initialization of the MCU + + This function does some low level initialization of the MCU. + Generated by ProcessorExpert and then cleaned up manually. +********************************************************************/ +void LowLevelInit(void) +{ + /* Initialization of the RCM module */ //***TEST_OK: Kann je nach Beschaltung des Reset-Pins zum Absturz führen + /* RCM_RPFW: RSTFLTSEL=0 */ + RCM_RPFW &= (uint8)~(uint8)(RCM_RPFW_RSTFLTSEL(0x1F)); + /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */ + RCM_RPFC &= (uint8)~(uint8)( + RCM_RPFC_RSTFLTSS_MASK | + RCM_RPFC_RSTFLTSRW(0x03) + ); + /* Initialization of the FTFL_FlashConfig module */ + /* SIM_SCGC7: MPU=1 */ + SIM_SCGC7 |= SIM_SCGC7_MPU_MASK; + /* Initialization of the MPU module */ + + //Turn off MPU (important e.g. for the USB stack to work properly) + /* MPU_CESR: SPERR=0,VLD=0 */ + MPU_CESR &= (uint32)~(uint32)((MPU_CESR_SPERR(0x1F) | MPU_CESR_VLD_MASK)); + + /* Initialization of the PMC module */ + /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */ + PMC_LVDSC1 = (uint8)((PMC_LVDSC1 & (uint8)~(uint8)( + PMC_LVDSC1_LVDIE_MASK | + PMC_LVDSC1_LVDV(0x03) + )) | (uint8)( + PMC_LVDSC1_LVDACK_MASK | + PMC_LVDSC1_LVDRE_MASK + )); + /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */ + PMC_LVDSC2 = (uint8)((PMC_LVDSC2 & (uint8)~(uint8)( + PMC_LVDSC2_LVWIE_MASK | + PMC_LVDSC2_LVWV(0x03) + )) | (uint8)( + PMC_LVDSC2_LVWACK_MASK + )); + /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */ + PMC_REGSC &= (uint8)~(uint8)( + PMC_REGSC_BGEN_MASK | + PMC_REGSC_ACKISO_MASK | + PMC_REGSC_BGBE_MASK + ); + /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */ + SMC_PMPROT = 0x00U; /* Setup Power mode protection register */ + + //Interrupt priority base setting + Cpu_SetBASEPRI(0); +} + + + + +/* END Cpu. */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h new file mode 100644 index 0000000..0331eb2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/Cpu.h @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.h +** Project : FS_TC_Test +** Processor : MK20DN512VLL10 +** Component : MK20DN512LL10 +** Version : Component 01.000, Driver 01.04, CPU db: 3.00.000 +** Datasheet : K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Compiler : GNU C Compiler +** Date/Time : 2014-12-17, 14:57, # CodeGen: 6 +** Abstract : +** +** Settings : +** +** Contents : +** No public methods +** +** (c) Freescale Semiconductor, Inc. +** 2004 All Rights Reserved +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file Cpu.h +** @version 01.04 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +#ifndef __Cpu_H +#define __Cpu_H + +/* MODULE Cpu. */ +/*Include shared modules, which are used for whole project*/ +#include "USB_CDC/PE_Types.h" +#include "USB_CDC/PE_Error.h" +#include "USB_CDC/PE_Const.h" +#include "hal/derivative.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Active configuration define symbol */ +#define PEcfg_FLASH 1U + +/* Methods configuration constants - generated for all enabled component's methods */ + +/* Events configuration constants - generated for all enabled component's events */ +#define Cpu_OnNMIINT_EVENT_ENABLED + +#define CPU_BUS_CLK_HZ 48000000U /* Initial value of the bus clock frequency in Hz */ +#define CPU_CORE_CLK_HZ 96000000U /* Initial value of the core/system clock frequency in Hz. */ + +#define CPU_CLOCK_CONFIG_NUMBER 0x01U /* Specifies number of defined clock configurations. */ + +#define CPU_BUS_CLK_HZ_CLOCK_CONFIG0 48000000U /* Value of the bus clock frequency in the clock configuration 0 in Hz. */ +#define CPU_CORE_CLK_HZ_CLOCK_CONFIG0 96000000U /* Value of the core/system clock frequency in the clock configuration 0 in Hz. */ + + +#define CPU_XTAL_CLK_HZ 16000000U /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ + +#define CPU_FAMILY_Kinetis /* Specification of the core type of the selected cpu */ +#define CPU_DERIVATIVE_MK20DN512LL10 /* Name of the selected cpu derivative */ +#define CPU_PARTNUM_MK20DN512VLL10 /* Part number of the selected cpu */ +#define CPU_LITTLE_ENDIAN /* The selected cpu uses little endian */ + + +/* CPU frequencies in clock configuration 0 */ +#define CPU_CLOCK_CONFIG_0 0x00U /* Clock configuration 0 identifier */ +#define CPU_CORE_CLK_HZ_CONFIG_0 96000000UL /* Core clock frequency in clock configuration 0 */ +#define CPU_BUS_CLK_HZ_CONFIG_0 48000000UL /* Bus clock frequency in clock configuration 0 */ +#define CPU_FLEXBUS_CLK_HZ_CONFIG_0 48000000UL /* Flexbus clock frequency in clock configuration 0 */ +#define CPU_FLASH_CLK_HZ_CONFIG_0 24000000UL /* FLASH clock frequency in clock configuration 0 */ +#define CPU_USB_CLK_HZ_CONFIG_0 0UL /* USB clock frequency in clock configuration 0 */ +#define CPU_PLL_FLL_CLK_HZ_CONFIG_0 96000000UL /* PLL/FLL clock frequency in clock configuration 0 */ +#define CPU_MCGIR_CLK_HZ_CONFIG_0 32768UL /* MCG internal reference clock frequency in clock configuration 0 */ +#define CPU_OSCER_CLK_HZ_CONFIG_0 16000000UL /* System OSC external reference clock frequency in clock configuration 0 */ +#define CPU_ERCLK32K_CLK_HZ_CONFIG_0 1000UL /* External reference clock 32k frequency in clock configuration 0 */ +#define CPU_MCGFF_CLK_HZ_CONFIG_0 31250UL /* MCG fixed frequency clock */ + + +typedef struct { + uint32 cpu_core_clk_hz; /* Core clock frequency in clock configuration */ + uint32 cpu_bus_clk_hz; /* Bus clock frequency in clock configuration */ + uint32 cpu_flexbus_clk_hz; /* Flexbus clock frequency in clock configuration */ + uint32 cpu_flash_clk_hz; /* FLASH clock frequency in clock configuration */ + uint32 cpu_usb_clk_hz; /* USB clock frequency in clock configuration */ + uint32 cpu_pll_fll_clk_hz; /* PLL/FLL clock frequency in clock configuration */ + uint32 cpu_mcgir_clk_hz; /* MCG internal reference clock frequency in clock configuration */ + uint32 cpu_oscer_clk_hz; /* System OSC external reference clock frequency in clock configuration */ + uint32 cpu_erclk32k_clk_hz; /* External reference clock 32k frequency in clock configuration */ + uint32 cpu_mcgff_clk_hz; /* MCG fixed frequency clock */ +} TCpuClockConfiguration; + +/* The array of clock frequencies in configured clock configurations */ +extern const TCpuClockConfiguration PE_CpuClockConfigurations[CPU_CLOCK_CONFIG_NUMBER]; + + /* Interrupt vector table type definition */ + typedef void (*const tIsrFunc)(void); + typedef struct { + void * __ptr; + tIsrFunc __fun[0x77]; + } tVectorTable; + + extern const tVectorTable __vect_table; + +/* Global variables */ +/*lint -esym(765,SR_reg) Disable MISRA rule (8.10) checking for symbols (SR_reg). The SR_reg is used in inline assembler. */ +extern volatile uint8 SR_reg; /* Current FAULTMASK register */ +/*lint -esym(765,SR_lock) Disable MISRA rule (8.10) checking for symbols (SR_lock). The SR_reg is used in inline assembler. */ +extern volatile uint8 SR_lock; + + +typedef struct +{ + void (*initClocks)(void); + void (*initLowLevel)(void); +} CpuTypeDef; + + +extern CpuTypeDef Cpu; + + +/* {Default RTOS Adapter} ISR function prototype */ +void __attribute__ ((interrupt)) Cpu_INT_NMIInterrupt(void); +/* +** =================================================================== +** Method : Cpu_INT_NMIInterrupt (component MK20DN512LL10) +** +** Description : +** This ISR services the Non Maskable Interrupt interrupt. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void __attribute__ ((interrupt)) Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Cpu_Interrupt (component MK20DN512LL10) +** +** Description : +** This ISR services an unused interrupt/exception vector. +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END Cpu. */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif +/* __Cpu_H */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h new file mode 100644 index 0000000..2887b0d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20D10.h @@ -0,0 +1,14458 @@ +//#include "typedefs.h" +/* +** ################################################################### +** Processors: MK20DN512VLK10 +** MK20DX256VLK10 +** MK20DN512VLL10 +** MK20DX256VLL10 +** MK20DN512VLQ10 +** MK20DX128VLQ10 +** MK20DX256VLQ10 +** MK20DN512VMB10 +** MK20DX256VMB10 +** MK20DN512VMC10 +** MK20DX256VMC10 +** MK20DN512VMD10 +** MK20DX256VMD10 +** MK20DX128VMD10 +** +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K20P144M100SF2V2RM Rev. 1, Jan 2012 +** Version: rev. 1.1, 2012-01-10 +** +** Abstract: +** This header file implements peripheral memory map for MK20D10 +** processor. +** +** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-09-15) +** Initial version +** - rev. 1.1 (2012-01-10) +** Registers updated according to the new reference manual revision - Rev. 1, Jan 2012 +** +** ################################################################### +*/ + +/** + * @file MK20D10.h + * @version 1.1 + * @date 2012-01-10 + * @brief Peripheral memory map for MK20D10 + * + * This header file implements peripheral memory map for MK20D10 processor. + */ + + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCU_MK20D10) /* Check if memory map has not been already included */ +#define MCU_MK20D10 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MK20D10 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001u + +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG(Reg,Bit) (*((uint32 volatile*)(0x42000000u + (32u*((uint32)&(Reg) - (uint32)0x40000000u)) + (4u*((uint32)(Bit)))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +typedef enum { + INT_Initial_Stack_Pointer = 0, /**< Initial Stack Pointer */ + INT_Initial_Program_Counter = 1, /**< Initial Program Counter */ + INT_NMI = 2, /**< Non-maskable Interrupt (NMI) */ + INT_Hard_Fault = 3, /**< Hard Fault */ + INT_Mem_Manage_Fault = 4, /**< MemManage Fault */ + INT_Bus_Fault = 5, /**< Bus Fault */ + INT_Usage_Fault = 6, /**< Usage Fault */ + INT_Reserved7 = 7, /**< Reserved interrupt 7 */ + INT_Reserved8 = 8, /**< Reserved interrupt 8 */ + INT_Reserved9 = 9, /**< Reserved interrupt 9 */ + INT_Reserved10 = 10, /**< Reserved interrupt 10 */ + INT_SVCall = 11, /**< Supervisor call (SVCall) */ + INT_DebugMonitor = 12, /**< Debug Monitor */ + INT_Reserved13 = 13, /**< Reserved interrupt 13 */ + INT_PendableSrvReq = 14, /**< Pendable request for system service (PendableSrvReq) */ + INT_SysTick = 15, /**< SysTick Interrupt */ + INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */ + INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */ + INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */ + INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */ + INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */ + INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */ + INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */ + INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */ + INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */ + INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */ + INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */ + INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */ + INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */ + INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */ + INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */ + INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */ + INT_DMA_Error = 32, /**< DMA Error Interrupt */ + INT_MCM = 33, /**< Normal Interrupt */ + INT_FTFL = 34, /**< FTFL Interrupt */ + INT_Read_Collision = 35, /**< Read Collision Interrupt */ + INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */ + INT_LLW = 37, /**< Low Leakage Wakeup */ + INT_Watchdog = 38, /**< WDOG Interrupt */ + INT_Reserved39 = 39, /**< Reserved Interrupt 39 */ + INT_I2C0 = 40, /**< I2C0 interrupt */ + INT_I2C1 = 41, /**< I2C1 interrupt */ + INT_SPI0 = 42, /**< SPI0 Interrupt */ + INT_SPI1 = 43, /**< SPI1 Interrupt */ + INT_SPI2 = 44, /**< SPI2 Interrupt */ + INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd message buffers interrupt */ + INT_CAN0_Bus_Off = 46, /**< CAN0 bus off interrupt */ + INT_CAN0_Error = 47, /**< CAN0 error interrupt */ + INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx warning interrupt */ + INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx warning interrupt */ + INT_CAN0_Wake_Up = 50, /**< CAN0 wake up interrupt */ + INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */ + INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */ + INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd message buffers interrupt */ + INT_CAN1_Bus_Off = 54, /**< CAN1 bus off interrupt */ + INT_CAN1_Error = 55, /**< CAN1 error interrupt */ + INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx warning interrupt */ + INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx warning interrupt */ + INT_CAN1_Wake_Up = 58, /**< CAN1 wake up interrupt */ + INT_Reserved59 = 59, /**< Reserved interrupt 59 */ + INT_UART0_LON = 60, /**< UART0 LON interrupt */ + INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */ + INT_UART0_ERR = 62, /**< UART0 Error interrupt */ + INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */ + INT_UART1_ERR = 64, /**< UART1 Error interrupt */ + INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */ + INT_UART2_ERR = 66, /**< UART2 Error interrupt */ + INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */ + INT_UART3_ERR = 68, /**< UART3 Error interrupt */ + INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */ + INT_UART4_ERR = 70, /**< UART4 Error interrupt */ + INT_UART5_RX_TX = 71, /**< UART5 Receive/Transmit interrupt */ + INT_UART5_ERR = 72, /**< UART5 Error interrupt */ + INT_ADC0 = 73, /**< ADC0 interrupt */ + INT_ADC1 = 74, /**< ADC1 interrupt */ + INT_CMP0 = 75, /**< CMP0 interrupt */ + INT_CMP1 = 76, /**< CMP1 interrupt */ + INT_CMP2 = 77, /**< CMP2 interrupt */ + INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */ + INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */ + INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */ + INT_CMT = 81, /**< CMT interrupt */ + INT_RTC = 82, /**< RTC interrupt */ + INT_RTC_Seconds = 83, /**< RTC seconds interrupt */ + INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */ + INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */ + INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */ + INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */ + INT_PDB0 = 88, /**< PDB0 Interrupt */ + INT_USB0 = 89, /**< USB0 interrupt */ + INT_USBDCD = 90, /**< USBDCD Interrupt */ + INT_Reserved91 = 91, /**< Reserved interrupt 91 */ + INT_Reserved92 = 92, /**< Reserved interrupt 92 */ + INT_Reserved93 = 93, /**< Reserved interrupt 93 */ + INT_Reserved94 = 94, /**< Reserved interrupt 94 */ + INT_Reserved95 = 95, /**< Reserved interrupt 95 */ + INT_SDHC = 96, /**< SDHC Interrupt */ + INT_DAC0 = 97, /**< DAC0 interrupt */ + INT_DAC1 = 98, /**< DAC1 interrupt */ + INT_TSI0 = 99, /**< TSI0 Interrupt */ + INT_MCG = 100, /**< MCG Interrupt */ + INT_LPTimer = 101, /**< LPTimer interrupt */ + INT_Reserved102 = 102, /**< Reserved interrupt 102 */ + INT_PORTA = 103, /**< Port A interrupt */ + INT_PORTB = 104, /**< Port B interrupt */ + INT_PORTC = 105, /**< Port C interrupt */ + INT_PORTD = 106, /**< Port D interrupt */ + INT_PORTE = 107, /**< Port E interrupt */ + INT_Reserved108 = 108, /**< Reserved interrupt 108 */ + INT_Reserved109 = 109, /**< Reserved interrupt 109 */ + INT_SWI = 110, /**< Software interrupt */ + INT_Reserved111 = 111, /**< Reserved interrupt 111 */ + INT_Reserved112 = 112, /**< Reserved interrupt 112 */ + INT_Reserved113 = 113, /**< Reserved interrupt 113 */ + INT_Reserved114 = 114, /**< Reserved interrupt 114 */ + INT_Reserved115 = 115, /**< Reserved interrupt 115 */ + INT_Reserved116 = 116, /**< Reserved interrupt 116 */ + INT_Reserved117 = 117, /**< Reserved interrupt 117 */ + INT_Reserved118 = 118, /**< Reserved interrupt 118 */ + INT_Reserved119 = 119 /**< Reserved interrupt 119 */ +} IRQInterruptIndex; + +/** + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Peripheral type defines + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Peripheral_defines Peripheral type defines + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Peripheral ADC + * @{ + */ + +/** ADC - Peripheral register structure */ +typedef struct ADC_MemMap { + uint32 SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + uint32 CFG1; /**< ADC configuration register 1, offset: 0x8 */ + uint32 CFG2; /**< Configuration register 2, offset: 0xC */ + uint32 R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + uint32 CV1; /**< Compare value registers, offset: 0x18 */ + uint32 CV2; /**< Compare value registers, offset: 0x1C */ + uint32 SC2; /**< Status and control register 2, offset: 0x20 */ + uint32 SC3; /**< Status and control register 3, offset: 0x24 */ + uint32 OFS; /**< ADC offset correction register, offset: 0x28 */ + uint32 PG; /**< ADC plus-side gain register, offset: 0x2C */ + uint32 MG; /**< ADC minus-side gain register, offset: 0x30 */ + uint32 CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + uint32 CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + uint32 CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + uint32 CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + uint32 CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + uint32 CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + uint32 CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + uint32 PGA; /**< ADC PGA register, offset: 0x50 */ + uint32 CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + uint32 CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + uint32 CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + uint32 CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + uint32 CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + uint32 CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + uint32 CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} volatile *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_SC1_REG(base,index) ((base)->SC1[index]) +#define ADC_CFG1_REG(base) ((base)->CFG1) +#define ADC_CFG2_REG(base) ((base)->CFG2) +#define ADC_R_REG(base,index) ((base)->R[index]) +#define ADC_CV1_REG(base) ((base)->CV1) +#define ADC_CV2_REG(base) ((base)->CV2) +#define ADC_SC2_REG(base) ((base)->SC2) +#define ADC_SC3_REG(base) ((base)->SC3) +#define ADC_OFS_REG(base) ((base)->OFS) +#define ADC_PG_REG(base) ((base)->PG) +#define ADC_MG_REG(base) ((base)->MG) +#define ADC_CLPD_REG(base) ((base)->CLPD) +#define ADC_CLPS_REG(base) ((base)->CLPS) +#define ADC_CLP4_REG(base) ((base)->CLP4) +#define ADC_CLP3_REG(base) ((base)->CLP3) +#define ADC_CLP2_REG(base) ((base)->CLP2) +#define ADC_CLP1_REG(base) ((base)->CLP1) +#define ADC_CLP0_REG(base) ((base)->CLP0) +#define ADC_PGA_REG(base) ((base)->PGA) +#define ADC_CLMD_REG(base) ((base)->CLMD) +#define ADC_CLMS_REG(base) ((base)->CLMS) +#define ADC_CLM4_REG(base) ((base)->CLM4) +#define ADC_CLM3_REG(base) ((base)->CLM3) +#define ADC_CLM2_REG(base) ((base)->CLM2) +#define ADC_CLM1_REG(base) ((base)->CLM1) +#define ADC_CLM0_REG(base) ((base)->CLM0) + +/** + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32)(((uint32)(x))<MPRA) +#define AIPS_PACRA_REG(base) ((base)->PACRA) +#define AIPS_PACRB_REG(base) ((base)->PACRB) +#define AIPS_PACRC_REG(base) ((base)->PACRC) +#define AIPS_PACRD_REG(base) ((base)->PACRD) +#define AIPS_PACRE_REG(base) ((base)->PACRE) +#define AIPS_PACRF_REG(base) ((base)->PACRF) +#define AIPS_PACRG_REG(base) ((base)->PACRG) +#define AIPS_PACRH_REG(base) ((base)->PACRH) +#define AIPS_PACRI_REG(base) ((base)->PACRI) +#define AIPS_PACRJ_REG(base) ((base)->PACRJ) +#define AIPS_PACRK_REG(base) ((base)->PACRK) +#define AIPS_PACRL_REG(base) ((base)->PACRL) +#define AIPS_PACRM_REG(base) ((base)->PACRM) +#define AIPS_PACRN_REG(base) ((base)->PACRN) +#define AIPS_PACRO_REG(base) ((base)->PACRO) +#define AIPS_PACRP_REG(base) ((base)->PACRP) + +/** + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AIPS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AIPS_Register_Masks AIPS Register Masks + * @{ + */ + +/* MPRA Bit Fields */ +#define AIPS_MPRA_MPL5_MASK 0x100u +#define AIPS_MPRA_MPL5_SHIFT 8 +#define AIPS_MPRA_MTW5_MASK 0x200u +#define AIPS_MPRA_MTW5_SHIFT 9 +#define AIPS_MPRA_MTR5_MASK 0x400u +#define AIPS_MPRA_MTR5_SHIFT 10 +#define AIPS_MPRA_MPL4_MASK 0x1000u +#define AIPS_MPRA_MPL4_SHIFT 12 +#define AIPS_MPRA_MTW4_MASK 0x2000u +#define AIPS_MPRA_MTW4_SHIFT 13 +#define AIPS_MPRA_MTR4_MASK 0x4000u +#define AIPS_MPRA_MTR4_SHIFT 14 +#define AIPS_MPRA_MPL3_MASK 0x10000u +#define AIPS_MPRA_MPL3_SHIFT 16 +#define AIPS_MPRA_MTW3_MASK 0x20000u +#define AIPS_MPRA_MTW3_SHIFT 17 +#define AIPS_MPRA_MTR3_MASK 0x40000u +#define AIPS_MPRA_MTR3_SHIFT 18 +#define AIPS_MPRA_MPL2_MASK 0x100000u +#define AIPS_MPRA_MPL2_SHIFT 20 +#define AIPS_MPRA_MTW2_MASK 0x200000u +#define AIPS_MPRA_MTW2_SHIFT 21 +#define AIPS_MPRA_MTR2_MASK 0x400000u +#define AIPS_MPRA_MTR2_SHIFT 22 +#define AIPS_MPRA_MPL1_MASK 0x1000000u +#define AIPS_MPRA_MPL1_SHIFT 24 +#define AIPS_MPRA_MTW1_MASK 0x2000000u +#define AIPS_MPRA_MTW1_SHIFT 25 +#define AIPS_MPRA_MTR1_MASK 0x4000000u +#define AIPS_MPRA_MTR1_SHIFT 26 +#define AIPS_MPRA_MPL0_MASK 0x10000000u +#define AIPS_MPRA_MPL0_SHIFT 28 +#define AIPS_MPRA_MTW0_MASK 0x20000000u +#define AIPS_MPRA_MTW0_SHIFT 29 +#define AIPS_MPRA_MTR0_MASK 0x40000000u +#define AIPS_MPRA_MTR0_SHIFT 30 +/* PACRA Bit Fields */ +#define AIPS_PACRA_TP7_MASK 0x1u +#define AIPS_PACRA_TP7_SHIFT 0 +#define AIPS_PACRA_WP7_MASK 0x2u +#define AIPS_PACRA_WP7_SHIFT 1 +#define AIPS_PACRA_SP7_MASK 0x4u +#define AIPS_PACRA_SP7_SHIFT 2 +#define AIPS_PACRA_TP6_MASK 0x10u +#define AIPS_PACRA_TP6_SHIFT 4 +#define AIPS_PACRA_WP6_MASK 0x20u +#define AIPS_PACRA_WP6_SHIFT 5 +#define AIPS_PACRA_SP6_MASK 0x40u +#define AIPS_PACRA_SP6_SHIFT 6 +#define AIPS_PACRA_TP5_MASK 0x100u +#define AIPS_PACRA_TP5_SHIFT 8 +#define AIPS_PACRA_WP5_MASK 0x200u +#define AIPS_PACRA_WP5_SHIFT 9 +#define AIPS_PACRA_SP5_MASK 0x400u +#define AIPS_PACRA_SP5_SHIFT 10 +#define AIPS_PACRA_TP4_MASK 0x1000u +#define AIPS_PACRA_TP4_SHIFT 12 +#define AIPS_PACRA_WP4_MASK 0x2000u +#define AIPS_PACRA_WP4_SHIFT 13 +#define AIPS_PACRA_SP4_MASK 0x4000u +#define AIPS_PACRA_SP4_SHIFT 14 +#define AIPS_PACRA_TP3_MASK 0x10000u +#define AIPS_PACRA_TP3_SHIFT 16 +#define AIPS_PACRA_WP3_MASK 0x20000u +#define AIPS_PACRA_WP3_SHIFT 17 +#define AIPS_PACRA_SP3_MASK 0x40000u +#define AIPS_PACRA_SP3_SHIFT 18 +#define AIPS_PACRA_TP2_MASK 0x100000u +#define AIPS_PACRA_TP2_SHIFT 20 +#define AIPS_PACRA_WP2_MASK 0x200000u +#define AIPS_PACRA_WP2_SHIFT 21 +#define AIPS_PACRA_SP2_MASK 0x400000u +#define AIPS_PACRA_SP2_SHIFT 22 +#define AIPS_PACRA_TP1_MASK 0x1000000u +#define AIPS_PACRA_TP1_SHIFT 24 +#define AIPS_PACRA_WP1_MASK 0x2000000u +#define AIPS_PACRA_WP1_SHIFT 25 +#define AIPS_PACRA_SP1_MASK 0x4000000u +#define AIPS_PACRA_SP1_SHIFT 26 +#define AIPS_PACRA_TP0_MASK 0x10000000u +#define AIPS_PACRA_TP0_SHIFT 28 +#define AIPS_PACRA_WP0_MASK 0x20000000u +#define AIPS_PACRA_WP0_SHIFT 29 +#define AIPS_PACRA_SP0_MASK 0x40000000u +#define AIPS_PACRA_SP0_SHIFT 30 +/* PACRB Bit Fields */ +#define AIPS_PACRB_TP7_MASK 0x1u +#define AIPS_PACRB_TP7_SHIFT 0 +#define AIPS_PACRB_WP7_MASK 0x2u +#define AIPS_PACRB_WP7_SHIFT 1 +#define AIPS_PACRB_SP7_MASK 0x4u +#define AIPS_PACRB_SP7_SHIFT 2 +#define AIPS_PACRB_TP6_MASK 0x10u +#define AIPS_PACRB_TP6_SHIFT 4 +#define AIPS_PACRB_WP6_MASK 0x20u +#define AIPS_PACRB_WP6_SHIFT 5 +#define AIPS_PACRB_SP6_MASK 0x40u +#define AIPS_PACRB_SP6_SHIFT 6 +#define AIPS_PACRB_TP5_MASK 0x100u +#define AIPS_PACRB_TP5_SHIFT 8 +#define AIPS_PACRB_WP5_MASK 0x200u +#define AIPS_PACRB_WP5_SHIFT 9 +#define AIPS_PACRB_SP5_MASK 0x400u +#define AIPS_PACRB_SP5_SHIFT 10 +#define AIPS_PACRB_TP4_MASK 0x1000u +#define AIPS_PACRB_TP4_SHIFT 12 +#define AIPS_PACRB_WP4_MASK 0x2000u +#define AIPS_PACRB_WP4_SHIFT 13 +#define AIPS_PACRB_SP4_MASK 0x4000u +#define AIPS_PACRB_SP4_SHIFT 14 +#define AIPS_PACRB_TP3_MASK 0x10000u +#define AIPS_PACRB_TP3_SHIFT 16 +#define AIPS_PACRB_WP3_MASK 0x20000u +#define AIPS_PACRB_WP3_SHIFT 17 +#define AIPS_PACRB_SP3_MASK 0x40000u +#define AIPS_PACRB_SP3_SHIFT 18 +#define AIPS_PACRB_TP2_MASK 0x100000u +#define AIPS_PACRB_TP2_SHIFT 20 +#define AIPS_PACRB_WP2_MASK 0x200000u +#define AIPS_PACRB_WP2_SHIFT 21 +#define AIPS_PACRB_SP2_MASK 0x400000u +#define AIPS_PACRB_SP2_SHIFT 22 +#define AIPS_PACRB_TP1_MASK 0x1000000u +#define AIPS_PACRB_TP1_SHIFT 24 +#define AIPS_PACRB_WP1_MASK 0x2000000u +#define AIPS_PACRB_WP1_SHIFT 25 +#define AIPS_PACRB_SP1_MASK 0x4000000u +#define AIPS_PACRB_SP1_SHIFT 26 +#define AIPS_PACRB_TP0_MASK 0x10000000u +#define AIPS_PACRB_TP0_SHIFT 28 +#define AIPS_PACRB_WP0_MASK 0x20000000u +#define AIPS_PACRB_WP0_SHIFT 29 +#define AIPS_PACRB_SP0_MASK 0x40000000u +#define AIPS_PACRB_SP0_SHIFT 30 +/* PACRC Bit Fields */ +#define AIPS_PACRC_TP7_MASK 0x1u +#define AIPS_PACRC_TP7_SHIFT 0 +#define AIPS_PACRC_WP7_MASK 0x2u +#define AIPS_PACRC_WP7_SHIFT 1 +#define AIPS_PACRC_SP7_MASK 0x4u +#define AIPS_PACRC_SP7_SHIFT 2 +#define AIPS_PACRC_TP6_MASK 0x10u +#define AIPS_PACRC_TP6_SHIFT 4 +#define AIPS_PACRC_WP6_MASK 0x20u +#define AIPS_PACRC_WP6_SHIFT 5 +#define AIPS_PACRC_SP6_MASK 0x40u +#define AIPS_PACRC_SP6_SHIFT 6 +#define AIPS_PACRC_TP5_MASK 0x100u +#define AIPS_PACRC_TP5_SHIFT 8 +#define AIPS_PACRC_WP5_MASK 0x200u +#define AIPS_PACRC_WP5_SHIFT 9 +#define AIPS_PACRC_SP5_MASK 0x400u +#define AIPS_PACRC_SP5_SHIFT 10 +#define AIPS_PACRC_TP4_MASK 0x1000u +#define AIPS_PACRC_TP4_SHIFT 12 +#define AIPS_PACRC_WP4_MASK 0x2000u +#define AIPS_PACRC_WP4_SHIFT 13 +#define AIPS_PACRC_SP4_MASK 0x4000u +#define AIPS_PACRC_SP4_SHIFT 14 +#define AIPS_PACRC_TP3_MASK 0x10000u +#define AIPS_PACRC_TP3_SHIFT 16 +#define AIPS_PACRC_WP3_MASK 0x20000u +#define AIPS_PACRC_WP3_SHIFT 17 +#define AIPS_PACRC_SP3_MASK 0x40000u +#define AIPS_PACRC_SP3_SHIFT 18 +#define AIPS_PACRC_TP2_MASK 0x100000u +#define AIPS_PACRC_TP2_SHIFT 20 +#define AIPS_PACRC_WP2_MASK 0x200000u +#define AIPS_PACRC_WP2_SHIFT 21 +#define AIPS_PACRC_SP2_MASK 0x400000u +#define AIPS_PACRC_SP2_SHIFT 22 +#define AIPS_PACRC_TP1_MASK 0x1000000u +#define AIPS_PACRC_TP1_SHIFT 24 +#define AIPS_PACRC_WP1_MASK 0x2000000u +#define AIPS_PACRC_WP1_SHIFT 25 +#define AIPS_PACRC_SP1_MASK 0x4000000u +#define AIPS_PACRC_SP1_SHIFT 26 +#define AIPS_PACRC_TP0_MASK 0x10000000u +#define AIPS_PACRC_TP0_SHIFT 28 +#define AIPS_PACRC_WP0_MASK 0x20000000u +#define AIPS_PACRC_WP0_SHIFT 29 +#define AIPS_PACRC_SP0_MASK 0x40000000u +#define AIPS_PACRC_SP0_SHIFT 30 +/* PACRD Bit Fields */ +#define AIPS_PACRD_TP7_MASK 0x1u +#define AIPS_PACRD_TP7_SHIFT 0 +#define AIPS_PACRD_WP7_MASK 0x2u +#define AIPS_PACRD_WP7_SHIFT 1 +#define AIPS_PACRD_SP7_MASK 0x4u +#define AIPS_PACRD_SP7_SHIFT 2 +#define AIPS_PACRD_TP6_MASK 0x10u +#define AIPS_PACRD_TP6_SHIFT 4 +#define AIPS_PACRD_WP6_MASK 0x20u +#define AIPS_PACRD_WP6_SHIFT 5 +#define AIPS_PACRD_SP6_MASK 0x40u +#define AIPS_PACRD_SP6_SHIFT 6 +#define AIPS_PACRD_TP5_MASK 0x100u +#define AIPS_PACRD_TP5_SHIFT 8 +#define AIPS_PACRD_WP5_MASK 0x200u +#define AIPS_PACRD_WP5_SHIFT 9 +#define AIPS_PACRD_SP5_MASK 0x400u +#define AIPS_PACRD_SP5_SHIFT 10 +#define AIPS_PACRD_TP4_MASK 0x1000u +#define AIPS_PACRD_TP4_SHIFT 12 +#define AIPS_PACRD_WP4_MASK 0x2000u +#define AIPS_PACRD_WP4_SHIFT 13 +#define AIPS_PACRD_SP4_MASK 0x4000u +#define AIPS_PACRD_SP4_SHIFT 14 +#define AIPS_PACRD_TP3_MASK 0x10000u +#define AIPS_PACRD_TP3_SHIFT 16 +#define AIPS_PACRD_WP3_MASK 0x20000u +#define AIPS_PACRD_WP3_SHIFT 17 +#define AIPS_PACRD_SP3_MASK 0x40000u +#define AIPS_PACRD_SP3_SHIFT 18 +#define AIPS_PACRD_TP2_MASK 0x100000u +#define AIPS_PACRD_TP2_SHIFT 20 +#define AIPS_PACRD_WP2_MASK 0x200000u +#define AIPS_PACRD_WP2_SHIFT 21 +#define AIPS_PACRD_SP2_MASK 0x400000u +#define AIPS_PACRD_SP2_SHIFT 22 +#define AIPS_PACRD_TP1_MASK 0x1000000u +#define AIPS_PACRD_TP1_SHIFT 24 +#define AIPS_PACRD_WP1_MASK 0x2000000u +#define AIPS_PACRD_WP1_SHIFT 25 +#define AIPS_PACRD_SP1_MASK 0x4000000u +#define AIPS_PACRD_SP1_SHIFT 26 +#define AIPS_PACRD_TP0_MASK 0x10000000u +#define AIPS_PACRD_TP0_SHIFT 28 +#define AIPS_PACRD_WP0_MASK 0x20000000u +#define AIPS_PACRD_WP0_SHIFT 29 +#define AIPS_PACRD_SP0_MASK 0x40000000u +#define AIPS_PACRD_SP0_SHIFT 30 +/* PACRE Bit Fields */ +#define AIPS_PACRE_TP7_MASK 0x1u +#define AIPS_PACRE_TP7_SHIFT 0 +#define AIPS_PACRE_WP7_MASK 0x2u +#define AIPS_PACRE_WP7_SHIFT 1 +#define AIPS_PACRE_SP7_MASK 0x4u +#define AIPS_PACRE_SP7_SHIFT 2 +#define AIPS_PACRE_TP6_MASK 0x10u +#define AIPS_PACRE_TP6_SHIFT 4 +#define AIPS_PACRE_WP6_MASK 0x20u +#define AIPS_PACRE_WP6_SHIFT 5 +#define AIPS_PACRE_SP6_MASK 0x40u +#define AIPS_PACRE_SP6_SHIFT 6 +#define AIPS_PACRE_TP5_MASK 0x100u +#define AIPS_PACRE_TP5_SHIFT 8 +#define AIPS_PACRE_WP5_MASK 0x200u +#define AIPS_PACRE_WP5_SHIFT 9 +#define AIPS_PACRE_SP5_MASK 0x400u +#define AIPS_PACRE_SP5_SHIFT 10 +#define AIPS_PACRE_TP4_MASK 0x1000u +#define AIPS_PACRE_TP4_SHIFT 12 +#define AIPS_PACRE_WP4_MASK 0x2000u +#define AIPS_PACRE_WP4_SHIFT 13 +#define AIPS_PACRE_SP4_MASK 0x4000u +#define AIPS_PACRE_SP4_SHIFT 14 +#define AIPS_PACRE_TP3_MASK 0x10000u +#define AIPS_PACRE_TP3_SHIFT 16 +#define AIPS_PACRE_WP3_MASK 0x20000u +#define AIPS_PACRE_WP3_SHIFT 17 +#define AIPS_PACRE_SP3_MASK 0x40000u +#define AIPS_PACRE_SP3_SHIFT 18 +#define AIPS_PACRE_TP2_MASK 0x100000u +#define AIPS_PACRE_TP2_SHIFT 20 +#define AIPS_PACRE_WP2_MASK 0x200000u +#define AIPS_PACRE_WP2_SHIFT 21 +#define AIPS_PACRE_SP2_MASK 0x400000u +#define AIPS_PACRE_SP2_SHIFT 22 +#define AIPS_PACRE_TP1_MASK 0x1000000u +#define AIPS_PACRE_TP1_SHIFT 24 +#define AIPS_PACRE_WP1_MASK 0x2000000u +#define AIPS_PACRE_WP1_SHIFT 25 +#define AIPS_PACRE_SP1_MASK 0x4000000u +#define AIPS_PACRE_SP1_SHIFT 26 +#define AIPS_PACRE_TP0_MASK 0x10000000u +#define AIPS_PACRE_TP0_SHIFT 28 +#define AIPS_PACRE_WP0_MASK 0x20000000u +#define AIPS_PACRE_WP0_SHIFT 29 +#define AIPS_PACRE_SP0_MASK 0x40000000u +#define AIPS_PACRE_SP0_SHIFT 30 +/* PACRF Bit Fields */ +#define AIPS_PACRF_TP7_MASK 0x1u +#define AIPS_PACRF_TP7_SHIFT 0 +#define AIPS_PACRF_WP7_MASK 0x2u +#define AIPS_PACRF_WP7_SHIFT 1 +#define AIPS_PACRF_SP7_MASK 0x4u +#define AIPS_PACRF_SP7_SHIFT 2 +#define AIPS_PACRF_TP6_MASK 0x10u +#define AIPS_PACRF_TP6_SHIFT 4 +#define AIPS_PACRF_WP6_MASK 0x20u +#define AIPS_PACRF_WP6_SHIFT 5 +#define AIPS_PACRF_SP6_MASK 0x40u +#define AIPS_PACRF_SP6_SHIFT 6 +#define AIPS_PACRF_TP5_MASK 0x100u +#define AIPS_PACRF_TP5_SHIFT 8 +#define AIPS_PACRF_WP5_MASK 0x200u +#define AIPS_PACRF_WP5_SHIFT 9 +#define AIPS_PACRF_SP5_MASK 0x400u +#define AIPS_PACRF_SP5_SHIFT 10 +#define AIPS_PACRF_TP4_MASK 0x1000u +#define AIPS_PACRF_TP4_SHIFT 12 +#define AIPS_PACRF_WP4_MASK 0x2000u +#define AIPS_PACRF_WP4_SHIFT 13 +#define AIPS_PACRF_SP4_MASK 0x4000u +#define AIPS_PACRF_SP4_SHIFT 14 +#define AIPS_PACRF_TP3_MASK 0x10000u +#define AIPS_PACRF_TP3_SHIFT 16 +#define AIPS_PACRF_WP3_MASK 0x20000u +#define AIPS_PACRF_WP3_SHIFT 17 +#define AIPS_PACRF_SP3_MASK 0x40000u +#define AIPS_PACRF_SP3_SHIFT 18 +#define AIPS_PACRF_TP2_MASK 0x100000u +#define AIPS_PACRF_TP2_SHIFT 20 +#define AIPS_PACRF_WP2_MASK 0x200000u +#define AIPS_PACRF_WP2_SHIFT 21 +#define AIPS_PACRF_SP2_MASK 0x400000u +#define AIPS_PACRF_SP2_SHIFT 22 +#define AIPS_PACRF_TP1_MASK 0x1000000u +#define AIPS_PACRF_TP1_SHIFT 24 +#define AIPS_PACRF_WP1_MASK 0x2000000u +#define AIPS_PACRF_WP1_SHIFT 25 +#define AIPS_PACRF_SP1_MASK 0x4000000u +#define AIPS_PACRF_SP1_SHIFT 26 +#define AIPS_PACRF_TP0_MASK 0x10000000u +#define AIPS_PACRF_TP0_SHIFT 28 +#define AIPS_PACRF_WP0_MASK 0x20000000u +#define AIPS_PACRF_WP0_SHIFT 29 +#define AIPS_PACRF_SP0_MASK 0x40000000u +#define AIPS_PACRF_SP0_SHIFT 30 +/* PACRG Bit Fields */ +#define AIPS_PACRG_TP7_MASK 0x1u +#define AIPS_PACRG_TP7_SHIFT 0 +#define AIPS_PACRG_WP7_MASK 0x2u +#define AIPS_PACRG_WP7_SHIFT 1 +#define AIPS_PACRG_SP7_MASK 0x4u +#define AIPS_PACRG_SP7_SHIFT 2 +#define AIPS_PACRG_TP6_MASK 0x10u +#define AIPS_PACRG_TP6_SHIFT 4 +#define AIPS_PACRG_WP6_MASK 0x20u +#define AIPS_PACRG_WP6_SHIFT 5 +#define AIPS_PACRG_SP6_MASK 0x40u +#define AIPS_PACRG_SP6_SHIFT 6 +#define AIPS_PACRG_TP5_MASK 0x100u +#define AIPS_PACRG_TP5_SHIFT 8 +#define AIPS_PACRG_WP5_MASK 0x200u +#define AIPS_PACRG_WP5_SHIFT 9 +#define AIPS_PACRG_SP5_MASK 0x400u +#define AIPS_PACRG_SP5_SHIFT 10 +#define AIPS_PACRG_TP4_MASK 0x1000u +#define AIPS_PACRG_TP4_SHIFT 12 +#define AIPS_PACRG_WP4_MASK 0x2000u +#define AIPS_PACRG_WP4_SHIFT 13 +#define AIPS_PACRG_SP4_MASK 0x4000u +#define AIPS_PACRG_SP4_SHIFT 14 +#define AIPS_PACRG_TP3_MASK 0x10000u +#define AIPS_PACRG_TP3_SHIFT 16 +#define AIPS_PACRG_WP3_MASK 0x20000u +#define AIPS_PACRG_WP3_SHIFT 17 +#define AIPS_PACRG_SP3_MASK 0x40000u +#define AIPS_PACRG_SP3_SHIFT 18 +#define AIPS_PACRG_TP2_MASK 0x100000u +#define AIPS_PACRG_TP2_SHIFT 20 +#define AIPS_PACRG_WP2_MASK 0x200000u +#define AIPS_PACRG_WP2_SHIFT 21 +#define AIPS_PACRG_SP2_MASK 0x400000u +#define AIPS_PACRG_SP2_SHIFT 22 +#define AIPS_PACRG_TP1_MASK 0x1000000u +#define AIPS_PACRG_TP1_SHIFT 24 +#define AIPS_PACRG_WP1_MASK 0x2000000u +#define AIPS_PACRG_WP1_SHIFT 25 +#define AIPS_PACRG_SP1_MASK 0x4000000u +#define AIPS_PACRG_SP1_SHIFT 26 +#define AIPS_PACRG_TP0_MASK 0x10000000u +#define AIPS_PACRG_TP0_SHIFT 28 +#define AIPS_PACRG_WP0_MASK 0x20000000u +#define AIPS_PACRG_WP0_SHIFT 29 +#define AIPS_PACRG_SP0_MASK 0x40000000u +#define AIPS_PACRG_SP0_SHIFT 30 +/* PACRH Bit Fields */ +#define AIPS_PACRH_TP7_MASK 0x1u +#define AIPS_PACRH_TP7_SHIFT 0 +#define AIPS_PACRH_WP7_MASK 0x2u +#define AIPS_PACRH_WP7_SHIFT 1 +#define AIPS_PACRH_SP7_MASK 0x4u +#define AIPS_PACRH_SP7_SHIFT 2 +#define AIPS_PACRH_TP6_MASK 0x10u +#define AIPS_PACRH_TP6_SHIFT 4 +#define AIPS_PACRH_WP6_MASK 0x20u +#define AIPS_PACRH_WP6_SHIFT 5 +#define AIPS_PACRH_SP6_MASK 0x40u +#define AIPS_PACRH_SP6_SHIFT 6 +#define AIPS_PACRH_TP5_MASK 0x100u +#define AIPS_PACRH_TP5_SHIFT 8 +#define AIPS_PACRH_WP5_MASK 0x200u +#define AIPS_PACRH_WP5_SHIFT 9 +#define AIPS_PACRH_SP5_MASK 0x400u +#define AIPS_PACRH_SP5_SHIFT 10 +#define AIPS_PACRH_TP4_MASK 0x1000u +#define AIPS_PACRH_TP4_SHIFT 12 +#define AIPS_PACRH_WP4_MASK 0x2000u +#define AIPS_PACRH_WP4_SHIFT 13 +#define AIPS_PACRH_SP4_MASK 0x4000u +#define AIPS_PACRH_SP4_SHIFT 14 +#define AIPS_PACRH_TP3_MASK 0x10000u +#define AIPS_PACRH_TP3_SHIFT 16 +#define AIPS_PACRH_WP3_MASK 0x20000u +#define AIPS_PACRH_WP3_SHIFT 17 +#define AIPS_PACRH_SP3_MASK 0x40000u +#define AIPS_PACRH_SP3_SHIFT 18 +#define AIPS_PACRH_TP2_MASK 0x100000u +#define AIPS_PACRH_TP2_SHIFT 20 +#define AIPS_PACRH_WP2_MASK 0x200000u +#define AIPS_PACRH_WP2_SHIFT 21 +#define AIPS_PACRH_SP2_MASK 0x400000u +#define AIPS_PACRH_SP2_SHIFT 22 +#define AIPS_PACRH_TP1_MASK 0x1000000u +#define AIPS_PACRH_TP1_SHIFT 24 +#define AIPS_PACRH_WP1_MASK 0x2000000u +#define AIPS_PACRH_WP1_SHIFT 25 +#define AIPS_PACRH_SP1_MASK 0x4000000u +#define AIPS_PACRH_SP1_SHIFT 26 +#define AIPS_PACRH_TP0_MASK 0x10000000u +#define AIPS_PACRH_TP0_SHIFT 28 +#define AIPS_PACRH_WP0_MASK 0x20000000u +#define AIPS_PACRH_WP0_SHIFT 29 +#define AIPS_PACRH_SP0_MASK 0x40000000u +#define AIPS_PACRH_SP0_SHIFT 30 +/* PACRI Bit Fields */ +#define AIPS_PACRI_TP7_MASK 0x1u +#define AIPS_PACRI_TP7_SHIFT 0 +#define AIPS_PACRI_WP7_MASK 0x2u +#define AIPS_PACRI_WP7_SHIFT 1 +#define AIPS_PACRI_SP7_MASK 0x4u +#define AIPS_PACRI_SP7_SHIFT 2 +#define AIPS_PACRI_TP6_MASK 0x10u +#define AIPS_PACRI_TP6_SHIFT 4 +#define AIPS_PACRI_WP6_MASK 0x20u +#define AIPS_PACRI_WP6_SHIFT 5 +#define AIPS_PACRI_SP6_MASK 0x40u +#define AIPS_PACRI_SP6_SHIFT 6 +#define AIPS_PACRI_TP5_MASK 0x100u +#define AIPS_PACRI_TP5_SHIFT 8 +#define AIPS_PACRI_WP5_MASK 0x200u +#define AIPS_PACRI_WP5_SHIFT 9 +#define AIPS_PACRI_SP5_MASK 0x400u +#define AIPS_PACRI_SP5_SHIFT 10 +#define AIPS_PACRI_TP4_MASK 0x1000u +#define AIPS_PACRI_TP4_SHIFT 12 +#define AIPS_PACRI_WP4_MASK 0x2000u +#define AIPS_PACRI_WP4_SHIFT 13 +#define AIPS_PACRI_SP4_MASK 0x4000u +#define AIPS_PACRI_SP4_SHIFT 14 +#define AIPS_PACRI_TP3_MASK 0x10000u +#define AIPS_PACRI_TP3_SHIFT 16 +#define AIPS_PACRI_WP3_MASK 0x20000u +#define AIPS_PACRI_WP3_SHIFT 17 +#define AIPS_PACRI_SP3_MASK 0x40000u +#define AIPS_PACRI_SP3_SHIFT 18 +#define AIPS_PACRI_TP2_MASK 0x100000u +#define AIPS_PACRI_TP2_SHIFT 20 +#define AIPS_PACRI_WP2_MASK 0x200000u +#define AIPS_PACRI_WP2_SHIFT 21 +#define AIPS_PACRI_SP2_MASK 0x400000u +#define AIPS_PACRI_SP2_SHIFT 22 +#define AIPS_PACRI_TP1_MASK 0x1000000u +#define AIPS_PACRI_TP1_SHIFT 24 +#define AIPS_PACRI_WP1_MASK 0x2000000u +#define AIPS_PACRI_WP1_SHIFT 25 +#define AIPS_PACRI_SP1_MASK 0x4000000u +#define AIPS_PACRI_SP1_SHIFT 26 +#define AIPS_PACRI_TP0_MASK 0x10000000u +#define AIPS_PACRI_TP0_SHIFT 28 +#define AIPS_PACRI_WP0_MASK 0x20000000u +#define AIPS_PACRI_WP0_SHIFT 29 +#define AIPS_PACRI_SP0_MASK 0x40000000u +#define AIPS_PACRI_SP0_SHIFT 30 +/* PACRJ Bit Fields */ +#define AIPS_PACRJ_TP7_MASK 0x1u +#define AIPS_PACRJ_TP7_SHIFT 0 +#define AIPS_PACRJ_WP7_MASK 0x2u +#define AIPS_PACRJ_WP7_SHIFT 1 +#define AIPS_PACRJ_SP7_MASK 0x4u +#define AIPS_PACRJ_SP7_SHIFT 2 +#define AIPS_PACRJ_TP6_MASK 0x10u +#define AIPS_PACRJ_TP6_SHIFT 4 +#define AIPS_PACRJ_WP6_MASK 0x20u +#define AIPS_PACRJ_WP6_SHIFT 5 +#define AIPS_PACRJ_SP6_MASK 0x40u +#define AIPS_PACRJ_SP6_SHIFT 6 +#define AIPS_PACRJ_TP5_MASK 0x100u +#define AIPS_PACRJ_TP5_SHIFT 8 +#define AIPS_PACRJ_WP5_MASK 0x200u +#define AIPS_PACRJ_WP5_SHIFT 9 +#define AIPS_PACRJ_SP5_MASK 0x400u +#define AIPS_PACRJ_SP5_SHIFT 10 +#define AIPS_PACRJ_TP4_MASK 0x1000u +#define AIPS_PACRJ_TP4_SHIFT 12 +#define AIPS_PACRJ_WP4_MASK 0x2000u +#define AIPS_PACRJ_WP4_SHIFT 13 +#define AIPS_PACRJ_SP4_MASK 0x4000u +#define AIPS_PACRJ_SP4_SHIFT 14 +#define AIPS_PACRJ_TP3_MASK 0x10000u +#define AIPS_PACRJ_TP3_SHIFT 16 +#define AIPS_PACRJ_WP3_MASK 0x20000u +#define AIPS_PACRJ_WP3_SHIFT 17 +#define AIPS_PACRJ_SP3_MASK 0x40000u +#define AIPS_PACRJ_SP3_SHIFT 18 +#define AIPS_PACRJ_TP2_MASK 0x100000u +#define AIPS_PACRJ_TP2_SHIFT 20 +#define AIPS_PACRJ_WP2_MASK 0x200000u +#define AIPS_PACRJ_WP2_SHIFT 21 +#define AIPS_PACRJ_SP2_MASK 0x400000u +#define AIPS_PACRJ_SP2_SHIFT 22 +#define AIPS_PACRJ_TP1_MASK 0x1000000u +#define AIPS_PACRJ_TP1_SHIFT 24 +#define AIPS_PACRJ_WP1_MASK 0x2000000u +#define AIPS_PACRJ_WP1_SHIFT 25 +#define AIPS_PACRJ_SP1_MASK 0x4000000u +#define AIPS_PACRJ_SP1_SHIFT 26 +#define AIPS_PACRJ_TP0_MASK 0x10000000u +#define AIPS_PACRJ_TP0_SHIFT 28 +#define AIPS_PACRJ_WP0_MASK 0x20000000u +#define AIPS_PACRJ_WP0_SHIFT 29 +#define AIPS_PACRJ_SP0_MASK 0x40000000u +#define AIPS_PACRJ_SP0_SHIFT 30 +/* PACRK Bit Fields */ +#define AIPS_PACRK_TP7_MASK 0x1u +#define AIPS_PACRK_TP7_SHIFT 0 +#define AIPS_PACRK_WP7_MASK 0x2u +#define AIPS_PACRK_WP7_SHIFT 1 +#define AIPS_PACRK_SP7_MASK 0x4u +#define AIPS_PACRK_SP7_SHIFT 2 +#define AIPS_PACRK_TP6_MASK 0x10u +#define AIPS_PACRK_TP6_SHIFT 4 +#define AIPS_PACRK_WP6_MASK 0x20u +#define AIPS_PACRK_WP6_SHIFT 5 +#define AIPS_PACRK_SP6_MASK 0x40u +#define AIPS_PACRK_SP6_SHIFT 6 +#define AIPS_PACRK_TP5_MASK 0x100u +#define AIPS_PACRK_TP5_SHIFT 8 +#define AIPS_PACRK_WP5_MASK 0x200u +#define AIPS_PACRK_WP5_SHIFT 9 +#define AIPS_PACRK_SP5_MASK 0x400u +#define AIPS_PACRK_SP5_SHIFT 10 +#define AIPS_PACRK_TP4_MASK 0x1000u +#define AIPS_PACRK_TP4_SHIFT 12 +#define AIPS_PACRK_WP4_MASK 0x2000u +#define AIPS_PACRK_WP4_SHIFT 13 +#define AIPS_PACRK_SP4_MASK 0x4000u +#define AIPS_PACRK_SP4_SHIFT 14 +#define AIPS_PACRK_TP3_MASK 0x10000u +#define AIPS_PACRK_TP3_SHIFT 16 +#define AIPS_PACRK_WP3_MASK 0x20000u +#define AIPS_PACRK_WP3_SHIFT 17 +#define AIPS_PACRK_SP3_MASK 0x40000u +#define AIPS_PACRK_SP3_SHIFT 18 +#define AIPS_PACRK_TP2_MASK 0x100000u +#define AIPS_PACRK_TP2_SHIFT 20 +#define AIPS_PACRK_WP2_MASK 0x200000u +#define AIPS_PACRK_WP2_SHIFT 21 +#define AIPS_PACRK_SP2_MASK 0x400000u +#define AIPS_PACRK_SP2_SHIFT 22 +#define AIPS_PACRK_TP1_MASK 0x1000000u +#define AIPS_PACRK_TP1_SHIFT 24 +#define AIPS_PACRK_WP1_MASK 0x2000000u +#define AIPS_PACRK_WP1_SHIFT 25 +#define AIPS_PACRK_SP1_MASK 0x4000000u +#define AIPS_PACRK_SP1_SHIFT 26 +#define AIPS_PACRK_TP0_MASK 0x10000000u +#define AIPS_PACRK_TP0_SHIFT 28 +#define AIPS_PACRK_WP0_MASK 0x20000000u +#define AIPS_PACRK_WP0_SHIFT 29 +#define AIPS_PACRK_SP0_MASK 0x40000000u +#define AIPS_PACRK_SP0_SHIFT 30 +/* PACRL Bit Fields */ +#define AIPS_PACRL_TP7_MASK 0x1u +#define AIPS_PACRL_TP7_SHIFT 0 +#define AIPS_PACRL_WP7_MASK 0x2u +#define AIPS_PACRL_WP7_SHIFT 1 +#define AIPS_PACRL_SP7_MASK 0x4u +#define AIPS_PACRL_SP7_SHIFT 2 +#define AIPS_PACRL_TP6_MASK 0x10u +#define AIPS_PACRL_TP6_SHIFT 4 +#define AIPS_PACRL_WP6_MASK 0x20u +#define AIPS_PACRL_WP6_SHIFT 5 +#define AIPS_PACRL_SP6_MASK 0x40u +#define AIPS_PACRL_SP6_SHIFT 6 +#define AIPS_PACRL_TP5_MASK 0x100u +#define AIPS_PACRL_TP5_SHIFT 8 +#define AIPS_PACRL_WP5_MASK 0x200u +#define AIPS_PACRL_WP5_SHIFT 9 +#define AIPS_PACRL_SP5_MASK 0x400u +#define AIPS_PACRL_SP5_SHIFT 10 +#define AIPS_PACRL_TP4_MASK 0x1000u +#define AIPS_PACRL_TP4_SHIFT 12 +#define AIPS_PACRL_WP4_MASK 0x2000u +#define AIPS_PACRL_WP4_SHIFT 13 +#define AIPS_PACRL_SP4_MASK 0x4000u +#define AIPS_PACRL_SP4_SHIFT 14 +#define AIPS_PACRL_TP3_MASK 0x10000u +#define AIPS_PACRL_TP3_SHIFT 16 +#define AIPS_PACRL_WP3_MASK 0x20000u +#define AIPS_PACRL_WP3_SHIFT 17 +#define AIPS_PACRL_SP3_MASK 0x40000u +#define AIPS_PACRL_SP3_SHIFT 18 +#define AIPS_PACRL_TP2_MASK 0x100000u +#define AIPS_PACRL_TP2_SHIFT 20 +#define AIPS_PACRL_WP2_MASK 0x200000u +#define AIPS_PACRL_WP2_SHIFT 21 +#define AIPS_PACRL_SP2_MASK 0x400000u +#define AIPS_PACRL_SP2_SHIFT 22 +#define AIPS_PACRL_TP1_MASK 0x1000000u +#define AIPS_PACRL_TP1_SHIFT 24 +#define AIPS_PACRL_WP1_MASK 0x2000000u +#define AIPS_PACRL_WP1_SHIFT 25 +#define AIPS_PACRL_SP1_MASK 0x4000000u +#define AIPS_PACRL_SP1_SHIFT 26 +#define AIPS_PACRL_TP0_MASK 0x10000000u +#define AIPS_PACRL_TP0_SHIFT 28 +#define AIPS_PACRL_WP0_MASK 0x20000000u +#define AIPS_PACRL_WP0_SHIFT 29 +#define AIPS_PACRL_SP0_MASK 0x40000000u +#define AIPS_PACRL_SP0_SHIFT 30 +/* PACRM Bit Fields */ +#define AIPS_PACRM_TP7_MASK 0x1u +#define AIPS_PACRM_TP7_SHIFT 0 +#define AIPS_PACRM_WP7_MASK 0x2u +#define AIPS_PACRM_WP7_SHIFT 1 +#define AIPS_PACRM_SP7_MASK 0x4u +#define AIPS_PACRM_SP7_SHIFT 2 +#define AIPS_PACRM_TP6_MASK 0x10u +#define AIPS_PACRM_TP6_SHIFT 4 +#define AIPS_PACRM_WP6_MASK 0x20u +#define AIPS_PACRM_WP6_SHIFT 5 +#define AIPS_PACRM_SP6_MASK 0x40u +#define AIPS_PACRM_SP6_SHIFT 6 +#define AIPS_PACRM_TP5_MASK 0x100u +#define AIPS_PACRM_TP5_SHIFT 8 +#define AIPS_PACRM_WP5_MASK 0x200u +#define AIPS_PACRM_WP5_SHIFT 9 +#define AIPS_PACRM_SP5_MASK 0x400u +#define AIPS_PACRM_SP5_SHIFT 10 +#define AIPS_PACRM_TP4_MASK 0x1000u +#define AIPS_PACRM_TP4_SHIFT 12 +#define AIPS_PACRM_WP4_MASK 0x2000u +#define AIPS_PACRM_WP4_SHIFT 13 +#define AIPS_PACRM_SP4_MASK 0x4000u +#define AIPS_PACRM_SP4_SHIFT 14 +#define AIPS_PACRM_TP3_MASK 0x10000u +#define AIPS_PACRM_TP3_SHIFT 16 +#define AIPS_PACRM_WP3_MASK 0x20000u +#define AIPS_PACRM_WP3_SHIFT 17 +#define AIPS_PACRM_SP3_MASK 0x40000u +#define AIPS_PACRM_SP3_SHIFT 18 +#define AIPS_PACRM_TP2_MASK 0x100000u +#define AIPS_PACRM_TP2_SHIFT 20 +#define AIPS_PACRM_WP2_MASK 0x200000u +#define AIPS_PACRM_WP2_SHIFT 21 +#define AIPS_PACRM_SP2_MASK 0x400000u +#define AIPS_PACRM_SP2_SHIFT 22 +#define AIPS_PACRM_TP1_MASK 0x1000000u +#define AIPS_PACRM_TP1_SHIFT 24 +#define AIPS_PACRM_WP1_MASK 0x2000000u +#define AIPS_PACRM_WP1_SHIFT 25 +#define AIPS_PACRM_SP1_MASK 0x4000000u +#define AIPS_PACRM_SP1_SHIFT 26 +#define AIPS_PACRM_TP0_MASK 0x10000000u +#define AIPS_PACRM_TP0_SHIFT 28 +#define AIPS_PACRM_WP0_MASK 0x20000000u +#define AIPS_PACRM_WP0_SHIFT 29 +#define AIPS_PACRM_SP0_MASK 0x40000000u +#define AIPS_PACRM_SP0_SHIFT 30 +/* PACRN Bit Fields */ +#define AIPS_PACRN_TP7_MASK 0x1u +#define AIPS_PACRN_TP7_SHIFT 0 +#define AIPS_PACRN_WP7_MASK 0x2u +#define AIPS_PACRN_WP7_SHIFT 1 +#define AIPS_PACRN_SP7_MASK 0x4u +#define AIPS_PACRN_SP7_SHIFT 2 +#define AIPS_PACRN_TP6_MASK 0x10u +#define AIPS_PACRN_TP6_SHIFT 4 +#define AIPS_PACRN_WP6_MASK 0x20u +#define AIPS_PACRN_WP6_SHIFT 5 +#define AIPS_PACRN_SP6_MASK 0x40u +#define AIPS_PACRN_SP6_SHIFT 6 +#define AIPS_PACRN_TP5_MASK 0x100u +#define AIPS_PACRN_TP5_SHIFT 8 +#define AIPS_PACRN_WP5_MASK 0x200u +#define AIPS_PACRN_WP5_SHIFT 9 +#define AIPS_PACRN_SP5_MASK 0x400u +#define AIPS_PACRN_SP5_SHIFT 10 +#define AIPS_PACRN_TP4_MASK 0x1000u +#define AIPS_PACRN_TP4_SHIFT 12 +#define AIPS_PACRN_WP4_MASK 0x2000u +#define AIPS_PACRN_WP4_SHIFT 13 +#define AIPS_PACRN_SP4_MASK 0x4000u +#define AIPS_PACRN_SP4_SHIFT 14 +#define AIPS_PACRN_TP3_MASK 0x10000u +#define AIPS_PACRN_TP3_SHIFT 16 +#define AIPS_PACRN_WP3_MASK 0x20000u +#define AIPS_PACRN_WP3_SHIFT 17 +#define AIPS_PACRN_SP3_MASK 0x40000u +#define AIPS_PACRN_SP3_SHIFT 18 +#define AIPS_PACRN_TP2_MASK 0x100000u +#define AIPS_PACRN_TP2_SHIFT 20 +#define AIPS_PACRN_WP2_MASK 0x200000u +#define AIPS_PACRN_WP2_SHIFT 21 +#define AIPS_PACRN_SP2_MASK 0x400000u +#define AIPS_PACRN_SP2_SHIFT 22 +#define AIPS_PACRN_TP1_MASK 0x1000000u +#define AIPS_PACRN_TP1_SHIFT 24 +#define AIPS_PACRN_WP1_MASK 0x2000000u +#define AIPS_PACRN_WP1_SHIFT 25 +#define AIPS_PACRN_SP1_MASK 0x4000000u +#define AIPS_PACRN_SP1_SHIFT 26 +#define AIPS_PACRN_TP0_MASK 0x10000000u +#define AIPS_PACRN_TP0_SHIFT 28 +#define AIPS_PACRN_WP0_MASK 0x20000000u +#define AIPS_PACRN_WP0_SHIFT 29 +#define AIPS_PACRN_SP0_MASK 0x40000000u +#define AIPS_PACRN_SP0_SHIFT 30 +/* PACRO Bit Fields */ +#define AIPS_PACRO_TP7_MASK 0x1u +#define AIPS_PACRO_TP7_SHIFT 0 +#define AIPS_PACRO_WP7_MASK 0x2u +#define AIPS_PACRO_WP7_SHIFT 1 +#define AIPS_PACRO_SP7_MASK 0x4u +#define AIPS_PACRO_SP7_SHIFT 2 +#define AIPS_PACRO_TP6_MASK 0x10u +#define AIPS_PACRO_TP6_SHIFT 4 +#define AIPS_PACRO_WP6_MASK 0x20u +#define AIPS_PACRO_WP6_SHIFT 5 +#define AIPS_PACRO_SP6_MASK 0x40u +#define AIPS_PACRO_SP6_SHIFT 6 +#define AIPS_PACRO_TP5_MASK 0x100u +#define AIPS_PACRO_TP5_SHIFT 8 +#define AIPS_PACRO_WP5_MASK 0x200u +#define AIPS_PACRO_WP5_SHIFT 9 +#define AIPS_PACRO_SP5_MASK 0x400u +#define AIPS_PACRO_SP5_SHIFT 10 +#define AIPS_PACRO_TP4_MASK 0x1000u +#define AIPS_PACRO_TP4_SHIFT 12 +#define AIPS_PACRO_WP4_MASK 0x2000u +#define AIPS_PACRO_WP4_SHIFT 13 +#define AIPS_PACRO_SP4_MASK 0x4000u +#define AIPS_PACRO_SP4_SHIFT 14 +#define AIPS_PACRO_TP3_MASK 0x10000u +#define AIPS_PACRO_TP3_SHIFT 16 +#define AIPS_PACRO_WP3_MASK 0x20000u +#define AIPS_PACRO_WP3_SHIFT 17 +#define AIPS_PACRO_SP3_MASK 0x40000u +#define AIPS_PACRO_SP3_SHIFT 18 +#define AIPS_PACRO_TP2_MASK 0x100000u +#define AIPS_PACRO_TP2_SHIFT 20 +#define AIPS_PACRO_WP2_MASK 0x200000u +#define AIPS_PACRO_WP2_SHIFT 21 +#define AIPS_PACRO_SP2_MASK 0x400000u +#define AIPS_PACRO_SP2_SHIFT 22 +#define AIPS_PACRO_TP1_MASK 0x1000000u +#define AIPS_PACRO_TP1_SHIFT 24 +#define AIPS_PACRO_WP1_MASK 0x2000000u +#define AIPS_PACRO_WP1_SHIFT 25 +#define AIPS_PACRO_SP1_MASK 0x4000000u +#define AIPS_PACRO_SP1_SHIFT 26 +#define AIPS_PACRO_TP0_MASK 0x10000000u +#define AIPS_PACRO_TP0_SHIFT 28 +#define AIPS_PACRO_WP0_MASK 0x20000000u +#define AIPS_PACRO_WP0_SHIFT 29 +#define AIPS_PACRO_SP0_MASK 0x40000000u +#define AIPS_PACRO_SP0_SHIFT 30 +/* PACRP Bit Fields */ +#define AIPS_PACRP_TP7_MASK 0x1u +#define AIPS_PACRP_TP7_SHIFT 0 +#define AIPS_PACRP_WP7_MASK 0x2u +#define AIPS_PACRP_WP7_SHIFT 1 +#define AIPS_PACRP_SP7_MASK 0x4u +#define AIPS_PACRP_SP7_SHIFT 2 +#define AIPS_PACRP_TP6_MASK 0x10u +#define AIPS_PACRP_TP6_SHIFT 4 +#define AIPS_PACRP_WP6_MASK 0x20u +#define AIPS_PACRP_WP6_SHIFT 5 +#define AIPS_PACRP_SP6_MASK 0x40u +#define AIPS_PACRP_SP6_SHIFT 6 +#define AIPS_PACRP_TP5_MASK 0x100u +#define AIPS_PACRP_TP5_SHIFT 8 +#define AIPS_PACRP_WP5_MASK 0x200u +#define AIPS_PACRP_WP5_SHIFT 9 +#define AIPS_PACRP_SP5_MASK 0x400u +#define AIPS_PACRP_SP5_SHIFT 10 +#define AIPS_PACRP_TP4_MASK 0x1000u +#define AIPS_PACRP_TP4_SHIFT 12 +#define AIPS_PACRP_WP4_MASK 0x2000u +#define AIPS_PACRP_WP4_SHIFT 13 +#define AIPS_PACRP_SP4_MASK 0x4000u +#define AIPS_PACRP_SP4_SHIFT 14 +#define AIPS_PACRP_TP3_MASK 0x10000u +#define AIPS_PACRP_TP3_SHIFT 16 +#define AIPS_PACRP_WP3_MASK 0x20000u +#define AIPS_PACRP_WP3_SHIFT 17 +#define AIPS_PACRP_SP3_MASK 0x40000u +#define AIPS_PACRP_SP3_SHIFT 18 +#define AIPS_PACRP_TP2_MASK 0x100000u +#define AIPS_PACRP_TP2_SHIFT 20 +#define AIPS_PACRP_WP2_MASK 0x200000u +#define AIPS_PACRP_WP2_SHIFT 21 +#define AIPS_PACRP_SP2_MASK 0x400000u +#define AIPS_PACRP_SP2_SHIFT 22 +#define AIPS_PACRP_TP1_MASK 0x1000000u +#define AIPS_PACRP_TP1_SHIFT 24 +#define AIPS_PACRP_WP1_MASK 0x2000000u +#define AIPS_PACRP_WP1_SHIFT 25 +#define AIPS_PACRP_SP1_MASK 0x4000000u +#define AIPS_PACRP_SP1_SHIFT 26 +#define AIPS_PACRP_TP0_MASK 0x10000000u +#define AIPS_PACRP_TP0_SHIFT 28 +#define AIPS_PACRP_WP0_MASK 0x20000000u +#define AIPS_PACRP_WP0_SHIFT 29 +#define AIPS_PACRP_SP0_MASK 0x40000000u +#define AIPS_PACRP_SP0_SHIFT 30 + +/** + * @} + */ /* end of group AIPS_Register_Masks */ + + +/* AIPS - Peripheral instance base addresses */ +/** Peripheral AIPS0 base pointer */ +#define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u) +/** Peripheral AIPS1 base pointer */ +#define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u) + +/* ---------------------------------------------------------------------------- + -- AIPS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros + * @{ + */ + + +/* AIPS - Register instance definitions */ +/* AIPS0 */ +#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR) +#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR) +/* AIPS1 */ +#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR) +#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR) + +/** + * @} + */ /* end of group AIPS_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group AIPS_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- AXBS + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Peripheral AXBS + * @{ + */ + +/** AXBS - Peripheral register structure */ +typedef struct AXBS_MemMap { + struct { /* offset: 0x0, array step: 0x100 */ + uint32 PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ + uint8 RESERVED_0[12]; + uint32 CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ + uint8 RESERVED_1[236]; + } SLAVE[5]; + uint8 RESERVED_0[768]; + uint32 MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8 RESERVED_1[252]; + uint32 MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8 RESERVED_2[252]; + uint32 MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8 RESERVED_3[508]; + uint32 MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8 RESERVED_4[252]; + uint32 MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ +} volatile *AXBS_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- AXBS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros + * @{ + */ + + +/* AXBS - Register accessors */ +#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) +#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) +#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) +#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) +#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) +#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) +#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) + +/** + * @} + */ /* end of group AXBS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/* PRS Bit Fields */ +#define AXBS_PRS_M0_MASK 0x7u +#define AXBS_PRS_M0_SHIFT 0 +#define AXBS_PRS_M0(x) (((uint32)(((uint32)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) + +/** + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32)(((uint32)(x))<CR0) +#define CMP_CR1_REG(base) ((base)->CR1) +#define CMP_FPR_REG(base) ((base)->FPR) +#define CMP_SCR_REG(base) ((base)->SCR) +#define CMP_DACCR_REG(base) ((base)->DACCR) +#define CMP_MUXCR_REG(base) ((base)->MUXCR) + +/** + * @} + */ /* end of group CMP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/* CR0 Bit Fields */ +#define CMP_CR0_HYSTCTR_MASK 0x3u +#define CMP_CR0_HYSTCTR_SHIFT 0 +#define CMP_CR0_HYSTCTR(x) (((uint8)(((uint8)(x))<CGH1) +#define CMT_CGL1_REG(base) ((base)->CGL1) +#define CMT_CGH2_REG(base) ((base)->CGH2) +#define CMT_CGL2_REG(base) ((base)->CGL2) +#define CMT_OC_REG(base) ((base)->OC) +#define CMT_MSC_REG(base) ((base)->MSC) +#define CMT_CMD1_REG(base) ((base)->CMD1) +#define CMT_CMD2_REG(base) ((base)->CMD2) +#define CMT_CMD3_REG(base) ((base)->CMD3) +#define CMT_CMD4_REG(base) ((base)->CMD4) +#define CMT_PPS_REG(base) ((base)->PPS) +#define CMT_DMA_REG(base) ((base)->DMA) + +/** + * @} + */ /* end of group CMT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/* CGH1 Bit Fields */ +#define CMT_CGH1_PH_MASK 0xFFu +#define CMT_CGH1_PH_SHIFT 0 +#define CMT_CGH1_PH(x) (((uint8)(((uint8)(x))<ACCESS16BIT.CRCL) +#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) +#define CRC_CRC_REG(base) ((base)->CRC) +#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) +#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) +#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) +#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) +#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) +#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) +#define CRC_GPOLY_REG(base) ((base)->GPOLY) +#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) +#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) +#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) +#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) +#define CRC_CTRL_REG(base) ((base)->CTRL) +#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) + +/** + * @} + */ /* end of group CRC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/* CRCL Bit Fields */ +#define CRC_CRCL_CRCL_MASK 0xFFFFu +#define CRC_CRCL_CRCL_SHIFT 0 +#define CRC_CRCL_CRCL(x) (((uint16)(((uint16)(x))<base_DHCSR_Read) +#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write) +#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR) +#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR) +#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR) + +/** + * @} + */ /* end of group CoreDebug_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CoreDebug Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group CoreDebug_Register_Masks */ + + +/* CoreDebug - Peripheral instance base addresses */ +/** Peripheral CoreDebug base pointer */ +#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u) + +/* ---------------------------------------------------------------------------- + -- CoreDebug - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros + * @{ + */ + + +/* CoreDebug - Register instance definitions */ +/* CoreDebug */ +#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR) +#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR) +#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR) +#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR) +#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR) + +/** + * @} + */ /* end of group CoreDebug_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group CoreDebug_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- DAC + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Peripheral DAC + * @{ + */ + +/** DAC - Peripheral register structure */ +typedef struct DAC_MemMap { + struct { /* offset: 0x0, array step: 0x2 */ + uint8 DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + uint8 DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + uint8 SR; /**< DAC Status Register, offset: 0x20 */ + uint8 C0; /**< DAC Control Register, offset: 0x21 */ + uint8 C1; /**< DAC Control Register 1, offset: 0x22 */ + uint8 C2; /**< DAC Control Register 2, offset: 0x23 */ +} volatile *DAC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DAC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros + * @{ + */ + + +/* DAC - Register accessors */ +#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) +#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) +#define DAC_SR_REG(base) ((base)->SR) +#define DAC_C0_REG(base) ((base)->C0) +#define DAC_C1_REG(base) ((base)->C1) +#define DAC_C2_REG(base) ((base)->C2) + +/** + * @} + */ /* end of group DAC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/* DATL Bit Fields */ +#define DAC_DATL_DATA_MASK 0xFFu +#define DAC_DATL_DATA_SHIFT 0 +#define DAC_DATL_DATA(x) (((uint8)(((uint8)(x))<CR) +#define DMA_ES_REG(base) ((base)->ES) +#define DMA_ERQ_REG(base) ((base)->ERQ) +#define DMA_EEI_REG(base) ((base)->EEI) +#define DMA_CEEI_REG(base) ((base)->CEEI) +#define DMA_SEEI_REG(base) ((base)->SEEI) +#define DMA_CERQ_REG(base) ((base)->CERQ) +#define DMA_SERQ_REG(base) ((base)->SERQ) +#define DMA_CDNE_REG(base) ((base)->CDNE) +#define DMA_SSRT_REG(base) ((base)->SSRT) +#define DMA_CERR_REG(base) ((base)->CERR) +#define DMA_CINT_REG(base) ((base)->CINT) +#define DMA_INT_REG(base) ((base)->INT) +#define DMA_ERR_REG(base) ((base)->ERR) +#define DMA_HRS_REG(base) ((base)->HRS) +#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) +#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) +#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) +#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) +#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) +#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) +#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) +#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) +#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) +#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) +#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) +#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) +#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) +#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) +#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) +#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) +#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) +#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) +#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) +#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) +#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) +#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) +#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) +#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) +#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) +#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) +#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) +#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) +#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) +#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) + +/** + * @} + */ /* end of group DMA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32)(((uint32)(x))<CHCFG[index]) + +/** + * @} + */ /* end of group DMAMUX_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/* CHCFG Bit Fields */ +#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu +#define DMAMUX_CHCFG_SOURCE_SHIFT 0 +#define DMAMUX_CHCFG_SOURCE(x) (((uint8)(((uint8)(x))<CTRL) +#define DWT_CYCCNT_REG(base) ((base)->CYCCNT) +#define DWT_CPICNT_REG(base) ((base)->CPICNT) +#define DWT_EXCCNT_REG(base) ((base)->EXCCNT) +#define DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT) +#define DWT_LSUCNT_REG(base) ((base)->LSUCNT) +#define DWT_FOLDCNT_REG(base) ((base)->FOLDCNT) +#define DWT_PCSR_REG(base) ((base)->PCSR) +#define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) +#define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) +#define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION) +#define DWT_PID4_REG(base) ((base)->PID4) +#define DWT_PID5_REG(base) ((base)->PID5) +#define DWT_PID6_REG(base) ((base)->PID6) +#define DWT_PID7_REG(base) ((base)->PID7) +#define DWT_PID0_REG(base) ((base)->PID0) +#define DWT_PID1_REG(base) ((base)->PID1) +#define DWT_PID2_REG(base) ((base)->PID2) +#define DWT_PID3_REG(base) ((base)->PID3) +#define DWT_CID0_REG(base) ((base)->CID0) +#define DWT_CID1_REG(base) ((base)->CID1) +#define DWT_CID2_REG(base) ((base)->CID2) +#define DWT_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group DWT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DWT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DWT_Register_Masks DWT Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group DWT_Register_Masks */ + + +/* DWT - Peripheral instance base addresses */ +/** Peripheral DWT base pointer */ +#define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u) + +/* ---------------------------------------------------------------------------- + -- DWT - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros + * @{ + */ + + +/* DWT - Register instance definitions */ +/* DWT */ +#define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR) +#define DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR) +#define DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR) +#define DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR) +#define DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR) +#define DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR) +#define DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR) +#define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR) +#define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0) +#define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0) +#define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0) +#define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1) +#define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1) +#define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1) +#define DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2) +#define DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2) +#define DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2) +#define DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3) +#define DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3) +#define DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3) +#define DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR) +#define DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR) +#define DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR) +#define DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR) +#define DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR) +#define DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR) +#define DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR) +#define DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR) +#define DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR) +#define DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR) +#define DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR) +#define DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR) + +/* DWT - Register array accessors */ +#define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index) +#define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index) +#define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index) + +/** + * @} + */ /* end of group DWT_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group DWT_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETB + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Peripheral ETB + * @{ + */ + +/** ETB - Peripheral register structure */ +typedef struct ETB_MemMap { + uint8 RESERVED_0[4]; + uint32 RDP; /**< RAM Depth Register, offset: 0x4 */ + uint8 RESERVED_1[4]; + uint32 STS; /**< Status Register, offset: 0xC */ + uint32 RRD; /**< RAM Read Data Register, offset: 0x10 */ + uint32 RRP; /**< RAM Read Pointer Register, offset: 0x14 */ + uint32 RWP; /**< RAM Write Pointer Register, offset: 0x18 */ + uint32 TRG; /**< Trigger Counter Register, offset: 0x1C */ + uint32 CTL; /**< Control Register, offset: 0x20 */ + uint32 RWD; /**< RAM Write Data Register, offset: 0x24 */ + uint8 RESERVED_2[728]; + uint32 FFSR; /**< Formatter and Flush Status Register, offset: 0x300 */ + uint32 FFCR; /**< Formatter and Flush Control Register, offset: 0x304 */ + uint8 RESERVED_3[3032]; + uint32 ITMISCOP0; /**< Integration Register, ITMISCOP0, offset: 0xEE0 */ + uint32 ITTRFLINACK; /**< Integration Register, ITTRFLINACK, offset: 0xEE4 */ + uint32 ITTRFLIN; /**< Integration Register, ITTRFLIN, offset: 0xEE8 */ + uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ + uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ + uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ + uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ + uint8 RESERVED_4[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_5[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_6[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_7[12]; + uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ + uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros + * @{ + */ + + +/* ETB - Register accessors */ +#define ETB_RDP_REG(base) ((base)->RDP) +#define ETB_STS_REG(base) ((base)->STS) +#define ETB_RRD_REG(base) ((base)->RRD) +#define ETB_RRP_REG(base) ((base)->RRP) +#define ETB_RWP_REG(base) ((base)->RWP) +#define ETB_TRG_REG(base) ((base)->TRG) +#define ETB_CTL_REG(base) ((base)->CTL) +#define ETB_RWD_REG(base) ((base)->RWD) +#define ETB_FFSR_REG(base) ((base)->FFSR) +#define ETB_FFCR_REG(base) ((base)->FFCR) +#define ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0) +#define ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK) +#define ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN) +#define ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0) +#define ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1) +#define ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETB_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETB_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETB_LAR_REG(base) ((base)->LAR) +#define ETB_LSR_REG(base) ((base)->LSR) +#define ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETB_DEVID_REG(base) ((base)->DEVID) +#define ETB_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETB_PIDR4_REG(base) ((base)->PIDR4) +#define ETB_PIDR5_REG(base) ((base)->PIDR5) +#define ETB_PIDR6_REG(base) ((base)->PIDR6) +#define ETB_PIDR7_REG(base) ((base)->PIDR7) +#define ETB_PIDR0_REG(base) ((base)->PIDR0) +#define ETB_PIDR1_REG(base) ((base)->PIDR1) +#define ETB_PIDR2_REG(base) ((base)->PIDR2) +#define ETB_PIDR3_REG(base) ((base)->PIDR3) +#define ETB_CIDR0_REG(base) ((base)->CIDR0) +#define ETB_CIDR1_REG(base) ((base)->CIDR1) +#define ETB_CIDR2_REG(base) ((base)->CIDR2) +#define ETB_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Masks ETB Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETB_Register_Masks */ + + +/* ETB - Peripheral instance base addresses */ +/** Peripheral ETB base pointer */ +#define ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u) + +/* ---------------------------------------------------------------------------- + -- ETB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros + * @{ + */ + + +/* ETB - Register instance definitions */ +/* ETB */ +#define ETB_RDP ETB_RDP_REG(ETB_BASE_PTR) +#define ETB_STS ETB_STS_REG(ETB_BASE_PTR) +#define ETB_RRD ETB_RRD_REG(ETB_BASE_PTR) +#define ETB_RRP ETB_RRP_REG(ETB_BASE_PTR) +#define ETB_RWP ETB_RWP_REG(ETB_BASE_PTR) +#define ETB_TRG ETB_TRG_REG(ETB_BASE_PTR) +#define ETB_CTL ETB_CTL_REG(ETB_BASE_PTR) +#define ETB_RWD ETB_RWD_REG(ETB_BASE_PTR) +#define ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR) +#define ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR) +#define ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR) +#define ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR) +#define ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR) +#define ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR) +#define ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR) +#define ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR) +#define ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR) +#define ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR) +#define ETB_LAR ETB_LAR_REG(ETB_BASE_PTR) +#define ETB_LSR ETB_LSR_REG(ETB_BASE_PTR) +#define ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR) +#define ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR) +#define ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR) +#define ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR) +#define ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR) +#define ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR) +#define ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR) +#define ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR) +#define ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR) +#define ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR) +#define ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR) +#define ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR) +#define ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR) +#define ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR) +#define ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR) + +/** + * @} + */ /* end of group ETB_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETB_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETF + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Peripheral ETF + * @{ + */ + +/** ETF - Peripheral register structure */ +typedef struct ETF_MemMap { + uint32 FCR; /**< Funnel Control Register, offset: 0x0 */ + uint32 PCR; /**< Priority Control Register, offset: 0x4 */ + uint8 RESERVED_0[3812]; + uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ + uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ + uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ + uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ + uint8 RESERVED_1[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_2[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_3[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_4[12]; + uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ + uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETF_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros + * @{ + */ + + +/* ETF - Register accessors */ +#define ETF_FCR_REG(base) ((base)->FCR) +#define ETF_PCR_REG(base) ((base)->PCR) +#define ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0) +#define ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1) +#define ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETF_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETF_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETF_LAR_REG(base) ((base)->LAR) +#define ETF_LSR_REG(base) ((base)->LSR) +#define ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETF_DEVID_REG(base) ((base)->DEVID) +#define ETF_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETF_PIDR4_REG(base) ((base)->PIDR4) +#define ETF_PIDR5_REG(base) ((base)->PIDR5) +#define ETF_PIDR6_REG(base) ((base)->PIDR6) +#define ETF_PIDR7_REG(base) ((base)->PIDR7) +#define ETF_PIDR0_REG(base) ((base)->PIDR0) +#define ETF_PIDR1_REG(base) ((base)->PIDR1) +#define ETF_PIDR2_REG(base) ((base)->PIDR2) +#define ETF_PIDR3_REG(base) ((base)->PIDR3) +#define ETF_CIDR0_REG(base) ((base)->CIDR0) +#define ETF_CIDR1_REG(base) ((base)->CIDR1) +#define ETF_CIDR2_REG(base) ((base)->CIDR2) +#define ETF_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Masks ETF Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETF_Register_Masks */ + + +/* ETF - Peripheral instance base addresses */ +/** Peripheral ETF base pointer */ +#define ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u) + +/* ---------------------------------------------------------------------------- + -- ETF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros + * @{ + */ + + +/* ETF - Register instance definitions */ +/* ETF */ +#define ETF_FCR ETF_FCR_REG(ETF_BASE_PTR) +#define ETF_PCR ETF_PCR_REG(ETF_BASE_PTR) +#define ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR) +#define ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR) +#define ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR) +#define ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR) +#define ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR) +#define ETF_LAR ETF_LAR_REG(ETF_BASE_PTR) +#define ETF_LSR ETF_LSR_REG(ETF_BASE_PTR) +#define ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR) +#define ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR) +#define ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR) +#define ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR) +#define ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR) +#define ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR) +#define ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR) +#define ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR) +#define ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR) +#define ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR) +#define ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR) +#define ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR) +#define ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR) +#define ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR) +#define ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR) + +/** + * @} + */ /* end of group ETF_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETF_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ETM + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Peripheral ETM + * @{ + */ + +/** ETM - Peripheral register structure */ +typedef struct ETM_MemMap { + uint32 CR; /**< Main Control Register, offset: 0x0 */ + uint32 CCR; /**< Configuration Code Register, offset: 0x4 */ + uint32 TRIGGER; /**< Trigger Event Register, offset: 0x8 */ + uint8 RESERVED_0[4]; + uint32 SR; /**< ETM Status Register, offset: 0x10 */ + uint32 SCR; /**< System Configuration Register, offset: 0x14 */ + uint8 RESERVED_1[8]; + uint32 EEVR; /**< Trace Enable Event Register, offset: 0x20 */ + uint32 TECR1; /**< Trace Enable Control 1 Register, offset: 0x24 */ + uint32 FFLR; /**< FIFOFULL Level Register, offset: 0x28 */ + uint8 RESERVED_2[276]; + uint32 CNTRLDVR1; /**< Free-running counter reload value, offset: 0x140 */ + uint8 RESERVED_3[156]; + uint32 SYNCFR; /**< Synchronization Frequency Register, offset: 0x1E0 */ + uint32 IDR; /**< ID Register, offset: 0x1E4 */ + uint32 CCER; /**< Configuration Code Extension Register, offset: 0x1E8 */ + uint8 RESERVED_4[4]; + uint32 TESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register, offset: 0x1F0 */ + uint8 RESERVED_5[4]; + uint32 TSEVR; /**< Timestamp Event Register, offset: 0x1F8 */ + uint8 RESERVED_6[4]; + uint32 TRACEIDR; /**< CoreSight Trace ID Register, offset: 0x200 */ + uint8 RESERVED_7[4]; + uint32 IDR2; /**< ETM ID Register 2, offset: 0x208 */ + uint8 RESERVED_8[264]; + uint32 PDSR; /**< Device Power-Down Status Register, offset: 0x314 */ + uint8 RESERVED_9[3016]; + uint32 ITMISCIN; /**< Integration Test Miscelaneous Inputs Register, offset: 0xEE0 */ + uint8 RESERVED_10[4]; + uint32 ITTRIGOUT; /**< Integration Test Trigger Out Register, offset: 0xEE8 */ + uint8 RESERVED_11[4]; + uint32 ITATBCTR2; /**< ETM Integration Test ATB Control 2 Register, offset: 0xEF0 */ + uint8 RESERVED_12[4]; + uint32 ITATBCTR0; /**< ETM Integration Test ATB Control 0 Register, offset: 0xEF8 */ + uint8 RESERVED_13[4]; + uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8 RESERVED_14[156]; + uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ + uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ + uint8 RESERVED_15[8]; + uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ + uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ + uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ + uint8 RESERVED_16[16]; + uint32 DEVTYPE; /**< CoreSight Device Type Register, offset: 0xFCC */ + uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ + uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ + uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ + uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ + uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ + uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ + uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ + uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ + uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ + uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ + uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ + uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ +} volatile *ETM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ETM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros + * @{ + */ + + +/* ETM - Register accessors */ +#define ETM_CR_REG(base) ((base)->CR) +#define ETM_CCR_REG(base) ((base)->CCR) +#define ETM_TRIGGER_REG(base) ((base)->TRIGGER) +#define ETM_SR_REG(base) ((base)->SR) +#define ETM_SCR_REG(base) ((base)->SCR) +#define ETM_EEVR_REG(base) ((base)->EEVR) +#define ETM_TECR1_REG(base) ((base)->TECR1) +#define ETM_FFLR_REG(base) ((base)->FFLR) +#define ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1) +#define ETM_SYNCFR_REG(base) ((base)->SYNCFR) +#define ETM_IDR_REG(base) ((base)->IDR) +#define ETM_CCER_REG(base) ((base)->CCER) +#define ETM_TESSEICR_REG(base) ((base)->TESSEICR) +#define ETM_TSEVR_REG(base) ((base)->TSEVR) +#define ETM_TRACEIDR_REG(base) ((base)->TRACEIDR) +#define ETM_IDR2_REG(base) ((base)->IDR2) +#define ETM_PDSR_REG(base) ((base)->PDSR) +#define ETM_ITMISCIN_REG(base) ((base)->ITMISCIN) +#define ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT) +#define ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define ETM_ITCTRL_REG(base) ((base)->ITCTRL) +#define ETM_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define ETM_LAR_REG(base) ((base)->LAR) +#define ETM_LSR_REG(base) ((base)->LSR) +#define ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) +#define ETM_DEVTYPE_REG(base) ((base)->DEVTYPE) +#define ETM_PIDR4_REG(base) ((base)->PIDR4) +#define ETM_PIDR5_REG(base) ((base)->PIDR5) +#define ETM_PIDR6_REG(base) ((base)->PIDR6) +#define ETM_PIDR7_REG(base) ((base)->PIDR7) +#define ETM_PIDR0_REG(base) ((base)->PIDR0) +#define ETM_PIDR1_REG(base) ((base)->PIDR1) +#define ETM_PIDR2_REG(base) ((base)->PIDR2) +#define ETM_PIDR3_REG(base) ((base)->PIDR3) +#define ETM_CIDR0_REG(base) ((base)->CIDR0) +#define ETM_CIDR1_REG(base) ((base)->CIDR1) +#define ETM_CIDR2_REG(base) ((base)->CIDR2) +#define ETM_CIDR3_REG(base) ((base)->CIDR3) + +/** + * @} + */ /* end of group ETM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ETM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Masks ETM Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ETM_Register_Masks */ + + +/* ETM - Peripheral instance base addresses */ +/** Peripheral ETM base pointer */ +#define ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u) + +/* ---------------------------------------------------------------------------- + -- ETM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros + * @{ + */ + + +/* ETM - Register instance definitions */ +/* ETM */ +#define ETMCR ETM_CR_REG(ETM_BASE_PTR) +#define ETMCCR ETM_CCR_REG(ETM_BASE_PTR) +#define ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR) +#define ETMSR ETM_SR_REG(ETM_BASE_PTR) +#define ETMSCR ETM_SCR_REG(ETM_BASE_PTR) +#define ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR) +#define ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR) +#define ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR) +#define ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR) +#define ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR) +#define ETMIDR ETM_IDR_REG(ETM_BASE_PTR) +#define ETMCCER ETM_CCER_REG(ETM_BASE_PTR) +#define ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR) +#define ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR) +#define ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR) +#define ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR) +#define ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR) +#define ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR) +#define ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR) +#define ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR) +#define ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR) +#define ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR) +#define ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR) +#define ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR) +#define ETMLAR ETM_LAR_REG(ETM_BASE_PTR) +#define ETMLSR ETM_LSR_REG(ETM_BASE_PTR) +#define ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR) +#define ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR) +#define ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR) +#define ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR) +#define ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR) +#define ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR) +#define ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR) +#define ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR) +#define ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR) +#define ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR) +#define ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR) +#define ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR) +#define ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR) +#define ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR) + +/** + * @} + */ /* end of group ETM_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ETM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- EWM + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Peripheral EWM + * @{ + */ + +/** EWM - Peripheral register structure */ +typedef struct EWM_MemMap { + uint8 CTRL; /**< Control Register, offset: 0x0 */ + uint8 SERV; /**< Service Register, offset: 0x1 */ + uint8 CMPL; /**< Compare Low Register, offset: 0x2 */ + uint8 CMPH; /**< Compare High Register, offset: 0x3 */ +} volatile *EWM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- EWM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros + * @{ + */ + + +/* EWM - Register accessors */ +#define EWM_CTRL_REG(base) ((base)->CTRL) +#define EWM_SERV_REG(base) ((base)->SERV) +#define EWM_CMPL_REG(base) ((base)->CMPL) +#define EWM_CMPH_REG(base) ((base)->CMPH) + +/** + * @} + */ /* end of group EWM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EWM_CTRL_EWMEN_MASK 0x1u +#define EWM_CTRL_EWMEN_SHIFT 0 +#define EWM_CTRL_ASSIN_MASK 0x2u +#define EWM_CTRL_ASSIN_SHIFT 1 +#define EWM_CTRL_INEN_MASK 0x4u +#define EWM_CTRL_INEN_SHIFT 2 +#define EWM_CTRL_INTEN_MASK 0x8u +#define EWM_CTRL_INTEN_SHIFT 3 +/* SERV Bit Fields */ +#define EWM_SERV_SERVICE_MASK 0xFFu +#define EWM_SERV_SERVICE_SHIFT 0 +#define EWM_SERV_SERVICE(x) (((uint8)(((uint8)(x))<CS[index].CSAR) +#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) +#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) +#define FB_CSPMCR_REG(base) ((base)->CSPMCR) + +/** + * @} + */ /* end of group FB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/* CSAR Bit Fields */ +#define FB_CSAR_BA_MASK 0xFFFF0000u +#define FB_CSAR_BA_SHIFT 16 +#define FB_CSAR_BA(x) (((uint32)(((uint32)(x))<PFAPR) +#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) +#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) +#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) +#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) +#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) + +/** + * @} + */ /* end of group FMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/* PFAPR Bit Fields */ +#define FMC_PFAPR_M0AP_MASK 0x3u +#define FMC_PFAPR_M0AP_SHIFT 0 +#define FMC_PFAPR_M0AP(x) (((uint32)(((uint32)(x))<CTRL) +#define FPB_REMAP_REG(base) ((base)->REMAP) +#define FPB_COMP_REG(base,index) ((base)->COMP[index]) +#define FPB_PID4_REG(base) ((base)->PID4) +#define FPB_PID5_REG(base) ((base)->PID5) +#define FPB_PID6_REG(base) ((base)->PID6) +#define FPB_PID7_REG(base) ((base)->PID7) +#define FPB_PID0_REG(base) ((base)->PID0) +#define FPB_PID1_REG(base) ((base)->PID1) +#define FPB_PID2_REG(base) ((base)->PID2) +#define FPB_PID3_REG(base) ((base)->PID3) +#define FPB_CID0_REG(base) ((base)->CID0) +#define FPB_CID1_REG(base) ((base)->CID1) +#define FPB_CID2_REG(base) ((base)->CID2) +#define FPB_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group FPB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FPB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FPB_Register_Masks FPB Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group FPB_Register_Masks */ + + +/* FPB - Peripheral instance base addresses */ +/** Peripheral FPB base pointer */ +#define FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u) + +/* ---------------------------------------------------------------------------- + -- FPB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros + * @{ + */ + + +/* FPB - Register instance definitions */ +/* FPB */ +#define FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR) +#define FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR) +#define FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0) +#define FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1) +#define FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2) +#define FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3) +#define FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4) +#define FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5) +#define FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6) +#define FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7) +#define FP_PID4 FPB_PID4_REG(FPB_BASE_PTR) +#define FP_PID5 FPB_PID5_REG(FPB_BASE_PTR) +#define FP_PID6 FPB_PID6_REG(FPB_BASE_PTR) +#define FP_PID7 FPB_PID7_REG(FPB_BASE_PTR) +#define FP_PID0 FPB_PID0_REG(FPB_BASE_PTR) +#define FP_PID1 FPB_PID1_REG(FPB_BASE_PTR) +#define FP_PID2 FPB_PID2_REG(FPB_BASE_PTR) +#define FP_PID3 FPB_PID3_REG(FPB_BASE_PTR) +#define FP_CID0 FPB_CID0_REG(FPB_BASE_PTR) +#define FP_CID1 FPB_CID1_REG(FPB_BASE_PTR) +#define FP_CID2 FPB_CID2_REG(FPB_BASE_PTR) +#define FP_CID3 FPB_CID3_REG(FPB_BASE_PTR) + +/* FPB - Register array accessors */ +#define FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index) + +/** + * @} + */ /* end of group FPB_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group FPB_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- FTFL + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Peripheral FTFL + * @{ + */ + +/** FTFL - Peripheral register structure */ +typedef struct FTFL_MemMap { + uint8 FSTAT; /**< Flash Status Register, offset: 0x0 */ + uint8 FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + uint8 FSEC; /**< Flash Security Register, offset: 0x2 */ + uint8 FOPT; /**< Flash Option Register, offset: 0x3 */ + uint8 FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + uint8 FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + uint8 FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + uint8 FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + uint8 FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + uint8 FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + uint8 FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + uint8 FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + uint8 FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + uint8 FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + uint8 FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + uint8 FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + uint8 FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + uint8 FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + uint8 FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + uint8 FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8 RESERVED_0[2]; + uint8 FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ + uint8 FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ +} volatile *FTFL_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- FTFL - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros + * @{ + */ + + +/* FTFL - Register accessors */ +#define FTFL_FSTAT_REG(base) ((base)->FSTAT) +#define FTFL_FCNFG_REG(base) ((base)->FCNFG) +#define FTFL_FSEC_REG(base) ((base)->FSEC) +#define FTFL_FOPT_REG(base) ((base)->FOPT) +#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) +#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) +#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) +#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) +#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) +#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) +#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) +#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) +#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) +#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) +#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) +#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) +#define FTFL_FPROT3_REG(base) ((base)->FPROT3) +#define FTFL_FPROT2_REG(base) ((base)->FPROT2) +#define FTFL_FPROT1_REG(base) ((base)->FPROT1) +#define FTFL_FPROT0_REG(base) ((base)->FPROT0) +#define FTFL_FEPROT_REG(base) ((base)->FEPROT) +#define FTFL_FDPROT_REG(base) ((base)->FDPROT) + +/** + * @} + */ /* end of group FTFL_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTFL Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Masks FTFL Register Masks + * @{ + */ + +/* FSTAT Bit Fields */ +#define FTFL_FSTAT_MGSTAT0_MASK 0x1u +#define FTFL_FSTAT_MGSTAT0_SHIFT 0 +#define FTFL_FSTAT_FPVIOL_MASK 0x10u +#define FTFL_FSTAT_FPVIOL_SHIFT 4 +#define FTFL_FSTAT_ACCERR_MASK 0x20u +#define FTFL_FSTAT_ACCERR_SHIFT 5 +#define FTFL_FSTAT_RDCOLERR_MASK 0x40u +#define FTFL_FSTAT_RDCOLERR_SHIFT 6 +#define FTFL_FSTAT_CCIF_MASK 0x80u +#define FTFL_FSTAT_CCIF_SHIFT 7 +/* FCNFG Bit Fields */ +#define FTFL_FCNFG_EEERDY_MASK 0x1u +#define FTFL_FCNFG_EEERDY_SHIFT 0 +#define FTFL_FCNFG_RAMRDY_MASK 0x2u +#define FTFL_FCNFG_RAMRDY_SHIFT 1 +#define FTFL_FCNFG_PFLSH_MASK 0x4u +#define FTFL_FCNFG_PFLSH_SHIFT 2 +#define FTFL_FCNFG_SWAP_MASK 0x8u +#define FTFL_FCNFG_SWAP_SHIFT 3 +#define FTFL_FCNFG_ERSSUSP_MASK 0x10u +#define FTFL_FCNFG_ERSSUSP_SHIFT 4 +#define FTFL_FCNFG_ERSAREQ_MASK 0x20u +#define FTFL_FCNFG_ERSAREQ_SHIFT 5 +#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u +#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 +#define FTFL_FCNFG_CCIE_MASK 0x80u +#define FTFL_FCNFG_CCIE_SHIFT 7 +/* FSEC Bit Fields */ +#define FTFL_FSEC_SEC_MASK 0x3u +#define FTFL_FSEC_SEC_SHIFT 0 +#define FTFL_FSEC_SEC(x) (((uint8)(((uint8)(x))<SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) +#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FMS_REG(base) ((base)->FMS) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/** + * @} + */ /* end of group FTM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32)(((uint32)(x))<PDOR) +#define GPIO_PSOR_REG(base) ((base)->PSOR) +#define GPIO_PCOR_REG(base) ((base)->PCOR) +#define GPIO_PTOR_REG(base) ((base)->PTOR) +#define GPIO_PDIR_REG(base) ((base)->PDIR) +#define GPIO_PDDR_REG(base) ((base)->PDDR) + +/** + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* PDOR Bit Fields */ +#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu +#define GPIO_PDOR_PDO_SHIFT 0 +#define GPIO_PDOR_PDO(x) (((uint32)(((uint32)(x))<A1) +#define I2C_F_REG(base) ((base)->F) +#define I2C_C1_REG(base) ((base)->C1) +#define I2C_S_REG(base) ((base)->S) +#define I2C_D_REG(base) ((base)->D) +#define I2C_C2_REG(base) ((base)->C2) +#define I2C_FLT_REG(base) ((base)->FLT) +#define I2C_RA_REG(base) ((base)->RA) +#define I2C_SMB_REG(base) ((base)->SMB) +#define I2C_A2_REG(base) ((base)->A2) +#define I2C_SLTH_REG(base) ((base)->SLTH) +#define I2C_SLTL_REG(base) ((base)->SLTL) + +/** + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* A1 Bit Fields */ +#define I2C_A1_AD_MASK 0xFEu +#define I2C_A1_AD_SHIFT 1 +#define I2C_A1_AD(x) (((uint8)(((uint8)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) +#define I2S_MCR_REG(base) ((base)->MCR) +#define I2S_MDR_REG(base) ((base)->MDR) + +/** + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x7u +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32)(((uint32)(x))<STIM_READ[index2]) +#define ITM_STIM_WRITE_REG(base,index2) ((base)->STIM_WRITE[index2]) +#define ITM_TER_REG(base) ((base)->TER) +#define ITM_TPR_REG(base) ((base)->TPR) +#define ITM_TCR_REG(base) ((base)->TCR) +#define ITM_LAR_REG(base) ((base)->LAR) +#define ITM_LSR_REG(base) ((base)->LSR) +#define ITM_PID4_REG(base) ((base)->PID4) +#define ITM_PID5_REG(base) ((base)->PID5) +#define ITM_PID6_REG(base) ((base)->PID6) +#define ITM_PID7_REG(base) ((base)->PID7) +#define ITM_PID0_REG(base) ((base)->PID0) +#define ITM_PID1_REG(base) ((base)->PID1) +#define ITM_PID2_REG(base) ((base)->PID2) +#define ITM_PID3_REG(base) ((base)->PID3) +#define ITM_CID0_REG(base) ((base)->CID0) +#define ITM_CID1_REG(base) ((base)->CID1) +#define ITM_CID2_REG(base) ((base)->CID2) +#define ITM_CID3_REG(base) ((base)->CID3) + +/** + * @} + */ /* end of group ITM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ITM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ITM_Register_Masks ITM Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group ITM_Register_Masks */ + + +/* ITM - Peripheral instance base addresses */ +/** Peripheral ITM base pointer */ +#define ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u) + +/* ---------------------------------------------------------------------------- + -- ITM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros + * @{ + */ + + +/* ITM - Register instance definitions */ +/* ITM */ +#define ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0) +#define ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0) +#define ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1) +#define ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1) +#define ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2) +#define ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2) +#define ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3) +#define ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3) +#define ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4) +#define ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4) +#define ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5) +#define ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5) +#define ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6) +#define ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6) +#define ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7) +#define ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7) +#define ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8) +#define ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8) +#define ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9) +#define ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9) +#define ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10) +#define ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10) +#define ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11) +#define ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11) +#define ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12) +#define ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12) +#define ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13) +#define ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13) +#define ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14) +#define ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14) +#define ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15) +#define ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15) +#define ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16) +#define ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16) +#define ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17) +#define ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17) +#define ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18) +#define ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18) +#define ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19) +#define ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19) +#define ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20) +#define ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20) +#define ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21) +#define ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21) +#define ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22) +#define ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22) +#define ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23) +#define ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23) +#define ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24) +#define ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24) +#define ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25) +#define ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25) +#define ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26) +#define ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26) +#define ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27) +#define ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27) +#define ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28) +#define ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28) +#define ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29) +#define ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29) +#define ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30) +#define ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30) +#define ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31) +#define ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31) +#define ITM_TER ITM_TER_REG(ITM_BASE_PTR) +#define ITM_TPR ITM_TPR_REG(ITM_BASE_PTR) +#define ITM_TCR ITM_TCR_REG(ITM_BASE_PTR) +#define ITM_LAR ITM_LAR_REG(ITM_BASE_PTR) +#define ITM_LSR ITM_LSR_REG(ITM_BASE_PTR) +#define ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR) +#define ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR) +#define ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR) +#define ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR) +#define ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR) +#define ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR) +#define ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR) +#define ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR) +#define ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR) +#define ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR) +#define ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR) +#define ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR) + +/* ITM - Register array accessors */ +#define ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2) +#define ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2) + +/** + * @} + */ /* end of group ITM_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group ITM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- LLWU + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Peripheral LLWU + * @{ + */ + +/** LLWU - Peripheral register structure */ +typedef struct LLWU_MemMap { + uint8 PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ + uint8 PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ + uint8 PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ + uint8 PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ + uint8 ME; /**< LLWU Module Enable Register, offset: 0x4 */ + uint8 F1; /**< LLWU Flag 1 Register, offset: 0x5 */ + uint8 F2; /**< LLWU Flag 2 Register, offset: 0x6 */ + uint8 F3; /**< LLWU Flag 3 Register, offset: 0x7 */ + uint8 FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ + uint8 FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ + uint8 RST; /**< LLWU Reset Enable Register, offset: 0xA */ +} volatile *LLWU_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- LLWU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros + * @{ + */ + + +/* LLWU - Register accessors */ +#define LLWU_PE1_REG(base) ((base)->PE1) +#define LLWU_PE2_REG(base) ((base)->PE2) +#define LLWU_PE3_REG(base) ((base)->PE3) +#define LLWU_PE4_REG(base) ((base)->PE4) +#define LLWU_ME_REG(base) ((base)->ME) +#define LLWU_F1_REG(base) ((base)->F1) +#define LLWU_F2_REG(base) ((base)->F2) +#define LLWU_F3_REG(base) ((base)->F3) +#define LLWU_FILT1_REG(base) ((base)->FILT1) +#define LLWU_FILT2_REG(base) ((base)->FILT2) +#define LLWU_RST_REG(base) ((base)->RST) + +/** + * @} + */ /* end of group LLWU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/* PE1 Bit Fields */ +#define LLWU_PE1_WUPE0_MASK 0x3u +#define LLWU_PE1_WUPE0_SHIFT 0 +#define LLWU_PE1_WUPE0(x) (((uint8)(((uint8)(x))<CSR) +#define LPTMR_PSR_REG(base) ((base)->PSR) +#define LPTMR_CMR_REG(base) ((base)->CMR) +#define LPTMR_CNR_REG(base) ((base)->CNR) + +/** + * @} + */ /* end of group LPTMR_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define LPTMR_CSR_TEN_MASK 0x1u +#define LPTMR_CSR_TEN_SHIFT 0 +#define LPTMR_CSR_TMS_MASK 0x2u +#define LPTMR_CSR_TMS_SHIFT 1 +#define LPTMR_CSR_TFC_MASK 0x4u +#define LPTMR_CSR_TFC_SHIFT 2 +#define LPTMR_CSR_TPP_MASK 0x8u +#define LPTMR_CSR_TPP_SHIFT 3 +#define LPTMR_CSR_TPS_MASK 0x30u +#define LPTMR_CSR_TPS_SHIFT 4 +#define LPTMR_CSR_TPS(x) (((uint32)(((uint32)(x))<C1) +#define MCG_C2_REG(base) ((base)->C2) +#define MCG_C3_REG(base) ((base)->C3) +#define MCG_C4_REG(base) ((base)->C4) +#define MCG_C5_REG(base) ((base)->C5) +#define MCG_C6_REG(base) ((base)->C6) +#define MCG_S_REG(base) ((base)->S) +#define MCG_SC_REG(base) ((base)->SC) +#define MCG_ATCVH_REG(base) ((base)->ATCVH) +#define MCG_ATCVL_REG(base) ((base)->ATCVL) +#define MCG_C7_REG(base) ((base)->C7) +#define MCG_C8_REG(base) ((base)->C8) + +/** + * @} + */ /* end of group MCG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/* C1 Bit Fields */ +#define MCG_C1_IREFSTEN_MASK 0x1u +#define MCG_C1_IREFSTEN_SHIFT 0 +#define MCG_C1_IRCLKEN_MASK 0x2u +#define MCG_C1_IRCLKEN_SHIFT 1 +#define MCG_C1_IREFS_MASK 0x4u +#define MCG_C1_IREFS_SHIFT 2 +#define MCG_C1_FRDIV_MASK 0x38u +#define MCG_C1_FRDIV_SHIFT 3 +#define MCG_C1_FRDIV(x) (((uint8)(((uint8)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_CR_REG(base) ((base)->CR) +#define MCM_ISR_REG(base) ((base)->ISR) +#define MCM_ETBCC_REG(base) ((base)->ETBCC) +#define MCM_ETBRL_REG(base) ((base)->ETBRL) +#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) +#define MCM_PID_REG(base) ((base)->PID) + +/** + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16)(((uint16)(x))<CESR) +#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) +#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) +#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) +#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) + +/** + * @} + */ /* end of group MPU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MPU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MPU_Register_Masks MPU Register Masks + * @{ + */ + +/* CESR Bit Fields */ +#define MPU_CESR_VLD_MASK 0x1u +#define MPU_CESR_VLD_SHIFT 0 +#define MPU_CESR_NRGD_MASK 0xF00u +#define MPU_CESR_NRGD_SHIFT 8 +#define MPU_CESR_NRGD(x) (((uint32)(((uint32)(x))<BACKKEY3) +#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) +#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) +#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) +#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) +#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) +#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) +#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) +#define NV_FPROT3_REG(base) ((base)->FPROT3) +#define NV_FPROT2_REG(base) ((base)->FPROT2) +#define NV_FPROT1_REG(base) ((base)->FPROT1) +#define NV_FPROT0_REG(base) ((base)->FPROT0) +#define NV_FSEC_REG(base) ((base)->FSEC) +#define NV_FOPT_REG(base) ((base)->FOPT) +#define NV_FEPROT_REG(base) ((base)->FEPROT) +#define NV_FDPROT_REG(base) ((base)->FDPROT) + +/** + * @} + */ /* end of group NV_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/* BACKKEY3 Bit Fields */ +#define NV_BACKKEY3_KEY_MASK 0xFFu +#define NV_BACKKEY3_KEY_SHIFT 0 +#define NV_BACKKEY3_KEY(x) (((uint8)(((uint8)(x))<ISER[index]) +#define NVIC_ICER_REG(base,index) ((base)->ICER[index]) +#define NVIC_ISPR_REG(base,index) ((base)->ISPR[index]) +#define NVIC_ICPR_REG(base,index) ((base)->ICPR[index]) +#define NVIC_IABR_REG(base,index) ((base)->IABR[index]) +#define NVIC_IP_REG(base,index) ((base)->IP[index]) +#define NVIC_STIR_REG(base,index) ((base)->STIR[index]) + +/** + * @} + */ /* end of group NVIC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- NVIC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NVIC_Register_Masks NVIC Register Masks + * @{ + */ + +/* ISER Bit Fields */ +#define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu +#define NVIC_ISER_SETENA_SHIFT 0 +#define NVIC_ISER_SETENA(x) (((uint32)(((uint32)(x))<CR) + +/** + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define OSC_CR_SC16P_MASK 0x1u +#define OSC_CR_SC16P_SHIFT 0 +#define OSC_CR_SC8P_MASK 0x2u +#define OSC_CR_SC8P_SHIFT 1 +#define OSC_CR_SC4P_MASK 0x4u +#define OSC_CR_SC4P_SHIFT 2 +#define OSC_CR_SC2P_MASK 0x8u +#define OSC_CR_SC2P_SHIFT 3 +#define OSC_CR_EREFSTEN_MASK 0x20u +#define OSC_CR_EREFSTEN_SHIFT 5 +#define OSC_CR_ERCLKEN_MASK 0x80u +#define OSC_CR_ERCLKEN_SHIFT 7 + +/** + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base pointer */ +#define OSC_BASE_PTR ((OSC_MemMapPtr)0x40065000u) + +/* ---------------------------------------------------------------------------- + -- OSC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros + * @{ + */ + + +/* OSC - Register instance definitions */ +/* OSC */ +#define OSC_CR OSC_CR_REG(OSC_BASE_PTR) + +/** + * @} + */ /* end of group OSC_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group OSC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PDB + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Peripheral PDB + * @{ + */ + +/** PDB - Peripheral register structure */ +typedef struct PDB_MemMap { + uint32 SC; /**< Status and Control Register, offset: 0x0 */ + uint32 MOD; /**< Modulus Register, offset: 0x4 */ + uint32 CNT; /**< Counter Register, offset: 0x8 */ + uint32 IDLY; /**< Interrupt Delay Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + uint32 C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */ + uint32 S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */ + uint32 DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8 RESERVED_0[24]; + } CH[2]; + uint8 RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + uint32 INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */ + uint32 INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8 RESERVED_1[48]; + uint32 POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ + uint32 PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ +} volatile *PDB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PDB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros + * @{ + */ + + +/* PDB - Register accessors */ +#define PDB_SC_REG(base) ((base)->SC) +#define PDB_MOD_REG(base) ((base)->MOD) +#define PDB_CNT_REG(base) ((base)->CNT) +#define PDB_IDLY_REG(base) ((base)->IDLY) +#define PDB_C1_REG(base,index) ((base)->CH[index].C1) +#define PDB_S_REG(base,index) ((base)->CH[index].S) +#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) +#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) +#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) +#define PDB_POEN_REG(base) ((base)->POEN) +#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) + +/** + * @} + */ /* end of group PDB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define PDB_SC_LDOK_MASK 0x1u +#define PDB_SC_LDOK_SHIFT 0 +#define PDB_SC_CONT_MASK 0x2u +#define PDB_SC_CONT_SHIFT 1 +#define PDB_SC_MULT_MASK 0xCu +#define PDB_SC_MULT_SHIFT 2 +#define PDB_SC_MULT(x) (((uint32)(((uint32)(x))<MCR) +#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) +#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) +#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) +#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) + +/** + * @} + */ /* end of group PIT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define PIT_MCR_FRZ_MASK 0x1u +#define PIT_MCR_FRZ_SHIFT 0 +#define PIT_MCR_MDIS_MASK 0x2u +#define PIT_MCR_MDIS_SHIFT 1 +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32)(((uint32)(x))<LVDSC1) +#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) +#define PMC_REGSC_REG(base) ((base)->REGSC) + +/** + * @} + */ /* end of group PMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/* LVDSC1 Bit Fields */ +#define PMC_LVDSC1_LVDV_MASK 0x3u +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8)(((uint8)(x))<PCR[index]) +#define PORT_GPCLR_REG(base) ((base)->GPCLR) +#define PORT_GPCHR_REG(base) ((base)->GPCHR) +#define PORT_ISFR_REG(base) ((base)->ISFR) +#define PORT_DFER_REG(base) ((base)->DFER) +#define PORT_DFCR_REG(base) ((base)->DFCR) +#define PORT_DFWR_REG(base) ((base)->DFWR) + +/** + * @} + */ /* end of group PORT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/* PCR Bit Fields */ +#define PORT_PCR_PS_MASK 0x1u +#define PORT_PCR_PS_SHIFT 0 +#define PORT_PCR_PE_MASK 0x2u +#define PORT_PCR_PE_SHIFT 1 +#define PORT_PCR_SRE_MASK 0x4u +#define PORT_PCR_SRE_SHIFT 2 +#define PORT_PCR_PFE_MASK 0x10u +#define PORT_PCR_PFE_SHIFT 4 +#define PORT_PCR_ODE_MASK 0x20u +#define PORT_PCR_ODE_SHIFT 5 +#define PORT_PCR_DSE_MASK 0x40u +#define PORT_PCR_DSE_SHIFT 6 +#define PORT_PCR_MUX_MASK 0x700u +#define PORT_PCR_MUX_SHIFT 8 +#define PORT_PCR_MUX(x) (((uint32)(((uint32)(x))<SRS0) +#define RCM_SRS1_REG(base) ((base)->SRS1) +#define RCM_RPFC_REG(base) ((base)->RPFC) +#define RCM_RPFW_REG(base) ((base)->RPFW) +#define RCM_MR_REG(base) ((base)->MR) + +/** + * @} + */ /* end of group RCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/* SRS0 Bit Fields */ +#define RCM_SRS0_WAKEUP_MASK 0x1u +#define RCM_SRS0_WAKEUP_SHIFT 0 +#define RCM_SRS0_LVD_MASK 0x2u +#define RCM_SRS0_LVD_SHIFT 1 +#define RCM_SRS0_LOC_MASK 0x4u +#define RCM_SRS0_LOC_SHIFT 2 +#define RCM_SRS0_LOL_MASK 0x8u +#define RCM_SRS0_LOL_SHIFT 3 +#define RCM_SRS0_WDOG_MASK 0x20u +#define RCM_SRS0_WDOG_SHIFT 5 +#define RCM_SRS0_PIN_MASK 0x40u +#define RCM_SRS0_PIN_SHIFT 6 +#define RCM_SRS0_POR_MASK 0x80u +#define RCM_SRS0_POR_SHIFT 7 +/* SRS1 Bit Fields */ +#define RCM_SRS1_JTAG_MASK 0x1u +#define RCM_SRS1_JTAG_SHIFT 0 +#define RCM_SRS1_LOCKUP_MASK 0x2u +#define RCM_SRS1_LOCKUP_SHIFT 1 +#define RCM_SRS1_SW_MASK 0x4u +#define RCM_SRS1_SW_SHIFT 2 +#define RCM_SRS1_MDM_AP_MASK 0x8u +#define RCM_SRS1_MDM_AP_SHIFT 3 +#define RCM_SRS1_EZPT_MASK 0x10u +#define RCM_SRS1_EZPT_SHIFT 4 +#define RCM_SRS1_SACKERR_MASK 0x20u +#define RCM_SRS1_SACKERR_SHIFT 5 +/* RPFC Bit Fields */ +#define RCM_RPFC_RSTFLTSRW_MASK 0x3u +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 +#define RCM_RPFC_RSTFLTSRW(x) (((uint8)(((uint8)(x))<REG[index]) + +/** + * @} + */ /* end of group RFSYS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFSYS_REG_LL_MASK 0xFFu +#define RFSYS_REG_LL_SHIFT 0 +#define RFSYS_REG_LL(x) (((uint32)(((uint32)(x))<REG[index]) + +/** + * @} + */ /* end of group RFVBAT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFVBAT_REG_LL_MASK 0xFFu +#define RFVBAT_REG_LL_SHIFT 0 +#define RFVBAT_REG_LL(x) (((uint32)(((uint32)(x))<TSR) +#define RTC_TPR_REG(base) ((base)->TPR) +#define RTC_TAR_REG(base) ((base)->TAR) +#define RTC_TCR_REG(base) ((base)->TCR) +#define RTC_CR_REG(base) ((base)->CR) +#define RTC_SR_REG(base) ((base)->SR) +#define RTC_LR_REG(base) ((base)->LR) +#define RTC_IER_REG(base) ((base)->IER) +#define RTC_WAR_REG(base) ((base)->WAR) +#define RTC_RAR_REG(base) ((base)->RAR) + +/** + * @} + */ /* end of group RTC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/* TSR Bit Fields */ +#define RTC_TSR_TSR_MASK 0xFFFFFFFFu +#define RTC_TSR_TSR_SHIFT 0 +#define RTC_TSR_TSR(x) (((uint32)(((uint32)(x))<ACTLR) +#define SCB_CPUID_REG(base) ((base)->CPUID) +#define SCB_ICSR_REG(base) ((base)->ICSR) +#define SCB_VTOR_REG(base) ((base)->VTOR) +#define SCB_AIRCR_REG(base) ((base)->AIRCR) +#define SCB_SCR_REG(base) ((base)->SCR) +#define SCB_CCR_REG(base) ((base)->CCR) +#define SCB_SHPR1_REG(base) ((base)->SHPR1) +#define SCB_SHPR2_REG(base) ((base)->SHPR2) +#define SCB_SHPR3_REG(base) ((base)->SHPR3) +#define SCB_SHCSR_REG(base) ((base)->SHCSR) +#define SCB_CFSR_REG(base) ((base)->CFSR) +#define SCB_HFSR_REG(base) ((base)->HFSR) +#define SCB_DFSR_REG(base) ((base)->DFSR) +#define SCB_MMFAR_REG(base) ((base)->MMFAR) +#define SCB_BFAR_REG(base) ((base)->BFAR) +#define SCB_AFSR_REG(base) ((base)->AFSR) + +/** + * @} + */ /* end of group SCB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SCB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SCB_Register_Masks SCB Register Masks + * @{ + */ + +/* ACTLR Bit Fields */ +#define SCB_ACTLR_DISMCYCINT_MASK 0x1u +#define SCB_ACTLR_DISMCYCINT_SHIFT 0 +#define SCB_ACTLR_DISDEFWBUF_MASK 0x2u +#define SCB_ACTLR_DISDEFWBUF_SHIFT 1 +#define SCB_ACTLR_DISFOLD_MASK 0x4u +#define SCB_ACTLR_DISFOLD_SHIFT 2 +/* CPUID Bit Fields */ +#define SCB_CPUID_REVISION_MASK 0xFu +#define SCB_CPUID_REVISION_SHIFT 0 +#define SCB_CPUID_REVISION(x) (((uint32)(((uint32)(x))<DSADDR) +#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) +#define SDHC_CMDARG_REG(base) ((base)->CMDARG) +#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) +#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) +#define SDHC_DATPORT_REG(base) ((base)->DATPORT) +#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) +#define SDHC_PROCTL_REG(base) ((base)->PROCTL) +#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) +#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) +#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) +#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) +#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) +#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) +#define SDHC_WML_REG(base) ((base)->WML) +#define SDHC_FEVT_REG(base) ((base)->FEVT) +#define SDHC_ADMAES_REG(base) ((base)->ADMAES) +#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) +#define SDHC_VENDOR_REG(base) ((base)->VENDOR) +#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) +#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) + +/** + * @} + */ /* end of group SDHC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDHC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SDHC_Register_Masks SDHC Register Masks + * @{ + */ + +/* DSADDR Bit Fields */ +#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu +#define SDHC_DSADDR_DSADDR_SHIFT 2 +#define SDHC_DSADDR_DSADDR(x) (((uint32)(((uint32)(x))<SOPT1) +#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) +#define SIM_SOPT2_REG(base) ((base)->SOPT2) +#define SIM_SOPT4_REG(base) ((base)->SOPT4) +#define SIM_SOPT5_REG(base) ((base)->SOPT5) +#define SIM_SOPT7_REG(base) ((base)->SOPT7) +#define SIM_SDID_REG(base) ((base)->SDID) +#define SIM_SCGC1_REG(base) ((base)->SCGC1) +#define SIM_SCGC2_REG(base) ((base)->SCGC2) +#define SIM_SCGC3_REG(base) ((base)->SCGC3) +#define SIM_SCGC4_REG(base) ((base)->SCGC4) +#define SIM_SCGC5_REG(base) ((base)->SCGC5) +#define SIM_SCGC6_REG(base) ((base)->SCGC6) +#define SIM_SCGC7_REG(base) ((base)->SCGC7) +#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) +#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) +#define SIM_FCFG1_REG(base) ((base)->FCFG1) +#define SIM_FCFG2_REG(base) ((base)->FCFG2) +#define SIM_UIDH_REG(base) ((base)->UIDH) +#define SIM_UIDMH_REG(base) ((base)->UIDMH) +#define SIM_UIDML_REG(base) ((base)->UIDML) +#define SIM_UIDL_REG(base) ((base)->UIDL) + +/** + * @} + */ /* end of group SIM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* SOPT1 Bit Fields */ +#define SIM_SOPT1_RAMSIZE_MASK 0xF000u +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE(x) (((uint32)(((uint32)(x))<PMPROT) +#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) +#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) +#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) + +/** + * @} + */ /* end of group SMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/* PMPROT Bit Fields */ +#define SMC_PMPROT_AVLLS_MASK 0x2u +#define SMC_PMPROT_AVLLS_SHIFT 1 +#define SMC_PMPROT_ALLS_MASK 0x8u +#define SMC_PMPROT_ALLS_SHIFT 3 +#define SMC_PMPROT_AVLP_MASK 0x20u +#define SMC_PMPROT_AVLP_SHIFT 5 +/* PMCTRL Bit Fields */ +#define SMC_PMCTRL_STOPM_MASK 0x7u +#define SMC_PMCTRL_STOPM_SHIFT 0 +#define SMC_PMCTRL_STOPM(x) (((uint8)(((uint8)(x))<MCR) +#define SPI_TCR_REG(base) ((base)->TCR) +#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) +#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) +#define SPI_SR_REG(base) ((base)->SR) +#define SPI_RSER_REG(base) ((base)->RSER) +#define SPI_PUSHR_REG(base) ((base)->PUSHR) +#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) +#define SPI_POPR_REG(base) ((base)->POPR) +#define SPI_TXFR0_REG(base) ((base)->TXFR0) +#define SPI_TXFR1_REG(base) ((base)->TXFR1) +#define SPI_TXFR2_REG(base) ((base)->TXFR2) +#define SPI_TXFR3_REG(base) ((base)->TXFR3) +#define SPI_RXFR0_REG(base) ((base)->RXFR0) +#define SPI_RXFR1_REG(base) ((base)->RXFR1) +#define SPI_RXFR2_REG(base) ((base)->RXFR2) +#define SPI_RXFR3_REG(base) ((base)->RXFR3) + +/** + * @} + */ /* end of group SPI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define SPI_MCR_HALT_MASK 0x1u +#define SPI_MCR_HALT_SHIFT 0 +#define SPI_MCR_SMPL_PT_MASK 0x300u +#define SPI_MCR_SMPL_PT_SHIFT 8 +#define SPI_MCR_SMPL_PT(x) (((uint32)(((uint32)(x))<CSR) +#define SysTick_RVR_REG(base) ((base)->RVR) +#define SysTick_CVR_REG(base) ((base)->CVR) +#define SysTick_CALIB_REG(base) ((base)->CALIB) + +/** + * @} + */ /* end of group SysTick_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SysTick Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SysTick_Register_Masks SysTick Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define SysTick_CSR_ENABLE_MASK 0x1u +#define SysTick_CSR_ENABLE_SHIFT 0 +#define SysTick_CSR_TICKINT_MASK 0x2u +#define SysTick_CSR_TICKINT_SHIFT 1 +#define SysTick_CSR_CLKSOURCE_MASK 0x4u +#define SysTick_CSR_CLKSOURCE_SHIFT 2 +#define SysTick_CSR_COUNTFLAG_MASK 0x10000u +#define SysTick_CSR_COUNTFLAG_SHIFT 16 +/* RVR Bit Fields */ +#define SysTick_RVR_RELOAD_MASK 0xFFFFFFu +#define SysTick_RVR_RELOAD_SHIFT 0 +#define SysTick_RVR_RELOAD(x) (((uint32)(((uint32)(x))<SSPSR) +#define TPIU_CSPSR_REG(base) ((base)->CSPSR) +#define TPIU_ACPR_REG(base) ((base)->ACPR) +#define TPIU_SPPR_REG(base) ((base)->SPPR) +#define TPIU_FFSR_REG(base) ((base)->FFSR) +#define TPIU_FFCR_REG(base) ((base)->FFCR) +#define TPIU_FSCR_REG(base) ((base)->FSCR) +#define TPIU_TRIGGER_REG(base) ((base)->TRIGGER) +#define TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0) +#define TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2) +#define TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0) +#define TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1) +#define TPIU_ITCTRL_REG(base) ((base)->ITCTRL) +#define TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET) +#define TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR) +#define TPIU_DEVID_REG(base) ((base)->DEVID) +#define TPIU_PID4_REG(base) ((base)->PID4) +#define TPIU_PID5_REG(base) ((base)->PID5) +#define TPIU_PID6_REG(base) ((base)->PID6) +#define TPIU_PID7_REG(base) ((base)->PID7) +#define TPIU_PID0_REG(base) ((base)->PID0) +#define TPIU_PID1_REG(base) ((base)->PID1) +#define TPIU_PID2_REG(base) ((base)->PID2) +#define TPIU_PID3_REG(base) ((base)->PID3) +#define TPIU_CID0_REG(base) ((base)->CID0) +#define TPIU_CID1_REG(base) ((base)->CID1) +#define TPIU_CID2_REG(base) ((base)->CID2) +#define TPIU_CID4_REG(base) ((base)->CID4) + +/** + * @} + */ /* end of group TPIU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TPIU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TPIU_Register_Masks TPIU Register Masks + * @{ + */ + + +/** + * @} + */ /* end of group TPIU_Register_Masks */ + + +/* TPIU - Peripheral instance base addresses */ +/** Peripheral TPIU base pointer */ +#define TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u) + +/* ---------------------------------------------------------------------------- + -- TPIU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros + * @{ + */ + + +/* TPIU - Register instance definitions */ +/* TPIU */ +#define TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR) +#define TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR) +#define TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR) +#define TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR) +#define TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR) +#define TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR) +#define TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR) +#define TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR) +#define TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR) +#define TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR) +#define TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR) +#define TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR) +#define TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR) +#define TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR) +#define TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR) +#define TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR) +#define TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR) +#define TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR) +#define TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR) +#define TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR) +#define TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR) +#define TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR) +#define TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR) +#define TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR) +#define TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR) +#define TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR) +#define TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR) +#define TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR) + +/** + * @} + */ /* end of group TPIU_Register_Accessor_Macros */ + + +/** + * @} + */ /* end of group TPIU_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- TSI + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Peripheral TSI + * @{ + */ + +/** TSI - Peripheral register structure */ +typedef struct TSI_MemMap { + uint32 GENCS; /**< General Control and Status Register, offset: 0x0 */ + uint32 SCANC; /**< SCAN Control Register, offset: 0x4 */ + uint32 PEN; /**< Pin Enable Register, offset: 0x8 */ + uint32 WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ + uint8 RESERVED_0[240]; + uint32 CNTR1; /**< Counter Register, offset: 0x100 */ + uint32 CNTR3; /**< Counter Register, offset: 0x104 */ + uint32 CNTR5; /**< Counter Register, offset: 0x108 */ + uint32 CNTR7; /**< Counter Register, offset: 0x10C */ + uint32 CNTR9; /**< Counter Register, offset: 0x110 */ + uint32 CNTR11; /**< Counter Register, offset: 0x114 */ + uint32 CNTR13; /**< Counter Register, offset: 0x118 */ + uint32 CNTR15; /**< Counter Register, offset: 0x11C */ + uint32 THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ +} volatile *TSI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- TSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros + * @{ + */ + + +/* TSI - Register accessors */ +#define TSI_GENCS_REG(base) ((base)->GENCS) +#define TSI_SCANC_REG(base) ((base)->SCANC) +#define TSI_PEN_REG(base) ((base)->PEN) +#define TSI_WUCNTR_REG(base) ((base)->WUCNTR) +#define TSI_CNTR1_REG(base) ((base)->CNTR1) +#define TSI_CNTR3_REG(base) ((base)->CNTR3) +#define TSI_CNTR5_REG(base) ((base)->CNTR5) +#define TSI_CNTR7_REG(base) ((base)->CNTR7) +#define TSI_CNTR9_REG(base) ((base)->CNTR9) +#define TSI_CNTR11_REG(base) ((base)->CNTR11) +#define TSI_CNTR13_REG(base) ((base)->CNTR13) +#define TSI_CNTR15_REG(base) ((base)->CNTR15) +#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) + +/** + * @} + */ /* end of group TSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TSI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Masks TSI Register Masks + * @{ + */ + +/* GENCS Bit Fields */ +#define TSI_GENCS_STPE_MASK 0x1u +#define TSI_GENCS_STPE_SHIFT 0 +#define TSI_GENCS_STM_MASK 0x2u +#define TSI_GENCS_STM_SHIFT 1 +#define TSI_GENCS_ESOR_MASK 0x10u +#define TSI_GENCS_ESOR_SHIFT 4 +#define TSI_GENCS_ERIE_MASK 0x20u +#define TSI_GENCS_ERIE_SHIFT 5 +#define TSI_GENCS_TSIIE_MASK 0x40u +#define TSI_GENCS_TSIIE_SHIFT 6 +#define TSI_GENCS_TSIEN_MASK 0x80u +#define TSI_GENCS_TSIEN_SHIFT 7 +#define TSI_GENCS_SWTS_MASK 0x100u +#define TSI_GENCS_SWTS_SHIFT 8 +#define TSI_GENCS_SCNIP_MASK 0x200u +#define TSI_GENCS_SCNIP_SHIFT 9 +#define TSI_GENCS_OVRF_MASK 0x1000u +#define TSI_GENCS_OVRF_SHIFT 12 +#define TSI_GENCS_EXTERF_MASK 0x2000u +#define TSI_GENCS_EXTERF_SHIFT 13 +#define TSI_GENCS_OUTRGF_MASK 0x4000u +#define TSI_GENCS_OUTRGF_SHIFT 14 +#define TSI_GENCS_EOSF_MASK 0x8000u +#define TSI_GENCS_EOSF_SHIFT 15 +#define TSI_GENCS_PS_MASK 0x70000u +#define TSI_GENCS_PS_SHIFT 16 +#define TSI_GENCS_PS(x) (((uint32)(((uint32)(x))<BDH) +#define UART_BDL_REG(base) ((base)->BDL) +#define UART_C1_REG(base) ((base)->C1) +#define UART_C2_REG(base) ((base)->C2) +#define UART_S1_REG(base) ((base)->S1) +#define UART_S2_REG(base) ((base)->S2) +#define UART_C3_REG(base) ((base)->C3) +#define UART_D_REG(base) ((base)->D) +#define UART_MA1_REG(base) ((base)->MA1) +#define UART_MA2_REG(base) ((base)->MA2) +#define UART_C4_REG(base) ((base)->C4) +#define UART_C5_REG(base) ((base)->C5) +#define UART_ED_REG(base) ((base)->ED) +#define UART_MODEM_REG(base) ((base)->MODEM) +#define UART_IR_REG(base) ((base)->IR) +#define UART_PFIFO_REG(base) ((base)->PFIFO) +#define UART_CFIFO_REG(base) ((base)->CFIFO) +#define UART_SFIFO_REG(base) ((base)->SFIFO) +#define UART_TWFIFO_REG(base) ((base)->TWFIFO) +#define UART_TCFIFO_REG(base) ((base)->TCFIFO) +#define UART_RWFIFO_REG(base) ((base)->RWFIFO) +#define UART_RCFIFO_REG(base) ((base)->RCFIFO) +#define UART_C7816_REG(base) ((base)->C7816) +#define UART_IE7816_REG(base) ((base)->IE7816) +#define UART_IS7816_REG(base) ((base)->IS7816) +#define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0) +#define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1) +#define UART_WN7816_REG(base) ((base)->WN7816) +#define UART_WF7816_REG(base) ((base)->WF7816) +#define UART_ET7816_REG(base) ((base)->ET7816) +#define UART_TL7816_REG(base) ((base)->TL7816) + +/** + * @} + */ /* end of group UART_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* BDH Bit Fields */ +#define UART_BDH_SBR_MASK 0x1Fu +#define UART_BDH_SBR_SHIFT 0 +#define UART_BDH_SBR(x) (((uint8)(((uint8)(x))<PERID) +#define USB_IDCOMP_REG(base) ((base)->IDCOMP) +#define USB_REV_REG(base) ((base)->REV) +#define USB_ADDINFO_REG(base) ((base)->ADDINFO) +#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) +#define USB_OTGICR_REG(base) ((base)->OTGICR) +#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) +#define USB_OTGCTL_REG(base) ((base)->OTGCTL) +#define USB_ISTAT_REG(base) ((base)->ISTAT) +#define USB_INTEN_REG(base) ((base)->INTEN) +#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) +#define USB_ERREN_REG(base) ((base)->ERREN) +#define USB_STAT_REG(base) ((base)->STAT) +#define USB_CTL_REG(base) ((base)->CTL) +#define USB_ADDR_REG(base) ((base)->ADDR) +#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) +#define USB_FRMNUML_REG(base) ((base)->FRMNUML) +#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) +#define USB_TOKEN_REG(base) ((base)->TOKEN) +#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) +#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) +#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) +#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) +#define USB_USBCTRL_REG(base) ((base)->USBCTRL) +#define USB_OBSERVE_REG(base) ((base)->OBSERVE) +#define USB_CONTROL_REG(base) ((base)->CONTROL) +#define USB_USBTRC0_REG(base) ((base)->USBTRC0) +#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) + +/** + * @} + */ /* end of group USB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* PERID Bit Fields */ +#define USB_PERID_ID_MASK 0x3Fu +#define USB_PERID_ID_SHIFT 0 +#define USB_PERID_ID(x) (((uint8)(((uint8)(x))<CONTROL) +#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) +#define USBDCD_STATUS_REG(base) ((base)->STATUS) +#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) +#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) +#define USBDCD_TIMER2_REG(base) ((base)->TIMER2) + +/** + * @} + */ /* end of group USBDCD_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/* CONTROL Bit Fields */ +#define USBDCD_CONTROL_IACK_MASK 0x1u +#define USBDCD_CONTROL_IACK_SHIFT 0 +#define USBDCD_CONTROL_IF_MASK 0x100u +#define USBDCD_CONTROL_IF_SHIFT 8 +#define USBDCD_CONTROL_IE_MASK 0x10000u +#define USBDCD_CONTROL_IE_SHIFT 16 +#define USBDCD_CONTROL_START_MASK 0x1000000u +#define USBDCD_CONTROL_START_SHIFT 24 +#define USBDCD_CONTROL_SR_MASK 0x2000000u +#define USBDCD_CONTROL_SR_SHIFT 25 +/* CLOCK Bit Fields */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 +#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32)(((uint32)(x))<TRM) +#define VREF_SC_REG(base) ((base)->SC) + +/** + * @} + */ /* end of group VREF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/* TRM Bit Fields */ +#define VREF_TRM_TRIM_MASK 0x3Fu +#define VREF_TRM_TRIM_SHIFT 0 +#define VREF_TRM_TRIM(x) (((uint8)(((uint8)(x))<STCTRLH) +#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) +#define WDOG_TOVALH_REG(base) ((base)->TOVALH) +#define WDOG_TOVALL_REG(base) ((base)->TOVALL) +#define WDOG_WINH_REG(base) ((base)->WINH) +#define WDOG_WINL_REG(base) ((base)->WINL) +#define WDOG_REFRESH_REG(base) ((base)->REFRESH) +#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) +#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) +#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) +#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) +#define WDOG_PRESC_REG(base) ((base)->PRESC) + +/** + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* STCTRLH Bit Fields */ +#define WDOG_STCTRLH_WDOGEN_MASK 0x1u +#define WDOG_STCTRLH_WDOGEN_SHIFT 0 +#define WDOG_STCTRLH_CLKSRC_MASK 0x2u +#define WDOG_STCTRLH_CLKSRC_SHIFT 1 +#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u +#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 +#define WDOG_STCTRLH_WINEN_MASK 0x8u +#define WDOG_STCTRLH_WINEN_SHIFT 3 +#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 +#define WDOG_STCTRLH_DBGEN_MASK 0x20u +#define WDOG_STCTRLH_DBGEN_SHIFT 5 +#define WDOG_STCTRLH_STOPEN_MASK 0x40u +#define WDOG_STCTRLH_STOPEN_SHIFT 6 +#define WDOG_STCTRLH_WAITEN_MASK 0x80u +#define WDOG_STCTRLH_WAITEN_SHIFT 7 +#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u +#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 +#define WDOG_STCTRLH_TESTSEL_MASK 0x800u +#define WDOG_STCTRLH_TESTSEL_SHIFT 11 +#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u +#define WDOG_STCTRLH_BYTESEL_SHIFT 12 +#define WDOG_STCTRLH_BYTESEL(x) (((uint16)(((uint16)(x))< m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld new file mode 100644 index 0000000..d6a2f70 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DN512.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DN512.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00000410, LENGTH = 512K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 128K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.ramcode) /* .ramcode section for code to be executed in SRAM */ + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld new file mode 100644 index 0000000..389690d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256-TMCM.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DX256-TMCM.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00008000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00008400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00008410, LENGTH = 512K-32K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld new file mode 100644 index 0000000..0e16652 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/MK20DX256.ld @@ -0,0 +1,205 @@ +/* +***************************************************************************** +** +** File : MK20DN512.ld +** +** Default linker command file for Flash targets +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of SRAM */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x400; /* required amount of heap */ +__stack_size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x1BC + m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 + m_text (rx) : ORIGIN = 0x00000410, LENGTH = 512K-0x410 + m_data (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K /* SRAM */ +} + + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > m_data + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.ramcode) /* .ramcode section for code to be executed in SRAM */ + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + . = . + __heap_size; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h new file mode 100644 index 0000000..5977c17 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/ADC_PDD.h @@ -0,0 +1,3727 @@ +/* + PDD layer implementation for peripheral type ADC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(ADC_PDD_H_) +#define ADC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error ADC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK10D5) /* ADC0 */ && \ + !defined(MCU_MK10D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK10F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK10DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK11D5) /* ADC0 */ && \ + !defined(MCU_MK11D5WS) /* ADC0 */ && \ + !defined(MCU_MK12D5) /* ADC0 */ && \ + !defined(MCU_MK20D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK20D5) /* ADC0 */ && \ + !defined(MCU_MK20D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK20F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK20DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK21D5) /* ADC0 */ && \ + !defined(MCU_MK21D5WS) /* ADC0 */ && \ + !defined(MCU_MK21F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK21F12WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22D5) /* ADC0 */ && \ + !defined(MCU_MK22F12810) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F25612) /* ADC0, ADC1 */ && \ + !defined(MCU_MK22F51212) /* ADC0, ADC1 */ && \ + !defined(MCU_MK24F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK30DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK40X256VMD100) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK50DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51D7) /* ADC0, ADC1 */ && \ + !defined(MCU_MK51DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK52D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK52DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK53D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK53DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60D10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK60F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK60DZ10) /* ADC0, ADC1 */ && \ + !defined(MCU_MK60N512VMD100) /* ADC0, ADC1 */ && \ + !defined(MCU_MK61F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F12WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK61F15WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK63F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK63F12WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK64F12) /* ADC0, ADC1 */ && \ + !defined(MCU_MK65F18) /* ADC0, ADC1 */ && \ + !defined(MCU_MK65F18WS) /* ADC0, ADC1 */ && \ + !defined(MCU_MK66F18) /* ADC0, ADC1 */ && \ + !defined(MCU_MK70F12) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F15) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F12WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MK70F15WS) /* ADC0, ADC1, ADC2, ADC3 */ && \ + !defined(MCU_MKE02Z2) /* ADC */ && \ + !defined(MCU_MKE02Z4) /* ADC */ && \ + !defined(MCU_SKEAZN642) /* ADC */ && \ + !defined(MCU_MKE04Z1284) /* ADC */ && \ + !defined(MCU_MKE04Z4) /* ADC */ && \ + !defined(MCU_SKEAZN84) /* ADC */ && \ + !defined(MCU_MKE06Z4) /* ADC */ && \ + !defined(MCU_MKL02Z4) /* ADC0 */ && \ + !defined(MCU_MKL03Z4) /* ADC0 */ && \ + !defined(MCU_MKL04Z4) /* ADC0 */ && \ + !defined(MCU_MKL05Z4) /* ADC0 */ && \ + !defined(MCU_MKL14Z4) /* ADC0 */ && \ + !defined(MCU_MKL15Z4) /* ADC0 */ && \ + !defined(MCU_MKL16Z4) /* ADC0 */ && \ + !defined(MCU_MKL24Z4) /* ADC0 */ && \ + !defined(MCU_MKL25Z4) /* ADC0 */ && \ + !defined(MCU_MKL26Z4) /* ADC0 */ && \ + !defined(MCU_MKL34Z4) /* ADC0 */ && \ + !defined(MCU_MKL36Z4) /* ADC0 */ && \ + !defined(MCU_MKL46Z4) /* ADC0 */ && \ + !defined(MCU_MKV10Z7) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F12810) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F25612) /* ADC0, ADC1 */ && \ + !defined(MCU_MKV31F51212) /* ADC0, ADC1 */ && \ + !defined(MCU_MKW01Z4) /* ADC0 */ && \ + !defined(MCU_MKW21D5) /* ADC0 */ && \ + !defined(MCU_MKW21D5WS) /* ADC0 */ && \ + !defined(MCU_MKW22D5) /* ADC0 */ && \ + !defined(MCU_MKW22D5WS) /* ADC0 */ && \ + !defined(MCU_MKW24D5) /* ADC0 */ && \ + !defined(MCU_MKW24D5WS) /* ADC0 */ && \ + !defined(MCU_PCK20L4) /* ADC0 */ && \ + !defined(MCU_SKEAZ1284) /* ADC */ + // Unsupported MCU is active + #error ADC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL24Z4))) +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x1AU /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x1BU /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x16U /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x17U /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Channel constants for channel selection */ + #define ADC_PDD_SINGLE_ENDED_DAD0 0U /**< Single-ended mode, channel 0 */ + #define ADC_PDD_SINGLE_ENDED_DAD1 0x1U /**< Single-ended mode, channel 1 */ + #define ADC_PDD_SINGLE_ENDED_DAD2 0x2U /**< Single-ended mode, channel 2 */ + #define ADC_PDD_SINGLE_ENDED_DAD3 0x3U /**< Single-ended mode, channel 3 */ + #define ADC_PDD_SINGLE_ENDED_AD4 0x4U /**< Single-ended mode, channel 4 */ + #define ADC_PDD_SINGLE_ENDED_AD5 0x5U /**< Single-ended mode, channel 5 */ + #define ADC_PDD_SINGLE_ENDED_AD6 0x6U /**< Single-ended mode, channel 6 */ + #define ADC_PDD_SINGLE_ENDED_AD7 0x7U /**< Single-ended mode, channel 7 */ + #define ADC_PDD_SINGLE_ENDED_AD8 0x8U /**< Single-ended mode, channel 8 */ + #define ADC_PDD_SINGLE_ENDED_AD9 0x9U /**< Single-ended mode, channel 9 */ + #define ADC_PDD_SINGLE_ENDED_AD10 0xAU /**< Single-ended mode, channel 10 */ + #define ADC_PDD_SINGLE_ENDED_AD11 0xBU /**< Single-ended mode, channel 11 */ + #define ADC_PDD_SINGLE_ENDED_AD12 0xCU /**< Single-ended mode, channel 12 */ + #define ADC_PDD_SINGLE_ENDED_AD13 0xDU /**< Single-ended mode, channel 13 */ + #define ADC_PDD_SINGLE_ENDED_AD14 0xEU /**< Single-ended mode, channel 14 */ + #define ADC_PDD_SINGLE_ENDED_AD15 0xFU /**< Single-ended mode, channel 15 */ + #define ADC_PDD_SINGLE_ENDED_AD16 0x10U /**< Single-ended mode, channel 16 */ + #define ADC_PDD_SINGLE_ENDED_AD17 0x11U /**< Single-ended mode, channel 17 */ + #define ADC_PDD_SINGLE_ENDED_AD18 0x12U /**< Single-ended mode, channel 18 */ + #define ADC_PDD_SINGLE_ENDED_AD19 0x13U /**< Single-ended mode, channel 19 */ + #define ADC_PDD_SINGLE_ENDED_AD20 0x14U /**< Single-ended mode, channel 20 */ + #define ADC_PDD_SINGLE_ENDED_AD21 0x15U /**< Single-ended mode, channel 21 */ + #define ADC_PDD_SINGLE_ENDED_AD22 0x16U /**< Single-ended mode, channel 22 */ + #define ADC_PDD_SINGLE_ENDED_AD23 0x17U /**< Single-ended mode, channel 23 */ + #define ADC_PDD_SINGLE_ENDED_AD24 0x18U /**< Single-ended mode, channel 24 */ + #define ADC_PDD_SINGLE_ENDED_AD25 0x19U /**< Single-ended mode, channel 25 */ + #define ADC_PDD_SINGLE_ENDED_AD26 0x1AU /**< Single-ended mode, channel 26 */ + #define ADC_PDD_SINGLE_ENDED_AD27 0x1BU /**< Single-ended mode, channel 27 */ + #define ADC_PDD_SINGLE_ENDED_AD28 0x1CU /**< Single-ended mode, channel 28 */ + #define ADC_PDD_SINGLE_ENDED_AD29 0x1DU /**< Single-ended mode, channel 29 */ + #define ADC_PDD_SINGLE_ENDED_AD30 0x1EU /**< Single-ended mode, channel 30 */ + #define ADC_PDD_DIFFERENTIAL_DADP0_DADM0 0x20U /**< Differential mode, positive and negative channel 0 */ + #define ADC_PDD_DIFFERENTIAL_DADP1_DADM1 0x21U /**< Differential mode, positive and negative channel 1 */ + #define ADC_PDD_DIFFERENTIAL_DADP2_DADM2 0x22U /**< Differential mode, positive and negative channel 2 */ + #define ADC_PDD_DIFFERENTIAL_DADP3_DADM3 0x23U /**< Differential mode, positive and negative channel 3 */ + #define ADC_PDD_MODULE_DISABLED 0x1FU /**< Module disabled */ + #define ADC_PDD_DIFFERENTIAL_BANDGAP 0x3BU /**< Differential mode, positive and negative bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_DIFFERENTIAL_VREFSH 0x3DU /**< Differential mode, positive and negative VREFS. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_TEMP_SENSOR 0x1AU /**< Single-ended mode, temp sensor. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_BANDGAP 0x1BU /**< Single-ended mode, bandgap. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSH 0x1DU /**< Single-ended mode, VREFSH. This constant is deprecated. It will not be supported in the future. */ + #define ADC_PDD_SINGLE_ENDED_VREFSL 0x1EU /**< Single-ended mode, VREFSL. This constant is deprecated. It will not be supported in the future. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for trigger type selection */ +#define ADC_PDD_SW_TRIGGER 0U /**< SW trigger */ +#define ADC_PDD_HW_TRIGGER 0x40U /**< HW trigger */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for compare function selection */ + #define ADC_PDD_COMPARE_DISABLED 0U /**< Compare function disabled */ + #define ADC_PDD_LESS_THAN 0x20U /**< Compare function enabled to 'less than' */ + #define ADC_PDD_GREATER_THAN_OR_EQUAL 0x30U /**< Compare function enabled to 'greater than or equal' */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for compare function selection */ + #define ADC_PDD_COMPARE_DISABLED 0U /**< Compare function disabled */ + #define ADC_PDD_LESS_THAN 0x20U /**< Compare function enabled to 'less than' */ + #define ADC_PDD_GREATER_THAN_OR_EQUAL 0x30U /**< Compare function enabled to 'greater than or equal' */ + #define ADC_PDD_RANGE_NOT_INCLUSIVE 0x28U /**< Compare function enabled to 'range, not inclusive' */ + #define ADC_PDD_RANGE_INCLUSIVE 0x38U /**< Compare function enabled to 'range, inclusive' */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock input constants */ +#define ADC_PDD_BUS_CLOCK 0U /**< Bus clock as clock input */ +#define ADC_PDD_BUS_CLOCK_DIV_2 0x1U /**< Bus clock divided 2 as clock input */ +#define ADC_PDD_ALTERNATE_CLOCK 0x2U /**< Alternate clock as clock input */ +#define ADC_PDD_ASYNCHRONOUS_CLOCK 0x3U /**< Asynchronous clock as clock input */ + +/* Resolution mode constants */ +#define ADC_PDD_RESOLUTION_8_BITS 0U /**< 8-bit conversion in single-ended mode, 9-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_12_BITS 0x4U /**< 12-bit conversion in single-ended mode, 13-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_10_BITS 0x8U /**< 10-bit conversion in single-ended mode, 11-bit conversion in differential mode */ +#define ADC_PDD_RESOLUTION_16_BITS 0xCU /**< 16-bit conversion in single-ended mode, 16-bit conversion in differential mode */ + +/* Clock division constants */ +#define ADC_PDD_DIVIDE_1 0U /**< The divide ration is 1 */ +#define ADC_PDD_DIVIDE_2 0x20U /**< The divide ration is 2 */ +#define ADC_PDD_DIVIDE_4 0x40U /**< The divide ration is 4 */ +#define ADC_PDD_DIVIDE_8 0x60U /**< The divide ration is 8 */ + +/* Long sample time constants */ +#define ADC_PDD_LONG_SAMPLE_TIME_20_CLOCKS 0U /**< 20 extra ADC clock cycles; 24 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_12_CLOCKS 0x1U /**< 12 extra ADC clock cycles; 16 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_6_CLOCKS 0x2U /**< 6 extra ADC clock cycles; 10 ADC clock cycles total */ +#define ADC_PDD_LONG_SAMPLE_TIME_2_CLOCKS 0x3U /**< 2 extra ADC clock cycles; 6 ADC clock cycles total */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for conversion speed selection */ + #define ADC_PDD_SHORT 0U /**< Short sample time - less precise conversion. */ + #define ADC_PDD_LONG 0x1U /**< Long sample time - more precise conversion. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Total sample time constants */ + #define ADC_PDD_SAMPLE_TIME_24_CLOCKS 0U /**< 24 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_16_CLOCKS 0x1U /**< 16 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_10_CLOCKS 0x2U /**< 10 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_6_CLOCKS 0x3U /**< 6 ADC clock cycles total */ + #define ADC_PDD_SAMPLE_TIME_4_CLOCKS 0x4U /**< 4 ADC clock cycles total */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Channel set constants */ +#define ADC_PDD_CHANNEL_SET_A 0U /**< ADxxa channel set */ +#define ADC_PDD_CHANNEL_SET_B 0x10U /**< ADxxb channel set */ + +/* Voltage reference constants */ +#define ADC_PDD_VOLTAGE_REFERENCE_DEFAULT 0U /**< Default voltage reference Vrefh and Vrefl */ +#define ADC_PDD_VOLTAGE_REFERENCE_ALTERNATE 0x1U /**< Alternate voltage reference */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Constants for one conversion or continuous selection */ + #define ADC_PDD_ONE_CONVERSION 0U /**< One conversion mode */ + #define ADC_PDD_CONTINUOUS_CONVERSIONS 0x20U /**< Continuous conversion mode */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for one conversion or continuous selection */ + #define ADC_PDD_ONE_CONVERSION 0U /**< One conversion mode */ + #define ADC_PDD_CONTINUOUS_CONVERSIONS 0x8U /**< Continuous conversion mode */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Constants for average type selection */ +#define ADC_PDD_AVERAGE_DISABLED 0U /**< Average function disabled */ +#define ADC_PDD_4_SAMPLES_AVERAGED 0x4U /**< Average function with 4 samples */ +#define ADC_PDD_8_SAMPLES_AVERAGED 0x5U /**< Average function with 8 samples */ +#define ADC_PDD_16_SAMPLES_AVERAGED 0x6U /**< Average function with 16 samples */ +#define ADC_PDD_32_SAMPLES_AVERAGED 0x7U /**< Average function with 32 samples */ + +/* Constants for voltage reference selection */ +#define ADC_PDD_VREF 0U /**< VREFH and VREFL signals are used as voltage reference. */ +#define ADC_PDD_VANALOG 0x1U /**< VDDA and VSSA (analog supply) signals are used as voltage reference. */ + +/* Constants for power mode selection */ +#define ADC_PDD_NORMAL 0U /**< Normal power mode - faster ADC clock. */ +#define ADC_PDD_LOW 0x80U /**< Low power mode - slower ADC clock. */ + +/* Constants for divider */ +#define ADC_PDD_DIV_1 0U /**< Input clock divided by 1. */ +#define ADC_PDD_DIV_2 0x20U /**< Input clock divided by 2. */ +#define ADC_PDD_DIV_4 0x40U /**< Input clock divided by 4. */ +#define ADC_PDD_DIV_8 0x60U /**< Input clock divided by 8. */ + +/* Constants for resolution settings */ +#define ADC_PDD_RES_8 0U /**< 8-bit conversion. */ +#define ADC_PDD_RES_10 0x4U /**< 10-bit conversion. */ +#define ADC_PDD_RES_12 0x8U /**< 12-bit conversion. */ + +/* Constants for clock source settings */ +#define ADC_PDD_PERIPH_CLK 0U /**< Peripheral clock (BUS_CLOCK) selected as clock source. */ +#define ADC_PDD_PERIPH_CLK_DIV_2 0x1U /**< Half of peripheral clock (BUS_CLOCK) selected as clock source. */ +#define ADC_PDD_ALT_CLK 0x2U /**< Alternate clock selected as clock source. */ +#define ADC_PDD_ASYNC_CLK 0x3U /**< Asynchro clock selected as clock source. */ + +/* Constants for FIFO scan mode settings */ +#define ADC_PDD_NORMAL 0U /**< Selects normal mode of the FIFO. */ +#define ADC_PDD_SCAN 0x40U /**< Selects scan mode of the FIFO. */ + +/* Constants for FIFO compare mode settings */ +#define ADC_PDD_OR 0U /**< Selects logic or between the compare trigger inside the FIFO. */ +#define ADC_PDD_AND 0x20U /**< Selects logic and between the compare trigger inside the FIFO. */ + +/* Constants for FIFO state */ +#define ADC_PDD_EMPTY 0x8U /**< FIFO is empty. */ +#define ADC_PDD_NOT_EMPTY 0U /**< FIFO contains some data - measurement in progress. */ +#define ADC_PDD_FULL 0x4U /**< FIFO is full, next measurements will rewrite previous results. */ + +/* Constants for HW trigger masking mode */ +#define ADC_PDD_HAND 0U /**< Selects hand mode: Hardware trigger masking depended on HTRGMASKE bit, see the EnableFIFO_HW_TriggerMasking macro. */ +#define ADC_PDD_AUTOMATIC 0x1U /**< Selects automatic mode: Hardware trigger masked automatically when data FIFO is not empty. */ + + +/* ---------------------------------------------------------------------------- + -- SetChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @param Value Parameter specifying new channel. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_SetChannel(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC1_ADCH_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new channel. Use constants from group + * "Channel constants for channel selection". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetChannel(_BASE_PTR, periphID, + * ADC_PDD_SINGLE_ENDED_DAD0); + * @endcode + */ + #define ADC_PDD_SetChannel(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)0x3FU))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableConversionCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_EnableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) |= \ + ADC_SC1_AIEN_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_EnableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) |= \ + ADC_SC1_AIEN_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableConversionCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_DisableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_DisableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC1_AIEN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disable conversion complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_DisableConversionCompleteInterrupt(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_DisableConversionCompleteInterrupt(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)ADC_SC1_AIEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetConversionCompleteFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns conversion complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionCompleteFlag(_BASE_PTR, periphID); + * @endcode + */ + #define ADC_PDD_GetConversionCompleteFlag(PeripheralBase, Index) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & ADC_SC1_COCO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns conversion complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionCompleteFlag(_BASE_PTR, periphID); + * @endcode + */ + #define ADC_PDD_GetConversionCompleteFlag(PeripheralBase, Index) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase,(Index)) & ADC_SC1_COCO_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl1Reg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_WriteStatusControl1Reg(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl1Reg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define ADC_PDD_WriteStatusControl1Reg(PeripheralBase, Index, Value) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the content of the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl1Reg(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_ReadStatusControl1Reg(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Status and control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SC1[Index], ADC_SC1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl1Reg(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_ReadStatusControl1Reg(PeripheralBase, Index) ( \ + ADC_SC1_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectInputClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects input clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Input Clock input. This parameter is of "Clock input constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectInputClock(_BASE_PTR, ADC_PDD_BUS_CLOCK); + * @endcode + */ +#define ADC_PDD_SelectInputClock(PeripheralBase, Input) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADICLK_MASK))) | ( \ + (uint32)(Input))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC resolution mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Resolution mode. This parameter is of "Resolution mode constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectResolution(_BASE_PTR, + * ADC_PDD_RESOLUTION_8_BITS); + * @endcode + */ +#define ADC_PDD_SelectResolution(PeripheralBase, Mode) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_MODE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLongSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables long sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if long sample time will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableLongSampleTime(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableLongSampleTime(PeripheralBase, State) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADLSMP_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG1_ADLSMP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClockDivision + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC clock division. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divide Clock division. This parameter is of "Clock division constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectClockDivision(_BASE_PTR, ADC_PDD_DIVIDE_1); + * @endcode + */ +#define ADC_PDD_SelectClockDivision(PeripheralBase, Divide) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADIV_MASK))) | ( \ + (uint32)(Divide))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables low power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if low power mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableLowPowerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableLowPowerMode(PeripheralBase, State) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG1_ADLPC_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG1_ADLPC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfiguration1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_WriteConfiguration1Reg(PeripheralBase, Value) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_WriteConfiguration1Reg(PeripheralBase, Value) ( \ + ADC_CFG1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadConfiguration1Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the content of the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration1Reg(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_ReadConfiguration1Reg(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC1_CFG1, + * ADC2_CFG1, ADC3_CFG1, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration1Reg(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_ReadConfiguration1Reg(PeripheralBase) ( \ + ADC_CFG1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectLongSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects sample time effective if long sample time is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time Long sample time. This parameter is of "Long sample time + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectLongSampleTime(_BASE_PTR, + * ADC_PDD_LONG_SAMPLE_TIME_20_CLOCKS); + * @endcode + */ +#define ADC_PDD_SelectLongSampleTime(PeripheralBase, Time) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)(Time))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects sample time effective if long sample time is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time Long sample time. This parameter is of "Total sample time + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG1, ADC0_CFG2, + * ADC1_CFG1, ADC1_CFG2, ADC2_CFG1, ADC2_CFG2, ADC3_CFG1, ADC3_CFG2 + * (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectSampleTime(_BASE_PTR, + * ADC_PDD_SAMPLE_TIME_24_CLOCKS); + * @endcode + */ +#define ADC_PDD_SelectSampleTime(PeripheralBase, Time) ( \ + ( \ + ((Time) == ADC_PDD_SAMPLE_TIME_24_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_16_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_10_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : (((Time) == ADC_PDD_SAMPLE_TIME_6_CLOCKS) ? ( \ + ADC_CFG1_REG(PeripheralBase) |= \ + ADC_CFG1_ADLSMP_MASK) : ( \ + ADC_CFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG1_ADLSMP_MASK)) \ + )))), \ + ( \ + ((Time) == ADC_PDD_SAMPLE_TIME_24_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK)) : (((Time) == ADC_PDD_SAMPLE_TIME_16_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)0x1U))) : (((Time) == ADC_PDD_SAMPLE_TIME_10_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK))) | ( \ + (uint32)0x2U))) : (((Time) == ADC_PDD_SAMPLE_TIME_6_CLOCKS) ? ( \ + ADC_CFG2_REG(PeripheralBase) |= \ + ADC_CFG2_ADLSTS_MASK) : ( \ + ADC_CFG2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_CFG2_ADLSTS_MASK)) \ + )))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHighSpeedMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables high speed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if high speed mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableHighSpeedMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableHighSpeedMode(PeripheralBase, State) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADHSC_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG2_ADHSC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsynchronousClockOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables asynchronous clock output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if asynchronous clock output will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableAsynchronousClockOutput(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableAsynchronousClockOutput(PeripheralBase, State) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_ADACKEN_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_CFG2_ADACKEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelSet + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects between alternate sets of ADC channels. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Set ADC channel set. This parameter is of "Channel set constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectChannelSet(_BASE_PTR, ADC_PDD_CHANNEL_SET_A); + * @endcode + */ +#define ADC_PDD_SelectChannelSet(PeripheralBase, Set) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_CFG2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_CFG2_MUXSEL_MASK))) | ( \ + (uint32)(Set))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteConfiguration2Reg(PeripheralBase, Value) ( \ + ADC_CFG2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CFG2, ADC1_CFG2, + * ADC2_CFG2, ADC3_CFG2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadConfiguration2Reg(PeripheralBase) ( \ + ADC_CFG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetConversionActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns conversion active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionActiveFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetConversionActiveFlag(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_ADACT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCompareValue1Raw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 1. This parameter is a + * 12-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue1Raw(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_SetCompareValue1Raw(PeripheralBase, Value) ( \ + ADC_CV_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 1. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue1Raw(_BASE_PTR, 1); + * @endcode + */ + #define ADC_PDD_SetCompareValue1Raw(PeripheralBase, Value) ( \ + ADC_CV1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCompareValue1Raw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue1Raw(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetCompareValue1Raw(PeripheralBase) ( \ + ADC_CV_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns compare value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV1, ADC1_CV1, + * ADC2_CV1, ADC3_CV1, ADC_CV (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue1Raw(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetCompareValue1Raw(PeripheralBase) ( \ + ADC_CV1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCompareValue2Raw + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets compare value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new compare value 2. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CV2, ADC1_CV2, + * ADC2_CV2, ADC3_CV2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareValue2Raw(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetCompareValue2Raw(PeripheralBase, Value) ( \ + ADC_CV2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCompareValue2Raw + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns compare value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CV2, ADC1_CV2, + * ADC2_CV2, ADC3_CV2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetCompareValue2Raw(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCompareValue2Raw(PeripheralBase) ( \ + ADC_CV2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetConversionTriggerType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets conversion trigger type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Trigger mode. This parameter is of "Constants for trigger type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetConversionTriggerType(_BASE_PTR, + * ADC_PDD_SW_TRIGGER); + * @endcode + */ +#define ADC_PDD_SetConversionTriggerType(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_ADTRG_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetConversionTriggerType + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns conversion trigger type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for trigger type selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetConversionTriggerType(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetConversionTriggerType(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_ADTRG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCompareFunction + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets compare type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Compare mode. This parameter is of "Constants for compare + * function selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareFunction(_BASE_PTR, + * ADC_PDD_COMPARE_DISABLED); + * @endcode + */ + #define ADC_PDD_SetCompareFunction(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)((uint32)0x3U << 4U)))) | ( \ + (uint32)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets compare type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Compare mode. This parameter is of "Constants for compare + * function selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetCompareFunction(_BASE_PTR, + * ADC_PDD_COMPARE_DISABLED); + * @endcode + */ + #define ADC_PDD_SetCompareFunction(PeripheralBase, Mode) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)((uint32)0x7U << 3U)))) | ( \ + (uint32)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_DMAEN_MASK))) | ( \ + (uint32)((uint32)(State) << ADC_SC2_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the voltage reference source used for conversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Voltage reference. This parameter is of "Voltage reference + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SelectVoltageReference(_BASE_PTR, + * ADC_PDD_VOLTAGE_REFERENCE_DEFAULT); + * @endcode + */ +#define ADC_PDD_SelectVoltageReference(PeripheralBase, Reference) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_REFSEL_MASK))) | ( \ + (uint32)(Reference))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteStatusControl2Reg(PeripheralBase, Value) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC2, ADC1_SC2, + * ADC2_SC2, ADC3_SC2, ADC_SC2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadStatusControl2Reg(PeripheralBase) ( \ + ADC_SC2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartCalibration + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts calibration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_StartCalibration(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_StartCalibration(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) |= \ + ADC_SC3_CAL_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCalibrationActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns calibration active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetCalibrationActiveFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCalibrationActiveFlag(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_CAL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCalibrationFailedStatusFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns calibration failed status flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetCalibrationFailedStatusFlag(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetCalibrationFailedStatusFlag(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_CALF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetContinuousMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode One conversion or continuous mode. This parameter is of + * "Constants for one conversion or continuous selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetContinuousMode(_BASE_PTR, + * ADC_PDD_ONE_CONVERSION); + * @endcode + */ + #define ADC_PDD_SetContinuousMode(PeripheralBase, Mode) ( \ + ADC_SC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC1_ADCO_MASK))) | ( \ + (uint32)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode One conversion or continuous mode. This parameter is of + * "Constants for one conversion or continuous selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetContinuousMode(_BASE_PTR, + * ADC_PDD_ONE_CONVERSION); + * @endcode + */ + #define ADC_PDD_SetContinuousMode(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADCO_MASK))) | ( \ + (uint32)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetContinuousMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for one conversion or continuous + * selection" type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetContinuousMode(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetContinuousMode(PeripheralBase) ( \ + (uint32)(ADC_SC1_REG(PeripheralBase) & ADC_SC1_ADCO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns one conversion or continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for one conversion or continuous + * selection" type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetContinuousMode(_BASE_PTR); + * @endcode + */ + #define ADC_PDD_GetContinuousMode(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADCO_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetAverageFunction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets average function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Average mode. This parameter is of "Constants for average type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetAverageFunction(_BASE_PTR, + * ADC_PDD_AVERAGE_DISABLED); + * @endcode + */ +#define ADC_PDD_SetAverageFunction(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)0x7U))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteStatusControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteStatusControl3Reg(PeripheralBase, Value) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_SC3, ADC1_SC3, + * ADC2_SC3, ADC3_SC3, ADC_SC3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadStatusControl3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadStatusControl3Reg(PeripheralBase) ( \ + ADC_SC3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResultValueRaw + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns raw data from result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. Now it is ignored. This parameter is of index + * type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index], ADC_R + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResultValueRaw(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_GetResultValueRaw(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns raw data from result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index], ADC_R + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResultValueRaw(_BASE_PTR, + * periphID); + * @endcode + */ + #define ADC_PDD_GetResultValueRaw(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadDataResultReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data result register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: R[Index]. + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadDataResultReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define ADC_PDD_ReadDataResultReg(PeripheralBase, Index) ( \ + ADC_R_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOffsetCorrectionValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets offset error correction value in 2's complement and left + * justified format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new offset correction value. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetOffsetCorrectionValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetOffsetCorrectionValue(PeripheralBase, Value) ( \ + ADC_OFS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOffsetCorrectionValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns offset error correction value in 2's complement and left + * justified format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetOffsetCorrectionValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetOffsetCorrectionValue(PeripheralBase) ( \ + ADC_OFS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOffsetCorrectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Offset correction register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteOffsetCorrectionReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteOffsetCorrectionReg(PeripheralBase, Value) ( \ + ADC_OFS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOffsetCorrectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Offset correction register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_OFS, ADC1_OFS, + * ADC2_OFS, ADC3_OFS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadOffsetCorrectionReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadOffsetCorrectionReg(PeripheralBase) ( \ + ADC_OFS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPlusGainValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets plus-side gain value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetPlusGainValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetPlusGainValue(PeripheralBase, Value) ( \ + ADC_PG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideGainReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideGainReg(PeripheralBase, Value) ( \ + ADC_PG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_PG, ADC1_PG, + * ADC2_PG, ADC3_PG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadPlusSideGainReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideGainReg(PeripheralBase) ( \ + ADC_PG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinusGainValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets minus-side gain value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_SetMinusGainValue(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetMinusGainValue(PeripheralBase, Value) ( \ + ADC_MG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideGainReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideGainReg(PeripheralBase, Value) ( \ + ADC_MG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideGainReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side gain register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_MG, ADC1_MG, + * ADC2_MG, ADC3_MG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = ADC_PDD_ReadMinusSideGainReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideGainReg(PeripheralBase) ( \ + ADC_MG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus0CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus0CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus0CalibrationValue(PeripheralBase) ( \ + ADC_CLP0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration0Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration0Reg(PeripheralBase, Value) ( \ + ADC_CLP0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP0, ADC1_CLP0, + * ADC2_CLP0, ADC3_CLP0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration0Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration0Reg(PeripheralBase) ( \ + ADC_CLP0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus1CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus1CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus1CalibrationValue(PeripheralBase) ( \ + ADC_CLP1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration1Reg(PeripheralBase, Value) ( \ + ADC_CLP1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP1, ADC1_CLP1, + * ADC2_CLP1, ADC3_CLP1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration1Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration1Reg(PeripheralBase) ( \ + ADC_CLP1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus2CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus2CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus2CalibrationValue(PeripheralBase) ( \ + ADC_CLP2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration2Reg(PeripheralBase, Value) ( \ + ADC_CLP2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP2, ADC1_CLP2, + * ADC2_CLP2, ADC3_CLP2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration2Reg(PeripheralBase) ( \ + ADC_CLP2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus3CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus3CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus3CalibrationValue(PeripheralBase) ( \ + ADC_CLP3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration3Reg(PeripheralBase, Value) ( \ + ADC_CLP3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP3, ADC1_CLP3, + * ADC2_CLP3, ADC3_CLP3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration3Reg(PeripheralBase) ( \ + ADC_CLP3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlus4CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlus4CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlus4CalibrationValue(PeripheralBase) ( \ + ADC_CLP4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibration4Reg(PeripheralBase, Value) ( \ + ADC_CLP4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLP4, ADC1_CLP4, + * ADC2_CLP4, ADC3_CLP4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibration4Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibration4Reg(PeripheralBase) ( \ + ADC_CLP4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlusSCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value S. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlusSCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlusSCalibrationValue(PeripheralBase) ( \ + ADC_CLPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibrationSReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibrationSReg(PeripheralBase, Value) ( \ + ADC_CLPS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPS, ADC1_CLPS, + * ADC2_CLPS, ADC3_CLPS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibrationSReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibrationSReg(PeripheralBase) ( \ + ADC_CLPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPlusDCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns plus-side general calibration value D. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetPlusDCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPlusDCalibrationValue(PeripheralBase) ( \ + ADC_CLPD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Plus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WritePlusSideCalibrationDReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WritePlusSideCalibrationDReg(PeripheralBase, Value) ( \ + ADC_CLPD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Plus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLPD, ADC1_CLPD, + * ADC2_CLPD, ADC3_CLPD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadPlusSideCalibrationDReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadPlusSideCalibrationDReg(PeripheralBase) ( \ + ADC_CLPD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus0CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus0CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus0CalibrationValue(PeripheralBase) ( \ + ADC_CLM0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration0Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration0Reg(PeripheralBase, Value) ( \ + ADC_CLM0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM0, ADC1_CLM0, + * ADC2_CLM0, ADC3_CLM0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration0Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration0Reg(PeripheralBase) ( \ + ADC_CLM0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus1CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus1CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus1CalibrationValue(PeripheralBase) ( \ + ADC_CLM1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration1Reg(PeripheralBase, Value) ( \ + ADC_CLM1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM1, ADC1_CLM1, + * ADC2_CLM1, ADC3_CLM1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration1Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration1Reg(PeripheralBase) ( \ + ADC_CLM1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus2CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus2CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus2CalibrationValue(PeripheralBase) ( \ + ADC_CLM2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration2Reg(PeripheralBase, Value) ( \ + ADC_CLM2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM2, ADC1_CLM2, + * ADC2_CLM2, ADC3_CLM2 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration2Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration2Reg(PeripheralBase) ( \ + ADC_CLM2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus3CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus3CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus3CalibrationValue(PeripheralBase) ( \ + ADC_CLM3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration3Reg(PeripheralBase, Value) ( \ + ADC_CLM3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM3, ADC1_CLM3, + * ADC2_CLM3, ADC3_CLM3 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration3Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration3Reg(PeripheralBase) ( \ + ADC_CLM3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinus4CalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinus4CalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinus4CalibrationValue(PeripheralBase) ( \ + ADC_CLM4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibration4Reg(PeripheralBase, Value) ( \ + ADC_CLM4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLM4, ADC1_CLM4, + * ADC2_CLM4, ADC3_CLM4 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibration4Reg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibration4Reg(PeripheralBase) ( \ + ADC_CLM4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinusSCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value S. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinusSCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinusSCalibrationValue(PeripheralBase) ( \ + ADC_CLMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibrationSReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibrationSReg(PeripheralBase, Value) ( \ + ADC_CLMS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibrationSReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration S register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMS, ADC1_CLMS, + * ADC2_CLMS, ADC3_CLMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibrationSReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibrationSReg(PeripheralBase) ( \ + ADC_CLMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinusDCalibrationValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minus-side general calibration value D. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_GetMinusDCalibrationValue(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetMinusDCalibrationValue(PeripheralBase) ( \ + ADC_CLMD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMinusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Minus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * ADC_PDD_WriteMinusSideCalibrationDReg(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_WriteMinusSideCalibrationDReg(PeripheralBase, Value) ( \ + ADC_CLMD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinusSideCalibrationDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Minus-side calibration D register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ADC0_CLMD, ADC1_CLMD, + * ADC2_CLMD, ADC3_CLMD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * ADC_PDD_ReadMinusSideCalibrationDReg(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_ReadMinusSideCalibrationDReg(PeripheralBase) ( \ + ADC_CLMD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the voltage reference source used for conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param RefSel Reference selection. This parameter is of "Constants for + * voltage reference selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * ADC_PDD_SetVoltageReference(_BASE_PTR, ADC_PDD_VREF); + * @endcode + */ +#define ADC_PDD_SetVoltageReference(PeripheralBase, RefSel) ( \ + ADC_SC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC2_REFSEL_MASK))) | ( \ + (uint32)(RefSel))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the voltage reference source used for conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for voltage reference selection" type. + * The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetVoltageReference(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetVoltageReference(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & ADC_SC2_REFSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SampleTime Selects short/long sample time. This parameter is of + * "Constants for conversion speed selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetSampleTime(_BASE_PTR, ADC_PDD_SHORT); + * @endcode + */ +#define ADC_PDD_SetSampleTime(PeripheralBase, SampleTime) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADLSMP_MASK))) | ( \ + (uint32)((uint32)(SampleTime) << ADC_SC3_ADLSMP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSampleTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns short/long sample time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for conversion speed selection" type. + * The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetSampleTime(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetSampleTime(PeripheralBase) ( \ + ((uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADLPC_MASK) == 0U) ? ( \ + ADC_PDD_SHORT) : ( \ + ADC_PDD_LONG) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Conversion speed. This parameter is of "Constants for power mode + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetPowerMode(_BASE_PTR, ADC_PDD_NORMAL); + * @endcode + */ +#define ADC_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADLPC_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for power mode selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetPowerMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetPowerMode(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADLPC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param DivVal Divider value. This parameter is of "Constants for divider" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetDivider(_BASE_PTR, ADC_PDD_DIV_1); + * @endcode + */ +#define ADC_PDD_SetDivider(PeripheralBase, DivVal) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADIV_MASK))) | ( \ + (uint32)(DivVal))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for divider" type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetDivider(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetDivider(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADIV_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets resolution of the conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Resolution Resolution value. This parameter is of "Constants for + * resolution settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetResolution(_BASE_PTR, ADC_PDD_RES_8); + * @endcode + */ +#define ADC_PDD_SetResolution(PeripheralBase, Resolution) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_MODE_MASK))) | ( \ + (uint32)(Resolution))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResolution + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns resolution of the conversions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for resolution settings" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetResolution(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetResolution(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_MODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Resolution value. This parameter is of "Constants for clock + * source settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * ADC_PDD_SetClockSource(_BASE_PTR, ADC_PDD_PERIPH_CLK); + * @endcode + */ +#define ADC_PDD_SetClockSource(PeripheralBase, Source) ( \ + ADC_SC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC3_ADICLK_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for clock source settings" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC3. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetClockSource(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetClockSource(PeripheralBase) ( \ + (uint32)(ADC_SC3_REG(PeripheralBase) & ADC_SC3_ADICLK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_ScanMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets normal or scan mode for FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Normal or scan mode for FIFO. This parameter is of "Constants for + * FIFO scan mode settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_ScanMode(_BASE_PTR, ADC_PDD_NORMAL); + * @endcode + */ +#define ADC_PDD_SetFIFO_ScanMode(PeripheralBase, Mode) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_ASCANE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_ScanMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns normal or scan mode for FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO scan mode settings" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_ScanMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_ScanMode(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_ASCANE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_CompareMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets logic mode of the compared result inside FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Mode of comparing result inside FIFO. This parameter is of + * "Constants for FIFO compare mode settings" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_CompareMode(_BASE_PTR, ADC_PDD_OR); + * @endcode + */ +#define ADC_PDD_SetFIFO_CompareMode(PeripheralBase, Mode) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_ACFSEL_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_CompareMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns logic mode of the compared result inside FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO compare mode settings" type. + * The value is cast to "uint32". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_CompareMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_CompareMode(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_ACFSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_Depth + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects between FIFO disabled and FIFO level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Depth Parameter specifying the requested FIFO depth. Value should be + * in range from 1 to 8. Value equal to one means that FIFO is disabled and + * just one channel can be measured. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_SetFIFO_Depth(_BASE_PTR, 1); + * @endcode + */ +#define ADC_PDD_SetFIFO_Depth(PeripheralBase, Depth) ( \ + ADC_SC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC4_AFDEP_MASK))) | ( \ + (uint32)(uint8)(Depth) - 1U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_Depth + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns depth of the FIFO. Value equal to one means that FIFO is + * disabled and just one channel can be measured. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * uint8 result = ADC_PDD_GetFIFO_Depth(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_Depth(PeripheralBase) ( \ + (uint32)(ADC_SC4_REG(PeripheralBase) & ADC_SC4_AFDEP_MASK) + 1U \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_State + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for FIFO state" type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: ADC_SC2. + * @par Example: + * @code + * uint32 result = ADC_PDD_GetFIFO_State(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_State(PeripheralBase) ( \ + (uint32)(ADC_SC2_REG(PeripheralBase) & (uint32)((uint32)0x3U << 2U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFIFO_HW_TriggerMultipleConversions + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable/disable HW trigger multiple conversions in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC4. + * @par Example: + * @code + * ADC_PDD_EnableFIFO_HW_TriggerMultipleConversions(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableFIFO_HW_TriggerMultipleConversions(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + ADC_SC4_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC4_HTRGME_MASK)) : ( \ + ADC_SC4_REG(PeripheralBase) |= \ + ADC_SC4_HTRGME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFIFO_HW_TriggerMasking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable/disable HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * ADC_PDD_EnableFIFO_HW_TriggerMasking(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define ADC_PDD_EnableFIFO_HW_TriggerMasking(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + ADC_SC5_REG(PeripheralBase) &= \ + (uint32)(~(uint32)ADC_SC5_HTRGMASKE_MASK)) : ( \ + ADC_SC5_REG(PeripheralBase) |= \ + ADC_SC5_HTRGMASKE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFO_HW_TriggerMaskingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mode of the HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Mode of comparing result inside FIFO. This parameter is of + * "Constants for HW trigger masking mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * ADC_PDD_SetFIFO_HW_TriggerMaskingMode(_BASE_PTR, + * ADC_PDD_HAND); + * @endcode + */ +#define ADC_PDD_SetFIFO_HW_TriggerMaskingMode(PeripheralBase, Mode) ( \ + ADC_SC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(ADC_SC5_REG(PeripheralBase) & (uint32)(~(uint32)ADC_SC5_HTRGMASKSEL_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFIFO_HW_TriggerMaskingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mode of the HW trigger masking in FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for HW trigger masking mode" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: ADC_SC5. + * @par Example: + * @code + * uint8 result = + * ADC_PDD_GetFIFO_HW_TriggerMaskingMode(_BASE_PTR); + * @endcode + */ +#define ADC_PDD_GetFIFO_HW_TriggerMaskingMode(PeripheralBase) ( \ + (uint32)(ADC_SC5_REG(PeripheralBase) & ADC_SC5_HTRGMASKSEL_MASK) \ + ) +#endif /* #if defined(ADC_PDD_H_) */ + +/* ADC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h new file mode 100644 index 0000000..aae4e10 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CAN_PDD.h @@ -0,0 +1,2898 @@ +/* + PDD layer implementation for peripheral type CAN + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CAN_PDD_H_) +#define CAN_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CAN PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK10D7) /* CAN0 */ && \ + !defined(MCU_MK10F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK10DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20D7) /* CAN0 */ && \ + !defined(MCU_MK20F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK20DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK21F12) /* CAN0 */ && \ + !defined(MCU_MK21F12WS) /* CAN0 */ && \ + !defined(MCU_MK22F12) /* CAN0 */ && \ + !defined(MCU_MK24F12) /* CAN0 */ && \ + !defined(MCU_MK30D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK30D7) /* CAN0 */ && \ + !defined(MCU_MK30DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40D7) /* CAN0 */ && \ + !defined(MCU_MK40DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK40X256VMD100) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60D10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60DZ10) /* CAN0, CAN1 */ && \ + !defined(MCU_MK60N512VMD100) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F12WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK61F15WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK63F12) /* CAN0 */ && \ + !defined(MCU_MK63F12WS) /* CAN0 */ && \ + !defined(MCU_MK64F12) /* CAN0 */ && \ + !defined(MCU_MK65F18) /* CAN0, CAN1 */ && \ + !defined(MCU_MK65F18WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK66F18) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F12) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F15) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F12WS) /* CAN0, CAN1 */ && \ + !defined(MCU_MK70F15WS) /* CAN0, CAN1 */ + // Unsupported MCU is active + #error CAN PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Warning interrupt mask (for EnableWarningInterruptsMask, + DisableWarningInterruptsMask macros). */ +#define CAN_PDD_TX_WARNING_INT_MASK CAN_CTRL1_TWRNMSK_MASK /**< Tx warning interrupt mask. */ +#define CAN_PDD_RX_WARNING_INT_MASK CAN_CTRL1_RWRNMSK_MASK /**< Rx warning interrupt mask. */ + +/* Status flags constants (for GetStatusInterruptFlags1, + ClearStatusInterruptFlags1 macros). */ +#define CAN_PDD_SYNCHRONIZED_TO_CAN_BUS CAN_ESR1_SYNCH_MASK /**< CAN synchronization status flag */ +#define CAN_PDD_TX_WARNING_INT CAN_ESR1_TWRNINT_MASK /**< Tx warning interrupt Flag */ +#define CAN_PDD_RX_WARNING_INT CAN_ESR1_RWRNINT_MASK /**< Rx warning interrupt Flag */ +#define CAN_PDD_BIT1_ERROR CAN_ESR1_BIT1ERR_MASK /**< Bit1 error flag */ +#define CAN_PDD_BIT0_ERROR CAN_ESR1_BIT0ERR_MASK /**< Bit0 error flag */ +#define CAN_PDD_ACKNOWLEDGE_ERROR CAN_ESR1_ACKERR_MASK /**< Acknowledge error flag */ +#define CAN_PDD_CRC_ERROR CAN_ESR1_CRCERR_MASK /**< Cyclic redundancy check error flag */ +#define CAN_PDD_FORM_ERROR CAN_ESR1_FRMERR_MASK /**< Form error detected */ +#define CAN_PDD_SUFFTING_ERROR CAN_ESR1_STFERR_MASK /**< Stuffing error flag */ +#define CAN_PDD_TX_ERROR_WARNING CAN_ESR1_TXWRN_MASK /**< Tx error warning - repetitive errors are occurring during message transmission */ +#define CAN_PDD_RX_ERROR_WARNING CAN_ESR1_RXWRN_MASK /**< Rx error warning - repetitive errors are occurring during message reception */ +#define CAN_PDD_CAN_BUS_IDLE CAN_ESR1_IDLE_MASK /**< CAN bus IDLE state. */ +#define CAN_PDD_TRANSMITTING_MESSAGE CAN_ESR1_TX_MASK /**< FlexCAN in transmission */ +#define CAN_PDD_RECEIVING_MESSAGE CAN_ESR1_RX_MASK /**< FlexCAN in reception */ +#define CAN_PDD_BUS_OFF_INT CAN_ESR1_BOFFINT_MASK /**< FlexCAN enters Bus Off state */ +#define CAN_PDD_ERROR_INT CAN_ESR1_ERRINT_MASK /**< Error interrupt */ +#define CAN_PDD_WAKEUP_INT CAN_ESR1_WAKINT_MASK /**< Wake-Up interrupt */ + +/* CAN device state mode constants (for GetReadyStatus macro). */ +#define CAN_PDD_IS_READY 0x8000000U /**< CAN module is either in Disable Mode, Doze Mode, Stop Mode or Freeze Mode. */ +#define CAN_PDD_NOT_READY 0U /**< CAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. */ + +/* CAN device soft reset state constants (for GetSoftReset macro). */ +#define CAN_PDD_IS_RESET 0U /**< No reset request */ +#define CAN_PDD_NOT_RESET 0x2000000U /**< Resets the registers affected by soft reset. */ + +/* CAN device freeze state constants (for GetFreezeAck macro). */ +#define CAN_PDD_IS_FREEZE 0x1000000U /**< CAN in Freeze Mode, prescaler stopped */ +#define CAN_PDD_NOT_FREEZE 0U /**< CAN not in Freeze Mode, prescaler running */ + +/* CAN device low power mode constants (for GetLowPowerAcknowledge macro). */ +#define CAN_PDD_IS_LOW_POWER_MODE 0x100000U /**< CAN is either in Disable Mode, Doze Mode or Stop mode */ +#define CAN_PDD_NOT_LOW_POWER_MODE 0U /**< CAN is not in any of the low power modes */ + +/* Rx FIFO Acceptance ID Mode constants (for SetRxFIFOAcceptanceIDMode macro). */ +#define CAN_PDD_FORMAT_A 0U /**< One full ID (standard and extended) per ID Filter Table element */ +#define CAN_PDD_FORMAT_B 0x1U /**< Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Tableelement */ +#define CAN_PDD_FORMAT_C 0x2U /**< Four partial 8-bit Standard IDs per ID Filter Table element */ +#define CAN_PDD_FORMAT_D 0x3U /**< All frames rejected */ + +/* CAN Engine Clock Source constants (for SetClockSource macro). */ +#define CAN_PDD_XTAL_CLOCK 0U /**< The CAN engine clock source is the oscillator clock */ +#define CAN_PDD_BUS_CLOCK 0x2000U /**< The CAN engine clock source is the peripheral clock */ + +/* Rx sampling mode constants (for SetBitSampling macro). */ +#define CAN_PDD_ONE_SAMPLE 0U /**< Just one sample is used to determine the bit value */ +#define CAN_PDD_THREE_SAMPLES 0x80U /**< Three samples are used to determine the value of the received bit */ + +/* Message buffer interrupt and flag mask constant constants (for + EnableMessageBufferInterruptMask1, DisableMessageBufferInterruptMask1 macros). */ +#define CAN_PDD_MESSAGE_BUFFER_0 0x1U /**< Buffer MB0 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_1 0x2U /**< Buffer MB1 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_2 0x4U /**< Buffer MB2 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_3 0x8U /**< Buffer MB3 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_4 0x10U /**< Buffer MB4 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_5 0x20U /**< Buffer MB5 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_6 0x40U /**< Buffer MB6 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_7 0x80U /**< Buffer MB7 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_8 0x100U /**< Buffer MB8 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_9 0x200U /**< Buffer MB9 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_10 0x400U /**< Buffer MB10 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_11 0x800U /**< Buffer MB11 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_12 0x1000U /**< Buffer MB12 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_13 0x2000U /**< Buffer MB13 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_14 0x4000U /**< Buffer MB14 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_15 0x8000U /**< Buffer MB15 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_16 0x10000U /**< Buffer MB16 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_17 0x20000U /**< Buffer MB17 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_18 0x40000U /**< Buffer MB18 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_19 0x80000U /**< Buffer MB19 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_20 0x100000U /**< Buffer MB20 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_21 0x200000U /**< Buffer MB21 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_22 0x400000U /**< Buffer MB22 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_23 0x800000U /**< Buffer MB23 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_24 0x1000000U /**< Buffer MB24 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_25 0x2000000U /**< Buffer MB25 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_26 0x4000000U /**< Buffer MB26 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_27 0x8000000U /**< Buffer MB27 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_28 0x10000000U /**< Buffer MB28 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_29 0x20000000U /**< Buffer MB29 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_30 0x40000000U /**< Buffer MB30 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_31 0x80000000U /**< Buffer MB31 interrupt mask */ + +/* Number Rx FIFO filter constants (for SetNumberRxFIFOFilter macro). */ +#define CAN_PDD_RX_FIFO_FILTERS_8 0U /**< 8 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_16 0x1U /**< 16 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_24 0x2U /**< 24 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_32 0x3U /**< 32 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_40 0x4U /**< 40 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_48 0x5U /**< 48 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_56 0x6U /**< 56 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_64 0x7U /**< 64 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_72 0x8U /**< 72 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_80 0x9U /**< 80 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_88 0xAU /**< 88 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_96 0xBU /**< 96 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_104 0xCU /**< 104 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_112 0xDU /**< 112 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_120 0xEU /**< 120 Rx FIFO Filters */ +#define CAN_PDD_RX_FIFO_FILTERS_128 0xFU /**< 128 Rx FIFO Filters */ + +/* Mailboxes reception priority constants (for SetReceptionPriority macro). */ +#define CAN_PDD_START_FIFO_THEN_MAILBOXES 0U /**< Matching starts from Rx FIFO and continues on Mailboxes */ +#define CAN_PDD_START_MAILBOXES_THEN_FIFO 0x40000U /**< Matching starts from Mailboxes and continues on Rx FIFO */ + +/* Remote request priority constants (for SetRemoteRequestPriority macro). */ +#define CAN_PDD_GENERATE_REMOTE_RESPONSE_FRAME 0U /**< Remote Response Frame is generated */ +#define CAN_PDD_STORE_REMOTE_REQUEST_FRANE 0x20000U /**< Remote Request Frame is stored */ + +/* Rx message buffer codes constants (for SetMessageBufferCode, + GetMessageBufferCode macros) */ +#define CAN_PDD_MB_RX_NOT_ACTIVE 0U /**< MB is not active */ +#define CAN_PDD_MB_RX_FULL 0x2U /**< MB is full */ +#define CAN_PDD_MB_RX_EMPTY 0x4U /**< MB is active and empty */ +#define CAN_PDD_MB_RX_OVERRUN 0x6U /**< MB is being overwritten into a full buffer */ +#define CAN_PDD_MB_RX_BUSY 0x1U /**< FlexCAN is updating the contents of the MB */ +#define CAN_PDD_MB_RX_RANSWER 0xAU /**< A frame was configured to recognize a Remote Request Frame and transmit a ResponseFrame in return */ + +/* Tx message buffer codes constants (for SetMessageBufferCode, + GetMessageBufferCode macros) */ +#define CAN_PDD_MB_TX_NOT_ACTIVE 0x8U /**< MB is not active */ +#define CAN_PDD_MB_TX_ABORT 0x9U /**< MB is aborted */ +#define CAN_PDD_MB_TX_DATA_FRAME 0xCU /**< MB is a Tx Data Frame */ +#define CAN_PDD_MB_TX_REMOTE_FRAME 0xCU /**< MB is a Tx Remote Request Frame */ +#define CAN_PDD_MB_TX_RESPONSE_FRAME 0xAU /**< MB is a Tx Response Frame from an incoming Remote Request Frame */ + +/* Type of message buffer ID constants (for SetMessageBufferID, + GetMessageBufferID macros). */ +#define CAN_PDD_BUFFER_ID_EXT 0U /**< Extended frame format */ +#define CAN_PDD_BUFFER_ID_STD 0x1U /**< Standard frame format */ + +/* Message buffer interrupt and flag mask constant constants (for + EnableMessageBufferInterruptMask2, DisableMessageBufferInterruptMask2 macros). */ +#define CAN_PDD_MESSAGE_BUFFER_32 0x1U /**< Buffer MB32 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_33 0x2U /**< Buffer MB33 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_34 0x4U /**< Buffer MB34 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_35 0x8U /**< Buffer MB35 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_36 0x10U /**< Buffer MB36 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_37 0x20U /**< Buffer MB37 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_38 0x40U /**< Buffer MB38 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_39 0x80U /**< Buffer MB39 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_40 0x100U /**< Buffer MB40 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_41 0x200U /**< Buffer MB41 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_42 0x400U /**< Buffer MB42 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_43 0x800U /**< Buffer MB43 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_44 0x1000U /**< Buffer MB44 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_45 0x2000U /**< Buffer MB45 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_46 0x4000U /**< Buffer MB46 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_47 0x8000U /**< Buffer MB47 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_48 0x10000U /**< Buffer MB48 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_49 0x20000U /**< Buffer MB49 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_50 0x40000U /**< Buffer MB50 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_51 0x80000U /**< Buffer MB51 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_52 0x100000U /**< Buffer MB52 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_53 0x200000U /**< Buffer MB53 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_54 0x400000U /**< Buffer MB54 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_55 0x800000U /**< Buffer MB55 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_56 0x1000000U /**< Buffer MB56 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_57 0x2000000U /**< Buffer MB57 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_58 0x4000000U /**< Buffer MB58 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_59 0x8000000U /**< Buffer MB59 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_60 0x10000000U /**< Buffer MB60 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_61 0x20000000U /**< Buffer MB61 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_62 0x40000000U /**< Buffer MB62 interrupt mask */ +#define CAN_PDD_MESSAGE_BUFFER_63 0x80000000U /**< Buffer MB63 interrupt mask */ + + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_MDIS_MASK) : ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_MDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnterFreezeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enter CAN device to freeze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnterFreezeMode(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnterFreezeMode(PeripheralBase) ( \ + (CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_FRZ_MASK), \ + (CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_HALT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ExitFreezeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Return CAN device from freeze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ExitFreezeMode(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_ExitFreezeMode(PeripheralBase) ( \ + (CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_HALT_MASK)), \ + (CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_FRZ_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receive FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Rx FIFO will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableRxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableRxFIFO(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_RFEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_RFEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadyStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ready state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device state mode constants (for + * GetReadyStatus macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetReadyStatus(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetReadyStatus(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_NOTRDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the WakeUp interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWakeUpInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableWakeUpInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_WAKMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWakeUpInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the WakeUp interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWakeUpInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableWakeUpInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_WAKMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSoftReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enters to the soft reset mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetSoftReset(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_SetSoftReset(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_SOFTRST_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSoftResetState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the soft reset operation state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device soft reset state constants (for + * GetSoftReset macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetSoftResetState(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetSoftResetState(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_SOFTRST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFreezeAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the acknowledge of freeze operation state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device freeze state constants (for + * GetFreezeAck macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetFreezeAck(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetFreezeAck(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_FRZACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSupervizorMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables supervisor mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if supervisor mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSupervizorMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSupervizorMode(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_SUPV_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_SUPV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSelfWakeUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables self wake up feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if self wake up will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSelfWakeUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSelfWakeUp(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_SLFWAK_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_SLFWAK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWarningInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the warning interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWarningInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableWarningInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_WRNEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWarningInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the warning interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWarningInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableWarningInterrupt(PeripheralBase) ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_WRNEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLowPowerAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the low power state of CAN device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CAN device low power mode constants (for + * GetLowPowerAcknowledge macro)." type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetLowPowerAcknowledge(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetLowPowerAcknowledge(PeripheralBase) ( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & CAN_MCR_LPMACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSelfReception + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables self reception. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if self reception will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableSelfReception(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableSelfReception(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_MCR_REG(PeripheralBase) |= \ + CAN_MCR_SRXDIS_MASK) : ( \ + CAN_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_MCR_SRXDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInvidualRxMasking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables invidual Rx masking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if invidual Rx masking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableInvidualRxMasking(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableInvidualRxMasking(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_IRMQ_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_IRMQ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLocalPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables local priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if local priority will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLocalPriority(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLocalPriority(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_LPRIOEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_LPRIOEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAbort + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables abort a pending transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if abort a pending transmission will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableAbort(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableAbort(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_AEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_AEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFIFOAcceptanceIDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Rx FIFO acceptance ID mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Rx FIFO acceptance ID mode value[0..3]. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRxFIFOAcceptanceIDMode(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetRxFIFOAcceptanceIDMode(PeripheralBase, Mode) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_IDAM_MASK))) | ( \ + (uint32)((uint32)(Mode) << CAN_MCR_IDAM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNumberOfLastMessageBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the number of the last Message Buffer that will take part in the + * matching and arbitration processes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Number of the last Message Buffer value[0..127]. This parameter + * is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetNumberOfLastMessageBuffer(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetNumberOfLastMessageBuffer(PeripheralBase, Value) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_MAXMB_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescalerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the prescaler division factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Prescaler division factor value[0..255]. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPrescalerValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPrescalerValue(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PRESDIV_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PRESDIV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetResyncJumpWidthValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the resync jump width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Resync jump width value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetResyncJumpWidthValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetResyncJumpWidthValue(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_RJW_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_RJW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseSegment1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of phase segment 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Phase segment 1 value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPhaseSegment1Value(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPhaseSegment1Value(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PSEG1_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PSEG1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseSegment2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of phase segment 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Phase segment 2 value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPhaseSegment2Value(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPhaseSegment2Value(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PSEG2_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL1_PSEG2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusOffInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Bus Off interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableBusOffInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableBusOffInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_BOFFMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusOffInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Bus Off interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableBusOffInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableBusOffInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_BOFFMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_EnableErrorInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_ERRMSK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_DisableErrorInterrupt(PeripheralBase) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_ERRMSK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CAN Engine Clock Source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Parameter specifying clock source of CAN Engine. This + * parameter is of "CAN Engine Clock Source constants (for SetClockSource + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetClockSource(_BASE_PTR, CAN_PDD_XTAL_CLOCK); + * @endcode + */ +#define CAN_PDD_SetClockSource(PeripheralBase, ClkSource) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_CLKSRC_MASK))) | ( \ + (uint32)(ClkSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLoopBack + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Loop Back mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Loop Back will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLoopBack(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLoopBack(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LPB_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LPB_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWarningInterruptsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Warning Interrupts Mask defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Warning + * interrupt mask (for EnableWarningInterruptsMask, + * DisableWarningInterruptsMask macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWarningInterruptsMask(_BASE_PTR, + * CAN_PDD_TX_WARNING_INT_MASK); + * @endcode + */ +#define CAN_PDD_EnableWarningInterruptsMask(PeripheralBase, Mask) ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableWarningInterruptsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Warning Interrupts Mask defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Warning + * interrupt mask (for EnableWarningInterruptsMask, + * DisableWarningInterruptsMask macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableWarningInterruptsMask(_BASE_PTR, + * CAN_PDD_TX_WARNING_INT_MASK); + * @endcode + */ +#define CAN_PDD_DisableWarningInterruptsMask(PeripheralBase, Mask) ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBitSampling + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CAN bit sampling at the Rx input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Sampling Parameter specifying bit sampling at the Rx input. This + * parameter is of "Rx sampling mode constants (for SetBitSampling macro)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetBitSampling(_BASE_PTR, CAN_PDD_ONE_SAMPLE); + * @endcode + */ +#define CAN_PDD_SetBitSampling(PeripheralBase, Sampling) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_SMP_MASK))) | ( \ + (uint32)(Sampling))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusOffRecovery + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Bus Off Recovery. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Bus Off Recovery will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableBusOffRecovery(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableBusOffRecovery(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + CAN_CTRL1_REG(PeripheralBase) |= \ + CAN_CTRL1_BOFFREC_MASK) : ( \ + CAN_CTRL1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CAN_CTRL1_BOFFREC_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimerSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Timer Synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Timer Synchronization will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableTimerSynchronization(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableTimerSynchronization(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_TSYN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_TSYN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowestBufferTransmitFirst + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Lowest Buffer Transmit First. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Lowest Buffer Transmit First will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableLowestBufferTransmitFirst(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableLowestBufferTransmitFirst(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LBUF_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableListenOnlyMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Listen Only Mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Listen Only Mode will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableListenOnlyMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableListenOnlyMode(PeripheralBase, State) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_LOM_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL1_LOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPropagationSegment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Propagation Segment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Propagation Segment value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL1, CAN1_CTRL1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetPropagationSegment(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetPropagationSegment(PeripheralBase, Value) ( \ + CAN_CTRL1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL1_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL1_PROPSEG_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value of the Timer, value[0..65535]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_TIMER, CAN1_TIMER + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTimerValue(PeripheralBase, Value) ( \ + CAN_TIMER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_TIMER_REG(PeripheralBase) & (uint32)(~(uint32)CAN_TIMER_TIMER_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CAN0_TIMER, CAN1_TIMER + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CAN_PDD_GetTimerValue(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetTimerValue(PeripheralBase) ( \ + (uint16)(CAN_TIMER_REG(PeripheralBase) & CAN_TIMER_TIMER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Global Acceptance Mask for mailboxes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Global Acceptance Mask value[0..0x1FFFFFFF]. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RXMGMASK, + * CAN1_RXMGMASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetGlobalAcceptanceMask(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetGlobalAcceptanceMask(PeripheralBase, AccMask) ( \ + CAN_RXMGMASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetGlobalAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Global Acceptance Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RXMGMASK, + * CAN1_RXMGMASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetGlobalAcceptanceMask(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetGlobalAcceptanceMask(PeripheralBase) ( \ + CAN_RXMGMASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAcceptanceMask14 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Acceptance Mask for message buffer 14. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Acceptance Mask for message bugger 14 value[0..0x1FFFFFFF]. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RX14MASK, + * CAN1_RX14MASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetAcceptanceMask14(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetAcceptanceMask14(PeripheralBase, AccMask) ( \ + CAN_RX14MASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAcceptanceMask14 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Acceptance Mask for message buffer 14. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RX14MASK, + * CAN1_RX14MASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetAcceptanceMask14(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetAcceptanceMask14(PeripheralBase) ( \ + CAN_RX14MASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAcceptanceMask15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Acceptance Mask for message buffer 15. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AccMask Acceptance Mask for message bugger 15 value[0..0x1FFFFFFF]. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RX15MASK, + * CAN1_RX15MASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetAcceptanceMask15(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetAcceptanceMask15(PeripheralBase, AccMask) ( \ + CAN_RX15MASK_REG(PeripheralBase) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAcceptanceMask15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Acceptance Mask for message buffer 15. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RX15MASK, + * CAN1_RX15MASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetAcceptanceMask15(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetAcceptanceMask15(PeripheralBase) ( \ + CAN_RX15MASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the transmit error counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmit error counter value[0..255]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTxErrorCounter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTxErrorCounter(PeripheralBase, Value) ( \ + CAN_ECR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_ECR_TXERRCNT_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the transmit error counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetTxErrorCounter(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetTxErrorCounter(PeripheralBase) ( \ + (uint8)(CAN_ECR_REG(PeripheralBase) & CAN_ECR_TXERRCNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the receive error counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receive error counter value[0..255]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRxErrorCounter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetRxErrorCounter(PeripheralBase, Value) ( \ + CAN_ECR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_ECR_RXERRCNT_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ECR_RXERRCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxErrorCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the receive error counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CAN0_ECR, CAN1_ECR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetRxErrorCounter(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetRxErrorCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CAN_ECR_REG(PeripheralBase) & CAN_ECR_RXERRCNT_MASK)) >> ( \ + CAN_ECR_RXERRCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for + * GetStatusInterruptFlags1, ClearStatusInterruptFlags1 macros)." for processing return + * value. + * @remarks The macro accesses the following registers: CAN0_ESR1, CAN1_ESR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetStatusInterruptFlags1(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetStatusInterruptFlags1(PeripheralBase) ( \ + CAN_ESR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStatusInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants (for GetStatusInterruptFlags1, + * ClearStatusInterruptFlags1 macros).". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_ESR1, CAN1_ESR1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearStatusInterruptFlags1(_BASE_PTR, + * CAN_PDD_SYNCHRONIZED_TO_CAN_BUS); + * @endcode + */ +#define CAN_PDD_ClearStatusInterruptFlags1(PeripheralBase, Mask) ( \ + CAN_ESR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CAN_ESR1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(( \ + CAN_ESR1_WAKINT_MASK) | (( \ + CAN_ESR1_ERRINT_MASK) | (( \ + CAN_ESR1_BOFFINT_MASK) | (( \ + CAN_ESR1_RWRNINT_MASK) | ( \ + CAN_ESR1_TWRNINT_MASK))))))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferInterruptMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables message buffer[0..31] interrupt requests defined by mask + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK1, CAN1_IMASK1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferInterruptMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferInterruptMask1(PeripheralBase, Mask) ( \ + CAN_IMASK1_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMessageBufferInterruptMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables message buffer interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK1, CAN1_IMASK1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableMessageBufferInterruptMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_DisableMessageBufferInterruptMask1(PeripheralBase, Mask) ( \ + CAN_IMASK1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferInterruptFlag1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Message Buffer Interrupt flag register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_IFLAG1, CAN1_IFLAG1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetMessageBufferInterruptFlag1(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetMessageBufferInterruptFlag1(PeripheralBase) ( \ + CAN_IFLAG1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearMessageBufferInterruptFlagMask1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear Message Buffer Interrupt Flag defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IFLAG1, CAN1_IFLAG1 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearMessageBufferInterruptFlagMask1(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_ClearMessageBufferInterruptFlagMask1(PeripheralBase, Mask) ( \ + CAN_IFLAG1_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWriteAccessToMemory + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables Write Access To Memory In Freeze Mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if Write Access To Memory In Freeze Mode + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableWriteAccessToMemory(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableWriteAccessToMemory(PeripheralBase, State) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_WRMFRZ_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL2_WRMFRZ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNumberRxFIFOFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Number Rx FIFO filter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Number of Rx FIFO filter[0..3]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetNumberRxFIFOFilter(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetNumberRxFIFOFilter(PeripheralBase, Value) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_RFFN_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL2_RFFN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxArbitrationStartDelay + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of Tx Arbitration Start Delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value[0..31] of Tx Arbitration Start Delay. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetTxArbitrationStartDelay(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetTxArbitrationStartDelay(PeripheralBase, Value) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_TASD_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CTRL2_TASD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReceptionPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mailboxes reception priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying mailboxes reception priority. This + * parameter is of "Mailboxes reception priority constants (for + * SetReceptionPriority macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetReceptionPriority(_BASE_PTR, + * CAN_PDD_START_FIFO_THEN_MAILBOXES); + * @endcode + */ +#define CAN_PDD_SetReceptionPriority(PeripheralBase, Priority) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_MRP_MASK))) | ( \ + (uint32)(Priority))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRemoteRequestPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets remote request priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying remote request priority. This parameter + * is of "Remote request priority constants (for SetRemoteRequestPriority + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetRemoteRequestPriority(_BASE_PTR, + * CAN_PDD_GENERATE_REMOTE_RESPONSE_FRAME); + * @endcode + */ +#define CAN_PDD_SetRemoteRequestPriority(PeripheralBase, Priority) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_RRS_MASK))) | ( \ + (uint32)(Priority))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRTRComparison + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the comparison of both Rx Mailbox filter's IDE and + * RTR bit with their corresponding bitswithin the incoming frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Rx mailbox filter's. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_CTRL2, CAN1_CTRL2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableRTRComparison(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableRTRComparison(PeripheralBase, State) ( \ + CAN_CTRL2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_CTRL2_REG(PeripheralBase) & (uint32)(~(uint32)CAN_CTRL2_EACEN_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CTRL2_EACEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusRegister2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Error Status Register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_ESR2, CAN1_ESR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetErrorStatusRegister2(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetErrorStatusRegister2(PeripheralBase) ( \ + CAN_ESR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCRCRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CRC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_CRCR, CAN1_CRCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetCRCRegister(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetCRCRegister(PeripheralBase) ( \ + CAN_CRCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalRxFIFOMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets Global Rx FIFO Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Global Rx FIFO mask value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_RXFGMASK, + * CAN1_RXFGMASK (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetGlobalRxFIFOMask(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_SetGlobalRxFIFOMask(PeripheralBase, Mask) ( \ + CAN_RXFGMASK_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOInfoRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Rx FIFO Information Register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_RXFIR, CAN1_RXFIR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CAN_PDD_GetRxFIFOInfoRegister(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetRxFIFOInfoRegister(PeripheralBase) ( \ + CAN_RXFIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInvidualAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets value of invidual acceptance mask defined by Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param AccMask Acceptance mask value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RXIMR[Index]. + * @par Example: + * @code + * CAN_PDD_SetInvidualAcceptanceMask(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetInvidualAcceptanceMask(PeripheralBase, Index, AccMask) ( \ + CAN_RXIMR_REG(PeripheralBase,(Index)) = \ + (uint32)(AccMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInvidualAcceptanceMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value Invidual Acceptance Mask Register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RXIMR[Index]. + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetInvidualAcceptanceMask(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetInvidualAcceptanceMask(PeripheralBase, Index) ( \ + CAN_RXIMR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer code. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferCode(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferCode(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_CODE_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CS_CODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer code. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferCode(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferCode(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_CODE_MASK)) >> ( \ + CAN_CS_CODE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferDataLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer data length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..8]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferDataLength(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferDataLength(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_DLC_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_CS_DLC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferDataLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = + * CAN_PDD_GetMessageBufferDataLength(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferDataLength(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_DLC_MASK)) >> ( \ + CAN_CS_DLC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferTimeStamp + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer TimeStamp. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer code value[0..8]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferTimeStamp(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferTimeStamp(PeripheralBase, Index, Value) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_CS_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)CAN_CS_TIME_STAMP_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferTimeStamp + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer TimeStamp. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint16 result = + * CAN_PDD_GetMessageBufferTimeStamp(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferTimeStamp(PeripheralBase, Index) ( \ + (uint16)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_TIME_STAMP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferRTR + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables RTR of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested state of Remote Transmission Request bit. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferRTR(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferRTR(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_RTR_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_RTR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferRTR + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of RTR bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferRTR(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferRTR(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_RTR_MASK)) >> ( \ + CAN_CS_RTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferSRR + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SRR of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested state of Substitute Remote Request bit. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferSRR(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferSRR(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_SRR_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_SRR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferSRR + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of SRR bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferSRR(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferSRR(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_SRR_MASK)) >> ( \ + CAN_CS_SRR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferIDExt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables extended ID of the message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param State Requested frame format. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferIDExt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferIDExt(PeripheralBase, Index, State) ( \ + CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_CS_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_CS_IDE_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_CS_IDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferIDExt + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of ID extended bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CS[Index]. + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferIDExt(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferIDExt(PeripheralBase, Index) ( \ + ((uint32)(CAN_CS_REG(PeripheralBase,(Index)) & CAN_CS_IDE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferID + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of message buffer ID. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param TypeID Requested ID format. This parameter is of "Type of message + * buffer ID constants (for SetMessageBufferID, GetMessageBufferID macros)." + * type. + * @param Value ID value. This parameter is a 29-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferID(_BASE_PTR, periphID, + * CAN_PDD_BUFFER_ID_EXT, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferID(PeripheralBase, Index, TypeID, Value) ( \ + ((TypeID) == CAN_PDD_BUFFER_ID_STD) ? ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_ID_STD_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ID_STD_SHIFT)))) : ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_ID_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(CAN_ID_STD_MASK | CAN_ID_EXT_MASK))))) | ( \ + (uint32)(Value)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferID + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value ID of message buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param TypeID Requested ID format. This parameter is of "Type of message + * buffer ID constants (for SetMessageBufferID, GetMessageBufferID macros)." + * type. + * @return Returns a 29-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferID(_BASE_PTR, + * periphID, CAN_PDD_BUFFER_ID_EXT); + * @endcode + */ +#define CAN_PDD_GetMessageBufferID(PeripheralBase, Index, TypeID) ( \ + ((TypeID) == CAN_PDD_BUFFER_ID_STD) ? ( \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & CAN_ID_STD_MASK)) >> ( \ + CAN_ID_STD_SHIFT))) : ( \ + (uint32)(( \ + CAN_ID_REG(PeripheralBase,(Index))) & ( \ + (uint32)(CAN_ID_STD_MASK | CAN_ID_EXT_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferWORD0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer data WORD0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer data value[0..0xFFFFFFFF]. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD0[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferWORD0(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferWORD0(PeripheralBase, Index, Value) ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferWORD0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data WORD0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: WORD0[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferWORD0(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferWORD0(PeripheralBase, Index) ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferWORD1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the message buffer message buffer data WORD1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Message buffer data value[0..0xFFFFFFFF]. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD1[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferWORD1(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferWORD1(PeripheralBase, Index, Value) ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferWORD1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of message buffer data WORD1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: WORD1[Index]. + * @par Example: + * @code + * uint32 result = CAN_PDD_GetMessageBufferWORD1(_BASE_PTR, + * periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferWORD1(PeripheralBase, Index) ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field in the message buffer denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param ByteIndex Data byte index. This parameter is of index type. + * @param Value Data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WORD0[Index], + * WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetMessageBufferData(_BASE_PTR, periphID, periphID, + * 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferData(PeripheralBase, Index, ByteIndex, Value) ( \ + ((uint8)((uint8)(ByteIndex) & 0xFCU) == 0U) ? ( \ + CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_WORD0_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(( \ + (uint32)0xFFU) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U))))))) | ( \ + (uint32)(( \ + (uint32)(Value)) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))))) : ( \ + CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + CAN_WORD1_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)(( \ + (uint32)0xFFU) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U))))))) | ( \ + (uint32)(( \ + (uint32)(Value)) << ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the data field in the message buffer denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param ByteIndex Data byte index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WORD0[Index], + * WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CAN_PDD_GetMessageBufferData(_BASE_PTR, + * periphID, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferData(PeripheralBase, Index, ByteIndex) ( \ + ((uint8)((uint8)(ByteIndex) & 0xFCU) == 0U) ? ( \ + (uint8)(( \ + CAN_WORD0_REG(PeripheralBase,(Index))) >> ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))) : ( \ + (uint8)(( \ + CAN_WORD1_REG(PeripheralBase,(Index))) >> ( \ + 24U - (uint8)((uint8)((uint8)(ByteIndex) & 0x3U) << 3U)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMessageBufferLocalPrio + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Local Priority Field within the message ID buffer + * denominated by Index. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param Value Local priority value[0..7]. This parameter is a 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * CAN_PDD_SetMessageBufferLocalPrio(_BASE_PTR, periphID, 1); + * @endcode + */ +#define CAN_PDD_SetMessageBufferLocalPrio(PeripheralBase, Index, Value) ( \ + CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)CAN_ID_PRIO_MASK))) | ( \ + (uint32)((uint32)(Value) << CAN_ID_PRIO_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferLocalPrio + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of Local priority. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ID[Index]. + * @par Example: + * @code + * uint8 result = + * CAN_PDD_GetMessageBufferLocalPrio(_BASE_PTR, periphID); + * @endcode + */ +#define CAN_PDD_GetMessageBufferLocalPrio(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(CAN_ID_REG(PeripheralBase,(Index)) & CAN_ID_PRIO_MASK)) >> ( \ + CAN_ID_PRIO_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFIFOFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the filters for FIFO table, this table is located on unavailable + * MB memory space. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Message buffer index. This parameter is of index type. + * @param CS Value of CS register. This parameter is a 32-bit value. + * @param ID Value of ID register. This parameter is a 32-bit value. + * @param WORD0 Value of WORD0 register. This parameter is a 32-bit value. + * @param WORD1 Value of WORD1 register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CS[Index], ID[Index], + * WORD0[Index], WORD1[Index] (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_SetFIFOFilter(_BASE_PTR, periphID, 1, 1, 1, 1); + * @endcode + */ +#define CAN_PDD_SetFIFOFilter(PeripheralBase, Index, CS, ID, WORD0, WORD1) ( \ + (CAN_CS_REG(PeripheralBase,(Index)) = \ + (uint32)(CS)), \ + ((CAN_ID_REG(PeripheralBase,(Index)) = \ + (uint32)(ID)), \ + ((CAN_WORD0_REG(PeripheralBase,(Index)) = \ + (uint32)(WORD0)), \ + (CAN_WORD1_REG(PeripheralBase,(Index)) = \ + (uint32)(WORD1)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMessageBufferInterruptMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables message buffer[32..63] interrupt requests defined by mask + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK2, CAN1_IMASK2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableMessageBufferInterruptMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_EnableMessageBufferInterruptMask2(PeripheralBase, Mask) ( \ + CAN_IMASK2_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMessageBufferInterruptMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables message buffer interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Message buffer interrupt mask value[0..0xFFFFFFFF]. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IMASK2, CAN1_IMASK2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_DisableMessageBufferInterruptMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_DisableMessageBufferInterruptMask2(PeripheralBase, Mask) ( \ + CAN_IMASK2_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMessageBufferInterruptFlag2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of Message Buffer Interrupt flag register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CAN0_IFLAG2, CAN1_IFLAG2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * CAN_PDD_GetMessageBufferInterruptFlag2(_BASE_PTR); + * @endcode + */ +#define CAN_PDD_GetMessageBufferInterruptFlag2(PeripheralBase) ( \ + CAN_IFLAG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearMessageBufferInterruptFlagMask2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear Message Buffer Interrupt Flag defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_IFLAG2, CAN1_IFLAG2 + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_ClearMessageBufferInterruptFlagMask2(_BASE_PTR, 1); + * @endcode + */ +#define CAN_PDD_ClearMessageBufferInterruptFlagMask2(PeripheralBase, Mask) ( \ + CAN_IFLAG2_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if doze mode will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CAN0_MCR, CAN1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * CAN_PDD_EnableDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CAN_PDD_EnableDozeMode(PeripheralBase, State) ( \ + CAN_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CAN_MCR_REG(PeripheralBase) & (uint32)(~(uint32)CAN_MCR_DOZE_MASK))) | ( \ + (uint32)((uint32)(State) << CAN_MCR_DOZE_SHIFT))) \ + ) +#endif /* #if defined(CAN_PDD_H_) */ + +/* CAN_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h new file mode 100644 index 0000000..f3a871b --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMP_PDD.h @@ -0,0 +1,2501 @@ +/* + PDD layer implementation for peripheral type CMP + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CMP_PDD_H_) +#define CMP_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CMP PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK10D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK10D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK10F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK10DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK11D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK11D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MK12D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK20D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK20D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK20D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK20F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK20DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK21D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK21D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MK21F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK21F12WS) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK22D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F12810) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK22F25612) /* CMP0, CMP1 */ && \ + !defined(MCU_MK22F51212) /* CMP0, CMP1 */ && \ + !defined(MCU_MK24F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK30DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK40X256VMD100) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK50DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51D7) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK51DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK52D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK52DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK53D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK53DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60D10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK60F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK60DZ10) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK60N512VMD100) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK61F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F12WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK61F15WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK63F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK63F12WS) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK64F12) /* CMP0, CMP1, CMP2 */ && \ + !defined(MCU_MK65F18) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK65F18WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK66F18) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F12) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F15) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F12WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MK70F15WS) /* CMP0, CMP1, CMP2, CMP3 */ && \ + !defined(MCU_MKE02Z2) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE02Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_SKEAZN642) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE04Z1284) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE04Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_SKEAZN84) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKE06Z4) /* ACMP0, ACMP1 */ && \ + !defined(MCU_MKL02Z4) /* CMP0 */ && \ + !defined(MCU_MKL03Z4) /* CMP0 */ && \ + !defined(MCU_MKL04Z4) /* CMP0 */ && \ + !defined(MCU_MKL05Z4) /* CMP0 */ && \ + !defined(MCU_MKL14Z4) /* CMP0 */ && \ + !defined(MCU_MKL15Z4) /* CMP0 */ && \ + !defined(MCU_MKL16Z4) /* CMP0 */ && \ + !defined(MCU_MKL24Z4) /* CMP0 */ && \ + !defined(MCU_MKL25Z4) /* CMP0 */ && \ + !defined(MCU_MKL26Z4) /* CMP0 */ && \ + !defined(MCU_MKL34Z4) /* CMP0 */ && \ + !defined(MCU_MKL36Z4) /* CMP0 */ && \ + !defined(MCU_MKL46Z4) /* CMP0 */ && \ + !defined(MCU_MKV10Z7) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F12810) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F25612) /* CMP0, CMP1 */ && \ + !defined(MCU_MKV31F51212) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW01Z4) /* CMP0 */ && \ + !defined(MCU_MKW21D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW21D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW22D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW22D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW24D5) /* CMP0, CMP1 */ && \ + !defined(MCU_MKW24D5WS) /* CMP0, CMP1 */ && \ + !defined(MCU_PCK20L4) /* CMP0, CMP1 */ && \ + !defined(MCU_SKEAZ1284) /* ACMP0, ACMP1 */ + // Unsupported MCU is active + #error CMP PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Interrupts' mask */ + #define CMP_PDD_EDGE_INTERRUPT ACMP_CS_ACIE_MASK /**< Falling edge interrupt enable mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Interrupts' mask */ + #define CMP_PDD_FALLING_EDGE_INTERRUPT CMP_SCR_IEF_MASK /**< Falling edge interrupt enable mask. */ + #define CMP_PDD_RISING_EDGE_INTERRUPT CMP_SCR_IER_MASK /**< Rising edge interrupt enable mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Interrupts' flags */ + #define CMP_PDD_EDGE_FLAG ACMP_CS_ACF_MASK /**< Edge flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Interrupts' flags */ + #define CMP_PDD_FALLING_EDGE_FLAG CMP_SCR_CFF_MASK /**< Falling edge flag. */ + #define CMP_PDD_RISING_EDGE_FLAG CMP_SCR_CFR_MASK /**< Rising edge flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Comparator modes */ + #define CMP_PDD_FALLING_EDGE_MODE 0U /**< Falling edge detection mode. */ + #define CMP_PDD_RISING_EDGE_MODE 0x1U /**< Rising edge detection mode. */ + #define CMP_PDD_BOTH_EDGES_MODE 0x3U /**< Both falling and rising edge detection mode. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Comparator modes */ + #define CMP_PDD_FALLING_EDGE_MODE CMP_SCR_IEF_MASK /**< Falling edge detection mode. */ + #define CMP_PDD_RISING_EDGE_MODE CMP_SCR_IER_MASK /**< Rising edge detection mode. */ + #define CMP_PDD_BOTH_EDGES_MODE 0x18U /**< Both falling and rising edge detection mode. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* External input mask */ +#define CMP_PDD_EXTERNAL_INPUT_0 0x1U /**< External input 0 */ +#define CMP_PDD_EXTERNAL_INPUT_1 0x2U /**< External input 1 */ +#define CMP_PDD_EXTERNAL_INPUT_2 0x4U /**< External input 2 */ + +/* Deprecated: Hysteresis constants. Please use HYSTERESIS_LEVEL_X constants. */ +#define CMP_PDD_HYSTERESIS_DISABLE 0U /**< Hysteresis not used. */ +#define CMP_PDD_HYSTERESIS_20MV 0x1U /**< 20 mV hysteresis used. */ +#define CMP_PDD_HYSTERESIS_40MV 0x2U /**< 40 mV hysteresis used. */ +#define CMP_PDD_HYSTERESIS_60MV 0x3U /**< 60 mV hysteresis used. */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Hysteresis constants. For exact value representation see peripheral device + documentation. */ + #define CMP_PDD_HYSTERESIS_LEVEL_0 0U /**< Level 0 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_1 0x40U /**< Level 1 hysteresis used. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Hysteresis constants. For exact value representation see peripheral device + documentation. */ + #define CMP_PDD_HYSTERESIS_LEVEL_0 0U /**< Level 0 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_1 0x1U /**< Level 1 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_2 0x2U /**< Level 2 hysteresis used. */ + #define CMP_PDD_HYSTERESIS_LEVEL_3 0x3U /**< Level 3 hysteresis used. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Filter sample count constants. */ +#define CMP_PDD_FILTER_DISABLED 0U /**< Filter disabled. */ +#define CMP_PDD_FILTER_1_SAMPLE 0x10U /**< 1 consecutive sample must agree. */ +#define CMP_PDD_FILTER_2_SAMPLES 0x20U /**< 2 consecutive samples must agree. */ +#define CMP_PDD_FILTER_3_SAMPLES 0x30U /**< 3 consecutive samples must agree. */ +#define CMP_PDD_FILTER_4_SAMPLES 0x40U /**< 4 consecutive samples must agree. */ +#define CMP_PDD_FILTER_5_SAMPLES 0x50U /**< 5 consecutive samples must agree. */ +#define CMP_PDD_FILTER_6_SAMPLES 0x60U /**< 6 consecutive samples must agree. */ +#define CMP_PDD_FILTER_7_SAMPLES 0x70U /**< 7 consecutive samples must agree. */ + +/* Comparator output filtration constant */ +#define CMP_PDD_FILTERED_OUTPUT 0U /**< Filtered comparator output. */ +#define CMP_PDD_UNFILTERED_OUTPUT CMP_CR1_COS_MASK /**< Filter on comparator output is bypassed. */ + +/* Comparator output inversion constant. */ +#define CMP_PDD_NOT_INVERTED_OUTPUT 0U /**< Comparator output is not inverted. */ +#define CMP_PDD_INVERTED_OUTPUT CMP_CR1_INV_MASK /**< Comparator output is inverted. */ + +/* Comparator power mode constant. */ +#define CMP_PDD_LOW_POWER_MODE 0U /**< Low power/low speed mode. */ +#define CMP_PDD_HIGH_SPEED_MODE CMP_CR1_PMODE_MASK /**< High power/high speed mode. */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100))) +/* Comparator's interrupt stop mode constant. */ + #define CMP_PDD_LEVEL_SENSITIVE_MODE 0U /**< Comparator is level sensitive in stop mode */ + #define CMP_PDD_EDGE_SENSITIVE_MODE CMP_SCR_SMELB_MASK /**< Comparator is edge sensitive in stop mode */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Comparator's interrupt stop mode constant. */ + #define CMP_PDD_LEVEL_SENSITIVE_MODE 0U /**< Comparator is level sensitive in stop mode */ + #define CMP_PDD_EDGE_SENSITIVE_MODE 0x1U /**< Comparator is edge sensitive in stop mode */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Analog comparator 6-bit DAC supply voltage reference source constant. For + exact connection see peripheral device documentation. */ + #define CMP_PDD_V_REF_INPUT_1 0U /**< Vin1 reference. */ + #define CMP_PDD_V_REF_INPUT_2 ACMP_C1_DACREF_MASK /**< Vin2 reference */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Analog comparator 6-bit DAC supply voltage reference source constant. */ + #define CMP_PDD_V_REF_INPUT_1 0U /**< Vin1 reference. */ + #define CMP_PDD_V_REF_INPUT_2 CMP_DACCR_VRSEL_MASK /**< Vin2 reference */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Negative input constant. */ + #define CMP_PDD_NEGATIVE_INPUT_0 0U /**< Negative input 0. */ + #define CMP_PDD_NEGATIVE_INPUT_1 0x1U /**< Negative input 1. */ + #define CMP_PDD_NEGATIVE_INPUT_2 0x2U /**< Negative input 2. */ + #define CMP_PDD_NEGATIVE_INPUT_3 0x3U /**< Negative input 3. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Negative input constant. */ + #define CMP_PDD_NEGATIVE_INPUT_0 0U /**< Negative input 0. */ + #define CMP_PDD_NEGATIVE_INPUT_1 0x1U /**< Negative input 1. */ + #define CMP_PDD_NEGATIVE_INPUT_2 0x2U /**< Negative input 2. */ + #define CMP_PDD_NEGATIVE_INPUT_3 0x3U /**< Negative input 3. */ + #define CMP_PDD_NEGATIVE_INPUT_4 0x4U /**< Negative input 4. */ + #define CMP_PDD_NEGATIVE_INPUT_5 0x5U /**< Negative input 5. */ + #define CMP_PDD_NEGATIVE_INPUT_6 0x6U /**< Negative input 6. */ + #define CMP_PDD_NEGATIVE_INPUT_7 0x7U /**< Negative input 7. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Positive input constant. */ + #define CMP_PDD_POSITIVE_INPUT_0 0U /**< Positive input 0. */ + #define CMP_PDD_POSITIVE_INPUT_1 0x10U /**< Positive input 1. */ + #define CMP_PDD_POSITIVE_INPUT_2 0x20U /**< Positive input 2. */ + #define CMP_PDD_POSITIVE_INPUT_3 0x30U /**< Positive input 3. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Positive input constant. */ + #define CMP_PDD_POSITIVE_INPUT_0 0U /**< Positive input 0. */ + #define CMP_PDD_POSITIVE_INPUT_1 0x8U /**< Positive input 1. */ + #define CMP_PDD_POSITIVE_INPUT_2 0x10U /**< Positive input 2. */ + #define CMP_PDD_POSITIVE_INPUT_3 0x18U /**< Positive input 3. */ + #define CMP_PDD_POSITIVE_INPUT_4 0x20U /**< Positive input 4. */ + #define CMP_PDD_POSITIVE_INPUT_5 0x28U /**< Positive input 5. */ + #define CMP_PDD_POSITIVE_INPUT_6 0x30U /**< Positive input 6. */ + #define CMP_PDD_POSITIVE_INPUT_7 0x38U /**< Positive input 7. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the comparator's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of comparator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDevice(PeripheralBase, State) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACE_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_CS_ACE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the comparator's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of comparator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDevice(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_EN_MASK))) | ( \ + (uint8)(State))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetDeviceEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of comparator's enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of comparator's enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_EN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableInterrupts(_BASE_PTR, CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableInterrupts(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_SCR_REG(PeripheralBase) | (uint8)(Mask))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_DisableInterrupts(_BASE_PTR, + * CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_DisableInterrupts(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetInterruptMask(_BASE_PTR, CMP_PDD_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACIE_MASK))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetInterruptMask(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)(CMP_SCR_IEF_MASK | CMP_SCR_IER_MASK))) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACIE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & (uint8)(CMP_SCR_IEF_MASK | CMP_SCR_IER_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACF_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & (uint8)(CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_ClearInterruptFlags(_BASE_PTR, CMP_PDD_EDGE_FLAG); + * @endcode + */ + #define CMP_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACF_MASK))) | ( \ + (uint8)((uint8)(~(uint8)(Mask)) & ACMP_CS_ACF_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' mask". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_ClearInterruptFlags(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_INTERRUPT); + * @endcode + */ + #define CMP_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetHysteresis + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets comparator hard block hysteresis control bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Hysteresis Hysteresis value. This parameter is of "Hysteresis + * constants. For exact value representation see peripheral device documentation." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetHysteresis(_BASE_PTR, + * CMP_PDD_HYSTERESIS_LEVEL_0); + * @endcode + */ + #define CMP_PDD_SetHysteresis(PeripheralBase, Hysteresis) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_HYST_MASK))) | ( \ + (uint8)(Hysteresis))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets comparator hard block hysteresis control bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Hysteresis Hysteresis value. This parameter is of "Hysteresis + * constants. For exact value representation see peripheral device documentation." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetHysteresis(_BASE_PTR, + * CMP_PDD_HYSTERESIS_LEVEL_0); + * @endcode + */ + #define CMP_PDD_SetHysteresis(PeripheralBase, Hysteresis) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR0_HYSTCTR_MASK))) | ( \ + (uint8)(Hysteresis))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetHysteresis + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Hysteresis constants. For exact value + * representation see peripheral device documentation." type. The value is cast to + * "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetHysteresis(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetHysteresis(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_HYST_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Hysteresis constants. For exact value + * representation see peripheral device documentation." type. The value is cast to + * "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetHysteresis(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetHysteresis(PeripheralBase) ( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & CMP_CR0_HYSTCTR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter sample count bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Filter sample count. This parameter is of "Filter sample count + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetFilterCount(_BASE_PTR, CMP_PDD_FILTER_DISABLED); + * @endcode + */ +#define CMP_PDD_SetFilterCount(PeripheralBase, Count) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR0_FILTER_CNT_MASK))) | ( \ + (uint8)(Count))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current level of hysteresis. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Filter sample count constants." type. The value + * is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetFilterCount(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetFilterCount(PeripheralBase) ( \ + (uint8)(CMP_CR0_REG(PeripheralBase) & CMP_CR0_FILTER_CNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOutputPin + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Comparator output pin enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if output pin will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableOutputPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableOutputPin(PeripheralBase, State) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACOPE_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_CS_ACOPE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Comparator output pin enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if output pin will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableOutputPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableOutputPin(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_OPE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_OPE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetOutputPinEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns whether is the output pin enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetOutputPinEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetOutputPinEnabled(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACOPE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns whether is the output pin enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetOutputPinEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetOutputPinEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_OPE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetComparatorOutputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator output filtration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Output Parameter specifying if output will be filtered or not. This + * parameter is of "Comparator output filtration constant" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorOutputFilter(_BASE_PTR, + * CMP_PDD_FILTERED_OUTPUT); + * @endcode + */ +#define CMP_PDD_SetComparatorOutputFilter(PeripheralBase, Output) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_COS_MASK))) | ( \ + (uint8)(Output))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of comparator output filtration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator output filtration constant" type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetComparatorOutputFilter(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorOutputFilter(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_COS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComparatorOutputInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator output inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Output Parameter specifying if output will be inverted or not. This + * parameter is of "Comparator output inversion constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorOutputInversion(_BASE_PTR, + * CMP_PDD_NOT_INVERTED_OUTPUT); + * @endcode + */ +#define CMP_PDD_SetComparatorOutputInversion(PeripheralBase, Output) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_INV_MASK))) | ( \ + (uint8)(Output))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutputInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the comparator output is inverted. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator output inversion constant." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetComparatorOutputInversion(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorOutputInversion(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_INV_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects comparator power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Power mode. This parameter is of "Comparator power mode + * constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetPowerMode(_BASE_PTR, CMP_PDD_LOW_POWER_MODE); + * @endcode + */ +#define CMP_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_PMODE_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current comparator power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Comparator power mode constant." type. The value + * is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPowerMode(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetPowerMode(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_PMODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWindowing + ---------------------------------------------------------------------------- */ + +/** + * @brief Windowing enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if windowing will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableWindowing(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableWindowing(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_WE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_WE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetWindowingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the windowing is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetWindowingEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetWindowingEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_WE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSampling + ---------------------------------------------------------------------------- */ + +/** + * @brief Sampling enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if sampling will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableSampling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableSampling(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_SE_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_SE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSamplingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the sampling is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetSamplingEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetSamplingEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_SE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterPeriod + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter sample period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Filter sample period value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetFilterPeriod(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_SetFilterPeriod(PeripheralBase, Period) ( \ + CMP_FPR_REG(PeripheralBase) = \ + (uint8)(Period) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterPeriod + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current filter sample period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetFilterPeriod(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetFilterPeriod(PeripheralBase) ( \ + CMP_FPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorOutput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current comparator output state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorOutput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetComparatorOutput(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACO_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current comparator output state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR, ACMP0_CS, ACMP1_CS (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorOutput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetComparatorOutput(PeripheralBase) ( \ + (uint8)(CMP_SCR_REG(PeripheralBase) & CMP_SCR_COUT_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)CMP_SCR_DMAEN_MASK)) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)((uint8)(State) << CMP_SCR_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComparatorMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets comparator's interrupt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Comparator interrupt mode. Use constants from group "Comparator + * modes". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorMode(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_MODE); + * @endcode + */ + #define CMP_PDD_SetComparatorMode(PeripheralBase, Mode) ( \ + ACMP_CS_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_CS_ACMOD_MASK))) | ( \ + (uint8)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets comparator's interrupt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Comparator interrupt mode. Use constants from group "Comparator + * modes". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetComparatorMode(_BASE_PTR, + * CMP_PDD_FALLING_EDGE_MODE); + * @endcode + */ + #define CMP_PDD_SetComparatorMode(PeripheralBase, Mode) ( \ + CMP_PDD_SetInterruptMask(PeripheralBase, (uint8)(Mode)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCompareStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns last detected edge on comparator's output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' mask" for processing return + * value. + * @par Example: + * @code + * uint8 result = CMP_PDD_GetCompareStatus(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetCompareStatus(PeripheralBase) ( \ + CMP_PDD_GetInterruptFlags(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetVoltage + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Output voltage value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetVoltage(_BASE_PTR, 1); + * @endcode + */ + #define CMP_PDD_SetVoltage(PeripheralBase, Value) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACVAL_MASK))) | ( \ + (uint8)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Output voltage value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetVoltage(_BASE_PTR, 1); + * @endcode + */ + #define CMP_PDD_SetVoltage(PeripheralBase, Value) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_VOSEL_MASK))) | ( \ + (uint8)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetVoltage + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetVoltage(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetVoltage(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACVAL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current DAC6b output voltage. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetVoltage(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetVoltage(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_VOSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetReference + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects analog comparator 6-bit DAC supply voltage reference source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Supply voltage source. This parameter is of "Analog + * comparator 6-bit DAC supply voltage reference source constant. For exact + * connection see peripheral device documentation." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetReference(_BASE_PTR, CMP_PDD_V_REF_INPUT_1); + * @endcode + */ + #define CMP_PDD_SetReference(PeripheralBase, Reference) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACREF_MASK))) | ( \ + (uint8)(Reference))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects analog comparator 6-bit DAC supply voltage reference source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Supply voltage source. This parameter is of "Analog + * comparator 6-bit DAC supply voltage reference source constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetReference(_BASE_PTR, CMP_PDD_V_REF_INPUT_1); + * @endcode + */ + #define CMP_PDD_SetReference(PeripheralBase, Reference) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_VRSEL_MASK))) | ( \ + (uint8)(Reference))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetReference + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected reference input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Analog comparator 6-bit DAC supply voltage + * reference source constant. For exact connection see peripheral device + * documentation." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetReference(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetReference(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACREF_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected reference input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Analog comparator 6-bit DAC supply voltage + * reference source constant." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetReference(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetReference(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_VRSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDac + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Analog comparator 6-bit DAC enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DAC will be enabled or disabled. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDac(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDac(PeripheralBase, State) ( \ + ACMP_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C1_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << ACMP_C1_DACEN_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Analog comparator 6-bit DAC enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DAC will be enabled or disabled. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_EnableDac(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define CMP_PDD_EnableDac(PeripheralBase, State) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_DACCR_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_DACCR_DACEN_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetDacEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of analog comparator 6-bit DAC enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDacEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDacEnabled(PeripheralBase) ( \ + (uint8)(ACMP_C1_REG(PeripheralBase) & ACMP_C1_DACEN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of analog comparator 6-bit DAC enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR, ACMP0_C1, ACMP1_C1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetDacEnabled(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetDacEnabled(PeripheralBase) ( \ + (uint8)(CMP_DACCR_REG(PeripheralBase) & CMP_DACCR_DACEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetNegativeInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets negative comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param NegativeInput Negative input number. This parameter is of "Negative + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetNegativeInput(_BASE_PTR, + * CMP_PDD_NEGATIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetNegativeInput(PeripheralBase, NegativeInput) ( \ + ACMP_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C0_ACNSEL_MASK))) | ( \ + (uint8)(NegativeInput))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets negative comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param NegativeInput Negative input number. This parameter is of "Negative + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetNegativeInput(_BASE_PTR, + * CMP_PDD_NEGATIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetNegativeInput(PeripheralBase, NegativeInput) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_MSEL_MASK))) | ( \ + (uint8)(NegativeInput))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetNegativeInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected negative input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Negative input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetNegativeInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetNegativeInput(PeripheralBase) ( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & ACMP_C0_ACNSEL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected negative input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Negative input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetNegativeInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetNegativeInput(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_MSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPositiveInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets positive comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PositiveInput Positive input number. This parameter is of "Positive + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetPositiveInput(_BASE_PTR, + * CMP_PDD_POSITIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetPositiveInput(PeripheralBase, PositiveInput) ( \ + ACMP_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C0_ACPSEL_MASK))) | ( \ + (uint8)(PositiveInput))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets positive comparator input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PositiveInput Positive input number. This parameter is of "Positive + * input constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * CMP_PDD_SetPositiveInput(_BASE_PTR, + * CMP_PDD_POSITIVE_INPUT_0); + * @endcode + */ + #define CMP_PDD_SetPositiveInput(PeripheralBase, PositiveInput) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PSEL_MASK))) | ( \ + (uint8)(PositiveInput))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetPositiveInput + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns selected positive input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Positive input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPositiveInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetPositiveInput(PeripheralBase) ( \ + (uint8)(ACMP_C0_REG(PeripheralBase) & ACMP_C0_ACPSEL_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns selected positive input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Positive input constant." type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR, ACMP0_C0, ACMP1_C0 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetPositiveInput(_BASE_PTR); + * @endcode + */ + #define CMP_PDD_GetPositiveInput(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_PSEL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePassThroughMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Used to enable to MUX pass through mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables/Disables pass through mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnablePassThroughMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnablePassThroughMode(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PSTM_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_PSTM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPassThroughModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the pass through mode is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * CMP_PDD_GetPassThroughModeEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetPassThroughModeEnabled(PeripheralBase) ( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & CMP_MUXCR_PSTM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteControl0Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteControl0Reg(PeripheralBase, Value) ( \ + CMP_CR0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR0, CMP1_CR0, + * CMP2_CR0, CMP3_CR0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadControl0Reg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadControl0Reg(PeripheralBase) ( \ + CMP_CR0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadControl1Reg(PeripheralBase) ( \ + CMP_CR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFilterPeriodReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Filter period register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteFilterPeriodReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteFilterPeriodReg(PeripheralBase, Value) ( \ + CMP_FPR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFilterPeriodReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Filter period register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_FPR, CMP1_FPR, + * CMP2_FPR, CMP3_FPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadFilterPeriodReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadFilterPeriodReg(PeripheralBase) ( \ + CMP_FPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR, CMP3_SCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadStatusControlReg(PeripheralBase) ( \ + CMP_SCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DAC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteDacControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteDacControlReg(PeripheralBase, Value) ( \ + CMP_DACCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Dac control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_DACCR, CMP1_DACCR, + * CMP2_DACCR, CMP3_DACCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadDacControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadDacControlReg(PeripheralBase) ( \ + CMP_DACCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMuxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the MUX control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_WriteMuxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMP_PDD_WriteMuxControlReg(PeripheralBase, Value) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMuxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the MUX control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR, CMP3_MUXCR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_ReadMuxControlReg(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_ReadMuxControlReg(PeripheralBase) ( \ + CMP_MUXCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects stop mode edge/level interrupt control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying if edge or level stop mode will be used. + * This parameter is of "Comparator's interrupt stop mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_SCR, CMP1_SCR, + * CMP2_SCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_SetStopMode(_BASE_PTR, + * CMP_PDD_LEVEL_SENSITIVE_MODE); + * @endcode + */ +#define CMP_PDD_SetStopMode(PeripheralBase, Mode) ( \ + CMP_SCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + CMP_SCR_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)CMP_SCR_SMELB_MASK)) & (( \ + (uint8)(~(uint8)CMP_SCR_CFF_MASK)) & ( \ + (uint8)(~(uint8)CMP_SCR_CFR_MASK)))))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableNegativeInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Negative MUX enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if negative input will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableNegativeInput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableNegativeInput(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_MEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_MEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePositiveInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Postive MUX enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if positive input will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_MUXCR, CMP1_MUXCR, + * CMP2_MUXCR (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnablePositiveInput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnablePositiveInput(PeripheralBase, State) ( \ + CMP_MUXCR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_MUXCR_REG(PeripheralBase) & (uint8)(~(uint8)CMP_MUXCR_PEN_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_MUXCR_PEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTriggerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Trigger mode enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if trigger mode for DAC will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableTriggerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMP_PDD_EnableTriggerMode(PeripheralBase, State) ( \ + CMP_CR1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & (uint8)(~(uint8)CMP_CR1_TRIGM_MASK))) | ( \ + (uint8)((uint8)(State) << CMP_CR1_TRIGM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns whether the trigger mode is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMP0_CR1, CMP1_CR1, + * CMP2_CR1, CMP3_CR1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetTriggerModeEnabled(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetTriggerModeEnabled(PeripheralBase) ( \ + (uint8)(CMP_CR1_REG(PeripheralBase) & CMP_CR1_TRIGM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComparatorMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current edge detection mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Comparator modes" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ACMP0_CS, ACMP1_CS + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetComparatorMode(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetComparatorMode(PeripheralBase) ( \ + (uint8)(ACMP_CS_REG(PeripheralBase) & ACMP_CS_ACMOD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExternalInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable specified external inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EnExtInput Mask of enabled external inputs. Use constants from group + * "External input mask". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ACMP0_C2, ACMP1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * CMP_PDD_EnableExternalInput(_BASE_PTR, + * CMP_PDD_EXTERNAL_INPUT_0); + * @endcode + */ +#define CMP_PDD_EnableExternalInput(PeripheralBase, EnExtInput) ( \ + ACMP_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(ACMP_C2_REG(PeripheralBase) & (uint8)(~(uint8)ACMP_C2_ACIPE_MASK))) | ( \ + (uint8)(EnExtInput))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnabledExternalInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the mask of enabled external inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "External input mask" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ACMP0_C2, ACMP1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = CMP_PDD_GetEnabledExternalInput(_BASE_PTR); + * @endcode + */ +#define CMP_PDD_GetEnabledExternalInput(PeripheralBase) ( \ + (uint8)(ACMP_C2_REG(PeripheralBase) & ACMP_C2_ACIPE_MASK) \ + ) +#endif /* #if defined(CMP_PDD_H_) */ + +/* CMP_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h new file mode 100644 index 0000000..01dcec7 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CMT_PDD.h @@ -0,0 +1,1110 @@ +/* + PDD layer implementation for peripheral type CMT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CMT_PDD_H_) +#define CMT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CMT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CMT */ && \ + !defined(MCU_MK10D5) /* CMT */ && \ + !defined(MCU_MK10D7) /* CMT */ && \ + !defined(MCU_MK10F12) /* CMT */ && \ + !defined(MCU_MK10DZ10) /* CMT */ && \ + !defined(MCU_MK11D5) /* CMT */ && \ + !defined(MCU_MK11D5WS) /* CMT */ && \ + !defined(MCU_MK12D5) /* CMT */ && \ + !defined(MCU_MK20D10) /* CMT */ && \ + !defined(MCU_MK20D5) /* CMT */ && \ + !defined(MCU_MK20D7) /* CMT */ && \ + !defined(MCU_MK20F12) /* CMT */ && \ + !defined(MCU_MK20DZ10) /* CMT */ && \ + !defined(MCU_MK21D5) /* CMT */ && \ + !defined(MCU_MK21D5WS) /* CMT */ && \ + !defined(MCU_MK21F12) /* CMT */ && \ + !defined(MCU_MK21F12WS) /* CMT */ && \ + !defined(MCU_MK22D5) /* CMT */ && \ + !defined(MCU_MK22F12) /* CMT */ && \ + !defined(MCU_MK24F12) /* CMT */ && \ + !defined(MCU_MK30D10) /* CMT */ && \ + !defined(MCU_MK30D7) /* CMT */ && \ + !defined(MCU_MK30DZ10) /* CMT */ && \ + !defined(MCU_MK40D10) /* CMT */ && \ + !defined(MCU_MK40D7) /* CMT */ && \ + !defined(MCU_MK40DZ10) /* CMT */ && \ + !defined(MCU_MK40X256VMD100) /* CMT */ && \ + !defined(MCU_MK50D10) /* CMT */ && \ + !defined(MCU_MK50D7) /* CMT */ && \ + !defined(MCU_MK50DZ10) /* CMT */ && \ + !defined(MCU_MK51D10) /* CMT */ && \ + !defined(MCU_MK51D7) /* CMT */ && \ + !defined(MCU_MK51DZ10) /* CMT */ && \ + !defined(MCU_MK52D10) /* CMT */ && \ + !defined(MCU_MK52DZ10) /* CMT */ && \ + !defined(MCU_MK53D10) /* CMT */ && \ + !defined(MCU_MK53DZ10) /* CMT */ && \ + !defined(MCU_MK60D10) /* CMT */ && \ + !defined(MCU_MK60F12) /* CMT */ && \ + !defined(MCU_MK60F15) /* CMT */ && \ + !defined(MCU_MK60DZ10) /* CMT */ && \ + !defined(MCU_MK60N512VMD100) /* CMT */ && \ + !defined(MCU_MK61F12) /* CMT */ && \ + !defined(MCU_MK61F15) /* CMT */ && \ + !defined(MCU_MK61F12WS) /* CMT */ && \ + !defined(MCU_MK61F15WS) /* CMT */ && \ + !defined(MCU_MK63F12) /* CMT */ && \ + !defined(MCU_MK63F12WS) /* CMT */ && \ + !defined(MCU_MK64F12) /* CMT */ && \ + !defined(MCU_MK65F18) /* CMT */ && \ + !defined(MCU_MK65F18WS) /* CMT */ && \ + !defined(MCU_MK66F18) /* CMT */ && \ + !defined(MCU_MK70F12) /* CMT */ && \ + !defined(MCU_MK70F15) /* CMT */ && \ + !defined(MCU_MK70F12WS) /* CMT */ && \ + !defined(MCU_MK70F15WS) /* CMT */ && \ + !defined(MCU_MKW21D5) /* CMT */ && \ + !defined(MCU_MKW21D5WS) /* CMT */ && \ + !defined(MCU_MKW22D5) /* CMT */ && \ + !defined(MCU_MKW22D5WS) /* CMT */ && \ + !defined(MCU_MKW24D5) /* CMT */ && \ + !defined(MCU_MKW24D5WS) /* CMT */ && \ + !defined(MCU_PCK20L4) /* CMT */ + // Unsupported MCU is active + #error CMT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Enable baseband constants */ +#define CMT_PDD_BASEBAND_DISABLED 0U /**< Disabled */ +#define CMT_PDD_BASEBAND_ENABLED CMT_MSC_BASE_MASK /**< Enabled */ + +/* Enable FSK constants */ +#define CMT_PDD_MODE_TIME_BASEBAND 0U /**< Time baseband */ +#define CMT_PDD_MODE_FSK CMT_MSC_FSK_MASK /**< FSK */ + +/* Divider constants */ +#define CMT_PDD_DIVIDER_1 0U /**< 1 */ +#define CMT_PDD_DIVIDER_2 0x1U /**< 2 */ +#define CMT_PDD_DIVIDER_4 0x2U /**< 4 */ +#define CMT_PDD_DIVIDER_8 0x3U /**< 8 */ + +/* Prescaler constants */ +#define CMT_PDD_PRESCALER_1 0U /**< 1 */ +#define CMT_PDD_PRESCALER_2 0x1U /**< 2 */ +#define CMT_PDD_PRESCALER_3 0x2U /**< 3 */ +#define CMT_PDD_PRESCALER_4 0x3U /**< 4 */ +#define CMT_PDD_PRESCALER_5 0x4U /**< 5 */ +#define CMT_PDD_PRESCALER_6 0x5U /**< 6 */ +#define CMT_PDD_PRESCALER_7 0x6U /**< 7 */ +#define CMT_PDD_PRESCALER_8 0x7U /**< 8 */ +#define CMT_PDD_PRESCALER_9 0x8U /**< 9 */ +#define CMT_PDD_PRESCALER_10 0x9U /**< 10 */ +#define CMT_PDD_PRESCALER_11 0xAU /**< 11 */ +#define CMT_PDD_PRESCALER_12 0xBU /**< 12 */ +#define CMT_PDD_PRESCALER_13 0xCU /**< 13 */ +#define CMT_PDD_PRESCALER_14 0xDU /**< 14 */ +#define CMT_PDD_PRESCALER_15 0xEU /**< 15 */ +#define CMT_PDD_PRESCALER_16 0xFU /**< 16 */ + +/* IRO pin constants */ +#define CMT_PDD_PIN_DISABLED 0U /**< Disabled */ +#define CMT_PDD_PIN_ENABLED CMT_OC_IROPEN_MASK /**< Enabled */ + +/* CMT output polarity constants */ +#define CMT_PDD_POLARITY_LOW 0U /**< Low */ +#define CMT_PDD_POLARITY_HIGH CMT_OC_CMTPOL_MASK /**< High */ + +/* IRO latch constants */ +#define CMT_PDD_LATCH_LOW 0U /**< Low */ +#define CMT_PDD_LATCH_HIGH CMT_OC_IROL_MASK /**< High */ + +/* Enable DMA constants */ +#define CMT_PDD_DMA_DISABLED 0U /**< Disabled */ +#define CMT_PDD_DMA_ENABLED CMT_DMA_DMA_MASK /**< Enabled */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_EOCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_EOCF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CMT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_EnableInterrupt(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) |= \ + CMT_MSC_EOCIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CMT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_DisableInterrupt(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) &= \ + (uint8)(~(uint8)CMT_MSC_EOCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CMT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC, CMT_CMD2 + * (depending on the peripheral). + * @par Example: + * @code + * CMT_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ClearInterruptFlag(PeripheralBase) ( \ + (void)CMT_MSC_REG(PeripheralBase), \ + (void)CMT_CMD2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBaseband + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the freerun mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Baseband New value of the baseband. Use constants from group "Enable + * baseband constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableBaseband(_BASE_PTR, + * CMT_PDD_BASEBAND_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableBaseband(PeripheralBase, Baseband) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_BASE_MASK))) | ( \ + (uint8)(Baseband))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFskMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Enable FSK + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_SelectFskMode(_BASE_PTR, + * CMT_PDD_MODE_TIME_BASEBAND); + * @endcode + */ +#define CMT_PDD_SelectFskMode(PeripheralBase, Mode) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_FSK_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExtendedSpace + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures extended space. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Extended Extended space enabled/disabled. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableExtendedSpace(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMT_PDD_EnableExtendedSpace(PeripheralBase, Extended) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_EXSPC_MASK))) | ( \ + (uint8)((uint8)(Extended) << CMT_MSC_EXSPC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CMT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of CMT device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define CMT_PDD_EnableDevice(PeripheralBase, State) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_MCGEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of CMT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & CMT_MSC_MCGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock divide prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the divider. Use constants from group "Divider + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_SetDivider(_BASE_PTR, CMT_PDD_DIVIDER_1); + * @endcode + */ +#define CMT_PDD_SetDivider(PeripheralBase, Divider) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_MSC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_MSC_CMTDIV_MASK))) | ( \ + (uint8)((uint8)(Divider) << CMT_MSC_CMTDIV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets primary prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * CMT_PDD_SetPrescaler(_BASE_PTR, CMT_PDD_PRESCALER_1); + * @endcode + */ +#define CMT_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + CMT_PPS_REG(PeripheralBase) = \ + (uint8)(Prescaler) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIroPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables IRO signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pin New value of the IROpin. Use constants from group "IRO pin + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_EnableIroPin(_BASE_PTR, CMT_PDD_PIN_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableIroPin(PeripheralBase, Pin) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_IROPEN_MASK))) | ( \ + (uint8)(Pin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures CMT output polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity New value of the polarity. Use constants from group "CMT + * output polarity constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_SetPolarity(_BASE_PTR, CMT_PDD_POLARITY_LOW); + * @endcode + */ +#define CMT_PDD_SetPolarity(PeripheralBase, Polarity) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_CMTPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLatch + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures IRO latch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State New value of the latch. Use constants from group "IRO latch + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_SetLatch(_BASE_PTR, CMT_PDD_LATCH_LOW); + * @endcode + */ +#define CMT_PDD_SetLatch(PeripheralBase, State) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_OC_REG(PeripheralBase) & (uint8)(~(uint8)CMT_OC_IROL_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDMA + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the dma mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the DMA. Use constants from group "Enable DMA + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * CMT_PDD_EnableDMA(_BASE_PTR, CMT_PDD_DMA_DISABLED); + * @endcode + */ +#define CMT_PDD_EnableDMA(PeripheralBase, Value) ( \ + CMT_DMA_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(CMT_DMA_REG(PeripheralBase) & (uint8)(~(uint8)CMT_DMA_DMA_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteHighData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGH1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGH1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGH1. + * @par Example: + * @code + * CMT_PDD_WriteHighData1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteHighData1Reg(PeripheralBase, Value) ( \ + CMT_CGH1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGH1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGH1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadHighData1Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadHighData1Reg(PeripheralBase) ( \ + CMT_CGH1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLowData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGL1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGL1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGL1. + * @par Example: + * @code + * CMT_PDD_WriteLowData1Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteLowData1Reg(PeripheralBase, Value) ( \ + CMT_CGL1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLowData1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGL1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGL1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadLowData1Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadLowData1Reg(PeripheralBase) ( \ + CMT_CGL1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteHighData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGH2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGH2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGH2. + * @par Example: + * @code + * CMT_PDD_WriteHighData2Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteHighData2Reg(PeripheralBase, Value) ( \ + CMT_CGH2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGH2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGH2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadHighData2Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadHighData2Reg(PeripheralBase) ( \ + CMT_CGH2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLowData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CGL2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CGL2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CGL2. + * @par Example: + * @code + * CMT_PDD_WriteLowData2Reg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteLowData2Reg(PeripheralBase, Value) ( \ + CMT_CGL2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLowData2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CGL2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CGL2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadLowData2Reg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadLowData2Reg(PeripheralBase) ( \ + CMT_CGL2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOutputControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the OC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the OC register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * CMT_PDD_WriteOutputControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteOutputControlReg(PeripheralBase, Value) ( \ + CMT_OC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOutputControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the OC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_OC. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadOutputControlReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadOutputControlReg(PeripheralBase) ( \ + CMT_OC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the MSC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the MSC register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * CMT_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + CMT_MSC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the MSC register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_MSC. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadStatusControlReg(PeripheralBase) ( \ + CMT_MSC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMarkHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD1. + * @par Example: + * @code + * CMT_PDD_WriteMarkHighReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteMarkHighReg(PeripheralBase, Value) ( \ + CMT_CMD1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMarkHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD1. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadMarkHighReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadMarkHighReg(PeripheralBase) ( \ + CMT_CMD1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMarkLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD2. + * @par Example: + * @code + * CMT_PDD_WriteMarkLowReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteMarkLowReg(PeripheralBase, Value) ( \ + CMT_CMD2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMarkLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD2. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadMarkLowReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadMarkLowReg(PeripheralBase) ( \ + CMT_CMD2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSpaceHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD3 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD3. + * @par Example: + * @code + * CMT_PDD_WriteSpaceHighReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteSpaceHighReg(PeripheralBase, Value) ( \ + CMT_CMD3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSpaceHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD3. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadSpaceHighReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadSpaceHighReg(PeripheralBase) ( \ + CMT_CMD3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSpaceLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the CMD4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the CMD4 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_CMD4. + * @par Example: + * @code + * CMT_PDD_WriteSpaceLowReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteSpaceLowReg(PeripheralBase, Value) ( \ + CMT_CMD4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSpaceLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the CMD4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_CMD4. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadSpaceLowReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadSpaceLowReg(PeripheralBase) ( \ + CMT_CMD4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePrimaryPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the PPS register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the PPS register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * CMT_PDD_WritePrimaryPrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WritePrimaryPrescalerReg(PeripheralBase, Value) ( \ + CMT_PPS_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrimaryPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the PPS register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_PPS. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadPrimaryPrescalerReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadPrimaryPrescalerReg(PeripheralBase) ( \ + CMT_PPS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDMAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DMA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the DMA register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * CMT_PDD_WriteDMAReg(_BASE_PTR, 1); + * @endcode + */ +#define CMT_PDD_WriteDMAReg(PeripheralBase, Value) ( \ + CMT_DMA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDMAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DMA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CMT_DMA. + * @par Example: + * @code + * uint8 result = CMT_PDD_ReadDMAReg(_BASE_PTR); + * @endcode + */ +#define CMT_PDD_ReadDMAReg(PeripheralBase) ( \ + CMT_DMA_REG(PeripheralBase) \ + ) +#endif /* #if defined(CMT_PDD_H_) */ + +/* CMT_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h new file mode 100644 index 0000000..6e165ab --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/CRC_PDD.h @@ -0,0 +1,1134 @@ +/* + PDD layer implementation for peripheral type CRC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(CRC_PDD_H_) +#define CRC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error CRC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* CRC */ && \ + !defined(MCU_MK10D5) /* CRC */ && \ + !defined(MCU_MK10D7) /* CRC */ && \ + !defined(MCU_MK10F12) /* CRC */ && \ + !defined(MCU_MK10DZ10) /* CRC */ && \ + !defined(MCU_MK11D5) /* CRC */ && \ + !defined(MCU_MK11D5WS) /* CRC */ && \ + !defined(MCU_MK12D5) /* CRC */ && \ + !defined(MCU_MK20D10) /* CRC */ && \ + !defined(MCU_MK20D5) /* CRC */ && \ + !defined(MCU_MK20D7) /* CRC */ && \ + !defined(MCU_MK20F12) /* CRC */ && \ + !defined(MCU_MK20DZ10) /* CRC */ && \ + !defined(MCU_MK21D5) /* CRC */ && \ + !defined(MCU_MK21D5WS) /* CRC */ && \ + !defined(MCU_MK21F12) /* CRC */ && \ + !defined(MCU_MK21F12WS) /* CRC */ && \ + !defined(MCU_MK22D5) /* CRC */ && \ + !defined(MCU_MK22F12810) /* CRC */ && \ + !defined(MCU_MK22F12) /* CRC */ && \ + !defined(MCU_MK22F25612) /* CRC */ && \ + !defined(MCU_MK22F51212) /* CRC */ && \ + !defined(MCU_MK24F12) /* CRC */ && \ + !defined(MCU_MK30D10) /* CRC */ && \ + !defined(MCU_MK30D7) /* CRC */ && \ + !defined(MCU_MK30DZ10) /* CRC */ && \ + !defined(MCU_MK40D10) /* CRC */ && \ + !defined(MCU_MK40D7) /* CRC */ && \ + !defined(MCU_MK40DZ10) /* CRC */ && \ + !defined(MCU_MK40X256VMD100) /* CRC */ && \ + !defined(MCU_MK50D10) /* CRC */ && \ + !defined(MCU_MK50D7) /* CRC */ && \ + !defined(MCU_MK50DZ10) /* CRC */ && \ + !defined(MCU_MK51D10) /* CRC */ && \ + !defined(MCU_MK51D7) /* CRC */ && \ + !defined(MCU_MK51DZ10) /* CRC */ && \ + !defined(MCU_MK52D10) /* CRC */ && \ + !defined(MCU_MK52DZ10) /* CRC */ && \ + !defined(MCU_MK53D10) /* CRC */ && \ + !defined(MCU_MK53DZ10) /* CRC */ && \ + !defined(MCU_MK60D10) /* CRC */ && \ + !defined(MCU_MK60F12) /* CRC */ && \ + !defined(MCU_MK60F15) /* CRC */ && \ + !defined(MCU_MK60DZ10) /* CRC */ && \ + !defined(MCU_MK60N512VMD100) /* CRC */ && \ + !defined(MCU_MK61F12) /* CRC */ && \ + !defined(MCU_MK61F15) /* CRC */ && \ + !defined(MCU_MK61F12WS) /* CRC */ && \ + !defined(MCU_MK61F15WS) /* CRC */ && \ + !defined(MCU_MK63F12) /* CRC */ && \ + !defined(MCU_MK63F12WS) /* CRC */ && \ + !defined(MCU_MK64F12) /* CRC */ && \ + !defined(MCU_MK65F18) /* CRC */ && \ + !defined(MCU_MK65F18WS) /* CRC */ && \ + !defined(MCU_MK66F18) /* CRC */ && \ + !defined(MCU_MK70F12) /* CRC */ && \ + !defined(MCU_MK70F15) /* CRC */ && \ + !defined(MCU_MK70F12WS) /* CRC */ && \ + !defined(MCU_MK70F15WS) /* CRC */ && \ + !defined(MCU_MKE02Z2) /* CRC */ && \ + !defined(MCU_MKE02Z4) /* CRC */ && \ + !defined(MCU_SKEAZN642) /* CRC */ && \ + !defined(MCU_MKE04Z1284) /* CRC */ && \ + !defined(MCU_MKE04Z4) /* CRC */ && \ + !defined(MCU_SKEAZN84) /* CRC */ && \ + !defined(MCU_MKE06Z4) /* CRC */ && \ + !defined(MCU_MKV10Z7) /* CRC */ && \ + !defined(MCU_MKV31F12810) /* CRC */ && \ + !defined(MCU_MKV31F25612) /* CRC */ && \ + !defined(MCU_MKV31F51212) /* CRC */ && \ + !defined(MCU_MKW21D5) /* CRC */ && \ + !defined(MCU_MKW21D5WS) /* CRC */ && \ + !defined(MCU_MKW22D5) /* CRC */ && \ + !defined(MCU_MKW22D5WS) /* CRC */ && \ + !defined(MCU_MKW24D5) /* CRC */ && \ + !defined(MCU_MKW24D5WS) /* CRC */ && \ + !defined(MCU_PCK20L4) /* CRC */ && \ + !defined(MCU_SKEAZ1284) /* CRC */ + // Unsupported MCU is active + #error CRC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Computation parameters of CRC standards. */ +#define CRC_PDD_NO_TRANSPOSE 0U /**< No transpose of data. */ +#define CRC_PDD_BITS 0x1U /**< Bits are swapped. */ +#define CRC_PDD_BITS_AND_BYTES 0x2U /**< Bytes and bits are swapped. */ +#define CRC_PDD_BYTES 0x3U /**< Bytes are swapped. */ + + +/* ---------------------------------------------------------------------------- + -- GetCRCDataRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CRC_PDD_GetCRCDataRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataRegister(PeripheralBase) ( \ + CRC_DATA_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = CRC_PDD_GetCRCDataRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataRegister(PeripheralBase) ( \ + CRC_CRC_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCRCDataHRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns upper 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataHRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataHRegister(PeripheralBase) ( \ + CRC_DATAH_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns upper 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataHRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataHRegister(PeripheralBase) ( \ + CRC_CRCH_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetCRCDataLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns lower 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataLRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataLRegister(PeripheralBase) ( \ + CRC_DATAL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns lower 16bits of current CRC result from data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = CRC_PDD_GetCRCDataLRegister(_BASE_PTR); + * @endcode + */ + #define CRC_PDD_GetCRCDataLRegister(PeripheralBase) ( \ + CRC_CRCL_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (4 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataRegister(PeripheralBase, Data) ( \ + CRC_DATA_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (4 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRC, CRC_DATA + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataRegister(PeripheralBase, Data) ( \ + CRC_CRC_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (2 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLRegister(PeripheralBase, Data) ( \ + CRC_DATAL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (2 bytes). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLRegister(PeripheralBase, Data) ( \ + CRC_CRCL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetCRCDataLLRegister + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set CRC data register (1 byte). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCLL, CRC_DATALL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLLRegister(PeripheralBase, Data) ( \ + CRC_DATALL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set CRC data register (1 byte). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data New data for CRC computation. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCLL, CRC_DATALL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetCRCDataLLRegister(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetCRCDataLLRegister(PeripheralBase, Data) ( \ + CRC_CRCLL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetSeedHigh + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set upper 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedHigh(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedHigh(PeripheralBase, Data) ( \ + CRC_DATAH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set upper 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCH, CRC_DATAH + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedHigh(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedHigh(PeripheralBase, Data) ( \ + CRC_CRCH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetSeedLow + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Set lower 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedLow(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedLow(PeripheralBase, Data) ( \ + CRC_DATAL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Set lower 16 bits of data register in seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Seed value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CRCL, CRC_DATAL + * (depending on the peripheral). + * @par Example: + * @code + * CRC_PDD_SetSeedLow(_BASE_PTR, 1); + * @endcode + */ + #define CRC_PDD_SetSeedLow(PeripheralBase, Data) ( \ + CRC_CRCL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPolyHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Set upper 16 bits of polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Polynomial value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLYH. + * @par Example: + * @code + * CRC_PDD_SetPolyHigh(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetPolyHigh(PeripheralBase, Data) ( \ + CRC_GPOLYH_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPolyLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Set lower 16 bits of polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Polynomial value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLYL. + * @par Example: + * @code + * CRC_PDD_SetPolyLow(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetPolyLow(PeripheralBase, Data) ( \ + CRC_GPOLYL_REG(PeripheralBase) = \ + (uint16)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRCControlRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Control register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRCControlRegister(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetCRCControlRegister(PeripheralBase, Data) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSeedBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetSeedBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetSeedBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_WAS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSeedBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_ClearSeedBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ClearSeedBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_WAS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetXorBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable result XORing with 0xFFFF or 0xFFFFFFFF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetXorBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetXorBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_FXOR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearXorBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable result XORing with 0xFFFF or 0xFFFFFFFF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_ClearXorBit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ClearXorBit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC32bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC module for 32bit computation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC32bit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC32bit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) |= \ + CRC_CTRL_TCRC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC16bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Set CRC module for 16bit computation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC16bit(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC16bit(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Set input data transposition type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Input data transposition type. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetInputTranspose(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetInputTranspose(PeripheralBase, Type) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & (uint32)(~(uint32)CRC_CTRL_TOT_MASK))) | ( \ + (uint32)((uint32)(Type) << CRC_CTRL_TOT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOutputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Set output data transposition type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Output data transposition type. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetOutputTranspose(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_SetOutputTranspose(PeripheralBase, Type) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))) | ( \ + (uint32)((uint32)(Type) << CRC_CTRL_TOTR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOutputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Get output transpose settings. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint8 result = CRC_PDD_GetOutputTranspose(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_GetOutputTranspose(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & CRC_CTRL_TOTR_MASK)) >> ( \ + CRC_CTRL_TOTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInputTranspose + ---------------------------------------------------------------------------- */ + +/** + * @brief Get input transpose settings. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint8 result = CRC_PDD_GetInputTranspose(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_GetInputTranspose(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(CRC_CTRL_REG(PeripheralBase) & CRC_CTRL_TOT_MASK)) >> ( \ + CRC_CTRL_TOT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_16 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CRC16 standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_16(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_16(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CRC32 standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_32(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_32(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) | (( \ + CRC_CTRL_TCRC_MASK) | (( \ + CRC_CTRL_WAS_MASK) | ( \ + CRC_CTRL_FXOR_MASK))))) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_CCITT + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for CCITT standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_CCITT(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_CCITT(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | ( \ + CRC_CTRL_WAS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_KERMIT + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for KERMIT standard operation and starts seed + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_KERMIT(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_KERMIT(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_DNP + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for DNP standard operation and starts seed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_DNP(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_DNP(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK)))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + CRC_CTRL_FXOR_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCRC_MODBUS16 + ---------------------------------------------------------------------------- */ + +/** + * @brief Set control register for MODBUS16 standard operation and starts seed + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_SetCRC_MODBUS16(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_SetCRC_MODBUS16(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + CRC_CTRL_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TCRC_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_FXOR_MASK)) & (( \ + (uint32)(~(uint32)CRC_CTRL_TOT_MASK)) & ( \ + (uint32)(~(uint32)CRC_CTRL_TOTR_MASK))))))) | (( \ + CRC_CTRL_WAS_MASK) | (( \ + (uint32)((uint32)0x1U << CRC_CTRL_TOT_SHIFT)) | ( \ + (uint32)((uint32)0x2U << CRC_CTRL_TOTR_SHIFT))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_DATA. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadDataReg(PeripheralBase) ( \ + CRC_DATA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC data + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC data register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_DATA. + * @par Example: + * @code + * CRC_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WriteDataReg(PeripheralBase, Value) ( \ + CRC_DATA_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPolynomialReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC polynomial register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_GPOLY. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadPolynomialReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadPolynomialReg(PeripheralBase) ( \ + CRC_GPOLY_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePolynomialReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC polynomial + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC polynomial register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_GPOLY. + * @par Example: + * @code + * CRC_PDD_WritePolynomialReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WritePolynomialReg(PeripheralBase, Value) ( \ + CRC_GPOLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CRC control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * uint32 result = CRC_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define CRC_PDD_ReadControlReg(PeripheralBase) ( \ + CRC_CTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into CRC control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CRC control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CRC_CTRL. + * @par Example: + * @code + * CRC_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define CRC_PDD_WriteControlReg(PeripheralBase, Value) ( \ + CRC_CTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(CRC_PDD_H_) */ + +/* CRC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h new file mode 100644 index 0000000..ff56063 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DAC_PDD.h @@ -0,0 +1,1353 @@ +/* + PDD layer implementation for peripheral type DAC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DAC_PDD_H_) +#define DAC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DAC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK10D7) /* DAC0 */ && \ + !defined(MCU_MK10F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK10DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK11D5) /* DAC0 */ && \ + !defined(MCU_MK11D5WS) /* DAC0 */ && \ + !defined(MCU_MK12D5) /* DAC0 */ && \ + !defined(MCU_MK20D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK20D7) /* DAC0 */ && \ + !defined(MCU_MK20F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK20DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK21D5) /* DAC0 */ && \ + !defined(MCU_MK21D5WS) /* DAC0 */ && \ + !defined(MCU_MK21F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK21F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK22D5) /* DAC0 */ && \ + !defined(MCU_MK22F12810) /* DAC0 */ && \ + !defined(MCU_MK22F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK22F25612) /* DAC0 */ && \ + !defined(MCU_MK22F51212) /* DAC0, DAC1 */ && \ + !defined(MCU_MK24F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK30D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK30D7) /* DAC0 */ && \ + !defined(MCU_MK30DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40D7) /* DAC0 */ && \ + !defined(MCU_MK40DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK40X256VMD100) /* DAC0, DAC1 */ && \ + !defined(MCU_MK50D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK50D7) /* DAC0 */ && \ + !defined(MCU_MK50DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK51D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK51D7) /* DAC0 */ && \ + !defined(MCU_MK51DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK52D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK52DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK53D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK53DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60D10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60DZ10) /* DAC0, DAC1 */ && \ + !defined(MCU_MK60N512VMD100) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK61F15WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK63F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK63F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK64F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK65F18) /* DAC0, DAC1 */ && \ + !defined(MCU_MK65F18WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK66F18) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F12) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F15) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F12WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MK70F15WS) /* DAC0, DAC1 */ && \ + !defined(MCU_MKL05Z4) /* DAC0 */ && \ + !defined(MCU_MKL15Z4) /* DAC0 */ && \ + !defined(MCU_MKL16Z4) /* DAC0 */ && \ + !defined(MCU_MKL25Z4) /* DAC0 */ && \ + !defined(MCU_MKL26Z4) /* DAC0 */ && \ + !defined(MCU_MKL36Z4) /* DAC0 */ && \ + !defined(MCU_MKL46Z4) /* DAC0 */ && \ + !defined(MCU_MKV10Z7) /* DAC0 */ && \ + !defined(MCU_MKV31F12810) /* DAC0 */ && \ + !defined(MCU_MKV31F25612) /* DAC0 */ && \ + !defined(MCU_MKV31F51212) /* DAC0, DAC1 */ && \ + !defined(MCU_MKW01Z4) /* DAC0 */ && \ + !defined(MCU_MKW21D5) /* DAC0 */ && \ + !defined(MCU_MKW21D5WS) /* DAC0 */ && \ + !defined(MCU_MKW22D5) /* DAC0 */ && \ + !defined(MCU_MKW22D5WS) /* DAC0 */ && \ + !defined(MCU_MKW24D5) /* DAC0 */ && \ + !defined(MCU_MKW24D5WS) /* DAC0 */ + // Unsupported MCU is active + #error DAC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Interrupts' masks. */ + #define DAC_PDD_BUFFER_START_INTERRUPT DAC_C0_DACBTIEN_MASK /**< Buffer start (top position) interrupt mask. */ + #define DAC_PDD_BUFFER_END_INTERRUPT DAC_C0_DACBBIEN_MASK /**< Buffer end (bottom position) interrupt mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' masks. */ + #define DAC_PDD_BUFFER_START_INTERRUPT DAC_C0_DACBTIEN_MASK /**< Buffer start (top position) interrupt mask. */ + #define DAC_PDD_BUFFER_END_INTERRUPT DAC_C0_DACBBIEN_MASK /**< Buffer end (bottom position) interrupt mask. */ + #define DAC_PDD_BUFFER_WATERMARK_INTERRUPT DAC_C0_DACBWIEN_MASK /**< Buffer watermark interrupt mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Interrupts' flags. */ + #define DAC_PDD_BUFFER_START_FLAG DAC_SR_DACBFRPTF_MASK /**< Buffer start (top position) flag. */ + #define DAC_PDD_BUFFER_END_FLAG DAC_SR_DACBFRPBF_MASK /**< Buffer end (bottom position) flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' flags. */ + #define DAC_PDD_BUFFER_START_FLAG DAC_SR_DACBFRPTF_MASK /**< Buffer start (top position) flag. */ + #define DAC_PDD_BUFFER_END_FLAG DAC_SR_DACBFRPBF_MASK /**< Buffer end (bottom position) flag. */ + #define DAC_PDD_BUFFER_WATERMARK_FLAG DAC_SR_DACBFWMF_MASK /**< Buffer watermark flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's trigger source constant. */ +#define DAC_PDD_HW_TRIGGER 0U /**< HW trigger. */ +#define DAC_PDD_SW_TRIGGER DAC_C0_DACTRGSEL_MASK /**< SW trigger. */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* D/A converter's buffer work mode constant. */ + #define DAC_PDD_BUFFER_NORMAL_MODE 0U /**< Normal mode. */ + #define DAC_PDD_BUFFER_OTSCAN_MODE 0x2U /**< One-time mode. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's buffer work mode constant. */ + #define DAC_PDD_BUFFER_NORMAL_MODE 0U /**< Normal mode. */ + #define DAC_PDD_BUFFER_SWING_MODE 0x1U /**< Swing mode. */ + #define DAC_PDD_BUFFER_OTSCAN_MODE 0x2U /**< One-time mode. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* D/A converter's buffer watermark constant. For exact value representation see + peripheral device documentation. */ +#define DAC_PDD_BUFFER_WATERMARK_L1 0U /**< Level 1 watermark (1 word). */ +#define DAC_PDD_BUFFER_WATERMARK_L2 0x1U /**< Level 2 watermark (2 words). */ +#define DAC_PDD_BUFFER_WATERMARK_L3 0x2U /**< Level 3 watermark (3 words). */ +#define DAC_PDD_BUFFER_WATERMARK_L4 0x3U /**< Level 4 watermark (4 words). */ + +/* D/A converter's buffer reference constant. */ +#define DAC_PDD_V_REF_INTERNAL 0U /**< Internal reference source. */ +#define DAC_PDD_V_REF_EXTERNAL DAC_C0_DACRFS_MASK /**< External reference source. */ + +/* D/A converter's buffer low power mode constant. */ +#define DAC_PDD_HIGH_POWER 0U /**< High power mode. */ +#define DAC_PDD_LOW_POWER DAC_C0_LPEN_MASK /**< Low power mode. */ + + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the D/A converter's device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of D/A converter. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableDevice(PeripheralBase, State) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACEN_MASK))) | ( \ + (uint8)((uint8)(State) << DAC_C0_DACEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of D/A converter enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetDeviceEnabled(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetDeviceEnabled(PeripheralBase) ( \ + (uint8)(DAC_C0_REG(PeripheralBase) & DAC_C0_DACEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableInterrupts(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ +#define DAC_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_DisableInterrupts(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ +#define DAC_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetInterruptMask(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ + #define DAC_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_C0_DACBBIEN_MASK | DAC_C0_DACBTIEN_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets all interrupts with value according to mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupts to enable - rest will be disabled. Use + * constants from group "Interrupts' masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetInterruptMask(_BASE_PTR, + * DAC_PDD_BUFFER_START_INTERRUPT); + * @endcode + */ + #define DAC_PDD_SetInterruptMask(PeripheralBase, Mask) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_C0_DACBBIEN_MASK | (DAC_C0_DACBTIEN_MASK | DAC_C0_DACBWIEN_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' masks." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(DAC_C0_DACBBIEN_MASK | DAC_C0_DACBTIEN_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns interrupts mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' masks." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(( \ + DAC_C0_REG(PeripheralBase)) & ( \ + (uint8)(DAC_C0_DACBBIEN_MASK | (DAC_C0_DACBTIEN_MASK | DAC_C0_DACBWIEN_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupts' flags." for processing return + * value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ClearInterruptFlags(_BASE_PTR, + * DAC_PDD_BUFFER_START_FLAG); + * @endcode + */ + #define DAC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))))) | ( \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | DAC_SR_DACBFRPTF_MASK))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ClearInterruptFlags(_BASE_PTR, + * DAC_PDD_BUFFER_START_FLAG); + * @endcode + */ + #define DAC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + DAC_SR_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))))) | ( \ + (uint8)(( \ + (uint8)(~(uint8)(Mask))) & ( \ + (uint8)(DAC_SR_DACBFRPBF_MASK | (DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFWMF_MASK)))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetData + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets value of D/A converter's data buffer word defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data word value. This parameter is a 12-bit value. + * @param RegIndex Buffer word index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[RegIndex], + * DATH[RegIndex] (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetData(_BASE_PTR, 1, periphID); + * @endcode + */ + #define DAC_PDD_SetData(PeripheralBase, Data, RegIndex) ( \ + (DAC_DATL_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(Data)), \ + (DAC_DATH_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(( \ + (uint8)(( \ + DAC_DATH_REG(PeripheralBase,(RegIndex))) & ( \ + (uint8)(~(uint8)DAC_DATH_DATA_MASK)))) | ( \ + (uint8)((uint16)(Data) >> 8U)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets value of D/A converter's data buffer word defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data word value. This parameter is a 12-bit value. + * @param RegIndex Buffer word index. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[RegIndex], + * DATH[RegIndex] (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetData(_BASE_PTR, 1, periphID); + * @endcode + */ + #define DAC_PDD_SetData(PeripheralBase, Data, RegIndex) ( \ + (DAC_DATL_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(Data)), \ + (DAC_DATH_REG(PeripheralBase,(RegIndex)) = \ + (uint8)(( \ + (uint8)(( \ + DAC_DATH_REG(PeripheralBase,(RegIndex))) & ( \ + (uint8)(~(uint8)DAC_DATH_DATA1_MASK)))) | ( \ + (uint8)((uint16)(Data) >> 8U)))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief D/A converter's buffer enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if D/A converter's buffer will be enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableBuffer(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableBuffer(PeripheralBase, State) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBufferEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current data buffer state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferEnabled(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetBufferEnabled(PeripheralBase) ( \ + (uint8)(DAC_C1_REG(PeripheralBase) & DAC_C1_DACBFEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Trigger Parameter specifying which trigger source will be used. This + * parameter is of "D/A converter's trigger source constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetTrigger(_BASE_PTR, DAC_PDD_HW_TRIGGER); + * @endcode + */ +#define DAC_PDD_SetTrigger(PeripheralBase, Trigger) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACTRGSEL_MASK))) | ( \ + (uint8)(Trigger))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current trigger source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetTriggerSource(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_GetTriggerSource(PeripheralBase) ( \ + (uint8)(DAC_C0_REG(PeripheralBase) & DAC_C0_DACTRGSEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceSwTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces D/A converter's software trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_ForceSwTrigger(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ForceSwTrigger(PeripheralBase) ( \ + DAC_C0_REG(PeripheralBase) |= \ + DAC_C0_DACSWTRG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Selects D/A converter's buffer work mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying which data buffer work mode will be used. + * This parameter is of "D/A converter's buffer work mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferMode(_BASE_PTR, + * DAC_PDD_BUFFER_NORMAL_MODE); + * @endcode + */ + #define DAC_PDD_SetBufferMode(PeripheralBase, Mode) ( \ + ((Mode) == DAC_PDD_BUFFER_NORMAL_MODE) ? ( \ + DAC_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)DAC_C1_DACBFMD_MASK)) : ( \ + DAC_C1_REG(PeripheralBase) |= \ + DAC_C1_DACBFMD_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects D/A converter's buffer work mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying which data buffer work mode will be used. + * This parameter is of "D/A converter's buffer work mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferMode(_BASE_PTR, + * DAC_PDD_BUFFER_NORMAL_MODE); + * @endcode + */ + #define DAC_PDD_SetBufferMode(PeripheralBase, Mode) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFMD_MASK))) | ( \ + (uint8)((uint8)(Mode) << DAC_C1_DACBFMD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetBufferWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets D/A converter's buffer watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Parameter specifying data buffer watermark level. This + * parameter is of "D/A converter's buffer watermark constant. For exact value + * representation see peripheral device documentation." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferWatermark(_BASE_PTR, + * DAC_PDD_BUFFER_WATERMARK_L1); + * @endcode + */ +#define DAC_PDD_SetBufferWatermark(PeripheralBase, Watermark) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DACBFWM_MASK))) | ( \ + (uint8)((uint8)(Watermark) << DAC_C1_DACBFWM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferReadPointer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets D/A converter's buffer read pointer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pointer Parameter specifying new data buffer read pointer value. This + * parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferReadPointer(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferReadPointer(PeripheralBase, Pointer) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFRP_MASK))) | ( \ + (uint8)((uint8)(Pointer) << DAC_C2_DACBFRP_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets D/A converter's buffer read pointer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pointer Parameter specifying new data buffer read pointer value. This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferReadPointer(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferReadPointer(PeripheralBase, Pointer) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFRP_MASK))) | ( \ + (uint8)((uint8)(Pointer) << DAC_C2_DACBFRP_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBufferReadPointer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns current data buffer read pointer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferReadPointer(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferReadPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFRP_MASK)) >> ( \ + DAC_C2_DACBFRP_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns current data buffer read pointer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferReadPointer(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferReadPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFRP_MASK)) >> ( \ + DAC_C2_DACBFRP_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetBufferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets D/A converter's buffer upper limit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Buffer upper limit (buffer register maximal index). This + * parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferSize(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferSize(PeripheralBase, Size) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFUP_MASK))) | ( \ + (uint8)(Size))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets D/A converter's buffer upper limit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Buffer upper limit (buffer register maximal index). This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetBufferSize(_BASE_PTR, 1); + * @endcode + */ + #define DAC_PDD_SetBufferSize(PeripheralBase, Size) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C2_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C2_DACBFUP_MASK))) | ( \ + (uint8)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBufferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL05Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns current data buffer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 1-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferSize(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferSize(PeripheralBase) ( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFUP_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns current data buffer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_GetBufferSize(_BASE_PTR); + * @endcode + */ + #define DAC_PDD_GetBufferSize(PeripheralBase) ( \ + (uint8)(DAC_C2_REG(PeripheralBase) & DAC_C2_DACBFUP_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Reference Parameter specifying if internal or external voltage + * reference source will be used. This parameter is of "D/A converter's buffer + * reference constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetReference(_BASE_PTR, DAC_PDD_V_REF_INTERNAL); + * @endcode + */ +#define DAC_PDD_SetReference(PeripheralBase, Reference) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_DACRFS_MASK))) | ( \ + (uint8)(Reference))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPowerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects D/A converter's low power mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Parameter specifying if high or low power mode will be used. This + * parameter is of "D/A converter's buffer low power mode constant." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_SetPowerMode(_BASE_PTR, DAC_PDD_HIGH_POWER); + * @endcode + */ +#define DAC_PDD_SetPowerMode(PeripheralBase, Mode) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C0_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C0_LPEN_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief DMA enable control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA requests will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DAC_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(DAC_C1_REG(PeripheralBase) & (uint8)(~(uint8)DAC_C1_DMAEN_MASK))) | ( \ + (uint8)((uint8)(State) << DAC_C1_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATL[Index]. + * @par Example: + * @code + * DAC_PDD_WriteDataLowReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DAC_PDD_WriteDataLowReg(PeripheralBase, Index, Value) ( \ + DAC_DATL_REG(PeripheralBase,(Index)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DATL[Index]. + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadDataLowReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DAC_PDD_ReadDataLowReg(PeripheralBase, Index) ( \ + DAC_DATL_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATH[Index]. + * @par Example: + * @code + * DAC_PDD_WriteDataHighReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DAC_PDD_WriteDataHighReg(PeripheralBase, Index, Value) ( \ + DAC_DATH_REG(PeripheralBase,(Index)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Register index. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DATH[Index]. + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadDataHighReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DAC_PDD_ReadDataHighReg(PeripheralBase, Index) ( \ + DAC_DATH_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + DAC_SR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_SR, DAC1_SR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadStatusReg(PeripheralBase) ( \ + DAC_SR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl0Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl0Reg(PeripheralBase, Value) ( \ + DAC_C0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C0, DAC1_C0 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl0Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl0Reg(PeripheralBase) ( \ + DAC_C0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + DAC_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C1, DAC1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl1Reg(PeripheralBase) ( \ + DAC_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * DAC_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define DAC_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + DAC_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DAC0_C2, DAC1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DAC_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define DAC_PDD_ReadControl2Reg(PeripheralBase) ( \ + DAC_C2_REG(PeripheralBase) \ + ) +#endif /* #if defined(DAC_PDD_H_) */ + +/* DAC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h new file mode 100644 index 0000000..4c794da --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMAMUX_PDD.h @@ -0,0 +1,402 @@ +/* + PDD layer implementation for peripheral type DMAMUX + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DMAMUX_PDD_H_) +#define DMAMUX_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DMAMUX PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DMAMUX */ && \ + !defined(MCU_MK10D5) /* DMAMUX */ && \ + !defined(MCU_MK10D7) /* DMAMUX */ && \ + !defined(MCU_MK10F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK10DZ10) /* DMAMUX */ && \ + !defined(MCU_MK11D5) /* DMAMUX */ && \ + !defined(MCU_MK11D5WS) /* DMAMUX */ && \ + !defined(MCU_MK12D5) /* DMAMUX */ && \ + !defined(MCU_MK20D10) /* DMAMUX */ && \ + !defined(MCU_MK20D5) /* DMAMUX */ && \ + !defined(MCU_MK20D7) /* DMAMUX */ && \ + !defined(MCU_MK20F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK20DZ10) /* DMAMUX */ && \ + !defined(MCU_MK21D5) /* DMAMUX */ && \ + !defined(MCU_MK21D5WS) /* DMAMUX */ && \ + !defined(MCU_MK21F12) /* DMAMUX */ && \ + !defined(MCU_MK21F12WS) /* DMAMUX */ && \ + !defined(MCU_MK22D5) /* DMAMUX */ && \ + !defined(MCU_MK22F12810) /* DMAMUX */ && \ + !defined(MCU_MK22F12) /* DMAMUX */ && \ + !defined(MCU_MK22F25612) /* DMAMUX */ && \ + !defined(MCU_MK22F51212) /* DMAMUX */ && \ + !defined(MCU_MK24F12) /* DMAMUX */ && \ + !defined(MCU_MK30D10) /* DMAMUX */ && \ + !defined(MCU_MK30D7) /* DMAMUX */ && \ + !defined(MCU_MK30DZ10) /* DMAMUX */ && \ + !defined(MCU_MK40D10) /* DMAMUX */ && \ + !defined(MCU_MK40D7) /* DMAMUX */ && \ + !defined(MCU_MK40DZ10) /* DMAMUX */ && \ + !defined(MCU_MK40X256VMD100) /* DMAMUX */ && \ + !defined(MCU_MK50D10) /* DMAMUX */ && \ + !defined(MCU_MK50D7) /* DMAMUX */ && \ + !defined(MCU_MK50DZ10) /* DMAMUX */ && \ + !defined(MCU_MK51D10) /* DMAMUX */ && \ + !defined(MCU_MK51D7) /* DMAMUX */ && \ + !defined(MCU_MK51DZ10) /* DMAMUX */ && \ + !defined(MCU_MK52D10) /* DMAMUX */ && \ + !defined(MCU_MK52DZ10) /* DMAMUX */ && \ + !defined(MCU_MK53D10) /* DMAMUX */ && \ + !defined(MCU_MK53DZ10) /* DMAMUX */ && \ + !defined(MCU_MK60D10) /* DMAMUX */ && \ + !defined(MCU_MK60F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK60F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK60DZ10) /* DMAMUX */ && \ + !defined(MCU_MK60N512VMD100) /* DMAMUX */ && \ + !defined(MCU_MK61F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F12WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK61F15WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK63F12) /* DMAMUX */ && \ + !defined(MCU_MK63F12WS) /* DMAMUX */ && \ + !defined(MCU_MK64F12) /* DMAMUX */ && \ + !defined(MCU_MK65F18) /* DMAMUX */ && \ + !defined(MCU_MK65F18WS) /* DMAMUX */ && \ + !defined(MCU_MK66F18) /* DMAMUX */ && \ + !defined(MCU_MK70F12) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F15) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F12WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MK70F15WS) /* DMAMUX0, DMAMUX1 */ && \ + !defined(MCU_MKL04Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL05Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL14Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL15Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL16Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL24Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL25Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL26Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL34Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL36Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKL46Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKV10Z7) /* DMAMUX */ && \ + !defined(MCU_MKV31F12810) /* DMAMUX */ && \ + !defined(MCU_MKV31F25612) /* DMAMUX */ && \ + !defined(MCU_MKV31F51212) /* DMAMUX */ && \ + !defined(MCU_MKW01Z4) /* DMAMUX0 */ && \ + !defined(MCU_MKW21D5) /* DMAMUX */ && \ + !defined(MCU_MKW21D5WS) /* DMAMUX */ && \ + !defined(MCU_MKW22D5) /* DMAMUX */ && \ + !defined(MCU_MKW22D5WS) /* DMAMUX */ && \ + !defined(MCU_MKW24D5) /* DMAMUX */ && \ + !defined(MCU_MKW24D5WS) /* DMAMUX */ && \ + !defined(MCU_PCK20L4) /* DMAMUX */ + // Unsupported MCU is active + #error DMAMUX PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Channel request source constants. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_0 0U /**< Channel request source 0. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_1 0x1U /**< Channel request source 1. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_2 0x2U /**< Channel request source 2. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_3 0x3U /**< Channel request source 3. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_4 0x4U /**< Channel request source 4. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_5 0x5U /**< Channel request source 5. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_6 0x6U /**< Channel request source 6. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_7 0x7U /**< Channel request source 7. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_8 0x8U /**< Channel request source 8. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_9 0x9U /**< Channel request source 9. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_10 0xAU /**< Channel request source 10. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_11 0xBU /**< Channel request source 11. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_12 0xCU /**< Channel request source 12. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_13 0xDU /**< Channel request source 13. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_14 0xEU /**< Channel request source 14. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_15 0xFU /**< Channel request source 15. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_16 0x10U /**< Channel request source 16. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_17 0x11U /**< Channel request source 17. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_18 0x12U /**< Channel request source 18. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_19 0x13U /**< Channel request source 19. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_20 0x14U /**< Channel request source 20. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_21 0x15U /**< Channel request source 21. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_22 0x16U /**< Channel request source 22. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_23 0x17U /**< Channel request source 23. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_24 0x18U /**< Channel request source 24. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_25 0x19U /**< Channel request source 25. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_26 0x1AU /**< Channel request source 26. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_27 0x1BU /**< Channel request source 27. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_28 0x1CU /**< Channel request source 28. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_29 0x1DU /**< Channel request source 29. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_30 0x1EU /**< Channel request source 30. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_31 0x1FU /**< Channel request source 31. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_32 0x20U /**< Channel request source 32. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_33 0x21U /**< Channel request source 33. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_34 0x22U /**< Channel request source 34. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_35 0x23U /**< Channel request source 35. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_36 0x24U /**< Channel request source 36. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_37 0x25U /**< Channel request source 37. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_38 0x26U /**< Channel request source 38. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_39 0x27U /**< Channel request source 39. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_40 0x28U /**< Channel request source 40. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_41 0x29U /**< Channel request source 41. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_42 0x2AU /**< Channel request source 42. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_43 0x2BU /**< Channel request source 43. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_44 0x2CU /**< Channel request source 44. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_45 0x2DU /**< Channel request source 45. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_46 0x2EU /**< Channel request source 46. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_47 0x2FU /**< Channel request source 47. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_48 0x30U /**< Channel request source 48. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_49 0x31U /**< Channel request source 49. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_50 0x32U /**< Channel request source 50. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_51 0x33U /**< Channel request source 51. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_52 0x34U /**< Channel request source 52. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_53 0x35U /**< Channel request source 53. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_54 0x36U /**< Channel request source 54. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_55 0x37U /**< Channel request source 55. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_56 0x38U /**< Channel request source 56. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_57 0x39U /**< Channel request source 57. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_58 0x3AU /**< Channel request source 58. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_59 0x3BU /**< Channel request source 59. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_60 0x3CU /**< Channel request source 60. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_61 0x3DU /**< Channel request source 61. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_62 0x3EU /**< Channel request source 62. */ +#define DMAMUX_PDD_CHANNEL_SOURCE_63 0x3FU /**< Channel request source 63. */ + +/* Channel enabled bit mask */ +#define DMAMUX_PDD_CHANNEL_ENABLED DMAMUX_CHCFG_ENBL_MASK /**< Channel enabled bit mask */ + +/* Trigger enabled bit mask */ +#define DMAMUX_PDD_TRIGGER_ENABLED DMAMUX_CHCFG_TRIG_MASK /**< Trigger enabled bit mask */ + + +/* ---------------------------------------------------------------------------- + -- WriteChannelConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA MUX channel configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA MUX channel configuration register value. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_WriteChannelConfigurationReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMAMUX_PDD_WriteChannelConfigurationReg(PeripheralBase, Channel, Value) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = + * DMAMUX_PDD_ReadChannelConfigurationReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMAMUX_PDD_ReadChannelConfigurationReg(PeripheralBase, Channel) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA MUX channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA MUX channel will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_EnableChannel(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define DMAMUX_PDD_EnableChannel(PeripheralBase, Channel, State) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_ENBL_MASK)))) | ( \ + (uint8)((uint8)(State) << DMAMUX_CHCFG_ENBL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetChannelEnabled(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetChannelEnabled(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_ENBL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA MUX channel triggering. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA MUX channel triggering will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_EnableTrigger(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define DMAMUX_PDD_EnableTrigger(PeripheralBase, Channel, State) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_TRIG_MASK)))) | ( \ + (uint8)((uint8)(State) << DMAMUX_CHCFG_TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTriggerEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA MUX channel triggering state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetTriggerEnabled(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetTriggerEnabled(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_TRIG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelSource DMA channel source number. This parameter is a 6-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * DMAMUX_PDD_SetChannelSource(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMAMUX_PDD_SetChannelSource(PeripheralBase, Channel, ChannelSource) ( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) = \ + (uint8)(( \ + (uint8)(( \ + DMAMUX_CHCFG_REG(PeripheralBase,(Channel))) & ( \ + (uint8)(~(uint8)DMAMUX_CHCFG_SOURCE_MASK)))) | ( \ + (uint8)(ChannelSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of enabled DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CHCFG[Channel]. + * @par Example: + * @code + * uint8 result = DMAMUX_PDD_GetChannelSource(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMAMUX_PDD_GetChannelSource(PeripheralBase, Channel) ( \ + (uint8)(DMAMUX_CHCFG_REG(PeripheralBase,(Channel)) & DMAMUX_CHCFG_SOURCE_MASK) \ + ) +#endif /* #if defined(DMAMUX_PDD_H_) */ + +/* DMAMUX_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h new file mode 100644 index 0000000..912199b --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/DMA_PDD.h @@ -0,0 +1,7966 @@ +/* + PDD layer implementation for peripheral type DMA + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(DMA_PDD_H_) +#define DMA_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error DMA PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* DMA */ && \ + !defined(MCU_MK10D5) /* DMA */ && \ + !defined(MCU_MK10D7) /* DMA */ && \ + !defined(MCU_MK10F12) /* DMA */ && \ + !defined(MCU_MK10DZ10) /* DMA */ && \ + !defined(MCU_MK11D5) /* DMA */ && \ + !defined(MCU_MK11D5WS) /* DMA */ && \ + !defined(MCU_MK12D5) /* DMA */ && \ + !defined(MCU_MK20D10) /* DMA */ && \ + !defined(MCU_MK20D5) /* DMA */ && \ + !defined(MCU_MK20D7) /* DMA */ && \ + !defined(MCU_MK20F12) /* DMA */ && \ + !defined(MCU_MK20DZ10) /* DMA */ && \ + !defined(MCU_MK21D5) /* DMA */ && \ + !defined(MCU_MK21D5WS) /* DMA */ && \ + !defined(MCU_MK21F12) /* DMA */ && \ + !defined(MCU_MK21F12WS) /* DMA */ && \ + !defined(MCU_MK22D5) /* DMA */ && \ + !defined(MCU_MK22F12810) /* DMA */ && \ + !defined(MCU_MK22F12) /* DMA */ && \ + !defined(MCU_MK22F25612) /* DMA */ && \ + !defined(MCU_MK22F51212) /* DMA */ && \ + !defined(MCU_MK24F12) /* DMA */ && \ + !defined(MCU_MK30D10) /* DMA */ && \ + !defined(MCU_MK30D7) /* DMA */ && \ + !defined(MCU_MK30DZ10) /* DMA */ && \ + !defined(MCU_MK40D10) /* DMA */ && \ + !defined(MCU_MK40D7) /* DMA */ && \ + !defined(MCU_MK40DZ10) /* DMA */ && \ + !defined(MCU_MK40X256VMD100) /* DMA */ && \ + !defined(MCU_MK50D10) /* DMA */ && \ + !defined(MCU_MK50D7) /* DMA */ && \ + !defined(MCU_MK50DZ10) /* DMA */ && \ + !defined(MCU_MK51D10) /* DMA */ && \ + !defined(MCU_MK51D7) /* DMA */ && \ + !defined(MCU_MK51DZ10) /* DMA */ && \ + !defined(MCU_MK52D10) /* DMA */ && \ + !defined(MCU_MK52DZ10) /* DMA */ && \ + !defined(MCU_MK53D10) /* DMA */ && \ + !defined(MCU_MK53DZ10) /* DMA */ && \ + !defined(MCU_MK60D10) /* DMA */ && \ + !defined(MCU_MK60F12) /* DMA */ && \ + !defined(MCU_MK60F15) /* DMA */ && \ + !defined(MCU_MK60DZ10) /* DMA */ && \ + !defined(MCU_MK60N512VMD100) /* DMA */ && \ + !defined(MCU_MK61F12) /* DMA */ && \ + !defined(MCU_MK61F15) /* DMA */ && \ + !defined(MCU_MK61F12WS) /* DMA */ && \ + !defined(MCU_MK61F15WS) /* DMA */ && \ + !defined(MCU_MK63F12) /* DMA */ && \ + !defined(MCU_MK63F12WS) /* DMA */ && \ + !defined(MCU_MK64F12) /* DMA */ && \ + !defined(MCU_MK65F18) /* DMA */ && \ + !defined(MCU_MK65F18WS) /* DMA */ && \ + !defined(MCU_MK66F18) /* DMA */ && \ + !defined(MCU_MK70F12) /* DMA */ && \ + !defined(MCU_MK70F15) /* DMA */ && \ + !defined(MCU_MK70F12WS) /* DMA */ && \ + !defined(MCU_MK70F15WS) /* DMA */ && \ + !defined(MCU_MKL04Z4) /* DMA */ && \ + !defined(MCU_MKL05Z4) /* DMA */ && \ + !defined(MCU_MKL14Z4) /* DMA */ && \ + !defined(MCU_MKL15Z4) /* DMA */ && \ + !defined(MCU_MKL16Z4) /* DMA */ && \ + !defined(MCU_MKL24Z4) /* DMA */ && \ + !defined(MCU_MKL25Z4) /* DMA */ && \ + !defined(MCU_MKL26Z4) /* DMA */ && \ + !defined(MCU_MKL34Z4) /* DMA */ && \ + !defined(MCU_MKL36Z4) /* DMA */ && \ + !defined(MCU_MKL46Z4) /* DMA */ && \ + !defined(MCU_MKV10Z7) /* DMA */ && \ + !defined(MCU_MKV31F12810) /* DMA */ && \ + !defined(MCU_MKV31F25612) /* DMA */ && \ + !defined(MCU_MKV31F51212) /* DMA */ && \ + !defined(MCU_MKW01Z4) /* DMA */ && \ + !defined(MCU_MKW21D5) /* DMA */ && \ + !defined(MCU_MKW21D5WS) /* DMA */ && \ + !defined(MCU_MKW22D5) /* DMA */ && \ + !defined(MCU_MKW22D5WS) /* DMA */ && \ + !defined(MCU_MKW24D5) /* DMA */ && \ + !defined(MCU_MKW24D5WS) /* DMA */ && \ + !defined(MCU_PCK20L4) /* DMA */ + // Unsupported MCU is active + #error DMA PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* DMA channel constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_4 0x4U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_5 0x5U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_6 0x6U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_7 0x7U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_8 0x8U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_9 0x9U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_10 0xAU /**< Channel 10. */ + #define DMA_PDD_CHANNEL_11 0xBU /**< Channel 11. */ + #define DMA_PDD_CHANNEL_12 0xCU /**< Channel 12. */ + #define DMA_PDD_CHANNEL_13 0xDU /**< Channel 13. */ + #define DMA_PDD_CHANNEL_14 0xEU /**< Channel 14. */ + #define DMA_PDD_CHANNEL_15 0xFU /**< Channel 15. */ + #define DMA_PDD_CHANNEL_16 0x10U /**< Channel 16. */ + #define DMA_PDD_CHANNEL_17 0x11U /**< Channel 17. */ + #define DMA_PDD_CHANNEL_18 0x12U /**< Channel 18. */ + #define DMA_PDD_CHANNEL_19 0x13U /**< Channel 19. */ + #define DMA_PDD_CHANNEL_20 0x14U /**< Channel 20. */ + #define DMA_PDD_CHANNEL_21 0x15U /**< Channel 21. */ + #define DMA_PDD_CHANNEL_22 0x16U /**< Channel 22. */ + #define DMA_PDD_CHANNEL_23 0x17U /**< Channel 23. */ + #define DMA_PDD_CHANNEL_24 0x18U /**< Channel 24. */ + #define DMA_PDD_CHANNEL_25 0x19U /**< Channel 25. */ + #define DMA_PDD_CHANNEL_26 0x1AU /**< Channel 26. */ + #define DMA_PDD_CHANNEL_27 0x1BU /**< Channel 27. */ + #define DMA_PDD_CHANNEL_28 0x1CU /**< Channel 28. */ + #define DMA_PDD_CHANNEL_29 0x1DU /**< Channel 29. */ + #define DMA_PDD_CHANNEL_30 0x1EU /**< Channel 30. */ + #define DMA_PDD_CHANNEL_31 0x1FU /**< Channel 31. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA channel number constants */ + #define DMA_PDD_CHANNEL_0 0U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_1 0x1U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_2 0x2U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_3 0x3U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_4 0x4U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_5 0x5U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_6 0x6U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_7 0x7U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_8 0x8U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_9 0x9U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_10 0xAU /**< Channel 10. */ + #define DMA_PDD_CHANNEL_11 0xBU /**< Channel 11. */ + #define DMA_PDD_CHANNEL_12 0xCU /**< Channel 12. */ + #define DMA_PDD_CHANNEL_13 0xDU /**< Channel 13. */ + #define DMA_PDD_CHANNEL_14 0xEU /**< Channel 14. */ + #define DMA_PDD_CHANNEL_15 0xFU /**< Channel 15. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_MASK_4 0x10U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_MASK_5 0x20U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_MASK_6 0x40U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_MASK_7 0x80U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_MASK_8 0x100U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_MASK_9 0x200U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_MASK_10 0x400U /**< Channel 10. */ + #define DMA_PDD_CHANNEL_MASK_11 0x800U /**< Channel 11. */ + #define DMA_PDD_CHANNEL_MASK_12 0x1000U /**< Channel 12. */ + #define DMA_PDD_CHANNEL_MASK_13 0x2000U /**< Channel 13. */ + #define DMA_PDD_CHANNEL_MASK_14 0x4000U /**< Channel 14. */ + #define DMA_PDD_CHANNEL_MASK_15 0x8000U /**< Channel 15. */ + #define DMA_PDD_CHANNEL_MASK_16 0x10000U /**< Channel 16. */ + #define DMA_PDD_CHANNEL_MASK_17 0x20000U /**< Channel 17. */ + #define DMA_PDD_CHANNEL_MASK_18 0x40000U /**< Channel 18. */ + #define DMA_PDD_CHANNEL_MASK_19 0x80000U /**< Channel 19. */ + #define DMA_PDD_CHANNEL_MASK_20 0x100000U /**< Channel 20. */ + #define DMA_PDD_CHANNEL_MASK_21 0x200000U /**< Channel 21. */ + #define DMA_PDD_CHANNEL_MASK_22 0x400000U /**< Channel 22. */ + #define DMA_PDD_CHANNEL_MASK_23 0x800000U /**< Channel 23. */ + #define DMA_PDD_CHANNEL_MASK_24 0x1000000U /**< Channel 24. */ + #define DMA_PDD_CHANNEL_MASK_25 0x2000000U /**< Channel 25. */ + #define DMA_PDD_CHANNEL_MASK_26 0x4000000U /**< Channel 26. */ + #define DMA_PDD_CHANNEL_MASK_27 0x8000000U /**< Channel 27. */ + #define DMA_PDD_CHANNEL_MASK_28 0x10000000U /**< Channel 28. */ + #define DMA_PDD_CHANNEL_MASK_29 0x20000000U /**< Channel 29. */ + #define DMA_PDD_CHANNEL_MASK_30 0x40000000U /**< Channel 30. */ + #define DMA_PDD_CHANNEL_MASK_31 0x80000000U /**< Channel 31. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA channel mask constants */ + #define DMA_PDD_CHANNEL_MASK_0 0x1U /**< Channel 0. */ + #define DMA_PDD_CHANNEL_MASK_1 0x2U /**< Channel 1. */ + #define DMA_PDD_CHANNEL_MASK_2 0x4U /**< Channel 2. */ + #define DMA_PDD_CHANNEL_MASK_3 0x8U /**< Channel 3. */ + #define DMA_PDD_CHANNEL_MASK_4 0x10U /**< Channel 4. */ + #define DMA_PDD_CHANNEL_MASK_5 0x20U /**< Channel 5. */ + #define DMA_PDD_CHANNEL_MASK_6 0x40U /**< Channel 6. */ + #define DMA_PDD_CHANNEL_MASK_7 0x80U /**< Channel 7. */ + #define DMA_PDD_CHANNEL_MASK_8 0x100U /**< Channel 8. */ + #define DMA_PDD_CHANNEL_MASK_9 0x200U /**< Channel 9. */ + #define DMA_PDD_CHANNEL_MASK_10 0x400U /**< Channel 10. */ + #define DMA_PDD_CHANNEL_MASK_11 0x800U /**< Channel 11. */ + #define DMA_PDD_CHANNEL_MASK_12 0x1000U /**< Channel 12. */ + #define DMA_PDD_CHANNEL_MASK_13 0x2000U /**< Channel 13. */ + #define DMA_PDD_CHANNEL_MASK_14 0x4000U /**< Channel 14. */ + #define DMA_PDD_CHANNEL_MASK_15 0x8000U /**< Channel 15. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel major loop linking disabled bit mask */ +#define DMA_PDD_MAJOR_LINK_DISABLED 0U /**< Channel major loop linking disabled */ + +/* Channel major loop linking enabled bit mask */ +#define DMA_PDD_MAJOR_LINK_ENABLED DMA_CSR_MAJORELINK_MASK /**< Channel major loop linking enabled */ + +/* Channel scatter/gather disabled bit mask */ +#define DMA_PDD_SCATTER_GATHER_DISABLED 0U /**< Channel scatter/gather disabled */ + +/* Channel scatter/gather enabled bit mask */ +#define DMA_PDD_SCATTER_GATHER_ENABLED DMA_CSR_ESG_MASK /**< Channel scatter/gather enabled */ + +/* Enable channel after request bit mask */ +#define DMA_PDD_ENABLE_AFTER_REQUEST 0U /**< Enable channel after request */ + +/* Disable channel after request bit mask */ +#define DMA_PDD_DISABLE_AFTER_REQUEST DMA_CSR_DREQ_MASK /**< Disable channel after request */ + +/* Minor loop offset bit position value */ +#define DMA_PDD_MINOR_LOOP_OFFSET_SHIFT 0U /**< Minor loop offset bit position value. */ + +/* Minor loop enable bit position value */ +#define DMA_PDD_MINOR_LOOP_ENABLE_SHIFT 0x1EU /**< Minor loop enable bit position value. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Channel error status constants */ + #define DMA_PDD_CONFIGURATION_ERROR_FLAG DMA_DSR_BCR_CE_MASK /**< Configuration error flag. */ + #define DMA_PDD_ERROR_ON_SOURCE_FLAG DMA_DSR_BCR_BES_MASK /**< Error on source side flag. */ + #define DMA_PDD_ERROR_ON_DESTINATION_FLAG DMA_DSR_BCR_BED_MASK /**< Error on destination side flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel-related error flags. Bit mask of flags associated with specific + channel (use GetErrorStatusChannel to obtain associated channel number). */ + #define DMA_PDD_CHANNEL_ERROR_FLAGS 0x100FFU /**< All channel-related error flags mask. */ + #define DMA_PDD_ERROR_TRANSFER_CANCELED_FLAG DMA_ES_ECX_MASK /**< Canceled transfer by the error cancel transfer input. */ + #define DMA_PDD_ERROR_SOURCE_ADDRESS_FLAG DMA_ES_SAE_MASK /**< Source address error. */ + #define DMA_PDD_ERROR_SOURCE_OFFSET_FLAG DMA_ES_SOE_MASK /**< Source offset error. */ + #define DMA_PDD_ERROR_DESTINATION_ADDRESS_FLAG DMA_ES_DAE_MASK /**< Destination address error. */ + #define DMA_PDD_ERROR_DESTINATION_OFFSET_FLAG DMA_ES_DOE_MASK /**< Source offset error. */ + #define DMA_PDD_ERROR_COUNT_FLAG DMA_ES_NCE_MASK /**< Error detected in minor loop byte count or major loop iteration count. */ + #define DMA_PDD_ERROR_SCATTER_GATHER_FLAG DMA_ES_SGE_MASK /**< Scatter/gather configuration error. */ + #define DMA_PDD_ERROR_ON_SOURCE_FLAG DMA_ES_SBE_MASK /**< Error on source side flag. */ + #define DMA_PDD_ERROR_ON_DESTINATION_FLAG DMA_ES_DBE_MASK /**< Error on destination side flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* Device-related error flags. Bit mask of flags associated with whole DMA + device or multiple channels. */ + #define DMA_PDD_DEVICE_ERROR_FLAGS 0xC000U /**< All device-related error flags mask. */ + #define DMA_PDD_ERROR_CHANNEL_PRIORITY_FLAG DMA_ES_CPE_MASK /**< Configuration error in the channel priorities (channel priorities are not unique). */ + #define DMA_PDD_ERROR_GROUP_PRIORITY_FLAG DMA_ES_GPE_MASK /**< Configuration error in the group priorities (group priorities are not unique). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Device-related error flags. Bit mask of flags associated with whole DMA + device or multiple channels. */ + #define DMA_PDD_DEVICE_ERROR_FLAGS 0x4000U /**< All device-related error flags mask. */ + #define DMA_PDD_ERROR_CHANNEL_PRIORITY_FLAG DMA_ES_CPE_MASK /**< Configuration error in the channel priorities (channel priorities are not unique). */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Constants used in SetChannelPriority */ +#define DMA_PDD_DCHPRI_DPA_MASK DMA_DCHPRI3_DPA_MASK /**< Disable preempt ability bit mask. */ +#define DMA_PDD_DCHPRI_CHPRI_MASK DMA_DCHPRI3_CHPRI_MASK /**< Channel arbitration priority bit group mask. */ +#define DMA_PDD_DCHPRI_ECP_SHIFT 0x7U /**< Enable channel preemption bit position. */ +#define DMA_PDD_DCHPRI_CHPRI_SHIFT 0U /**< Channel arbitration priority bit group position. */ + +/* Constant specifying if DMA channel can be temporarily suspended by the + service request of a higher priority channel */ +#define DMA_PDD_CHANNEL_CAN_BE_PREEMPTED 0U /**< Channel can be preempted. */ +#define DMA_PDD_CHANNEL_CANNOT_BE_PREEMPTED DMA_DCHPRI3_ECP_MASK /**< Channel can't be preempted. */ + +/* Constant specifying if DMA channel can suspend a lower priority channel */ +#define DMA_PDD_CHANNEL_CAN_PREEMPT_OTHER 0U /**< Channel can suspend other channels. */ +#define DMA_PDD_CHANNEL_CANNOT_PREEMPT_OTHER DMA_DCHPRI3_DPA_MASK /**< Channel can't suspend other channels. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Circular buffer size constants */ + #define DMA_PDD_CIRCULAR_BUFFER_DISABLED 0U /**< Circular buffer disabled. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_BYTES 0x1U /**< 16 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_BYTES 0x2U /**< 32 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_BYTES 0x3U /**< 64 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_BYTES 0x4U /**< 128 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_BYTES 0x5U /**< 256 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_BYTES 0x6U /**< 512 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_KBYTE 0x7U /**< 1 Kbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_KBYTES 0x8U /**< 2 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_KBYTES 0x9U /**< 4 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_KBYTES 0xAU /**< 8 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_KBYTES 0xBU /**< 16 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_KBYTES 0xCU /**< 32 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_KBYTES 0xDU /**< 64 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_KBYTES 0xEU /**< 128 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_KBYTES 0xFU /**< 256 Kbytes circular buffer. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Circular buffer size constants */ + #define DMA_PDD_CIRCULAR_BUFFER_DISABLED 0U /**< Circular buffer disabled. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_BYTES 0x1U /**< 2 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_BYTES 0x2U /**< 4 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_BYTES 0x3U /**< 8 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_BYTES 0x4U /**< 16 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_BYTES 0x5U /**< 32 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_BYTES 0x6U /**< 64 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_BYTES 0x7U /**< 128 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_BYTES 0x8U /**< 256 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_BYTES 0x9U /**< 512 bytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_KBYTE 0xAU /**< 1 Kbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_KBYTES 0xBU /**< 2 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_KBYTES 0xCU /**< 4 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_KBYTES 0xDU /**< 8 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_KBYTES 0xEU /**< 16 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_KBYTES 0xFU /**< 32 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_KBYTES 0x10U /**< 64 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_KBYTES 0x11U /**< 128 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_KBYTES 0x12U /**< 256 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_KBYTES 0x13U /**< 512 Kbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_MBYTE 0x14U /**< 1 Mbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_MBYTES 0x15U /**< 2 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_4_MBYTES 0x16U /**< 4 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_8_MBYTES 0x17U /**< 8 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_16_MBYTES 0x18U /**< 16 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_32_MBYTES 0x19U /**< 32 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_64_MBYTES 0x1AU /**< 64 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_128_MBYTES 0x1BU /**< 128 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_256_MBYTES 0x1CU /**< 256 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_512_MBYTES 0x1DU /**< 512 Mbytes circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_1_GBYTE 0x1EU /**< 1 Gbyte circular buffer. */ + #define DMA_PDD_CIRCULAR_BUFFER_2_GBYTES 0x1FU /**< 2 Gbytes circular buffer. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Channel activity status constants */ + #define DMA_PDD_TRANSFER_DONE_FLAG DMA_DSR_BCR_DONE_MASK /**< Transfer done flag. */ + #define DMA_PDD_TRANSFER_BUSY_FLAG DMA_DSR_BCR_BSY_MASK /**< Transfer in progress flag. */ + #define DMA_PDD_TRANSFER_REQUEST_PENDING_FLAG DMA_DSR_BCR_REQ_MASK /**< Transfer request pending flag. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Channel activity status constants */ + #define DMA_PDD_TRANSFER_DONE_FLAG DMA_CSR_DONE_MASK /**< Transfer done flag. */ + #define DMA_PDD_TRANSFER_ACTIVE_FLAG DMA_CSR_ACTIVE_MASK /**< Transfer in progress flag. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* Transfer complete interrupt enable/disable constants */ + #define DMA_PDD_TRANSFER_COMPLETE_ENABLE DMA_DCR_EINT_MASK /**< Transfer complete interrupt enabled. */ + #define DMA_PDD_TRANSFER_COMPLETE_DISABLE 0U /**< Transfer complete interrupt disabled. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Transfer complete interrupt enable/disable constants */ + #define DMA_PDD_TRANSFER_COMPLETE_ENABLE DMA_CSR_INTMAJOR_MASK /**< Transfer complete interrupt enabled. */ + #define DMA_PDD_TRANSFER_COMPLETE_DISABLE 0U /**< Transfer complete interrupt disabled. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Interrupts' mask */ +#define DMA_PDD_TRANSFER_COMPLETE_INTERRUPT DMA_DCR_EINT_MASK /**< Transfer complete interrupt mask. */ + +/* Interrupts' flags */ +#define DMA_PDD_TRANSFER_COMPLETE_FLAG DMA_DSR_BCR_DONE_MASK /**< Transfer complete flag. */ + +/* Channel request source constants */ +#define DMA_PDD_CHANNEL_SOURCE_0 0U /**< Channel request source 0. */ +#define DMA_PDD_CHANNEL_SOURCE_1 0x1U /**< Channel request source 1. */ +#define DMA_PDD_CHANNEL_SOURCE_2 0x2U /**< Channel request source 2. */ +#define DMA_PDD_CHANNEL_SOURCE_3 0x3U /**< Channel request source 3. */ +#define DMA_PDD_CHANNEL_SOURCE_4 0x4U /**< Channel request source 4. */ +#define DMA_PDD_CHANNEL_SOURCE_5 0x5U /**< Channel request source 5. */ +#define DMA_PDD_CHANNEL_SOURCE_6 0x6U /**< Channel request source 6. */ +#define DMA_PDD_CHANNEL_SOURCE_7 0x7U /**< Channel request source 7. */ +#define DMA_PDD_CHANNEL_SOURCE_8 0x8U /**< Channel request source 8. */ +#define DMA_PDD_CHANNEL_SOURCE_9 0x9U /**< Channel request source 9. */ +#define DMA_PDD_CHANNEL_SOURCE_10 0xAU /**< Channel request source 10. */ +#define DMA_PDD_CHANNEL_SOURCE_11 0xBU /**< Channel request source 11. */ +#define DMA_PDD_CHANNEL_SOURCE_12 0xCU /**< Channel request source 12. */ +#define DMA_PDD_CHANNEL_SOURCE_13 0xDU /**< Channel request source 13. */ +#define DMA_PDD_CHANNEL_SOURCE_14 0xEU /**< Channel request source 14. */ +#define DMA_PDD_CHANNEL_SOURCE_15 0xFU /**< Channel request source 15. */ + +/* Set all or only one DMA channel. Used in Set/Clear macros to distinct between + setting/clearing attribute of one specified channel or of all channels. */ +#define DMA_PDD_ONE_CHANNEL 0U /**< Set only one DMA channel. */ +#define DMA_PDD_ALL_CHANNELS DMA_SERQ_SAER_MASK /**< Set all DMA channels. */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0x1U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x2U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0U /**< 32-bit transfer size. */ + +#elif ((defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x1U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0x2U /**< 32-bit transfer size. */ + #define DMA_PDD_16_BYTE 0x4U /**< 16-byte transfer size. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA data transfer block size. */ + #define DMA_PDD_8_BIT 0U /**< 8-bit transfer size. */ + #define DMA_PDD_16_BIT 0x1U /**< 16-bit transfer size. */ + #define DMA_PDD_32_BIT 0x2U /**< 32-bit transfer size. */ + #define DMA_PDD_16_BYTE 0x4U /**< 16-byte transfer size. */ + #define DMA_PDD_32_BYTE 0x5U /**< 32-byte transfer size. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* DMA stall time value. */ +#define DMA_PDD_NO_STALL 0U /**< No stall. */ +#define DMA_PDD_STALL_4_CYCLES 0x8000U /**< Stall 4 cycles. */ +#define DMA_PDD_STALL_8_CYCLES 0xC000U /**< Stall 8 cycles. */ + +/* DMA data transfer size. */ +#define DMA_PDD_LINKING_DISABLED 0U /**< Channel linking disabled. */ +#define DMA_PDD_CYCLE_STEAL_AND_TRANSFER_COMPLETE_LINKING 0x10U /**< Channel linked after each cycle-steal transfer and after transfer complete. */ +#define DMA_PDD_CYCLE_STEAL_LINKING 0x20U /**< Channel linked only after each cycle-steal transfer. */ +#define DMA_PDD_TRANSFER_COMPLETE_LINKING 0x30U /**< Channel linked only after transfer complete. */ + + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Writes to DMA channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel control register value. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_WriteControlReg(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ + #define DMA_PDD_WriteControlReg(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Writes to DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA control register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_WriteControlReg(PeripheralBase, Value) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadControlReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_ReadControlReg(PeripheralBase, Channel) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_ReadControlReg(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- CancelTransfer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Cancels remaining data transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DSR_BCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_CancelTransfer(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_CancelTransfer(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DSR_BCR_DONE_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Cancels remaining data transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR, DSR_BCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_CancelTransfer(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_CancelTransfer(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_CX_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ErrorCancelTransfer + ---------------------------------------------------------------------------- */ + +/** + * @brief Cancels remaining data transfer with error generation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_ErrorCancelTransfer(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ErrorCancelTransfer(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_ECX_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMinorLoopMapping + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables minor loop mapping. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if minor loop mapping will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableMinorLoopMapping(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableMinorLoopMapping(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_EMLM_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_EMLM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopMappingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minor loop mapping state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetMinorLoopMappingEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetMinorLoopMappingEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_EMLM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousLinkMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables minor loop continuous link mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if minor loop continuous link mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableContinuousLinkMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableContinuousLinkMode(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_CLM_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_CLM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetContinuousLinkModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns minor loop continuous link mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetContinuousLinkModeEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetContinuousLinkModeEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_CLM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- HaltOperations + ---------------------------------------------------------------------------- */ + +/** + * @brief Halts DMA operations. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_HaltOperations(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_HaltOperations(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) |= \ + DMA_CR_HALT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResumeOperations + ---------------------------------------------------------------------------- */ + +/** + * @brief Resumes halted DMA operations. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_ResumeOperations(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ResumeOperations(PeripheralBase) ( \ + DMA_CR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)DMA_CR_HALT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHaltOnError + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables stalling of DMA operations after error occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if error occurance halts DMA operations. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableHaltOnError(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableHaltOnError(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_HOE_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_HOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetHaltOnErrorEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA operations halt on error state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetHaltOnErrorEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetHaltOnErrorEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_HOE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRoundRobinArbitration + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables round robin channel arbitration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if round robin channel arbitration is + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableRoundRobinArbitration(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableRoundRobinArbitration(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_ERCA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_ERCA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRoundRobinArbitrationEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns round robin channel arbitration state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRoundRobinArbitrationEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRoundRobinArbitrationEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_ERCA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDebug + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA operations in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if DMA operations in debug mode are enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableDebug(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDebug(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_EDBG_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_EDBG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDebugEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA operations in debug mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDebugEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetDebugEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_EDBG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadErrorStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel error status register provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadErrorStatusReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadErrorStatusReg(PeripheralBase) ( \ + DMA_ES_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use ReadErrorStatusReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusRegister(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorStatusRegister(PeripheralBase) ( \ + DMA_ES_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel error status flags provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusFlags(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusFlags(PeripheralBase) ( \ + (uint32)(( \ + DMA_ES_REG(PeripheralBase)) & ( \ + (uint32)(( \ + DMA_ES_ECX_MASK) | (( \ + DMA_ES_GPE_MASK) | (( \ + DMA_ES_CPE_MASK) | (( \ + DMA_ES_SAE_MASK) | (( \ + DMA_ES_SOE_MASK) | (( \ + DMA_ES_DAE_MASK) | (( \ + DMA_ES_DOE_MASK) | (( \ + DMA_ES_NCE_MASK) | (( \ + DMA_ES_SGE_MASK) | (( \ + DMA_ES_SBE_MASK) | ( \ + DMA_ES_DBE_MASK))))))))))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel error status flags provading information about + * last recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorStatusFlags(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusFlags(PeripheralBase) ( \ + (uint32)(( \ + DMA_ES_REG(PeripheralBase)) & ( \ + (uint32)(( \ + DMA_ES_ECX_MASK) | (( \ + DMA_ES_CPE_MASK) | (( \ + DMA_ES_SAE_MASK) | (( \ + DMA_ES_SOE_MASK) | (( \ + DMA_ES_DAE_MASK) | (( \ + DMA_ES_DOE_MASK) | (( \ + DMA_ES_NCE_MASK) | (( \ + DMA_ES_SGE_MASK) | (( \ + DMA_ES_SBE_MASK) | ( \ + DMA_ES_DBE_MASK)))))))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetErrorStatusChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel provading information about last recorded channel + * error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DMA_ES. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetErrorStatusChannel(_BASE_PTR); + * @endcode + */ + #define DMA_PDD_GetErrorStatusChannel(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(DMA_ES_REG(PeripheralBase) & DMA_ES_ERRCHN_MASK)) >> ( \ + DMA_ES_ERRCHN_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteChannelPriorityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteChannelPriorityReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteChannelPriorityReg(PeripheralBase, Channel, Value) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) = (uint8)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelPriorityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = DMA_PDD_ReadChannelPriorityReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadChannelPriorityReg(PeripheralBase, Channel) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- DCHPRI_REG + ---------------------------------------------------------------------------- */ + +/** + * @brief SetChannelPriority channel parameter conversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_DCHPRI_REG(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) ( \ + (&DMA_DCHPRI3_REG(PeripheralBase))[Channel^3U] \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel priority register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @param EnablePreemption Parameter specifying if DMA channel can be + * temporarily suspended by the service request of a higher priority channel. This + * parameter is a 8-bit value. + * @param EnablePreemptAbility Parameter specifying if DMA channel can suspend a + * lower priority channel. This parameter is a 8-bit value. + * @param Priority Data word value. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_SetChannelPriority(_BASE_PTR, periphID, 1, 1, 1); + * @endcode + */ +#define DMA_PDD_SetChannelPriority(PeripheralBase, Channel, EnablePreemption, EnablePreemptAbility, Priority) ( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) = ( \ + (EnablePreemptAbility) ? ( \ + (uint8)((uint8)(EnablePreemption) << DMA_DCHPRI3_ECP_SHIFT) | \ + (uint8)((((uint8)(Priority) & DMA_DCHPRI3_CHPRI_MASK) << DMA_DCHPRI3_CHPRI_SHIFT)) \ + ) : ( \ + (uint8)((uint8)(EnablePreemption) << DMA_DCHPRI3_ECP_SHIFT) | \ + (uint8)((((uint8)(Priority) & DMA_DCHPRI3_CHPRI_MASK) << DMA_DCHPRI3_CHPRI_SHIFT)) | \ + (DMA_DCHPRI3_DPA_MASK) \ + ) \ + )) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableRegs + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set/clear error interrupts and channel requests enable + * registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA control registers value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteEnableRegs(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableRegs(PeripheralBase, Value) ( \ + DMA_CEEI_REG(PeripheralBase) = (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlagRegs + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear done status, clear error and interrupt flags and + * set start channel request registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value DMA flag registers value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteFlagRegs(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteFlagRegs(PeripheralBase, Value) ( \ + DMA_CDNE_REG(PeripheralBase) = (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_WriteEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableRequestReg(PeripheralBase, Value) ( \ + DMA_ERQ_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadEnableRequestReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableRequestReg(PeripheralBase) ( \ + DMA_ERQ_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRequestMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels requests specified by Mask parameter, rest is not + * changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_EnableRequestMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableRequestMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRequestMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels requests specified by Mask parameter, rest is + * not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be disabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_DisableRequestMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableRequestMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRequestEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnableMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetRequestEnableMask(PeripheralBase, Mask) ( \ + DMA_ERQ_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of enabled DMA channels requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERQ. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestEnableMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRequestEnableMask(PeripheralBase) ( \ + DMA_ERQ_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_WriteSetEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetEnableRequestReg(PeripheralBase, Value) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRequestEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel request. If AllChannels = '1' then all requests are + * enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA channel requests. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_SetRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channel peripheral request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SERQ. + * @par Example: + * @code + * DMA_PDD_EnableRequest(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableRequest(PeripheralBase, Channel) ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearEnableRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear enable request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_WriteClearEnableRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearEnableRequestReg(PeripheralBase, Value) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channel peripheral request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_DisableRequest(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableRequest(PeripheralBase, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearRequestEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel request. If AllChannels = '1' then all requests are + * disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA channel requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA channel request number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ. + * @par Example: + * @code + * DMA_PDD_ClearRequestEnable(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearRequestEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePeripheralRequest + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables peripheral requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel peripheral requests will be + * enabled or ignored. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ, DMA_SERQ, + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnablePeripheralRequest(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnablePeripheralRequest(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_ERQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_ERQ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables peripheral requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel request number. This parameter is a 8-bit value. + * @param State Parameter specifying if DMA channel peripheral requests will be + * enabled or ignored. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERQ, DMA_SERQ, + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnablePeripheralRequest(_BASE_PTR, 1, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnablePeripheralRequest(PeripheralBase, Channel, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + DMA_CERQ_REG(PeripheralBase) = \ + (uint8)(Channel)) : ( \ + DMA_SERQ_REG(PeripheralBase) = \ + (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_WriteEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_EEI_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadEnableErrorInterruptReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableErrorInterruptReg(PeripheralBase) ( \ + DMA_EEI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels error interrupts specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be enabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_EnableErrorInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableErrorInterruptMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels error interrupts specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be disabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_DisableErrorInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableErrorInterruptMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channels error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA error interrupts to be enabled. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnableMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetErrorInterruptEnableMask(PeripheralBase, Mask) ( \ + DMA_EEI_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptEnableMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EEI. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetErrorInterruptEnableMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorInterruptEnableMask(PeripheralBase) ( \ + DMA_EEI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_WriteSetEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are enabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Enable all DMA error interrupts. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_SetErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_SetErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channel error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SEEI. + * @par Example: + * @code + * DMA_PDD_EnableErrorInterrupt(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableErrorInterrupt(PeripheralBase, Channel) ( \ + DMA_SEEI_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearEnableErrorInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear enable error interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_WriteClearEnableErrorInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearEnableErrorInterruptReg(PeripheralBase, Value) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorInterruptEnable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel error interrupt. If AllChannels = '1' then all + * interrupts are disabled regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Disable all DMA error interrupts. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA error interrupt channel number. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_ClearErrorInterruptEnable(_BASE_PTR, + * DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorInterruptEnable(PeripheralBase, AllChannels, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channel error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CEEI. + * @par Example: + * @code + * DMA_PDD_DisableErrorInterrupt(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableErrorInterrupt(PeripheralBase, Channel) ( \ + DMA_CEEI_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT. + * @par Example: + * @code + * DMA_PDD_WriteClearInterruptRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearInterruptRequestReg(PeripheralBase, Value) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupt's flags to clear. Use constants from group + * "Interrupts' flags". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_FLAG); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, Channel, Mask) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + (uint32)(Mask) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel interrupt request flag. If AllChannels = '1' then + * all requests are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA interrupt requests. This parameter is of + * "Set all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA interrupt request channel number. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, + * 1); + * @endcode + */ + #define DMA_PDD_ClearInterruptFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CINT. + * @par Example: + * @code + * DMA_PDD_ClearChannelInterruptFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearChannelInterruptFlag(PeripheralBase, Channel) ( \ + DMA_CINT_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * DMA_PDD_WriteInterruptRequestReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteInterruptRequestReg(PeripheralBase, Value) ( \ + DMA_INT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptRequestReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA interrupt request register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadInterruptRequestReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadInterruptRequestReg(PeripheralBase) ( \ + DMA_INT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channels interrupt requests specified by Mask parameter, + * rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA interrupt requests to be cleared. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * DMA_PDD_ClearInterruptFlagsMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearInterruptFlagsMask(PeripheralBase, Mask) ( \ + DMA_INT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels interrupt requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_INT. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetInterruptFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetInterruptFlagsMask(PeripheralBase) ( \ + DMA_INT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear error register register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_WriteClearErrorReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearErrorReg(PeripheralBase, Value) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channel error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearChannelErrorFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearChannelErrorFlag(PeripheralBase, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel error flag. If AllChannels = '1' then all errors + * are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA errors. This parameter is of "Set all or + * only one DMA channel. Used in Set/Clear macros to distinct between + * setting/clearing attribute of one specified channel or of all channels." type. + * @param Channel DMA error channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearErrorFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CERR_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA error register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * DMA_PDD_WriteErrorReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteErrorReg(PeripheralBase, Value) ( \ + DMA_ERR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadErrorReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA error register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadErrorReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadErrorReg(PeripheralBase) ( \ + DMA_ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears DMA channels error flags specified by Mask parameter, rest is + * not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA errors to be cleared. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * DMA_PDD_ClearErrorFlagsMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_ClearErrorFlagsMask(PeripheralBase, Mask) ( \ + DMA_ERR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channel error flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetErrorFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetErrorFlagsMask(PeripheralBase) ( \ + DMA_ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_ERR. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetChannelErrorFlag(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_GetChannelErrorFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_ERR_REG(PeripheralBase) & (uint32)((uint32)0x1U << (uint8)(Channel))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSetStartBitReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA set START bit register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT. + * @par Example: + * @code + * DMA_PDD_WriteSetStartBitReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteSetStartBitReg(PeripheralBase, Value) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartTransfer + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, Channel) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DCR_START_MASK \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Starts DMA channel transfer request via a software initiated service + * request. If AllChannels = '1' then transfer start is requested for all channels + * regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Request transfer start for all channels. This parameter is + * of "Set all or only one DMA channel. Used in Set/Clear macros to + * distinct between setting/clearing attribute of one specified channel or of + * all channels." type. + * @param Channel DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_SSRT, DCR[Channel] + * (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_StartTransfer(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_StartTransfer(PeripheralBase, AllChannels, Channel) ( \ + DMA_SSRT_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteClearDoneBitReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA clear DONE status bit register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_WriteClearDoneBitReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteClearDoneBitReg(PeripheralBase, Value) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDoneFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel done status. If AllChannels = '1' then all status + * of all channels are cleared regardless of Channel parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AllChannels Clear all DMA channels status. This parameter is of "Set + * all or only one DMA channel. Used in Set/Clear macros to distinct + * between setting/clearing attribute of one specified channel or of all + * channels." type. + * @param Channel DMA status channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE. + * @par Example: + * @code + * DMA_PDD_ClearDoneFlags(_BASE_PTR, DMA_PDD_ONE_CHANNEL, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlags(PeripheralBase, AllChannels, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)((uint8)(AllChannels) | (uint8)(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearDoneFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Clears channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CDNE, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_ClearDoneFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_ClearDoneFlag(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DSR_BCR_DONE_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears DMA channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CDNE, + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_ClearDoneFlag(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_ClearDoneFlag(PeripheralBase, Channel) ( \ + DMA_CDNE_REG(PeripheralBase) = \ + (uint8)(Channel) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteHwRequestStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA hardware request status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * DMA_PDD_WriteHwRequestStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteHwRequestStatusReg(PeripheralBase, Value) ( \ + DMA_HRS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHwRequestStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA hardware request status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadHwRequestStatusReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadHwRequestStatusReg(PeripheralBase) ( \ + DMA_HRS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestFlagsMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels requests status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_HRS. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestFlagsMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRequestFlagsMask(PeripheralBase) ( \ + DMA_HRS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSourceAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD source address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteSourceAddressReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteSourceAddressReg(PeripheralBase, Channel, Value) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSourceAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD source address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadSourceAddressReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadSourceAddressReg(PeripheralBase, Channel) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Address DMA channel source address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddress(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddress(PeripheralBase, Channel, Address) ( \ + DMA_SAR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Address DMA channel source address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddress(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddress(PeripheralBase, Channel, Address) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetSourceAddress(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceAddress(PeripheralBase, Channel) ( \ + DMA_SAR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SADDR[Channel], + * SAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetSourceAddress(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetSourceAddress(PeripheralBase, Channel) ( \ + DMA_SADDR_REG(PeripheralBase,(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteDestinationAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD destination address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteDestinationAddressReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteDestinationAddressReg(PeripheralBase, Channel, Value) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDestinationAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD destination address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadDestinationAddressReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadDestinationAddressReg(PeripheralBase, Channel) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Address DMA channel destination address. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddress(_BASE_PTR, DMA_PDD_CHANNEL_0, + * 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddress(PeripheralBase, Channel, Address) ( \ + DMA_DAR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Address DMA channel destination address. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddress(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddress(PeripheralBase, Channel, Address) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Address) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddress + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDestinationAddress(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationAddress(PeripheralBase, Channel) ( \ + DMA_DAR_REG(PeripheralBase,(Channel)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DADDR[Channel], + * DAR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDestinationAddress(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationAddress(PeripheralBase, Channel) ( \ + DMA_DADDR_REG(PeripheralBase,(Channel)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteSourceAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD source address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteSourceAddressOffsetReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteSourceAddressOffsetReg(PeripheralBase, Channel, Value) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSourceAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD source address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadSourceAddressOffsetReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadSourceAddressOffsetReg(PeripheralBase, Channel) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel source address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Offset DMA channel source address offset. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_SetSourceAddressOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetSourceAddressOffset(PeripheralBase, Channel, Offset) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Offset) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel source address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SOFF[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_GetSourceAddressOffset(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetSourceAddressOffset(PeripheralBase, Channel) ( \ + DMA_SOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDestinationAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD destination address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteDestinationAddressOffsetReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteDestinationAddressOffsetReg(PeripheralBase, Channel, Value) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDestinationAddressOffsetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA TCD destination address offset register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadDestinationAddressOffsetReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadDestinationAddressOffsetReg(PeripheralBase, Channel) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel destination address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Offset DMA channel destination address offset. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetDestinationAddressOffset(PeripheralBase, Channel, Offset) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) = \ + (uint16)(Offset) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel destination address offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: DOFF[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetDestinationAddressOffset(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetDestinationAddressOffset(PeripheralBase, Channel) ( \ + DMA_DOFF_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransferAttributesReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel transfer attributes register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Transfer attributes register value. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteTransferAttributesReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteTransferAttributesReg(PeripheralBase, Channel, Value) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransferAttributesReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel transfer attributes register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: ATTR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadTransferAttributesReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadTransferAttributesReg(PeripheralBase, Channel) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSourceAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Modulo DMA channel source address modulo. Use constants from group + * "Circular buffer size constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_CIRCULAR_BUFFER_DISABLED); + * @endcode + */ + #define DMA_PDD_SetSourceAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SMOD_MASK)))) | ( \ + (uint32)((uint32)(Modulo) << DMA_DCR_SMOD_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Modulo DMA channel source address modulo. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceAddressModulo(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetSourceAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_SMOD_MASK)))) | ( \ + (uint16)((uint16)(Modulo) << DMA_ATTR_SMOD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Circular buffer size constants" for + * processing return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DMA_PDD_GetSourceAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SMOD_MASK)) >> ( \ + DMA_DCR_SMOD_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = DMA_PDD_GetSourceAddressModulo(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetSourceAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_SMOD_MASK)) >> ( \ + DMA_ATTR_SMOD_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetSourceDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Size DMA channel source data tranfer block size. This parameter is of + * "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceDataTransferSize(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetSourceDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SSIZE_MASK)))) | ( \ + (uint32)((uint32)(Size) << DMA_DCR_SSIZE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Size DMA channel source data tranfer block size. This parameter is of + * "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetSourceDataTransferSize(_BASE_PTR, periphID, + * DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetSourceDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_SSIZE_MASK)))) | ( \ + (uint16)((uint16)(Size) << DMA_ATTR_SSIZE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSourceDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetSourceDataTransferSize(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetSourceDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SSIZE_MASK)) >> ( \ + DMA_DCR_SSIZE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel source data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetSourceDataTransferSize(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetSourceDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_SSIZE_MASK)) >> ( \ + DMA_ATTR_SSIZE_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetDestinationAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Modulo DMA channel destination address modulo. Use constants from + * group "Circular buffer size constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressModulo(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_CIRCULAR_BUFFER_DISABLED); + * @endcode + */ + #define DMA_PDD_SetDestinationAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DMOD_MASK)))) | ( \ + (uint32)((uint32)(Modulo) << DMA_DCR_DMOD_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Modulo DMA channel destination address modulo. This parameter is a + * 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationAddressModulo(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetDestinationAddressModulo(PeripheralBase, Channel, Modulo) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_DMOD_MASK)))) | ( \ + (uint16)((uint16)(Modulo) << DMA_ATTR_DMOD_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressModulo + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Circular buffer size constants" for + * processing return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationAddressModulo(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DMOD_MASK)) >> ( \ + DMA_DCR_DMOD_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination address modulo. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationAddressModulo(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationAddressModulo(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_DMOD_MASK)) >> ( \ + DMA_ATTR_DMOD_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetDestinationDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Sets DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Size DMA channel destination data tranfer block size. This parameter + * is of "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationDataTransferSize(_BASE_PTR, + * DMA_PDD_CHANNEL_0, DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetDestinationDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DSIZE_MASK)))) | ( \ + (uint32)((uint32)(Size) << DMA_DCR_DSIZE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Size DMA channel destination data tranfer block size. This parameter + * is of "DMA data transfer block size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_SetDestinationDataTransferSize(_BASE_PTR, periphID, + * DMA_PDD_8_BIT); + * @endcode + */ + #define DMA_PDD_SetDestinationDataTransferSize(PeripheralBase, Channel, Size) ( \ + DMA_ATTR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_ATTR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_ATTR_DSIZE_MASK)))) | ( \ + (uint16)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDestinationDataTransferSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationDataTransferSize(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDestinationDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DSIZE_MASK)) >> ( \ + DMA_DCR_DSIZE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel destination data tranfer size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 3-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: ATTR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetDestinationDataTransferSize(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDestinationDataTransferSize(PeripheralBase, Channel) ( \ + (uint8)(DMA_ATTR_REG(PeripheralBase,(Channel)) & DMA_ATTR_DSIZE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteMinorLoopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel minor loop register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteMinorLoopReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteMinorLoopReg(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMinorLoopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor loop register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadMinorLoopReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadMinorLoopReg(PeripheralBase, Channel) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 32-bit DMA channel byte count. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount32(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount32(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount32 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount32(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount32(PeripheralBase, Channel) ( \ + DMA_NBYTES_MLNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount30 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 30-bit DMA channel byte count. This parameter is a 30-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount30(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount30(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFNO_NBYTES_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount30 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 30-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: NBYTES_MLOFFNO[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount30(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount30(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFNO_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFNO_NBYTES_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount10 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 10-bit DMA channel byte count. This parameter is a 10-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount10(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount10(PeripheralBase, Channel, Value) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_NBYTES_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount10 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount10(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetByteCount10(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFYES_NBYTES_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSourceMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel source minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel source minor loop offset + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableSourceMinorLoopOffset(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableSourceMinorLoopOffset(PeripheralBase, Channel, State) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_SMLOE_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDestinationMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel destination minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel source minor loop offset + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableDestinationMinorLoopOffset(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDestinationMinorLoopOffset(PeripheralBase, Channel, State) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_DMLOE_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopOffsetEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns source and destination minor loop offset enable bits state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetMinorLoopOffsetEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetMinorLoopOffsetEnabled(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param AddressOffset Address offset added to source and/or destination + * address. This parameter is a 20-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMinorLoopOffset(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetMinorLoopOffset(PeripheralBase, Channel, AddressOffset) ( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_NBYTES_MLOFFYES_MLOFF_MASK)))) | ( \ + (uint32)((uint32)(AddressOffset) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMinorLoopOffset + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel minor loop offset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 20-bit value. The value is cast to "uint32". + * @remarks The macro accesses the following registers: NBYTES_MLOFFYES[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetMinorLoopOffset(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetMinorLoopOffset(PeripheralBase, Channel) ( \ + (uint32)(( \ + (uint32)(( \ + DMA_NBYTES_MLOFFYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_NBYTES_MLOFFYES_MLOFF_MASK))) >> ( \ + DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCurrentMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel current minor loop link major loop count + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteCurrentMajorLoopCountReg(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_WriteCurrentMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCurrentMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel current minor loop link major loop count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadCurrentMajorLoopCountReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_ReadCurrentMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCurrentMinorLoopLinking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel current minor loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableCurrentMinorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableCurrentMinorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKNO_ELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CITER_ELINKNO_ELINK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCurrentMinorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current minor loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMinorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMinorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_CITER_ELINKNO_ELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel current major loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 15-bit DMA channel major loop count. This parameter is a 15-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount15(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_SetCurrentMajorLoopCount15(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKNO_CITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)(Value))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @param Value DMA channel major loop count. This parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_CITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetCurrentMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel current major loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 15-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: CITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMajorLoopCount15(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMajorLoopCount15(PeripheralBase, Channel) ( \ + (uint16)(DMA_CITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_CITER_ELINKNO_CITER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCurrentMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel current major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel 9-bit DMA channel number. This parameter is of index type. + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetCurrentMajorLoopCount9(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetCurrentMajorLoopCount9(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_CITER_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCurrentMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel current link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetCurrentMinorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetCurrentMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetCurrentMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel current link number when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetCurrentMinorLinkChannel(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetCurrentMinorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(( \ + DMA_CITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_CITER_ELINKYES_LINKCH_MASK))) >> ( \ + DMA_CITER_ELINKYES_LINKCH_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteBeginningMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel beginning minor loop link major loop count + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteBeginningMajorLoopCountReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteBeginningMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBeginningMajorLoopCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel beginning minor loop link major loop count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel minor loop link major loop count register value. + * This parameter is a 16-bit value. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_ReadBeginningMajorLoopCountReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_ReadBeginningMajorLoopCountReg(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBeginningMinorLoopLinking + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DMA channel beginning minor loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableBeginningMinorLoopLinking(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableBeginningMinorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKNO_ELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_BITER_ELINKNO_ELINK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBeginningMinorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns beginning minor loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMinorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMinorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_BITER_ELINKNO_ELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 15-bit DMA channel major loop count. This parameter is a 15-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount15(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_SetBeginningMajorLoopCount15(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKNO_BITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBeginningMajorLoopCount15 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 15-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: BITER_ELINKNO[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMajorLoopCount15(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMajorLoopCount15(PeripheralBase, Channel) ( \ + (uint16)(DMA_BITER_ELINKNO_REG(PeripheralBase,(Channel)) & DMA_BITER_ELINKNO_BITER_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)(Value))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel beginning major loop count when channel linking is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value 9-bit DMA channel major loop count. This parameter is a 9-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMajorLoopCount9(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMajorLoopCount9(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_BITER_MASK)))) | ( \ + (uint16)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetBeginningMajorLoopCount9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel major beginning loop count when channel linking is + * disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetBeginningMajorLoopCount9(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetBeginningMajorLoopCount9(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + DMA_BITER_ELINKYES_BITER_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBeginningMinorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x7800U))))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x4000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel beginning link number when channel linking is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: BITER_ELINKYES[Channel]. + * @par Example: + * @code + * DMA_PDD_SetBeginningMinorLinkChannel(_BASE_PTR, periphID, + * 1); + * @endcode + */ + #define DMA_PDD_SetBeginningMinorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_BITER_ELINKYES_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_BITER_ELINKYES_LINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_BITER_ELINKYES_LINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- WriteLastSourceAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD last source address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteLastSourceAddressAdjustmentReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteLastSourceAddressAdjustmentReg(PeripheralBase, Channel, Value) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLastSourceAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA TCD last source address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadLastSourceAddressAdjustmentReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadLastSourceAddressAdjustmentReg(PeripheralBase, Channel) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLastSourceAddressAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel last source address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel last source address adjustment. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLastSourceAddressAdjustment(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define DMA_PDD_SetLastSourceAddressAdjustment(PeripheralBase, Channel, Value) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLastSourceAddressAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel last source address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SLAST[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetLastSourceAddressAdjustment(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetLastSourceAddressAdjustment(PeripheralBase, Channel) ( \ + DMA_SLAST_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLastDestinationAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA TCD last destination address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteLastDestinationAddressAdjustmentReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteLastDestinationAddressAdjustmentReg(PeripheralBase, Channel, Value) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLastDestinationAddressAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA TCD last destination address adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadLastDestinationAddressAdjustmentReg(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_ReadLastDestinationAddressAdjustmentReg(PeripheralBase, Channel) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLastDestinationAddressAdjustment_ScatterGather + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel last destination address adjustment or address for + * next TCD to be loaded into this channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel last destination address adjustment or TCD address. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLastDestinationAddressAdjustment_ScatterGather(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define DMA_PDD_SetLastDestinationAddressAdjustment_ScatterGather(PeripheralBase, Channel, Value) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLastDestinationAddressAdjustment_ScatterGather + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel last destination address adjustment. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DLAST_SGA[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetLastDestinationAddressAdjustment_ScatterGather(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetLastDestinationAddressAdjustment_ScatterGather(PeripheralBase, Channel) ( \ + DMA_DLAST_SGA_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value Channel control status register value. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteControlStatusReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define DMA_PDD_WriteControlStatusReg(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads DMA channel control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_ReadControlStatusReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_ReadControlStatusReg(PeripheralBase, Channel) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStallTime + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)(StallTime))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)(StallTime))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Bandwidth control - forces DMA to stall after each r/w operation for + * selected period of time. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param StallTime Selects one of stall time values. This parameter is of "DMA + * stall time value." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetStallTime(_BASE_PTR, periphID, DMA_PDD_NO_STALL); + * @endcode + */ + #define DMA_PDD_SetStallTime(PeripheralBase, Channel, StallTime) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_BWC_MASK)))) | ( \ + (uint16)(StallTime))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetStallTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns bandwidth control stall time value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetStallTime(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetStallTime(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_BWC_MASK)) >> ( \ + DMA_CSR_BWC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMajorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param Value DMA channel number. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetMajorLinkChannel(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_SetMajorLinkChannel(PeripheralBase, Channel, Value) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORLINKCH_MASK)))) | ( \ + (uint16)((uint16)(Value) << DMA_CSR_MAJORLINKCH_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetMajorLinkChannel + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns DMA channel major link number. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetMajorLinkChannel(_BASE_PTR, + * periphID); + * @endcode + */ + #define DMA_PDD_GetMajorLinkChannel(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORLINKCH_MASK)) >> ( \ + DMA_CSR_MAJORLINKCH_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetChannelActivityFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns DMA channel request pending, busy and done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Channel activity status constants" for + * processing return value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetChannelActivityFlags(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetChannelActivityFlags(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_DSR_BCR_REQ_MASK | (DMA_DSR_BCR_BSY_MASK | DMA_DSR_BCR_DONE_MASK)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns channel done and channel active status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetChannelActivityFlags(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetChannelActivityFlags(PeripheralBase, Channel) ( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(DMA_CSR_DONE_MASK | DMA_CSR_ACTIVE_MASK))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ClearChannelActivityFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)((uint16)(~(uint16)(ChannelActivityFlags)) & (uint16)(~(uint16)0x3C00U)) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)((uint16)(~(uint16)(ChannelActivityFlags)) & (uint16)(~(uint16)0x2000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Clears channel activity status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param ChannelActivityFlags DMA channel activity status flags. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_ClearChannelActivityFlags(_BASE_PTR, periphID, 1); + * @endcode + */ + #define DMA_PDD_ClearChannelActivityFlags(PeripheralBase, Channel, ChannelActivityFlags) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) &= \ + (uint16)(~(uint16)(ChannelActivityFlags)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetDoneFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = DMA_PDD_GetDoneFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetDoneFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_DONE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns channel done status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DSR_BCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = DMA_PDD_GetDoneFlag(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetDoneFlag(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_DONE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel active status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = DMA_PDD_GetActiveFlag(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetActiveFlag(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_ACTIVE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMajorLoopLinking + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel major loop linking. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel linking will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableMajorLoopLinking(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableMajorLoopLinking(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_MAJORELINK_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_MAJORELINK_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetMajorLoopLinkingEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns major loop linking state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetMajorLoopLinkingEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetMajorLoopLinkingEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_MAJORELINK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableScatterGather + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel scatter/gather processing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel scatter/gather processing + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableScatterGather(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableScatterGather(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_ESG_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_ESG_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetScatterGatherEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns scatter/gather processing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetScatterGatherEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetScatterGatherEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_ESG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRequestAutoDisable + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_D_REQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_D_REQ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables DMA channel automaticall request clearing. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel automaticall request + * clearing will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableRequestAutoDisable(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableRequestAutoDisable(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_DREQ_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_DREQ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetRequestAutoDisableEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns automaticall request clearing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRequestAutoDisableEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetRequestAutoDisableEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_D_REQ_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns automaticall request clearing state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetRequestAutoDisableEnabled(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetRequestAutoDisableEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_DREQ_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransferCompleteInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#elif ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_EINT_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_EINT_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables channel transfer complete interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer complete interrupt + * will be enabled or disabled. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * DMA_PDD_EnableTransferCompleteInterrupt(_BASE_PTR, + * periphID, PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferCompleteInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_INTMAJOR_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTMAJOR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetTransferCompleteInterruptEnabled + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4))) +/** + * @brief Returns transfer complete enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetTransferCompleteInterruptEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ + #define DMA_PDD_GetTransferCompleteInterruptEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_EINT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns transfer complete enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel], + * DCR[Channel] (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetTransferCompleteInterruptEnabled(_BASE_PTR, periphID); + * @endcode + */ + #define DMA_PDD_GetTransferCompleteInterruptEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_INTMAJOR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransferHalfInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK22F12810)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810))) +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)) & ( \ + (uint16)(~(uint16)0x3C00U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & (( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)) & ( \ + (uint16)(~(uint16)0x2000U))))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Enables or disables channel transfer half interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @param State Parameter specifying if DMA channel transfer half interrupt will + * be enabled or disabled. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableTransferHalfInterrupt(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ + #define DMA_PDD_EnableTransferHalfInterrupt(PeripheralBase, Channel, State) ( \ + DMA_CSR_REG(PeripheralBase,(Channel)) = \ + (uint16)(( \ + (uint16)(( \ + DMA_CSR_REG(PeripheralBase,(Channel))) & ( \ + (uint16)(~(uint16)DMA_CSR_INTHALF_MASK)))) | ( \ + (uint16)((uint16)(State) << DMA_CSR_INTHALF_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetTransferHalfInterruptEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transfer half enable interrupt state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: CSR[Channel]. + * @par Example: + * @code + * uint16 result = + * DMA_PDD_GetTransferHalfInterruptEnabled(_BASE_PTR, periphID); + * @endcode + */ +#define DMA_PDD_GetTransferHalfInterruptEnabled(PeripheralBase, Channel) ( \ + (uint16)(DMA_CSR_REG(PeripheralBase,(Channel)) & DMA_CSR_INTHALF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelGroup1Priority + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets group 1 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup1Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup1Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP1PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP1PRI_SHIFT))) \ + ) +#else /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Sets group 1 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup1Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup1Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP1PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP1PRI_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- SetChannelGroup0Priority + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/** + * @brief Sets group 0 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 1-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup0Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup0Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP0PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP0PRI_SHIFT))) \ + ) +#else /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Sets group 0 priority level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Priority Parameter specifying group priority 1 level when fixed + * priority group arbitration is enabled. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_SetChannelGroup0Priority(_BASE_PTR, 1); + * @endcode + */ + #define DMA_PDD_SetChannelGroup0Priority(PeripheralBase, Priority) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_GRP0PRI_MASK))) | ( \ + (uint32)((uint32)(Priority) << DMA_CR_GRP0PRI_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- EnableRoundRobinGroupArbitration + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables round robin group arbitration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if round robin group arbitration is enabled + * or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * DMA_PDD_EnableRoundRobinGroupArbitration(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableRoundRobinGroupArbitration(PeripheralBase, State) ( \ + DMA_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(DMA_CR_REG(PeripheralBase) & (uint32)(~(uint32)DMA_CR_ERGA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_CR_ERGA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRoundRobinGroupArbitrationEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns round robin group arbitration state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_CR. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetRoundRobinGroupArbitrationEnabled(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetRoundRobinGroupArbitrationEnabled(PeripheralBase) ( \ + (uint32)(DMA_CR_REG(PeripheralBase) & DMA_CR_ERGA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelGroupPriority + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns group priority assigned to specified DMA channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel index. This parameter is of index type. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @par Example: + * @code + * uint8 result = DMA_PDD_GetChannelGroupPriority(_BASE_PTR, + * periphID); + * @endcode + */ +#define DMA_PDD_GetChannelGroupPriority(PeripheralBase, Channel) ( \ + (uint8)( \ + (DMA_PDD_DCHPRI_REG(PeripheralBase, Channel) & DMA_DCHPRI3_GRPPRI_MASK) >> DMA_DCHPRI3_GRPPRI_SHIFT \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA channels asynchrounous requests in stop mode specified by + * Mask parameter, rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_EnableAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_EnableAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA channels asynchrounous requests in stop mode specified by + * Mask parameter, rest is not changed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be disabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_DisableAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_DisableAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mask of DMA channels enabled for asynchronous requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA requests to be enabled. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_SetAsyncRequestInStopMask(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_SetAsyncRequestInStopMask(PeripheralBase, Mask) ( \ + DMA_EARS_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAsyncRequestInStopMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns mask of DMA channels enabled for asynchronous request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetAsyncRequestInStopMask(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_GetAsyncRequestInStopMask(PeripheralBase) ( \ + DMA_EARS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEnableAsyncRequestInStopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA enable asynchronous request in STOP register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Register value. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * DMA_PDD_WriteEnableAsyncRequestInStopReg(_BASE_PTR, 1); + * @endcode + */ +#define DMA_PDD_WriteEnableAsyncRequestInStopReg(PeripheralBase, Value) ( \ + DMA_EARS_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEnableAsyncRequestInStopReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA enable asynchronous request in STOP register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DMA_EARS. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_ReadEnableAsyncRequestInStopReg(_BASE_PTR); + * @endcode + */ +#define DMA_PDD_ReadEnableAsyncRequestInStopReg(PeripheralBase) ( \ + DMA_EARS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupts to enable. Use constants from group + * "Interrupts' mask". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableInterrupts(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_INTERRUPT); + * @endcode + */ +#define DMA_PDD_EnableInterrupts(PeripheralBase, Channel, Mask) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mask Mask of interrupts to disable. Use constants from group + * "Interrupts' mask". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_DisableInterrupts(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_TRANSFER_COMPLETE_INTERRUPT); + * @endcode + */ +#define DMA_PDD_DisableInterrupts(PeripheralBase, Channel, Mask) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Interrupts' flags" for processing return + * value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetInterruptFlags(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetInterruptFlags(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_DONE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusByteCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel status and byte count control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteStatusByteCountReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_WriteStatusByteCountReg(PeripheralBase, Channel, Value) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusByteCountRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use WriteStatusByteCountReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * DMA_PDD_WriteStatusByteCountRegister(_BASE_PTR, + * DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_WriteStatusByteCountRegister(PeripheralBase, Channel, Value) ( \ + DMA_PDD_WriteStatusByteCountReg(PeripheralBase, (Channel), (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusByteCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel status and byte count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_ReadStatusByteCountReg(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_ReadStatusByteCountReg(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusByteCountRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Deprecated. Use ReadStatusByteCountReg PDD macro instead. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetStatusByteCountRegister(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetStatusByteCountRegister(PeripheralBase, Channel) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to DMA channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value DMA channel request control register value. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR[Channel]. + * @par Example: + * @code + * DMA_PDD_WriteStatusRegister(_BASE_PTR, DMA_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define DMA_PDD_WriteStatusRegister(PeripheralBase, Channel, Value) ( \ + DMA_DSR_REG(PeripheralBase,(Channel)) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusRegister + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel status register provading information about last + * recorded channel error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: DSR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetStatusRegister(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetStatusRegister(PeripheralBase, Channel) ( \ + DMA_DSR_REG(PeripheralBase,(Channel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel busy status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetBusyFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetBusyFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_BSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRequestPendingFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel request pending status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetRequestPendingFlag(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetRequestPendingFlag(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_REQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel configuration error, bus error on source and bus + * error on destination status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Use constants from group "Channel error status constants" for + * processing return value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetChannelErrorFlags(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetChannelErrorFlags(PeripheralBase, Channel) ( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(DMA_DSR_BCR_CE_MASK | (DMA_DSR_BCR_BES_MASK | DMA_DSR_BCR_BED_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetByteCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value 24-bit DMA channel byte count. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetByteCount(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetByteCount(PeripheralBase, Channel, Value) ( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DSR_BCR_REG(PeripheralBase,(Channel))) & (( \ + (uint32)(~(uint32)DMA_DSR_BCR_BCR_MASK)) & ( \ + (uint32)(~(uint32)DMA_DSR_BCR_DONE_MASK))))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetByteCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel byte transfer count. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DSR_BCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetByteCount(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetByteCount(PeripheralBase, Channel) ( \ + (uint32)(DMA_DSR_BCR_REG(PeripheralBase,(Channel)) & DMA_DSR_BCR_BCR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPeripheralRequestEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns peripheral requests enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetPeripheralRequestEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetPeripheralRequestEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_ERQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCycleSteal + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables cycle steal mode (single read/write transfer per + * request). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel cycle-steal mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableCycleSteal(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableCycleSteal(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & (uint32)(~(uint32)DMA_DCR_CS_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_CS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCycleStealEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns cycle steal mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetCycleStealEnabled(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetCycleStealEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_CS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables continuous mode (whole transfer per request). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel continuous mode will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableContinuousMode(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableContinuousMode(PeripheralBase, Channel, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) |= \ + DMA_DCR_CS_MASK) : ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) &= \ + (uint32)(~(uint32)DMA_DCR_CS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetContinuousModeEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns continuous mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = + * DMA_PDD_GetContinuousModeEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetContinuousModeEnabled(PeripheralBase, Channel) ( \ + ((uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_CS_MASK) == 0U) ? ( \ + PDD_ENABLE) : ( \ + PDD_DISABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAutoAlign + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables auto-align mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfers will be transfers + * are optimized based on the address and size or not. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableAutoAlign(_BASE_PTR, DMA_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableAutoAlign(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & (uint32)(~(uint32)DMA_DCR_AA_MASK))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_AA_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAutoAlignEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns auto-align mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = DMA_PDD_GetAutoAlignEnabled(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetAutoAlignEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_AA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAsynchronousRequests + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables asynchronous requests. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel transfers will be transfers + * are optimized based on the address and size or not. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableAsynchronousRequests(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableAsynchronousRequests(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_EADREQ_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_EADREQ_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAsynchronousRequestsEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns auto-align mode state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetAsynchronousRequestsEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetAsynchronousRequestsEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_EADREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSourceAddressIncrement + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables source address incrementation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel source address increments + * after each successful transfer (according to transfer size) or not. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableSourceAddressIncrement(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableSourceAddressIncrement(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_SINC_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_SINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSourceAddressIncrementEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns source address incrementation enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetSourceAddressIncrementEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetSourceAddressIncrementEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_SINC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDestinationAddressIncrement + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables destination address incrementation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param State Parameter specifying if DMA channel destination address + * increments after each successful transfer (according to transfer size) or not. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_EnableDestinationAddressIncrement(_BASE_PTR, + * DMA_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define DMA_PDD_EnableDestinationAddressIncrement(PeripheralBase, Channel, State) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_DINC_MASK)))) | ( \ + (uint32)((uint32)(State) << DMA_DCR_DINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDestinationAddressIncrementEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns destination address incrementation enable state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint32 result = + * DMA_PDD_GetDestinationAddressIncrementEnabled(_BASE_PTR, DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetDestinationAddressIncrementEnabled(PeripheralBase, Channel) ( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_DINC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelLinkingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel linking mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Mode DMA channel linking mode. This parameter is of "DMA data transfer + * size." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetChannelLinkingMode(_BASE_PTR, DMA_PDD_CHANNEL_0, + * DMA_PDD_LINKING_DISABLED); + * @endcode + */ +#define DMA_PDD_SetChannelLinkingMode(PeripheralBase, Channel, Mode) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LINKCC_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelLinkingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel linking mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetChannelLinkingMode(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetChannelLinkingMode(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LINKCC_MASK)) >> ( \ + DMA_DCR_LINKCC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLinkChannel1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel link 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value Linked DMA channel number. Use constants from group "DMA channel + * constants". This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLinkChannel1(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetLinkChannel1(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LCH1_MASK)))) | ( \ + (uint32)((uint32)(Value) << DMA_DCR_LCH1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLinkChannel1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel link 1 channel number. Use constants from group + * "DMA channel constants" for processing return value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetLinkChannel1(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetLinkChannel1(PeripheralBase, Channel) ( \ + (uint8)(( \ + (uint32)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LCH1_MASK)) >> ( \ + DMA_DCR_LCH1_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLinkChannel2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DMA channel link 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @param Value Linked DMA channel number. Use constants from group "DMA channel + * constants". This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * DMA_PDD_SetLinkChannel2(_BASE_PTR, DMA_PDD_CHANNEL_0, 1); + * @endcode + */ +#define DMA_PDD_SetLinkChannel2(PeripheralBase, Channel, Value) ( \ + DMA_DCR_REG(PeripheralBase,(Channel)) = \ + (uint32)(( \ + (uint32)(( \ + DMA_DCR_REG(PeripheralBase,(Channel))) & ( \ + (uint32)(~(uint32)DMA_DCR_LCH2_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLinkChannel2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns DMA channel link 2 channel number. Use constants from group + * "DMA channel constants" for processing return value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Channel DMA channel number. Use constants from group "DMA channel + * constants". This parameter is 2 bits wide. + * @return Returns a 2-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: DCR[Channel]. + * @par Example: + * @code + * uint8 result = DMA_PDD_GetLinkChannel2(_BASE_PTR, + * DMA_PDD_CHANNEL_0); + * @endcode + */ +#define DMA_PDD_GetLinkChannel2(PeripheralBase, Channel) ( \ + (uint8)(DMA_DCR_REG(PeripheralBase,(Channel)) & DMA_DCR_LCH2_MASK) \ + ) +#endif /* #if defined(DMA_PDD_H_) */ + +/* DMA_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h new file mode 100644 index 0000000..2f524a0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/EWM_PDD.h @@ -0,0 +1,490 @@ +/* + PDD layer implementation for peripheral type EWM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(EWM_PDD_H_) +#define EWM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error EWM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* EWM */ && \ + !defined(MCU_MK10D5) /* EWM */ && \ + !defined(MCU_MK10D7) /* EWM */ && \ + !defined(MCU_MK10F12) /* EWM */ && \ + !defined(MCU_MK10DZ10) /* EWM */ && \ + !defined(MCU_MK11D5) /* EWM */ && \ + !defined(MCU_MK11D5WS) /* EWM */ && \ + !defined(MCU_MK12D5) /* EWM */ && \ + !defined(MCU_MK20D10) /* EWM */ && \ + !defined(MCU_MK20D5) /* EWM */ && \ + !defined(MCU_MK20D7) /* EWM */ && \ + !defined(MCU_MK20F12) /* EWM */ && \ + !defined(MCU_MK20DZ10) /* EWM */ && \ + !defined(MCU_MK21D5) /* EWM */ && \ + !defined(MCU_MK21D5WS) /* EWM */ && \ + !defined(MCU_MK21F12) /* EWM */ && \ + !defined(MCU_MK21F12WS) /* EWM */ && \ + !defined(MCU_MK22D5) /* EWM */ && \ + !defined(MCU_MK22F12810) /* EWM */ && \ + !defined(MCU_MK22F12) /* EWM */ && \ + !defined(MCU_MK22F25612) /* EWM */ && \ + !defined(MCU_MK22F51212) /* EWM */ && \ + !defined(MCU_MK24F12) /* EWM */ && \ + !defined(MCU_MK30D10) /* EWM */ && \ + !defined(MCU_MK30D7) /* EWM */ && \ + !defined(MCU_MK30DZ10) /* EWM */ && \ + !defined(MCU_MK40D10) /* EWM */ && \ + !defined(MCU_MK40D7) /* EWM */ && \ + !defined(MCU_MK40DZ10) /* EWM */ && \ + !defined(MCU_MK40X256VMD100) /* EWM */ && \ + !defined(MCU_MK50D10) /* EWM */ && \ + !defined(MCU_MK50D7) /* EWM */ && \ + !defined(MCU_MK50DZ10) /* EWM */ && \ + !defined(MCU_MK51D10) /* EWM */ && \ + !defined(MCU_MK51D7) /* EWM */ && \ + !defined(MCU_MK51DZ10) /* EWM */ && \ + !defined(MCU_MK52D10) /* EWM */ && \ + !defined(MCU_MK52DZ10) /* EWM */ && \ + !defined(MCU_MK53D10) /* EWM */ && \ + !defined(MCU_MK53DZ10) /* EWM */ && \ + !defined(MCU_MK60D10) /* EWM */ && \ + !defined(MCU_MK60F12) /* EWM */ && \ + !defined(MCU_MK60F15) /* EWM */ && \ + !defined(MCU_MK60DZ10) /* EWM */ && \ + !defined(MCU_MK60N512VMD100) /* EWM */ && \ + !defined(MCU_MK61F12) /* EWM */ && \ + !defined(MCU_MK61F15) /* EWM */ && \ + !defined(MCU_MK61F12WS) /* EWM */ && \ + !defined(MCU_MK61F15WS) /* EWM */ && \ + !defined(MCU_MK63F12) /* EWM */ && \ + !defined(MCU_MK63F12WS) /* EWM */ && \ + !defined(MCU_MK64F12) /* EWM */ && \ + !defined(MCU_MK65F18) /* EWM */ && \ + !defined(MCU_MK65F18WS) /* EWM */ && \ + !defined(MCU_MK66F18) /* EWM */ && \ + !defined(MCU_MK70F12) /* EWM */ && \ + !defined(MCU_MK70F15) /* EWM */ && \ + !defined(MCU_MK70F12WS) /* EWM */ && \ + !defined(MCU_MK70F15WS) /* EWM */ && \ + !defined(MCU_MKV10Z7) /* EWM */ && \ + !defined(MCU_MKV31F12810) /* EWM */ && \ + !defined(MCU_MKV31F25612) /* EWM */ && \ + !defined(MCU_MKV31F51212) /* EWM */ && \ + !defined(MCU_MKW21D5) /* EWM */ && \ + !defined(MCU_MKW21D5WS) /* EWM */ && \ + !defined(MCU_MKW22D5) /* EWM */ && \ + !defined(MCU_MKW22D5WS) /* EWM */ && \ + !defined(MCU_MKW24D5) /* EWM */ && \ + !defined(MCU_MKW24D5WS) /* EWM */ && \ + !defined(MCU_PCK20L4) /* EWM */ + // Unsupported MCU is active + #error EWM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Service constants */ +#define EWM_PDD_KEY_1 0xB4U /**< First key */ +#define EWM_PDD_KEY_2 0x2CU /**< Second key */ + +/* Clock source constants. */ +#define EWM_PDD_SOURCE_ROSC_8M 0U /**< Relaxation oscillator clock */ +#define EWM_PDD_SOURCE_XTAL_OSC 0x1U /**< Crystal oscillator clock */ +#define EWM_PDD_SOURCE_BUS_CLK 0x2U /**< IP bus clock */ +#define EWM_PDD_SOURCE_ROSC_200K 0x3U /**< Low speed oscillator clock */ + + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteControlReg(PeripheralBase, Value) ( \ + EWM_CTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of EWM device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(EWM_CTRL_REG(PeripheralBase) & EWM_CTRL_EWMEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare low register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CMPL. + * @par Example: + * @code + * EWM_PDD_WriteCompareLowReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteCompareLowReg(PeripheralBase, Value) ( \ + EWM_CMPL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CMPL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadCompareLowReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadCompareLowReg(PeripheralBase) ( \ + EWM_CMPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare high register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CMPH. + * @par Example: + * @code + * EWM_PDD_WriteCompareHighReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteCompareHighReg(PeripheralBase, Value) ( \ + EWM_CMPH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CMPH. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadCompareHighReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadCompareHighReg(PeripheralBase) ( \ + EWM_CMPH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteServiceReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the service register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_SERV. + * @par Example: + * @code + * EWM_PDD_WriteServiceReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteServiceReg(PeripheralBase, Value) ( \ + EWM_SERV_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the EWM interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_DisableInterrupt(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)EWM_CTRL_INTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the EWM interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * EWM_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_EnableInterrupt(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) |= \ + EWM_CTRL_INTEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * EWM_PDD_SelectClockSource(_BASE_PTR, + * EWM_PDD_SOURCE_ROSC_8M); + * @endcode + */ +#define EWM_PDD_SelectClockSource(PeripheralBase, Source) ( \ + EWM_CLKCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(EWM_CLKCTRL_REG(PeripheralBase) & (uint8)(~(uint8)EWM_CLKCTRL_CLKSEL_MASK))) | ( \ + (uint8)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the prescaler. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * EWM_PDD_SetPrescaler(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_SetPrescaler(PeripheralBase, Value) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadControlReg(PeripheralBase) ( \ + EWM_CTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the clock control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * EWM_PDD_WriteClockControlReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteClockControlReg(PeripheralBase, Value) ( \ + EWM_CLKCTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CLKCTRL. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadClockControlReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadClockControlReg(PeripheralBase) ( \ + EWM_CLKCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the clock prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the clock prescaler register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * EWM_PDD_WriteClockPrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define EWM_PDD_WriteClockPrescalerReg(PeripheralBase, Value) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the clock prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: EWM_CLKPRESCALER. + * @par Example: + * @code + * uint8 result = EWM_PDD_ReadClockPrescalerReg(_BASE_PTR); + * @endcode + */ +#define EWM_PDD_ReadClockPrescalerReg(PeripheralBase) ( \ + EWM_CLKPRESCALER_REG(PeripheralBase) \ + ) +#endif /* #if defined(EWM_PDD_H_) */ + +/* EWM_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h new file mode 100644 index 0000000..5410393 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FMC_PDD.h @@ -0,0 +1,1244 @@ +/* + PDD layer implementation for peripheral type FMC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FMC_PDD_H_) +#define FMC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FMC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FMC */ && \ + !defined(MCU_MK10D5) /* FMC */ && \ + !defined(MCU_MK10D7) /* FMC */ && \ + !defined(MCU_MK10F12) /* FMC */ && \ + !defined(MCU_MK10DZ10) /* FMC */ && \ + !defined(MCU_MK11D5) /* FMC */ && \ + !defined(MCU_MK11D5WS) /* FMC */ && \ + !defined(MCU_MK12D5) /* FMC */ && \ + !defined(MCU_MK20D10) /* FMC */ && \ + !defined(MCU_MK20D5) /* FMC */ && \ + !defined(MCU_MK20D7) /* FMC */ && \ + !defined(MCU_MK20F12) /* FMC */ && \ + !defined(MCU_MK20DZ10) /* FMC */ && \ + !defined(MCU_MK21D5) /* FMC */ && \ + !defined(MCU_MK21D5WS) /* FMC */ && \ + !defined(MCU_MK21F12) /* FMC */ && \ + !defined(MCU_MK21F12WS) /* FMC */ && \ + !defined(MCU_MK22D5) /* FMC */ && \ + !defined(MCU_MK22F12810) /* FMC */ && \ + !defined(MCU_MK22F12) /* FMC */ && \ + !defined(MCU_MK22F25612) /* FMC */ && \ + !defined(MCU_MK22F51212) /* FMC */ && \ + !defined(MCU_MK24F12) /* FMC */ && \ + !defined(MCU_MK30D10) /* FMC */ && \ + !defined(MCU_MK30D7) /* FMC */ && \ + !defined(MCU_MK30DZ10) /* FMC */ && \ + !defined(MCU_MK40D10) /* FMC */ && \ + !defined(MCU_MK40D7) /* FMC */ && \ + !defined(MCU_MK40DZ10) /* FMC */ && \ + !defined(MCU_MK40X256VMD100) /* FMC */ && \ + !defined(MCU_MK50D10) /* FMC */ && \ + !defined(MCU_MK50D7) /* FMC */ && \ + !defined(MCU_MK50DZ10) /* FMC */ && \ + !defined(MCU_MK51D10) /* FMC */ && \ + !defined(MCU_MK51D7) /* FMC */ && \ + !defined(MCU_MK51DZ10) /* FMC */ && \ + !defined(MCU_MK52D10) /* FMC */ && \ + !defined(MCU_MK52DZ10) /* FMC */ && \ + !defined(MCU_MK53D10) /* FMC */ && \ + !defined(MCU_MK53DZ10) /* FMC */ && \ + !defined(MCU_MK60D10) /* FMC */ && \ + !defined(MCU_MK60F12) /* FMC */ && \ + !defined(MCU_MK60F15) /* FMC */ && \ + !defined(MCU_MK60DZ10) /* FMC */ && \ + !defined(MCU_MK60N512VMD100) /* FMC */ && \ + !defined(MCU_MK61F12) /* FMC */ && \ + !defined(MCU_MK61F15) /* FMC */ && \ + !defined(MCU_MK61F12WS) /* FMC */ && \ + !defined(MCU_MK61F15WS) /* FMC */ && \ + !defined(MCU_MK63F12) /* FMC */ && \ + !defined(MCU_MK63F12WS) /* FMC */ && \ + !defined(MCU_MK64F12) /* FMC */ && \ + !defined(MCU_MK65F18) /* FMC */ && \ + !defined(MCU_MK65F18WS) /* FMC */ && \ + !defined(MCU_MK66F18) /* FMC */ && \ + !defined(MCU_MK70F12) /* FMC */ && \ + !defined(MCU_MK70F15) /* FMC */ && \ + !defined(MCU_MK70F12WS) /* FMC */ && \ + !defined(MCU_MK70F15WS) /* FMC */ && \ + !defined(MCU_MKV31F12810) /* FMC */ && \ + !defined(MCU_MKV31F25612) /* FMC */ && \ + !defined(MCU_MKV31F51212) /* FMC */ && \ + !defined(MCU_MKW21D5) /* FMC */ && \ + !defined(MCU_MKW21D5WS) /* FMC */ && \ + !defined(MCU_MKW22D5) /* FMC */ && \ + !defined(MCU_MKW22D5WS) /* FMC */ && \ + !defined(MCU_MKW24D5) /* FMC */ && \ + !defined(MCU_MKW24D5WS) /* FMC */ && \ + !defined(MCU_PCK20L4) /* FMC */ + // Unsupported MCU is active + #error FMC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Master acces protection constants. */ +#define FMC_PDD_NO_ACCESS 0U /**< No access may be performed by master */ +#define FMC_PDD_READ_ONLY_ACCESS 0x1U /**< Only read accesses may be performed by master */ +#define FMC_PDD_WRITE_ONLY_ACCESS 0x2U /**< Only write accesses may be performed by master */ +#define FMC_PDD_READ_AND_WRITE_ACCESS 0x3U /**< Read and write accesses may be performed by master */ + +/* Wait state required to access the flash memory constants. */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_1 0U /**< 1 wait state required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_2 0x1U /**< 2 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_3 0x2U /**< 3 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_4 0x3U /**< 4 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_5 0x4U /**< 5 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_6 0x5U /**< 6 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_7 0x6U /**< 7 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_8 0x7U /**< 8 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_9 0x8U /**< 9 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_10 0x9U /**< 10 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_11 0xAU /**< 11 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_12 0xBU /**< 12 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_13 0xCU /**< 13 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_14 0xDU /**< 14 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_15 0xEU /**< 15 wait states required to access the flash memory */ +#define FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_16 0xFU /**< 16 wait states required to access the flash memory */ + +/* Cache lock way constants. */ +#define FMC_PDD_CACHE_LOCK_WAY_0 0x1U /**< Cache lock way 0 */ +#define FMC_PDD_CACHE_LOCK_WAY_1 0x2U /**< Cache lock way 1 */ +#define FMC_PDD_CACHE_LOCK_WAY_2 0x4U /**< Cache lock way 2 */ +#define FMC_PDD_CACHE_LOCK_WAY_3 0x8U /**< Cache lock way 3 */ +#define FMC_PDD_CACHE_LOCK_WAY_ALL 0xFU /**< Cache lock all ways */ + +/* Invalide flash cache way mask constants. */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_0 0x100000U /**< Cache invalidate way 0 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_1 0x200000U /**< Cache invalidate way 1 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_2 0x400000U /**< Cache invalidate way 2 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_3 0x800000U /**< Cache invalidate way 3 mask */ +#define FMC_PDD_CACHE_INVALIDATE_WAY_ALL 0xF00000U /**< Cache invalidate all ways mask */ + +/* Memory width constants. */ +#define FMC_PDD_MEMORY_WIDTH_32BITS 0U /**< Memory width 32 bits constant */ +#define FMC_PDD_MEMORY_WIDTH_64BITS 0x20000U /**< Memory width 64 bits constant */ + +/* Cache replacement control constants */ +#define FMC_PDD_LRU_REPLACEMENT_FOR_ALL_4_WAYS 0U /**< LRU replacement algorithm per set across all four ways */ +#define FMC_PDD_LRU_WITH_01_IFETCHES_23_DATA_WAYS 0x40U /**< Independent LRU with ways [0-1] for ifetches, [2-3] for data */ +#define FMC_PDD_LRU_WITH_02_IFETCHES_3_DATA_WAYS 0x60U /**< Independent LRU with ways [0-2] for ifetches, [3] for data */ + + +/* ---------------------------------------------------------------------------- + -- InvalidateFlashCache + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR, FMC_PFB01CR + * (depending on the peripheral). + * @par Example: + * @code + * FMC_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ + #define FMC_PDD_InvalidateFlashCache(PeripheralBase) ( \ + FMC_PFB01CR_REG(PeripheralBase) |= \ + (uint32)(FMC_PFB01CR_CINV_WAY_MASK | FMC_PFB01CR_S_B_INV_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR, FMC_PFB01CR + * (depending on the peripheral). + * @par Example: + * @code + * FMC_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ + #define FMC_PDD_InvalidateFlashCache(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) |= \ + (uint32)(FMC_PFB0CR_CINV_WAY_MASK | FMC_PFB0CR_S_B_INV_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableMaster7Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 7 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 7 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster7Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster7Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M7PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M7PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster6Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 6 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 6 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster6Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster6Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M6PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M6PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster5Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 5 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 5 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster5Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster5Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M5PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M5PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster4Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 4 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 4 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster4Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster4Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M4PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M4PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster3Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 3 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 3 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster3Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster3Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M3PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M3PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster2Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 2 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 2 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster2Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster2Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M2PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M2PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster1Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 1 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 1 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster1Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster1Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M1PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M1PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMaster0Prefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables master 0 prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master 0 prefetch. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_EnableMaster0Prefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableMaster0Prefetch(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FMC_PFAPR_REG(PeripheralBase) |= \ + FMC_PFAPR_M0PFD_MASK) : ( \ + FMC_PFAPR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FMC_PFAPR_M0PFD_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster7AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 7 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster7AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster7AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M7AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M7AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster6AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 6 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster6AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster6AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M6AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M6AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster5AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 5 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster5AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster5AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M5AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M5AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster4AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 4 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster4AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster4AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M4AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M4AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster3AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 3 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster3AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster3AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M3AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M3AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster2AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 2 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster2AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster2AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M2AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M2AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster1AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 1 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster1AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster1AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M1AP_MASK))) | ( \ + (uint32)((uint32)(Value) << FMC_PFAPR_M1AP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaster0AccessProtection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets read and write control to the flash memory on the logical master + * number of the requesting crossbar switch master. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Master 0 acces protection value. The user should use one from + * the enumerated values. This parameter is of "Master acces protection + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_SetMaster0AccessProtection(_BASE_PTR, + * FMC_PDD_NO_ACCESS); + * @endcode + */ +#define FMC_PDD_SetMaster0AccessProtection(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFAPR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFAPR_M0AP_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashAccessProtectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash access protection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadFlashAccessProtectionReg(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_ReadFlashAccessProtectionReg(PeripheralBase) ( \ + FMC_PFAPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashAccessProtectionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash access + * protection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash access protection register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFAPR. + * @par Example: + * @code + * FMC_PDD_WriteFlashAccessProtectionReg(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_WriteFlashAccessProtectionReg(PeripheralBase, Value) ( \ + FMC_PFAPR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadWaitStateControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the wait state control value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint8 result = FMC_PDD_GetReadWaitStateControl(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetReadWaitStateControl(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_B0RWSC_MASK)) >> ( \ + FMC_PFB0CR_B0RWSC_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCacheLockWayMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the cache lock way defined by mas parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Cache lock way mask. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_SetCacheLockWayMask(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_SetCacheLockWayMask(PeripheralBase, Mask) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FMC_PFB0CR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FMC_PFB0CR_CLCK_WAY_MASK)))) | ( \ + (uint32)((uint32)(Mask) << FMC_PFB0CR_CLCK_WAY_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCacheLockWay + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the cache lock way mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint8 result = FMC_PDD_GetCacheLockWay(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetCacheLockWay(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_CLCK_WAY_MASK)) >> ( \ + FMC_PFB0CR_CLCK_WAY_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalideFlashCacheWay + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalide flash cache way requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of invalide flash cache way. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_InvalideFlashCacheWay(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_InvalideFlashCacheWay(PeripheralBase, Mask) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FMC_PFB0CR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FMC_PFB0CR_CINV_WAY_MASK)))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalidePrefetchSpeculationBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalidate (clear) speculation buffer and single entry buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_InvalidePrefetchSpeculationBuffer(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_InvalidePrefetchSpeculationBuffer(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) |= \ + FMC_PFB0CR_S_B_INV_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMemoryWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the memory width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Memory width constants." type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint32 result = FMC_PDD_GetMemoryWidth(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_GetMemoryWidth(PeripheralBase) ( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & FMC_PFB0CR_B0MW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCacheReplacementControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the cache replacement control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Control Cache replacement control value. The user should use one from + * the enumerated values. This parameter is of "Cache replacement control + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_SetCacheReplacementControl(_BASE_PTR, + * FMC_PDD_LRU_REPLACEMENT_FOR_ALL_4_WAYS); + * @endcode + */ +#define FMC_PDD_SetCacheReplacementControl(PeripheralBase, Control) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_CRC_MASK))) | ( \ + (uint32)(Control))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDataCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a data cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of data cache request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableDataCache(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableDataCache(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0DCE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0DCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInstructionCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a instruction cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of instruction cache request. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableInstructionCache(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableInstructionCache(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0ICE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0ICE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDataPrefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a data prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of data prefetch request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableDataPrefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableDataPrefetch(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0DPE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0DPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInstructionPrefetch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a instruction prefetch. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of instruction prefetch request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableInstructionPrefetch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableInstructionPrefetch(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0IPE_MASK))) | ( \ + (uint32)((uint32)(State) << FMC_PFB0CR_B0IPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSingleEntryBuffer + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a single entry buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of single entry buffer request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_EnableSingleEntryBuffer(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FMC_PDD_EnableSingleEntryBuffer(PeripheralBase, State) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FMC_PFB0CR_REG(PeripheralBase) & (uint32)(~(uint32)FMC_PFB0CR_B0SEBE_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * uint32 result = FMC_PDD_ReadFlashControlReg(_BASE_PTR); + * @endcode + */ +#define FMC_PDD_ReadFlashControlReg(PeripheralBase) ( \ + FMC_PFB0CR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FMC_PFB0CR. + * @par Example: + * @code + * FMC_PDD_WriteFlashControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FMC_PDD_WriteFlashControlReg(PeripheralBase, Value) ( \ + FMC_PFB0CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheTagStorageWaySetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache tag way and set storage register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache tag storage way index. This parameter is of index type. + * @param SetIdx Cache tag storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TAGVD[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheTagStorageWaySetReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheTagStorageWaySetReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_TAGVD_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheTagStorageWaySetReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache tag way + * and set storage register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache tag storage way index. This parameter is of index type. + * @param SetIdx Cache tag storage set index. This parameter is of index type. + * @param Value Value to be written to the cache tag way and set storage + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TAGVD[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheTagStorageWaySetReg(_BASE_PTR, periphID, + * periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheTagStorageWaySetReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_TAGVD_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheDataStorageWaySetUpperWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache data way and set storage upper word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DATA_U[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheDataStorageWaySetUpperWordReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheDataStorageWaySetUpperWordReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_DATA_U_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheDataStorageWaySetUpperWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache data way + * and set storage upper word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @param Value Value to be written to the cache data way and set storage upper + * word register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATA_U[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheDataStorageWaySetUpperWordReg(_BASE_PTR, + * periphID, periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheDataStorageWaySetUpperWordReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_DATA_U_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCacheDataStorageWaySetLowerWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads cache data way and set storage lower word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: DATA_L[WayIdx][SetIdx]. + * @par Example: + * @code + * uint32 result = + * FMC_PDD_ReadCacheDataStorageWaySetLowerWordReg(_BASE_PTR, periphID, periphID); + * @endcode + */ +#define FMC_PDD_ReadCacheDataStorageWaySetLowerWordReg(PeripheralBase, WayIdx, SetIdx) ( \ + FMC_DATA_L_REG(PeripheralBase,(WayIdx),(SetIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCacheDataStorageWaySetLowerWordReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into cache data way + * and set storage lower word register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param WayIdx Cache data storage way index. This parameter is of index type. + * @param SetIdx Cache data storage set index. This parameter is of index type. + * @param Value Value to be written to the cache data way and set storage lower + * word register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: DATA_L[WayIdx][SetIdx]. + * @par Example: + * @code + * FMC_PDD_WriteCacheDataStorageWaySetLowerWordReg(_BASE_PTR, + * periphID, periphID, 1); + * @endcode + */ +#define FMC_PDD_WriteCacheDataStorageWaySetLowerWordReg(PeripheralBase, WayIdx, SetIdx, Value) ( \ + FMC_DATA_L_REG(PeripheralBase,(WayIdx),(SetIdx)) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(FMC_PDD_H_) */ + +/* FMC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h new file mode 100644 index 0000000..029c053 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTFL_PDD.h @@ -0,0 +1,3215 @@ +/* + PDD layer implementation for peripheral type FTFL + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FTFL_PDD_H_) +#define FTFL_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FTFL PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FTFL */ && \ + !defined(MCU_MK10D5) /* FTFL */ && \ + !defined(MCU_MK10D7) /* FTFL */ && \ + !defined(MCU_MK10DZ10) /* FTFL */ && \ + !defined(MCU_MK11D5) /* FTFL */ && \ + !defined(MCU_MK11D5WS) /* FTFL */ && \ + !defined(MCU_MK12D5) /* FTFL */ && \ + !defined(MCU_MK20D10) /* FTFL */ && \ + !defined(MCU_MK20D5) /* FTFL */ && \ + !defined(MCU_MK20D7) /* FTFL */ && \ + !defined(MCU_MK20DZ10) /* FTFL */ && \ + !defined(MCU_MK21D5) /* FTFL */ && \ + !defined(MCU_MK21D5WS) /* FTFL */ && \ + !defined(MCU_MK22D5) /* FTFL */ && \ + !defined(MCU_MK30D10) /* FTFL */ && \ + !defined(MCU_MK30D7) /* FTFL */ && \ + !defined(MCU_MK30DZ10) /* FTFL */ && \ + !defined(MCU_MK40D10) /* FTFL */ && \ + !defined(MCU_MK40D7) /* FTFL */ && \ + !defined(MCU_MK40DZ10) /* FTFL */ && \ + !defined(MCU_MK40X256VMD100) /* FTFL */ && \ + !defined(MCU_MK50D10) /* FTFL */ && \ + !defined(MCU_MK50D7) /* FTFL */ && \ + !defined(MCU_MK50DZ10) /* FTFL */ && \ + !defined(MCU_MK51D10) /* FTFL */ && \ + !defined(MCU_MK51D7) /* FTFL */ && \ + !defined(MCU_MK51DZ10) /* FTFL */ && \ + !defined(MCU_MK52D10) /* FTFL */ && \ + !defined(MCU_MK52DZ10) /* FTFL */ && \ + !defined(MCU_MK53D10) /* FTFL */ && \ + !defined(MCU_MK53DZ10) /* FTFL */ && \ + !defined(MCU_MK60D10) /* FTFL */ && \ + !defined(MCU_MK60DZ10) /* FTFL */ && \ + !defined(MCU_MK60N512VMD100) /* FTFL */ && \ + !defined(MCU_MKW21D5) /* FTFL */ && \ + !defined(MCU_MKW21D5WS) /* FTFL */ && \ + !defined(MCU_MKW22D5) /* FTFL */ && \ + !defined(MCU_MKW22D5WS) /* FTFL */ && \ + !defined(MCU_MKW24D5) /* FTFL */ && \ + !defined(MCU_MKW24D5WS) /* FTFL */ && \ + !defined(MCU_PCK20L4) /* FTFL */ + // Unsupported MCU is active + #error FTFL PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* ClearFlags constants */ +#define FTFL_PDD_COMMAND_COMPLETE FTFL_FSTAT_CCIF_MASK /**< Command complete flag mask */ +#define FTFL_PDD_READ_COLLISION_ERROR FTFL_FSTAT_RDCOLERR_MASK /**< Read collision error flag mask */ +#define FTFL_PDD_ACCESS_ERROR FTFL_FSTAT_ACCERR_MASK /**< Access error flag mask */ +#define FTFL_PDD_PROTECTION_VIOLATION FTFL_FSTAT_FPVIOL_MASK /**< Protection violation flag mask */ +#define FTFL_PDD_COMMAND_COMPLETION_STATUS FTFL_FSTAT_MGSTAT0_MASK /**< Command completion ststus flag mask */ + +/* EnableInterrupts;, DisableInterrupts constants */ +#define FTFL_PDD_COMMAND_COMPLETE_INT FTFL_FCNFG_CCIE_MASK /**< Command complete interrupt mask */ +#define FTFL_PDD_READ_COLLISION_ERROR_INT FTFL_FCNFG_RDCOLLIE_MASK /**< Read collision error interrupt mask */ + +/* SetFCCOBCommand constants */ +#define FTFL_PDD_READ_1S_BLOCK 0U /**< Read 1s Block command value */ +#define FTFL_PDD_READ_1S_SECTION 0x1U /**< Read 1s Section command value */ +#define FTFL_PDD_PROGRAM_CHECK 0x2U /**< Program Check command value */ +#define FTFL_PDD_READ_RESOURCE 0x3U /**< Read Resource command value */ +#define FTFL_PDD_PROGRAM_LONGWORD 0x6U /**< Program Longword command value */ +#define FTFL_PDD_ERASE_FLASH_BLOCK 0x8U /**< Erase Flash Block command value */ +#define FTFL_PDD_ERASE_FLASH_SECTOR 0x9U /**< Erase Flash Sector command value */ +#define FTFL_PDD_PROGRAM_SECTION 0xBU /**< Program Section command value */ +#define FTFL_PDD_READ_1S_ALL_BLOCKS 0x40U /**< Read 1s All Blocks command value */ +#define FTFL_PDD_PDD_READ_ONCE 0x41U /**< Read Once command value */ +#define FTFL_PDD_PROGRAM_ONCE 0x43U /**< Program Once command value */ +#define FTFL_PDD_ERASE_ALL_BLOCKS 0x44U /**< Erase All Blocks command value */ +#define FTFL_PDD_VERIFY_BACKDOOR_ACCESS_KEY 0x45U /**< Verify Backdoor Access Key command value */ +#define FTFL_PDD_PROGRAM_PARTITION 0x80U /**< Program Partition command value */ +#define FTFL_PDD_SET_EERAM_FUCTION 0x81U /**< Set FlexRAM Function command value */ + +/* Margin level constants */ +#define FTFL_PDD_READ_MARGIN_LEVEL_NORMAL 0U /**< Normal read level constant */ +#define FTFL_PDD_READ_MARGIN_LEVEL_USER 0x1U /**< User read level constant */ +#define FTFL_PDD_READ_MARGIN_LEVEL_FACTORY 0x2U /**< Factory read level constant */ + +/* Read resource command resource code constants */ +#define FTFL_PDD_RESOURCE_IFR 0U /**< IFR */ +#define FTFL_PDD_RESOURCE_VERSION_ID 0x1U /**< Version ID */ + +/* EEPROM size constants */ +#define FTFL_PDD_EEPROM_DATA_SIZE_0_B 0xFU /**< No EEPROM */ +#define FTFL_PDD_EEPROM_DATA_SIZE_32_B 0x9U /**< 32 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_64_B 0x8U /**< 64 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_128_B 0x7U /**< 128 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_256_B 0x6U /**< 256 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_512_B 0x5U /**< 512 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_1024_B 0x4U /**< 1024 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_SIZE_2048_B 0x3U /**< 2048 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_4096_B 0x2U /**< 4096 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_8192_B 0x1U /**< 8192 bytes of EEPROM data */ +#define FTFL_PDD_EEPROM_DATA_SIZE_16384_B 0U /**< 16384 bytes of EEPROM data */ + +/* EEPROM backup size constants */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_0_KB 0U /**< No EEPROM */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_8_KB 0x1U /**< 8 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_16_KB 0x2U /**< 16 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_32_KB 0x3U /**< 32 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_64_KB 0x4U /**< 64 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_128_KB 0x5U /**< 128 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_256_KB 0x6U /**< 256 KB of EEPROM backup */ +#define FTFL_PDD_EEPROM_BACKUP_SIZE_512_KB 0x7U /**< 512 KB of EEPROM backup */ +#define FTFL_PDD_DATA_FLASH_SIZE_0_KB 0x8U /**< No data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_8_KB 0x9U /**< 8 KB of data falsh */ +#define FTFL_PDD_EDATA_FLASH_SIZE_16_KB 0xAU /**< 16 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_32_KB 0xBU /**< 32 KB of data falshp */ +#define FTFL_PDD_DATA_FLASH_SIZE_64_KB 0xCU /**< 64 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_128_KB 0xDU /**< 128 KB of data falsh */ +#define FTFL_PDD_EDATA_FLASH_SIZE_256_KB 0xEU /**< 256 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_512_KB 0xFU /**< 512 KB of data falsh */ +#define FTFL_PDD_DATA_FLASH_SIZE_MAX 0xFU /**< No EEPROM backup data falsh only */ + +/* FlexRAM function constants */ +#define FTFL_PDD_FLEXRAM_AS_RAM 0xFFU /**< Make FlexRAM available as RAM */ +#define FTFL_PDD_FLEXRAM_AS_EEPROM 0U /**< Make FlexRAM available for EEPROM */ + +/* BackDoorKey constants */ +#define FTFL_PDD_BACKDOOR_KEY_ENABLED 0U /**< Backdoor key enable constant */ +#define FTFL_PDD_BACKDOOR_KEY_DISABLED 0x1U /**< Backdoor key disable constant */ + +/* Mass erase constants */ +#define FTFL_PDD_MASS_ERASE_ENABLED 0U /**< Mass erase enable constant */ +#define FTFL_PDD_MASS_ERASE_DISABLED 0x1U /**< Mass erase disable constant */ + +/* Factory access constants */ +#define FTFL_PDD_FACTORY_ACCESS_GRANTED 0U /**< Factory access granted constant */ +#define FTFL_PDD_FACTORY_ACCESS_DENIED 0x1U /**< Factory access denied constant */ + +/* Security state constants */ +#define FTFL_PDD_UNSECURED 0U /**< Unsecure constant */ +#define FTFL_PDD_SECURED 0x1U /**< Secure constant */ + +/* FlashProtection constants */ +#define FTFL_PDD_UNPROTECTED 0U /**< Unprotect constant */ +#define FTFL_PDD_PROTECTED 0x1U /**< Protect constant */ + + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "ClearFlags constants" for processing return + * value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadStatusReg(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Flash status register. Use constants from + * group "ClearFlags constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_WriteStatusReg(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE); + * @endcode + */ +#define FTFL_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCommandCompleteFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Command complete flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearCommandCompleteFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearCommandCompleteFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_CCIF_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearReadCollisionErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Read collision error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearReadCollisionErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearReadCollisionErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_RDCOLERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAccessErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Access error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearAccessErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearAccessErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_ACCERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearProtectionViolationErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Protection violation error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearProtectionViolationErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearProtectionViolationErrorFlag(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) | FTFL_FSTAT_FPVIOL_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_ACCERR_MASK)) & (( \ + (uint8)(~(uint8)FTFL_FSTAT_RDCOLERR_MASK)) & ( \ + (uint8)(~(uint8)FTFL_FSTAT_CCIF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- LaunchCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts new command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_LaunchCommand(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_LaunchCommand(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + 0x80U \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Flags Interrupt mask. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearFlags(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_ClearFlags(PeripheralBase, Flags) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(Flags) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetFlags(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns value of the Flash configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadConfigReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadConfigReg(PeripheralBase) ( \ + FTFL_FCNFG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Flash configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Flash configuration register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_WriteConfigReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteConfigReg(PeripheralBase, Value) ( \ + FTFL_FCNFG_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Command commplete end Read collision error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "EnableInterrupts;, + * DisableInterrupts constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_EnableInterrupts(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define FTFL_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + FTFL_FCNFG_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + FTFL_FCNFG_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(FTFL_FCNFG_CCIE_MASK | FTFL_FCNFG_RDCOLLIE_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Command commplete end Read collision error interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "EnableInterrupts;, + * DisableInterrupts constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_DisableInterrupts(_BASE_PTR, + * FTFL_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define FTFL_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + FTFL_FCNFG_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEraseAllRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the erase all request bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetEraseAllRequest(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEraseAllRequest(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_ERSAREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SuspendErasing + ---------------------------------------------------------------------------- */ + +/** + * @brief Suspends the current Erase Flash Sector command execution. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * FTFL_PDD_SuspendErasing(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_SuspendErasing(PeripheralBase) ( \ + FTFL_FCNFG_REG(PeripheralBase) |= \ + FTFL_FCNFG_ERSSUSP_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRAMReady + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Ram ready bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetRAMReady(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetRAMReady(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_RAMRDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEEEReady + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the EEE ready bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCNFG. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetEEEReady(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEEEReady(PeripheralBase) ( \ + (uint8)(FTFL_FCNFG_REG(PeripheralBase) & FTFL_FCNFG_EEERDY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSecurityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Security register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadSecurityReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadSecurityReg(PeripheralBase) ( \ + FTFL_FSEC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBackdoorEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FTFL_PDD_BACKDOOR_KEY_ENABLED if backdoor key + * access is enabled else returns the FTFL_PDD_BACKDOOR_KEY_DISABLED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "BackDoorKey constants" type. The value is cast to + * "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetBackdoorEnable(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetBackdoorEnable(PeripheralBase) ( \ + (( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_KEYEN_MASK)) >> ( \ + FTFL_FSEC_KEYEN_SHIFT))) == ( \ + 0x2U)) ? ( \ + FTFL_PDD_BACKDOOR_KEY_ENABLED) : ( \ + FTFL_PDD_BACKDOOR_KEY_DISABLED) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMassEraseEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant MASS_ERASE_ENABLED if mass erase is enabled else + * returns the MASS_ERASE_DISABLED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Mass erase constants" type. The value is cast to + * "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetMassEraseEnable(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetMassEraseEnable(PeripheralBase) ( \ + (( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_MEEN_MASK)) >> ( \ + FTFL_FSEC_MEEN_SHIFT))) == ( \ + 0x2U)) ? ( \ + FTFL_PDD_MASS_ERASE_DISABLED) : ( \ + FTFL_PDD_MASS_ERASE_ENABLED) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFactoryAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FACTORY_ACCESS_GRANTED if access to the flash + * memory contents is enabled else returns the FACTORY_ACCESS_DENIED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Factory access constants" type. The value is cast + * to "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetFactoryAccess(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetFactoryAccess(PeripheralBase) ( \ + ((uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_FSLACC_MASK) == 0U) ? ( \ + FTFL_PDD_FACTORY_ACCESS_GRANTED) : ((( \ + (uint8)(( \ + (uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_FSLACC_MASK)) >> ( \ + FTFL_FSEC_FSLACC_SHIFT))) == ( \ + 0x3U)) ? ( \ + FTFL_PDD_FACTORY_ACCESS_GRANTED) : ( \ + FTFL_PDD_FACTORY_ACCESS_DENIED) \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSecurityState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the constant FTFL_PDD_SECURED if MCU is in secure state else + * returns the FTFL_PDD_UNSECURED constant. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Security state constants" type. The value is cast + * to "uint16". + * @remarks The macro accesses the following registers: FTFL_FSEC. + * @par Example: + * @code + * uint16 result = FTFL_PDD_GetSecurityState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetSecurityState(PeripheralBase) ( \ + ((uint8)(FTFL_FSEC_REG(PeripheralBase) & FTFL_FSEC_SEC_MASK) == 0x2U) ? ( \ + FTFL_PDD_UNSECURED) : ( \ + FTFL_PDD_SECURED) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOptionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Optional register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FOPT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadOptionReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadOptionReg(PeripheralBase) ( \ + FTFL_FOPT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB0Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB0Reg(PeripheralBase) ( \ + FTFL_FCCOB0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB1Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB1Reg(PeripheralBase) ( \ + FTFL_FCCOB1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB2. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB2Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB2Reg(PeripheralBase) ( \ + FTFL_FCCOB2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB3. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB3Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB3Reg(PeripheralBase) ( \ + FTFL_FCCOB3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB4Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB4Reg(PeripheralBase) ( \ + FTFL_FCCOB4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB5Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB5Reg(PeripheralBase) ( \ + FTFL_FCCOB5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB6Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB6Reg(PeripheralBase) ( \ + FTFL_FCCOB6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB7Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB7Reg(PeripheralBase) ( \ + FTFL_FCCOB7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 8. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB8Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB8Reg(PeripheralBase) ( \ + FTFL_FCCOB8_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOB9Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register 9. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOB9Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOB9Reg(PeripheralBase) ( \ + FTFL_FCCOB9_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOBAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register A. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOBAReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOBAReg(PeripheralBase) ( \ + FTFL_FCCOBA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFCCOBBReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Common command object register B. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * uint8 result = FTFL_PDD_ReadFCCOBBReg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadFCCOBBReg(PeripheralBase) ( \ + FTFL_FCCOBB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB0 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB0Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB0Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB1 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB1Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB1Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB2 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB2. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB2Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB2Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB3register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB3 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB3. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB3Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB3Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB4 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB4Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB4Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB5 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB5Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB5Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB6 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB6Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB6Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB7 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB7Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB7Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB8 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB8Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB8Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOB9Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB9 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOB9 register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOB9Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOB9Reg(PeripheralBase, Value) ( \ + FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBAReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOBA register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOBA register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBAReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBAReg(PeripheralBase, Value) ( \ + FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBBReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOBB register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the FCCOBB register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBBReg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBBReg(PeripheralBase, Value) ( \ + FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFCCOBCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB Command register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Command Value written to the FCCOB Command register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * FTFL_PDD_SetFCCOBCommand(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_SetFCCOBCommand(PeripheralBase, Command) ( \ + FTFL_FCCOB0_REG(PeripheralBase) = \ + (uint8)(Command) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFCCOBAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the value to the FCCOB Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Value written to the FCCOB Address register. This parameter is + * a 24-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB3, + * FTFL_FCCOB2, FTFL_FCCOB1 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_SetFCCOBAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_SetFCCOBAddress(PeripheralBase, Address) ( \ + (FTFL_FCCOB3_REG(PeripheralBase) = \ + (uint8)(Address)), \ + ((FTFL_FCCOB2_REG(PeripheralBase) = \ + (uint8)((uint32)(Address) >> 8U)), \ + (FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)((uint32)(Address) >> 16U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 0 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData0(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData0(PeripheralBase, Data) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 1 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData1(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData1(PeripheralBase, Data) ( \ + FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 2 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData2(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData2(PeripheralBase, Data) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 3 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB7. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData3(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData3(PeripheralBase, Data) ( \ + FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 4 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData4(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData4(PeripheralBase, Data) ( \ + FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData5 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 5 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB9. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData5(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData5(PeripheralBase, Data) ( \ + FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData6 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 6 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBA. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData6(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData6(PeripheralBase, Data) ( \ + FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBData7 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data byte 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the FCCOB Data 7 register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOBB. + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBData7(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBData7(PeripheralBase, Data) ( \ + FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBFirstLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets first longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7 (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBFirstLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBFirstLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFCCOBSecondLongWordData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets second longword data to be programmed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Flash in the CPU native endian format. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB8, + * FTFL_FCCOB9, FTFL_FCCOBA, FTFL_FCCOBB (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_WriteFCCOBSecondLongWordData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteFCCOBSecondLongWordData(PeripheralBase, Data) ( \ + (FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 24U)), \ + ((FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 16U)), \ + ((FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)((uint32)(Data) >> 8U)), \ + (FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Data)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets program Flash protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions Protected regions. This parameter is a 32-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * FTFL_PDD_SetPFlashProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetPFlashProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + *(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)) |= \ + (uint32)(Regions)) : ( \ + *(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)) &= \ + (uint32)(~(uint32)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns program falsh protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_GetPFlashProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetPFlashProtectionState(PeripheralBase) ( \ + (uint32)(~(*(uint32 *)(void *)&(FTFL_FPROT3_REG(PeripheralBase)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT0. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection0Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection0Reg(PeripheralBase) ( \ + FTFL_FPROT0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 0 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT0. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection0Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection0Reg(PeripheralBase, Value) ( \ + FTFL_FPROT0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT1. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection1Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection1Reg(PeripheralBase) ( \ + FTFL_FPROT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 1 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT1. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection1Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection1Reg(PeripheralBase, Value) ( \ + FTFL_FPROT1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT2. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection2Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection2Reg(PeripheralBase) ( \ + FTFL_FPROT2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 2 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT2. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection2Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection2Reg(PeripheralBase, Value) ( \ + FTFL_FPROT2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadProgramFlashProtection3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads program flash protection 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_ReadProgramFlashProtection3Reg(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ReadProgramFlashProtection3Reg(PeripheralBase) ( \ + FTFL_FPROT3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProgramFlashProtection3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into program flash + * protection 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the program flash protection 3 register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FPROT3. + * @par Example: + * @code + * FTFL_PDD_WriteProgramFlashProtection3Reg(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_WriteProgramFlashProtection3Reg(PeripheralBase, Value) ( \ + FTFL_FPROT3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns all error flags in the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetErrorFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetErrorFlags(PeripheralBase) ( \ + (uint8)(( \ + FTFL_FSTAT_REG(PeripheralBase)) & ( \ + (uint8)(( \ + FTFL_FSTAT_RDCOLERR_MASK) | (( \ + FTFL_FSTAT_ACCERR_MASK) | (( \ + FTFL_FSTAT_FPVIOL_MASK) | ( \ + FTFL_FSTAT_MGSTAT0_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear all error flags in the Flash status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_ClearErrorFlags(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_ClearErrorFlags(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + (uint8)(FTFL_FSTAT_RDCOLERR_MASK | (FTFL_FSTAT_ACCERR_MASK | FTFL_FSTAT_FPVIOL_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCompleteFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Command complete" flag is set otherwise + * returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetCmdCompleteFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCompleteFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_CCIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetReadCollisionErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Read collision error" flag is set + * otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetReadCollisionErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetReadCollisionErrorFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_RDCOLERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAccessErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Access error" flag is set otherwise + * returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetAccessErrorFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetAccessErrorFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_ACCERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetProtectionViolationFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Protection violationr" flag is set + * otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetProtectionViolationFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetProtectionViolationFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_FPVIOL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCompleteStatusFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non-zero value if the "Memory controller command completion + * status" flag is set otherwise returns zero. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetCmdCompleteStatusFlag(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCompleteStatusFlag(PeripheralBase) ( \ + (uint8)(FTFL_FSTAT_REG(PeripheralBase) & FTFL_FSTAT_MGSTAT0_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartCmd + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts commad execution. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FSTAT. + * @par Example: + * @code + * FTFL_PDD_StartCmd(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_StartCmd(PeripheralBase) ( \ + FTFL_FSTAT_REG(PeripheralBase) = \ + FTFL_FSTAT_CCIF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCmdCode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current command (value of the FCCOB0 register). This macro + * is common for all commands. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB0. + * @par Example: + * @code + * uint8 result = FTFL_PDD_GetCmdCode(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetCmdCode(PeripheralBase) ( \ + FTFL_FCCOB0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s block command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_Init(_BASE_PTR, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_Init(PeripheralBase, Address, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_BLOCK << 24), \ + (FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_Read1sBlock_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_BLOCK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sBlock_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB4_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sBlock_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sBlock_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sBlock_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s section command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block to be verified. This + * parameter is a 24-bit value. + * @param SectionUnitCount Number of section units to be verified. This + * parameter is a 16-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_Init(_BASE_PTR, 1, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_Init(PeripheralBase, Address, SectionUnitCount, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_SECTION << 24), \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = (SectionUnitCount << 16) | (MarginLevel << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_Read1sSection_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Address in the flash block to be verified. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_READ_1S_SECTION << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the size field of the command (value of the FCCOB4-FCC0B5 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @par Example: + * @code + * uint16 result = + * FTFL_PDD_Cmd_Read1sSection_GetSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetSize(PeripheralBase) ( \ + (uint16)((*(uint16 *)(void *)&(FTFL_FCCOB5_REG(PeripheralBase)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the size field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SectionUnitCount Number of section units to be verified. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetSize(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetSize(PeripheralBase, SectionUnitCount) ( \ + *(uint16*)&FTFL_FCCOB5_REG(PeripheralBase) = (SectionUnitCount) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sSection_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB6_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sSection_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB6 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB6. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sSection_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sSection_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program check command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be longword aligned. + * This parameter is a 24-bit value. + * @param Data Expected data. This parameter is a 32-bit value. + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_Init(_BASE_PTR, 1, 1, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_Init(PeripheralBase, Address, Data, MarginLevel) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_CHECK << 24), \ + ((FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel)), \ + *(uint32*)&FTFL_FCCOBB_REG(PeripheralBase) = Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramCheck_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be longword aligned. + * This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_CHECK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the data field of the command (FCCOB8-FCC0BB registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramCheck_GetData(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetData(PeripheralBase) ( \ + (uint32)(*(uint32 *)(void *)&FTFL_FCCOBB_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetData + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field of the command (FCCOB8-FCC0BB registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Expected data. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetData(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetData(PeripheralBase, Data) ( \ + *(uint32*)&FTFL_FCCOBB_REG(PeripheralBase) = Data \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ProgramCheck_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB4_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramCheck_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB4 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramCheck_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramCheck_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program longword command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be 32-bit aligned. This + * parameter is a 24-bit value. + * @param Data Longword to be written. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_Init(_BASE_PTR, 1, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_Init(PeripheralBase, Address, Data) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24), \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = Data \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_getAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramLongword_getAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_getAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_GetDWord + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the data field of the command (FCCOB4-FCC0B7 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_ProgramLongword_GetDWord(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_GetDWord(PeripheralBase) ( \ + (uint32)(*(uint32 *)(void *)&FTFL_FCCOB7_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramLongword_SetDWord + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data field of the command (FCCOB4-FCC0B7 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param DWord Expected data. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramLongword_SetDWord(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramLongword_SetDWord(PeripheralBase, DWord) ( \ + *(uint32*)&FTFL_FCCOB7_REG(PeripheralBase) = DWord \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase flash block command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block to be erased. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseFlashBlock_Init(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_Init(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_ERASE_FLASH_BLOCK << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_EraseFlashBlock_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseFlashBlock_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash block. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseFlashBlock_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseFlashBlock_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase flash sector command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash sector to be erased. Must be dword + * aligned. This parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseSector_Init(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_Init(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_ERASE_FLASH_SECTOR << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_GetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @par Example: + * @code + * uint32 result = + * FTFL_PDD_Cmd_EraseSector_GetAddress(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_GetAddress(PeripheralBase) ( \ + (uint32)((*(uint32 *)(void *)&(FTFL_FCCOB3_REG(PeripheralBase))) & 0xFFFFFF) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseSector_SetAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the address field of the command (FCCOB1-FCC0B3 registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Flash address in the flash sector. Must be dword aligned. This + * parameter is a 24-bit value. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseSector_SetAddress(_BASE_PTR, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseSector_SetAddress(PeripheralBase, Address) ( \ + *(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = (Address) | (FTFL_PDD_PROGRAM_LONGWORD << 24) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read 1s all blocks command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sAllBlocks_Init(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_Init(PeripheralBase, MarginLevel) ( \ + *(uint16*)&FTFL_FCCOB1_REG(PeripheralBase) = MarginLevel | (FTFL_PDD_READ_1S_ALL_BLOCKS << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_GetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns margin level field of the command (FCCOB1 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_Read1sAllBlocks_GetMarginLevel(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_GetMarginLevel(PeripheralBase) ( \ + (FTFL_FCCOB1_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_Read1sAllBlocks_SetMarginLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the margin level field of the command (FCCOB1 register). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MarginLevel Read-1 margin choice. Use constants from group "Margin + * level constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB1. + * @par Example: + * @code + * FTFL_PDD_Cmd_Read1sAllBlocks_SetMarginLevel(_BASE_PTR, + * FTFL_PDD_READ_MARGIN_LEVEL_NORMAL); + * @endcode + */ +#define FTFL_PDD_Cmd_Read1sAllBlocks_SetMarginLevel(PeripheralBase, MarginLevel) ( \ + FTFL_FCCOB1_REG(PeripheralBase) = \ + (uint8)(MarginLevel) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_EraseAllBlocks_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Erase all blocks command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_EraseAllBlocks_Init(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_EraseAllBlocks_Init(PeripheralBase) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_ERASE_ALL_BLOCKS \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ProgramPartition_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Program partition command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EepromDataSize EEPROM data size and split factor(if supported) code. + * Use constants from group "EEPROM size constants". This parameter is 8 + * bits wide. + * @param EepromBackupSize EEPROM backup size. Use constants from group "EEPROM + * backup size constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ProgramPartition_Init(_BASE_PTR, + * FTFL_PDD_EEPROM_DATA_SIZE_0_B, FTFL_PDD_EEPROM_BACKUP_SIZE_0_KB); + * @endcode + */ +#define FTFL_PDD_Cmd_ProgramPartition_Init(PeripheralBase, EepromDataSize, EepromBackupSize) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_PROGRAM_PARTITION, \ + (*(uint8*)&FTFL_FCCOB4_REG(PeripheralBase) = EepromDataSize, \ + *(uint8*)&FTFL_FCCOB5_REG(PeripheralBase) = EepromBackupSize) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Read Resource command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_ReadPartition_Init(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_Init(PeripheralBase) ( \ + *(uint8*)&FTFL_FCCOB8_REG(PeripheralBase) = 0x00, \ + (*(uint32*)&FTFL_FCCOB3_REG(PeripheralBase) = 0x00800000 | 0xFC | (FTFL_PDD_READ_RESOURCE << 24), \ + *(uint8*)&FTFL_FCCOB8_REG(PeripheralBase) = FTFL_PDD_RESOURCE_IFR) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_GetEepromDataSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB4. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ReadPartition_GetEepromDataSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_GetEepromDataSize(PeripheralBase) ( \ + FTFL_FCCOB4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_ReadPartition_GetEepromBackUpSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address field of the command (value of the FCCOB1-FCC0B3 + * registers). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FCCOB5. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_Cmd_ReadPartition_GetEepromBackUpSize(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_Cmd_ReadPartition_GetEepromBackUpSize(PeripheralBase) ( \ + FTFL_FCCOB5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_SetFlexRAMFunction_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Set FlexRAM Function command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Function FrexRam function choice. Use constants from group "FlexRAM + * function constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * FTFL_PDD_Cmd_SetFlexRAMFunction_Init(_BASE_PTR, + * FTFL_PDD_FLEXRAM_AS_RAM); + * @endcode + */ +#define FTFL_PDD_Cmd_SetFlexRAMFunction_Init(PeripheralBase, Function) ( \ + *(uint16*)&FTFL_FCCOB1_REG(PeripheralBase) = Function | (FTFL_PDD_SET_EERAM_FUCTION << 8) \ + ) + +/* ---------------------------------------------------------------------------- + -- Cmd_VerifyBackdoorAccessKey_Init + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialzes FCCOB registers for Verify Backdoor Access Key command. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Key0 Key 0. This parameter is a 8-bit value. + * @param Key1 Key 0. This parameter is a 8-bit value. + * @param Key2 Key 0. This parameter is a 8-bit value. + * @param Key3 Key 0. This parameter is a 8-bit value. + * @param Key4 Key 0. This parameter is a 8-bit value. + * @param Key5 Key 0. This parameter is a 8-bit value. + * @param Key6 Key 0. This parameter is a 8-bit value. + * @param Key7 Key 0. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FCCOB4, + * FTFL_FCCOB5, FTFL_FCCOB6, FTFL_FCCOB7, FTFL_FCCOB8, FTFL_FCCOB9, FTFL_FCCOBA, + * FTFL_FCCOBB (depending on the peripheral). + * @par Example: + * @code + * FTFL_PDD_Cmd_VerifyBackdoorAccessKey_Init(_BASE_PTR, 1, 1, + * 1, 1, 1, 1, 1, 1); + * @endcode + */ +#define FTFL_PDD_Cmd_VerifyBackdoorAccessKey_Init(PeripheralBase, Key0, Key1, Key2, Key3, Key4, Key5, Key6, Key7) ( \ + *(uint8*)&FTFL_FCCOB0_REG(PeripheralBase) = FTFL_PDD_VERIFY_BACKDOOR_ACCESS_KEY, \ + ((FTFL_FCCOB4_REG(PeripheralBase) = \ + (uint8)(Key0)), \ + ((FTFL_FCCOB5_REG(PeripheralBase) = \ + (uint8)(Key1)), \ + ((FTFL_FCCOB6_REG(PeripheralBase) = \ + (uint8)(Key2)), \ + ((FTFL_FCCOB7_REG(PeripheralBase) = \ + (uint8)(Key3)), \ + ((FTFL_FCCOB8_REG(PeripheralBase) = \ + (uint8)(Key4)), \ + ((FTFL_FCCOB9_REG(PeripheralBase) = \ + (uint8)(Key5)), \ + ((FTFL_FCCOBA_REG(PeripheralBase) = \ + (uint8)(Key6)), \ + (FTFL_FCCOBB_REG(PeripheralBase) = \ + (uint8)(Key7))))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data Flash protection state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions FTFL_PDD_PROTECTED or FTFL_PDD_UNPROTECTED. This parameter is + * a 8-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FDPROT. + * @par Example: + * @code + * FTFL_PDD_SetDFlashProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetDFlashProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + FTFL_FDPROT_REG(PeripheralBase) |= \ + (uint8)(Regions)) : ( \ + FTFL_FDPROT_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDFlashProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the returned value represent 1/8 of the Data FLASH memory. + * If the bit is set the region is protected else the region is unprotected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FDPROT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetDFlashProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetDFlashProtectionState(PeripheralBase) ( \ + (uint8)(~(uint8)FTFL_FDPROT_REG(PeripheralBase)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetEERAMProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the Region parameter represent 1/8 of the EERPROM memory. + * To change the protection state of the region(s) select requested regions + * (Region param) and set new state (State param). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Regions Protected regions. This parameter is a 8-bit value. + * @param State Requested state. This parameter is of "FlashProtection + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTFL_FEPROT. + * @par Example: + * @code + * FTFL_PDD_SetEERAMProtectionState(_BASE_PTR, 1, + * FTFL_PDD_UNPROTECTED); + * @endcode + */ +#define FTFL_PDD_SetEERAMProtectionState(PeripheralBase, Regions, State) ( \ + ((State) == FTFL_PDD_UNPROTECTED) ? ( \ + FTFL_FEPROT_REG(PeripheralBase) |= \ + (uint8)(Regions)) : ( \ + FTFL_FEPROT_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Regions))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEERAMProtectionState + ---------------------------------------------------------------------------- */ + +/** + * @brief Each bit of the returned value represent 1/8 of the EERPROM memory. If + * the bit is set the region is protected else the region is unprotected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: FTFL_FEPROT. + * @par Example: + * @code + * uint8 result = + * FTFL_PDD_GetEERAMProtectionState(_BASE_PTR); + * @endcode + */ +#define FTFL_PDD_GetEERAMProtectionState(PeripheralBase) ( \ + (uint8)(~(uint8)FTFL_FEPROT_REG(PeripheralBase)) \ + ) +#endif /* #if defined(FTFL_PDD_H_) */ + +/* FTFL_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h new file mode 100644 index 0000000..242a599 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/FTM_PDD.h @@ -0,0 +1,5072 @@ +/* + PDD layer implementation for peripheral type FTM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(FTM_PDD_H_) +#define FTM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error FTM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK10D5) /* FTM0, FTM1 */ && \ + !defined(MCU_MK10D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK10F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK10DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK11D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK11D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK12D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20D5) /* FTM0, FTM1 */ && \ + !defined(MCU_MK20D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK20F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK20DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK21F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK21F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK22D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F12810) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK22F25612) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK22F51212) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK24F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK30D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK30D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK30DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK40X256VMD100) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK50DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51D7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK51DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK52D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK52DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK53D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK53DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60D10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK60F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK60DZ10) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK60N512VMD100) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MK61F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK61F15WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK63F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK63F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK64F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK65F18) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK65F18WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK66F18) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F12) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F15) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F12WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MK70F15WS) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MKE02Z2) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE02Z4) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_SKEAZN642) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE04Z1284) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKE04Z4) /* FTM0, FTM2 */ && \ + !defined(MCU_SKEAZN84) /* FTM0, FTM2 */ && \ + !defined(MCU_MKE06Z4) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV10Z7) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F12810) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F25612) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKV31F51212) /* FTM0, FTM1, FTM2, FTM3 */ && \ + !defined(MCU_MKW21D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW21D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW22D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW22D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW24D5) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_MKW24D5WS) /* FTM0, FTM1, FTM2 */ && \ + !defined(MCU_PCK20L4) /* FTM0, FTM1 */ && \ + !defined(MCU_SKEAZ1284) /* FTM0, FTM1, FTM2 */ + // Unsupported MCU is active + #error FTM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* FTM channel constants */ +#define FTM_PDD_CHANNEL_0 0U /**< 0 */ +#define FTM_PDD_CHANNEL_1 0x1U /**< 1 */ +#define FTM_PDD_CHANNEL_2 0x2U /**< 2 */ +#define FTM_PDD_CHANNEL_3 0x3U /**< 3 */ +#define FTM_PDD_CHANNEL_4 0x4U /**< 4 */ +#define FTM_PDD_CHANNEL_5 0x5U /**< 5 */ +#define FTM_PDD_CHANNEL_6 0x6U /**< 6 */ +#define FTM_PDD_CHANNEL_7 0x7U /**< 7 */ + +/* Prescaler constants */ +#define FTM_PDD_DIVIDE_1 0U /**< 1 */ +#define FTM_PDD_DIVIDE_2 0x1U /**< 2 */ +#define FTM_PDD_DIVIDE_4 0x2U /**< 4 */ +#define FTM_PDD_DIVIDE_8 0x3U /**< 8 */ +#define FTM_PDD_DIVIDE_16 0x4U /**< 16 */ +#define FTM_PDD_DIVIDE_32 0x5U /**< 32 */ +#define FTM_PDD_DIVIDE_64 0x6U /**< 64 */ +#define FTM_PDD_DIVIDE_128 0x7U /**< 128 */ + +/* PWM aligned mode constants */ +#define FTM_PDD_EDGE_ALIGNED 0U /**< Edge aligned */ +#define FTM_PDD_CENTER_ALIGNED FTM_SC_CPWMS_MASK /**< Center aligned */ + +/* Interrupt flag masks for ClearChannelFlag */ +#define FTM_PDD_FLAG_0 0x1U /**< 0 */ +#define FTM_PDD_FLAG_1 0x2U /**< 1 */ +#define FTM_PDD_FLAG_2 0x4U /**< 2 */ +#define FTM_PDD_FLAG_3 0x8U /**< 3 */ +#define FTM_PDD_FLAG_4 0x10U /**< 4 */ +#define FTM_PDD_FLAG_5 0x20U /**< 5 */ +#define FTM_PDD_FLAG_6 0x40U /**< 6 */ +#define FTM_PDD_FLAG_7 0x80U /**< 7 */ + +/* FTM channel masks. */ +#define FTM_PDD_CHANNEL_0_MASK 0x1U /**< Channel 0 mask */ +#define FTM_PDD_CHANNEL_1_MASK 0x2U /**< Channel 1 mask */ +#define FTM_PDD_CHANNEL_2_MASK 0x4U /**< Channel 2 mask */ +#define FTM_PDD_CHANNEL_3_MASK 0x8U /**< Channel 3 mask */ +#define FTM_PDD_CHANNEL_4_MASK 0x10U /**< Channel 4 mask */ +#define FTM_PDD_CHANNEL_5_MASK 0x20U /**< Channel 5 mask */ +#define FTM_PDD_CHANNEL_6_MASK 0x40U /**< Channel 6 mask */ +#define FTM_PDD_CHANNEL_7_MASK 0x80U /**< Channel 7 mask */ + +/* Deadtime prescaler constants */ +#define FTM_PDD_DT_DIVIDE_1 0U /**< 1 */ +#define FTM_PDD_DT_DIVIDE_4 0x2U /**< 4 */ +#define FTM_PDD_DT_DIVIDE_16 0x3U /**< 16 */ + +/* Clock source constants. */ +#define FTM_PDD_DISABLED 0U /**< Disabled */ +#define FTM_PDD_SYSTEM 0x8U /**< System clock */ +#define FTM_PDD_FIXED 0x10U /**< Fixed clock */ +#define FTM_PDD_EXTERNAL 0x18U /**< External clock */ + +/* Edge and level constants. */ +#define FTM_PDD_EDGE_NONE 0U /**< Disabled */ +#define FTM_PDD_EDGE_RISING 0x4U /**< Rising */ +#define FTM_PDD_EDGE_FALLING 0x8U /**< Falling */ +#define FTM_PDD_EDGE_BOTH 0xCU /**< Both */ + +/* Output action constants. */ +#define FTM_PDD_OUTPUT_NONE 0U /**< Disconnect */ +#define FTM_PDD_OUTPUT_TOGGLE 0x10U /**< Toggle */ +#define FTM_PDD_OUTPUT_CLEAR 0x20U /**< Clear */ +#define FTM_PDD_OUTPUT_SET 0x30U /**< Set */ + +/* Fault mode constants. */ +#define FTM_PDD_FAULT_DISABLED 0U /**< Fault control is disabled for all channels. */ +#define FTM_PDD_FAULT_EVEN_MANUAL 0x20U /**< Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. */ +#define FTM_PDD_FAULT_ALL_MANUAL 0x40U /**< Fault control is enabled for all channels, and the selected mode is the manual fault clearing. */ +#define FTM_PDD_FAULT_ALL_AUTOMATIC 0x60U /**< Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. */ + +/* PWM synchronization mode constants. */ +#define FTM_PDD_NO_RESTRICTIONS 0U /**< Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. */ +#define FTM_PDD_WITH_RESTRICTIONS 0x8U /**< Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. */ + +/* Output mask synchronization constants. */ +#define FTM_PDD_RISING_EDGES 0U /**< OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. */ +#define FTM_PDD_PWM_SYNCHRONIZATION 0x8U /**< OUTMASK register is updated with the value of its buffer only by the PWM synchronization. */ + +/* FTM counter synchronization constants. */ +#define FTM_PDD_COUNT_NORMALLY 0U /**< FTM counter continues to count normally. */ +#define FTM_PDD_UPDATE 0x4U /**< FTM counter is updated with its initial value when the selected trigger is detected. */ + +/* Phase input polarity constants. */ +#define FTM_PDD_QD_NORMAL_POLARITY 0U /**< Phase input signal is not inverted before identifying the rising and falling edges of this signal. */ +#define FTM_PDD_QD_INVERTED_POLARITY 0x1U /**< Phase input signal is inverted before identifying the rising and falling edges of this signal. */ + +/* Quadrature decoder encoding mode constants. */ +#define FTM_PDD_QD_PHASEA_AND_PHASEB 0U /**< Phase A and phase B encoding mode. */ +#define FTM_PDD_QD_COUNT_AND_DIRECTION 0x8U /**< Count and direction encoding mode. */ + +/* BDM mode constants. */ +#define FTM_PDD_BDM_00 0U /**< FTM counter: stopped. CH(n)F bit: can be set. FTM Channels Output: Functional mode. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_01 0x40U /**< FTM counter: stopped. CH(n)F bit: is not set. FTM Channels Output: The channels outputs are forced to their safe value according to POLn bit. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_10 0x80U /**< FTM counter: stopped. CH(n)F bit: is not set. FTM Channels Output: The channels outputs are frozen when the chip enters in BDM mode. Writes to MOD, CNTIN, and C(n)V registers: Writes to these registers bypass the registers buffers. */ +#define FTM_PDD_BDM_11 0xC0U /**< FTM counter: Functional mode. CH(n)F bit: can be set. FTM Channels Output: Functional mode. Writes to MOD, CNTIN, and C(n)V registers: Functional mode. */ + +/* Fault input polarity constants. */ +#define FTM_PDD_FAULT_POLARITY_HIGH 0U /**< The fault input polarity is active high. A one at the fault input indicates a fault. */ +#define FTM_PDD_FAULT_POLARITY_LOW 0x1U /**< The fault input polarity is active low. A zero at the fault input indicates a fault. */ + +/* Synchronization mode constants. */ +#define FTM_PDD_SYNC_LEGACY 0U /**< Legacy PWM synchronization is selected. */ +#define FTM_PDD_SYNC_ENHANCED 0x80U /**< Enhanced PWM synchronization is selected. */ + +/* Register synchronization constants. */ +#define FTM_PDD_SYNC_BY_SYSTEM_CLOCK 0U /**< Register is updated with its buffer value at all rising edges of system clock. */ +#define FTM_PDD_SYNC_BY_PWM 0x1U /**< Register is updated with its buffer value by the PWM synchronization. */ + + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler constants". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPrescaler(_BASE_PTR, FTM_PDD_DIVIDE_1); + * @endcode + */ +#define FTM_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_PS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Prescaler))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Select clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPrescalerSource(_BASE_PTR, FTM_PDD_DISABLED); + * @endcode + */ +#define FTM_PDD_SelectPrescalerSource(PeripheralBase, Source) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_CLKS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of FTM device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_CLKS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPwmAlignMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures PWM aligned mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "PWM aligned mode + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPwmAlignMode(_BASE_PTR, FTM_PDD_EDGE_ALIGNED); + * @endcode + */ +#define FTM_PDD_SelectPwmAlignMode(PeripheralBase, Mode) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SC_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_SC_CPWMS_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOverflowInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns overflow interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetOverflowInterruptMask(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetOverflowInterruptMask(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_TOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_EnableOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_EnableOverflowInterrupt(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SC_REG(PeripheralBase) | FTM_SC_TOIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_DisableOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_DisableOverflowInterrupt(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_SC_TOIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_SC_TOF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOverflowInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns overflow interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetOverflowInterruptFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetOverflowInterruptFlag(PeripheralBase) ( \ + (uint32)(FTM_SC_REG(PeripheralBase) & FTM_SC_TOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearOverflowInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears overflow interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_ClearOverflowInterruptFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ClearOverflowInterruptFlag(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_SC_TOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CNT, FTM1_CNT, + * FTM2_CNT, FTM3_CNT (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadCounterReg(PeripheralBase) ( \ + FTM_CNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- InitializeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value 0 to the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CNT, FTM1_CNT, + * FTM2_CNT, FTM3_CNT (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_InitializeCounter(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_InitializeCounter(PeripheralBase) ( \ + FTM_CNT_REG(PeripheralBase) = \ + 0U \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuloReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the modulo register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the modulo register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MOD, FTM1_MOD, + * FTM2_MOD, FTM3_MOD (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteModuloReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteModuloReg(PeripheralBase, Value) ( \ + FTM_MOD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuloReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the modulo register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_MOD, FTM1_MOD, + * FTM2_MOD, FTM3_MOD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadModuloReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadModuloReg(PeripheralBase) ( \ + FTM_MOD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannelDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM channel DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_EnableChannelDma(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_EnableChannelDma(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) | FTM_CnSC_DMA_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableChannelDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM channel DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_DisableChannelDma(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_DisableChannelDma(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_CnSC_DMA_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelEdgeLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the FTM channel edge and level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param ELSBA_val FTM channel ELSB:ELSA bits. This parameter is of "Edge and + * level constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SelectChannelEdgeLevel(_BASE_PTR, + * FTM_PDD_CHANNEL_0, FTM_PDD_EDGE_NONE); + * @endcode + */ +#define FTM_PDD_SelectChannelEdgeLevel(PeripheralBase, ChannelIdx, ELSBA_val) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)((uint32)0x3U << 2U))) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)(ELSBA_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectChannelMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the FTM channel mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param MSBA_val FTM channel MSB:MSA bits. This parameter is of "Output action + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SelectChannelMode(_BASE_PTR, FTM_PDD_CHANNEL_0, + * FTM_PDD_OUTPUT_NONE); + * @endcode + */ +#define FTM_PDD_SelectChannelMode(PeripheralBase, ChannelIdx, MSBA_val) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)((uint32)0x3U << 4U))) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)(MSBA_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetChannelInterruptMask(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_GetChannelInterruptMask(PeripheralBase, ChannelIdx) ( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) & FTM_CnSC_CHIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableChannelInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM channel interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_EnableChannelInterrupt(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_EnableChannelInterrupt(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) | FTM_CnSC_CHIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableChannelInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM channel interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_DisableChannelInterrupt(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_DisableChannelInterrupt(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(( \ + (uint32)(~(uint32)FTM_CnSC_CHIE_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetChannelInterruptFlag(_BASE_PTR, FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_GetChannelInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (uint32)(FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) & FTM_CnSC_CHF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_ClearChannelInterruptFlag(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ClearChannelInterruptFlag(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadChannelControlReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ReadChannelControlReg(PeripheralBase, ChannelIdx) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the channel status and control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_WriteChannelControlReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0, 1); + * @endcode + */ +#define FTM_PDD_WriteChannelControlReg(PeripheralBase, ChannelIdx, Value) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CnV[ChannelIdx]. + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadChannelValueReg(_BASE_PTR, + * FTM_PDD_CHANNEL_0); + * @endcode + */ +#define FTM_PDD_ReadChannelValueReg(PeripheralBase, ChannelIdx) ( \ + FTM_CnV_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the channel value register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnV[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_WriteChannelValueReg(_BASE_PTR, FTM_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define FTM_PDD_WriteChannelValueReg(PeripheralBase, ChannelIdx, Value) ( \ + FTM_CnV_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInitialValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the counter initial value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the counter initial value register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CNTIN, FTM1_CNTIN, + * FTM2_CNTIN, FTM3_CNTIN (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInitialValueReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInitialValueReg(PeripheralBase, Value) ( \ + FTM_CNTIN_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInitialValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter initial value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CNTIN, FTM1_CNTIN, + * FTM2_CNTIN, FTM3_CNTIN (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInitialValueReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInitialValueReg(PeripheralBase) ( \ + FTM_CNTIN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the capture and compare status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_STATUS, + * FTM1_STATUS, FTM2_STATUS, FTM3_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetChannelFlags(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetChannelFlags(PeripheralBase) ( \ + FTM_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears channel interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt flag + * masks for ClearChannelFlag". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_STATUS, + * FTM1_STATUS, FTM2_STATUS, FTM3_STATUS (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_ClearChannelFlags(_BASE_PTR, FTM_PDD_FLAG_0); + * @endcode + */ +#define FTM_PDD_ClearChannelFlags(PeripheralBase, Mask) ( \ + FTM_STATUS_REG(PeripheralBase) = \ + (uint32)((uint32)(~(uint32)(Mask)) & (uint32)0xFFU) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFaultInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM fault interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_EnableFaultInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_EnableFaultInterrupt(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_FAULTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFaultInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the FTM fault interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_DisableFaultInterrupt(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_DisableFaultInterrupt(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_MODE_FAULTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProtectionDisable + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the write protection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteProtectionDisable(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_WriteProtectionDisable(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_WPDIS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InitializeOutputs + ---------------------------------------------------------------------------- */ + +/** + * @brief Initialize the channel outputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_InitializeOutputs(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_InitializeOutputs(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) |= \ + FTM_MODE_INIT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFeaturesModeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the feature mode selection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the feature mode selection register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFeaturesModeReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFeaturesModeReg(PeripheralBase, Value) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFeaturesModeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the features mode selection register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFeaturesModeReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFeaturesModeReg(PeripheralBase) ( \ + FTM_MODE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSynchronizationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the synchronization register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the synchronization register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSynchronizationReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSynchronizationReg(PeripheralBase, Value) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSynchronizationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the synchronization register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadSynchronizationReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSynchronizationReg(PeripheralBase) ( \ + FTM_SYNC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInitialOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the initial state for channels output register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the initial state for channel output register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_OUTINIT, + * FTM1_OUTINIT, FTM2_OUTINIT, FTM3_OUTINIT (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInitialOutputReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInitialOutputReg(PeripheralBase, Value) ( \ + FTM_OUTINIT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInitialOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the initial state for channels output register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_OUTINIT, + * FTM1_OUTINIT, FTM2_OUTINIT, FTM3_OUTINIT (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInitialOutputReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInitialOutputReg(PeripheralBase) ( \ + FTM_OUTINIT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOutputMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the output mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the output mask register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_OUTMASK, + * FTM1_OUTMASK, FTM2_OUTMASK, FTM3_OUTMASK (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteOutputMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteOutputMaskReg(PeripheralBase, Value) ( \ + FTM_OUTMASK_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOutputMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the output mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_OUTMASK, + * FTM1_OUTMASK, FTM2_OUTMASK, FTM3_OUTMASK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadOutputMaskReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadOutputMaskReg(PeripheralBase) ( \ + FTM_OUTMASK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCombineReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the function for linked channels register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the function for linked channels register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteCombineReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteCombineReg(PeripheralBase, Value) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCombineReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the function for linked channels register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadCombineReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadCombineReg(PeripheralBase) ( \ + FTM_COMBINE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDeadtimeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the deadtime insertion control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the deadtime insertion control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteDeadtimeReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteDeadtimeReg(PeripheralBase, Value) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDeadtimeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the deadtime insertion control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadDeadtimeReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadDeadtimeReg(PeripheralBase) ( \ + FTM_DEADTIME_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteExternalTriggerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM external trigger register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM external trigger register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteExternalTriggerReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteExternalTriggerReg(PeripheralBase, Value) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExternalTriggerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM external trigger register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadExternalTriggerReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadExternalTriggerReg(PeripheralBase) ( \ + FTM_EXTTRIG_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channels polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the channels polarity register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_POL, FTM1_POL, + * FTM2_POL, FTM3_POL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WritePolarityReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WritePolarityReg(PeripheralBase, Value) ( \ + FTM_POL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channels polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_POL, FTM1_POL, + * FTM2_POL, FTM3_POL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadPolarityReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadPolarityReg(PeripheralBase) ( \ + FTM_POL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the fault mode status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FMS, FTM1_FMS, + * FTM2_FMS, FTM3_FMS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFaultStatusReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultStatusReg(PeripheralBase) ( \ + FTM_FMS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteProtectionEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the write protection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FMS, FTM1_FMS, + * FTM2_FMS, FTM3_FMS (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteProtectionEnable(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_WriteProtectionEnable(PeripheralBase) ( \ + FTM_FMS_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_FMS_REG(PeripheralBase) | FTM_FMS_WPEN_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF0_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF1_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF2_MASK)) & (( \ + (uint32)(~(uint32)FTM_FMS_FAULTF3_MASK)) & ( \ + (uint32)(~(uint32)FTM_FMS_FAULTF_MASK))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInputCaptureFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the input capture filter control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the input capture filter control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInputCaptureFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInputCaptureFilterReg(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInputCaptureFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the input capture filter control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadInputCaptureFilterReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInputCaptureFilterReg(PeripheralBase) ( \ + FTM_FILTER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFaultControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the fault control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the fault control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFaultControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFaultControlReg(PeripheralBase, Value) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the fault control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadFaultControlReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultControlReg(PeripheralBase) ( \ + FTM_FLTCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteQuadratureDecoderReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the quadrature decoder control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the quadrature decoder control and status + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteQuadratureDecoderReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteQuadratureDecoderReg(PeripheralBase, Value) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadQuadratureDecoderReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the quadrature decoder control and status + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadQuadratureDecoderReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadQuadratureDecoderReg(PeripheralBase) ( \ + FTM_QDCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the configuration register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteConfigurationReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteConfigurationReg(PeripheralBase, Value) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadConfigurationReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadConfigurationReg(PeripheralBase) ( \ + FTM_CONF_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFaultInputPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM fault input polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM fault input polarity register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteFaultInputPolarityReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteFaultInputPolarityReg(PeripheralBase, Value) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFaultInputPolarityReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM fault input polarity register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadFaultInputPolarityReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadFaultInputPolarityReg(PeripheralBase) ( \ + FTM_FLTPOL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSynchronizationConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the synchronization configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the synchronization configuration register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSynchronizationConfigReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSynchronizationConfigReg(PeripheralBase, Value) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSynchronizationConfigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the synchronization configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_ReadSynchronizationConfigReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSynchronizationConfigReg(PeripheralBase) ( \ + FTM_SYNCONF_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInvertingReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM inverting control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM inverting control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteInvertingReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteInvertingReg(PeripheralBase, Value) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInvertingReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM inverting control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadInvertingReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadInvertingReg(PeripheralBase) ( \ + FTM_INVCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSoftwareOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM software output control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM software output control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SWOCTRL, + * FTM1_SWOCTRL, FTM2_SWOCTRL, FTM3_SWOCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteSoftwareOutputReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteSoftwareOutputReg(PeripheralBase, Value) ( \ + FTM_SWOCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSoftwareOutputReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM software output control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SWOCTRL, + * FTM1_SWOCTRL, FTM2_SWOCTRL, FTM3_SWOCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadSoftwareOutputReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadSoftwareOutputReg(PeripheralBase) ( \ + FTM_SWOCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePwmLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the FTM PWM load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the FTM PWM load register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_PWMLOAD, + * FTM1_PWMLOAD, FTM2_PWMLOAD, FTM3_PWMLOAD (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WritePwmLoadReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WritePwmLoadReg(PeripheralBase, Value) ( \ + FTM_PWMLOAD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPwmLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the FTM PWM load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_PWMLOAD, + * FTM1_PWMLOAD, FTM2_PWMLOAD, FTM3_PWMLOAD (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadPwmLoadReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadPwmLoadReg(PeripheralBase) ( \ + FTM_PWMLOAD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the status and control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + FTM_SC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_SC, FTM1_SC, + * FTM2_SC, FTM3_SC (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_ReadStatusControlReg(PeripheralBase) ( \ + FTM_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCounterResetByCapture + ---------------------------------------------------------------------------- */ + +/** + * @brief Counter reset is driven by the selected event of the channel (n) in + * the Input Capture mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx FTM channel index. Use constants from group "FTM channel + * constants". This parameter is 32 bits wide. + * @param State Requested state of FTM counter reset when the selected channel + * (n) input event is detected. This parameter is of "Global enumeration + * used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CnSC[ChannelIdx]. + * @par Example: + * @code + * FTM_PDD_SetCounterResetByCapture(_BASE_PTR, + * FTM_PDD_CHANNEL_0, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCounterResetByCapture(PeripheralBase, ChannelIdx, State) ( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + FTM_CnSC_REG(PeripheralBase,(ChannelIdx))) & (( \ + (uint32)(~(uint32)FTM_CnSC_ICRST_MASK)) & ( \ + (uint32)(~(uint32)FTM_CnSC_CHF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_CnSC_ICRST_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultControlMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Select the FTM fault control mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault control mode. This parameter is of "Fault + * mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultControlMode(_BASE_PTR, + * FTM_PDD_FAULT_DISABLED); + * @endcode + */ +#define FTM_PDD_SelectFaultControlMode(PeripheralBase, Mode) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_FAULTM_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCaptureTestMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture test mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the capture test mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCaptureTestMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCaptureTestMode(PeripheralBase, State) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_CAPTEST_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_MODE_CAPTEST_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPWMSynchronizationMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM + * counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the PWM synchronization mode. This parameter is of + * "PWM synchronization mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPWMSynchronizationMode(_BASE_PTR, + * FTM_PDD_NO_RESTRICTIONS); + * @endcode + */ +#define FTM_PDD_SelectPWMSynchronizationMode(PeripheralBase, Mode) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_PWMSYNC_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFTMEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables all registers including the FTM-specific registers (second set + * of registers) are available for use with no restrictions. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the FTM enable. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_MODE, FTM1_MODE, + * FTM2_MODE, FTM3_MODE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFTMEnable(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFTMEnable(PeripheralBase, State) ( \ + FTM_MODE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_MODE_REG(PeripheralBase) & (uint32)(~(uint32)FTM_MODE_FTMEN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- PWMSoftwareTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the software trigger as the PWM synchronization trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_PWMSoftwareTrigger(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_PWMSoftwareTrigger(PeripheralBase) ( \ + FTM_SYNC_REG(PeripheralBase) |= \ + FTM_SYNC_SWSYNC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 2 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 2. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger2(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG2_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 1 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 1. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger1(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG1_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPWMHardwareTrigger0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables hardware trigger 0 to the PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the PWM synchronization hardware trigger 0. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPWMHardwareTrigger0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPWMHardwareTrigger0(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_TRIG0_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_TRIG0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectOutputMaskSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects when the OUTMASK register is updated with the value of its + * buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the output mask synchronization. This parameter is + * of "Output mask synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectOutputMaskSynchronization(_BASE_PTR, + * FTM_PDD_RISING_EDGES); + * @endcode + */ +#define FTM_PDD_SelectOutputMaskSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_SYNCHOM_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFTMCounterSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Determines if the FTM counter is reinitialized when the selected + * trigger for the synchronization is detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the FTM counter synchronization. This parameter is + * of "FTM counter synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFTMCounterSynchronization(_BASE_PTR, + * FTM_PDD_COUNT_NORMALLY); + * @endcode + */ +#define FTM_PDD_SelectFTMCounterSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_REINIT_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMaximumLoadingPoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the maximum loading point to PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the maximum loading point to PWM + * synchronization. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetMaximumLoadingPoint(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetMaximumLoadingPoint(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_CNTMAX_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNC_CNTMAX_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMinimumLoadingPoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the minimum loading point to PWM synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the maximum loading point to PWM + * synchronization. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNC, FTM1_SYNC, + * FTM2_SYNC, FTM3_SYNC (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetMinimumLoadingPoint(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetMinimumLoadingPoint(PeripheralBase, State) ( \ + FTM_SYNC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNC_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNC_CNTMIN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultControl01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault control in channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultControl01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultControl01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_FAULTEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_FAULTEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C6V and C7V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C4V and C5V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C2V and C3V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSynchronization01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables PWM synchronization of registers C0V and C1V. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the synchronization. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSynchronization01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSynchronization01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_SYNCEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_SYNCEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadTime01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the deadtime insertion in the channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the deadtime insertion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadTime01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDeadTime01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DTEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DTEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures6 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 6 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 6. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures6(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures6(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 4 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 4. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures4(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures4(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 2 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 2. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures2(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptures0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the capture of the FTM counter value according to the channel + * 0 input event and the configuration of the dual edge capture bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge captures for channel 0. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptures0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptures0(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAP0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAP0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDualEdgeCaptureMode01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Dual Edge Capture mode in the channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the dual edge capture mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDualEdgeCaptureMode01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetDualEdgeCaptureMode01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_DECAPEN0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_DECAPEN0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 7 output is the inverse of the channel 6 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 5 output is the inverse of the channel 4 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 3 output is the inverse of the channel 2 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComplementaryMode01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables Complementary mode for the combined channels. In Complementary + * mode the channel 1 output is the inverse of the channel 0 output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the complementary mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetComplementaryMode01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetComplementaryMode01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMP0_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMP0_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels67 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 6 and 7. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels67(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels67(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE3_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE3_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels45 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 4 and 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels45(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels45(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE2_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels23 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 2 and 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels23(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels23(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE1_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_COMBINE_COMBINE1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCombineChannels01 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the combine feature for channels 0 and 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the combine channels. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_COMBINE, + * FTM1_COMBINE, FTM2_COMBINE, FTM3_COMBINE (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetCombineChannels01(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetCombineChannels01(PeripheralBase, State) ( \ + FTM_COMBINE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_COMBINE_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_COMBINE_COMBINE0_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadtimePrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets deadtime prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the deadtime prescaler. Use constants from + * group "Deadtime prescaler constants". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadtimePrescaler(_BASE_PTR, + * FTM_PDD_DT_DIVIDE_1); + * @endcode + */ +#define FTM_PDD_SetDeadtimePrescaler(PeripheralBase, Prescaler) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_DEADTIME_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_DEADTIME_DTPS_MASK)))) | ( \ + (uint32)((uint32)(Prescaler) << FTM_DEADTIME_DTPS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeadtimeValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the deadtime insertion value for the deadtime counter. The + * deadtime counter is clocked by a scaled version of the system clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the deadtime. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_DEADTIME, + * FTM1_DEADTIME, FTM2_DEADTIME, FTM3_DEADTIME (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetDeadtimeValue(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetDeadtimeValue(PeripheralBase, Value) ( \ + FTM_DEADTIME_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_DEADTIME_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_DEADTIME_DTVAL_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelTriggerFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns channel trigger flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetChannelTriggerFlag(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetChannelTriggerFlag(PeripheralBase) ( \ + (uint32)(FTM_EXTTRIG_REG(PeripheralBase) & FTM_EXTTRIG_TRIGF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInitializationTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the generation of the trigger when the FTM counter is equal to + * the CNTIN register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the generation of the trigger. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInitializationTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetInitializationTrigger(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_INITTRIGEN_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_INITTRIGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C0V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 0 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger0(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH0TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH0TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C1V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 1 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger1(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH1TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH1TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C2V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 2 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger2(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH2TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C3V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 3 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger3(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH3TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH3TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger4 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C4V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 4 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger4(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger4(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH4TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH4TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelTrigger5 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable the generation of the channel trigger when the FTM counter is + * equal to the C5V register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the channel 5 trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_EXTTRIG, + * FTM1_EXTTRIG, FTM2_EXTTRIG, FTM3_EXTTRIG (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetChannelTrigger5(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetChannelTrigger5(PeripheralBase, State) ( \ + FTM_EXTTRIG_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_EXTTRIG_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)FTM_EXTTRIG_CH5TRIG_MASK)) & ( \ + (uint32)(~(uint32)FTM_EXTTRIG_TRIGF_MASK))))) | ( \ + (uint32)((uint32)(State) << FTM_EXTTRIG_CH5TRIG_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter3(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter3(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH3FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH3FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter2(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter2(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH2FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH2FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter1(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter1(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH1FVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FILTER_CH1FVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the channel 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the channel filter. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FILTER, + * FTM1_FILTER, FTM2_FILTER, FTM3_FILTER (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetInputFilter0(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetInputFilter0(PeripheralBase, Value) ( \ + FTM_FILTER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FILTER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FILTER_CH0FVAL_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInpuFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the filter value for the fault inputs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the fault input filter. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInpuFilter(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetFaultInpuFilter(PeripheralBase, Value) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFVAL_MASK)))) | ( \ + (uint32)((uint32)(Value) << FTM_FLTCTRL_FFVAL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter3(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter2(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter1(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInputFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the fault 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInputFilter0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInputFilter0(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FFLTR0EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FFLTR0EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput3 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 3 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput3(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput3(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput2 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 2 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput2(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput2(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 1 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput1(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput1(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_FLTCTRL_FAULT1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFaultInput0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the fault 0 input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the fault input filter. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTCTRL, + * FTM1_FLTCTRL, FTM2_FLTCTRL, FTM3_FLTCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetFaultInput0(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetFaultInput0(PeripheralBase, State) ( \ + FTM_FLTCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTCTRL_FAULT0EN_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseAInputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the quadrature decoder phase A input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the filter for quadrature decoder. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPhaseAInputFilter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPhaseAInputFilter(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_PHAFLTREN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_QDCTRL_PHAFLTREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPhaseBInputFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the filter for the quadrature decoder phase B input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the filter for quadrature decoder. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPhaseBInputFilter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPhaseBInputFilter(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_PHBFLTREN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_QDCTRL_PHBFLTREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPhaseAInputPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity for the quadrature decoder phase A input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the phase A input polarity. This parameter is of + * "Phase input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPhaseAInputPolarity(_BASE_PTR, + * FTM_PDD_QD_NORMAL_POLARITY); + * @endcode + */ +#define FTM_PDD_SelectPhaseAInputPolarity(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_PHAPOL_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_QDCTRL_PHAPOL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPhaseBInputPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity for the quadrature decoder phase B input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the phase B input polarity. This parameter is of + * "Phase input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectPhaseBInputPolarity(_BASE_PTR, + * FTM_PDD_QD_NORMAL_POLARITY); + * @endcode + */ +#define FTM_PDD_SelectPhaseBInputPolarity(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_PHBPOL_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_QDCTRL_PHBPOL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectQDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the encoding mode used in the quadrature decoder mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the quadrature decoder encoding mode. This parameter + * is of "Quadrature decoder encoding mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectQDMode(_BASE_PTR, + * FTM_PDD_QD_PHASEA_AND_PHASEB); + * @endcode + */ +#define FTM_PDD_SelectQDMode(PeripheralBase, Mode) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_QDCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_QDCTRL_QUADMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetQDCounterDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates the counting direction in quadrature mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = FTM_PDD_GetQDCounterDirection(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetQDCounterDirection(PeripheralBase) ( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & FTM_QDCTRL_QUADIR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetQDTimerOverflowDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates if the TOF bit was set on the top or the bottom of counting + * in quadrature decoder mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * FTM_PDD_GetQDTimerOverflowDirection(_BASE_PTR); + * @endcode + */ +#define FTM_PDD_GetQDTimerOverflowDirection(PeripheralBase) ( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & FTM_QDCTRL_TOFDIR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetQDMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the quadrature decoder mode. In this mode, the phase A and B + * input signals control the FTM counter direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the quadrature decoder. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_QDCTRL, + * FTM1_QDCTRL, FTM2_QDCTRL, FTM3_QDCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetQDMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetQDMode(PeripheralBase, State) ( \ + FTM_QDCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_QDCTRL_REG(PeripheralBase) & (uint32)(~(uint32)FTM_QDCTRL_QUADEN_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalTimeBaseOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the global time base signal generation to other FTMs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the global time base output. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetGlobalTimeBaseOutput(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetGlobalTimeBaseOutput(PeripheralBase, State) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_GTBEOUT_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_CONF_GTBEOUT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalTimeBase + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the FTM to use an external global time base signal that is + * generated by another FTM. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the global time base output. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetGlobalTimeBase(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetGlobalTimeBase(PeripheralBase, State) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_GTBEEN_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_CONF_GTBEEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectBDMMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects Selects the FTM behavior in BDM mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the quadrature decoder encoding mode. This parameter + * is of "BDM mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectBDMMode(_BASE_PTR, FTM_PDD_BDM_00); + * @endcode + */ +#define FTM_PDD_SelectBDMMode(PeripheralBase, Mode) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_BDMMODE_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTOFFrequency + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ratio between the number of counter overflows to the + * number of times the TOF bit is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New value of the TOF frequency. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_CONF, FTM1_CONF, + * FTM2_CONF, FTM3_CONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetTOFFrequency(_BASE_PTR, 1); + * @endcode + */ +#define FTM_PDD_SetTOFFrequency(PeripheralBase, Value) ( \ + FTM_CONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_CONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_CONF_NUMTOF_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput3Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput3Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput3Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT3POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT3POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput2Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput2Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput2Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT2POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT2POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput1Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput1Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput1Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT1POL_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_FLTPOL_FLT1POL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFaultInput0Polarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the polarity of the fault input 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the fault input polarity. This parameter is of + * "Fault input polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_FLTPOL, + * FTM1_FLTPOL, FTM2_FLTPOL, FTM3_FLTPOL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectFaultInput0Polarity(_BASE_PTR, + * FTM_PDD_FAULT_POLARITY_HIGH); + * @endcode + */ +#define FTM_PDD_SelectFaultInput0Polarity(PeripheralBase, Mode) ( \ + FTM_FLTPOL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_FLTPOL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_FLTPOL_FLT0POL_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerSWOCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerSWOCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerSWOCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWSOC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWSOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerINVCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerINVCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerINVCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWINVC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWINVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerOUTMASK + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the OUTMASK register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerOUTMASK(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerOUTMASK(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_HWOM_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerWRBUF + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates MOD, CNTIN, and CV registers + * synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerWRBUF(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerWRBUF(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWWRBUF_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWWRBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHWTriggerRSTCNT + ---------------------------------------------------------------------------- */ + +/** + * @brief A hardware trigger activates the FTM counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the HW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHWTriggerRSTCNT(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHWTriggerRSTCNT(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_HWRSTCNT_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_HWRSTCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerSWOCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerSWOCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerSWOCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWSOC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWSOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerINVCTRL + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerINVCTRL(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerINVCTRL(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWINVC_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWINVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerOUTMASK + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the OUTMASK register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerOUTMASK(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerOUTMASK(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_SWOM_MASK))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWOM_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerWRBUF + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates MOD, CNTIN, and CV registers + * synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerWRBUF(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerWRBUF(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWWRBUF_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWWRBUF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSWTriggerRSTCNT + ---------------------------------------------------------------------------- */ + +/** + * @brief The software trigger activates the FTM counter synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the SW trigger. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetSWTriggerRSTCNT(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetSWTriggerRSTCNT(PeripheralBase, State) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SWRSTCNT_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_SYNCONF_SWRSTCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSynchronizationMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the PWM synchronization mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the synchronization mode. This parameter is of + * "Synchronization mode constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectSynchronizationMode(_BASE_PTR, + * FTM_PDD_SYNC_LEGACY); + * @endcode + */ +#define FTM_PDD_SelectSynchronizationMode(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_SYNCMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSWOCTRLSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects SWOCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the SWOCTRL synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectSWOCTRLSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectSWOCTRLSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_SWOC_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_SWOC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectINVCTRLSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects INVCTRL register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the INVCTRL synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectINVCTRLSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectINVCTRLSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(FTM_SYNCONF_REG(PeripheralBase) & (uint32)(~(uint32)FTM_SYNCONF_INVC_MASK))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_INVC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectCNTINSynchronization + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects CNTIN register synchronization. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the CNTIN synchronization. This parameter is of + * "Register synchronization constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SelectCNTINSynchronization(_BASE_PTR, + * FTM_PDD_SYNC_BY_SYSTEM_CLOCK); + * @endcode + */ +#define FTM_PDD_SelectCNTINSynchronization(PeripheralBase, Mode) ( \ + FTM_SYNCONF_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_SYNCONF_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_SYNCONF_CNTINC_MASK)))) | ( \ + (uint32)((uint32)(Mode) << FTM_SYNCONF_CNTINC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHardwareTriggerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief The FTM clears the TRIGj bit when the hardware trigger j is detected, + * where j = 0, 1,2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the hardware trigger mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_SYNCONF, + * FTM1_SYNCONF, FTM2_SYNCONF, FTM3_SYNCONF (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetHardwareTriggerMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetHardwareTriggerMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + FTM_SYNCONF_REG(PeripheralBase) |= \ + FTM_SYNCONF_HWTRIGMODE_MASK) : ( \ + FTM_SYNCONF_REG(PeripheralBase) &= \ + (uint32)(~(uint32)FTM_SYNCONF_HWTRIGMODE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels3Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 3 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 3 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels3Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels3Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV3EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV3EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels2Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 2 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 2 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels2Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels2Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV2EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV2EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels1Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 1 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 1 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels1Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels1Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV1EN_MASK)))) | ( \ + (uint32)((uint32)(State) << FTM_INVCTRL_INV1EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPairChannels0Inverting + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the pair channels 0 inverting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of the pair channels 0 inverting. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: FTM0_INVCTRL, + * FTM1_INVCTRL, FTM2_INVCTRL, FTM3_INVCTRL (depending on the peripheral). + * @par Example: + * @code + * FTM_PDD_SetPairChannels0Inverting(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define FTM_PDD_SetPairChannels0Inverting(PeripheralBase, State) ( \ + FTM_INVCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + FTM_INVCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)FTM_INVCTRL_INV0EN_MASK)))) | ( \ + (uint32)(State))) \ + ) +#endif /* #if defined(FTM_PDD_H_) */ + +/* FTM_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h new file mode 100644 index 0000000..870ee69 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h @@ -0,0 +1,516 @@ +/* + PDD layer implementation for peripheral type GPIO + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(GPIO_PDD_H_) +#define GPIO_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error GPIO PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK10F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK10DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK11D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK11D5WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK12D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK20F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK20DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21D5WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK21F12WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22D5) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F12810) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F25612) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK22F51212) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK24F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK30DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK40X256VMD100) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK50DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51D7) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK51DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK52D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK52DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK53D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK53DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60D10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK60F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK60DZ10) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK60N512VMD100) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK61F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F12WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK61F15WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK63F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK63F12WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK64F12) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK65F18) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK65F18WS) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK66F18) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MK70F12) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F15) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F12WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MK70F15WS) /* PTA, PTB, PTC, PTD, PTE, PTF */ && \ + !defined(MCU_MKE02Z2) /* GPIOA, GPIOB */ && \ + !defined(MCU_MKE02Z4) /* GPIOA, GPIOB */ && \ + !defined(MCU_SKEAZN642) /* GPIOA, GPIOB */ && \ + !defined(MCU_MKE04Z1284) /* GPIOA, GPIOB, GPIOC */ && \ + !defined(MCU_MKE04Z4) /* GPIOA */ && \ + !defined(MCU_SKEAZN84) /* GPIOA */ && \ + !defined(MCU_MKE06Z4) /* GPIOA, GPIOB, GPIOC */ && \ + !defined(MCU_MKL02Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL03Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL04Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL05Z4) /* PTA, PTB */ && \ + !defined(MCU_MKL14Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL15Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL16Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL24Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL25Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL26Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL34Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL36Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKL46Z4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV10Z7) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKV31F12810) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV31F25612) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKV31F51212) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_MKW01Z4) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW21D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW21D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW22D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW22D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW24D5) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_MKW24D5WS) /* GPIOA, GPIOB, GPIOC, GPIOD, GPIOE */ && \ + !defined(MCU_PCK20L4) /* PTA, PTB, PTC, PTD, PTE */ && \ + !defined(MCU_SKEAZ1284) /* GPIOA, GPIOB, GPIOC */ + // Unsupported MCU is active + #error GPIO PDD library: Unsupported derivative is active. +#endif + +//#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Pin masks */ +#define GPIO_PDD_PIN_0 0x1U /**< Pin 0 mask */ +#define GPIO_PDD_PIN_1 0x2U /**< Pin 1 mask */ +#define GPIO_PDD_PIN_2 0x4U /**< Pin 2 mask */ +#define GPIO_PDD_PIN_3 0x8U /**< Pin 3 mask */ +#define GPIO_PDD_PIN_4 0x10U /**< Pin 4 mask */ +#define GPIO_PDD_PIN_5 0x20U /**< Pin 5 mask */ +#define GPIO_PDD_PIN_6 0x40U /**< Pin 6 mask */ +#define GPIO_PDD_PIN_7 0x80U /**< Pin 7 mask */ +#define GPIO_PDD_PIN_8 0x100U /**< Pin 8 mask */ +#define GPIO_PDD_PIN_9 0x200U /**< Pin 9 mask */ +#define GPIO_PDD_PIN_10 0x400U /**< Pin 10 mask */ +#define GPIO_PDD_PIN_11 0x800U /**< Pin 11 mask */ +#define GPIO_PDD_PIN_12 0x1000U /**< Pin 12 mask */ +#define GPIO_PDD_PIN_13 0x2000U /**< Pin 13 mask */ +#define GPIO_PDD_PIN_14 0x4000U /**< Pin 14 mask */ +#define GPIO_PDD_PIN_15 0x8000U /**< Pin 15 mask */ +#define GPIO_PDD_PIN_16 0x10000U /**< Pin 16 mask */ +#define GPIO_PDD_PIN_17 0x20000U /**< Pin 17 mask */ +#define GPIO_PDD_PIN_18 0x40000U /**< Pin 18 mask */ +#define GPIO_PDD_PIN_19 0x80000U /**< Pin 19 mask */ +#define GPIO_PDD_PIN_20 0x100000U /**< Pin 20 mask */ +#define GPIO_PDD_PIN_21 0x200000U /**< Pin 21 mask */ +#define GPIO_PDD_PIN_22 0x400000U /**< Pin 22 mask */ +#define GPIO_PDD_PIN_23 0x800000U /**< Pin 23 mask */ +#define GPIO_PDD_PIN_24 0x1000000U /**< Pin 24 mask */ +#define GPIO_PDD_PIN_25 0x2000000U /**< Pin 25 mask */ +#define GPIO_PDD_PIN_26 0x4000000U /**< Pin 26 mask */ +#define GPIO_PDD_PIN_27 0x8000000U /**< Pin 27 mask */ +#define GPIO_PDD_PIN_28 0x10000000U /**< Pin 28 mask */ +#define GPIO_PDD_PIN_29 0x20000000U /**< Pin 29 mask */ +#define GPIO_PDD_PIN_30 0x40000000U /**< Pin 30 mask */ +#define GPIO_PDD_PIN_31 0x80000000U /**< Pin 31 mask */ + + +/* ---------------------------------------------------------------------------- + -- GetPortDataInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets port data input independently of current direction setting nor + * pin usage. It returns zeros for pins which are not configured for a digital + * function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDIR, GPIOB_PDIR, + * GPIOC_PDIR, GPIOD_PDIR, GPIOE_PDIR, GPIOF_PDIR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDataInput(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDataInput(PeripheralBase) ( \ + (uint32)GPIO_PDIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDataOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets port data output. The value is driven out to the corresponding + * pin if direction of the pin is set to output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new data output value. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDOR, GPIOB_PDOR, + * GPIOC_PDOR, GPIOD_PDOR, GPIOE_PDOR, GPIOF_PDOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDataOutput(_BASE_PTR, 1); + * @endcode + */ +#define GPIO_PDD_SetPortDataOutput(PeripheralBase, Value) ( \ + GPIO_PDOR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPortDataOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets port data output independently of current direction setting. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDOR, GPIOB_PDOR, + * GPIOC_PDOR, GPIOD_PDOR, GPIOE_PDOR, GPIOF_PDOR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDataOutput(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDataOutput(PeripheralBase) ( \ + (uint32)GPIO_PDOR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be cleared. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PCOR, GPIOB_PCOR, + * GPIOC_PCOR, GPIOD_PCOR, GPIOE_PCOR, GPIOF_PCOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_ClearPortDataOutputMask(_BASE_PTR, GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_ClearPortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PCOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PSOR, GPIOB_PSOR, + * GPIOC_PSOR, GPIOD_PSOR, GPIOE_PSOR, GPIOF_PSOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDataOutputMask(_BASE_PTR, GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_SetPortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PSOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- TogglePortDataOutputMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Toggles required bits of port data output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be inverted. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PTOR, GPIOB_PTOR, + * GPIOC_PTOR, GPIOD_PTOR, GPIOE_PTOR, GPIOF_PTOR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_TogglePortDataOutputMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_TogglePortDataOutputMask(PeripheralBase, Mask) ( \ + GPIO_PTOR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortInputDirectionMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets required pins as input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortInputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortInputDirectionMask(PeripheralBase, Mask) ( \ + (GPIO_PDDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask))), \ + (GPIO_PIDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets required pins as input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortInputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortInputDirectionMask(PeripheralBase, Mask) ( \ + GPIO_PDDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPortOutputDirectionMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pins as output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Parameter specifying port pins which should be set as output. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortOutputDirectionMask(_BASE_PTR, + * GPIO_PDD_PIN_0); + * @endcode + */ +#define GPIO_PDD_SetPortOutputDirectionMask(PeripheralBase, Mask) ( \ + GPIO_PDDR_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPortDirectionMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets direction on pins specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param InputMask Mask of port pins defining which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @param OutputMask Mask of port pins defining which should be set as output. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirectionMask(_BASE_PTR, GPIO_PDD_PIN_0, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortDirectionMask(PeripheralBase, InputMask, OutputMask) ( \ + (GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(GPIO_PDDR_REG(PeripheralBase) & (uint32)(~(uint32)(InputMask)))) | ( \ + (uint32)(OutputMask)))), \ + (GPIO_PIDR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(InputMask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets direction on pins specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param InputMask Mask of port pins defining which should be set as input. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @param OutputMask Mask of port pins defining which should be set as output. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR, GPIOA_PIDR, + * GPIOB_PIDR, GPIOC_PIDR (depending on the peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirectionMask(_BASE_PTR, GPIO_PDD_PIN_0, + * GPIO_PDD_PIN_0); + * @endcode + */ + #define GPIO_PDD_SetPortDirectionMask(PeripheralBase, InputMask, OutputMask) ( \ + GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(GPIO_PDDR_REG(PeripheralBase) & (uint32)(~(uint32)(InputMask)))) | ( \ + (uint32)(OutputMask))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPortDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets direction of every pin in the port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new direction for port pins. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * GPIO_PDD_SetPortDirection(_BASE_PTR, 1); + * @endcode + */ +#define GPIO_PDD_SetPortDirection(PeripheralBase, Value) ( \ + GPIO_PDDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPortDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets direction of every pin in the port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: GPIOA_PDDR, GPIOB_PDDR, + * GPIOC_PDDR, GPIOD_PDDR, GPIOE_PDDR, GPIOF_PDDR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = GPIO_PDD_GetPortDirection(_BASE_PTR); + * @endcode + */ +#define GPIO_PDD_GetPortDirection(PeripheralBase) ( \ + (uint32)GPIO_PDDR_REG(PeripheralBase) \ + ) +#endif /* #if defined(GPIO_PDD_H_) */ + +/* GPIO_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h new file mode 100644 index 0000000..8e10db4 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/I2C_PDD.h @@ -0,0 +1,2150 @@ +/* + PDD layer implementation for peripheral type I2C + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(I2C_PDD_H_) +#define I2C_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error I2C PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10D5) /* I2C0 */ && \ + !defined(MCU_MK10D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK10DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK11D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK11D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK12D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20D5) /* I2C0 */ && \ + !defined(MCU_MK20D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK20DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK21F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK21F12WS) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK22D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F12810) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK22F25612) /* I2C0, I2C1 */ && \ + !defined(MCU_MK22F51212) /* I2C0, I2C1 */ && \ + !defined(MCU_MK24F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK30D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK30D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK30DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK40X256VMD100) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK50DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51D7) /* I2C0, I2C1 */ && \ + !defined(MCU_MK51DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK52D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK52DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK53D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK53DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60D10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60DZ10) /* I2C0, I2C1 */ && \ + !defined(MCU_MK60N512VMD100) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F12WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK61F15WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK63F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK63F12WS) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK64F12) /* I2C0, I2C1, I2C2 */ && \ + !defined(MCU_MK65F18) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK65F18WS) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK66F18) /* I2C0, I2C1, I2C2, I2C3 */ && \ + !defined(MCU_MK70F12) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F15) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F12WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MK70F15WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKE02Z2) /* I2C0 */ && \ + !defined(MCU_MKE02Z4) /* I2C0 */ && \ + !defined(MCU_SKEAZN642) /* I2C0 */ && \ + !defined(MCU_MKE04Z1284) /* I2C0, I2C1 */ && \ + !defined(MCU_MKE04Z4) /* I2C0 */ && \ + !defined(MCU_SKEAZN84) /* I2C0 */ && \ + !defined(MCU_MKE06Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL02Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL03Z4) /* I2C0 */ && \ + !defined(MCU_MKL04Z4) /* I2C0 */ && \ + !defined(MCU_MKL05Z4) /* I2C0 */ && \ + !defined(MCU_MKL14Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL15Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL16Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL24Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL25Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL26Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL34Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL36Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKL46Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV10Z7) /* I2C0 */ && \ + !defined(MCU_MKV31F12810) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV31F25612) /* I2C0, I2C1 */ && \ + !defined(MCU_MKV31F51212) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW01Z4) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW21D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW21D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW22D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW22D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW24D5) /* I2C0, I2C1 */ && \ + !defined(MCU_MKW24D5WS) /* I2C0, I2C1 */ && \ + !defined(MCU_PCK20L4) /* I2C0 */ && \ + !defined(MCU_SKEAZ1284) /* I2C0, I2C1 */ + // Unsupported MCU is active + #error I2C PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define I2C_PDD_RX_ACKNOWLEDGE I2C_S_RXAK_MASK /**< Receive acknowledge. */ +#define I2C_PDD_INTERRUPT_FLAG I2C_S_IICIF_MASK /**< Interrupt flag. */ +#define I2C_PDD_SLAVE_TRANSMIT I2C_S_SRW_MASK /**< Slave read/write request. */ +#define I2C_PDD_RANGE_ADDRESS_MATCH I2C_S_RAM_MASK /**< Range address match. */ +#define I2C_PDD_ARBIT_LOST I2C_S_ARBL_MASK /**< Arbitration lost. */ +#define I2C_PDD_BUS_IS_BUSY I2C_S_BUSY_MASK /**< Bus busy - set when a START signal is detected. */ +#define I2C_PDD_ADDRESSED_AS_SLAVE I2C_S_IAAS_MASK /**< Addressed as a slave. */ +#define I2C_PDD_TX_COMPLETE I2C_S_TCF_MASK /**< Transfer complete flag. */ + +/* SCL timeout flags constants (for GetSCLTimeoutInterruptFlags, + ClearSCLTimeoutInterruptFlags macros). */ +#define I2C_PDD_SCL_LOW_TIMEOUT I2C_SMB_SLTF_MASK /**< SCL low timeout flag. */ +#define I2C_PDD_SCL_HI_AND_SDA_HI_TIMEOUT I2C_SMB_SHTF1_MASK /**< SCL high timeout flag - sets when SCL and SDA are held high more than clock × LoValue / 512. */ +#define I2C_PDD_SCL_HI_AND_SDA_LOW_TIMEOUT I2C_SMB_SHTF2_MASK /**< SCL high timeout flag - sets when SCL is held high and SDA is held low more than clock × LoValue/512. */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/* Status flags constants. */ + #define I2C_PDD_BUS_STOP_FLAG I2C_FLT_STOPF_MASK /**< Stop detected on I2C bus */ + +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Status flags constants. */ + #define I2C_PDD_BUS_STOP_FLAG I2C_FLT_STOPF_MASK /**< Stop detected on I2C bus */ + #define I2C_PDD_BUS_START_FLAG I2C_FLT_STARTF_MASK /**< Start detected on I2C bus */ + +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Frequency multiplier constants (for SetFrequencyMultiplier macro). */ +#define I2C_PDD_FREQUENCY_MUL_1 0U /**< Multiplier factor = 1 */ +#define I2C_PDD_FREQUENCY_MUL_2 0x1U /**< Multiplier factor = 2 */ +#define I2C_PDD_FREQUENCY_MUL_4 0x2U /**< Multiplier factor = 4 */ + +/* Master mode constants (for MasterMode, GetMasterMode macros). */ +#define I2C_PDD_MASTER_MODE 0x20U /**< Master mode. */ +#define I2C_PDD_SLAVE_MODE 0U /**< Slave mode. */ + +/* Transmit mode constants (for SetTransmitMode, GetTransmitMode macros). */ +#define I2C_PDD_TX_DIRECTION 0x10U /**< SDA pin set as output. */ +#define I2C_PDD_RX_DIRECTION 0U /**< SDA pin set as input. */ + +/* BUS status constants (for GetBusStatus macro). */ +#define I2C_PDD_BUS_IDLE 0U /**< Bus is idle. */ +#define I2C_PDD_BUS_BUSY 0x20U /**< Bus is busy. */ + +/* Fast SMBus Acknowledge constants (for GetFastSmBusAcknowledge macro). */ +#define I2C_PDD_ACK_FOLLOWING_RX_DATA 0U /**< ACK or NACK is sent on the following receiving data byte. */ +#define I2C_PDD_ACK_AFTER_RX_DATA 0x80U /**< ACK or NACK is sent after receiving a data byte. */ + +/* Clock source constants (for SetSCLTimeoutBusClockSource macro). */ +#define I2C_PDD_BUS_CLOCK 0x10U /**< Bus clock frequency */ +#define I2C_PDD_BUS_CLOCK_DIV64 0U /**< Bus clock / 64 frequency */ + + +/* ---------------------------------------------------------------------------- + -- SetSlaveAddress7bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to the address register and set address length to 7 bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AddrValue Slave address value[0..127]. This parameter is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C0_C2, + * I2C1_A1, I2C1_C2, I2C2_A1, I2C2_C2, I2C3_A1, I2C3_C2 (depending on the + * peripheral). + * @par Example: + * @code + * I2C_PDD_SetSlaveAddress7bits(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSlaveAddress7bits(PeripheralBase, AddrValue) ( \ + (I2C_A1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A1_AD_MASK))) | ( \ + (uint8)((uint8)(AddrValue) << I2C_A1_AD_SHIFT)))), \ + (I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_ADEXT_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSlaveAddress10bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes to the address register and set address length to 10 bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param AddrValue Slave address value[0..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C0_C2, + * I2C1_A1, I2C1_C2, I2C2_A1, I2C2_C2, I2C3_A1, I2C3_C2 (depending on the + * peripheral). + * @par Example: + * @code + * I2C_PDD_SetSlaveAddress10bits(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSlaveAddress10bits(PeripheralBase, AddrValue) ( \ + (I2C_A1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A1_AD_MASK))) | ( \ + (uint8)((uint8)((uint16)(AddrValue) & 0x7FU) << I2C_A1_AD_SHIFT)))), \ + (I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_AD_MASK))) | (( \ + (uint8)((uint16)(AddrValue) >> 7U)) | ( \ + I2C_C2_ADEXT_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads address 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_A1, I2C1_A1, + * I2C2_A1, I2C3_A1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadAddress1Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadAddress1Reg(PeripheralBase) ( \ + I2C_A1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into address 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A1, I2C1_A1, + * I2C2_A1, I2C3_A1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteAddress1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteAddress1Reg(PeripheralBase, Value) ( \ + I2C_A1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrequencyDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler to configure the I2C clock for the bit-rate + * selection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FreqDividerValue Frequency divider value[0..63]. This parameter is a + * 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetFrequencyDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetFrequencyDivider(PeripheralBase, FreqDividerValue) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_F_REG(PeripheralBase) & (uint8)(~(uint8)I2C_F_ICR_MASK))) | ( \ + (uint8)(FreqDividerValue))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrequencyMultiplier + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the factor, what is used along with frequency divider to generate + * the I2C baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FreqMultiplierValue Frequency multiplier value[0..2]. This parameter + * is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetFrequencyMultiplier(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetFrequencyMultiplier(PeripheralBase, FreqMultiplierValue) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_F_REG(PeripheralBase) & (uint8)(~(uint8)I2C_F_MULT_MASK))) | ( \ + (uint8)((uint8)(FreqMultiplierValue) << I2C_F_MULT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFrequencyDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads frequency divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadFrequencyDividerReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadFrequencyDividerReg(PeripheralBase) ( \ + I2C_F_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFrequencyDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into frequency + * divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the frequency divider register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_F, I2C1_F, I2C2_F, + * I2C3_F (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteFrequencyDividerReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteFrequencyDividerReg(PeripheralBase, Value) ( \ + I2C_F_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables I2C device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableDevice(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_IICEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C1_IICEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the I2C interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableInterrupt(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_IICIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the I2C interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableInterrupt(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C1_IICIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMasterMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts the I2C to the master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param MasterMode I2C mode value. The user should use one from the enumerated + * values. This parameter is of "Master mode constants (for MasterMode, + * GetMasterMode macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetMasterMode(_BASE_PTR, I2C_PDD_MASTER_MODE); + * @endcode + */ +#define I2C_PDD_SetMasterMode(PeripheralBase, MasterMode) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_MST_MASK))) | ( \ + (uint8)(MasterMode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMasterMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current operating mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Master mode constants (for MasterMode, + * GetMasterMode macros)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetMasterMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetMasterMode(PeripheralBase) ( \ + (uint8)(I2C_C1_REG(PeripheralBase) & I2C_C1_MST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data pin to the output or input direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param TransmitMode Direction I2C pins. The user should use one from the + * enumerated values. This parameter is of "Transmit mode constants (for + * SetTransmitMode, GetTransmitMode macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetTransmitMode(_BASE_PTR, I2C_PDD_TX_DIRECTION); + * @endcode + */ +#define I2C_PDD_SetTransmitMode(PeripheralBase, TransmitMode) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_TX_MASK))) | ( \ + (uint8)(TransmitMode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransmitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current direction mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Transmit mode constants (for SetTransmitMode, + * GetTransmitMode macros)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetTransmitMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetTransmitMode(PeripheralBase) ( \ + (uint8)(I2C_C1_REG(PeripheralBase) & I2C_C1_TX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables an acknowledge signal to be sent to the bus at the + * ninth clock bit after receiving one byte of data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of acknowledge signal. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableTransmitAcknowledge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableTransmitAcknowledge(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_TXAK_MASK) : ( \ + I2C_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C1_TXAK_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- RepeatStart + ---------------------------------------------------------------------------- */ + +/** + * @brief Generates a repeated START condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_RepeatStart(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_RepeatStart(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) |= \ + I2C_C1_RSTA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the wakeup function in stop3 mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of wakeup function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableWakeUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableWakeUp(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_WUEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C1_WUEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of DMA function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C1_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C1_DMAEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadControl1Reg(PeripheralBase) ( \ + I2C_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C1, I2C1_C1, + * I2C2_C1, I2C3_C1 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + I2C_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadStatusReg(PeripheralBase) ( \ + I2C_S_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns status of the BUS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "BUS status constants (for GetBusStatus macro)." + * type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetBusStatus(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetBusStatus(PeripheralBase) ( \ + (uint8)(I2C_S_REG(PeripheralBase) & I2C_S_BUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value that represents a mask of active (pending) interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + I2C_S_REG(PeripheralBase)) & ( \ + (uint8)(( \ + I2C_S_TCF_MASK) | (( \ + I2C_S_IICIF_MASK) | (( \ + I2C_S_RAM_MASK) | (( \ + I2C_S_ARBL_MASK) | ( \ + I2C_S_IAAS_MASK))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants (for ReadStatusReg, GetInterruptFlags, + * ClearInterruptFlags macros).". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearInterruptFlags(_BASE_PTR, + * I2C_PDD_RX_ACKNOWLEDGE); + * @endcode + */ +#define I2C_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + I2C_S_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_S_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_S_IICIF_MASK | I2C_S_ARBL_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_S, I2C1_S, I2C2_S, + * I2C0_S1, I2C1_S1, I2C3_S (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + I2C_S_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_D, I2C1_D, I2C2_D, + * I2C3_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadDataReg(PeripheralBase) ( \ + I2C_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_D, I2C1_D, I2C2_D, + * I2C3_D (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteDataReg(PeripheralBase, Data) ( \ + I2C_D_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGeneralCallAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables general call address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of general call address function. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableGeneralCallAddress(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableGeneralCallAddress(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_GCAEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_GCAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAddressExtension + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables extension address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of extension address. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableAddressExtension(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableAddressExtension(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_ADEXT_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_ADEXT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPadsNormalDriveMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets control the drive capability of the I2C pads to normal drive mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetPadsNormalDriveMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_SetPadsNormalDriveMode(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_HDRS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPadsHighDriveMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets control the drive capability of the I2C pads to high drive mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetPadsHighDriveMode(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_SetPadsHighDriveMode(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) |= \ + I2C_C2_HDRS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSlaveBaudControlByMaster + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables slave baud rate control by master device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of slave baud rate control. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSlaveBaudControlByMaster(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSlaveBaudControlByMaster(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2C_C2_REG(PeripheralBase) |= \ + I2C_C2_SBRC_MASK) : ( \ + I2C_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)I2C_C2_SBRC_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRangeAddressMatch + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables range address matching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of range address matching function. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableRangeAddressMatch(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableRangeAddressMatch(PeripheralBase, State) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_C2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_C2_RMEN_MASK))) | ( \ + (uint8)((uint8)(State) << I2C_C2_RMEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadControl2Reg(PeripheralBase) ( \ + I2C_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_C2, I2C1_C2, + * I2C2_C2, I2C3_C2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + I2C_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInputGlitchFilter + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..31]. This parameter is + * a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_FLT_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#elif ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_FLT_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the programming controls for the width of glitch (in terms of bus + * clock cycles) the filter must absorb. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterFactorValue Input glitch filter value[0..31]. This parameter is + * a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetInputGlitchFilter(_BASE_PTR, 1); + * @endcode + */ + #define I2C_PDD_SetInputGlitchFilter(PeripheralBase, FilterFactorValue) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) & (uint8)(~(uint8)I2C_FLT_FLT_MASK))) | ( \ + (uint8)(FilterFactorValue))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadInputGlitchFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads input glitch filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadInputGlitchFilterReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadInputGlitchFilterReg(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInputGlitchFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into input glitch + * filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the input glitch filter register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteInputGlitchFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteInputGlitchFilterReg(PeripheralBase, Value) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRangeAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the range slave address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param RangeAddressValue Range Address value[0..127]. This parameter is a + * 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetRangeAddress(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetRangeAddress(PeripheralBase, RangeAddressValue) ( \ + I2C_RA_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_RA_REG(PeripheralBase) & (uint8)(~(uint8)I2C_RA_RAD_MASK))) | ( \ + (uint8)((uint8)(RangeAddressValue) << I2C_RA_RAD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRangeAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads value of range address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadRangeAddressReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadRangeAddressReg(PeripheralBase) ( \ + I2C_RA_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRangeAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into range address + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the range address register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_RA, I2C1_RA, + * I2C2_RA, I2C3_RA (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteRangeAddressReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteRangeAddressReg(PeripheralBase, Value) ( \ + I2C_RA_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFastSmBusNackAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables fast SMBus NACK/ACK. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus alert response will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableFastSmBusNackAck(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableFastSmBusNackAck(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_FACK_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_FACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFastSmBusAcknowledge + ---------------------------------------------------------------------------- */ + +/** + * @brief Fast NACK/ACK enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Fast SMBus Acknowledge constants (for + * GetFastSmBusAcknowledge macro)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_GetFastSmBusAcknowledge(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetFastSmBusAcknowledge(PeripheralBase) ( \ + (uint8)(I2C_SMB_REG(PeripheralBase) & I2C_SMB_FACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSmBusAlertResponseAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SMBus alert response address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus alert response will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSmBusAlertResponseAddress(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSmBusAlertResponseAddress(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_ALERTEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_ALERTEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondI2CAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SMBus device default address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Parameter specifying if SMBus device default address will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSecondI2CAddress(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2C_PDD_EnableSecondI2CAddress(PeripheralBase, State) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_SIICAEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_SMB_SIICAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSCLTimeoutBusClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source of the timeout counter to Bus clock or Bus clock/64 + * frequency. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClockSource SCL timeout BUS clock source value. The user should use + * one from the enumerated values. This parameter is of "Clock source + * constants (for SetSCLTimeoutBusClockSource macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSCLTimeoutBusClockSource(_BASE_PTR, + * I2C_PDD_BUS_CLOCK); + * @endcode + */ +#define I2C_PDD_SetSCLTimeoutBusClockSource(PeripheralBase, ClockSource) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_SMB_TCKSEL_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))))) | ( \ + (uint8)(ClockSource))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSCLTimeoutInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value that represents a mask of active (pending) interrupts. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "SCL timeout flags constants (for + * GetSCLTimeoutInterruptFlags, ClearSCLTimeoutInterruptFlags macros)." for + * processing return value. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_GetSCLTimeoutInterruptFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_GetSCLTimeoutInterruptFlags(PeripheralBase) ( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & ( \ + (uint8)(I2C_SMB_SLTF_MASK | (I2C_SMB_SHTF1_MASK | I2C_SMB_SHTF2_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSCLTimeoutInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group "SCL + * timeout flags constants (for GetSCLTimeoutInterruptFlags, + * ClearSCLTimeoutInterruptFlags macros).". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearSCLTimeoutInterruptFlags(_BASE_PTR, + * I2C_PDD_SCL_LOW_TIMEOUT); + * @endcode + */ +#define I2C_PDD_ClearSCLTimeoutInterruptFlags(PeripheralBase, Mask) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_SMB_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSCLTimeoutInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables SCL high and SDA low timeout interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableSCLTimeoutInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableSCLTimeoutInterrupt(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_SMB_REG(PeripheralBase) | I2C_SMB_SHTF2IE_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSCLTimeoutInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables SCL high and SDA low timeout interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableSCLTimeoutInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableSCLTimeoutInterrupt(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_SMB_SHTF2IE_MASK)) & (( \ + (uint8)(~(uint8)I2C_SMB_SHTF2_MASK)) & ( \ + (uint8)(~(uint8)I2C_SMB_SLTF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSMBusControlAndStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SMBus control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadSMBusControlAndStatusReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSMBusControlAndStatusReg(PeripheralBase) ( \ + I2C_SMB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSMBusControlAndStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SMBus control + * and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SMBus control and status register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SMB, I2C1_SMB, + * I2C2_SMB, I2C3_SMB (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSMBusControlAndStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSMBusControlAndStatusReg(PeripheralBase, Value) ( \ + I2C_SMB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSMBusSlaveAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets SMBus address to the address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SMBusSlaveAddrValue SMBus slave address value[0..127]. This parameter + * is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSMBusSlaveAddress(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSMBusSlaveAddress(PeripheralBase, SMBusSlaveAddrValue) ( \ + I2C_A2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_A2_REG(PeripheralBase) & (uint8)(~(uint8)I2C_A2_SAD_MASK))) | ( \ + (uint8)((uint8)(SMBusSlaveAddrValue) << I2C_A2_SAD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads address 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadAddress2Reg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadAddress2Reg(PeripheralBase) ( \ + I2C_A2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into address 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the address 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_A2, I2C1_A2, + * I2C2_A2, I2C3_A2 (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteAddress2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteAddress2Reg(PeripheralBase, Value) ( \ + I2C_A2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSCLLowTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets SCL low timeout value that determines the timeout period of SCL + * low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SCLLowTimeoutValue SCL low timeout value[0..65535]. This parameter is + * a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C0_SLTH, + * I2C1_SLTL, I2C1_SLTH, I2C2_SLTL, I2C2_SLTH, I2C3_SLTL, I2C3_SLTH + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_SetSCLLowTimeout(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_SetSCLLowTimeout(PeripheralBase, SCLLowTimeoutValue) ( \ + (I2C_SLTL_REG(PeripheralBase) = \ + (uint8)(SCLLowTimeoutValue)), \ + (I2C_SLTH_REG(PeripheralBase) = \ + (uint8)((uint16)(SCLLowTimeoutValue) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSclLowTimeoutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SCL low timeout high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SLTH, I2C1_SLTH, + * I2C2_SLTH, I2C3_SLTH (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * I2C_PDD_ReadSclLowTimeoutHighReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSclLowTimeoutHighReg(PeripheralBase) ( \ + I2C_SLTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSclLowTimeoutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SCL low timeout + * high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SCL low timeout high register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTH, I2C1_SLTH, + * I2C2_SLTH, I2C3_SLTH (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSclLowTimeoutHighReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSclLowTimeoutHighReg(PeripheralBase, Value) ( \ + I2C_SLTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSclLowTimeoutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads SCL low timeout high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C1_SLTL, + * I2C2_SLTL, I2C3_SLTL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadSclLowTimeoutLowReg(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadSclLowTimeoutLowReg(PeripheralBase) ( \ + I2C_SLTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSclLowTimeoutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into SCL low timeout + * low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the SCL low timeout low register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_SLTL, I2C1_SLTL, + * I2C2_SLTL, I2C3_SLTL (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_WriteSclLowTimeoutLowReg(_BASE_PTR, 1); + * @endcode + */ +#define I2C_PDD_WriteSclLowTimeoutLowReg(PeripheralBase, Value) ( \ + I2C_SLTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStopHoldOffMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables stop mode holdoff. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of stop mode holdoff. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableStopHoldOffMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define I2C_PDD_EnableStopHoldOffMode(PeripheralBase, State) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_SHEN_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))))) | ( \ + (uint8)((uint8)(State) << I2C_FLT_SHEN_SHIFT))) \ + ) +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables/disables stop mode holdoff. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of stop mode holdoff. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableStopHoldOffMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define I2C_PDD_EnableStopHoldOffMode(PeripheralBase, State) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)I2C_FLT_SHEN_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))))) | ( \ + (uint8)((uint8)(State) << I2C_FLT_SHEN_SHIFT))) \ + ) +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadBusStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the bus status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants." for processing + * return value. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2C_PDD_ReadBusStatusFlags(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_ReadBusStatusFlags(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBusStatusInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4))) +/** + * @brief Clears bus status interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearBusStatusInterruptFlags(_BASE_PTR, + * I2C_PDD_BUS_STOP_FLAG); + * @endcode + */ + #define I2C_PDD_ClearBusStatusInterruptFlags(PeripheralBase, Mask) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) & (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) | ( \ + (uint8)(Mask))) \ + ) +#else /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Clears bus status interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Status flags constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_ClearBusStatusInterruptFlags(_BASE_PTR, + * I2C_PDD_BUS_STOP_FLAG); + * @endcode + */ + #define I2C_PDD_ClearBusStatusInterruptFlags(PeripheralBase, Mask) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + I2C_FLT_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK))))) | ( \ + (uint8)(Mask))) \ + ) +#endif /* (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableBusStopOrStartInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the bus stop or start interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableBusStopOrStartInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableBusStopOrStartInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) | I2C_FLT_SSIE_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusStopOrStartInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the bus stop or start interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT, + * I2C2_FLT, I2C3_FLT (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableBusStopOrStartInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableBusStopOrStartInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_FLT_SSIE_MASK)) & (( \ + (uint8)(~(uint8)I2C_FLT_STARTF_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusStopInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the bus stop interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_EnableBusStopInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_EnableBusStopInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(I2C_FLT_REG(PeripheralBase) | I2C_FLT_STOPIE_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusStopInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the bus stop interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2C0_FLT, I2C1_FLT + * (depending on the peripheral). + * @par Example: + * @code + * I2C_PDD_DisableBusStopInterrupt(_BASE_PTR); + * @endcode + */ +#define I2C_PDD_DisableBusStopInterrupt(PeripheralBase) ( \ + I2C_FLT_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)I2C_FLT_STOPIE_MASK)) & ( \ + (uint8)(~(uint8)I2C_FLT_STOPF_MASK))) \ + ) +#endif /* #if defined(I2C_PDD_H_) */ + +/* I2C_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h new file mode 100644 index 0000000..49ae674 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/LPTMR_PDD.h @@ -0,0 +1,788 @@ +/* + PDD layer implementation for peripheral type LPTMR + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(LPTMR_PDD_H_) +#define LPTMR_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error LPTMR PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* LPTMR0 */ && \ + !defined(MCU_MK10D5) /* LPTMR0 */ && \ + !defined(MCU_MK10D7) /* LPTMR0 */ && \ + !defined(MCU_MK10F12) /* LPTMR0 */ && \ + !defined(MCU_MK10DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK11D5) /* LPTMR0 */ && \ + !defined(MCU_MK11D5WS) /* LPTMR0 */ && \ + !defined(MCU_MK12D5) /* LPTMR0 */ && \ + !defined(MCU_MK20D10) /* LPTMR0 */ && \ + !defined(MCU_MK20D5) /* LPTMR0 */ && \ + !defined(MCU_MK20D7) /* LPTMR0 */ && \ + !defined(MCU_MK20F12) /* LPTMR0 */ && \ + !defined(MCU_MK20DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK21D5) /* LPTMR0 */ && \ + !defined(MCU_MK21D5WS) /* LPTMR0 */ && \ + !defined(MCU_MK21F12) /* LPTMR0 */ && \ + !defined(MCU_MK21F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK22D5) /* LPTMR0 */ && \ + !defined(MCU_MK22F12810) /* LPTMR0 */ && \ + !defined(MCU_MK22F12) /* LPTMR0 */ && \ + !defined(MCU_MK22F25612) /* LPTMR0 */ && \ + !defined(MCU_MK22F51212) /* LPTMR0 */ && \ + !defined(MCU_MK24F12) /* LPTMR0 */ && \ + !defined(MCU_MK30D10) /* LPTMR0 */ && \ + !defined(MCU_MK30D7) /* LPTMR0 */ && \ + !defined(MCU_MK30DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK40D10) /* LPTMR0 */ && \ + !defined(MCU_MK40D7) /* LPTMR0 */ && \ + !defined(MCU_MK40DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK40X256VMD100) /* LPTMR0 */ && \ + !defined(MCU_MK50D10) /* LPTMR0 */ && \ + !defined(MCU_MK50D7) /* LPTMR0 */ && \ + !defined(MCU_MK50DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK51D10) /* LPTMR0 */ && \ + !defined(MCU_MK51D7) /* LPTMR0 */ && \ + !defined(MCU_MK51DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK52D10) /* LPTMR0 */ && \ + !defined(MCU_MK52DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK53D10) /* LPTMR0 */ && \ + !defined(MCU_MK53DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK60D10) /* LPTMR0 */ && \ + !defined(MCU_MK60F12) /* LPTMR0 */ && \ + !defined(MCU_MK60F15) /* LPTMR0 */ && \ + !defined(MCU_MK60DZ10) /* LPTMR0 */ && \ + !defined(MCU_MK60N512VMD100) /* LPTMR0 */ && \ + !defined(MCU_MK61F12) /* LPTMR0 */ && \ + !defined(MCU_MK61F15) /* LPTMR0 */ && \ + !defined(MCU_MK61F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK61F15WS) /* LPTMR0 */ && \ + !defined(MCU_MK63F12) /* LPTMR0 */ && \ + !defined(MCU_MK63F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK64F12) /* LPTMR0 */ && \ + !defined(MCU_MK65F18) /* LPTMR0 */ && \ + !defined(MCU_MK65F18WS) /* LPTMR0 */ && \ + !defined(MCU_MK66F18) /* LPTMR0 */ && \ + !defined(MCU_MK70F12) /* LPTMR0 */ && \ + !defined(MCU_MK70F15) /* LPTMR0 */ && \ + !defined(MCU_MK70F12WS) /* LPTMR0 */ && \ + !defined(MCU_MK70F15WS) /* LPTMR0 */ && \ + !defined(MCU_MKL02Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL03Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL04Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL05Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL14Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL15Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL16Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL24Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL25Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL26Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL34Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL36Z4) /* LPTMR0 */ && \ + !defined(MCU_MKL46Z4) /* LPTMR0 */ && \ + !defined(MCU_MKV10Z7) /* LPTMR0 */ && \ + !defined(MCU_MKV31F12810) /* LPTMR0 */ && \ + !defined(MCU_MKV31F25612) /* LPTMR0 */ && \ + !defined(MCU_MKV31F51212) /* LPTMR0 */ && \ + !defined(MCU_MKW01Z4) /* LPTMR0 */ && \ + !defined(MCU_MKW21D5) /* LPTMR0 */ && \ + !defined(MCU_MKW21D5WS) /* LPTMR0 */ && \ + !defined(MCU_MKW22D5) /* LPTMR0 */ && \ + !defined(MCU_MKW22D5WS) /* LPTMR0 */ && \ + !defined(MCU_MKW24D5) /* LPTMR0 */ && \ + !defined(MCU_MKW24D5WS) /* LPTMR0 */ && \ + !defined(MCU_PCK20L4) /* LPTMR0 */ + // Unsupported MCU is active + #error LPTMR PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Enable freerun constants */ +#define LPTMR_PDD_RESTART_ENABLED 0U /**< Enabled */ +#define LPTMR_PDD_RESTART_DISABLED LPTMR_CSR_TFC_MASK /**< Disabled */ + +/* Timer mode constants */ +#define LPTMR_PDD_SOURCE_INTERNAL 0U /**< Internal */ +#define LPTMR_PDD_SOURCE_EXTERNAL LPTMR_CSR_TMS_MASK /**< External */ + +/* Prescaler/Filter constants */ +#define LPTMR_PDD_PRESCALER_2 0U /**< 2 */ +#define LPTMR_PDD_PRESCALER_4 0x1U /**< 4 */ +#define LPTMR_PDD_PRESCALER_8 0x2U /**< 8 */ +#define LPTMR_PDD_PRESCALER_16 0x3U /**< 16 */ +#define LPTMR_PDD_PRESCALER_32 0x4U /**< 32 */ +#define LPTMR_PDD_PRESCALER_64 0x5U /**< 64 */ +#define LPTMR_PDD_PRESCALER_128 0x6U /**< 128 */ +#define LPTMR_PDD_PRESCALER_256 0x7U /**< 256 */ +#define LPTMR_PDD_PRESCALER_512 0x8U /**< 512 */ +#define LPTMR_PDD_PRESCALER_1024 0x9U /**< 1024 */ +#define LPTMR_PDD_PRESCALER_2048 0xAU /**< 2048 */ +#define LPTMR_PDD_PRESCALER_4096 0xBU /**< 4096 */ +#define LPTMR_PDD_PRESCALER_8192 0xCU /**< 8192 */ +#define LPTMR_PDD_PRESCALER_16384 0xDU /**< 16384 */ +#define LPTMR_PDD_PRESCALER_32768 0xEU /**< 32768 */ +#define LPTMR_PDD_PRESCALER_65536 0xFU /**< 65536 */ +#define LPTMR_PDD_FILTER_2 0x1U /**< 2 */ +#define LPTMR_PDD_FILTER_4 0x2U /**< 4 */ +#define LPTMR_PDD_FILTER_8 0x3U /**< 8 */ +#define LPTMR_PDD_FILTER_16 0x4U /**< 16 */ +#define LPTMR_PDD_FILTER_32 0x5U /**< 32 */ +#define LPTMR_PDD_FILTER_64 0x6U /**< 64 */ +#define LPTMR_PDD_FILTER_128 0x7U /**< 128 */ +#define LPTMR_PDD_FILTER_256 0x8U /**< 256 */ +#define LPTMR_PDD_FILTER_512 0x9U /**< 512 */ +#define LPTMR_PDD_FILTER_1024 0xAU /**< 1024 */ +#define LPTMR_PDD_FILTER_2048 0xBU /**< 2048 */ +#define LPTMR_PDD_FILTER_4096 0xCU /**< 4096 */ +#define LPTMR_PDD_FILTER_8192 0xDU /**< 8192 */ +#define LPTMR_PDD_FILTER_16384 0xEU /**< 16384 */ +#define LPTMR_PDD_FILTER_32768 0xFU /**< 32768 */ + +/* Divider constants */ +#define LPTMR_PDD_DIVIDER_1 0x1U /**< 1 */ +#define LPTMR_PDD_DIVIDER_2 0U /**< 2 */ +#define LPTMR_PDD_DIVIDER_4 0x2U /**< 4 */ +#define LPTMR_PDD_DIVIDER_8 0x4U /**< 8 */ +#define LPTMR_PDD_DIVIDER_16 0x6U /**< 16 */ +#define LPTMR_PDD_DIVIDER_32 0x8U /**< 32 */ +#define LPTMR_PDD_DIVIDER_64 0xAU /**< 64 */ +#define LPTMR_PDD_DIVIDER_128 0xCU /**< 128 */ +#define LPTMR_PDD_DIVIDER_256 0xEU /**< 256 */ +#define LPTMR_PDD_DIVIDER_512 0x10U /**< 512 */ +#define LPTMR_PDD_DIVIDER_1024 0x12U /**< 1024 */ +#define LPTMR_PDD_DIVIDER_2048 0x14U /**< 2048 */ +#define LPTMR_PDD_DIVIDER_4096 0x16U /**< 4096 */ +#define LPTMR_PDD_DIVIDER_8192 0x18U /**< 8192 */ +#define LPTMR_PDD_DIVIDER_16384 0x1AU /**< 16384 */ +#define LPTMR_PDD_DIVIDER_32768 0x1CU /**< 32768 */ +#define LPTMR_PDD_DIVIDER_65536 0x1EU /**< 65536 */ + +/* Timer Pin Select constants. */ +#define LPTMR_PDD_HSCMP 0U /**< Alt 0 */ +#define LPTMR_PDD_PIN_1 0x10U /**< Alt 1 */ +#define LPTMR_PDD_PIN_2 0x20U /**< Alt 2 */ +#define LPTMR_PDD_PIN_3 0x30U /**< Alt 3 */ + +/* Timer Pin Polarity constants. */ +#define LPTMR_PDD_POLARITY_RISING 0U /**< Rising */ +#define LPTMR_PDD_POLARITY_FALLING 0x8U /**< Falling */ + +/* Prescaler bypass constants. */ +#define LPTMR_PDD_BYPASS_DISABLED 0U /**< Disabled */ +#define LPTMR_PDD_BYPASS_ENABLED 0x4U /**< Enabled */ + +/* Clock source constants. */ +#define LPTMR_PDD_SOURCE_INTREF 0U /**< Internal reference clock */ +#define LPTMR_PDD_SOURCE_LPO1KHZ 0x1U /**< Low power oscillator clock */ +#define LPTMR_PDD_SOURCE_EXT32KHZ 0x2U /**< External 32 kHz clock */ +#define LPTMR_PDD_SOURCE_EXTREF 0x3U /**< External reference clock */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TCF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the LPT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_EnableInterrupt(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) | LPTMR_CSR_TIE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the LPT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_DisableInterrupt(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)LPTMR_CSR_TIE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears LPT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ClearInterruptFlag(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) |= \ + LPTMR_CSR_TCF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets Timer Pin Select bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param TPS_val New value of the TPS. This parameter is of "Timer Pin Select + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SelectPin(_BASE_PTR, LPTMR_PDD_HSCMP); + * @endcode + */ +#define LPTMR_PDD_SelectPin(PeripheralBase, TPS_val) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TPS_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(TPS_val))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the polarity of the input source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Edge New value of the polarity. This parameter is of "Timer Pin + * Polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SetPinPolarity(_BASE_PTR, + * LPTMR_PDD_POLARITY_RISING); + * @endcode + */ +#define LPTMR_PDD_SetPinPolarity(PeripheralBase, Edge) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TPP_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Edge))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFreerun + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the freerun mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Restart New value of the restart. Use constants from group "Enable + * freerun constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableFreerun(_BASE_PTR, + * LPTMR_PDD_RESTART_ENABLED); + * @endcode + */ +#define LPTMR_PDD_EnableFreerun(PeripheralBase, Restart) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TFC_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Restart))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimerMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects timer mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Timer mode + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_SetTimerMode(_BASE_PTR, + * LPTMR_PDD_SOURCE_INTERNAL); + * @endcode + */ +#define LPTMR_PDD_SetTimerMode(PeripheralBase, Source) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TMS_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the LPT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of LPT device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define LPTMR_PDD_EnableDevice(PeripheralBase, State) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_CSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_CSR_TEN_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_CSR_TCF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of LPT device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = + * LPTMR_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(LPTMR_CSR_REG(PeripheralBase) & LPTMR_CSR_TEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Prescaler/Filter constants". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SetPrescaler(_BASE_PTR, LPTMR_PDD_PRESCALER_2); + * @endcode + */ +#define LPTMR_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PRESCALE_MASK))) | ( \ + (uint32)((uint32)(Prescaler) << LPTMR_PSR_PRESCALE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePrescalerBypass + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets prescaler bypass. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Bypass New value of the bypass. This parameter is of "Prescaler bypass + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_EnablePrescalerBypass(_BASE_PTR, + * LPTMR_PDD_BYPASS_DISABLED); + * @endcode + */ +#define LPTMR_PDD_EnablePrescalerBypass(PeripheralBase, Bypass) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PBYP_MASK))) | ( \ + (uint32)(Bypass))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets both prescale value and bypass value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the divider. Use constants from group "Divider + * constants". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SetDivider(_BASE_PTR, LPTMR_PDD_DIVIDER_1); + * @endcode + */ +#define LPTMR_PDD_SetDivider(PeripheralBase, Divider) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + LPTMR_PSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)LPTMR_PSR_PRESCALE_MASK)) & ( \ + (uint32)(~(uint32)LPTMR_PSR_PBYP_MASK))))) | (( \ + (uint32)((uint32)((uint32)(Divider) >> 1U) << LPTMR_PSR_PRESCALE_SHIFT)) | ( \ + (uint32)((uint32)((uint32)(Divider) & 0x1U) << LPTMR_PSR_PBYP_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. This parameter is of "Clock source + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_SelectPrescalerSource(_BASE_PTR, + * LPTMR_PDD_SOURCE_INTREF); + * @endcode + */ +#define LPTMR_PDD_SelectPrescalerSource(PeripheralBase, Source) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(LPTMR_PSR_REG(PeripheralBase) & (uint32)(~(uint32)LPTMR_PSR_PCS_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCompareReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the compare register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the compare register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CMR. + * @par Example: + * @code + * LPTMR_PDD_WriteCompareReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WriteCompareReg(PeripheralBase, Value) ( \ + LPTMR_CMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCompareReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the compare register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CMR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCompareReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadCompareReg(PeripheralBase) ( \ + LPTMR_CMR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100))) +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CNR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ + #define LPTMR_PDD_ReadCounterReg(PeripheralBase) ( \ + LPTMR_CNR_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CNR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ + #define LPTMR_PDD_ReadCounterReg(PeripheralBase) ( \ + (LPTMR_CNR_REG(PeripheralBase) = \ + 0U), \ + LPTMR_CNR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control status register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * LPTMR_PDD_WriteControlStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WriteControlStatusReg(PeripheralBase, Value) ( \ + LPTMR_CSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_CSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadControlStatusReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadControlStatusReg(PeripheralBase) ( \ + LPTMR_CSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePrescaleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the prescale register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the prescale register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * LPTMR_PDD_WritePrescaleReg(_BASE_PTR, 1); + * @endcode + */ +#define LPTMR_PDD_WritePrescaleReg(PeripheralBase, Value) ( \ + LPTMR_PSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrescaleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the prescale register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LPTMR0_PSR. + * @par Example: + * @code + * uint32 result = LPTMR_PDD_ReadPrescaleReg(_BASE_PTR); + * @endcode + */ +#define LPTMR_PDD_ReadPrescaleReg(PeripheralBase) ( \ + LPTMR_PSR_REG(PeripheralBase) \ + ) +#endif /* #if defined(LPTMR_PDD_H_) */ + +/* LPTMR_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h new file mode 100644 index 0000000..ebc7cf7 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/MCM_PDD.h @@ -0,0 +1,787 @@ +/* + PDD layer implementation for peripheral type MCM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(MCM_PDD_H_) +#define MCM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error MCM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* MCM */ && \ + !defined(MCU_MK10D7) /* MCM */ && \ + !defined(MCU_MK10F12) /* MCM */ && \ + !defined(MCU_MK10DZ10) /* MCM */ && \ + !defined(MCU_MK11D5) /* MCM */ && \ + !defined(MCU_MK11D5WS) /* MCM */ && \ + !defined(MCU_MK12D5) /* MCM */ && \ + !defined(MCU_MK20D10) /* MCM */ && \ + !defined(MCU_MK20D7) /* MCM */ && \ + !defined(MCU_MK20F12) /* MCM */ && \ + !defined(MCU_MK20DZ10) /* MCM */ && \ + !defined(MCU_MK21D5) /* MCM */ && \ + !defined(MCU_MK21D5WS) /* MCM */ && \ + !defined(MCU_MK21F12) /* MCM */ && \ + !defined(MCU_MK21F12WS) /* MCM */ && \ + !defined(MCU_MK22D5) /* MCM */ && \ + !defined(MCU_MK22F12810) /* MCM */ && \ + !defined(MCU_MK22F12) /* MCM */ && \ + !defined(MCU_MK22F25612) /* MCM */ && \ + !defined(MCU_MK22F51212) /* MCM */ && \ + !defined(MCU_MK24F12) /* MCM */ && \ + !defined(MCU_MK30D10) /* MCM */ && \ + !defined(MCU_MK30D7) /* MCM */ && \ + !defined(MCU_MK30DZ10) /* MCM */ && \ + !defined(MCU_MK40D10) /* MCM */ && \ + !defined(MCU_MK40D7) /* MCM */ && \ + !defined(MCU_MK40DZ10) /* MCM */ && \ + !defined(MCU_MK40X256VMD100) /* MCM */ && \ + !defined(MCU_MK50D10) /* MCM */ && \ + !defined(MCU_MK50D7) /* MCM */ && \ + !defined(MCU_MK50DZ10) /* MCM */ && \ + !defined(MCU_MK51D10) /* MCM */ && \ + !defined(MCU_MK51D7) /* MCM */ && \ + !defined(MCU_MK51DZ10) /* MCM */ && \ + !defined(MCU_MK52D10) /* MCM */ && \ + !defined(MCU_MK52DZ10) /* MCM */ && \ + !defined(MCU_MK53D10) /* MCM */ && \ + !defined(MCU_MK53DZ10) /* MCM */ && \ + !defined(MCU_MK60D10) /* MCM */ && \ + !defined(MCU_MK60F12) /* MCM */ && \ + !defined(MCU_MK60F15) /* MCM */ && \ + !defined(MCU_MK60DZ10) /* MCM */ && \ + !defined(MCU_MK60N512VMD100) /* MCM */ && \ + !defined(MCU_MK61F12) /* MCM */ && \ + !defined(MCU_MK61F15) /* MCM */ && \ + !defined(MCU_MK61F12WS) /* MCM */ && \ + !defined(MCU_MK61F15WS) /* MCM */ && \ + !defined(MCU_MK63F12) /* MCM */ && \ + !defined(MCU_MK63F12WS) /* MCM */ && \ + !defined(MCU_MK64F12) /* MCM */ && \ + !defined(MCU_MK65F18) /* MCM */ && \ + !defined(MCU_MK65F18WS) /* MCM */ && \ + !defined(MCU_MK66F18) /* MCM */ && \ + !defined(MCU_MK70F12) /* MCM */ && \ + !defined(MCU_MK70F15) /* MCM */ && \ + !defined(MCU_MK70F12WS) /* MCM */ && \ + !defined(MCU_MK70F15WS) /* MCM */ && \ + !defined(MCU_MKE02Z2) /* MCM */ && \ + !defined(MCU_MKE02Z4) /* MCM */ && \ + !defined(MCU_SKEAZN642) /* MCM */ && \ + !defined(MCU_MKE04Z1284) /* MCM */ && \ + !defined(MCU_MKE04Z4) /* MCM */ && \ + !defined(MCU_SKEAZN84) /* MCM */ && \ + !defined(MCU_MKE06Z4) /* MCM */ && \ + !defined(MCU_MKL02Z4) /* MCM */ && \ + !defined(MCU_MKL03Z4) /* MCM */ && \ + !defined(MCU_MKL04Z4) /* MCM */ && \ + !defined(MCU_MKL05Z4) /* MCM */ && \ + !defined(MCU_MKL14Z4) /* MCM */ && \ + !defined(MCU_MKL15Z4) /* MCM */ && \ + !defined(MCU_MKL16Z4) /* MCM */ && \ + !defined(MCU_MKL24Z4) /* MCM */ && \ + !defined(MCU_MKL25Z4) /* MCM */ && \ + !defined(MCU_MKL26Z4) /* MCM */ && \ + !defined(MCU_MKL34Z4) /* MCM */ && \ + !defined(MCU_MKL36Z4) /* MCM */ && \ + !defined(MCU_MKL46Z4) /* MCM */ && \ + !defined(MCU_MKV10Z7) /* MCM */ && \ + !defined(MCU_MKV31F12810) /* MCM */ && \ + !defined(MCU_MKV31F25612) /* MCM */ && \ + !defined(MCU_MKV31F51212) /* MCM */ && \ + !defined(MCU_MKW01Z4) /* MCM */ && \ + !defined(MCU_MKW21D5) /* MCM */ && \ + !defined(MCU_MKW21D5WS) /* MCM */ && \ + !defined(MCU_MKW22D5) /* MCM */ && \ + !defined(MCU_MKW22D5WS) /* MCM */ && \ + !defined(MCU_MKW24D5) /* MCM */ && \ + !defined(MCU_MKW24D5WS) /* MCM */ && \ + !defined(MCU_SKEAZ1284) /* MCM */ + // Unsupported MCU is active + #error MCM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Slave bus connection to AXBS input port masks constants (for + GetSlaveBusConnectionToAxbsInputPort macro). */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_0 0x1U /**< A bus slave connection to AXBS input port 0 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_1 0x2U /**< A bus slave connection to AXBS input port 1 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_2 0x4U /**< A bus slave connection to AXBS input port 2 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_3 0x8U /**< A bus slave connection to AXBS input port 3 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_4 0x10U /**< A bus slave connection to AXBS input port 4 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_5 0x20U /**< A bus slave connection to AXBS input port 5 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_6 0x40U /**< A bus slave connection to AXBS input port 6 is present */ +#define MCM_PDD_SLAVE_BUS_CONNECTION_TO_AXBS_INPUT_PORT_7 0x80U /**< A bus slave connection to AXBS input port 7 is present */ + +/* Master bus connection to AXBS input port masks constants (for + GetMasterBusConnectionToAxbsInputPortMask macro). */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_0 0x1U /**< A bus master connection to AXBS input port 0 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_1 0x2U /**< A bus master connection to AXBS input port 1 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_2 0x4U /**< A bus master connection to AXBS input port 2 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_3 0x8U /**< A bus master connection to AXBS input port 3 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_4 0x10U /**< A bus master connection to AXBS input port 4 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_5 0x20U /**< A bus master connection to AXBS input port 5 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_6 0x40U /**< A bus master connection to AXBS input port 6 is present */ +#define MCM_PDD_MASTER_BUS_CONNECTION_TO_AXBS_INPUT_PORT_7 0x80U /**< A bus master connection to AXBS input port 7 is present */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/* Crossbar master arbitration type */ + #define MCM_PDD_FIXED_PRIORITY 0U /**< Fixed-priority arbitration for the crossbar masters */ + #define MCM_PDD_ROUND_ROBIN 0x200U /**< Round-robin arbitration for the crossbar masters */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Crossbar master arbitration type */ + #define MCM_PDD_FIXED_PRIORITY 0U /**< Fixed-priority arbitration for the crossbar masters */ + #define MCM_PDD_ROUND_ROBIN 0x1U /**< Round-robin arbitration for the crossbar masters */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSlaveBusConnectionToAxbsInputPortMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns present mask value of a corresponding connection to the + * crossbar switch's slave input port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: MCM_PLASC. + * @par Example: + * @code + * uint8 result = + * MCM_PDD_GetSlaveBusConnectionToAxbsInputPortMask(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetSlaveBusConnectionToAxbsInputPortMask(PeripheralBase) ( \ + (uint8)(MCM_PLASC_REG(PeripheralBase) & MCM_PLASC_ASC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCrossbarSwitchSlaveConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads crossbar switch (AXBS) slave configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: MCM_PLASC. + * @par Example: + * @code + * uint16 result = + * MCM_PDD_ReadCrossbarSwitchSlaveConfigurationReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadCrossbarSwitchSlaveConfigurationReg(PeripheralBase) ( \ + MCM_PLASC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMasterBusConnectionToAxbsInputPortMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns present mask value of a corresponding connection to the + * crossbar switch's master input port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: MCM_PLAMC. + * @par Example: + * @code + * uint8 result = + * MCM_PDD_GetMasterBusConnectionToAxbsInputPortMask(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetMasterBusConnectionToAxbsInputPortMask(PeripheralBase) ( \ + (uint8)(MCM_PLAMC_REG(PeripheralBase) & MCM_PLAMC_AMC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCrossbarSwitchMasterConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads crossbar switch (AXBS) master configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: MCM_PLAMC. + * @par Example: + * @code + * uint16 result = + * MCM_PDD_ReadCrossbarSwitchMasterConfigurationReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadCrossbarSwitchMasterConfigurationReg(PeripheralBase) ( \ + MCM_PLAMC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCrossbarMastersArbitrationType + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects arbitration type for crossbar masters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Crossbar masters arbitration type. This parameter is of + * "Crossbar master arbitration type" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_SetCrossbarMastersArbitrationType(_BASE_PTR, + * MCM_PDD_FIXED_PRIORITY); + * @endcode + */ +#define MCM_PDD_SetCrossbarMastersArbitrationType(PeripheralBase, State) ( \ + MCM_PLACR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(MCM_PLACR_REG(PeripheralBase) & (uint32)(~(uint32)MCM_PLACR_ARB_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPlatformControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads platform control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * uint32 result = MCM_PDD_ReadPlatformControlReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadPlatformControlReg(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePlatformControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into platform control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the platform control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_WritePlatformControlReg(_BASE_PTR, 1); + * @endcode + */ +#define MCM_PDD_WritePlatformControlReg(PeripheralBase, Value) ( \ + MCM_PLACR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableStallingFlashController + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable stalling flash controller. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableStallingFlashController(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableStallingFlashController(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_ESFC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStallingFlashController + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable stalling flash controller. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableStallingFlashController(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableStallingFlashController(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_ESFC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashDataSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash data speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashDataSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashDataSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_EFDS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashDataSpeculation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash data speculation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashDataSpeculation(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashDataSpeculation(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_EFDS_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controllerCache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controllerCache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerInstructionCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller instruction caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerInstructionCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerInstructionCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCIC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerInstructionCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller instruction caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerInstructionCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerInstructionCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCIC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashControllerDataCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable flash controller data caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_EnableFlashControllerDataCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableFlashControllerDataCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_PLACR_DFCDA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashControllerDataCaching + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable flash controller data caching. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_DisableFlashControllerDataCaching(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_DisableFlashControllerDataCaching(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_DFCDA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InvalidateFlashCache + ---------------------------------------------------------------------------- */ + +/** + * @brief Invalidates flash cache. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_PLACR. + * @par Example: + * @code + * MCM_PDD_InvalidateFlashCache(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_InvalidateFlashCache(PeripheralBase) ( \ + MCM_PLACR_REG(PeripheralBase) |= \ + MCM_PLACR_CFCC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableComputeOperationWakeupOnInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enable compute operation wakeup on interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_EnableComputeOperationWakeupOnInterrupt(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_EnableComputeOperationWakeupOnInterrupt(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) |= \ + MCM_CPO_CPOWOI_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComputeOperationState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non zero value if compute operation entry has completed or + * compute operation exit has not completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_GetComputeOperationState(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetComputeOperationState(PeripheralBase) ( \ + (uint32)(MCM_CPO_REG(PeripheralBase) & MCM_CPO_CPOACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns non zero value if compute operation request is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_GetComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_GetComputeOperationRequest(PeripheralBase) ( \ + (uint32)(MCM_CPO_REG(PeripheralBase) & MCM_CPO_CPOREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Set compute operation request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_SetComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_SetComputeOperationRequest(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) |= \ + MCM_CPO_CPOREQ_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearComputeOperationRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Clear compute operation request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_ClearComputeOperationRequest(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ClearComputeOperationRequest(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) &= \ + (uint32)(~(uint32)MCM_CPO_CPOREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadComputeOperationControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads compute operation control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * uint32 result = + * MCM_PDD_ReadComputeOperationControlReg(_BASE_PTR); + * @endcode + */ +#define MCM_PDD_ReadComputeOperationControlReg(PeripheralBase) ( \ + MCM_CPO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteComputeOperationControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into compute operation + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the compute operation control register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: MCM_CPO. + * @par Example: + * @code + * MCM_PDD_WriteComputeOperationControlReg(_BASE_PTR, 1); + * @endcode + */ +#define MCM_PDD_WriteComputeOperationControlReg(PeripheralBase, Value) ( \ + MCM_CPO_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(MCM_PDD_H_) */ + +/* MCM_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h new file mode 100644 index 0000000..3dd641a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDB_PDD.h @@ -0,0 +1,1716 @@ +/* + PDD layer implementation for peripheral type PDB + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PDB_PDD_H_) +#define PDB_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PDB PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PDB0 */ && \ + !defined(MCU_MK10D5) /* PDB0 */ && \ + !defined(MCU_MK10D7) /* PDB0 */ && \ + !defined(MCU_MK10F12) /* PDB0 */ && \ + !defined(MCU_MK10DZ10) /* PDB0 */ && \ + !defined(MCU_MK11D5) /* PDB0 */ && \ + !defined(MCU_MK11D5WS) /* PDB0 */ && \ + !defined(MCU_MK12D5) /* PDB0 */ && \ + !defined(MCU_MK20D10) /* PDB0 */ && \ + !defined(MCU_MK20D5) /* PDB0 */ && \ + !defined(MCU_MK20D7) /* PDB0 */ && \ + !defined(MCU_MK20F12) /* PDB0 */ && \ + !defined(MCU_MK20DZ10) /* PDB0 */ && \ + !defined(MCU_MK21D5) /* PDB0 */ && \ + !defined(MCU_MK21D5WS) /* PDB0 */ && \ + !defined(MCU_MK21F12) /* PDB0 */ && \ + !defined(MCU_MK21F12WS) /* PDB0 */ && \ + !defined(MCU_MK22D5) /* PDB0 */ && \ + !defined(MCU_MK22F12810) /* PDB0 */ && \ + !defined(MCU_MK22F12) /* PDB0 */ && \ + !defined(MCU_MK22F25612) /* PDB0 */ && \ + !defined(MCU_MK22F51212) /* PDB0 */ && \ + !defined(MCU_MK24F12) /* PDB0 */ && \ + !defined(MCU_MK30D10) /* PDB0 */ && \ + !defined(MCU_MK30D7) /* PDB0 */ && \ + !defined(MCU_MK30DZ10) /* PDB0 */ && \ + !defined(MCU_MK40D10) /* PDB0 */ && \ + !defined(MCU_MK40D7) /* PDB0 */ && \ + !defined(MCU_MK40DZ10) /* PDB0 */ && \ + !defined(MCU_MK40X256VMD100) /* PDB0 */ && \ + !defined(MCU_MK50D10) /* PDB0 */ && \ + !defined(MCU_MK50D7) /* PDB0 */ && \ + !defined(MCU_MK50DZ10) /* PDB0 */ && \ + !defined(MCU_MK51D10) /* PDB0 */ && \ + !defined(MCU_MK51D7) /* PDB0 */ && \ + !defined(MCU_MK51DZ10) /* PDB0 */ && \ + !defined(MCU_MK52D10) /* PDB0 */ && \ + !defined(MCU_MK52DZ10) /* PDB0 */ && \ + !defined(MCU_MK53D10) /* PDB0 */ && \ + !defined(MCU_MK53DZ10) /* PDB0 */ && \ + !defined(MCU_MK60D10) /* PDB0 */ && \ + !defined(MCU_MK60F12) /* PDB0 */ && \ + !defined(MCU_MK60F15) /* PDB0 */ && \ + !defined(MCU_MK60DZ10) /* PDB0 */ && \ + !defined(MCU_MK60N512VMD100) /* PDB0 */ && \ + !defined(MCU_MK61F12) /* PDB0 */ && \ + !defined(MCU_MK61F15) /* PDB0 */ && \ + !defined(MCU_MK61F12WS) /* PDB0 */ && \ + !defined(MCU_MK61F15WS) /* PDB0 */ && \ + !defined(MCU_MK63F12) /* PDB0 */ && \ + !defined(MCU_MK63F12WS) /* PDB0 */ && \ + !defined(MCU_MK64F12) /* PDB0 */ && \ + !defined(MCU_MK65F18) /* PDB0 */ && \ + !defined(MCU_MK65F18WS) /* PDB0 */ && \ + !defined(MCU_MK66F18) /* PDB0 */ && \ + !defined(MCU_MK70F12) /* PDB0 */ && \ + !defined(MCU_MK70F15) /* PDB0 */ && \ + !defined(MCU_MK70F12WS) /* PDB0 */ && \ + !defined(MCU_MK70F15WS) /* PDB0 */ && \ + !defined(MCU_MKV10Z7) /* PDB0 */ && \ + !defined(MCU_MKV31F12810) /* PDB0 */ && \ + !defined(MCU_MKV31F25612) /* PDB0 */ && \ + !defined(MCU_MKV31F51212) /* PDB0 */ && \ + !defined(MCU_MKW21D5) /* PDB0 */ && \ + !defined(MCU_MKW21D5WS) /* PDB0 */ && \ + !defined(MCU_MKW22D5) /* PDB0 */ && \ + !defined(MCU_MKW22D5WS) /* PDB0 */ && \ + !defined(MCU_MKW24D5) /* PDB0 */ && \ + !defined(MCU_MKW24D5WS) /* PDB0 */ && \ + !defined(MCU_PCK20L4) /* PDB0 */ + // Unsupported MCU is active + #error PDB PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Interrupt masks. */ +#define PDB_PDD_SEQUENCE_ERROR_INT PDB_SC_PDBEIE_MASK /**< PDB sequence error interrupt mask */ +#define PDB_PDD_INTERRUPT_INT PDB_SC_PDBIE_MASK /**< PDB interrupt mask */ + +/* Trigger masks. */ +#define PDB_PDD_PRE_TRIGGER_0 0x1U /**< Trigger 0 mask. */ +#define PDB_PDD_PRE_TRIGGER_1 0x2U /**< Trigger 1 mask. */ +#define PDB_PDD_PRE_TRIGGER_2 0x4U /**< Trigger 2 mask. */ +#define PDB_PDD_PRE_TRIGGER_3 0x8U /**< Trigger 3 mask. */ +#define PDB_PDD_PRE_TRIGGER_4 0x10U /**< Trigger 4 mask. */ +#define PDB_PDD_PRE_TRIGGER_5 0x20U /**< Trigger 5 mask. */ +#define PDB_PDD_PRE_TRIGGER_6 0x40U /**< Trigger 6 mask. */ +#define PDB_PDD_PRE_TRIGGER_7 0x80U /**< Trigger 7 mask. */ + +/* Channel pre-trigger status constants. */ +#define PDB_PDD_PRE_TRIGGER_FLAG_0 0x10000U /**< Pre-Trigger channel flag 0 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_1 0x20000U /**< Pre-Trigger channel flag 1 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_2 0x40000U /**< Pre-Trigger channel flag 2 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_3 0x80000U /**< Pre-Trigger channel flag 3 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_4 0x100000U /**< Pre-Trigger channel flag 4 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_5 0x200000U /**< Pre-Trigger channel flag 5 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_6 0x400000U /**< Pre-Trigger channel flag 6 mask */ +#define PDB_PDD_PRE_TRIGGER_FLAG_7 0x800000U /**< Pre-Trigger channel flag 7 mask */ +#define PDB_PDD_PRE_TRIGGER_ALL_FLAGS 0xFF0000U /**< Pre-Trigger channel all flags mask */ + +/* Pre-trigger sequence error constants. */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_0 0x1U /**< Pre-Trigger sequence error flag 0 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_1 0x2U /**< Pre-Trigger sequence error flag 1 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_2 0x4U /**< Pre-Trigger sequence error flag 2 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_3 0x8U /**< Pre-Trigger sequence error flag 3 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_4 0x10U /**< Pre-Trigger sequence error flag 4 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_5 0x20U /**< Pre-Trigger sequence error flag 5 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_6 0x40U /**< Pre-Trigger sequence error flag 6 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_FLAG_7 0x80U /**< Pre-Trigger sequence error flag 7 mask */ +#define PDB_PDD_PRE_TRIGGER_SEQUENCE_ERROR_ALL_FLAGS 0x80U /**< Pre-Trigger sequence all error flags mask */ + +/* Load mode constants */ +#define PDB_PDD_LOAD_IMMEDIATE 0U /**< The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED_WITH_COUNTER 0x40000U /**< The internal registers are loaded with the values from their buffers when the PDB counter reaches the PDB_MOD register value after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED_WITH_INPUT_TRIGGER 0x80000U /**< The internal registers are loaded with the values from their buffers when the PDB counter reaches the PDB_MOD register value after 1 is written to LDOK */ +#define PDB_PDD_LOAD_SYNCHRONIZED 0xC0000U /**< The internal registers are loaded with the values from their buffers when either the PDB counter reaches the PDB_MOD register value or a trigger input event is detected, after 1 is written to LDOK */ + +/* Prescaler divider constants */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_1 0U /**< Divide by 1 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_2 0x1000U /**< Divide by 2 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_4 0x2000U /**< Divide by 4 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_8 0x3000U /**< Divide by 8 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_16 0x4000U /**< Divide by 16 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_32 0x5000U /**< Divide by 32 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_64 0x6000U /**< Divide by 64 */ +#define PDB_PDD_PRESCALER_DIVIDE_BY_128 0x7000U /**< Divide by 128 */ + +/* Trigger input source constants */ +#define PDB_PDD_TRIGGER_INPUT_0 0U /**< Trigger-Input 0 */ +#define PDB_PDD_TRIGGER_INPUT_1 0x1U /**< Trigger-Input 1 */ +#define PDB_PDD_TRIGGER_INPUT_2 0x2U /**< Trigger-Input 2 */ +#define PDB_PDD_TRIGGER_INPUT_3 0x3U /**< Trigger-Input 3 */ +#define PDB_PDD_TRIGGER_INPUT_4 0x4U /**< Trigger-Input 4 */ +#define PDB_PDD_TRIGGER_INPUT_5 0x5U /**< Trigger-Input 5 */ +#define PDB_PDD_TRIGGER_INPUT_6 0x6U /**< Trigger-Input 6 */ +#define PDB_PDD_TRIGGER_INPUT_7 0x7U /**< Trigger-Input 7 */ +#define PDB_PDD_TRIGGER_INPUT_8 0x8U /**< Trigger-Input 8 */ +#define PDB_PDD_TRIGGER_INPUT_9 0x9U /**< Trigger-Input 9 */ +#define PDB_PDD_TRIGGER_INPUT_10 0xAU /**< Trigger-Input 10 */ +#define PDB_PDD_TRIGGER_INPUT_11 0xBU /**< Trigger-Input 11 */ +#define PDB_PDD_TRIGGER_INPUT_12 0xCU /**< Trigger-Input 12 */ +#define PDB_PDD_TRIGGER_INPUT_13 0xDU /**< Trigger-Input 13 */ +#define PDB_PDD_TRIGGER_INPUT_14 0xEU /**< Trigger-Input 14 */ +#define PDB_PDD_TRIGGER_INPUT_15 0xFU /**< Trigger-Input 15 */ +#define PDB_PDD_SOFTWARE_TRIGGER 0x10U /**< Software trigger */ + +/* Multiplication factor for prescalerconstants */ +#define PDB_PDD_MULTIPLICATION_FACTOR_1 0U /**< Multiplication factor is 1 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_10 0x4U /**< Multiplication factor is 10 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_20 0x8U /**< Multiplication factor is 20 */ +#define PDB_PDD_MULTIPLICATION_FACTOR_40 0xCU /**< Multiplication factor is 40 */ + + +/* ---------------------------------------------------------------------------- + -- SelectLoadMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects load register mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Load register mode value. The user should use one from the + * enumerated values. This parameter is of "Load mode constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectLoadMode(_BASE_PTR, PDB_PDD_LOAD_IMMEDIATE); + * @endcode + */ +#define PDB_PDD_SelectLoadMode(PeripheralBase, Mode) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_LDMOD_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks.". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableInterrupt(_BASE_PTR, + * PDB_PDD_SEQUENCE_ERROR_INT); + * @endcode + */ +#define PDB_PDD_EnableInterrupt(PeripheralBase, Mask) ( \ + PDB_SC_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks.". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_DisableInterrupt(_BASE_PTR, + * PDB_PDD_SEQUENCE_ERROR_INT); + * @endcode + */ +#define PDB_PDD_DisableInterrupt(PeripheralBase, Mask) ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SoftwareTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets and restarts the counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SoftwareTrigger(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_SoftwareTrigger(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_SWTRIG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of DMA function. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableDmaRequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDmaRequest(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_DMAEN_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_DMAEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPrescalerDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects prescaler divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider Prescaler divider value. The user should use one from the + * enumerated values. This parameter is of "Prescaler divider constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectPrescalerDivider(_BASE_PTR, + * PDB_PDD_PRESCALER_DIVIDE_BY_1); + * @endcode + */ +#define PDB_PDD_SelectPrescalerDivider(PeripheralBase, Divider) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_PRESCALER_MASK))) | ( \ + (uint32)(Divider))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectTriggerInputSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects trigger input source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Trigger input source. The user should use one from the + * enumerated values. This parameter is of "Trigger input source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectTriggerInputSource(_BASE_PTR, + * PDB_PDD_TRIGGER_INPUT_0); + * @endcode + */ +#define PDB_PDD_SelectTriggerInputSource(PeripheralBase, Source) ( \ + ((Source) == PDB_PDD_TRIGGER_INPUT_0) ? ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)PDB_SC_TRGSEL_MASK)) : (((Source) == PDB_PDD_TRIGGER_INPUT_1) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x1U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_2) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x2U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_3) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x3U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_4) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x4U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_5) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x5U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_6) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x6U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_7) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x7U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_8) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x8U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_9) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0x9U << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_10) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xAU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_11) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xBU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_12) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xCU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_13) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xDU << PDB_SC_TRGSEL_SHIFT)))) : (((Source) == PDB_PDD_TRIGGER_INPUT_14) ? ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_TRGSEL_MASK))) | ( \ + (uint32)((uint32)0xEU << PDB_SC_TRGSEL_SHIFT)))) : ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_TRGSEL_MASK) \ + )))))))))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables PDB device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDevice(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_PDBEN_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_PDBEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a value of the PDB interrupt flag. Flag is set when the + * counter value is equal to the IDLY register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * uint32 result = PDB_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(PDB_SC_REG(PeripheralBase) & PDB_SC_PDBIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ClearInterruptFlag(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) &= \ + (uint32)(~(uint32)PDB_SC_PDBIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectMultiplicationFactor + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects multiplication factor for prescaler. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Factor Multiplication factor value. The user should use one from the + * enumerated values. This parameter is of "Multiplication factor for + * prescalerconstants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_SelectMultiplicationFactor(_BASE_PTR, + * PDB_PDD_MULTIPLICATION_FACTOR_1); + * @endcode + */ +#define PDB_PDD_SelectMultiplicationFactor(PeripheralBase, Factor) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_MULT_MASK))) | ( \ + (uint32)(Factor))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableContinuousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the PDB operation in continuous mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of continuous operation mode. This parameter is + * of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_EnableContinuousMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableContinuousMode(PeripheralBase, State) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_SC_REG(PeripheralBase) & (uint32)(~(uint32)PDB_SC_CONT_MASK))) | ( \ + (uint32)((uint32)(State) << PDB_SC_CONT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- LoadInternalRegisters + ---------------------------------------------------------------------------- */ + +/** + * @brief Updates the internal registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_LoadInternalRegisters(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_LoadInternalRegisters(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) |= \ + PDB_SC_LDOK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusAndControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the status and control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * PDB_PDD_WriteStatusAndControlReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteStatusAndControlReg(PeripheralBase, Value) ( \ + PDB_SC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusAndControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_SC. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_ReadStatusAndControlReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadStatusAndControlReg(PeripheralBase) ( \ + PDB_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetModulusValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the modulus value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Modulus value[0..65535]. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * PDB_PDD_SetModulusValue(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_SetModulusValue(PeripheralBase, Value) ( \ + PDB_MOD_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_MOD_REG(PeripheralBase) & (uint32)(~(uint32)PDB_MOD_MOD_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModulusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the modulus register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the modulus register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * PDB_PDD_WriteModulusReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteModulusReg(PeripheralBase, Value) ( \ + PDB_MOD_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModulusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the modulus register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_MOD. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadModulusReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadModulusReg(PeripheralBase) ( \ + PDB_MOD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCounterValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: PDB0_CNT. + * @par Example: + * @code + * uint16 result = PDB_PDD_GetCounterValue(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetCounterValue(PeripheralBase) ( \ + (uint16)(PDB_CNT_REG(PeripheralBase) & PDB_CNT_CNT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCounterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the counter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_CNT. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadCounterReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadCounterReg(PeripheralBase) ( \ + PDB_CNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetInterruptDelayValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the interrupt delay value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Interrupt delay value[0..65535]. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * PDB_PDD_SetInterruptDelayValue(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_SetInterruptDelayValue(PeripheralBase, Value) ( \ + PDB_IDLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_IDLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_IDLY_IDLY_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptDelayValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt delay value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * uint16 result = PDB_PDD_GetInterruptDelayValue(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_GetInterruptDelayValue(PeripheralBase) ( \ + (uint16)(PDB_IDLY_REG(PeripheralBase) & PDB_IDLY_IDLY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInterruptDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the interrupt delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the interrupt delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * PDB_PDD_WriteInterruptDelayReg(_BASE_PTR, 1); + * @endcode + */ +#define PDB_PDD_WriteInterruptDelayReg(PeripheralBase, Value) ( \ + PDB_IDLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the interrupt delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_IDLY. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadInterruptDelayReg(_BASE_PTR); + * @endcode + */ +#define PDB_PDD_ReadInterruptDelayReg(PeripheralBase) ( \ + PDB_IDLY_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPreTriggerBackToBackMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables (specified by mask parameters) the PDB pre-trigger + * operation as back-to-back mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Enable Trigger mask defining which pre-trigger back-to-back operation + * is disabled. Use constants from group "Trigger masks.". This parameter + * is 8 bits wide. + * @param Disable Trigger mask defining which pre-trigger back-to-back operation + * is enabled. Use constants from group "Trigger masks.". This parameter + * is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_SelectPreTriggerBackToBackMode(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_SelectPreTriggerBackToBackMode(PeripheralBase, Index, Enable, Disable) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_C1_REG(PeripheralBase,(Index))) | ( \ + (uint32)((uint32)(Enable) << PDB_C1_BB_SHIFT)))) & ( \ + (uint32)(~(uint32)((uint32)(Disable) << PDB_C1_BB_SHIFT)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectPreTriggerOutputMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the PDB pre-trigger bypassed/delay output operation mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Bypass Trigger mask defining which pre-trigger output operation is + * bypassed. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @param Delay Trigger mask defining which pre-trigger output operation is + * delayed. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_SelectPreTriggerOutputMode(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_SelectPreTriggerOutputMode(PeripheralBase, Index, Bypass, Delay) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_C1_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)((uint32)(Bypass) << PDB_C1_TOS_SHIFT))))) | ( \ + (uint32)((uint32)(Delay) << PDB_C1_TOS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePreTriggerOutput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/Disables the PDB pre-trigger output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Enable Trigger mask defining which pre-trigger output is enabled. Use + * constants from group "Trigger masks.". This parameter is 8 bits wide. + * @param Disable Trigger mask defining which pre-trigger output is disabled. + * Use constants from group "Trigger masks.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_EnablePreTriggerOutput(_BASE_PTR, periphID, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_EnablePreTriggerOutput(PeripheralBase, Index, Enable, Disable) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(PDB_C1_REG(PeripheralBase,(Index)) | (uint32)(Enable))) & ( \ + (uint32)(~(uint32)(Disable)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the channel control register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * PDB_PDD_WriteChannelControlReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteChannelControlReg(PeripheralBase, Index, Value) ( \ + PDB_C1_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: C1[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelControlReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelControlReg(PeripheralBase, Index) ( \ + PDB_C1_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelPreTriggerFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PDB channel pre-trigger flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_GetChannelPreTriggerFlags(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_GetChannelPreTriggerFlags(PeripheralBase, Index) ( \ + (uint32)(PDB_S_REG(PeripheralBase,(Index)) & PDB_S_CF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelPreTriggerFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PDB channel pre-trigger flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Mask Pre-trigger flag mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_ClearChannelPreTriggerFlags(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_ClearChannelPreTriggerFlags(PeripheralBase, Index, Mask) ( \ + PDB_S_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChannelPreTriggerSequenceErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PDB channel pre-trigger sequence error flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_GetChannelPreTriggerSequenceErrorFlags(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_GetChannelPreTriggerSequenceErrorFlags(PeripheralBase, Index) ( \ + (uint32)(PDB_S_REG(PeripheralBase,(Index)) & PDB_S_ERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearChannelPreTriggerSequenceErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PDB channel pre-trigger sequence error flags defined by + * mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Mask Pre-trigger sequence error flag mask. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_ClearChannelPreTriggerSequenceErrorFlags(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_ClearChannelPreTriggerSequenceErrorFlags(PeripheralBase, Index, Mask) ( \ + PDB_S_REG(PeripheralBase,(Index)) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the channel status register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * PDB_PDD_WriteChannelStatusReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteChannelStatusReg(PeripheralBase, Index, Value) ( \ + PDB_S_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: S[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelStatusReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelStatusReg(PeripheralBase, Index) ( \ + PDB_S_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChannelPreTriggerDelay + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets delay value for the PDB channel's corresponding pre-trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param PreTriggerIdx Pre-trigger index. This parameter is of index type. + * @param Value Pre-trigger channel delay value. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][PreTriggerIdx]. + * @par Example: + * @code + * PDB_PDD_SetChannelPreTriggerDelay(_BASE_PTR, periphID, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_SetChannelPreTriggerDelay(PeripheralBase, ChannelIdx, PreTriggerIdx, Value) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(PreTriggerIdx)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(PreTriggerIdx))) & ( \ + (uint32)(~(uint32)PDB_DLY_DLY_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteChannelDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the channel delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param RegisterIdx Delay register index. This parameter is of index type. + * @param Value Value stored to the channel delay register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][RegisterIdx]. + * @par Example: + * @code + * PDB_PDD_WriteChannelDelayReg(_BASE_PTR, periphID, periphID, + * 1); + * @endcode + */ +#define PDB_PDD_WriteChannelDelayReg(PeripheralBase, ChannelIdx, RegisterIdx, Value) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(RegisterIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadChannelDelayReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the channel delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx Channel index. This parameter is of index type. + * @param RegisterIdx Delay register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: + * DLY[ChannelIdx][RegisterIdx]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadChannelDelayReg(_BASE_PTR, + * periphID, periphID); + * @endcode + */ +#define PDB_PDD_ReadChannelDelayReg(PeripheralBase, ChannelIdx, RegisterIdx) ( \ + PDB_DLY_REG(PeripheralBase,(ChannelIdx),(RegisterIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDacExternalTriggerInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DAC external trigger input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param State Parameter specifying if DAC external trigger input will be + * enabled or disabled. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE defined + * in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_EnableDacExternalTriggerInput(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDacExternalTriggerInput(PeripheralBase, Index, State) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_INTC_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_INTC_EXT_MASK)))) | ( \ + (uint32)((uint32)(State) << PDB_INTC_EXT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDacIntervalTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables DAC interval trigger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param State Parameter specifying if DAC interval trigger will be enabled or + * disabled. This parameter is of "Global enumeration used for specifying + * general enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_EnableDacIntervalTrigger(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define PDB_PDD_EnableDacIntervalTrigger(PeripheralBase, Index, State) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_INTC_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_INTC_TOE_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacIntervalTrigerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DACx interval trigger control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @param Value Value stored to the DACx interval trigger control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * PDB_PDD_WriteDacIntervalTrigerControlReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteDacIntervalTrigerControlReg(PeripheralBase, Index, Value) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacIntervalTrigerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DACx interval trigger control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: INTC[Index]. + * @par Example: + * @code + * uint32 result = + * PDB_PDD_ReadDacIntervalTrigerControlReg(_BASE_PTR, periphID); + * @endcode + */ +#define PDB_PDD_ReadDacIntervalTrigerControlReg(PeripheralBase, Index) ( \ + PDB_INTC_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDacIntervalTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets DAC interval trigger value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC channel index. This parameter is of index type. + * @param Value DAC intervaltrigger value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * PDB_PDD_SetDacIntervalTrigger(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_SetDacIntervalTrigger(PeripheralBase, Index, Value) ( \ + PDB_INT_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(PDB_INT_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)PDB_INT_INT_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDacIntervalReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DACx interval register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @param Value Value stored to the DACx interval register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * PDB_PDD_WriteDacIntervalReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WriteDacIntervalReg(PeripheralBase, Index, Value) ( \ + PDB_INT_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDacIntervalReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DACx interval register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index DAC index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: INT[Index]. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadDacIntervalReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadDacIntervalReg(PeripheralBase, Index) ( \ + PDB_INT_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePreTriggerPulseOut + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the PDB pre-trigger pulse output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Pre-trigger mask defining which pre-trigger pulse output is + * disabled. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @param Disable Pre-trigger mask defining which pre-trigger pulse output is + * enabled. Use constants from group "Trigger masks.". This parameter is 8 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * PDB_PDD_EnablePreTriggerPulseOut(_BASE_PTR, + * PDB_PDD_PRE_TRIGGER_0, PDB_PDD_PRE_TRIGGER_0); + * @endcode + */ +#define PDB_PDD_EnablePreTriggerPulseOut(PeripheralBase, Enable, Disable) ( \ + PDB_POEN_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_POEN_REG(PeripheralBase) | (uint32)(Enable))) & ( \ + (uint32)(~(uint32)(Disable)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePulseOutEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the pulse-out enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out enable register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * PDB_PDD_WritePulseOutEnableReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define PDB_PDD_WritePulseOutEnableReg(PeripheralBase, Index, Value) ( \ + PDB_POEN_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPulseOutEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the pulse-out enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PDB0_POEN. + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutEnableReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define PDB_PDD_ReadPulseOutEnableReg(PeripheralBase, Index) ( \ + PDB_POEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPulseOutDelay1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets the PDB pulse output delay 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 1 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay1(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay1(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_PODLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_PODLY_DLY1_MASK))) | ( \ + (uint32)((uint32)(Value) << PDB_PODLY_DLY1_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the PDB pulse output delay 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 1 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay1(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay1(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_PODLY_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_PODLY_DLY1_MASK)))) | ( \ + (uint32)((uint32)(Value) << PDB_PODLY_DLY1_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPulseOutDelay2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets the PDB pulse output delay 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 2 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay2(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay2(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PDB_PODLY_REG(PeripheralBase) & (uint32)(~(uint32)PDB_PODLY_DLY2_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the PDB pulse output delay 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value PDB pulse output delay 2 value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_SetPulseOutDelay2(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_SetPulseOutDelay2(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + PDB_PODLY_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)PDB_PODLY_DLY2_MASK)))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WritePulseOutDelayReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Writes value to the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_WritePulseOutDelayReg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_WritePulseOutDelayReg(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @param Value Value stored to the pulse-out delay register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * PDB_PDD_WritePulseOutDelayReg(_BASE_PTR, periphID, 1); + * @endcode + */ + #define PDB_PDD_WritePulseOutDelayReg(PeripheralBase, Index, Value) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPulseOutDelayReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10DZ10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKV10Z7))) +/** + * @brief Returns the content of the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutDelayReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define PDB_PDD_ReadPulseOutDelayReg(PeripheralBase, Index) ( \ + PDB_PODLY_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the pulse-out delay register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PODLY[Index], + * PDB0_PO0DLY (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PDB_PDD_ReadPulseOutDelayReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define PDB_PDD_ReadPulseOutDelayReg(PeripheralBase, Index) ( \ + PDB_PODLY_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#endif /* #if defined(PDB_PDD_H_) */ + +/* PDB_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h new file mode 100644 index 0000000..5860196 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PDD_Types.h @@ -0,0 +1,69 @@ +/* Common type declarations for PDD layer */ +/* This file is static and it is generated from API-Factory */ + +#ifndef PDD_TYPES_H_ +#define PDD_TYPES_H_ + +/* --------------------------------------------------------------- */ +/* --------- PDD_TBool */ +/* --------------------------------------------------------------- */ + +/* Implementation note for boolean type: */ +/* Native "bool" type should be used for boolean values */ +/* because the compiler provides optimization and best type representation. */ +/* If the compiler does not support native "bool" type, common "Bool" */ +/* at each place there should be used the most suitable integer type */ +/* and no explicit conversion to 0 and 1 values should be used. */ +/* Common "TBool" typedef could have possible performance issue */ +/* (there is a problem how wide type to select). It is good to avoid using */ +/* explicit "!= 0" because of performance penalty, but without such */ +/* explicit conversion to 0/1 the resulting type may be too wide. */ +/* Every bool type (native or replaced by integer value) should be always */ +/* treated as zero-equal or non-zero (see below for examples). */ + +/* E.g.: This compiler supports boolean type only in C++ mode. */ +/* Out of the C++ mode the boolean type must be simulated. */ + +#ifndef __cplusplus +typedef uint16 PDD_TBool; +#else +typedef bool PDD_TBool; +#endif + +/* ============================================================================ + ================== General PDD macros ====================================== + ============================================================================ */ + +#define PDD_DISABLE 0u +#define PDD_ENABLE 1u + +/* ============================================================================ + ================== General register manipulating routines ================== + ============================================================================ */ + +#define setReg8(Reg, val) ((Reg) = (uint8)(val)) +#define getReg8(Reg) (Reg) +#define testReg8Bits(Reg, GetMask) ((Reg) & (uint8)(GetMask)) +#define clrReg8Bits(Reg, ClrMask) ((Reg) &= (uint8)((uint8)(~(uint8)(ClrMask)))) +#define setReg8Bits(Reg, SetMask) ((Reg) |= (uint8)(SetMask)) +#define invertReg8Bits(Reg, InvMask) ((Reg) ^= (uint8)(InvMask)) +#define clrSetReg8Bits(Reg, ClrMask, SetMask) ((Reg) = (uint8)(((Reg) & (uint8)(~(uint8)(ClrMask))) | (uint8)(SetMask))) + +#define setReg16(Reg, val) ((Reg) = (uint16)(val)) +#define getReg16(Reg) (Reg) +#define testReg16Bits(Reg, GetMask) ((Reg) & (uint16)(GetMask)) +#define clrReg16Bits(Reg, ClrMask) ((Reg) &= (uint16)(~(uint16)(ClrMask))) +#define setReg16Bits(Reg, SetMask) ((Reg) |= (uint16)(SetMask)) +#define invertReg16Bits(Reg, InvMask) ((Reg) ^= (uint16)(InvMask)) +#define clrSetReg16Bits(Reg, ClrMask, SetMask) ((Reg) = (uint16)(((Reg) & (uint16)(~(uint16)(ClrMask))) | (uint16)(SetMask))) + +#define setReg32(Reg, val) ((Reg) = (uint32)(val)) +#define getReg32(Reg) (Reg) +#define testReg32Bits(Reg, GetMask) ((Reg) & (uint32)(GetMask)) +#define clrReg32Bits(Reg, ClrMask) ((Reg) &= (uint32)(~(uint32)(ClrMask))) +#define setReg32Bits(Reg, SetMask) ((Reg) |= (uint32)(SetMask)) +#define invertReg32Bits(Reg, InvMask) ((Reg) ^= (uint32)(InvMask)) +#define clrSetReg32Bits(Reg, ClrMask, SetMask) ((Reg) = (uint32)(((Reg) & (uint32)(~(uint32)(ClrMask))) | (uint32)(SetMask))) + + +#endif /* #if !defined(PDD_TYPES_H_) */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h new file mode 100644 index 0000000..c8c5d69 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PIT_PDD.h @@ -0,0 +1,602 @@ +/* + PDD layer implementation for peripheral type PIT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PIT_PDD_H_) +#define PIT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PIT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PIT */ && \ + !defined(MCU_MK10D5) /* PIT */ && \ + !defined(MCU_MK10D7) /* PIT */ && \ + !defined(MCU_MK10F12) /* PIT */ && \ + !defined(MCU_MK10DZ10) /* PIT */ && \ + !defined(MCU_MK11D5) /* PIT */ && \ + !defined(MCU_MK11D5WS) /* PIT */ && \ + !defined(MCU_MK12D5) /* PIT */ && \ + !defined(MCU_MK20D10) /* PIT */ && \ + !defined(MCU_MK20D5) /* PIT */ && \ + !defined(MCU_MK20D7) /* PIT */ && \ + !defined(MCU_MK20F12) /* PIT */ && \ + !defined(MCU_MK20DZ10) /* PIT */ && \ + !defined(MCU_MK21D5) /* PIT */ && \ + !defined(MCU_MK21D5WS) /* PIT */ && \ + !defined(MCU_MK21F12) /* PIT */ && \ + !defined(MCU_MK21F12WS) /* PIT */ && \ + !defined(MCU_MK22D5) /* PIT */ && \ + !defined(MCU_MK22F12810) /* PIT */ && \ + !defined(MCU_MK22F12) /* PIT */ && \ + !defined(MCU_MK22F25612) /* PIT */ && \ + !defined(MCU_MK22F51212) /* PIT */ && \ + !defined(MCU_MK24F12) /* PIT */ && \ + !defined(MCU_MK30D10) /* PIT */ && \ + !defined(MCU_MK30D7) /* PIT */ && \ + !defined(MCU_MK30DZ10) /* PIT */ && \ + !defined(MCU_MK40D10) /* PIT */ && \ + !defined(MCU_MK40D7) /* PIT */ && \ + !defined(MCU_MK40DZ10) /* PIT */ && \ + !defined(MCU_MK40X256VMD100) /* PIT */ && \ + !defined(MCU_MK50D10) /* PIT */ && \ + !defined(MCU_MK50D7) /* PIT */ && \ + !defined(MCU_MK50DZ10) /* PIT */ && \ + !defined(MCU_MK51D10) /* PIT */ && \ + !defined(MCU_MK51D7) /* PIT */ && \ + !defined(MCU_MK51DZ10) /* PIT */ && \ + !defined(MCU_MK52D10) /* PIT */ && \ + !defined(MCU_MK52DZ10) /* PIT */ && \ + !defined(MCU_MK53D10) /* PIT */ && \ + !defined(MCU_MK53DZ10) /* PIT */ && \ + !defined(MCU_MK60D10) /* PIT */ && \ + !defined(MCU_MK60F12) /* PIT */ && \ + !defined(MCU_MK60F15) /* PIT */ && \ + !defined(MCU_MK60DZ10) /* PIT */ && \ + !defined(MCU_MK60N512VMD100) /* PIT */ && \ + !defined(MCU_MK61F12) /* PIT */ && \ + !defined(MCU_MK61F15) /* PIT */ && \ + !defined(MCU_MK61F12WS) /* PIT */ && \ + !defined(MCU_MK61F15WS) /* PIT */ && \ + !defined(MCU_MK63F12) /* PIT */ && \ + !defined(MCU_MK63F12WS) /* PIT */ && \ + !defined(MCU_MK64F12) /* PIT */ && \ + !defined(MCU_MK65F18) /* PIT */ && \ + !defined(MCU_MK65F18WS) /* PIT */ && \ + !defined(MCU_MK66F18) /* PIT */ && \ + !defined(MCU_MK70F12) /* PIT */ && \ + !defined(MCU_MK70F15) /* PIT */ && \ + !defined(MCU_MK70F12WS) /* PIT */ && \ + !defined(MCU_MK70F15WS) /* PIT */ && \ + !defined(MCU_MKE02Z2) /* PIT */ && \ + !defined(MCU_MKE02Z4) /* PIT */ && \ + !defined(MCU_SKEAZN642) /* PIT */ && \ + !defined(MCU_MKE04Z1284) /* PIT */ && \ + !defined(MCU_MKE04Z4) /* PIT */ && \ + !defined(MCU_SKEAZN84) /* PIT */ && \ + !defined(MCU_MKE06Z4) /* PIT */ && \ + !defined(MCU_MKL04Z4) /* PIT */ && \ + !defined(MCU_MKL05Z4) /* PIT */ && \ + !defined(MCU_MKL14Z4) /* PIT */ && \ + !defined(MCU_MKL15Z4) /* PIT */ && \ + !defined(MCU_MKL16Z4) /* PIT */ && \ + !defined(MCU_MKL24Z4) /* PIT */ && \ + !defined(MCU_MKL25Z4) /* PIT */ && \ + !defined(MCU_MKL26Z4) /* PIT */ && \ + !defined(MCU_MKL34Z4) /* PIT */ && \ + !defined(MCU_MKL36Z4) /* PIT */ && \ + !defined(MCU_MKL46Z4) /* PIT */ && \ + !defined(MCU_MKV31F12810) /* PIT */ && \ + !defined(MCU_MKV31F25612) /* PIT */ && \ + !defined(MCU_MKV31F51212) /* PIT */ && \ + !defined(MCU_MKW01Z4) /* PIT */ && \ + !defined(MCU_MKW21D5) /* PIT */ && \ + !defined(MCU_MKW21D5WS) /* PIT */ && \ + !defined(MCU_MKW22D5) /* PIT */ && \ + !defined(MCU_MKW22D5WS) /* PIT */ && \ + !defined(MCU_MKW24D5) /* PIT */ && \ + !defined(MCU_MKW24D5WS) /* PIT */ && \ + !defined(MCU_PCK20L4) /* PIT */ && \ + !defined(MCU_SKEAZ1284) /* PIT */ + // Unsupported MCU is active + #error PIT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* PIT channel constants */ +#define PIT_PDD_CHANNEL_0 0U /**< 0 */ +#define PIT_PDD_CHANNEL_1 0x1U /**< 1 */ +#define PIT_PDD_CHANNEL_2 0x2U /**< 2 */ +#define PIT_PDD_CHANNEL_3 0x3U /**< 3 */ + +/* Module clock constants */ +#define PIT_PDD_CLOCK_ENABLED 0U /**< Enabled */ +#define PIT_PDD_CLOCK_DISABLED PIT_MCR_MDIS_MASK /**< Disabled */ + +/* Freeze constants */ +#define PIT_PDD_TIMERS_RUN 0U /**< Run */ +#define PIT_PDD_TIMERS_STOPPED PIT_MCR_FRZ_MASK /**< Stopped */ + + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetInterruptMask(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetInterruptMask(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) & PIT_TCTRL_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetInterruptFlag(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) & PIT_TFLG_TIF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PIT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_EnableInterrupt(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_EnableInterrupt(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) |= \ + PIT_TCTRL_TIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the PIT interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_DisableInterrupt(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_DisableInterrupt(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) &= \ + (uint32)(~(uint32)PIT_TCTRL_TIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears PIT interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx], + * LDVAL[ChannelIdx] (depending on the peripheral). + * @par Example: + * @code + * PIT_PDD_ClearInterruptFlag(_BASE_PTR, PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ClearInterruptFlag(PeripheralBase, ChannelIdx) ( \ + (PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) = \ + PIT_TFLG_TIF_MASK), \ + (void)PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ModuleClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables PIT module clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Clock New value of the clock. Use constants from group "Module clock + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_ModuleClock(_BASE_PTR, PIT_PDD_CLOCK_ENABLED); + * @endcode + */ +#define PIT_PDD_ModuleClock(PeripheralBase, Clock) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PIT_MCR_REG(PeripheralBase) & (uint32)(~(uint32)PIT_MCR_MDIS_MASK))) | ( \ + (uint32)(Clock))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ModuleFreeze + ---------------------------------------------------------------------------- */ + +/** + * @brief Allows the timers to be stopped when the device enters debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Freeze New value of the freeze. Use constants from group "Freeze + * constants". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_ModuleFreeze(_BASE_PTR, PIT_PDD_TIMERS_RUN); + * @endcode + */ +#define PIT_PDD_ModuleFreeze(PeripheralBase, Freeze) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PIT_MCR_REG(PeripheralBase) & (uint32)(~(uint32)PIT_MCR_FRZ_MASK))) | ( \ + (uint32)(Freeze))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the load register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: LDVAL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteLoadReg(_BASE_PTR, PIT_PDD_CHANNEL_0, 1); + * @endcode + */ +#define PIT_PDD_WriteLoadReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLoadReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the load register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: LDVAL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadLoadReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadLoadReg(PeripheralBase, ChannelIdx) ( \ + PIT_LDVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the current timer value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CVAL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerValueReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerValueReg(PeripheralBase, ChannelIdx) ( \ + PIT_CVAL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PIT channel device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param State Requested state of PIT channel. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_EnableDevice(_BASE_PTR, PIT_PDD_CHANNEL_0, + * PDD_DISABLE); + * @endcode + */ +#define PIT_PDD_EnableDevice(PeripheralBase, ChannelIdx, State) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(( \ + (uint32)(( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx))) & ( \ + (uint32)(~(uint32)PIT_TCTRL_TEN_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of PIT channel device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_GetEnableDeviceStatus(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_GetEnableDeviceStatus(PeripheralBase, ChannelIdx) ( \ + (uint32)(PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) & PIT_TCTRL_TEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuleControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the module control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the module control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * PIT_PDD_WriteModuleControlReg(_BASE_PTR, 1); + * @endcode + */ +#define PIT_PDD_WriteModuleControlReg(PeripheralBase, Value) ( \ + PIT_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuleControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the module control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PIT_MCR. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadModuleControlReg(_BASE_PTR); + * @endcode + */ +#define PIT_PDD_ReadModuleControlReg(PeripheralBase) ( \ + PIT_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the timer control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the timer control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteTimerControlReg(_BASE_PTR, PIT_PDD_CHANNEL_0, + * 1); + * @endcode + */ +#define PIT_PDD_WriteTimerControlReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the timer control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TCTRL[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerControlReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerControlReg(PeripheralBase, ChannelIdx) ( \ + PIT_TCTRL_REG(PeripheralBase,(ChannelIdx)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerFlagReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the timer flag register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @param Value New content of the timer flag register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * PIT_PDD_WriteTimerFlagReg(_BASE_PTR, PIT_PDD_CHANNEL_0, 1); + * @endcode + */ +#define PIT_PDD_WriteTimerFlagReg(PeripheralBase, ChannelIdx, Value) ( \ + PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerFlagReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the timer flag register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ChannelIdx PIT channel index. Use constants from group "PIT channel + * constants". This parameter is 32 bits wide. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFLG[ChannelIdx]. + * @par Example: + * @code + * uint32 result = PIT_PDD_ReadTimerFlagReg(_BASE_PTR, + * PIT_PDD_CHANNEL_0); + * @endcode + */ +#define PIT_PDD_ReadTimerFlagReg(PeripheralBase, ChannelIdx) ( \ + PIT_TFLG_REG(PeripheralBase,(ChannelIdx)) \ + ) +#endif /* #if defined(PIT_PDD_H_) */ + +/* PIT_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h new file mode 100644 index 0000000..7f72e7c --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/PORT_PDD.h @@ -0,0 +1,2375 @@ +/* + PDD layer implementation for peripheral type PORT + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(PORT_PDD_H_) +#define PORT_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error PORT PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK10F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK10DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK11D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK11D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK12D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK20F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK20DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK21F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F12810) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F25612) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK22F51212) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK24F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK30DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK40X256VMD100) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK50DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51D7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK51DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK52D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK52DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK53D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK53DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60D10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK60F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK60DZ10) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK60N512VMD100) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK61F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK61F15WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK63F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK63F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK64F12) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK65F18) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK65F18WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK66F18) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MK70F12) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F15) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F12WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MK70F15WS) /* PORTA, PORTB, PORTC, PORTD, PORTE, PORTF */ && \ + !defined(MCU_MKE02Z2) /* PORT */ && \ + !defined(MCU_MKE02Z4) /* PORT */ && \ + !defined(MCU_SKEAZN642) /* PORT */ && \ + !defined(MCU_MKE04Z1284) /* PORT */ && \ + !defined(MCU_MKE04Z4) /* PORT */ && \ + !defined(MCU_SKEAZN84) /* PORT */ && \ + !defined(MCU_MKE06Z4) /* PORT */ && \ + !defined(MCU_MKL02Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL03Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL04Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL05Z4) /* PORTA, PORTB */ && \ + !defined(MCU_MKL14Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL15Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL16Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL24Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL25Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL26Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL34Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL36Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKL46Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV10Z7) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F12810) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F25612) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKV31F51212) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW01Z4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW21D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW21D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW22D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW22D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW24D5) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_MKW24D5WS) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_PCK20L4) /* PORTA, PORTB, PORTC, PORTD, PORTE */ && \ + !defined(MCU_SKEAZ1284) /* PORT */ + // Unsupported MCU is active + #error PORT PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Pin masks */ +#define PORT_PDD_PIN_0 0x1U /**< Pin 0 mask */ +#define PORT_PDD_PIN_1 0x2U /**< Pin 1 mask */ +#define PORT_PDD_PIN_2 0x4U /**< Pin 2 mask */ +#define PORT_PDD_PIN_3 0x8U /**< Pin 3 mask */ +#define PORT_PDD_PIN_4 0x10U /**< Pin 4 mask */ +#define PORT_PDD_PIN_5 0x20U /**< Pin 5 mask */ +#define PORT_PDD_PIN_6 0x40U /**< Pin 6 mask */ +#define PORT_PDD_PIN_7 0x80U /**< Pin 7 mask */ +#define PORT_PDD_PIN_8 0x100U /**< Pin 8 mask */ +#define PORT_PDD_PIN_9 0x200U /**< Pin 9 mask */ +#define PORT_PDD_PIN_10 0x400U /**< Pin 10 mask */ +#define PORT_PDD_PIN_11 0x800U /**< Pin 11 mask */ +#define PORT_PDD_PIN_12 0x1000U /**< Pin 12 mask */ +#define PORT_PDD_PIN_13 0x2000U /**< Pin 13 mask */ +#define PORT_PDD_PIN_14 0x4000U /**< Pin 14 mask */ +#define PORT_PDD_PIN_15 0x8000U /**< Pin 15 mask */ +#define PORT_PDD_PIN_16 0x10000U /**< Pin 16 mask */ +#define PORT_PDD_PIN_17 0x20000U /**< Pin 17 mask */ +#define PORT_PDD_PIN_18 0x40000U /**< Pin 18 mask */ +#define PORT_PDD_PIN_19 0x80000U /**< Pin 19 mask */ +#define PORT_PDD_PIN_20 0x100000U /**< Pin 20 mask */ +#define PORT_PDD_PIN_21 0x200000U /**< Pin 21 mask */ +#define PORT_PDD_PIN_22 0x400000U /**< Pin 22 mask */ +#define PORT_PDD_PIN_23 0x800000U /**< Pin 23 mask */ +#define PORT_PDD_PIN_24 0x1000000U /**< Pin 24 mask */ +#define PORT_PDD_PIN_25 0x2000000U /**< Pin 25 mask */ +#define PORT_PDD_PIN_26 0x4000000U /**< Pin 26 mask */ +#define PORT_PDD_PIN_27 0x8000000U /**< Pin 27 mask */ +#define PORT_PDD_PIN_28 0x10000000U /**< Pin 28 mask */ +#define PORT_PDD_PIN_29 0x20000000U /**< Pin 29 mask */ +#define PORT_PDD_PIN_30 0x40000000U /**< Pin 30 mask */ +#define PORT_PDD_PIN_31 0x80000000U /**< Pin 31 mask */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* List of pins offering high drive capability */ + #define PORT_PDD_PTB5 0x2U /**< PTB5 mask */ + #define PORT_PDD_PTC1 0x4U /**< PTC1 mask */ + #define PORT_PDD_PTC5 0x8U /**< PTC5 mask */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/* List of pins offering high drive capability */ + #define PORT_PDD_PTB4 0x1U /**< PTB4 mask */ + #define PORT_PDD_PTB5 0x2U /**< PTB5 mask */ + #define PORT_PDD_PTD0 0x4U /**< PTD0 mask */ + #define PORT_PDD_PTD1 0x8U /**< PTD1 mask */ + #define PORT_PDD_PTE0 0x10U /**< PTE0 mask */ + #define PORT_PDD_PTE1 0x20U /**< PTE1 mask */ + #define PORT_PDD_PTH0 0x40U /**< PTH0 mask */ + #define PORT_PDD_PTH1 0x80U /**< PTH1 mask */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/* Filter selection */ +#define PORT_PDD_NO_FILTER 0U /**< No filter */ +#define PORT_PDD_BUSCLK 0U /**< BUSCLK */ +#define PORT_PDD_FLTDIV1 0x1U /**< FLTDIV1 */ +#define PORT_PDD_FLTDIV2 0x2U /**< FLTDIV2 */ +#define PORT_PDD_FLTDIV3 0x3U /**< FLTDIV3 */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + #define PORT_PDD_IIC 0xAU /**< Selects filter for input from IIC */ + #define PORT_PDD_FTM0 0xCU /**< Selects filter for input from FTM0 */ + #define PORT_PDD_PWT 0xEU /**< Selects filter for input from PWT */ + +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_PTD 0x6U /**< Selects filter for input from PTD */ + #define PORT_PDD_PTE 0x8U /**< Selects filter for input from PTE */ + #define PORT_PDD_PTF 0xAU /**< Selects filter for input from PTF */ + #define PORT_PDD_PTG 0xCU /**< Selects filter for input from PTG */ + #define PORT_PDD_PTH 0xEU /**< Selects filter for input from PTH */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/* Modules offering input pin filtering capability */ + #define PORT_PDD_PTA 0U /**< Selects filter for input from PTA */ + #define PORT_PDD_PTB 0x2U /**< Selects filter for input from PTB */ + #define PORT_PDD_PTC 0x4U /**< Selects filter for input from PTC */ + #define PORT_PDD_PTD 0x6U /**< Selects filter for input from PTD */ + #define PORT_PDD_PTE 0x8U /**< Selects filter for input from PTE */ + #define PORT_PDD_PTF 0xAU /**< Selects filter for input from PTF */ + #define PORT_PDD_PTG 0xCU /**< Selects filter for input from PTG */ + #define PORT_PDD_PTH 0xEU /**< Selects filter for input from PTH */ + #define PORT_PDD_RST 0x10U /**< Selects filter for input from RST */ + #define PORT_PDD_KBI0 0x12U /**< Selects filter for input from KBI0 */ + #define PORT_PDD_KBI1 0x14U /**< Selects filter for input from KBI1 */ + #define PORT_PDD_NMI 0x16U /**< Selects filter for input from NMI */ + #define PORT_PDD_PTI 0U /**< Selects filter for input from PTI */ + #define PORT_PDD_IRQ 0x4U /**< Selects filter for input from IRQ */ + #define PORT_PDD_FTM0 0x6U /**< Selects filter for input from FTM0 */ + #define PORT_PDD_FTM1 0x8U /**< Selects filter for input from FTM1 */ + #define PORT_PDD_PWT 0xAU /**< Selects filter for input from PWT */ + #define PORT_PDD_I2C0 0xCU /**< Selects filter for input from I2C0 */ + #define PORT_PDD_I2C1 0xEU /**< Selects filter for input from I2C1 */ + +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/* Constants for pull type selection */ +#define PORT_PDD_PULL_DOWN 0U /**< Pull down */ +#define PORT_PDD_PULL_UP 0x1U /**< Pull up */ + +/* Constants for pull enabling/disabling */ +#define PORT_PDD_PULL_DISABLE 0U /**< Pull resistor disabled */ +#define PORT_PDD_PULL_ENABLE 0x2U /**< Pull resistor enabled */ + +/* Constants for slew rate setting */ +#define PORT_PDD_SLEW_RATE_FAST 0U /**< Fast slew rate */ +#define PORT_PDD_SLEW_RATE_SLOW 0x4U /**< Slow slew rate */ + +/* Constants for slew rate setting */ +#define PORT_PDD_PASSIVE_FILTER_DISABLE 0U /**< Passive filter disabled */ +#define PORT_PDD_PASSIVE_FILTER_ENABLE 0x10U /**< Passive filter enabled */ + +/* Constants for open drain setting */ +#define PORT_PDD_OPEN_DRAIN_DISABLE 0U /**< Open drain disabled */ +#define PORT_PDD_OPEN_DRAIN_ENABLE 0x20U /**< Open drain enabled */ + +/* Constants for drive strength setting */ +#define PORT_PDD_DRIVE_STRENGTH_LOW 0U /**< Low drive strength */ +#define PORT_PDD_DRIVE_STRENGTH_HIGH 0x40U /**< High drive strength */ + +/* Constants for mux control setting */ +#define PORT_PDD_MUX_CONTROL_DISABLE 0U /**< Mux control disabled */ +#define PORT_PDD_MUX_CONTROL_ALT1 0x100U /**< Pin used with alternate 1 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT2 0x200U /**< Pin used with alternate 2 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT3 0x300U /**< Pin used with alternate 3 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT4 0x400U /**< Pin used with alternate 4 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT5 0x500U /**< Pin used with alternate 5 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT6 0x600U /**< Pin used with alternate 6 functionality */ +#define PORT_PDD_MUX_CONTROL_ALT7 0x700U /**< Pin used with alternate 7 functionality */ + +/* Constants for pin lock setting */ +#define PORT_PDD_PIN_CONTROL_UNLOCK 0U /**< Pin control unlocked */ +#define PORT_PDD_PIN_CONTROL_LOCK 0x8000U /**< Pin control locked */ + +/* Constants for interrupt configuration setting */ +#define PORT_PDD_INTERRUPT_DMA_DISABLED 0U /**< Interrupt and DMA disabled */ +#define PORT_PDD_DMA_ON_RISING 0x10000U /**< DMA enabled on rising edge */ +#define PORT_PDD_DMA_ON_FALLING 0x20000U /**< DMA enabled on falling edge */ +#define PORT_PDD_DMA_ON_RISING_FALLING 0x30000U /**< DMA enabled on rising and falling edges */ +#define PORT_PDD_INTERRUPT_ON_ZERO 0x80000U /**< Interrupt enabled on low level */ +#define PORT_PDD_INTERRUPT_ON_RISING 0x90000U /**< Interrupt enabled on rising edge */ +#define PORT_PDD_INTERRUPT_ON_FALLING 0xA0000U /**< Interrupt enabled on falling edge */ +#define PORT_PDD_INTERRUPT_ON_RISING_FALLING 0xB0000U /**< Interrupt enabled on rising and falling edges */ +#define PORT_PDD_INTERRUPT_ON_ONE 0xC0000U /**< Interrupt enabled on high level */ + +/* Constants for digital clock source setting */ +#define PORT_PDD_BUS_CLOCK 0U /**< Bus clock as filter clock source */ +#define PORT_PDD_LPO_CLOCK 0x1U /**< LPO clock as filter clock source */ + +/* Constants for Filter Division Set 1 */ +#define PORT_PDD_BUSCLK_DIV_2 0U /**< BUSCLK/2 */ +#define PORT_PDD_BUSCLK_DIV_4 0x1000000U /**< BUSCLK/4 */ +#define PORT_PDD_BUSCLK_DIV_8 0x2000000U /**< BUSCLK/8 */ +#define PORT_PDD_BUSCLK_DIV_16 0x3000000U /**< BUSCLK/16 */ + +/* Constants for Filter Division Set 2 */ +#define PORT_PDD_BUSCLK_DIV_32 0U /**< BUSCLK/32 */ +#define PORT_PDD_BUSCLK_DIV_64 0x4000000U /**< BUSCLK/64 */ +#define PORT_PDD_BUSCLK_DIV_128 0x8000000U /**< BUSCLK/128 */ +#define PORT_PDD_BUSCLK_DIV_256 0xC000000U /**< BUSCLK/256 */ +#define PORT_PDD_BUSCLK_DIV_512 0x10000000U /**< BUSCLK/512 */ +#define PORT_PDD_BUSCLK_DIV_1024 0x14000000U /**< BUSCLK/1024 */ +#define PORT_PDD_BUSCLK_DIV_2048 0x18000000U /**< BUSCLK/2048 */ +#define PORT_PDD_BUSCLK_DIV_4096 0x1C000000U /**< BUSCLK/4096 */ + +/* Constants for Filter Division Set 3 */ +#define PORT_PDD_LPOCLK 0U /**< LPOCLK */ +#define PORT_PDD_LPOCLK_DIV_2 0x20000000U /**< LPOCLK/2 */ +#define PORT_PDD_LPOCLK_DIV_4 0x40000000U /**< LPOCLK/4 */ +#define PORT_PDD_LPOCLK_DIV_8 0x60000000U /**< LPOCLK/8 */ +#define PORT_PDD_LPOCLK_DIV_16 0x80000000U /**< LPOCLK/16 */ +#define PORT_PDD_LPOCLK_DIV_32 0xA0000000U /**< LPOCLK/32 */ +#define PORT_PDD_LPOCLK_DIV_64 0xC0000000U /**< LPOCLK/64 */ +#define PORT_PDD_LPOCLK_DIV_128 0xE0000000U /**< LPOCLK/128 */ + + +/* ---------------------------------------------------------------------------- + -- GetPinPullSelect + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets which pull resistor is selected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pull type selection" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPullSelect(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPullSelect(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPullSelect + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets pull type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param Type Pull type. This parameter is of "Constants for pull type + * selection" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPullSelect(_BASE_PTR, periphID, + * PORT_PDD_PULL_DOWN); + * @endcode + */ +#define PORT_PDD_SetPinPullSelect(PeripheralBase, PinIndex, Type) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PS_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinPullEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether pull resistor is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pull enabling/disabling" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPullEnable(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPullEnable(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPullEnable + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets pull type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of pull enable. This parameter is of "Constants + * for pull enabling/disabling" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPullEnable(_BASE_PTR, periphID, + * PORT_PDD_PULL_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinPullEnable(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinSlewRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how slew rate is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for slew rate setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinSlewRate(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinSlewRate(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_SRE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinSlewRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets slew rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of slew rate. This parameter is of "Constants + * for slew rate setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinSlewRate(_BASE_PTR, periphID, + * PORT_PDD_SLEW_RATE_FAST); + * @endcode + */ +#define PORT_PDD_SetPinSlewRate(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_SRE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinPassiveFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether passive filter is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for slew rate setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinPassiveFilter(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinPassiveFilter(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_PFE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinPassiveFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets passive filter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of passive filter. This parameter is of + * "Constants for slew rate setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinPassiveFilter(_BASE_PTR, periphID, + * PORT_PDD_PASSIVE_FILTER_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinPassiveFilter(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_PFE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinOpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets whether open drain is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for open drain setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinOpenDrain(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinOpenDrain(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_ODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinOpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets open drain. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of open drain. This parameter is of "Constants + * for open drain setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinOpenDrain(_BASE_PTR, periphID, + * PORT_PDD_OPEN_DRAIN_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinOpenDrain(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_ODE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinDriverStrength + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how drive strength is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for drive strength setting" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinDriverStrength(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinDriverStrength(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_DSE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinDriveStrength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets drive strength. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of drive strength. This parameter is of + * "Constants for drive strength setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinDriveStrength(_BASE_PTR, periphID, + * PORT_PDD_DRIVE_STRENGTH_LOW); + * @endcode + */ +#define PORT_PDD_SetPinDriveStrength(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_DSE_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinMuxControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how mux control is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for mux control setting" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinMuxControl(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinMuxControl(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_MUX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinMuxControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets mux control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of Mux control. This parameter is of "Constants + * for mux control setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinMuxControl(_BASE_PTR, periphID, + * PORT_PDD_MUX_CONTROL_DISABLE); + * @endcode + */ +#define PORT_PDD_SetPinMuxControl(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_MUX_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinControlLock + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how pin lock is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for pin lock setting" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinControlLock(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinControlLock(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_LK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockPinControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Locks pin control such as settings of pull, slew rate, passive filter, + * open drain, mux control and pin lock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of pin lock. This parameter is of "Constants for + * pin lock setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_LockPinControl(_BASE_PTR, periphID, + * PORT_PDD_PIN_CONTROL_UNLOCK); + * @endcode + */ +#define PORT_PDD_LockPinControl(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_LK_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinInterruptConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how interupt configuration is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of "Constants for interrupt configuration setting" + * type. The value is cast to "uint32". + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_GetPinInterruptConfiguration(_BASE_PTR, periphID); + * @endcode + */ +#define PORT_PDD_GetPinInterruptConfiguration(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_IRQC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPinInterruptConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets interrupt configuration. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @param State Requested state of interrupt configuration. This parameter is of + * "Constants for interrupt configuration setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_SetPinInterruptConfiguration(_BASE_PTR, periphID, + * PORT_PDD_INTERRUPT_DMA_DISABLED); + * @endcode + */ +#define PORT_PDD_SetPinInterruptConfiguration(PeripheralBase, PinIndex, State) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) = \ + (uint32)(( \ + (uint32)(( \ + PORT_PCR_REG(PeripheralBase,(PinIndex))) & (( \ + (uint32)(~(uint32)PORT_PCR_IRQC_MASK)) & ( \ + (uint32)(~(uint32)PORT_PCR_ISF_MASK))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPinInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * uint32 result = PORT_PDD_GetPinInterruptFlag(_BASE_PTR, + * periphID); + * @endcode + */ +#define PORT_PDD_GetPinInterruptFlag(PeripheralBase, PinIndex) ( \ + (uint32)(PORT_PCR_REG(PeripheralBase,(PinIndex)) & PORT_PCR_ISF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_ISFR, PORTB_ISFR, + * PORTC_ISFR, PORTD_ISFR, PORTE_ISFR, PORTF_ISFR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetInterruptFlags(PeripheralBase) ( \ + PORT_ISFR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPinInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PinIndex Pin index inside the port. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PCR[PinIndex]. + * @par Example: + * @code + * PORT_PDD_ClearPinInterruptFlag(_BASE_PTR, periphID); + * @endcode + */ +#define PORT_PDD_ClearPinInterruptFlag(PeripheralBase, PinIndex) ( \ + PORT_PCR_REG(PeripheralBase,(PinIndex)) |= \ + PORT_PCR_ISF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins to clearing theirs interrupt flags. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_ISFR, PORTB_ISFR, + * PORTC_ISFR, PORTD_ISFR, PORTE_ISFR, PORTF_ISFR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_ClearInterruptFlags(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + PORT_ISFR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins of whole port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 0 within the port and the bit 31 corresponds with the pin + * which has index 31 within the port. This parameter is a 32-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCLR, + * PORTA_GPCHR, PORTB_GPCLR, PORTB_GPCHR, PORTC_GPCLR, PORTC_GPCHR, PORTD_GPCLR, + * PORTD_GPCHR, PORTE_GPCLR, PORTE_GPCHR, PORTF_GPCLR, PORTF_GPCHR + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControl(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControl(PeripheralBase, Mask, Value) ( \ + (PORT_GPCLR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)((uint32)((uint32)(Mask) & 0xFFFFU) << PORT_GPCLR_GPWE_SHIFT)) | ( \ + (uint32)(Value)))), \ + (PORT_GPCHR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)((uint32)(Mask) & (uint32)(~(uint32)0xFFFFU))) | ( \ + (uint32)(Value)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControlLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins from low part of port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 0 within the port and the bit 15 corresponds with the pin + * which has index 15 within the port. This parameter is a 16-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCLR, + * PORTB_GPCLR, PORTC_GPCLR, PORTD_GPCLR, PORTE_GPCLR, PORTF_GPCLR (depending on + * the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControlLow(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControlLow(PeripheralBase, Mask, Value) ( \ + PORT_GPCLR_REG(PeripheralBase) = \ + (uint32)((uint32)((uint32)(Mask) << PORT_GPCLR_GPWE_SHIFT) | (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetGlobalPinControlHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets required pin control for required pins from high part of port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins in port where the bit 0 corresponds with the pin + * which has index 16 within the port and the bit 15 corresponds with the pin + * which has index 31 within the port. This parameter is a 16-bit value. + * @param Value Settings of pull, slew rate, passive filter, open drain, mux + * control and pin lock . This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_GPCHR, + * PORTB_GPCHR, PORTC_GPCHR, PORTD_GPCHR, PORTE_GPCHR, PORTF_GPCHR (depending on + * the peripheral). + * @par Example: + * @code + * PORT_PDD_SetGlobalPinControlHigh(_BASE_PTR, 1, 1); + * @endcode + */ +#define PORT_PDD_SetGlobalPinControlHigh(PeripheralBase, Mask, Value) ( \ + PORT_GPCHR_REG(PeripheralBase) = \ + (uint32)((uint32)((uint32)(Mask) << PORT_GPCHR_GPWE_SHIFT) | (uint32)(Value)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDigitalFilterStatusMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns enable status of digital filter for whole port. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_GetEnableDigitalFilterStatusMask(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetEnableDigitalFilterStatusMask(PeripheralBase) ( \ + PORT_DFER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDigitalFilters + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables digital filters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins. Use constants from group "Pin masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_EnableDigitalFilters(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_EnableDigitalFilters(PeripheralBase, Mask) ( \ + PORT_DFER_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDigitalFilters + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables digital filters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of pins. Use constants from group "Pin masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFER, PORTB_DFER, + * PORTC_DFER, PORTD_DFER, PORTE_DFER, PORTF_DFER (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_DisableDigitalFilters(_BASE_PTR, PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_DisableDigitalFilters(PeripheralBase, Mask) ( \ + PORT_DFER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets how filter clock source is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for digital clock source setting" type. + * The value is cast to "uint32". + * @remarks The macro accesses the following registers: PORTA_DFCR, PORTB_DFCR, + * PORTC_DFCR, PORTD_DFCR, PORTE_DFCR, PORTF_DFCR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterClockSource(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetFilterClockSource(PeripheralBase) ( \ + (uint32)(PORT_DFCR_REG(PeripheralBase) & PORT_DFCR_CS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of filter clock source. This parameter is of + * "Constants for digital clock source setting" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFCR, PORTB_DFCR, + * PORTC_DFCR, PORTD_DFCR, PORTE_DFCR, PORTF_DFCR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterClockSource(_BASE_PTR, + * PORT_PDD_BUS_CLOCK); + * @endcode + */ +#define PORT_PDD_SetFilterClockSource(PeripheralBase, State) ( \ + PORT_DFCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_DFCR_REG(PeripheralBase) & (uint32)(~(uint32)PORT_DFCR_CS_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns filter length in clock cycles. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORTA_DFWR, PORTB_DFWR, + * PORTC_DFWR, PORTD_DFWR, PORTE_DFWR, PORTF_DFWR (depending on the + * peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterLength(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_GetFilterLength(PeripheralBase) ( \ + PORT_DFWR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilterLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter length in clock cycles. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORTA_DFWR, PORTB_DFWR, + * PORTC_DFWR, PORTD_DFWR, PORTE_DFWR, PORTF_DFWR (depending on the + * peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterLength(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_SetFilterLength(PeripheralBase, Value) ( \ + PORT_DFWR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 1" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet1(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet1(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV1_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 1" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet1(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet1(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV1_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet1 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 1. This parameter is of "Constants for + * Filter Division Set 1" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet1(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_2); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet1(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV1_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 1. This parameter is of "Constants for + * Filter Division Set 1" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet1(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_2); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet1(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV1_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 2" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet2(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet2(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV2_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 2" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet2(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet2(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV2_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet2 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 2. This parameter is of "Constants for + * Filter Division Set 2" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet2(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_32); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet2(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV2_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 2. This parameter is of "Constants for + * Filter Division Set 2" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet2(_BASE_PTR, + * PORT_PDD_BUSCLK_DIV_32); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet2(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV2_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilterDivisionSet3 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Gets configuration of the Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 3" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet3(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet3(PeripheralBase) ( \ + (uint32)(PORT_IOFLT0_REG(PeripheralBase) & PORT_IOFLT0_FLTDIV3_MASK) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Gets configuration of the Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Constants for Filter Division Set 3" type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = PORT_PDD_GetFilterDivisionSet3(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_GetFilterDivisionSet3(PeripheralBase) ( \ + (uint32)(PORT_IOFLT_REG(PeripheralBase) & PORT_IOFLT_FLTDIV3_MASK) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetFilterDivisionSet3 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Configures Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 3. This parameter is of "Constants for + * Filter Division Set 3" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet3(_BASE_PTR, PORT_PDD_LPOCLK); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet3(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT0_FLTDIV3_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Configures Filter Division Set 3. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FilterDivision Filter division 3. This parameter is of "Constants for + * Filter Division Set 3" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT, PORT_IOFLT0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_SetFilterDivisionSet3(_BASE_PTR, PORT_PDD_LPOCLK); + * @endcode + */ + #define PORT_PDD_SetFilterDivisionSet3(PeripheralBase, FilterDivision) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)PORT_IOFLT_FLTDIV3_MASK)))) | ( \ + (uint32)(FilterDivision))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- GetFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter(PeripheralBase, Module) ( \ + (uint8)((uint8)(PORT_IOFLT_REG(PeripheralBase) >> (uint8)(Module)) & (uint8)0x3U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * PORT_PDD_SetFilter(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT0 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * PORT_PDD_WritePortFilterReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilterReg(PeripheralBase, Value) ( \ + PORT_IOFLT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilterReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilterReg(PeripheralBase) ( \ + PORT_IOFLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePullupLowPortMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Enables/Disables pullup resistors on low port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of low port pins to be disabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of low port pins to be enabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupLowPortMask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupLowPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE0_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables/Disables pullup resistors on low port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of low port pins to be disabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of low port pins to be enabled. Use constants + * from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupLowPortMask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupLowPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUEL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUEL_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WritePullupEnableLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Writes pullup enable low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * low port pins. Bit #0 of the mask controls pullup setting of the low + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 disables + * pullup for associated low port pin, bit value 1 enables pullup for + * associated low port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableLowReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableLowReg(PeripheralBase, Value) ( \ + PORT_PUE0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes pullup enable low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * low port pins. Bit #0 of the mask controls pullup setting of the low + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 disables + * pullup for associated low port pin, bit value 1 enables pullup for + * associated low port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableLowReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableLowReg(PeripheralBase, Value) ( \ + PORT_PUEL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPullupEnableLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Reads pullup enable configuration of the low port pins. Bit #0 of + * return value contains pullup setting of the low port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableLowReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableLowReg(PeripheralBase) ( \ + PORT_PUE0_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads pullup enable configuration of the low port pins. Bit #0 of + * return value contains pullup setting of the low port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEL, PORT_PUE0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableLowReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableLowReg(PeripheralBase) ( \ + PORT_PUEL_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnablePullupHighPortMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Enables/Disables pullup resistors on high port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupHighPortMask(_BASE_PTR, + * PORT_PDD_PIN_0, PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupHighPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUEH_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUEH_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Enables/Disables pullup resistors on high port pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_EnablePullupHighPortMask(_BASE_PTR, + * PORT_PDD_PIN_0, PORT_PDD_PIN_0); + * @endcode + */ + #define PORT_PDD_EnablePullupHighPortMask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE1_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- WritePullupEnableHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Writes pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableHighReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableHighReg(PeripheralBase, Value) ( \ + PORT_PUEH_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Writes pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * PORT_PDD_WritePullupEnableHighReg(_BASE_PTR, 1); + * @endcode + */ + #define PORT_PDD_WritePullupEnableHighReg(PeripheralBase, Value) ( \ + PORT_PUE1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- ReadPullupEnableHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642))) +/** + * @brief Reads pullup enable configuration of the high port pins. Bit #0 of + * return value contains pullup setting of the high port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableHighReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableHighReg(PeripheralBase) ( \ + PORT_PUEH_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ +/** + * @brief Reads pullup enable configuration of the high port pins. Bit #0 of + * return value contains pullup setting of the high port pin #0, bit #31 contains + * setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUEH, PORT_PUE1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPullupEnableHighReg(_BASE_PTR); + * @endcode + */ + #define PORT_PDD_ReadPullupEnableHighReg(PeripheralBase) ( \ + PORT_PUE1_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) */ + +/* ---------------------------------------------------------------------------- + -- EnableHighDriveMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables/Disables high current drive capability on port pins specified + * by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighDriveDisableMask Mask of pins with high drive to be disabled. Use + * constants from group "List of pins offering high drive capability". + * This parameter is 32 bits wide. + * @param HighDriveEnableMask Mask of pins with high drive to be enabled. Use + * constants from group "List of pins offering high drive capability". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_EnableHighDriveMask(_BASE_PTR, PORT_PDD_PTB5, + * PORT_PDD_PTB5); + * @endcode + */ + #define PORT_PDD_EnableHighDriveMask(PeripheralBase, HighDriveDisableMask, HighDriveEnableMask) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_HDRVE_REG(PeripheralBase) & (uint32)(~(uint32)(HighDriveDisableMask)))) | ( \ + (uint32)(HighDriveEnableMask))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ +/** + * @brief Enables/Disables high current drive capability on port pins specified + * by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighDriveDisableMask Mask of pins with high drive to be disabled. Use + * constants from group "List of pins offering high drive capability". + * This parameter is 32 bits wide. + * @param HighDriveEnableMask Mask of pins with high drive to be enabled. Use + * constants from group "List of pins offering high drive capability". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_EnableHighDriveMask(_BASE_PTR, PORT_PDD_PTB4, + * PORT_PDD_PTB4); + * @endcode + */ + #define PORT_PDD_EnableHighDriveMask(PeripheralBase, HighDriveDisableMask, HighDriveEnableMask) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_HDRVE_REG(PeripheralBase) & (uint32)(~(uint32)(HighDriveDisableMask)))) | ( \ + (uint32)(HighDriveEnableMask))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) */ + +/* ---------------------------------------------------------------------------- + -- WriteHighDriveEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes high drive enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new high drive enable setting + * for associated pins. Pins supporting high drive capability are defined + * by High drive pin list. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * PORT_PDD_WriteHighDriveEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WriteHighDriveEnableReg(PeripheralBase, Value) ( \ + PORT_HDRVE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadHighDriveEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads high drive enable configuration of the associated pins. Pins + * supporting high drive capability are defined by High drive pin list. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_HDRVE. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadHighDriveEnableReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadHighDriveEnableReg(PeripheralBase) ( \ + PORT_HDRVE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter 0 configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter0(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter0(PeripheralBase, Module) ( \ + (uint8)(( \ + (uint8)(PORT_IOFLT0_REG(PeripheralBase) >> (uint8)(Module))) & ( \ + (uint8)0x3U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets filter 1 configuration for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module. Use constants from group "Modules offering input pin + * filtering capability". This parameter is 5 bits wide. + * @return Use constants from group "Filter selection" for processing return + * value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * uint8 result = PORT_PDD_GetFilter1(_BASE_PTR, + * PORT_PDD_PTA); + * @endcode + */ +#define PORT_PDD_GetFilter1(PeripheralBase, Module) ( \ + (uint8)(( \ + (uint8)(PORT_IOFLT1_REG(PeripheralBase) >> (uint8)(Module))) & ( \ + (uint8)0x3U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter 0 for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * PORT_PDD_SetFilter0(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter0(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFilter1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets filter 1 for module input pins. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Module Module to be configured. Use constants from group "Modules + * offering input pin filtering capability". This parameter is 5 bits wide. + * @param Filter Selected filter. Use constants from group "Filter selection". + * This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * PORT_PDD_SetFilter1(_BASE_PTR, PORT_PDD_PTA, + * PORT_PDD_NO_FILTER); + * @endcode + */ +#define PORT_PDD_SetFilter1(PeripheralBase, Module, Filter) ( \ + PORT_IOFLT1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + PORT_IOFLT1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x3U << (uint8)(Module)))))) | ( \ + (uint32)((uint32)(Filter) << (uint8)(Module)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilter0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT1 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * PORT_PDD_WritePortFilter0Reg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilter0Reg(PeripheralBase, Value) ( \ + PORT_IOFLT0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePortFilter1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port filter 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written into IOFLT register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * PORT_PDD_WritePortFilter1Reg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePortFilter1Reg(PeripheralBase, Value) ( \ + PORT_IOFLT1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilter0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT0. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilter0Reg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilter0Reg(PeripheralBase) ( \ + PORT_IOFLT0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPortFilter1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port filter 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_IOFLT1. + * @par Example: + * @code + * uint32 result = PORT_PDD_ReadPortFilter1Reg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPortFilter1Reg(PeripheralBase) ( \ + PORT_IOFLT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePullupPort2Mask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/Disables pullup resistors on port 2 pins specified by mask + * parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param PullupDisableMask Mask of high port pins with pullup to be disabled. + * Use constants from group "Pin masks". This parameter is 32 bits wide. + * @param PullupEnableMask Mask of high port pins with pullup to be enabled. Use + * constants from group "Pin masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * PORT_PDD_EnablePullupPort2Mask(_BASE_PTR, PORT_PDD_PIN_0, + * PORT_PDD_PIN_0); + * @endcode + */ +#define PORT_PDD_EnablePullupPort2Mask(PeripheralBase, PullupDisableMask, PullupEnableMask) ( \ + PORT_PUE2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(PORT_PUE2_REG(PeripheralBase) & (uint32)(~(uint32)(PullupDisableMask)))) | ( \ + (uint32)(PullupEnableMask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePort2PullupEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes port 2 pullup enable high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying mask of the new pullup enable setting for + * high port pins. Bit #0 of the mask controls pullup setting of the high + * port pin #0, bit #31 controls setting of the pin #31. Bit value 0 + * disables pullup for associated high port pin, bit value 1 enables pullup for + * associated high port pin. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * PORT_PDD_WritePort2PullupEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define PORT_PDD_WritePort2PullupEnableReg(PeripheralBase, Value) ( \ + PORT_PUE2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPort2PullupEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads port 2 pullup enable configuration of the high port pins. Bit #0 + * of return value contains pullup setting of the high port pin #0, bit #31 + * contains setting of the pin #31. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: PORT_PUE2. + * @par Example: + * @code + * uint32 result = + * PORT_PDD_ReadPort2PullupEnableReg(_BASE_PTR); + * @endcode + */ +#define PORT_PDD_ReadPort2PullupEnableReg(PeripheralBase) ( \ + PORT_PUE2_REG(PeripheralBase) \ + ) +#endif /* #if defined(PORT_PDD_H_) */ + +/* PORT_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h new file mode 100644 index 0000000..b9ab2c0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/RTC_PDD.h @@ -0,0 +1,3576 @@ +/* + PDD layer implementation for peripheral type RTC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(RTC_PDD_H_) +#define RTC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error RTC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* RTC */ && \ + !defined(MCU_MK10D5) /* RTC */ && \ + !defined(MCU_MK10D7) /* RTC */ && \ + !defined(MCU_MK10F12) /* RTC */ && \ + !defined(MCU_MK10DZ10) /* RTC */ && \ + !defined(MCU_MK11D5) /* RTC */ && \ + !defined(MCU_MK11D5WS) /* RTC */ && \ + !defined(MCU_MK12D5) /* RTC */ && \ + !defined(MCU_MK20D10) /* RTC */ && \ + !defined(MCU_MK20D5) /* RTC */ && \ + !defined(MCU_MK20D7) /* RTC */ && \ + !defined(MCU_MK20F12) /* RTC */ && \ + !defined(MCU_MK20DZ10) /* RTC */ && \ + !defined(MCU_MK21D5) /* RTC */ && \ + !defined(MCU_MK21D5WS) /* RTC */ && \ + !defined(MCU_MK21F12) /* RTC */ && \ + !defined(MCU_MK21F12WS) /* RTC */ && \ + !defined(MCU_MK22D5) /* RTC */ && \ + !defined(MCU_MK22F12810) /* RTC */ && \ + !defined(MCU_MK22F12) /* RTC */ && \ + !defined(MCU_MK22F25612) /* RTC */ && \ + !defined(MCU_MK22F51212) /* RTC */ && \ + !defined(MCU_MK24F12) /* RTC */ && \ + !defined(MCU_MK30D10) /* RTC */ && \ + !defined(MCU_MK30D7) /* RTC */ && \ + !defined(MCU_MK30DZ10) /* RTC */ && \ + !defined(MCU_MK40D10) /* RTC */ && \ + !defined(MCU_MK40D7) /* RTC */ && \ + !defined(MCU_MK40DZ10) /* RTC */ && \ + !defined(MCU_MK40X256VMD100) /* RTC */ && \ + !defined(MCU_MK50D10) /* RTC */ && \ + !defined(MCU_MK50D7) /* RTC */ && \ + !defined(MCU_MK50DZ10) /* RTC */ && \ + !defined(MCU_MK51D10) /* RTC */ && \ + !defined(MCU_MK51D7) /* RTC */ && \ + !defined(MCU_MK51DZ10) /* RTC */ && \ + !defined(MCU_MK52D10) /* RTC */ && \ + !defined(MCU_MK52DZ10) /* RTC */ && \ + !defined(MCU_MK53D10) /* RTC */ && \ + !defined(MCU_MK53DZ10) /* RTC */ && \ + !defined(MCU_MK60D10) /* RTC */ && \ + !defined(MCU_MK60F12) /* RTC */ && \ + !defined(MCU_MK60F15) /* RTC */ && \ + !defined(MCU_MK60DZ10) /* RTC */ && \ + !defined(MCU_MK60N512VMD100) /* RTC */ && \ + !defined(MCU_MK61F12) /* RTC */ && \ + !defined(MCU_MK61F15) /* RTC */ && \ + !defined(MCU_MK61F12WS) /* RTC */ && \ + !defined(MCU_MK61F15WS) /* RTC */ && \ + !defined(MCU_MK63F12) /* RTC */ && \ + !defined(MCU_MK63F12WS) /* RTC */ && \ + !defined(MCU_MK64F12) /* RTC */ && \ + !defined(MCU_MK65F18) /* RTC */ && \ + !defined(MCU_MK65F18WS) /* RTC */ && \ + !defined(MCU_MK66F18) /* RTC */ && \ + !defined(MCU_MK70F12) /* RTC */ && \ + !defined(MCU_MK70F15) /* RTC */ && \ + !defined(MCU_MK70F12WS) /* RTC */ && \ + !defined(MCU_MK70F15WS) /* RTC */ && \ + !defined(MCU_MKL03Z4) /* RTC */ && \ + !defined(MCU_MKL04Z4) /* RTC */ && \ + !defined(MCU_MKL05Z4) /* RTC */ && \ + !defined(MCU_MKL14Z4) /* RTC */ && \ + !defined(MCU_MKL15Z4) /* RTC */ && \ + !defined(MCU_MKL16Z4) /* RTC */ && \ + !defined(MCU_MKL24Z4) /* RTC */ && \ + !defined(MCU_MKL25Z4) /* RTC */ && \ + !defined(MCU_MKL26Z4) /* RTC */ && \ + !defined(MCU_MKL34Z4) /* RTC */ && \ + !defined(MCU_MKL36Z4) /* RTC */ && \ + !defined(MCU_MKL46Z4) /* RTC */ && \ + !defined(MCU_MKW01Z4) /* RTC */ && \ + !defined(MCU_MKW21D5) /* RTC */ && \ + !defined(MCU_MKW21D5WS) /* RTC */ && \ + !defined(MCU_MKW22D5) /* RTC */ && \ + !defined(MCU_MKW22D5WS) /* RTC */ && \ + !defined(MCU_MKW24D5) /* RTC */ && \ + !defined(MCU_MKW24D5WS) /* RTC */ && \ + !defined(MCU_PCK20L4) /* RTC */ + // Unsupported MCU is active + #error RTC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/* Interrupt masks */ + #define RTC_PDD_MOF_INT RTC_SR_MOF_MASK /**< Monotonic overflow interrupt mask */ + #define RTC_PDD_TAF_INT RTC_SR_TAF_MASK /**< Alarm interrupt mask */ + #define RTC_PDD_TOF_INT RTC_SR_TOF_MASK /**< Timer overflow interrupt mask */ + #define RTC_PDD_TIF_INT RTC_SR_TIF_MASK /**< Time invalid interrupt mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +/* Interrupt masks */ + #define RTC_PDD_TAF_INT RTC_SR_TAF_MASK /**< Alarm interrupt mask */ + #define RTC_PDD_TOF_INT RTC_SR_TOF_MASK /**< Timer overflow interrupt mask */ + #define RTC_PDD_TIF_INT RTC_SR_TIF_MASK /**< Time invalid interrupt mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +#if (defined(MCU_MK65F18WS)) +/* Tamper interrupt masks */ + #define RTC_PDD_TMF_INT RTC_TDR_TMF_MASK /**< Test mode tamper interrupt mask */ + #define RTC_PDD_FSF_INT RTC_TDR_FSF_MASK /**< Flash security tamper interrupt mask */ + #define RTC_PDD_TTF_INT RTC_TDR_TTF_MASK /**< Temperature tamper interrupt mask */ + #define RTC_PDD_CTF_INT RTC_TDR_CTF_MASK /**< Clock tamper interrupt mask */ + #define RTC_PDD_VTF_INT RTC_TDR_VTF_MASK /**< Volatge tamper interrupt mask */ + +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS)) */ +/* Tamper interrupt masks */ + #define RTC_PDD_TMF_INT RTC_TDR_TMF_MASK /**< Test mode tamper interrupt mask */ + #define RTC_PDD_FSF_INT RTC_TDR_FSF_MASK /**< Flash security tamper interrupt mask */ + #define RTC_PDD_TTF_INT RTC_TDR_TTF_MASK /**< Temperature tamper interrupt mask */ + #define RTC_PDD_CTF_INT RTC_TDR_CTF_MASK /**< Clock tamper interrupt mask */ + #define RTC_PDD_VTF_INT RTC_TDR_VTF_MASK /**< Volatge tamper interrupt mask */ + #define RTC_PDD_DTF_INT RTC_TDR_DTF_MASK /**< DryIce tamper interrupt mask */ + +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS)) */ +/* WakeUpPinState constants */ +#define RTC_PDD_ASSERTED 0x8U /**< Pin is asserted */ +#define RTC_PDD_NOT_ASSERTED 0U /**< Pin is not asserted */ + + +/* ---------------------------------------------------------------------------- + -- ReadTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TSR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimeSecondsReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeSecondsReg(PeripheralBase) ( \ + RTC_TSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time seconds register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TSR. + * @par Example: + * @code + * RTC_PDD_WriteTimeSecondsReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeSecondsReg(PeripheralBase, Value) ( \ + RTC_TSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TPR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimePrescalerReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimePrescalerReg(PeripheralBase) ( \ + RTC_TPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time prescaler register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TPR. + * @par Example: + * @code + * RTC_PDD_WriteTimePrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimePrescalerReg(PeripheralBase, Value) ( \ + RTC_TPR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimeAlarmReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time alarm register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTimeAlarmReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeAlarmReg(PeripheralBase) ( \ + RTC_TAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeAlarmReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time alarm register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time alarm register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TAR. + * @par Example: + * @code + * RTC_PDD_WriteTimeAlarmReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeAlarmReg(PeripheralBase, Value) ( \ + RTC_TAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimeCompensationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Time compensation register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TCR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadTimeCompensationReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTimeCompensationReg(PeripheralBase) ( \ + RTC_TCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeCompensationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Time compensation register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Time compensation register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TCR. + * @par Example: + * @code + * RTC_PDD_WriteTimeCompensationReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTimeCompensationReg(PeripheralBase, Value) ( \ + RTC_TCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadControlReg(PeripheralBase) ( \ + RTC_CR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteControlReg(PeripheralBase, Value) ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUpdateMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables update mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableUpdateMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableUpdateMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_UM_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_UM_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSupervisorAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables supervisor accesss. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableSupervisorAccess(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableSupervisorAccess(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_SUP_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_SUP_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeupPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wakeup pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_EnableWakeupPin(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableWakeupPin(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_WPE_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))) : ( \ + RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_WPE_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceSwReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces the equivalent of a VBAT POR to the rest of the RTC module, + * except the access control registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_CR. + * @par Example: + * @code + * RTC_PDD_ForceSwReset(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ForceSwReset(PeripheralBase) ( \ + (RTC_CR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_CR_REG(PeripheralBase) | RTC_CR_SWR_MASK)) & ( \ + (uint32)(~(uint32)0x4000U)))), \ + (RTC_CR_REG(PeripheralBase) &= \ + (uint32)((uint32)(~(uint32)RTC_CR_SWR_MASK) & (uint32)(~(uint32)0x4000U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRtcInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the RTC interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetRtcInterruptMask(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetRtcInterruptMask(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRtcInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables RTC interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Imterrupt mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_SetRtcInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_SetRtcInterruptMask(PeripheralBase, Mask) ( \ + RTC_IER_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondsInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Seconds interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableSecondsInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableSecondsInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TSIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAlarmInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Alarm interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableAlarmInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableAlarmInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TAIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimeOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Time overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableTimeOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTimeOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TOIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTimeInvalidInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Time invalid interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableTimeInvalidInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTimeInvalidInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_TIIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSecondsInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Seconds interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableSecondsInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableSecondsInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TSIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAlarmInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Alarm interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableAlarmInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableAlarmInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TAIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTimeOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Time overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableTimeOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTimeOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTimeInvalidInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Time invalid interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableTimeInvalidInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTimeInvalidInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_TIIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWakeUpPinState + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets wake-up pin state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "WakeUpPinState constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_SetWakeUpPinState(_BASE_PTR, RTC_PDD_ASSERTED); + * @endcode + */ +#define RTC_PDD_SetWakeUpPinState(PeripheralBase, State) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(State) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadStatusReg(PeripheralBase) ( \ + RTC_SR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Status register. Use constants from group + * "Interrupt masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_WriteStatusReg(_BASE_PTR, RTC_PDD_MOF_INT); + * @endcode + */ + #define RTC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Status register. Use constants from group + * "Interrupt masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_WriteStatusReg(_BASE_PTR, RTC_PDD_TAF_INT); + * @endcode + */ + #define RTC_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + RTC_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK64F12)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables seconds counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * RTC_PDD_EnableCounter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableCounter(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_SR_REG(PeripheralBase) = \ + 0U) : ( \ + RTC_SR_REG(PeripheralBase) = \ + 0x10U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableCounterStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns zero if the Time counter is disabled else return non-zero + * value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_SR. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetEnableCounterStatus(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetEnableCounterStatus(PeripheralBase) ( \ + (uint32)(RTC_SR_REG(PeripheralBase) & RTC_SR_TCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadLockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Lock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadLockReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadLockReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteLockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Lock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Lock register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_WriteLockReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteLockReg(PeripheralBase, Value) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockStatusReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockStatusReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_SRL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockStatusReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockStatusReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_SRL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- LockControlReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockControlReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockControlReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_CRL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockControlReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockControlReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_CRL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- LockTimeComensationReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTimeComensationReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTimeComensationReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_TCL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTimeComensationReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTimeComensationReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TCL_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWriteAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Write access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadWriteAccessReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadWriteAccessReg(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWriteAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Write access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Write access register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_WriteWriteAccessReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteWriteAccessReg(PeripheralBase, Value) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptEnableRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_IERW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_IERW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableLockRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_LRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_LRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableStatusRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_SRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_SRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableControlRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_CRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_CRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeCompensationRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TCRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TCRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeAlarmRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TARW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TARW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimePrescalerRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TPRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TPRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeSecondsRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TSRW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TSRW_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadReadAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Read access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadReadAccessReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadReadAccessReg(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteReadAccessReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Read access register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Read access register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_WriteReadAccessReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteReadAccessReg(PeripheralBase, Value) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptEnableRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_IERR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableInterruptEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableInterruptEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_IERR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableLockRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_LRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableLockRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableLockRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_LRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableStatusRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_SRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableStatusRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableStatusRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_SRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableControlRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_CRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableControlRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableControlRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_CRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeCompensationRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TCRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeCompensationRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeCompensationRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TCRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeAlarmRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TARR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeAlarmRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeAlarmRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TARR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimePrescalerRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TPRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimePrescalerRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimePrescalerRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TPRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTimeSecondsRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TSRR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TSRR_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableMonotonicOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Monotonic counter overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_EnableMonotonicOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableMonotonicOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) |= \ + RTC_IER_MOIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicOverflowInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Monotonic counter overflow interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_IER. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicOverflowInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableMonotonicOverflowInterrupt(PeripheralBase) ( \ + RTC_IER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_IER_MOIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockMonotonicCounterHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MCHL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MCHL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockMonotonicCounterLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MCLL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MCLL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicEnableReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_MEL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockMonotonicEnableReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockMonotonicEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_MEL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockTamperTimeSecondsReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_LR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_LR_TTSL_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_LockTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TTSL_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTamperTimeSecondsReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper time seconds register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTSR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadTamperTimeSecondsReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperTimeSecondsReg(PeripheralBase) ( \ + RTC_TTSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTamperTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper time in seconds. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTSR. + * @par Example: + * @code + * uint32 result = RTC_PDD_GetTamperTime(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetTamperTime(PeripheralBase) ( \ + RTC_TTSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadMonotonicEnableReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicEnableReg(PeripheralBase) ( \ + RTC_MER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic enable register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicEnableReg(PeripheralBase, Value) ( \ + RTC_MER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMonotonicCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Monotonis counter counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * RTC_PDD_EnableMonotonicCounter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define RTC_PDD_EnableMonotonicCounter(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + RTC_MER_REG(PeripheralBase) = \ + 0U) : ( \ + RTC_MER_REG(PeripheralBase) = \ + 0x10U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMonotonicCounterEnableStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns zero if the Monotonic counter is disabled else return non-zero + * value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MER. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_GetMonotonicCounterEnableStatus(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetMonotonicCounterEnableStatus(PeripheralBase) ( \ + (uint32)(RTC_MER_REG(PeripheralBase) & RTC_MER_MCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MCHR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadMonotonicCounterHighReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicCounterHighReg(PeripheralBase) ( \ + RTC_MCHR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicCounterHigReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic counter high register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MCHR. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicCounterHigReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicCounterHigReg(PeripheralBase, Value) ( \ + RTC_MCHR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMonotonicCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Monotonic counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_MCLR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_ReadMonotonicCounterLowReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadMonotonicCounterLowReg(PeripheralBase) ( \ + RTC_MCLR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMonotonicCounterLowgReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Monotonic counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Monotonic counter low register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_MCLR. + * @par Example: + * @code + * RTC_PDD_WriteMonotonicCounterLowgReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteMonotonicCounterLowgReg(PeripheralBase, Value) ( \ + RTC_MCLR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterHighRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MCHW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MCHW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterLowRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MCLW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MCLW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicEnableRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_MERW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_MERW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTamperTimeSecondsRegWrite + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_WAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_WAR_TTSW_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegWrite(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TTSW_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterHighRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MCHR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterHighRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterHighRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MCHR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicCounterLowRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MCLR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicCounterLowRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicCounterLowRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MCLR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableMonotonicEnableRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_MERR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableMonotonicEnableRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableMonotonicEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_MERR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- DisableTamperTimeSecondsRegRead + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21F12)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F15)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(RTC_RAR_REG(PeripheralBase) & (uint32)(~(uint32)RTC_RAR_TTSR_MASK))) | ( \ + 0xF000U)) \ + ) +#else /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTimeSecondsRegRead(_BASE_PTR); + * @endcode + */ + #define RTC_PDD_DisableTamperTimeSecondsRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TTSR_MASK) \ + ) +#endif /* (defined(MCU_MK11D5WS)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- LockTamperInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperInterruptReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperInterruptReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TIL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperTrimReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperTrimReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperDetectReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperDetectReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TDL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LockTamperEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief The lock register is used to block write accesses to certain registers + * until the next VBAT_POR or software reset.Write accesses to a locked register + * are ignored and do not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_LR. + * @par Example: + * @code + * RTC_PDD_LockTamperEnableReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_LockTamperEnableReg(PeripheralBase) ( \ + RTC_LR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_LR_TEL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRtcTamperInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the RTC tamper interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * uint32 result = + * RTC_PDD_GetRtcTamperInterruptMask(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_GetRtcTamperInterruptMask(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRtcTamperInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables RTC tamper interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Imterrupt mask. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_SetRtcTamperInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_SetRtcTamperInterruptMask(PeripheralBase, Mask) ( \ + RTC_TIR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTestModeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Test mode interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableTestModeInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTestModeInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_TMIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashSecurityInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Flash security interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableFlashSecurityInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableFlashSecurityInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_FSIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTemperatureTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Temperature tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableTemperatureTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableTemperatureTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_TTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableClockTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Clock tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableClockTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableClockTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_CTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVolatgeTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Voltage tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableVolatgeTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableVolatgeTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_VTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDryIceTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DryIce tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_EnableDryIceTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_EnableDryIceTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) |= \ + RTC_TIR_DTIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTestModeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Test mode interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableTestModeInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTestModeInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_TMIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFlashSecurityInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Flash security interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableFlashSecurityInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableFlashSecurityInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_FSIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTemperatureTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Temperature tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableTemperatureTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTemperatureTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_TTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableClockTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Clock tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableClockTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableClockTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_CTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableVolatgeTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Voltage tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableVolatgeTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableVolatgeTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_VTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDryIceTamperInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DryIce tamper interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TIR. + * @par Example: + * @code + * RTC_PDD_DisableDryIceTamperInterrupt(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableDryIceTamperInterrupt(PeripheralBase) ( \ + RTC_TIR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_TIR_DTIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper detect register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TDR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTamperDetectReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperDetectReg(PeripheralBase) ( \ + RTC_TDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTamperDetectReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Tamper detect register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Tamper detect register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TDR. + * @par Example: + * @code + * RTC_PDD_WriteTamperDetectReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTamperDetectReg(PeripheralBase, Value) ( \ + RTC_TDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperInterruptRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperInterruptRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperInterruptRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TIRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperTrimRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTrimRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperTrimRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TTRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperDetectRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperDetectRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperDetectRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TDRW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperEnableRegWrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables write accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_WAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperEnableRegWrite(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperEnableRegWrite(PeripheralBase) ( \ + RTC_WAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_WAR_TERW_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Tamper trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RTC_TTR. + * @par Example: + * @code + * uint32 result = RTC_PDD_ReadTamperTrimReg(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_ReadTamperTrimReg(PeripheralBase) ( \ + RTC_TTR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTamperTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Tamper trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Tamper trim register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_TTR. + * @par Example: + * @code + * RTC_PDD_WriteTamperTrimReg(_BASE_PTR, 1); + * @endcode + */ +#define RTC_PDD_WriteTamperTrimReg(PeripheralBase, Value) ( \ + RTC_TTR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperInterruptRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperInterruptRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperInterruptRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TIRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperTrimRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperTrimRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperTrimRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TTRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperDetectRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperDetectRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperDetectRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TDRR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTamperEnableRegRead + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables read accesses to the register until the next chip system + * reset. When accesses are blocked the bus access is not seen in the VBAT power + * supply and does not generate a bus error. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: RTC_RAR. + * @par Example: + * @code + * RTC_PDD_DisableTamperEnableRegRead(_BASE_PTR); + * @endcode + */ +#define RTC_PDD_DisableTamperEnableRegRead(PeripheralBase) ( \ + RTC_RAR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)RTC_RAR_TERR_MASK) \ + ) +#endif /* #if defined(RTC_PDD_H_) */ + +/* RTC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h new file mode 100644 index 0000000..7b65a78 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SAI_PDD.h @@ -0,0 +1,4409 @@ +/* + PDD layer implementation for peripheral type I2S + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SAI_PDD_H_) +#define SAI_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error I2S PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* I2S0 */ && \ + !defined(MCU_MK10D5) /* I2S0 */ && \ + !defined(MCU_MK10D7) /* I2S0 */ && \ + !defined(MCU_MK10F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK11D5) /* I2S0 */ && \ + !defined(MCU_MK11D5WS) /* I2S0 */ && \ + !defined(MCU_MK12D5) /* I2S0 */ && \ + !defined(MCU_MK20D10) /* I2S0 */ && \ + !defined(MCU_MK20D5) /* I2S0 */ && \ + !defined(MCU_MK20D7) /* I2S0 */ && \ + !defined(MCU_MK20F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK21D5) /* I2S0 */ && \ + !defined(MCU_MK21D5WS) /* I2S0 */ && \ + !defined(MCU_MK21F12) /* I2S0 */ && \ + !defined(MCU_MK21F12WS) /* I2S0 */ && \ + !defined(MCU_MK22D5) /* I2S0 */ && \ + !defined(MCU_MK22F12810) /* I2S0 */ && \ + !defined(MCU_MK22F12) /* I2S0 */ && \ + !defined(MCU_MK22F25612) /* I2S0 */ && \ + !defined(MCU_MK22F51212) /* I2S0 */ && \ + !defined(MCU_MK24F12) /* I2S0 */ && \ + !defined(MCU_MK30D10) /* I2S0 */ && \ + !defined(MCU_MK30D7) /* I2S0 */ && \ + !defined(MCU_MK40D10) /* I2S0 */ && \ + !defined(MCU_MK40D7) /* I2S0 */ && \ + !defined(MCU_MK50D10) /* I2S0 */ && \ + !defined(MCU_MK50D7) /* I2S0 */ && \ + !defined(MCU_MK51D10) /* I2S0 */ && \ + !defined(MCU_MK51D7) /* I2S0 */ && \ + !defined(MCU_MK52D10) /* I2S0 */ && \ + !defined(MCU_MK53D10) /* I2S0 */ && \ + !defined(MCU_MK60D10) /* I2S0 */ && \ + !defined(MCU_MK60F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK60F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F12WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK61F15WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK63F12) /* I2S0 */ && \ + !defined(MCU_MK63F12WS) /* I2S0 */ && \ + !defined(MCU_MK64F12) /* I2S0 */ && \ + !defined(MCU_MK65F18) /* I2S0 */ && \ + !defined(MCU_MK65F18WS) /* I2S0 */ && \ + !defined(MCU_MK66F18) /* I2S0 */ && \ + !defined(MCU_MK70F12) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F15) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F12WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MK70F15WS) /* I2S0, I2S1 */ && \ + !defined(MCU_MKL16Z4) /* I2S0 */ && \ + !defined(MCU_MKL26Z4) /* I2S0 */ && \ + !defined(MCU_MKL36Z4) /* I2S0 */ && \ + !defined(MCU_MKL46Z4) /* I2S0 */ && \ + !defined(MCU_MKW01Z4) /* I2S0 */ && \ + !defined(MCU_MKW21D5) /* I2S0 */ && \ + !defined(MCU_MKW21D5WS) /* I2S0 */ && \ + !defined(MCU_MKW22D5) /* I2S0 */ && \ + !defined(MCU_MKW22D5WS) /* I2S0 */ && \ + !defined(MCU_MKW24D5) /* I2S0 */ && \ + !defined(MCU_MKW24D5WS) /* I2S0 */ && \ + !defined(MCU_PCK20L4) /* I2S0 */ + // Unsupported MCU is active + #error I2S PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter/receiver status flags constants. */ + #define I2S_PDD_WORD_START_FLAG I2S_TCSR_WSF_MASK /**< Word start flag. */ + #define I2S_PDD_SYNC_ERROR_FLAG I2S_TCSR_SEF_MASK /**< Sync error flag. */ + #define I2S_PDD_FIFO_ERROR_FLAG I2S_TCSR_FEF_MASK /**< FIFO error flag. */ + #define I2S_PDD_FIFO_WARNING_FLAG I2S_TCSR_FWF_MASK /**< FIFO warning flag. */ + #define I2S_PDD_ALL_INT_FLAG 0x1C0000U /**< All interrupt flags. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter/receiver status flags constants. */ + #define I2S_PDD_WORD_START_FLAG I2S_TCSR_WSF_MASK /**< Word start flag. */ + #define I2S_PDD_SYNC_ERROR_FLAG I2S_TCSR_SEF_MASK /**< Sync error flag. */ + #define I2S_PDD_FIFO_ERROR_FLAG I2S_TCSR_FEF_MASK /**< FIFO error flag. */ + #define I2S_PDD_FIFO_WARNING_FLAG I2S_TCSR_FWF_MASK /**< FIFO warning flag. */ + #define I2S_PDD_FIFO_REQUEST_FLAG I2S_TCSR_FRF_MASK /**< FIFO request flag. */ + #define I2S_PDD_ALL_INT_FLAG 0x1C0000U /**< All interrupt flags. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter/receiver interrupt enable/disable constants (for + EnableTxInterrupt, DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros). */ + #define I2S_PDD_WORD_START_INT I2S_TCSR_WSIE_MASK /**< Word start interrupt mask. */ + #define I2S_PDD_SYNC_ERROR_INT I2S_TCSR_SEIE_MASK /**< Sync error interrupt mask. */ + #define I2S_PDD_FIFO_ERROR_INT I2S_TCSR_FEIE_MASK /**< FIFO error interrupt mask. */ + #define I2S_PDD_FIFO_WARNING_INT I2S_TCSR_FWIE_MASK /**< FIFO warning interrupt mask. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter/receiver interrupt enable/disable constants (for + EnableTxInterrupt, DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros). */ + #define I2S_PDD_WORD_START_INT I2S_TCSR_WSIE_MASK /**< Word start interrupt mask. */ + #define I2S_PDD_SYNC_ERROR_INT I2S_TCSR_SEIE_MASK /**< Sync error interrupt mask. */ + #define I2S_PDD_FIFO_ERROR_INT I2S_TCSR_FEIE_MASK /**< FIFO error interrupt mask. */ + #define I2S_PDD_FIFO_WARNING_INT I2S_TCSR_FWIE_MASK /**< FIFO warning interrupt mask. */ + #define I2S_PDD_FIFO_REQUEST_INT I2S_TCSR_FRIE_MASK /**< FIFO request interrupt mask. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter watermark constants (for SetTxFifoWatermark macro). */ +#define I2S_PDD_TX_WATERMARK_VALUE_0 0U /**< Transmitter FIFO watermark 0 */ +#define I2S_PDD_TX_WATERMARK_VALUE_1 0x1U /**< Transmitter FIFO watermark 1 */ +#define I2S_PDD_TX_WATERMARK_VALUE_2 0x2U /**< Transmitter FIFO watermark 2 */ +#define I2S_PDD_TX_WATERMARK_VALUE_3 0x3U /**< Transmitter FIFO watermark 3 */ +#define I2S_PDD_TX_WATERMARK_VALUE_4 0x4U /**< Transmitter FIFO watermark 4 */ +#define I2S_PDD_TX_WATERMARK_VALUE_5 0x5U /**< Transmitter FIFO watermark 5 */ +#define I2S_PDD_TX_WATERMARK_VALUE_6 0x6U /**< Transmitter FIFO watermark 6 */ +#define I2S_PDD_TX_WATERMARK_VALUE_7 0x7U /**< Transmitter FIFO watermark 7 */ + +/* Clocking transmitter mode constants (for SetTxSynchronousMode macro). */ +#define I2S_PDD_TX_ASYNCHRONOUS_MODE 0U /**< Asynchronous mode. */ +#define I2S_PDD_TX_SYNC_WITH_RECEIVER 0x1U /**< Synchronous with receiver. */ +#define I2S_PDD_TX_SYNC_WITH_ANOTHER_TRANSMITTER 0x2U /**< Synchronous with another SAI transmitter. */ +#define I2S_PDD_TX_SYNC_WITH_ANOTHER_RECEIVER 0x3U /**< Synchronous with another SAI receiver. */ + +#if (defined(MCU_MKW01Z4)) +/* Clocking transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + macro). */ + #define I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE 0U /**< Asynchronous mode (external bit clock) or Bus Clock selected (internal bit clock). */ + #define I2S_PDD_TX_SYNC_MODE_EXTERNAL_OR_SAI_MCLK_CLK_SOURCE 0x1U /**< Synchronous with another SAI transmitter (external bit clock) or Master Clock selected (internal bit clock). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clocking transmitter mode constants (for SetTxBitClockSource, + SetRxBitClockSource macro). */ + #define I2S_PDD_BUS_CLOCK_SOURCE 0U /**< Bus clock selected. */ + #define I2S_PDD_MASTER_CLOCK_1_SOURCE 0x1U /**< Mclk output 1 source */ + #define I2S_PDD_MASTER_CLOCK_2_SOURCE 0x2U /**< Mclk output 2 source */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter or receiver word flag configuration constants. */ + #define I2S_PDD_WORD_FLAG_1 0U /**< Word flag is set on 1st word. */ + #define I2S_PDD_WORD_FLAG_2 0x1U /**< Word flag is set on 2nd word. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver word flag configuration constants. */ + #define I2S_PDD_WORD_FLAG_1 0U /**< Word flag is set on 1st word. */ + #define I2S_PDD_WORD_FLAG_2 0x1U /**< Word flag is set on 2nd word. */ + #define I2S_PDD_WORD_FLAG_3 0x2U /**< Word flag is set on 3rd word. */ + #define I2S_PDD_WORD_FLAG_4 0x3U /**< Word flag is set on 4th word. */ + #define I2S_PDD_WORD_FLAG_5 0x4U /**< Word flag is set on 5th word. */ + #define I2S_PDD_WORD_FLAG_6 0x5U /**< Word flag is set on 6th word. */ + #define I2S_PDD_WORD_FLAG_7 0x6U /**< Word flag is set on 7th word. */ + #define I2S_PDD_WORD_FLAG_8 0x7U /**< Word flag is set on 8th word. */ + #define I2S_PDD_WORD_FLAG_9 0x8U /**< Word flag is set on 9th word. */ + #define I2S_PDD_WORD_FLAG_10 0x9U /**< Word flag is set on 10th word. */ + #define I2S_PDD_WORD_FLAG_11 0xAU /**< Word flag is set on 11th word. */ + #define I2S_PDD_WORD_FLAG_12 0xBU /**< Word flag is set on 12th word. */ + #define I2S_PDD_WORD_FLAG_13 0xCU /**< Word flag is set on 13th word. */ + #define I2S_PDD_WORD_FLAG_14 0xDU /**< Word flag is set on 14th word. */ + #define I2S_PDD_WORD_FLAG_15 0xEU /**< Word flag is set on 15th word. */ + #define I2S_PDD_WORD_FLAG_16 0xFU /**< Word flag is set on 16th word. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* Transmitter or receiver frame size constants. */ + #define I2S_PDD_FRAME_SIZE_1 0U /**< 1 word per frame. */ + #define I2S_PDD_FRAME_SIZE_2 0x1U /**< 2 words per frame. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver frame size constants. */ + #define I2S_PDD_FRAME_SIZE_1 0U /**< 1 word per frame. */ + #define I2S_PDD_FRAME_SIZE_2 0x1U /**< 2 words per frame. */ + #define I2S_PDD_FRAME_SIZE_3 0x2U /**< 3 words per frame. */ + #define I2S_PDD_FRAME_SIZE_4 0x3U /**< 4 words per frame. */ + #define I2S_PDD_FRAME_SIZE_5 0x4U /**< 5 words per frame. */ + #define I2S_PDD_FRAME_SIZE_6 0x5U /**< 6 words per frame. */ + #define I2S_PDD_FRAME_SIZE_7 0x6U /**< 7 words per frame. */ + #define I2S_PDD_FRAME_SIZE_8 0x7U /**< 8 words per frame. */ + #define I2S_PDD_FRAME_SIZE_9 0x8U /**< 9 words per frame. */ + #define I2S_PDD_FRAME_SIZE_10 0x9U /**< 10 words per frame. */ + #define I2S_PDD_FRAME_SIZE_11 0xAU /**< 11 words per frame. */ + #define I2S_PDD_FRAME_SIZE_12 0xBU /**< 12 words per frame. */ + #define I2S_PDD_FRAME_SIZE_13 0xCU /**< 13 words per frame. */ + #define I2S_PDD_FRAME_SIZE_14 0xDU /**< 14 words per frame. */ + #define I2S_PDD_FRAME_SIZE_15 0xEU /**< 15 words per frame. */ + #define I2S_PDD_FRAME_SIZE_16 0xFU /**< 16 words per frame. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Transmitter or receiver sync width constants. */ +#define I2S_PDD_SYNC_WIDTH_1 0U /**< 1 bit clock. */ +#define I2S_PDD_SYNC_WIDTH_2 0x1U /**< 2 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_3 0x2U /**< 3 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_4 0x3U /**< 4 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_5 0x4U /**< 5 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_6 0x5U /**< 6 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_7 0x6U /**< 7 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_8 0x7U /**< 8 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_9 0x8U /**< 9 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_10 0x9U /**< 10 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_11 0xAU /**< 11 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_12 0xBU /**< 12 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_13 0xCU /**< 13 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_14 0xDU /**< 14 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_15 0xEU /**< 15 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_16 0xFU /**< 16 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_17 0x10U /**< 17 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_18 0x11U /**< 18 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_19 0x12U /**< 19 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_20 0x13U /**< 20 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_21 0x14U /**< 21 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_22 0x15U /**< 22 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_23 0x16U /**< 23 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_24 0x17U /**< 24 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_25 0x18U /**< 25 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_26 0x19U /**< 26 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_27 0x1AU /**< 27 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_28 0x1BU /**< 28 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_29 0x1CU /**< 29 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_30 0x1DU /**< 30 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_31 0x1EU /**< 31 bits clock. */ +#define I2S_PDD_SYNC_WIDTH_32 0x1FU /**< 32 bits clock. */ + +/* Transmitter or receiver word width (in bits) constants. */ +#define I2S_PDD_WORD_WIDTH_1 0U /**< 1 bit. */ +#define I2S_PDD_WORD_WIDTH_2 0x1U /**< 2 bits. */ +#define I2S_PDD_WORD_WIDTH_3 0x2U /**< 3 bits. */ +#define I2S_PDD_WORD_WIDTH_4 0x3U /**< 4 bits. */ +#define I2S_PDD_WORD_WIDTH_5 0x4U /**< 5 bits. */ +#define I2S_PDD_WORD_WIDTH_6 0x5U /**< 6 bits. */ +#define I2S_PDD_WORD_WIDTH_7 0x6U /**< 7 bits. */ +#define I2S_PDD_WORD_WIDTH_8 0x7U /**< 8 bits. */ +#define I2S_PDD_WORD_WIDTH_9 0x8U /**< 9 bits. */ +#define I2S_PDD_WORD_WIDTH_10 0x9U /**< 10 bits. */ +#define I2S_PDD_WORD_WIDTH_11 0xAU /**< 11 bits. */ +#define I2S_PDD_WORD_WIDTH_12 0xBU /**< 12 bits. */ +#define I2S_PDD_WORD_WIDTH_13 0xCU /**< 13 bits. */ +#define I2S_PDD_WORD_WIDTH_14 0xDU /**< 14 bits. */ +#define I2S_PDD_WORD_WIDTH_15 0xEU /**< 15 bits. */ +#define I2S_PDD_WORD_WIDTH_16 0xFU /**< 16 bits. */ +#define I2S_PDD_WORD_WIDTH_17 0x10U /**< 17 bits. */ +#define I2S_PDD_WORD_WIDTH_18 0x11U /**< 18 bits. */ +#define I2S_PDD_WORD_WIDTH_19 0x12U /**< 19 bits. */ +#define I2S_PDD_WORD_WIDTH_20 0x13U /**< 20 bits. */ +#define I2S_PDD_WORD_WIDTH_21 0x14U /**< 21 bits. */ +#define I2S_PDD_WORD_WIDTH_22 0x15U /**< 22 bits. */ +#define I2S_PDD_WORD_WIDTH_23 0x16U /**< 23 bits. */ +#define I2S_PDD_WORD_WIDTH_24 0x17U /**< 24 bits. */ +#define I2S_PDD_WORD_WIDTH_25 0x18U /**< 25 bits. */ +#define I2S_PDD_WORD_WIDTH_26 0x19U /**< 26 bits. */ +#define I2S_PDD_WORD_WIDTH_27 0x1AU /**< 27 bits. */ +#define I2S_PDD_WORD_WIDTH_28 0x1BU /**< 28 bits. */ +#define I2S_PDD_WORD_WIDTH_29 0x1CU /**< 29 bits. */ +#define I2S_PDD_WORD_WIDTH_30 0x1DU /**< 30 bits. */ +#define I2S_PDD_WORD_WIDTH_31 0x1EU /**< 31 bits. */ +#define I2S_PDD_WORD_WIDTH_32 0x1FU /**< 32 bits. */ + +/* Receiver watermark constants (for SetRxFifoWatermark macro). */ +#define I2S_PDD_RX_WATERMARK_VALUE_1 0U /**< Receiver FIFO watermark 1 */ +#define I2S_PDD_RX_WATERMARK_VALUE_2 0x1U /**< Receiver FIFO watermark 2 */ +#define I2S_PDD_RX_WATERMARK_VALUE_3 0x2U /**< Receiver FIFO watermark 3 */ +#define I2S_PDD_RX_WATERMARK_VALUE_4 0x3U /**< Receiver FIFO watermark 4 */ +#define I2S_PDD_RX_WATERMARK_VALUE_5 0x4U /**< Receiver FIFO watermark 5 */ +#define I2S_PDD_RX_WATERMARK_VALUE_6 0x5U /**< Receiver FIFO watermark 6 */ +#define I2S_PDD_RX_WATERMARK_VALUE_7 0x6U /**< Receiver FIFO watermark 7 */ +#define I2S_PDD_RX_WATERMARK_VALUE_8 0x7U /**< Receiver FIFO watermark 8 */ + +/* Clocking transmitter mode constants (for SetRxSynchronousMode macro). */ +#define I2S_PDD_RX_ASYNCHRONOUS_MODE 0U /**< Asynchronous mode. */ +#define I2S_PDD_RX_SYNC_WITH_TRANSMITTER 0x1U /**< Synchronous with receiver. */ +#define I2S_PDD_RX_SYNC_WITH_ANOTHER_RECEIVER 0x2U /**< Synchronous with another SAI transmitter. */ +#define I2S_PDD_RX_SYNC_WITH_ANOTHER_TRANSMITTER 0x3U /**< Synchronous with another SAI transmitter. */ + +/* Divider update status flag constant (for GetDividerUpdateFlag macro). */ +#define I2S_PDD_MCLK_DIVIDER_RATIO_UPDATED I2S_MCR_DUF_MASK /**< MCLK Divider ratio is updating on-the-fly. */ + +/* Transmitter internal logic bit clock input constants (for SetTxBitClockInput + macros). */ +#define I2S_PDD_INTERNAL_BIT_CLOCK 0U /**< No effect. */ +#define I2S_PDD_EXTERNAL_BIT_CLOCK 0x10000000U /**< Internal logic is clocked as if bit clock was externally generated. */ + +/* Transmitter bit clock polarity constants (for SetTxBitClockPolarity, + SetRxBitClockPolarity macros). */ +#define I2S_PDD_BIT_CLOCK_ACTIVE_HIGH 0U /**< Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). */ +#define I2S_PDD_BIT_CLOCK_ACTIVE_LOW 0x2000000U /**< Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). */ + +/* Bit clock direction constants (for SetTxBitClockDirection, + SetRxBitClockDirection macros). */ +#define I2S_PDD_BIT_CLOCK_OUTPUT 0x1000000U /**< Bit clock is generated internally (master mode). */ +#define I2S_PDD_BIT_CLOCK_INPUT 0U /**< Bit clock is generated externally (slave mode). */ + +/* Data channel mask constant constants (for EnableRx/TxDataChannels, + DisableRx/TxDataChannels macros). */ +#define I2S_PDD_DATA_CHANNEL_0 0x1U /**< Data channel 0 mask */ +#define I2S_PDD_DATA_CHANNEL_1 0x2U /**< Data channel 1 mask */ + +/* Bit shift order constants (for SetTxShiftDirection, SetRxShiftDirection + macros). */ +#define I2S_PDD_MSB_FIRST 0U /**< MBS is transmitted/received first. */ +#define I2S_PDD_LSB_FIRST 0x10U /**< LBS is transmitted/received first. */ + +/* Frame sync position in stream constants (for SetTxFrameSyncEarly, + SetRxFrameSyncEarly macros). */ +#define I2S_PDD_FIRST_BIT_OF_DATA 0U /**< Asserts with the first bit of the frame. */ +#define I2S_PDD_ONE_BIT_BEFORE_DATA 0x8U /**< Asserts one bit before the first bit of the frame. */ + +/* Frame sync active polarity constants (for SetTxFrameSyncPolarity, + SetRxFrameSyncPolarity macros). */ +#define I2S_PDD_FRAME_SYNC_ACTIVE_HIGH 0U /**< Active high. */ +#define I2S_PDD_FRAME_SYNC_ACTIVE_LOW 0x2U /**< Active low. */ + +/* Frame sync PIN direction constants (for SetTxFrameSyncDirection, + SetRxFrameSyncDirection macros). */ +#define I2S_PDD_FRAME_SYNC_OUTPUT 0x1U /**< Generated internally (master mode). */ +#define I2S_PDD_FRAME_SYNC_INPUT 0U /**< Generated externally (slave mode). */ + +/* Receiver internal logic bit clock input constants (for SetRxBitClockInput + macros). */ +#define I2S_PDD_INTERNAL_BIT_CLOCK 0U /**< No effect. */ +#define I2S_PDD_EXTERNAL_BIT_CLOCK 0x10000000U /**< Internal logic is clocked as if bit clock was externally generated. */ + +#if (defined(MCU_MK22D5)) +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_PLL_FLL_CLK 0x3000000U /**< MCG PLL/FLL out. */ + #define I2S_PDD_PLL_CLK 0x3000000U /**< MCG PLL out. */ + +#elif ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_ER_OSC1 0x2000000U /**< ER OSC1 */ + #define I2S_PDD_PLL_CLK 0x3000000U /**< MCG PLL out. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Mclk clock input constants (for SetMclkClockSource macro). */ + #define I2S_PDD_SYSTEM_CLK 0U /**< System Clock. */ + #define I2S_PDD_ER_OSC0 0x1000000U /**< ER OSC0 */ + #define I2S_PDD_PLL_FLL_CLK 0x3000000U /**< MCG PLL/FLL out. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTxDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2S_TCSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)I2S_TCSR_TE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) : ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCSR_REG(PeripheralBase) | I2S_TCSR_TE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDeviceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transmitter enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxDeviceState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxDeviceState(PeripheralBase) ( \ + ((uint32)(I2S_TCSR_REG(PeripheralBase) & I2S_TCSR_TE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmitter operation in stop mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in stop mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInStopMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxInStopMode(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_STOPE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_STOPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmitter operation in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in debug mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxInDebugMode(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_DBGE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_DBGE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxBitClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmit bit clock, separately from the + * transmit enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Tx bit clock. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxBitClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxBitClock(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_BCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxBitClockState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transmitter bit clock enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxBitClockState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxBitClockState(PeripheralBase) ( \ + ((uint32)(I2S_TCSR_REG(PeripheralBase) & I2S_TCSR_BCE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- TxFifoReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the transmitter FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_TxFifoReset(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_TxFifoReset(PeripheralBase) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCSR_REG(PeripheralBase) | I2S_TCSR_FR_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the internal transmitter logic including the FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested transmitter reset state. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxSoftwareReset(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxSoftwareReset(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SR_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_SR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetTxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_TCSR_WSF_MASK) | (( \ + I2S_TCSR_SEF_MASK) | (( \ + I2S_TCSR_FEF_MASK) | ( \ + I2S_TCSR_FWF_MASK)))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetTxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_TCSR_WSF_MASK) | (( \ + I2S_TCSR_SEF_MASK) | (( \ + I2S_TCSR_FEF_MASK) | (( \ + I2S_TCSR_FWF_MASK) | ( \ + I2S_TCSR_FRF_MASK))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearTxInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears transmitter interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Transmitter/receiver status flags constants.". This parameter is 32 bits + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_ClearTxInterruptFlags(_BASE_PTR, + * I2S_PDD_WORD_START_FLAG); + * @endcode + */ +#define I2S_PDD_ClearTxInterruptFlags(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_TCSR_WSF_MASK | (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables transmitter interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_EnableTxInterrupt(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_TCSR_WSF_MASK | (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables transmitter interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableTxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_DisableTxInterrupt(PeripheralBase, Mask) ( \ + I2S_TCSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxFifoWarningDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter FIFO warning DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO warning DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxFifoWarningDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxFifoWarningDma(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FWDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_TCSR_FWDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxFifoRequestDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter FIFO request DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO request DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxFifoRequestDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxFifoRequestDma(PeripheralBase, State) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_TCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FRDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_TCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_TCSR_WSF_MASK))))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxControlReg(PeripheralBase) ( \ + I2S_TCSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCSR, I2S1_TCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxControlReg(PeripheralBase, Value) ( \ + I2S_TCSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter FIFO watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmitter FIFO watermark. Use constants from group + * "Transmitter watermark constants (for SetTxFifoWatermark macro).". This parameter + * is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWatermark(_BASE_PTR, + * I2S_PDD_TX_WATERMARK_VALUE_0); + * @endcode + */ +#define I2S_PDD_SetTxFifoWatermark(PeripheralBase, Value) ( \ + I2S_TCR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR1_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR1_TFW_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration1Reg(PeripheralBase) ( \ + I2S_TCR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 1 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR1, I2S1_TCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration1Reg(PeripheralBase, Value) ( \ + I2S_TCR1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxSynchronousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter asynchronous or synchronous modes of operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Transmit synchronous mode value. Use constants from group + * "Clocking transmitter mode constants (for SetTxSynchronousMode macro).". This + * parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxSynchronousMode(_BASE_PTR, + * I2S_PDD_TX_ASYNCHRONOUS_MODE); + * @endcode + */ +#define I2S_PDD_SetTxSynchronousMode(PeripheralBase, Mode) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_SYNC_MASK))) | ( \ + (uint32)((uint32)(Mode) << I2S_TCR2_SYNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxBitClockSwap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter swap bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of swap bit clock source. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxBitClockSwap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxBitClockSwap(PeripheralBase, State) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCS_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_TCR2_BCS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter internal logic bit clock input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Transmitter internal logic bit clock input value. The user + * should use one from the enumerated values. This parameter is of + * "Transmitter internal logic bit clock input constants (for SetTxBitClockInput + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockInput(_BASE_PTR, + * I2S_PDD_INTERNAL_BIT_CLOCK); + * @endcode + */ +#define I2S_PDD_SetTxBitClockInput(PeripheralBase, Source) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCI_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Transmit bit clock source value. Use constants from group + * "Clocking transmitter mode constants (for SetTxBitClockSource, + * SetRxBitClockSource macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockSource(_BASE_PTR, + * I2S_PDD_BUS_CLOCK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetTxBitClockSource(PeripheralBase, ClkSource) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_MSEL_MASK))) | ( \ + (uint32)((uint32)(ClkSource) << I2S_TCR2_MSEL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transmitter bit clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Transmitter bit clock polarity value. The user should use one + * from the enumerated values. This parameter is of "Transmitter bit + * clock polarity constants (for SetTxBitClockPolarity, SetRxBitClockPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockPolarity(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetTxBitClockPolarity(PeripheralBase, Polarity) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter bit clock PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Transmitter bit clock direction value. The user should use + * one from the enumerated values. This parameter is of "Bit clock + * direction constants (for SetTxBitClockDirection, SetRxBitClockDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockDirection(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetTxBitClockDirection(PeripheralBase, Direction) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_BCD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxBitClockDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter bit clock divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Bit clock divider value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxBitClockDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetTxBitClockDivider(PeripheralBase, Value) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_DIV_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration2Reg(PeripheralBase) ( \ + I2S_TCR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 2 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2, I2S1_TCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration2Reg(PeripheralBase, Value) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the transmitter data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Transmitter data channel mask value. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableTxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_EnableTxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_TCR3_REG(PeripheralBase) |= \ + (uint32)((uint32)(Mask) << I2S_TCR3_TCE_SHIFT) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the transmitter data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Transmitter data channel mask value. This parameter is a 2-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableTxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_DisableTxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_TCR3_REG(PeripheralBase) &= \ + (uint32)(~(uint32)((uint32)(Mask) << I2S_TCR3_TCE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoWordFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 1 bit + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 4 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetTxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration3Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration3Reg(PeripheralBase) ( \ + I2S_TCR3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 3 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3, I2S1_TCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration3Reg(PeripheralBase, Value) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetTxFrameSize(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_FRSZ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetTxSyncWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the length of the frame sync in number of bit clocks. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Sync width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxSyncWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxSyncWidth(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_SYWD_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR4_SYWD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxShiftDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Specifies whether the LSB or the MSB is transmitted first. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Bit shift order value. The user should use one from the + * enumerated values. This parameter is of "Bit shift order constants (for + * SetTxShiftDirection, SetRxShiftDirection macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxShiftDirection(_BASE_PTR, I2S_PDD_MSB_FIRST); + * @endcode + */ +#define I2S_PDD_SetTxShiftDirection(PeripheralBase, Direction) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_MF_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncEarly + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync position in stream. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SyncEarly Frame sync position in stream value. The user should use one + * from the enumerated values. This parameter is of "Frame sync position + * in stream constants (for SetTxFrameSyncEarly, SetRxFrameSyncEarly + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncEarly(_BASE_PTR, + * I2S_PDD_FIRST_BIT_OF_DATA); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncEarly(PeripheralBase, SyncEarly) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSE_MASK))) | ( \ + (uint32)(SyncEarly))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync active polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Active frame sync polarity value. The user should use one + * from the enumerated values. This parameter is of "Frame sync active + * polarity constants (for SetTxFrameSyncPolarity, SetRxFrameSyncPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncPolarity(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncPolarity(PeripheralBase, Polarity) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFrameSyncDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Frame sync PIN direction value. The user should use one from + * the enumerated values. This parameter is of "Frame sync PIN direction + * constants (for SetTxFrameSyncDirection, SetRxFrameSyncDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFrameSyncDirection(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetTxFrameSyncDirection(PeripheralBase, Direction) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR4_FSD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration4Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration4Reg(PeripheralBase) ( \ + I2S_TCR4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 4 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR4, I2S1_TCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration4Reg(PeripheralBase, Value) ( \ + I2S_TCR4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxWordNWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in each word, for each word except the + * first in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word N width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxWordNWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxWordNWidth(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_WNW_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_WNW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxWord0Width + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in the first word in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word 0 width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxWord0Width(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetTxWord0Width(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_W0W_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_W0W_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFirstBitShifted + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the bit index for the first bit transmitted for each word + * in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value First bit shifted index [0..31]. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetTxFirstBitShifted(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetTxFirstBitShifted(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR5_FBT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_TCR5_FBT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads transmit configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadTxConfiguration5Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadTxConfiguration5Reg(PeripheralBase) ( \ + I2S_TCR5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit + * configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit configuration 5 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR5, I2S1_TCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxConfiguration5Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxConfiguration5Reg(PeripheralBase, Value) ( \ + I2S_TCR5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxDataChannelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data channel register defined by Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @param Data Value stored to the data channel register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TDR[Index]. + * @par Example: + * @code + * I2S_PDD_WriteTxDataChannelReg(_BASE_PTR, periphID, 1); + * @endcode + */ +#define I2S_PDD_WriteTxDataChannelReg(PeripheralBase, Index, Data) ( \ + I2S_TDR_REG(PeripheralBase,(Index)) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDataChannelRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TDR[Index]. + * @par Example: + * @code + * uint32 result = + * I2S_PDD_GetTxDataChannelRegAddress(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxDataChannelRegAddress(PeripheralBase, Index) ( \ + (uint32)&I2S_TDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxChannelWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for transmit data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetTxChannelWriteFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxChannelWriteFifoPointer(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(I2S_TFR_REG(PeripheralBase,(Index)) & I2S_TFR_WFP_MASK)) >> ( \ + I2S_TFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxChannelReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for transmit data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetTxChannelReadFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetTxChannelReadFifoPointer(PeripheralBase, Index) ( \ + (uint8)(I2S_TFR_REG(PeripheralBase,(Index)) & I2S_TFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Reads transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFR[Index], TFR[] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxFifoReg(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_ReadTxFifoReg(PeripheralBase) ( \ + I2S_TFR_REG(PeripheralBase,0U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Reads transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TFR[Index], TFR[] + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadTxFifoReg(_BASE_PTR, + * periphID); + * @endcode + */ + #define I2S_PDD_ReadTxFifoReg(PeripheralBase, Index) ( \ + I2S_TFR_REG(PeripheralBase,(Index)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteTxTimeSlotMaskReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TMR_TWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TMR_TWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Transmit word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the transmit time slot register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteTxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteTxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into transmit mask + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit mask register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TMR, I2S1_TMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteTxMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxMaskReg(PeripheralBase, Value) ( \ + I2S_TMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + I2S_RCSR_REG(PeripheralBase) &= \ + (uint32)(( \ + (uint32)(~(uint32)I2S_RCSR_RE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) : ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCSR_REG(PeripheralBase) | I2S_RCSR_RE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK)))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDeviceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns receiver enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxDeviceState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxDeviceState(PeripheralBase) ( \ + ((uint32)(I2S_RCSR_REG(PeripheralBase) & I2S_RCSR_RE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxBitClockState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns receiver bit clock enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxBitClockState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxBitClockState(PeripheralBase) ( \ + ((uint32)(I2S_RCSR_REG(PeripheralBase) & I2S_RCSR_BCE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInStopMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receiver operation in stop mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in stop mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInStopMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxInStopMode(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_STOPE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_STOPE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receiver operation in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state in debug mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxInDebugMode(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_DBGE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_DBGE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxBitClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receive bit clock, separately from the receive + * enable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of Rx bit clock. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxBitClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxBitClock(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_BCE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_BCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- RxFifoReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the receiver FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_RxFifoReset(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_RxFifoReset(PeripheralBase) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCSR_REG(PeripheralBase) | I2S_RCSR_FR_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the internal receiver logic including the FIFO pointers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested receiver reset state. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxSoftwareReset(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxSoftwareReset(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SR_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_SR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxInterruptFlags + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetRxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_RCSR_WSF_MASK) | (( \ + I2S_RCSR_SEF_MASK) | (( \ + I2S_RCSR_FEF_MASK) | ( \ + I2S_RCSR_FWF_MASK)))))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the value of the status flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Transmitter/receiver status flags + * constants." for processing return value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxInterruptFlags(_BASE_PTR); + * @endcode + */ + #define I2S_PDD_GetRxInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + I2S_RCSR_WSF_MASK) | (( \ + I2S_RCSR_SEF_MASK) | (( \ + I2S_RCSR_FEF_MASK) | (( \ + I2S_RCSR_FWF_MASK) | ( \ + I2S_RCSR_FRF_MASK))))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearRxInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears receiver interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "Transmitter/receiver status flags constants.". This parameter is 32 bits + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_ClearRxInterruptFlags(_BASE_PTR, + * I2S_PDD_WORD_START_FLAG); + * @endcode + */ +#define I2S_PDD_ClearRxInterruptFlags(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_RCSR_WSF_MASK | (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables receiver interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_EnableRxInterrupt(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(I2S_RCSR_WSF_MASK | (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK)))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables receiver interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group + * "Transmitter/receiver interrupt enable/disable constants (for EnableTxInterrupt, + * DisableTxInterrupt, EnableRxInterrupt and DisableRxInterrupt macros).". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableRxInterrupt(_BASE_PTR, + * I2S_PDD_WORD_START_INT); + * @endcode + */ +#define I2S_PDD_DisableRxInterrupt(PeripheralBase, Mask) ( \ + I2S_RCSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoWarningDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver FIFO warning DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO warning DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxFifoWarningDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxFifoWarningDma(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FWDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)((uint32)(State) << I2S_RCSR_FWDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoRequestDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver FIFO request DMA. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO request DMA. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxFifoRequestDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxFifoRequestDma(PeripheralBase, State) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + I2S_RCSR_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FRDE_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_FEF_MASK)) & (( \ + (uint32)(~(uint32)I2S_RCSR_SEF_MASK)) & ( \ + (uint32)(~(uint32)I2S_RCSR_WSF_MASK))))))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxControlReg(PeripheralBase) ( \ + I2S_RCSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCSR, I2S1_RCSR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxControlReg(PeripheralBase, Value) ( \ + I2S_RCSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver FIFO watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receiver FIFO watermark. Use constants from group "Receiver + * watermark constants (for SetRxFifoWatermark macro).". This parameter is 3 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWatermark(_BASE_PTR, + * I2S_PDD_RX_WATERMARK_VALUE_1); + * @endcode + */ +#define I2S_PDD_SetRxFifoWatermark(PeripheralBase, Value) ( \ + I2S_RCR1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR1_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR1_RFW_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration1Reg(PeripheralBase) ( \ + I2S_RCR1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 1 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR1, I2S1_RCR1 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration1Reg(PeripheralBase, Value) ( \ + I2S_RCR1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxSynchronousMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver asynchronous or synchronous modes of operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Receive synchronous mode value. Use constants from group + * "Clocking transmitter mode constants (for SetRxSynchronousMode macro).". This + * parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxSynchronousMode(_BASE_PTR, + * I2S_PDD_RX_ASYNCHRONOUS_MODE); + * @endcode + */ +#define I2S_PDD_SetRxSynchronousMode(PeripheralBase, Mode) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_SYNC_MASK))) | ( \ + (uint32)((uint32)(Mode) << I2S_RCR2_SYNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxBitClockSwap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver swap bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of swap bit clock source. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxBitClockSwap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxBitClockSwap(PeripheralBase, State) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCS_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_RCR2_BCS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockInput + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver internal logic bit clock input. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Receiver internal logic bit clock input value. The user should + * use one from the enumerated values. This parameter is of "Receiver + * internal logic bit clock input constants (for SetRxBitClockInput macros)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockInput(_BASE_PTR, + * I2S_PDD_INTERNAL_BIT_CLOCK); + * @endcode + */ +#define I2S_PDD_SetRxBitClockInput(PeripheralBase, Source) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCI_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver bit clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource Receive bit clock source value. Use constants from group + * "Clocking transmitter mode constants (for SetTxBitClockSource, + * SetRxBitClockSource macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockSource(_BASE_PTR, + * I2S_PDD_BUS_CLOCK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetRxBitClockSource(PeripheralBase, ClkSource) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_MSEL_MASK))) | ( \ + (uint32)((uint32)(ClkSource) << I2S_RCR2_MSEL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets receiver bit clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Receiver bit clock polarity value. The user should use one + * from the enumerated values. This parameter is of "Transmitter bit clock + * polarity constants (for SetTxBitClockPolarity, SetRxBitClockPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockPolarity(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetRxBitClockPolarity(PeripheralBase, Polarity) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver bit clock PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Receiver bit clock direction value. The user should use one + * from the enumerated values. This parameter is of "Bit clock direction + * constants (for SetTxBitClockDirection, SetRxBitClockDirection macros)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockDirection(_BASE_PTR, + * I2S_PDD_BIT_CLOCK_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetRxBitClockDirection(PeripheralBase, Direction) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_BCD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxBitClockDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the receiver bit clock divider value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Bit clock divider value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxBitClockDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetRxBitClockDivider(PeripheralBase, Value) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_DIV_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration2Reg(PeripheralBase) ( \ + I2S_RCR2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 2 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2, I2S1_RCR2 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration2Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration2Reg(PeripheralBase, Value) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the receiver data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Receiver data channel mask value. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableRxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_EnableRxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_RCR3_REG(PeripheralBase) |= \ + (uint32)((uint32)(Mask) << I2S_RCR3_RCE_SHIFT) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxDataChannelMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the receiver data channel defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Receiver data channel mask value. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_DisableRxDataChannelMask(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_DisableRxDataChannelMask(PeripheralBase, Mask) ( \ + I2S_RCR3_REG(PeripheralBase) &= \ + (uint32)(~(uint32)((uint32)(Mask) << I2S_RCR3_RCE_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoWordFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 1 bit + * wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 4 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures which word the start of word flag is set. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word flag configuration. Use constants from group "Transmitter + * or receiver word flag configuration constants.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFifoWordFlag(_BASE_PTR, I2S_PDD_WORD_FLAG_1); + * @endcode + */ + #define I2S_PDD_SetRxFifoWordFlag(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_WDFL_MASK))) | ( \ + (uint32)(Value))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration3Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration3Reg(PeripheralBase) ( \ + I2S_RCR3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 3 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3, I2S1_RCR3 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration3Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration3Reg(PeripheralBase, Value) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSize + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 4 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the number of words in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Frame size. Use constants from group "Transmitter or receiver + * frame size constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSize(_BASE_PTR, I2S_PDD_FRAME_SIZE_1); + * @endcode + */ + #define I2S_PDD_SetRxFrameSize(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FRSZ_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_FRSZ_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetRxSyncWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the length of the frame sync in number of bit clocks. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Sync width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxSyncWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxSyncWidth(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_SYWD_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR4_SYWD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxShiftDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Specifies whether the LSB or the MSB is received first. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Bit shift order value. The user should use one from the + * enumerated values. This parameter is of "Bit shift order constants (for + * SetTxShiftDirection, SetRxShiftDirection macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxShiftDirection(_BASE_PTR, I2S_PDD_MSB_FIRST); + * @endcode + */ +#define I2S_PDD_SetRxShiftDirection(PeripheralBase, Direction) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_MF_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncEarly + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync position in stream. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param SyncEarly Frame sync position in stream value. The user should use one + * from the enumerated values. This parameter is of "Frame sync position + * in stream constants (for SetTxFrameSyncEarly, SetRxFrameSyncEarly + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncEarly(_BASE_PTR, + * I2S_PDD_FIRST_BIT_OF_DATA); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncEarly(PeripheralBase, SyncEarly) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSE_MASK))) | ( \ + (uint32)(SyncEarly))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync active polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Active frame sync polarity value. The user should use one + * from the enumerated values. This parameter is of "Frame sync active + * polarity constants (for SetTxFrameSyncPolarity, SetRxFrameSyncPolarity + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncPolarity(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_ACTIVE_HIGH); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncPolarity(PeripheralBase, Polarity) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSP_MASK))) | ( \ + (uint32)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFrameSyncDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame sync PIN direction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Frame sync PIN direction value. The user should use one from + * the enumerated values. This parameter is of "Frame sync PIN direction + * constants (for SetTxFrameSyncDirection, SetRxFrameSyncDirection + * macros)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFrameSyncDirection(_BASE_PTR, + * I2S_PDD_FRAME_SYNC_OUTPUT); + * @endcode + */ +#define I2S_PDD_SetRxFrameSyncDirection(PeripheralBase, Direction) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR4_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR4_FSD_MASK))) | ( \ + (uint32)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration4Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration4Reg(PeripheralBase) ( \ + I2S_RCR4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 4 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR4, I2S1_RCR4 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration4Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration4Reg(PeripheralBase, Value) ( \ + I2S_RCR4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxWordNWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in each word, for each word except the + * first in the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word N width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxWordNWidth(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxWordNWidth(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_WNW_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_WNW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxWord0Width + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the number of bits in the first word in each frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Word 0 width. Use constants from group "Transmitter or receiver + * sync width constants.". This parameter is 5 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxWord0Width(_BASE_PTR, I2S_PDD_SYNC_WIDTH_1); + * @endcode + */ +#define I2S_PDD_SetRxWord0Width(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_W0W_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_W0W_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFirstBitShifted + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures the bit index for the first bit received for each word in + * the frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value First bit shifted index [0..31]. This parameter is a 5-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetRxFirstBitShifted(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetRxFirstBitShifted(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR5_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR5_FBT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_RCR5_FBT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * I2S_PDD_ReadRxConfiguration5Reg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxConfiguration5Reg(PeripheralBase) ( \ + I2S_RCR5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxConfiguration5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive + * configuration 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive configuration 5 register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR5, I2S1_RCR5 + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxConfiguration5Reg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxConfiguration5Reg(PeripheralBase, Value) ( \ + I2S_RCR5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxDataChannelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[Index]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxDataChannelReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define I2S_PDD_ReadRxDataChannelReg(PeripheralBase, Index) ( \ + I2S_RDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataChannelRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register defined by Index + * parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[Index]. + * @par Example: + * @code + * uint32 result = + * I2S_PDD_GetRxDataChannelRegAddress(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxDataChannelRegAddress(PeripheralBase, Index) ( \ + (uint32)&I2S_RDR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxChannelWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for receive data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetRxChannelWriteFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxChannelWriteFifoPointer(PeripheralBase, Index) ( \ + (uint8)(( \ + (uint32)(I2S_RFR_REG(PeripheralBase,(Index)) & I2S_RFR_WFP_MASK)) >> ( \ + I2S_RFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxChannelReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for receive data channel defined by + * Index parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint8 result = + * I2S_PDD_GetRxChannelReadFifoPointer(_BASE_PTR, periphID); + * @endcode + */ +#define I2S_PDD_GetRxChannelReadFifoPointer(PeripheralBase, Index) ( \ + (uint8)(I2S_RFR_REG(PeripheralBase,(Index)) & I2S_RFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxChannelFifoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Data channel index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RFR[Index]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxChannelFifoReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define I2S_PDD_ReadRxChannelFifoReg(PeripheralBase, Index) ( \ + I2S_RFR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxTimeSlotMaskReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RMR_RWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#elif ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RMR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RMR_RWM_MASK))) | ( \ + (uint32)(Mask))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Receive word mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Value stored to the receive time slot register. This parameter is + * a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxTimeSlotMaskReg(_BASE_PTR, 1); + * @endcode + */ + #define I2S_PDD_WriteRxTimeSlotMaskReg(PeripheralBase, Mask) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive mask register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxMaskReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxMaskReg(PeripheralBase) ( \ + I2S_RMR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxMaskReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into receive mask + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the receive mask register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RMR, I2S1_RMR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteRxMaskReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteRxMaskReg(PeripheralBase, Value) ( \ + I2S_RMR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDividerUpdateFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns divider update status flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Divider update status flag constant (for + * GetDividerUpdateFlag macro)." for processing return value. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_GetDividerUpdateFlag(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetDividerUpdateFlag(PeripheralBase) ( \ + I2S_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMclkDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the MCLK divider and configures the SAI_MCLK pin as + * an output. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of master clock divider. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_EnableMclkDivider(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableMclkDivider(PeripheralBase, State) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MCR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MCR_MOE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_MCR_MOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMclkDividerState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns Mclk divider enable/disable status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = I2S_PDD_GetMclkDividerState(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetMclkDividerState(PeripheralBase) ( \ + ((uint32)(I2S_MCR_REG(PeripheralBase) & I2S_MCR_MOE_MASK) == 0U) ? ( \ + PDD_DISABLE) : ( \ + PDD_ENABLE) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock input to the MCLK Divider. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source value. The user should use one from the enumerated + * values. This parameter is of "Mclk clock input constants (for + * SetMclkClockSource macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkClockSource(_BASE_PTR, I2S_PDD_SYSTEM_CLK); + * @endcode + */ +#define I2S_PDD_SetMclkClockSource(PeripheralBase, Source) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MCR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MCR_MICS_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMclkControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads master clock control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadMclkControlReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadMclkControlReg(PeripheralBase) ( \ + I2S_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into master clock + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the master clock control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MCR, I2S1_MCR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkControlReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkControlReg(PeripheralBase, Value) ( \ + I2S_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkFraction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Mclk fraction factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Fraction value[0..255]. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkFraction(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetMclkFraction(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MDR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MDR_FRACT_MASK))) | ( \ + (uint32)((uint32)(Value) << I2S_MDR_FRACT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMclkDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the Mclk divider factor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Divider value[0..4095]. This parameter is a 12-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_SetMclkDivider(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_SetMclkDivider(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_MDR_REG(PeripheralBase) & (uint32)(~(uint32)I2S_MDR_DIVIDE_MASK))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkDivideRatioReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the Mclk divide ratio register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the Mclk divide ration register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkDivideRatioReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkDivideRatioReg(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMclkDivideReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads master clock divide register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadMclkDivideReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadMclkDivideReg(PeripheralBase) ( \ + I2S_MDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMclkDivideReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into master clock + * divide register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the master clock divide register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_MDR, I2S1_MDR + * (depending on the peripheral). + * @par Example: + * @code + * I2S_PDD_WriteMclkDivideReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteMclkDivideReg(PeripheralBase, Value) ( \ + I2S_MDR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTxDataChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the transmitter data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter data channel. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR3. + * @par Example: + * @code + * I2S_PDD_EnableTxDataChannel(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableTxDataChannel(PeripheralBase, State) ( \ + I2S_TCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR3_TCE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_TCR3_TCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value stored to the data register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: TDR[]. + * @par Example: + * @code + * I2S_PDD_WriteTxDataReg(_BASE_PTR, 1); + * @endcode + */ +#define I2S_PDD_WriteTxDataReg(PeripheralBase, Data) ( \ + I2S_TDR_REG(PeripheralBase,0U) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxDataRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: TDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_GetTxDataRegAddress(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxDataRegAddress(PeripheralBase) ( \ + (uint32)&I2S_TDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for transmit data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxWriteFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxWriteFifoPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(I2S_TFR_REG(PeripheralBase,0U) & I2S_TFR_WFP_MASK)) >> ( \ + I2S_TFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for transmit data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: TFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetTxReadFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetTxReadFifoPointer(PeripheralBase) ( \ + (uint8)(I2S_TFR_REG(PeripheralBase,0U) & I2S_TFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxDataChannel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the receiver data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver data channel. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR3. + * @par Example: + * @code + * I2S_PDD_EnableRxDataChannel(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define I2S_PDD_EnableRxDataChannel(PeripheralBase, State) ( \ + I2S_RCR3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR3_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR3_RCE_MASK))) | ( \ + (uint32)((uint32)(State) << I2S_RCR3_RCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxDataReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxDataReg(PeripheralBase) ( \ + I2S_RDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataRegAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the data channel register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RDR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_GetRxDataRegAddress(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxDataRegAddress(PeripheralBase) ( \ + (uint32)&I2S_RDR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxWriteFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO write pointer for receive data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxWriteFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxWriteFifoPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(I2S_RFR_REG(PeripheralBase,0U) & I2S_RFR_WFP_MASK)) >> ( \ + I2S_RFR_WFP_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxReadFifoPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the FIFO read pointer for receive data channel. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint8 result = I2S_PDD_GetRxReadFifoPointer(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_GetRxReadFifoPointer(PeripheralBase) ( \ + (uint8)(I2S_RFR_REG(PeripheralBase,0U) & I2S_RFR_RFP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: RFR[]. + * @par Example: + * @code + * uint32 result = I2S_PDD_ReadRxFifoReg(_BASE_PTR); + * @endcode + */ +#define I2S_PDD_ReadRxFifoReg(PeripheralBase) ( \ + I2S_RFR_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxClockingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock transmit clock mode and source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkMode Transmit clock mode value. Use constants from group "Clocking + * transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + * macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_TCR2. + * @par Example: + * @code + * I2S_PDD_SetTxClockingMode(_BASE_PTR, + * I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetTxClockingMode(PeripheralBase, ClkMode) ( \ + I2S_TCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_TCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_TCR2_CLKMODE_MASK))) | ( \ + (uint32)((uint32)(ClkMode) << I2S_TCR2_CLKMODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxClockingMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock receive clock mode and source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkMode Transmit clock mode value. Use constants from group "Clocking + * transmitter mode constants (for SetTxClockingMode, SetRxClockingMode + * macro).". This parameter is 2 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: I2S0_RCR2. + * @par Example: + * @code + * I2S_PDD_SetRxClockingMode(_BASE_PTR, + * I2S_PDD_TX_ASYNC_MODE_EXTERNAL_OR_BUS_CLK_SOURCE ); + * @endcode + */ +#define I2S_PDD_SetRxClockingMode(PeripheralBase, ClkMode) ( \ + I2S_RCR2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(I2S_RCR2_REG(PeripheralBase) & (uint32)(~(uint32)I2S_RCR2_CLKMODE_MASK))) | ( \ + (uint32)((uint32)(ClkMode) << I2S_RCR2_CLKMODE_SHIFT))) \ + ) +#endif /* #if defined(SAI_PDD_H_) */ + +/* SAI_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h new file mode 100644 index 0000000..5050213 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SDHC_PDD.h @@ -0,0 +1,2413 @@ +/* + PDD layer implementation for peripheral type SDHC + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SDHC_PDD_H_) +#define SDHC_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SDHC PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SDHC */ && \ + !defined(MCU_MK10F12) /* SDHC */ && \ + !defined(MCU_MK10DZ10) /* SDHC */ && \ + !defined(MCU_MK20D10) /* SDHC */ && \ + !defined(MCU_MK20F12) /* SDHC */ && \ + !defined(MCU_MK20DZ10) /* SDHC */ && \ + !defined(MCU_MK21F12) /* SDHC */ && \ + !defined(MCU_MK21F12WS) /* SDHC */ && \ + !defined(MCU_MK22F12) /* SDHC */ && \ + !defined(MCU_MK24F12) /* SDHC */ && \ + !defined(MCU_MK30D10) /* SDHC */ && \ + !defined(MCU_MK30DZ10) /* SDHC */ && \ + !defined(MCU_MK40D10) /* SDHC */ && \ + !defined(MCU_MK40DZ10) /* SDHC */ && \ + !defined(MCU_MK40X256VMD100) /* SDHC */ && \ + !defined(MCU_MK50D10) /* SDHC */ && \ + !defined(MCU_MK50DZ10) /* SDHC */ && \ + !defined(MCU_MK51D10) /* SDHC */ && \ + !defined(MCU_MK51DZ10) /* SDHC */ && \ + !defined(MCU_MK52D10) /* SDHC */ && \ + !defined(MCU_MK52DZ10) /* SDHC */ && \ + !defined(MCU_MK53D10) /* SDHC */ && \ + !defined(MCU_MK53DZ10) /* SDHC */ && \ + !defined(MCU_MK60D10) /* SDHC */ && \ + !defined(MCU_MK60F12) /* SDHC */ && \ + !defined(MCU_MK60F15) /* SDHC */ && \ + !defined(MCU_MK60DZ10) /* SDHC */ && \ + !defined(MCU_MK60N512VMD100) /* SDHC */ && \ + !defined(MCU_MK61F12) /* SDHC */ && \ + !defined(MCU_MK61F15) /* SDHC */ && \ + !defined(MCU_MK61F12WS) /* SDHC */ && \ + !defined(MCU_MK61F15WS) /* SDHC */ && \ + !defined(MCU_MK63F12) /* SDHC */ && \ + !defined(MCU_MK63F12WS) /* SDHC */ && \ + !defined(MCU_MK64F12) /* SDHC */ && \ + !defined(MCU_MK65F18) /* SDHC */ && \ + !defined(MCU_MK65F18WS) /* SDHC */ && \ + !defined(MCU_MK66F18) /* SDHC */ && \ + !defined(MCU_MK70F12) /* SDHC */ && \ + !defined(MCU_MK70F15) /* SDHC */ && \ + !defined(MCU_MK70F12WS) /* SDHC */ && \ + !defined(MCU_MK70F15WS) /* SDHC */ + // Unsupported MCU is active + #error SDHC PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Transfer DMA usage */ +#define SDHC_PDD_ENABLE_DMA SDHC_XFERTYP_DMAEN_MASK /**< Enable DMA. */ +#define SDHC_PDD_DISABLE_DMA 0U /**< Disable DMA. */ + +/* Transfer block count */ +#define SDHC_PDD_ENABLE_BLOCK_COUNT SDHC_XFERTYP_BCEN_MASK /**< Enable block count. */ +#define SDHC_PDD_DISABLE_BLOCK_COUNT 0U /**< Disable block count. */ + +/* Transfer auto CMD12 */ +#define SDHC_PDD_ENABLE_AUTO_CMD12 SDHC_XFERTYP_AC12EN_MASK /**< Enable auto CMD12. */ +#define SDHC_PDD_DISABLE_AUTO_CMD12 0U /**< Disable auto CMD12. */ + +/* Transfer data direction */ +#define SDHC_PDD_DATA_READ SDHC_XFERTYP_DTDSEL_MASK /**< Data read. */ +#define SDHC_PDD_DATA_WRITE 0U /**< Data write. */ + +/* Transfer multi/single block */ +#define SDHC_PDD_SINGLE_BLOCK 0U /**< Single block. */ +#define SDHC_PDD_MULTIPLE_BLOCK SDHC_XFERTYP_MSBSEL_MASK /**< Multiple block. */ + +/* Command response type */ +#define SDHC_PDD_NO_RESPONSE 0U /**< No response. */ +#define SDHC_PDD_RESPONSE_LENGTH_136 0x10000U /**< Response of length 136 bit. */ +#define SDHC_PDD_RESPONSE_LENGTH_48 0x20000U /**< Response of length 48 bit. */ +#define SDHC_PDD_RESPONSE_LENGTH_48_BUSY_CHECK 0x30000U /**< Response of length 48 bit with busy check. */ + +/* Command CRC check */ +#define SDHC_PDD_ENABLE_CRC_CHECK SDHC_XFERTYP_CCCEN_MASK /**< Enable CRC check. */ +#define SDHC_PDD_DISABLE_CRC_CHECK 0U /**< Disable CRC check. */ + +/* Command index check */ +#define SDHC_PDD_ENABLE_INDEX_CHECK SDHC_XFERTYP_CICEN_MASK /**< Enable index check. */ +#define SDHC_PDD_DISABLE_INDEX_CHECK 0U /**< Disable index check. */ + +/* Command data present */ +#define SDHC_PDD_DATA_PRESENT SDHC_XFERTYP_DPSEL_MASK /**< Data present. */ +#define SDHC_PDD_NO_DATA_PRESENT 0U /**< No data present. */ + +/* Command type */ +#define SDHC_PDD_NORMAL_CMD 0U /**< Normal command. */ +#define SDHC_PDD_SUSPEND_CMD 0x400000U /**< Suspend command. */ +#define SDHC_PDD_RESUME_CMD 0x800000U /**< Resume command. */ +#define SDHC_PDD_ABORT_CMD 0xC00000U /**< Abort command. */ + +/* Command class 0 - basic */ +#define SDHC_PDD_CMD0_GO_IDLE_STATE 0U /**< Go idle state. */ +#define SDHC_PDD_CMD1_SEND_OP_COND 0x1U /**< Send operation conditions. */ +#define SDHC_PDD_CMD2_ALL_SEND_CID 0x2U /**< All send CID (card identification register). */ +#define SDHC_PDD_CMD3_SET_RELATIVE_ADDR 0x3U /**< Set/send relative address. */ +#define SDHC_PDD_CMD4_SET_DSR 0x4U /**< Set DSR (driver stage register). */ +#define SDHC_PDD_CMD5_IO_SEND_OP_COND 0x5U /**< Send IO conditions. */ +#define SDHC_PDD_CMD6_SWITCH 0x6U /**< Switch function. */ +#define SDHC_PDD_CMD7_SELECT_CARD 0x7U /**< Select/deselect card. */ +#define SDHC_PDD_CMD8_SEND_EXT_CSD 0x8U /**< Send EXT_CSD (extended card specific data register). */ +#define SDHC_PDD_CMD9_SEND_CSD 0x9U /**< Send CSD (card specific data register). */ +#define SDHC_PDD_CMD10_SEND_CID 0xAU /**< Send CID (card identification register). */ +#define SDHC_PDD_CMD12_STOP_TRANSMISSION 0xCU /**< Stop transmission. */ +#define SDHC_PDD_CMD13_SEND_STATUS 0xDU /**< Send status. */ +#define SDHC_PDD_CMD14_BUS_TEST_READ 0xEU /**< Bus test pattern read. */ +#define SDHC_PDD_CMD15_GO_INACTIVE_STATE 0xFU /**< Go inactive state. */ +#define SDHC_PDD_CMD19_BUS_TEST_WRITE 0x13U /**< Bus test pattern write. */ + +/* Command class 1 - stream read */ +#define SDHC_PDD_CMD11_READ_DAT_UNTIL_STOP 0xBU /**< Read data until stop. */ + +/* Command class 2 - block read */ +#define SDHC_PDD_CMD16_SET_BLOCKLEN 0x10U /**< Set block length. */ +#define SDHC_PDD_CMD17_READ_SINGLE_BLOCK 0x11U /**< Read single block. */ +#define SDHC_PDD_CMD18_READ_MULTIPLE_BLOCK 0x12U /**< Read multiple block. */ + +/* Command class 3 - stream write */ +#define SDHC_PDD_CMD20_WRITE_DAT_UNTIL_STOP 0x14U /**< Write data until stop. */ + +/* Command class 4 - block write */ +#define SDHC_PDD_CMD24_WRITE_BLOCK 0x18U /**< Write block. */ +#define SDHC_PDD_CMD25_WRITE_MULTIPLE_BLOCK 0x19U /**< Write multiple block. */ +#define SDHC_PDD_CMD26_PROGRAM_CID 0x1AU /**< Program CID (card identification register). */ +#define SDHC_PDD_CMD27_PROGRAM_CSD 0x1BU /**< Program CSD (card specific data register). */ + +/* Command class 5 - erase */ +#define SDHC_PDD_CMD32_TAG_SECTOR_START 0x20U /**< Tag sector start [SD]. */ +#define SDHC_PDD_CMD33_TAG_SECTOR_END 0x21U /**< Tag sector end [SD]. */ +#define SDHC_PDD_CMD34_UNTAG_SECTOR 0x22U /**< Untag sector. */ +#define SDHC_PDD_CMD35_TAG_ERASE_GROUP_START 0x23U /**< Tag erase group start [MMC]. */ +#define SDHC_PDD_CMD36_TAG_ERASE_GROUP_END 0x24U /**< Tag erase group end [MMC]. */ +#define SDHC_PDD_CMD37_UNTAG_ERASE_GROUP 0x25U /**< Untag erase group. */ +#define SDHC_PDD_CMD38_ERASE 0x26U /**< Erase. */ + +/* Command class 6 - write protection */ +#define SDHC_PDD_CMD28_SET_WRITE_PROT 0x1CU /**< Set write protection. */ +#define SDHC_PDD_CMD29_CLR_WRITE_PROT 0x1DU /**< Clear write protection. */ +#define SDHC_PDD_CMD30_SEND_WRITE_PROT 0x1EU /**< Send write protection. */ + +/* Command class 7 - lock card */ +#define SDHC_PDD_CMD42_LOCK_UNLOCK 0x2AU /**< Lock/unlock card. */ + +/* Command class 8 - application specific */ +#define SDHC_PDD_CMD55_APP_CMD 0x37U /**< Application specific command. */ +#define SDHC_PDD_CMD56_GEN_CMD 0x38U /**< General purpose command. */ + +/* Command class 9 - IO mode */ +#define SDHC_PDD_CMD39_FAST_IO 0x27U /**< Fast IO [MMC]. */ +#define SDHC_PDD_CMD40_GO_IRQ_STATE 0x28U /**< Go IRQ state [MMC]. */ +#define SDHC_PDD_CMD52_IO_RW_DIRECT 0x34U /**< IO direct read/write [SD]. */ +#define SDHC_PDD_CMD53_IO_RW_EXTENDED 0x35U /**< IO extended read/write [SD]. */ + +/* Command class 10 - switch [SD] */ +#define SDHC_PDD_CMD60_RW_MULTIPLE_REG 0x3CU /**< Read/write multiple register. */ +#define SDHC_PDD_CMD61_RW_MULTIPLE_BLOCK 0x3DU /**< Read/write multiple block. */ + +/* Application specific commands [SD] */ +#define SDHC_PDD_ACMD6_SET_BUS_WIDTH 0x6U /**< Set bus width. */ +#define SDHC_PDD_ACMD13_SD_STATUS 0xDU /**< Send SD status. */ +#define SDHC_PDD_ACMD22_SEND_NUM_WR_SECTORS 0x16U /**< Send number of written sectors. */ +#define SDHC_PDD_ACMD23_SET_WR_BLK_ERASE_COUNT 0x17U /**< Set write block erase count. */ +#define SDHC_PDD_ACMD41_SD_APP_OP_COND 0x29U /**< Send operational conditions. */ +#define SDHC_PDD_ACMD42_SET_CLR_CARD_DETECT 0x2AU /**< Set/clear card detection. */ +#define SDHC_PDD_ACMD51_SEND_SCR 0x33U /**< Send SCR (SD configuration register). */ + +/* Clock divider values */ +#define SDHC_PDD_BASE_DIV_BY_2 0x1U /**< Base clock divided by 2. */ +#define SDHC_PDD_BASE_DIV_BY_4 0x2U /**< Base clock divided by 4. */ +#define SDHC_PDD_BASE_DIV_BY_8 0x4U /**< Base clock divided by 8. */ +#define SDHC_PDD_BASE_DIV_BY_16 0x8U /**< Base clock divided by 16. */ +#define SDHC_PDD_BASE_DIV_BY_32 0x10U /**< Base clock divided by 32. */ +#define SDHC_PDD_BASE_DIV_BY_64 0x20U /**< Base clock divided by 64. */ +#define SDHC_PDD_BASE_DIV_BY_128 0x40U /**< Base clock divided by 128. */ +#define SDHC_PDD_BASE_DIV_BY_256 0x80U /**< Base clock divided by 256. */ + +/* Interrupt masks */ +#define SDHC_PDD_COMMAND_COMPLETE_INT SDHC_IRQSTAT_CC_MASK /**< The end bit of the command response is received (except Auto CMD12). */ +#define SDHC_PDD_TRANSFER_COMPLETE_INT SDHC_IRQSTAT_TC_MASK /**< Read or write transfer is completed. */ +#define SDHC_PDD_BLOCK_GAP_EVENT_INT SDHC_IRQSTAT_BGE_MASK /**< Read or write transaction is stopped at a block gap. */ +#define SDHC_PDD_DMA_INT SDHC_IRQSTAT_DINT_MASK /**< The internal DMA (simple or advanced) finished the data transfer successfully. */ +#define SDHC_PDD_BUFFER_WRITE_READY_INT SDHC_IRQSTAT_BWR_MASK /**< Ready to write buffer. */ +#define SDHC_PDD_BUFFER_READ_READY_INT SDHC_IRQSTAT_BRR_MASK /**< Ready to read buffer. */ +#define SDHC_PDD_CARD_INSERTION_INT SDHC_IRQSTAT_CINS_MASK /**< Card inserted. */ +#define SDHC_PDD_CARD_REMOVAL_INT SDHC_IRQSTAT_CRM_MASK /**< Card removed. */ +#define SDHC_PDD_CARD_INT SDHC_IRQSTAT_CINT_MASK /**< Card interrupt. */ +#define SDHC_PDD_COMMAND_TIMEOUT_ERROR_INT SDHC_IRQSTAT_CTOE_MASK /**< No response is returned within 64 SDHC_CLK cycles from the end bit of the command or SDHC detects a SDHC_CMD line conflict. */ +#define SDHC_PDD_COMMAND_CRC_ERROR_INT SDHC_IRQSTAT_CCE_MASK /**< CRC error in the command response is detected or SDHC_CMD line conflict is detected when a command is issued. */ +#define SDHC_PDD_COMMAND_END_BIT_ERROR_INT SDHC_IRQSTAT_CEBE_MASK /**< The end bit of a command response is 0. */ +#define SDHC_PDD_COMMAND_INDEX_ERROR_INT SDHC_IRQSTAT_CIE_MASK /**< Command index error occured in the command response. */ +#define SDHC_PDD_DATA_TIMEOUT_ERROR_INT SDHC_IRQSTAT_DTOE_MASK /**< Data timeout error. */ +#define SDHC_PDD_DATA_CRC_ERROR_INT SDHC_IRQSTAT_DCE_MASK /**< CRC error detected when transferring read data on the SDHC_DAT line or the write CRC status having a value other than 0b010 detected. */ +#define SDHC_PDD_DATA_END_BIT_ERROR_INT SDHC_IRQSTAT_DEBE_MASK /**< Zero at the end bit position of read data on the SDHC_DAT line or at the end bit position of the CRC detected. */ +#define SDHC_PDD_AUTO_CMD12_ERROR_INT SDHC_IRQSTAT_AC12E_MASK /**< Auto CMD12 error. */ +#define SDHC_PDD_DMA_ERROR_INT SDHC_IRQSTAT_DMAE_MASK /**< Internal DMA (simple or advanced) transfer failed. */ + +/* Filter modes */ +#define SDHC_PDD_AUTO_CMD12_NOT_EXECUTED SDHC_AC12ERR_AC12NE_MASK /**< Auto CMD12 not executed. */ +#define SDHC_PDD_AUTO_CMD12_TIMEOUT_ERROR SDHC_AC12ERR_AC12TOE_MASK /**< Auto CMD12 timeout error. */ +#define SDHC_PDD_AUTO_CMD12_END_BIT_ERROR SDHC_AC12ERR_AC12EBE_MASK /**< Auto CMD12 end bit error. */ +#define SDHC_PDD_AUTO_CMD12_CRC_ERROR SDHC_AC12ERR_AC12CE_MASK /**< Auto CMD12 CRC error. */ +#define SDHC_PDD_AUTO_CMD12_INDEX_ERROR SDHC_AC12ERR_AC12IE_MASK /**< Auto CMD12 index error. */ +#define SDHC_PDD_CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR SDHC_AC12ERR_CNIBAC12E_MASK /**< Command not issued by Auto CMD12 error. */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18))) +/* Host capabilities flags */ + #define SDHC_PDD_ADMA_SUPPORT SDHC_HTCAPBLT_ADMAS_MASK /**< Advanced DMA support. */ + #define SDHC_PDD_HIGH_SPEED_SUPPORT SDHC_HTCAPBLT_HSS_MASK /**< High speed support. */ + #define SDHC_PDD_DMA_SUPPORT SDHC_HTCAPBLT_DMAS_MASK /**< DMA support. */ + #define SDHC_PDD_SUSPEND_RESUME_SUPPORT SDHC_HTCAPBLT_SRS_MASK /**< Suspend/resume support. */ + #define SDHC_PDD_3_3_V_SUPPORT SDHC_HTCAPBLT_VS33_MASK /**< Voltage support 3.3V. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Host capabilities flags */ + #define SDHC_PDD_ADMA_SUPPORT SDHC_HTCAPBLT_ADMAS_MASK /**< Advanced DMA support. */ + #define SDHC_PDD_HIGH_SPEED_SUPPORT SDHC_HTCAPBLT_HSS_MASK /**< High speed support. */ + #define SDHC_PDD_DMA_SUPPORT SDHC_HTCAPBLT_DMAS_MASK /**< DMA support. */ + #define SDHC_PDD_SUSPEND_RESUME_SUPPORT SDHC_HTCAPBLT_SRS_MASK /**< Suspend/resume support. */ + #define SDHC_PDD_3_3_V_SUPPORT SDHC_HTCAPBLT_VS33_MASK /**< Voltage support 3.3V. */ + #define SDHC_PDD_3_0_V_SUPPORT SDHC_HTCAPBLT_VS30_MASK /**< Voltage support 3.0V. */ + #define SDHC_PDD_1_8_V_SUPPORT SDHC_HTCAPBLT_VS18_MASK /**< Voltage support 1.8V. */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/* Force event masks */ +#define SDHC_PDD_AUTO_CMD12_NOT_EXECUTED_EVENT SDHC_FEVT_AC12NE_MASK /**< Auto CMD12 not executed event. */ +#define SDHC_PDD_AUTO_CMD12_TIMEOUT_ERROR_EVENT SDHC_FEVT_AC12TOE_MASK /**< Auto CMD12 timeout error event. */ +#define SDHC_PDD_AUTO_CMD12_CRC_ERROR_EVENT SDHC_FEVT_AC12CE_MASK /**< Auto CMD12 CRC error event. */ +#define SDHC_PDD_AUTO_CMD12_END_BIT_ERROR_EVENT SDHC_FEVT_AC12EBE_MASK /**< Auto CMD12 end bit error event. */ +#define SDHC_PDD_AUTO_CMD12_INDEX_ERROR_EVENT SDHC_FEVT_AC12IE_MASK /**< Auto CMD12 index error event. */ +#define SDHC_PDD_CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR_EVENT SDHC_FEVT_CNIBAC12E_MASK /**< Command not executed by Auto CMD12 error event. */ +#define SDHC_PDD_COMMAND_TIMEOUT_ERROR_EVENT SDHC_FEVT_CTOE_MASK /**< Command time out error event. */ +#define SDHC_PDD_COMMAND_CRC_ERROR_EVENT SDHC_FEVT_CCE_MASK /**< Command CRC error event. */ +#define SDHC_PDD_COMMAND_END_BIT_ERROR_EVENT SDHC_FEVT_CEBE_MASK /**< Command end bit error event. */ +#define SDHC_PDD_COMMAND_INDEX_ERROR_EVENT SDHC_FEVT_CIE_MASK /**< Command index error event. */ +#define SDHC_PDD_DATA_TIMEOUT_ERROR_EVENT SDHC_FEVT_DTOE_MASK /**< Data time out error event. */ +#define SDHC_PDD_DATA_CRC_ERROR_EVENT SDHC_FEVT_DCE_MASK /**< Data CRC error event. */ +#define SDHC_PDD_DATA_END_BIT_ERROR_EVENT SDHC_FEVT_DEBE_MASK /**< Data end bit error event. */ +#define SDHC_PDD_AUTO_CMD12_ERROR_EVENT SDHC_FEVT_AC12E_MASK /**< Auto CMD12 error event. */ +#define SDHC_PDD_DMA_ERROR_EVENT SDHC_FEVT_DMAE_MASK /**< DMA error event. */ +#define SDHC_PDD_CARD_INTERRUPT_EVENT SDHC_FEVT_CINT_MASK /**< Card interrupt event. */ + +/* Clock sources */ +#define SDHC_PDD_CORE_SYSTEM_CLOCK 0U /**< Core/system clock. */ +#define SDHC_PDD_PLL_FLL_CLOCK 0x1U /**< PLL or FLL clock. */ +#define SDHC_PDD_EXTAL_CLOCK 0x2U /**< Extal clock. */ +#define SDHC_PDD_EXTERNAL_CLOCK 0x3U /**< External clock. */ + +/* LED states */ +#define SDHC_PDD_LED_ON 0x1U /**< LED on. */ +#define SDHC_PDD_LED_OFF 0U /**< LED off. */ + +/* Data transfer widths */ +#define SDHC_PDD_1_BIT_MODE 0U /**< 1 bit data width. */ +#define SDHC_PDD_4_BIT_MODE 0x2U /**< 4 bit data width. */ +#define SDHC_PDD_8_BIT_MODE 0x4U /**< 8 bit data width. */ + +/* Endian modes */ +#define SDHC_PDD_BIG_ENDIAN_MODE 0U /**< Big endian. */ +#define SDHC_PDD_HALF_WORD_BIG_ENDIAN_MODE 0x10U /**< Half word big endian. */ +#define SDHC_PDD_LITTLE_ENDIAN_MODE 0x20U /**< Little endian. */ + +/* DMA modes */ +#define SDHC_PDD_NO_OR_SIMPLE_DMA_MODE 0U /**< No DMA or simple DMA. */ +#define SDHC_PDD_ADVANCED_DMA_1_MODE 0x100U /**< Advanced DMA version 1. */ +#define SDHC_PDD_ADVANCED_DMA_2_MODE 0x200U /**< Advanced DMA version 2. */ + +/* ADMA error states */ +#define SDHC_PDD_ADMA_STOP 0U /**< Stop DMA. */ +#define SDHC_PDD_ADMA_FETCH_DESCRIPTOR 0x1U /**< Fetch descriptor. */ +#define SDHC_PDD_ADMA_CHANGE_ADDRESS 0x2U /**< Change address. */ +#define SDHC_PDD_ADMA_TRANSFER_DATA 0x3U /**< Transfer data. */ + +/* MMC boot modes */ +#define SDHC_PDD_NORMAL_BOOT 0U /**< Normal boot. */ +#define SDHC_PDD_ALTERNATIVE_BOOT 0x20U /**< Alternative boot. */ + +/* Specification version numbers */ +#define SDHC_PDD_SD_HOST_SPECIFICATION_V_2_0 0x1U /**< SD host specification version 2.0. */ + +/* Vendor version numbers */ +#define SDHC_PDD_FREESCALE_ESDHC_V_1_0 0U /**< Freescale eSDHC version 1.0. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_0 0x100U /**< Freescale eSDHC version 2.0. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_1 0x1100U /**< Freescale eSDHC version 2.1. */ +#define SDHC_PDD_FREESCALE_ESDHC_V_2_2 0x1200U /**< Freescale eSDHC version 2.2. */ + + +/* ---------------------------------------------------------------------------- + -- SetDMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the DMA system address containing the physical system memory + * address used for DMA transfers. Should be called only when no transactions are + * executing (after transactions have stopped). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address DMA system address. Should be aligned to a 4 byte boundary. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_DSADDR. + * @par Example: + * @code + * SDHC_PDD_SetDMAAddress(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetDMAAddress(PeripheralBase, Address) ( \ + SDHC_DSADDR_REG(PeripheralBase) = \ + (uint32)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DMA system address containing the system address of the + * next contiguous data position after the last DMA transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_DSADDR. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetDMAAddress(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetDMAAddress(PeripheralBase) ( \ + SDHC_DSADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBlockSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the block size for block data transfers. Should be called only + * when no transactions are executing (after transactions have stopped). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Size Transfer block size (from 0 to 4096). Should be aligned to a 4 + * byte boundary. This parameter is a 13-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * SDHC_PDD_SetBlockSize(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBlockSize(PeripheralBase, Size) ( \ + SDHC_BLKATTR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_BLKATTR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_BLKATTR_BLKSIZE_MASK)))) | ( \ + (uint32)(Size))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the block count for multiple block transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Block count for current transfer. This parameter is a 16-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * SDHC_PDD_SetBlockCount(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBlockCount(PeripheralBase, Count) ( \ + SDHC_BLKATTR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_BLKATTR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_BLKATTR_BLKCNT_MASK)))) | ( \ + (uint32)((uint32)(Count) << SDHC_BLKATTR_BLKCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the block count left for the current transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SDHC_BLKATTR. + * @par Example: + * @code + * uint16 result = SDHC_PDD_GetBlockCount(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetBlockCount(PeripheralBase) ( \ + (uint16)(( \ + (uint32)(SDHC_BLKATTR_REG(PeripheralBase) & SDHC_BLKATTR_BLKCNT_MASK)) >> ( \ + SDHC_BLKATTR_BLKCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCommandArgument + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the command argument specified as bits 39-8 of the SD/MMC command + * format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Argument Command argument. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_CMDARG. + * @par Example: + * @code + * SDHC_PDD_SetCommandArgument(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetCommandArgument(PeripheralBase, Argument) ( \ + SDHC_CMDARG_REG(PeripheralBase) = \ + (uint32)(Argument) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Sends a command through the CMD bus line. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Command index. Use constants from the following groups: "Command + * class 0 - basic", "Command class 1 - stream read", "Command class 2 - + * block read", "Command class 3 - stream write", "Command class 4 - block + * write", "Command class 5 - erase", "Command class 6 - write + * protection", "Command class 7 - lock card", "Command class 8 - application + * specific", "Command class 9 - IO mode", "Command class 10 - switch [SD]", + * "Application specific commands [SD]". This parameter is 6 bits wide. + * @param Options Command options mask (one value from each constants group). + * Use constants from the following groups: "Transfer DMA usage", "Transfer + * block count", "Transfer auto CMD12", "Transfer data direction", + * "Transfer multi/single block", "Command response type", "Command CRC check", + * "Command index check", "Command data present", "Command type". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_XFERTYP. + * @par Example: + * @code + * SDHC_PDD_SendCommand(_BASE_PTR, 1, 1); + * @endcode + */ +#define SDHC_PDD_SendCommand(PeripheralBase, Index, Options) ( \ + SDHC_XFERTYP_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(Options)) | ( \ + (uint32)((uint32)(Index) << SDHC_XFERTYP_CMDINX_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandResponse + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the command response. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Response A four 32-bit values array variable, where to store the + * response. This parameter is of user-defined type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CMDRSP[]. + * @par Example: + * @code + * SDHC_PDD_GetCommandResponse(_BASE_PTR, [Response]); + * @endcode + */ +#define SDHC_PDD_GetCommandResponse(PeripheralBase, Response) ( \ + Response[0] = SDHC_CMDRSP_REG(PeripheralBase,0U), \ + (Response[1] = SDHC_CMDRSP_REG(PeripheralBase,1U), \ + (Response[2] = SDHC_CMDRSP_REG(PeripheralBase,2U), \ + Response[3] = SDHC_CMDRSP_REG(PeripheralBase,3U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes the internal buffer data content if the internal DMA is not + * used. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Data content. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_DATPORT. + * @par Example: + * @code + * SDHC_PDD_SetBufferData(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBufferData(PeripheralBase, Data) ( \ + SDHC_DATPORT_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBufferData + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads the internal buffer data content if the internal DMA is not used. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_DATPORT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetBufferData(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetBufferData(PeripheralBase) ( \ + SDHC_DATPORT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCommandInhibited + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if a command is in progress (SDHC_CMD line is in use) + * until a command response is received. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCommandInhibited(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCommandInhibited(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CIHB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsDataCommandInhibited + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if a command with data transfer is in progress (SDHC_DAT + * line is in use) until data transfer is completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsDataCommandInhibited(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsDataCommandInhibited(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CDIHB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsDataLineActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns true if any of the data lines are in use. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsDataLineActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsDataLineActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_DLA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsSDClockStable + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the SD clock is stable. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsSDClockStable(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsSDClockStable(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_SDSTB_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsControllerClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the controller clock is gated off internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsControllerClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsControllerClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_IPGOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCrossbarClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the crossbar switch master clock is gated off + * internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsCrossbarClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCrossbarClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_HCKOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsPeripheralClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the crossbar switch master clock is gated off + * internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_IsPeripheralClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsPeripheralClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_PEROFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsSDHCClockGatedOff + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether the SDHC clock is gated off internally. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsSDHCClockGatedOff(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsSDHCClockGatedOff(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_SDOFF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsWriteTransferActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a write transfer is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsWriteTransferActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsWriteTransferActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_WTA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsReadTransferActive + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a read transfer is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsReadTransferActive(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsReadTransferActive(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_RTA_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsBufferWriteEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether there is space for write data in the internal + * buffer. Used for non-DMA write transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsBufferWriteEnabled(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsBufferWriteEnabled(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_BWEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsBufferReadEnabled + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether there is space for read data in the internal buffer. + * Used for non-DMA read transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsBufferReadEnabled(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsBufferReadEnabled(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_BREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCardInserted + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether a card is inserted. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCardInserted(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCardInserted(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CINS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCMDLineLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the SDHC_CMD line signal level. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetCMDLineLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetCMDLineLevel(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_CLSL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDATLineLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the SDHC_DAT line signal levels. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PRSSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetDATLineLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetDATLineLevel(PeripheralBase) ( \ + (uint32)(SDHC_PRSSTAT_REG(PeripheralBase) & SDHC_PRSSTAT_DLSL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLEDState + ---------------------------------------------------------------------------- */ + +/** + * @brief Controls the LED state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State LED state. This parameter is of "LED states" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetLEDState(_BASE_PTR, SDHC_PDD_LED_ON); + * @endcode + */ +#define SDHC_PDD_SetLEDState(PeripheralBase, State) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_LCTL_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataTransferWidth + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data transfer width (data width of the SD bus). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data transfer width. This parameter is of "Data transfer widths" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetDataTransferWidth(_BASE_PTR, + * SDHC_PDD_1_BIT_MODE); + * @endcode + */ +#define SDHC_PDD_SetDataTransferWidth(PeripheralBase, Width) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_DTW_MASK))) | ( \ + (uint32)(Width))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDAT3AsCardDetectionPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables card detection on the DAT3 pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableDAT3AsCardDetectionPin(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableDAT3AsCardDetectionPin(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_D3CD_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_D3CD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetEndianMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the endian mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Endian mode. This parameter is of "Endian modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetEndianMode(_BASE_PTR, SDHC_PDD_BIG_ENDIAN_MODE); + * @endcode + */ +#define SDHC_PDD_SetEndianMode(PeripheralBase, Mode) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_PROCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_PROCTL_EMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCardDetectTestLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Determines card insertion status when card detection test level is + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetCardDetectTestLevel(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetCardDetectTestLevel(PeripheralBase) ( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & SDHC_PROCTL_CDTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCardDetectionTestLevel + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables card detection test level (for test purpose). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableCardDetectionTestLevel(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableCardDetectionTestLevel(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_CDSS_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_CDSS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDMAMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the DMA mode when DMA is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode DMA mode. This parameter is of "DMA modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_SetDMAMode(_BASE_PTR, + * SDHC_PDD_NO_OR_SIMPLE_DMA_MODE); + * @endcode + */ +#define SDHC_PDD_SetDMAMode(PeripheralBase, Mode) ( \ + SDHC_PROCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_PROCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_PROCTL_DMAS_MASK))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStopAtBlockGapRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transaction execution stop at the next block gap for + * both DMA and non-DMA transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableStopAtBlockGapRequest(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableStopAtBlockGapRequest(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_SABGREQ_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_SABGREQ_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ContinueRequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Restarts a transaction which was stopped using the stop-at-block-gap + * request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_ContinueRequest(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ContinueRequest(PeripheralBase) ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_CREQ_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReadWaitControl + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables read wait control. Should be enabled only if the card + * supports this feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableReadWaitControl(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableReadWaitControl(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_RWCTL_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_RWCTL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptAtBlockGap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables interrupt at block gap. Interrupt enable is valid + * only in 4-bit mode and the SD card should support this feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableInterruptAtBlockGap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableInterruptAtBlockGap(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_IABG_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_IABG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card interrupt. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardInterrupt(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardInterrupt(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECINT_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardInsertion + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card insertion. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardInsertion(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardInsertion(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECINS_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECINS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWakeUpOnCardRemoval + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables wake-up event on card removal. Can be enabled if + * wake-up support is enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_PROCTL. + * @par Example: + * @code + * SDHC_PDD_EnableWakeUpOnCardRemoval(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableWakeUpOnCardRemoval(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_PROCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_PROCTL_WECRM_MASK)) : ( \ + SDHC_PROCTL_REG(PeripheralBase) |= \ + SDHC_PROCTL_WECRM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableControllerClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables controller clock. If enabled, the controller clock is + * always active and no automatic gating is applied. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableControllerClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableControllerClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_IPGEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_IPGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrossbarClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables crossbar switch master clock. If enabled, the clock + * is always active and no automatic gating is applied. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableCrossbarClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableCrossbarClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_HCKEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_HCKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePeripheralClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables peripheral clock. If enabled, the peripheral clock is + * always active and no automatic gating is applied, thus SDHC_CLK is active + * only except auto gating-off during buffer danger. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnablePeripheralClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnablePeripheralClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_PEREN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_PEREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSDHCClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SDHC clock. The SDHC_CLK frequency should be changed + * only if SDHC clock is disabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_EnableSDHCClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableSDHCClock(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_SYSCTL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_SYSCTL_SDCLKEN_MASK)) : ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_SDCLKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSDHCClockDivisor + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SDHC clock divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divisor SDHC clock divisor decreased by 1 (e.g. 2 means divisor by 3). + * This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetSDHCClockDivisor(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetSDHCClockDivisor(PeripheralBase, Divisor) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_SYSCTL_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_SYSCTL_DVS_MASK))) | ( \ + (uint32)((uint32)(Divisor) << SDHC_SYSCTL_DVS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSDHCClockFrequency + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SDHC clock frequency. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Frequency SDHC clock frequency. Use constants from group "Clock + * divider values". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetSDHCClockFrequency(_BASE_PTR, + * SDHC_PDD_BASE_DIV_BY_2); + * @endcode + */ +#define SDHC_PDD_SetSDHCClockFrequency(PeripheralBase, Frequency) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_SYSCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_SYSCTL_SDCLKFS_MASK)))) | ( \ + (uint32)((uint32)(Frequency) << SDHC_SYSCTL_SDCLKFS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the data timeout counter value. Determines the interval by which + * SDHC_DAT line timeouts are detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Timeout Data timeout counter value (from 0 to 14). Specifies the + * timeout value as 2^(13 + Timeout) SDHC clock cycles. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_SetDataTimeout(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetDataTimeout(PeripheralBase, Timeout) ( \ + SDHC_SYSCTL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_SYSCTL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_SYSCTL_DTOCV_MASK)))) | ( \ + (uint32)((uint32)(Timeout) << SDHC_SYSCTL_DTOCV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetDevice(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetDevice(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetCMDLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the SDHC_CMD line. Only part of the command circuit is reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetCMDLine(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetCMDLine(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetDATLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets the SDHC_DAT line. The DMA and part of the data circuit are + * reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_ResetDATLine(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_ResetDATLine(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_RSTD_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- InitCard + ---------------------------------------------------------------------------- */ + +/** + * @brief Send 80 SD clocks to the card. Should be used during the card power-up + * period. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * SDHC_PDD_InitCard(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_InitCard(PeripheralBase) ( \ + SDHC_SYSCTL_REG(PeripheralBase) |= \ + SDHC_SYSCTL_INITA_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCardInitComplete + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates whether card initialization is completed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_SYSCTL. + * @par Example: + * @code + * uint32 result = SDHC_PDD_IsCardInitComplete(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_IsCardInitComplete(PeripheralBase) ( \ + (uint32)(( \ + (uint32)(SDHC_SYSCTL_REG(PeripheralBase) & SDHC_SYSCTL_INITA_MASK)) ^ ( \ + SDHC_SYSCTL_INITA_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the interrupt flags. The returned value can be masked with + * predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_IRQSTAT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetInterruptFlags(PeripheralBase) ( \ + SDHC_IRQSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the specified interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTAT. + * @par Example: + * @code + * SDHC_PDD_ClearInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTAT_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupts; + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSIGEN. + * @par Example: + * @code + * SDHC_PDD_EnableInterrupts(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_EnableInterrupts(PeripheralBase, Mask) ( \ + SDHC_IRQSIGEN_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSIGEN. + * @par Example: + * @code + * SDHC_PDD_DisableInterrupts(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_DisableInterrupts(PeripheralBase, Mask) ( \ + SDHC_IRQSIGEN_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt flags specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt masks". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTATEN. + * @par Example: + * @code + * SDHC_PDD_EnableInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_EnableInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTATEN_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt flags specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt flag mask. Use constants from group "Interrupt masks". + * This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_IRQSTATEN. + * @par Example: + * @code + * SDHC_PDD_DisableInterruptFlags(_BASE_PTR, + * SDHC_PDD_COMMAND_COMPLETE_INT); + * @endcode + */ +#define SDHC_PDD_DisableInterruptFlags(PeripheralBase, Mask) ( \ + SDHC_IRQSTATEN_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAutoCMD12ErrorFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the Auto CMD12 error flags. The return value can be mask with: + * AUTO_CMD12_NOT_EXECUTED, AUTO_CMD12_TIMEOUT_ERROR, AUTO_CMD12_END_BIT_ERROR, + * AUTO_CMD12_CRC_ERROR, AUTO_CMD12_INDEX_ERROR, + * CMD_NOT_ISSUED_BY_AUTO_CMD12_ERROR. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_AC12ERR. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetAutoCMD12ErrorFlags(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetAutoCMD12ErrorFlags(PeripheralBase) ( \ + SDHC_AC12ERR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetHostCapabilities + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns host controller capabilities flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_HTCAPBLT. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetHostCapabilities(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetHostCapabilities(PeripheralBase) ( \ + SDHC_HTCAPBLT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMaxBlockLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Indicates the maximum block size that the host driver can read and + * write to the buffer in the SDHC. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_HTCAPBLT. + * @par Example: + * @code + * SDHC_PDD_GetMaxBlockLength(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetMaxBlockLength(PeripheralBase) ( \ + 512 << (uint8)(( \ + (uint32)(SDHC_HTCAPBLT_REG(PeripheralBase) & SDHC_HTCAPBLT_MBL_MASK)) >> ( \ + SDHC_HTCAPBLT_MBL_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWriteWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the watermark level in DMA write operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Write watermark level (from 1 to 128). Number of 4-byte + * words of watermark level in DMA write operation. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_WML. + * @par Example: + * @code + * SDHC_PDD_SetWriteWatermark(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetWriteWatermark(PeripheralBase, Watermark) ( \ + SDHC_WML_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_WML_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_WML_WRWML_MASK))) | ( \ + (uint32)((uint32)(Watermark) << SDHC_WML_WRWML_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReadWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the watermark level in DMA read operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Watermark Read watermark level (from 1 to 128). Number of 4-byte words + * of watermark level in DMA read operation. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_WML. + * @par Example: + * @code + * SDHC_PDD_SetReadWatermark(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetReadWatermark(PeripheralBase, Watermark) ( \ + SDHC_WML_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_WML_REG(PeripheralBase) & (uint32)(~(uint32)SDHC_WML_RDWML_MASK))) | ( \ + (uint32)(Watermark))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ForceEvents + ---------------------------------------------------------------------------- */ + +/** + * @brief Forces events specified by the mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Event mask. Use constants from group "Force event masks". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_FEVT. + * @par Example: + * @code + * SDHC_PDD_ForceEvents(_BASE_PTR, + * SDHC_PDD_AUTO_CMD12_NOT_EXECUTED_EVENT); + * @endcode + */ +#define SDHC_PDD_ForceEvents(PeripheralBase, Mask) ( \ + SDHC_FEVT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SDHC_FEVT_REG(PeripheralBase) | (uint32)(Mask))) & (( \ + (uint32)(~(uint32)0x60U)) & (( \ + (uint32)(~(uint32)0xFF00U)) & (( \ + (uint32)(~(uint32)0x800000U)) & (( \ + (uint32)(~(uint32)0xE000000U)) & ( \ + (uint32)(~(uint32)0x60000000U))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMALengthMismatchErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA length mismatch error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetADMALengthMismatchErrorFlag(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMALengthMismatchErrorFlag(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMALME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMADescriptorErrorFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA descriptor error flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetADMADescriptorErrorFlag(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMADescriptorErrorFlag(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMADCE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMAErrorState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA error state. The return value can be compared with + * predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "ADMA error states" type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SDHC_ADMAES. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetADMAErrorState(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMAErrorState(PeripheralBase) ( \ + (uint32)(SDHC_ADMAES_REG(PeripheralBase) & SDHC_ADMAES_ADMAES_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetADMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the ADMA system address containing the physical system memory + * address used for ADMA transfers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address ADMA system address. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_ADSADDR. + * @par Example: + * @code + * SDHC_PDD_SetADMAAddress(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetADMAAddress(PeripheralBase, Address) ( \ + SDHC_ADSADDR_REG(PeripheralBase) = \ + (uint32)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetADMAAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the ADMA system address containing the address of the + * executing command of the descriptor table. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SDHC_ADSADDR. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetADMAAddress(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetADMAAddress(PeripheralBase) ( \ + SDHC_ADSADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExternalDMARequest + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the external DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_VENDOR. + * @par Example: + * @code + * SDHC_PDD_EnableExternalDMARequest(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableExternalDMARequest(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_VENDOR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_VENDOR_EXTDMAEN_MASK)) : ( \ + SDHC_VENDOR_REG(PeripheralBase) |= \ + SDHC_VENDOR_EXTDMAEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableExactBlockNum + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables exact block number for SDIO CMD53. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_VENDOR. + * @par Example: + * @code + * SDHC_PDD_EnableExactBlockNum(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableExactBlockNum(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_VENDOR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_VENDOR_EXBLKNU_MASK)) : ( \ + SDHC_VENDOR_REG(PeripheralBase) |= \ + SDHC_VENDOR_EXBLKNU_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootAckTimeout + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the boot acknowled timeout counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Timeout Boot ack timeout counter value (from 0 to 14). Specifies the + * timeout value as 2^(8 + Timeout) SD clock cycles. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootAckTimeout(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBootAckTimeout(PeripheralBase, Timeout) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_DTOCVACK_MASK)))) | ( \ + (uint32)(Timeout))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBootAck + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables boot acknowledge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableBootAck(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableBootAck(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTACK_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_BOOTACK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the boot mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Boot mode. This parameter is of "MMC boot modes" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootMode(_BASE_PTR, SDHC_PDD_NORMAL_BOOT); + * @endcode + */ +#define SDHC_PDD_SetBootMode(PeripheralBase, Mode) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTMODE_MASK)))) | ( \ + (uint32)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBootMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the boot mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableBootMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableBootMode(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTEN_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_BOOTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAutoStopAtBlockGap + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables auto stop at block gap function when boot. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Enable Enable flag. This parameter is of "Global enumeration used for + * specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_EnableAutoStopAtBlockGap(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SDHC_PDD_EnableAutoStopAtBlockGap(PeripheralBase, Enable) ( \ + ((Enable) == PDD_DISABLE) ? ( \ + SDHC_MMCBOOT_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SDHC_MMCBOOT_AUTOSABGEN_MASK)) : ( \ + SDHC_MMCBOOT_REG(PeripheralBase) |= \ + SDHC_MMCBOOT_AUTOSABGEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBootBlockCount + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the received boot block count after which 'stop at block gap' + * occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Count Boot block count. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SDHC_MMCBOOT. + * @par Example: + * @code + * SDHC_PDD_SetBootBlockCount(_BASE_PTR, 1); + * @endcode + */ +#define SDHC_PDD_SetBootBlockCount(PeripheralBase, Count) ( \ + SDHC_MMCBOOT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SDHC_MMCBOOT_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SDHC_MMCBOOT_BOOTBLKCNT_MASK)))) | ( \ + (uint32)((uint32)(Count) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSpecificationVersion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the specification version number. The return value can be + * compared with predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Specification version numbers" type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SDHC_HOSTVER. + * @par Example: + * @code + * uint32 result = + * SDHC_PDD_GetSpecificationVersion(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetSpecificationVersion(PeripheralBase) ( \ + (uint32)(SDHC_HOSTVER_REG(PeripheralBase) & SDHC_HOSTVER_SVN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVendorVersion + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the vendor version number. The return value can be compared + * with predefined macros. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Vendor version numbers" type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: SDHC_HOSTVER. + * @par Example: + * @code + * uint32 result = SDHC_PDD_GetVendorVersion(_BASE_PTR); + * @endcode + */ +#define SDHC_PDD_GetVendorVersion(PeripheralBase) ( \ + (uint32)(SDHC_HOSTVER_REG(PeripheralBase) & SDHC_HOSTVER_VVN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK10F12)) || (defined(MCU_MK20F12)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS))) +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Use constants from group "Clock sources". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * SDHC_PDD_SetClockSource(_BASE_PTR, + * SDHC_PDD_CORE_SYSTEM_CLOCK); + * @endcode + */ + #define SDHC_PDD_SetClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(SIM_BASE_PTR) = \ + (( \ + (uint32)(SIM_SOPT2_REG(SIM_BASE_PTR) & (uint32)(~(uint32)SIM_SOPT2_ESDHCSRC_MASK))) | ( \ + (uint32)((uint32)(Source) << SIM_SOPT2_ESDHCSRC_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) */ +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Use constants from group "Clock sources". This + * parameter is 32 bits wide. + * @return Returns a value of void type. + * @par Example: + * @code + * SDHC_PDD_SetClockSource(_BASE_PTR, + * SDHC_PDD_CORE_SYSTEM_CLOCK); + * @endcode + */ + #define SDHC_PDD_SetClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(SIM_BASE_PTR) = \ + (( \ + (uint32)(SIM_SOPT2_REG(SIM_BASE_PTR) & (uint32)(~(uint32)SIM_SOPT2_SDHCSRC_MASK))) | ( \ + (uint32)((uint32)(Source) << SIM_SOPT2_SDHCSRC_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) */ +#endif /* #if defined(SDHC_PDD_H_) */ + +/* SDHC_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h new file mode 100644 index 0000000..d7365e3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SIM_PDD.h @@ -0,0 +1,6806 @@ +/* + PDD layer implementation for peripheral type SIM + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SIM_PDD_H_) +#define SIM_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SIM PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SIM */ && \ + !defined(MCU_MK10D5) /* SIM */ && \ + !defined(MCU_MK10D7) /* SIM */ && \ + !defined(MCU_MK10F12) /* SIM */ && \ + !defined(MCU_MK10DZ10) /* SIM */ && \ + !defined(MCU_MK11D5) /* SIM */ && \ + !defined(MCU_MK11D5WS) /* SIM */ && \ + !defined(MCU_MK12D5) /* SIM */ && \ + !defined(MCU_MK20D10) /* SIM */ && \ + !defined(MCU_MK20D5) /* SIM */ && \ + !defined(MCU_MK20D7) /* SIM */ && \ + !defined(MCU_MK20F12) /* SIM */ && \ + !defined(MCU_MK20DZ10) /* SIM */ && \ + !defined(MCU_MK21D5) /* SIM */ && \ + !defined(MCU_MK21D5WS) /* SIM */ && \ + !defined(MCU_MK21F12) /* SIM */ && \ + !defined(MCU_MK21F12WS) /* SIM */ && \ + !defined(MCU_MK22D5) /* SIM */ && \ + !defined(MCU_MK22F12810) /* SIM */ && \ + !defined(MCU_MK22F12) /* SIM */ && \ + !defined(MCU_MK22F25612) /* SIM */ && \ + !defined(MCU_MK22F51212) /* SIM */ && \ + !defined(MCU_MK24F12) /* SIM */ && \ + !defined(MCU_MK30D10) /* SIM */ && \ + !defined(MCU_MK30D7) /* SIM */ && \ + !defined(MCU_MK30DZ10) /* SIM */ && \ + !defined(MCU_MK40D10) /* SIM */ && \ + !defined(MCU_MK40D7) /* SIM */ && \ + !defined(MCU_MK40DZ10) /* SIM */ && \ + !defined(MCU_MK40X256VMD100) /* SIM */ && \ + !defined(MCU_MK50D10) /* SIM */ && \ + !defined(MCU_MK50D7) /* SIM */ && \ + !defined(MCU_MK50DZ10) /* SIM */ && \ + !defined(MCU_MK51D10) /* SIM */ && \ + !defined(MCU_MK51D7) /* SIM */ && \ + !defined(MCU_MK51DZ10) /* SIM */ && \ + !defined(MCU_MK52D10) /* SIM */ && \ + !defined(MCU_MK52DZ10) /* SIM */ && \ + !defined(MCU_MK53D10) /* SIM */ && \ + !defined(MCU_MK53DZ10) /* SIM */ && \ + !defined(MCU_MK60D10) /* SIM */ && \ + !defined(MCU_MK60F12) /* SIM */ && \ + !defined(MCU_MK60F15) /* SIM */ && \ + !defined(MCU_MK60DZ10) /* SIM */ && \ + !defined(MCU_MK60N512VMD100) /* SIM */ && \ + !defined(MCU_MK61F12) /* SIM */ && \ + !defined(MCU_MK61F15) /* SIM */ && \ + !defined(MCU_MK61F12WS) /* SIM */ && \ + !defined(MCU_MK61F15WS) /* SIM */ && \ + !defined(MCU_MK63F12) /* SIM */ && \ + !defined(MCU_MK63F12WS) /* SIM */ && \ + !defined(MCU_MK64F12) /* SIM */ && \ + !defined(MCU_MK65F18) /* SIM */ && \ + !defined(MCU_MK65F18WS) /* SIM */ && \ + !defined(MCU_MK66F18) /* SIM */ && \ + !defined(MCU_MK70F12) /* SIM */ && \ + !defined(MCU_MK70F15) /* SIM */ && \ + !defined(MCU_MK70F12WS) /* SIM */ && \ + !defined(MCU_MK70F15WS) /* SIM */ && \ + !defined(MCU_MKE02Z2) /* SIM */ && \ + !defined(MCU_MKE02Z4) /* SIM */ && \ + !defined(MCU_SKEAZN642) /* SIM */ && \ + !defined(MCU_MKE04Z1284) /* SIM */ && \ + !defined(MCU_MKE04Z4) /* SIM */ && \ + !defined(MCU_SKEAZN84) /* SIM */ && \ + !defined(MCU_MKE06Z4) /* SIM */ && \ + !defined(MCU_MKL02Z4) /* SIM */ && \ + !defined(MCU_MKL03Z4) /* SIM */ && \ + !defined(MCU_MKL04Z4) /* SIM */ && \ + !defined(MCU_MKL05Z4) /* SIM */ && \ + !defined(MCU_MKL14Z4) /* SIM */ && \ + !defined(MCU_MKL15Z4) /* SIM */ && \ + !defined(MCU_MKL16Z4) /* SIM */ && \ + !defined(MCU_MKL24Z4) /* SIM */ && \ + !defined(MCU_MKL25Z4) /* SIM */ && \ + !defined(MCU_MKL26Z4) /* SIM */ && \ + !defined(MCU_MKL34Z4) /* SIM */ && \ + !defined(MCU_MKL36Z4) /* SIM */ && \ + !defined(MCU_MKL46Z4) /* SIM */ && \ + !defined(MCU_MKV10Z7) /* SIM */ && \ + !defined(MCU_MKV31F12810) /* SIM */ && \ + !defined(MCU_MKV31F25612) /* SIM */ && \ + !defined(MCU_MKV31F51212) /* SIM */ && \ + !defined(MCU_MKW21D5) /* SIM */ && \ + !defined(MCU_MKW21D5WS) /* SIM */ && \ + !defined(MCU_MKW22D5) /* SIM */ && \ + !defined(MCU_MKW22D5WS) /* SIM */ && \ + !defined(MCU_MKW24D5) /* SIM */ && \ + !defined(MCU_MKW24D5WS) /* SIM */ && \ + !defined(MCU_PCK20L4) /* SIM */ && \ + !defined(MCU_SKEAZ1284) /* SIM */ + // Unsupported MCU is active + #error SIM PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MK10D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK10D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK10D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK10DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK10F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK11D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK11D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK12D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + +#elif (defined(MCU_MK20D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK20D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK20DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK20F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK21D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK21D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + +#elif (defined(MCU_MK21F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK21F12WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK22D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + +#elif (defined(MCU_MK22F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK22F12810)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK22F25612)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK22F51212)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0xA6U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0xA8U /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MK24F12)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK30D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK30D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK30DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK40DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK40X256VMD100)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK50D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + +#elif (defined(MCU_MK50D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK50DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + +#elif (defined(MCU_MK51D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK51D7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + +#elif (defined(MCU_MK51DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + +#elif (defined(MCU_MK52D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK52DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK53D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier 0/1 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK53DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_OPAMP 0x15U /**< Clock gate identifier for Operational Amplifier */ + #define SIM_PDD_CLOCK_GATE_TRIAMP 0x18U /**< Clock gate identifier for Trans-impedance amplifier */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LCD 0x5EU /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK60D10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_RNG 0x40U /**< Clock gate identifier for Random number generator (RNG) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK60DZ10)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + +#elif (defined(MCU_MK60N512VMD100)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGB 0x40U /**< Clock gate identifier for Random number generator (RNGB) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System Register File */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory controller */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for PDMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK63F12WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif (defined(MCU_MK65F18WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_I2C3 0x7U /**< Clock gate identifier for I2C3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x24U /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0x29U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0x2AU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_USBHS 0x41U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBPHY 0x42U /**< Clock gate identifier for USBPHY */ + #define SIM_PDD_CLOCK_GATE_USBHSDCD 0x43U /**< Clock gate identifier for USBHSDCD */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDRAM 0xC3U /**< Clock gate identifier for Synchronous DRAM controller */ + +#elif (defined(MCU_MKE04Z1284)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x10U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C1) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif (defined(MCU_MKL02Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + +#elif (defined(MCU_MKL03Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x94U /**< Clock gate identifier for LPUART0 */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + +#elif (defined(MCU_MKL04Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL05Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for FlexTimer (TPM) 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for FlexTimer (TPM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL14Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL15Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL16Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL24Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL25Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL26Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL34Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL36Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKL46Z4)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x76U /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x77U /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LCD 0x93U /**< Clock gate identifier for Segment LCD */ + #define SIM_PDD_CLOCK_GATE_FTFA 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S/SAI */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_TPM0 0xB8U /**< Clock gate identifier for Low Power TPM 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0xB9U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0xBAU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV10Z7)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xBCU /**< Clock gate identifier for Analog-to-Digital Converter 1 */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + +#elif (defined(MCU_MKV31F12810)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV31F25612)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKV31F51212)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0xA6U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0xA7U /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0xA8U /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0xAAU /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif (defined(MCU_MKW21D5)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif (defined(MCU_MKW21D5WS)) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif ((defined(MCU_MK20D5)) || (defined(MCU_PCK20L4))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + +#elif ((defined(MCU_MK60F12)) || (defined(MCU_MK60F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MK61F12)) || (defined(MCU_MK61F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK63F12)) || (defined(MCU_MK64F12))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0xA9U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MK65F18)) || (defined(MCU_MK66F18))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_I2C2 0x6U /**< Clock gate identifier for I2C2 */ + #define SIM_PDD_CLOCK_GATE_I2C3 0x7U /**< Clock gate identifier for I2C3 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART4 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_LPUART0 0x24U /**< Clock gate identifier for LPUART 0 */ + #define SIM_PDD_CLOCK_GATE_TPM1 0x29U /**< Clock gate identifier for Low Power TPM 1 */ + #define SIM_PDD_CLOCK_GATE_TPM2 0x2AU /**< Clock gate identifier for Low Power TPM 2 */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_USBHS 0x41U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBPHY 0x42U /**< Clock gate identifier for USBPHY */ + #define SIM_PDD_CLOCK_GATE_USBHSDCD 0x43U /**< Clock gate identifier for USBHSDCD */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_FTFE 0xA0U /**< Clock gate identifier for Flash memory */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USBDCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_SDRAM 0xC3U /**< Clock gate identifier for Synchronous DRAM controller */ + +#elif ((defined(MCU_MK70F12)) || (defined(MCU_MK70F15))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_LCDC 0x56U /**< Clock gate identifier for Graphical LCD controller */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + +#elif ((defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_OSC1 0x5U /**< Clock gate identifier for OSC1 */ + #define SIM_PDD_CLOCK_GATE_UART4 0xAU /**< Clock gate identifier for UART 4 */ + #define SIM_PDD_CLOCK_GATE_UART5 0xBU /**< Clock gate identifier for UART 5 */ + #define SIM_PDD_CLOCK_GATE_ENET 0x20U /**< Clock gate identifier for Ethernet MAC and IEEE 1588 timers */ + #define SIM_PDD_CLOCK_GATE_DAC0 0x2CU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 0 */ + #define SIM_PDD_CLOCK_GATE_DAC1 0x2DU /**< Clock gate identifier for 12-bit digital-to-analog converter (DAC) 1 */ + #define SIM_PDD_CLOCK_GATE_RNGA 0x40U /**< Clock gate identifier for Random number generator accelerator (RNGA) */ + #define SIM_PDD_CLOCK_GATE_CAN1 0x44U /**< Clock gate identifier for CAN 1 */ + #define SIM_PDD_CLOCK_GATE_NFC 0x48U /**< Clock gate identifier for NAND flash controller */ + #define SIM_PDD_CLOCK_GATE_SPI2 0x4CU /**< Clock gate identifier for SPI 2 */ + #define SIM_PDD_CLOCK_GATE_DDR 0x4EU /**< Clock gate identifier for Dual data rate memory controller */ + #define SIM_PDD_CLOCK_GATE_I2S1 0x4FU /**< Clock gate identifier for I2S 1/SAI 1 */ + #define SIM_PDD_CLOCK_GATE_SDHC 0x51U /**< Clock gate identifier for SDHC */ + #define SIM_PDD_CLOCK_GATE_LCDC 0x56U /**< Clock gate identifier for Graphical LCD controller */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x58U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_FTM3 0x59U /**< Clock gate identifier for FlexTimer (FTM) 3 */ + #define SIM_PDD_CLOCK_GATE_ADC1 0x5BU /**< Clock gate identifier for Analog-to-digital converter (ADC) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC3 0x5CU /**< Clock gate identifier for Analog-to-digital converter (ADC) 3 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External watchdog */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for I2C0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for I2C1 */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for UART 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for UART 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for UART 2 */ + #define SIM_PDD_CLOCK_GATE_UART3 0x6DU /**< Clock gate identifier for UART 3 */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for High-speed comparator (CMP)/6-bit digital-to-analog converter (DAC) */ + #define SIM_PDD_CLOCK_GATE_VREF 0x74U /**< Clock gate identifier for Voltage reference (VREF) */ + #define SIM_PDD_CLOCK_GATE_LLWU 0x7CU /**< Clock gate identifier for Low-leakage wakeup unit (LLWU) */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for Low-power timer (LPTMR) */ + #define SIM_PDD_CLOCK_GATE_SYSTEM_REGS 0x81U /**< Clock gate identifier for System register file */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_TSI0 0x85U /**< Clock gate identifier for Touch sense interface (TSI) */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_PORTF 0x8EU /**< Clock gate identifier for Port F control */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR0 0xA1U /**< Clock gate identifier for DMA channel mutiplexor 0 */ + #define SIM_PDD_CLOCK_GATE_DMA_MULTIPLEXOR1 0xA2U /**< Clock gate identifier for DMA channel mutiplexor 1 */ + #define SIM_PDD_CLOCK_GATE_CAN0 0xA4U /**< Clock gate identifier for CAN 0 */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for SPI 0 */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for SPI 1 */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for I2S 0/SAI 0 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_USBHS 0xB4U /**< Clock gate identifier for USB OTG HS/FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB DCD */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-digital converter (ADC) 0 */ + #define SIM_PDD_CLOCK_GATE_ADC2 0xBCU /**< Clock gate identifier for Analog-to-digital converter (ADC) 2 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) */ + #define SIM_PDD_CLOCK_GATE_FB 0xC0U /**< Clock gate identifier for FlexBus */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC1U /**< Clock gate identifier for DMA controller */ + #define SIM_PDD_CLOCK_GATE_MPU 0xC2U /**< Clock gate identifier for MPU */ + +#elif ((defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN84))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif ((defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_PWT 0x4U /**< Clock gate identifier for Pulse Width Timer (PWT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRE 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRE) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_MSCAN 0xFU /**< Clock gate identifier for Modular Scalable Controller Area Network (MSCAN) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x10U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C1) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + +#elif ((defined(MCU_MKW22D5)) || (defined(MCU_MKW24D5))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB Device Charger Detection Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#elif ((defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5WS))) +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_CMP 0x73U /**< Clock gate identifier for Comparators */ + #define SIM_PDD_CLOCK_GATE_UART0 0x6AU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 0 */ + #define SIM_PDD_CLOCK_GATE_UART1 0x6BU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 1 */ + #define SIM_PDD_CLOCK_GATE_UART2 0x6CU /**< Clock gate identifier for Universal Asynchronous Receiver Transmitter 2 */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x66U /**< Clock gate identifier for Inter-Integrated Circuit 0 */ + #define SIM_PDD_CLOCK_GATE_I2C1 0x67U /**< Clock gate identifier for Inter-Integrated Circuit 1 */ + #define SIM_PDD_CLOCK_GATE_EWM 0x61U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_PORTA 0x89U /**< Clock gate identifier for Port A control */ + #define SIM_PDD_CLOCK_GATE_PORTB 0x8AU /**< Clock gate identifier for Port B control */ + #define SIM_PDD_CLOCK_GATE_PORTC 0x8BU /**< Clock gate identifier for Port C control */ + #define SIM_PDD_CLOCK_GATE_PORTD 0x8CU /**< Clock gate identifier for Port D control */ + #define SIM_PDD_CLOCK_GATE_PORTE 0x8DU /**< Clock gate identifier for Port E control */ + #define SIM_PDD_CLOCK_GATE_LPTMR0 0x80U /**< Clock gate identifier for External Watchdog Monitor */ + #define SIM_PDD_CLOCK_GATE_DAC0 0xBFU /**< Clock gate identifier for Digital-to-Analog Converter 0 */ + #define SIM_PDD_CLOCK_GATE_ADC0 0xBBU /**< Clock gate identifier for Analog-to-Digital Converter 0 */ + #define SIM_PDD_CLOCK_GATE_RTC 0xBDU /**< Clock gate identifier for Real-time clock (RTC) seconds LLWU source */ + #define SIM_PDD_CLOCK_GATE_FTM0 0xB8U /**< Clock gate identifier for FlexTimer Module 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0xB9U /**< Clock gate identifier for FlexTimer Module 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0xBAU /**< Clock gate identifier for FlexTimer Module 2 */ + #define SIM_PDD_CLOCK_GATE_PDB0 0xB6U /**< Clock gate identifier for Programmable delay block (PDB) */ + #define SIM_PDD_CLOCK_GATE_CRC 0xB2U /**< Clock gate identifier for Cyclic Redundancy Check */ + #define SIM_PDD_CLOCK_GATE_SPI0 0xACU /**< Clock gate identifier for Serial Peripheral Interface */ + #define SIM_PDD_CLOCK_GATE_SPI1 0xADU /**< Clock gate identifier for Serial Peripheral Interface 1 */ + #define SIM_PDD_CLOCK_GATE_DMAMUX 0xA1U /**< Clock gate identifier for Direct Memory Access Multiplexer */ + #define SIM_PDD_CLOCK_GATE_DMA 0xC8U /**< Clock gate identifier for Direct Memory Access Controller */ + #define SIM_PDD_CLOCK_GATE_FTFL 0xA0U /**< Clock gate identifier for Flash Memory Module */ + #define SIM_PDD_CLOCK_GATE_USB0 0x72U /**< Clock gate identifier for USB OTG FS/LS */ + #define SIM_PDD_CLOCK_GATE_USBDCD 0xB5U /**< Clock gate identifier for USB Device Charger Detection Module */ + #define SIM_PDD_CLOCK_GATE_CMT 0x62U /**< Clock gate identifier for Carrier modulator timer (CMT) */ + #define SIM_PDD_CLOCK_GATE_DRY 0x82U /**< Clock gate identifier for DryIce */ + #define SIM_PDD_CLOCK_GATE_DRY_SECREG 0x83U /**< Clock gate identifier for DryIce secure storage */ + #define SIM_PDD_CLOCK_GATE_PIT 0xB7U /**< Clock gate identifier for Periodic interrupt timers (PIT) */ + #define SIM_PDD_CLOCK_GATE_I2S0 0xAFU /**< Clock gate identifier for Integrated Interchip Sound (I2S) */ + #define SIM_PDD_CLOCK_GATE_RNG 0xA9U /**< Clock gate identifier for Random number generator accelerator */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642)) */ +/* Clock gate identifiers */ + #define SIM_PDD_CLOCK_GATE_RTC 0U /**< Clock gate identifier for Real-Time Counter (RTC) */ + #define SIM_PDD_CLOCK_GATE_PIT 0x1U /**< Clock gate identifier for Periodic Interrupt Timer (PIT) */ + #define SIM_PDD_CLOCK_GATE_FTM0 0x5U /**< Clock gate identifier for FlexTimer (FTM) 0 */ + #define SIM_PDD_CLOCK_GATE_FTM1 0x6U /**< Clock gate identifier for FlexTimer (FTM) 1 */ + #define SIM_PDD_CLOCK_GATE_FTM2 0x7U /**< Clock gate identifier for FlexTimer (FTM) 2 */ + #define SIM_PDD_CLOCK_GATE_CRC 0xAU /**< Clock gate identifier for CRC */ + #define SIM_PDD_CLOCK_GATE_FTMRH 0xCU /**< Clock gate identifier for Flash Memory Module (FTMRH) */ + #define SIM_PDD_CLOCK_GATE_SWD 0xDU /**< Clock gate identifier for Serial Wire Debug (SWD) */ + #define SIM_PDD_CLOCK_GATE_I2C0 0x11U /**< Clock gate identifier for Inter-Integrated Circuit (I2C0) */ + #define SIM_PDD_CLOCK_GATE_SPI0 0x12U /**< Clock gate identifier for Serial Peripheral Interface (SPI0) */ + #define SIM_PDD_CLOCK_GATE_SPI1 0x13U /**< Clock gate identifier for Serial Peripheral Interface (SPI1) */ + #define SIM_PDD_CLOCK_GATE_UART0 0x14U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART0) */ + #define SIM_PDD_CLOCK_GATE_UART1 0x15U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART1) */ + #define SIM_PDD_CLOCK_GATE_KBI0 0x18U /**< Clock gate identifier for Keyboard Interrupt (KBI0) */ + #define SIM_PDD_CLOCK_GATE_KBI1 0x19U /**< Clock gate identifier for Keyboard Interrupt (KBI1) */ + #define SIM_PDD_CLOCK_GATE_IRQ 0x1BU /**< Clock gate identifier for Interrupt (IRQ) */ + #define SIM_PDD_CLOCK_GATE_ADC 0x1DU /**< Clock gate identifier for Analog-to-digital converter (ADC) */ + #define SIM_PDD_CLOCK_GATE_ACMP0 0x1EU /**< Clock gate identifier for Analog comparator (ACMP0) */ + #define SIM_PDD_CLOCK_GATE_ACMP1 0x1FU /**< Clock gate identifier for Analog comparator (ACMP1) */ + #define SIM_PDD_CLOCK_GATE_UART2 0x16U /**< Clock gate identifier for Universal Asynchronous Receiver/Transmitter (UART2) */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_SKEAZN642)) */ +/* Clock 1 output divider constants */ +#define SIM_PDD_CLK_OUT1_DIVIDER_1 0U /**< Divide by 1 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_2 0x1U /**< Divide by 2 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_3 0x2U /**< Divide by 3 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_4 0x3U /**< Divide by 4 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_5 0x4U /**< Divide by 5 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_6 0x5U /**< Divide by 6 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_7 0x6U /**< Divide by 7 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_8 0x7U /**< Divide by 8 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_9 0x8U /**< Divide by 9 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_10 0x9U /**< Divide by 10 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_11 0xAU /**< Divide by 11 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_12 0xBU /**< Divide by 12 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_13 0xCU /**< Divide by 13 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_14 0xDU /**< Divide by 14 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_15 0xEU /**< Divide by 15 */ +#define SIM_PDD_CLK_OUT1_DIVIDER_16 0xFU /**< Divide by 16 */ + +#if ((defined(MCU_MKL03Z4)) || (defined(MCU_MKV10Z7))) +/* Clock 4 output divider constants */ + #define SIM_PDD_CLK_OUT4_DIVIDER_1 0U /**< Divide by 1 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_2 0x1U /**< Divide by 2 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_3 0x2U /**< Divide by 3 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_4 0x3U /**< Divide by 4 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_5 0x4U /**< Divide by 5 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_6 0x5U /**< Divide by 6 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_7 0x6U /**< Divide by 7 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_8 0x7U /**< Divide by 8 */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Clock 4 output divider constants */ + #define SIM_PDD_CLK_OUT4_DIVIDER_1 0U /**< Divide by 1 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_2 0x1U /**< Divide by 2 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_3 0x2U /**< Divide by 3 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_4 0x3U /**< Divide by 4 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_5 0x4U /**< Divide by 5 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_6 0x5U /**< Divide by 6 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_7 0x6U /**< Divide by 7 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_8 0x7U /**< Divide by 8 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_9 0x8U /**< Divide by 9 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_10 0x9U /**< Divide by 10 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_11 0xAU /**< Divide by 11 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_12 0xBU /**< Divide by 12 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_13 0xCU /**< Divide by 13 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_14 0xDU /**< Divide by 14 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_15 0xEU /**< Divide by 15 */ + #define SIM_PDD_CLK_OUT4_DIVIDER_16 0xFU /**< Divide by 16 */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Clock 5 output divider constants */ +#define SIM_PDD_CLK_OUT5_DIVIDER_1 0U /**< Divide by 1 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_2 0x1U /**< Divide by 2 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_3 0x2U /**< Divide by 3 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_4 0x3U /**< Divide by 4 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_5 0x4U /**< Divide by 5 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_6 0x5U /**< Divide by 6 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_7 0x6U /**< Divide by 7 */ +#define SIM_PDD_CLK_OUT5_DIVIDER_8 0x7U /**< Divide by 8 */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4))) +/* Clock sources */ + #define SIM_PDD_UART0_DISABLE_CLOCK 0U /**< Disable the clock. */ + #define SIM_PDD_UART0_FLL_CLOCK 0x4000000U /**< MCG FLL clock. */ + #define SIM_PDD_UART0_EXTERNAL_REF_CLOCK 0x8000000U /**< External reference clock. */ + #define SIM_PDD_UART0_INTERNAL_REF_CLOCK 0xC000000U /**< Internal reference clock. */ + +#else /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/* Clock sources */ + #define SIM_PDD_UART0_DISABLE_CLOCK 0U /**< Disable the clock. */ + #define SIM_PDD_UART0_PLL_FLL_CLOCK 0x4000000U /**< MCG PLL or FLL clock. */ + #define SIM_PDD_UART0_EXTERNAL_REF_CLOCK 0x8000000U /**< External reference clock. */ + #define SIM_PDD_UART0_INTERNAL_REF_CLOCK 0xC000000U /**< Internal reference clock. */ + +#endif /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/* Clock sources */ +#define SIM_PDD_LPUART1_DISABLE_CLOCK 0U /**< Disable the clock. */ +#define SIM_PDD_LPUART1_FAST_INTERNAL_REF_CLOCK 0x10000000U /**< Fast internal reference clock. */ +#define SIM_PDD_LPUART1_EXTERNAL_REF_CLOCK 0x20000000U /**< External reference clock. */ +#define SIM_PDD_LPUART1_SLOW_INTERNAL_REF_CLOCK 0x30000000U /**< Slow internal reference clock. */ + +/* 32 kHz clock source constants */ +#define SIM_PDD_LPTMR_SYSTEM_OSCILLATOR 0U /**< System oscillator (OSC32KCLK) */ +#define SIM_PDD_LPTMR_LOW_POWER_OSCILLATOR 0xC0000U /**< Low power oscillator 1kHz (LPO) */ + +/* Clock for FTMx constants */ +#define SIM_PDD_FTM_FIXED_FREQUENCY 0U /**< Fixed frequency clock (MCGFFCLK) */ +#define SIM_PDD_FTM_INTERNAL_REFERENCE 0x1000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_FTM_SYSTEM_OSCILLATOR 0x2000000U /**< System oscillator clock (OSCERCLK) */ + +/* Clock to output on the CLKOUT pin constants */ +#define SIM_PDD_CLKOUT_BUS_CLOCK 0x40U /**< Bus clock */ +#define SIM_PDD_CLKOUT_LOW_POWER_OSCILLATOR 0x60U /**< Low power oscillator 1kHz (LPO) */ +#define SIM_PDD_CLKOUT_INTERNAL_REFERENCE 0x80U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_CLKOUT_SYSTEM_OSCILLATOR 0xC0U /**< System oscillator clock (OSCERCLK) */ + +#if (defined(MCU_MKV10Z7)) +/* FTM2 external clock pin constants */ + #define SIM_PDD_FTM2_CLKIN0_PIN 0U /**< FTM2 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM2_CLKIN1_PIN 0x10000000U /**< FTM2 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM2_CLKIN2_PIN 0x20000000U /**< FTM2 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM2 external clock pin constants */ + #define SIM_PDD_FTM2_CLKIN0_PIN 0U /**< FTM2 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM2_CLKIN1_PIN 0x4000000U /**< FTM2 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* FTM1 external clock pin constants */ + #define SIM_PDD_FTM1_CLKIN0_PIN 0U /**< FTM1 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM1_CLKIN1_PIN 0x4000000U /**< FTM1 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM1_CLKIN2_PIN 0x8000000U /**< FTM1 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM1 external clock pin constants */ + #define SIM_PDD_FTM1_CLKIN0_PIN 0U /**< FTM1 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM1_CLKIN1_PIN 0x2000000U /**< FTM1 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* FTM0 external clock pin constants */ + #define SIM_PDD_FTM0_CLKIN0_PIN 0U /**< FTM0 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM0_CLKIN1_PIN 0x1000000U /**< FTM0 external clock driven by FTM_CLKIN1 pin */ + #define SIM_PDD_FTM0_CLKIN2_PIN 0x2000000U /**< FTM0 external clock driven by FTM_CLKIN2 pin */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM0 external clock pin constants */ + #define SIM_PDD_FTM0_CLKIN0_PIN 0U /**< FTM0 external clock driven by FTM_CLKIN0 pin */ + #define SIM_PDD_FTM0_CLKIN1_PIN 0x1000000U /**< FTM0 external clock driven by FTM_CLKIN1 pin */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FTM2 channel 1 input capture source constants */ +#define SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1 0U /**< FTM2_CH1 pin is fed to FTM2 CH1 */ +#define SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1_XOR_FTM2_CH0_XOR_FTM1_CH1 0x400000U /**< FTM2_CH1 pin XOR FTM2_CH0 pin XOR FTM1_CH1 pin is fed to FTM2 CH1 */ + +/* FTM2 channel 0 input capture source constants */ +#define SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0 0U /**< FTM2_CH0 signal */ +#define SIM_PDD_FTM2_CH0_INPUT_CMP0 0x100000U /**< CMP0 output */ +#define SIM_PDD_FTM2_CH0_INPUT_CMP1 0x200000U /**< CMP1 output */ + +/* FTM1 channel 0 input capture source constants */ +#define SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0 0U /**< FTM1_CH0 signal */ +#define SIM_PDD_FTM1_CH0_INPUT_CMP0 0x40000U /**< CMP0 output */ +#define SIM_PDD_FTM1_CH0_INPUT_CMP1 0x80000U /**< CMP1 output */ + +/* Source of FTM2 hardware trigger 2 constants */ +#define SIM_PDD_FTM2_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM2_TRIGGER2_CMP1_OUTPUT 0x8000U /**< CMP1 output */ + +/* Source of FTM2 hardware trigger 1 constants */ +#define SIM_PDD_FTM2_TRIGGER1_PDB_TRIGGER1 0U /**< PDB output trigger 1 */ +#define SIM_PDD_FTM2_TRIGGER1_FTM1_MATCH 0x4000U /**< FTM1 channel match */ + +/* Source of FTM2 hardware trigger 0 constants */ +#define SIM_PDD_FTM2_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM2_TRIGGER0_FTM0_MATCH 0x2000U /**< FTM0 channel match */ + +/* Source of FTM1 hardware trigger 2 constants */ +#define SIM_PDD_FTM1_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM1_TRIGGER2_CMP1_OUTPUT 0x1000U /**< CMP1 output */ + +/* Source of FTM1 hardware trigger 1 constants */ +#define SIM_PDD_FTM1_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ +#define SIM_PDD_FTM1_TRIGGER1_FTM2_MATCH 0x800U /**< FTM2 channel match */ + +/* Source of FTM1 hardware trigger 0 constants */ +#define SIM_PDD_FTM1_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM1_TRIGGER0_FTM0_MATCH 0x400U /**< FTM0 channel match */ + +/* Source of FTM0 hardware trigger 2 constants */ +#define SIM_PDD_FTM0_TRIGGER2_CMP0_OUTPUT 0U /**< CMP0 output */ +#define SIM_PDD_FTM0_TRIGGER2_CMP1_OUTPUT 0x200U /**< CMP1 output */ + +#if (defined(MCU_MKV10Z7)) +/* Source of FTM0 hardware trigger 1 constants */ + #define SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ + #define SIM_PDD_FTM0_TRIGGER1_FTM2_MATCH 0x100U /**< FTM2 channel match */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 hardware trigger 1 constants */ + #define SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1 0U /**< PDB channel 1 trigger */ + #define SIM_PDD_FTM0_TRIGGER1_FTM2_MATCH 0x20000000U /**< FTM2 channel match */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM0 hardware trigger 0 constants */ + #define SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ + #define SIM_PDD_FTM0_TRIGGER0_FTM1_MATCH 0x80U /**< FTM1 channel match */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 hardware trigger 0 constants */ + #define SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT 0U /**< CMP0 output */ + #define SIM_PDD_FTM0_TRIGGER0_FTM1_MATCH 0x10000000U /**< FTM1 channel match */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM2 fault 0 constants */ + #define SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN 0U /**< FTM2_FLT0 pin */ + #define SIM_PDD_FTM2_FAULT0_CMP0_OUTPUT 0x8U /**< CMP0 output */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM2 fault 0 constants */ + #define SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN 0U /**< FTM2_FLT0 pin */ + #define SIM_PDD_FTM2_FAULT0_CMP0_OUTPUT 0x100U /**< CMP0 output */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if (defined(MCU_MKV10Z7)) +/* Source of FTM1 fault 0 constants */ + #define SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN 0U /**< FTM1_FLT0 pin */ + #define SIM_PDD_FTM1_FAULT0_CMP0_OUTPUT 0x4U /**< CMP0 output */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM1 fault 0 constants */ + #define SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN 0U /**< FTM1_FLT0 pin */ + #define SIM_PDD_FTM1_FAULT0_CMP0_OUTPUT 0x10U /**< CMP0 output */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Source of FTM0 fault 1 constants */ +#define SIM_PDD_FTM0_FAULT1_FTM0_FLT1_PIN 0U /**< FTM0_FLT1 pin */ +#define SIM_PDD_FTM0_FAULT1_CMP1_OUTPUT 0x2U /**< CMP1 output */ + +/* Source of FTM0 fault 0 constants */ +#define SIM_PDD_FTM0_FAULT0_FTM0_FLT0_PIN 0U /**< FTM0_FLT0 pin */ +#define SIM_PDD_FTM0_FAULT0_CMP1_OUTPUT 0x1U /**< CMP1 output */ + +/* Source of UART 1 RxD constants */ +#define SIM_PDD_UART1_RX_PIN 0U /**< UART1_RX pin */ +#define SIM_PDD_UART1_CMP0_OUTPUT 0x40U /**< CMP0 output */ +#define SIM_PDD_UART1_CMP1_OUTPUT 0x80U /**< CMP1 output */ + +/* Source of UART 1 TxD constants */ +#define SIM_PDD_UART1_TX_PIN 0U /**< UART1_TX pin */ +#define SIM_PDD_UART1_TX_PIN_MUDULATED_FTM1_CHANNEL0 0x10U /**< UART1 Tx pin modulated with FTM1 channel 0 output */ +#define SIM_PDD_UART1_TX_PIN_MUDULATED_FTM2_CHANNEL0 0x20U /**< UART1 Tx pin modulated with FTM2 channel 0 output */ + +/* Source of UART 0 RxD constants */ +#define SIM_PDD_UART0_RX_PIN 0U /**< UART1_RX pin */ +#define SIM_PDD_UART0_CMP0_OUTPUT 0x4U /**< CMP0 output */ +#define SIM_PDD_UART0_CMP1_OUTPUT 0x8U /**< CMP1 output */ + +/* Source of UART 0 TxD constants */ +#define SIM_PDD_UART0_TX_PIN 0U /**< UART1_TX pin */ +#define SIM_PDD_UART0_TX_PIN_MUDULATED_FTM1_CHANNEL0 0x10U /**< UART1 Tx pin modulated with FTM1 channel 0 output */ +#define SIM_PDD_UART0_TX_PIN_MUDULATED_FTM2_CHANNEL0 0x20U /**< UART1 Tx pin modulated with FTM2 channel 0 output */ + +/* ADC1 alternate clock source constants */ +#define SIM_PDD_ADC1_ALT_CLK_CORE_CLK_DIV_5 0U /**< Core frequency divided by 5 (OUTDIV5) */ +#define SIM_PDD_ADC1_ALT_CLK_INTERNAL_REFERENCE 0x4000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_ADC1_ALT_CLK_SYSTEM_OSCILLATOR 0x8000000U /**< System oscillator clock (OSCERCLK) */ + +/* ADC0 alternate clock source constants */ +#define SIM_PDD_ADC0_ALT_CLK_CORE_CLK_DIV_5 0U /**< Core frequency divided by 5 (OUTDIV5) */ +#define SIM_PDD_ADC0_ALT_CLK_INTERNAL_REFERENCE 0x1000000U /**< Internal reference clock (MCGIRCLK) */ +#define SIM_PDD_ADC0_ALT_CLK_SYSTEM_OSCILLATOR 0x2000000U /**< System oscillator clock (OSCERCLK) */ + +/* ADC1 pre-trigger source constants */ +#define SIM_PDD_ADC1_PRE_TRIGGER_A 0U /**< Pre-trigger A */ +#define SIM_PDD_ADC1_PRE_TRIGGER_B 0x1000U /**< Pre-trigger B */ + +/* ADC1 trigger source constants */ +#define SIM_PDD_ADC1_TRIGGER_EXTERNAL_PIN 0U /**< External trigger pin input (PDB0_EXTRG) */ +#define SIM_PDD_ADC1_TRIGGER_CMP0_OUTPUT 0x100U /**< HSCMP0 output */ +#define SIM_PDD_ADC1_TRIGGER_CMP1_OUTPUT 0x200U /**< HSCMP1 output */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL0_COMPLETE 0x400U /**< DMA channel 0 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL1_COMPLETE 0x500U /**< DMA channel 1 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL2_COMPLETE 0x600U /**< DMA channel 2 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_DMA_CHANNEL3_COMPLETE 0x700U /**< DMA channel 3 transfer last write complete */ +#define SIM_PDD_ADC1_TRIGGER_FTM0_OVERFLOW 0x800U /**< FTM0 overflow */ +#define SIM_PDD_ADC1_TRIGGER_FTM1_OVERFLOW 0x900U /**< FTM1 overflow */ +#define SIM_PDD_ADC1_TRIGGER_FTM2_OVERFLOW 0xA00U /**< FTM2 overflow */ +#define SIM_PDD_ADC1_TRIGGER_LOW_POWER_TIMER0 0xE00U /**< LPTMR0 trigger */ + +/* ADC0 pre-trigger source constants */ +#define SIM_PDD_ADC0_PRE_TRIGGER_A 0U /**< Pre-trigger A */ +#define SIM_PDD_ADC0_PRE_TRIGGER_B 0x10U /**< Pre-trigger B */ + +/* ADC0 trigger source constants */ +#define SIM_PDD_ADC0_TRIGGER_EXTERNAL_PIN 0U /**< External trigger pin input (PDB0_EXTRG) */ +#define SIM_PDD_ADC0_TRIGGER_CMP0_OUTPUT 0x1U /**< HSCMP0 output */ +#define SIM_PDD_ADC0_TRIGGER_CMP1_OUTPUT 0x2U /**< HSCMP1 output */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL0_COMPLETE 0x4U /**< DMA channel 0 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL1_COMPLETE 0x5U /**< DMA channel 1 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL2_COMPLETE 0x6U /**< DMA channel 2 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_DMA_CHANNEL3_COMPLETE 0x7U /**< DMA channel 3 transfer last write complete */ +#define SIM_PDD_ADC0_TRIGGER_FTM0_OVERFLOW 0x8U /**< FTM0 overflow */ +#define SIM_PDD_ADC0_TRIGGER_FTM1_OVERFLOW 0x9U /**< FTM1 overflow */ +#define SIM_PDD_ADC0_TRIGGER_FTM2_OVERFLOW 0xAU /**< FTM2 overflow */ +#define SIM_PDD_ADC0_TRIGGER_LOW_POWER_TIMER0 0xEU /**< LPTMR0 trigger */ + +#if (defined(MCU_MKV10Z7)) +/* V-family ID constant. */ + #define SIM_PDD_V_FAMILY_ID_MKV10ZX 0x10000000U /**< MKV10Zx V-family device ID */ + +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* V-family ID constant. */ + #define SIM_PDD_V_FAMILY_ID_MKW24ZX 0x10U /**< MKW24Zx W-family device ID */ + +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Sub-family ID constant. */ +#define SIM_PDD_SUB_FAMILY_ID_MKV10XXXX 0U /**< MKV10xxxx sub-family device ID */ + +/* Series ID constant. */ +#define SIM_PDD_SERIES_ID_V_FAMILY_MOTOR_CONTROL 0x600000U /**< V-family - motor control series ID */ + +/* System SRAM size constant. */ +#define SIM_PDD_SYSTEM_SRAM_512B 0U /**< System SRAM size is 512B */ +#define SIM_PDD_SYSTEM_SRAM_1KB 0x10000U /**< System SRAM size is 1kB */ +#define SIM_PDD_SYSTEM_SRAM_2KB 0x20000U /**< System SRAM size is 2kB */ +#define SIM_PDD_SYSTEM_SRAM_4KB 0x30000U /**< System SRAM size is 4kB */ +#define SIM_PDD_SYSTEM_SRAM_8KB 0x40000U /**< System SRAM size is 8kB */ +#define SIM_PDD_SYSTEM_SRAM_16KB 0x50000U /**< System SRAM size is 16kB */ +#define SIM_PDD_SYSTEM_SRAM_32KB 0x60000U /**< System SRAM size is 32kB */ +#define SIM_PDD_SYSTEM_SRAM_64KB 0x70000U /**< System SRAM size is 64kB */ + +/* Pincount indetification constant. */ +#define SIM_PDD_PINCOUNT_ID_32 0x2U /**< 32 pincount */ +#define SIM_PDD_PINCOUNT_ID_48 0x4U /**< 48 pincount */ +#define SIM_PDD_PINCOUNT_ID_64 0x5U /**< 64 pincount */ +#define SIM_PDD_PINCOUNT_ID_80 0x6U /**< 80 pincount */ +#define SIM_PDD_PINCOUNT_ID_81 0x7U /**< 81 pincount */ +#define SIM_PDD_PINCOUNT_ID_100 0x8U /**< 100 pincount */ +#define SIM_PDD_PINCOUNT_ID_121 0x9U /**< 121 pincount */ +#define SIM_PDD_PINCOUNT_ID_144 0xAU /**< 144 pincount */ +#define SIM_PDD_PINCOUNT_ID_196 0xCU /**< 196 pincount */ +#define SIM_PDD_PINCOUNT_ID_256 0xEU /**< 256 pincount */ + +/* Program flash size constants. */ +#define SIM_PDD_PROGRAM_FLASH_8KB_PROTECTION_256B 0U /**< 8 KB of program flash memory, 0.25 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_16KB_PROTECTION_512B 0x1000000U /**< 16 KB of program flash memory, 0.5 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_32KB_PROTECTION_1KB 0x3000000U /**< 32 KB of program flash memory, 1 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_64KB_PROTECTION_2KB 0x5000000U /**< 64 KB of program flash memory, 2 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_128KB_PROTECTION_4KB 0x7000000U /**< 128 KB of program flash memory, 4 KB protection region */ +#define SIM_PDD_PROGRAM_FLASH_256KB_PROTECTION_4KB 0x9000000U /**< 256 KB of program flash memory, 4 KB protection region */ + +/* Watchdog clock source constants */ +#define SIM_PDD_WDOG_INTERNAL_1KHZ 0U /**< Internal 1 kHz clock is source to watchdog */ +#define SIM_PDD_WDOG_INTERNAL_REFERENCE 0x2U /**< Internal reference clock (MCGIRCLK) is source to watchdog */ + + +/* ---------------------------------------------------------------------------- + -- SetClockGate + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + ) \ + ) +#elif ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + SIM_SCGC_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU)))) \ + ) +#elif ((defined(MCU_MK10D5)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4))) +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x5U) ? ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + )) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ +/** + * @brief Enable or disable clock gate for specified device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Parameter specifying which device will be addressed. Use + * constants from group 'Clock gate identifiers'. This parameter is of index type. + * @param State Parameter specifying if clock gate will be enabled or disabled. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in + * PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC1, SIM_SCGC2, + * SIM_SCGC3, SIM_SCGC4, SIM_SCGC5, SIM_SCGC6, SIM_SCGC7, SIM_SCGC + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetClockGate(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ + #define SIM_PDD_SetClockGate(PeripheralBase, Index, State) ( \ + ((uint32)((uint32)(Index) >> 5U) == 0U) ? ( \ + SIM_SCGC1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x1U) ? ( \ + SIM_SCGC2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x2U) ? ( \ + SIM_SCGC3_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC3_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x3U) ? ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x4U) ? ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : (((uint32)((uint32)(Index) >> 5U) == 0x5U) ? ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC6_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) : ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SCGC7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)0x1U << (uint8)((uint8)(Index) & 0x1FU)))))) | ( \ + (uint32)((uint32)(State) << (uint8)((uint8)(Index) & 0x1FU))))) \ + ))))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemResetStatusIDReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system reset status and ID register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SRSID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemResetStatusIDReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemResetStatusIDReg(PeripheralBase) ( \ + SIM_SRSID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption0Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Writes new value specified by the Value parameter into system options + * 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WriteSystemOption0Reg(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_WriteSystemOption0Reg(PeripheralBase, Value) ( \ + SIM_SOPT0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into system options + * 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WriteSystemOption0Reg(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_WriteSystemOption0Reg(PeripheralBase, Value) ( \ + SIM_SOPT_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption0Reg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Reads system options 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption0Reg(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_ReadSystemOption0Reg(PeripheralBase) ( \ + SIM_SOPT0_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads system options 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption0Reg(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_ReadSystemOption0Reg(PeripheralBase) ( \ + SIM_SOPT_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WritePinSelection0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into pin selection 0 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the pin selection 0 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_PINSEL, SIM_PINSEL0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_WritePinSelection0Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WritePinSelection0Reg(PeripheralBase, Value) ( \ + SIM_PINSEL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniversallyUniqueIdentifierLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads Universally Unique Identifier Low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UUIDL. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniversallyUniqueIdentifierLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniversallyUniqueIdentifierLowReg(PeripheralBase) ( \ + SIM_UUIDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTriggerDelay + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE04Z1284)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284))) +/** + * @brief Set ADC HW trigger delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Delay Parameter specifying the requested ADC HW trigger delay. Value + * should be in range from 0 to 255. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetTriggerDelay(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetTriggerDelay(PeripheralBase, Delay) ( \ + SIM_SOPT0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT0_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT0_DELAY_MASK))) | ( \ + (uint32)((uint32)(Delay) << SIM_SOPT0_DELAY_SHIFT))) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Set ADC HW trigger delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Delay Parameter specifying the requested ADC HW trigger delay. Value + * should be in range from 0 to 255. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT, SIM_SOPT0 + * (depending on the peripheral). + * @par Example: + * @code + * SIM_PDD_SetTriggerDelay(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetTriggerDelay(PeripheralBase, Delay) ( \ + SIM_SOPT_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT_DELAY_MASK))) | ( \ + (uint32)((uint32)(Delay) << SIM_SOPT_DELAY_SHIFT))) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z4)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption1Reg(PeripheralBase, Value) ( \ + SIM_SOPT1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption1Reg(PeripheralBase) ( \ + SIM_SOPT1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WritePinSelection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into pin selection 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the pin selection 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_PINSEL1. + * @par Example: + * @code + * SIM_PDD_WritePinSelection1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WritePinSelection1Reg(PeripheralBase, Value) ( \ + SIM_PINSEL1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPinSelection1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads pin selection 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_PINSEL1. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadPinSelection1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadPinSelection1Reg(PeripheralBase) ( \ + SIM_PINSEL1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniversallyUniqueIdentifierMidHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads Universally Unique Identifier Middle High register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UUIDMH. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniversallyUniqueIdentifierMidHighReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniversallyUniqueIdentifierMidHighReg(PeripheralBase) ( \ + SIM_UUIDMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock divider register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockDividerReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockDividerReg(PeripheralBase, Value) ( \ + SIM_CLKDIV_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockDividerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock divider register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_CLKDIV. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockDividerReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockDividerReg(PeripheralBase) ( \ + SIM_CLKDIV_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSourceUART0 + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL02Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4))) +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, FLL_CLOCK, + * EXTERNAL_REF_CLOCK, INTERNAL_REF_CLOCK. This parameter is of "Clock sources" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceUART0(_BASE_PTR, + * SIM_PDD_UART0_DISABLE_CLOCK); + * @endcode + */ + #define SIM_PDD_SetClockSourceUART0(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT2_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT2_UART0SRC_MASK))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, PLL_FLL_CLOCK, + * EXTERNAL_REF_CLOCK, INTERNAL_REF_CLOCK. This parameter is of "Clock + * sources" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceUART0(_BASE_PTR, + * SIM_PDD_UART0_DISABLE_CLOCK); + * @endcode + */ + #define SIM_PDD_SetClockSourceUART0(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT2_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT2_UART0SRC_MASK))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption2Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption2Reg(PeripheralBase) ( \ + SIM_SOPT2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 2 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption2Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption2Reg(PeripheralBase, Value) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption4Reg(PeripheralBase) ( \ + SIM_SOPT4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 4 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption4Reg(PeripheralBase, Value) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption5Reg(PeripheralBase) ( \ + SIM_SOPT5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 5 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption5Reg(PeripheralBase, Value) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption7Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption7Reg(PeripheralBase) ( \ + SIM_SOPT7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 7 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption7Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption7Reg(PeripheralBase, Value) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating4Reg(PeripheralBase) ( \ + SIM_SCGC4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 4. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 4. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * SIM_PDD_WriteClockGating4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating4Reg(PeripheralBase, Value) ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating5Reg(PeripheralBase) ( \ + SIM_SCGC5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 5. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 5. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * SIM_PDD_WriteClockGating5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating5Reg(PeripheralBase, Value) ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockGating6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock gating control register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadClockGating6Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadClockGating6Reg(PeripheralBase) ( \ + SIM_SCGC6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockGating6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clock gating + * control register 6. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock gating control register 6. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * SIM_PDD_WriteClockGating6Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteClockGating6Reg(PeripheralBase, Value) ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock1OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock 1 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 1 output divider. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock1OutputDivider(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_SetClock1OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV1_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock4OutputDivider + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL03Z4)) || (defined(MCU_MKV10Z7))) +/** + * @brief Sets clock 4 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 4 output divider. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock4OutputDivider(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetClock4OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV4_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV4_SHIFT))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Sets clock 4 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 4 output divider. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock4OutputDivider(_BASE_PTR, 1); + * @endcode + */ + #define SIM_PDD_SetClock4OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV4_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV4_SHIFT))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- ReadFlashConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadFlashConfiguration1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadFlashConfiguration1Reg(PeripheralBase) ( \ + SIM_FCFG1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFlashConfiguration1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into flash + * configuration 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the flash configuration 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_WriteFlashConfiguration1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteFlashConfiguration1Reg(PeripheralBase, Value) ( \ + SIM_FCFG1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFlashConfiguration2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads flash configuration 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG2. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadFlashConfiguration2Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadFlashConfiguration2Reg(PeripheralBase) ( \ + SIM_FCFG2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationMidHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification mid-high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDMH. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationMidHighReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationMidHighReg(PeripheralBase) ( \ + SIM_UIDMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationMidLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification mid-low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDML. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationMidLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationMidLowReg(PeripheralBase) ( \ + SIM_UIDML_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUniqueIdentificationLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads unique identification low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_UIDL. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadUniqueIdentificationLowReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadUniqueIdentificationLowReg(PeripheralBase) ( \ + SIM_UIDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCOPControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads COP control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_COPC. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadCOPControlReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadCOPControlReg(PeripheralBase) ( \ + SIM_COPC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCOPControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into COP control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the COP control register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_COPC. + * @par Example: + * @code + * SIM_PDD_WriteCOPControlReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteCOPControlReg(PeripheralBase, Value) ( \ + SIM_COPC_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCOPServiceReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into COP service + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the COP service register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SRVCOP. + * @par Example: + * @code + * SIM_PDD_WriteCOPServiceReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteCOPServiceReg(PeripheralBase, Value) ( \ + SIM_SRVCOP_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSourceLPUART1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock source (in the SIM module). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. Possible values: DISABLE_CLOCK, + * FAST_INTERNAL_REF_CLOCK, EXTERNAL_REF_CLOCK, SLOW_INTERNAL_REF_CLOCK. This parameter is + * of "Clock sources" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SetClockSourceLPUART1(_BASE_PTR, + * SIM_PDD_LPUART1_DISABLE_CLOCK); + * @endcode + */ +#define SIM_PDD_SetClockSourceLPUART1(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_LPUART1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectLptrm32kHzClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the 32 kHz clock source (ERCLK32K) for LPTMR. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Clock source. The user should use one from the enumerated + * values. This parameter is of "32 kHz clock source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT1. + * @par Example: + * @code + * SIM_PDD_SelectLptrm32kHzClockSource(_BASE_PTR, + * SIM_PDD_LPTMR_SYSTEM_OSCILLATOR); + * @endcode + */ +#define SIM_PDD_SelectLptrm32kHzClockSource(PeripheralBase, Source) ( \ + SIM_SOPT1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT1_OSC32KSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtmClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the fixed frequency clock for FTM0, FTM1 and FTM2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTMx clock source. The user should use one from the enumerated + * values. This parameter is of "Clock for FTMx constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SelectFtmClockSource(_BASE_PTR, + * SIM_PDD_FTM_FIXED_FREQUENCY); + * @endcode + */ +#define SIM_PDD_SelectFtmClockSource(PeripheralBase, Source) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_FTMFFCLKSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectClkOutPinClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock to output on the CLKOUT pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkOut Clock to output on the CLKOUT pin source. The user should use + * one from the enumerated values. This parameter is of "Clock to output on + * the CLKOUT pin constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT2. + * @par Example: + * @code + * SIM_PDD_SelectClkOutPinClock(_BASE_PTR, + * SIM_PDD_CLKOUT_BUS_CLOCK); + * @endcode + */ +#define SIM_PDD_SelectClkOutPinClock(PeripheralBase, ClkOut) ( \ + SIM_SOPT2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT2_CLKOUTSEL_MASK)))) | ( \ + (uint32)(ClkOut))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 2 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM2 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM2 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM2_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm2ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 1 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM1 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM1 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM1_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm1ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0ExternalClockPin + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the flex timer 0 external clock pin. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ExtPin FTM0 external clock pin select. The user should use one from + * the enumerated values. This parameter is of "FTM0 external clock pin + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0ExternalClockPin(_BASE_PTR, + * SIM_PDD_FTM0_CLKIN0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0ExternalClockPin(PeripheralBase, ExtPin) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0CLKSEL_MASK)))) | ( \ + (uint32)(ExtPin))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Channel1InputCaptureSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for flex timer 2 channel 1 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 1 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 1 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel1InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH1_INPUT_FTM2_CH1); + * @endcode + */ +#define SIM_PDD_SelectFtm2Channel1InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2ICH1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Channel0InputCaptureSource + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Selects the source for flex timer 2 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm2Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2ICH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects the source for flex timer 2 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM2 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM2 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM2_CH0_INPUT_FTM2_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm2Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2CH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SelectFtm1Channel0InputCaptureSource + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Selects the source for flex timer 1 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM1 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM1 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm1Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1ICH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Selects the source for flex timer 1 channel 0 input capture. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source FTM1 channel 0 input capture source. The user should use one + * from the enumerated values. This parameter is of "FTM1 channel 0 input + * capture source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Channel0InputCaptureSource(_BASE_PTR, + * SIM_PDD_FTM1_CH0_INPUT_FTM1_CH0); + * @endcode + */ + #define SIM_PDD_SelectFtm1Channel0InputCaptureSource(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1CH0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER1_PDB_TRIGGER1); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM2 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM2_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm2HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM2TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER1_PDB_CHANNEL1); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM1 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM1_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm1HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM1TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0HardwareTrigger2Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 2. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 2. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 2 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0HardwareTrigger2Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER2_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm0HardwareTrigger2Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG2SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Hardw0areTrigger1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 1. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 1 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Hardw0areTrigger1Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER1_PDB_CHANNEL1); + * @endcode + */ +#define SIM_PDD_SelectFtm0Hardw0areTrigger1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG1SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0HardwareTrigger0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 hardware trigger 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 hardware trigger 0. The user should use one from + * the enumerated values. This parameter is of "Source of FTM0 hardware + * trigger 0 constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0HardwareTrigger0Source(_BASE_PTR, + * SIM_PDD_FTM0_TRIGGER0_CMP0_OUTPUT); + * @endcode + */ +#define SIM_PDD_SelectFtm0HardwareTrigger0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT4_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT4_FTM0TRG0SRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm2Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 2 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM2 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM2 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm2Fault0Source(_BASE_PTR, + * SIM_PDD_FTM2_FAULT0_FTM2_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm2Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM2FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm1Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 1 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM1 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM1 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm1Fault0Source(_BASE_PTR, + * SIM_PDD_FTM1_FAULT0_FTM1_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm1Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM1FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Fault1Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 fault 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 fault 1. The user should use one from the + * enumerated values. This parameter is of "Source of FTM0 fault 1 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Fault1Source(_BASE_PTR, + * SIM_PDD_FTM0_FAULT1_FTM0_FLT1_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0Fault1Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM0FLT1_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectFtm0Fault0Source + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source of flex timer 0 fault 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of FTM0 fault 0. The user should use one from the + * enumerated values. This parameter is of "Source of FTM0 fault 0 constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT4. + * @par Example: + * @code + * SIM_PDD_SelectFtm0Fault0Source(_BASE_PTR, + * SIM_PDD_FTM0_FAULT0_FTM0_FLT0_PIN); + * @endcode + */ +#define SIM_PDD_SelectFtm0Fault0Source(PeripheralBase, Source) ( \ + SIM_SOPT4_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT4_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT4_FTM0FLT0_MASK))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUart1OpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the open drain on UART1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of open drain on UART1. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_EnableUart1OpenDrain(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableUart1OpenDrain(PeripheralBase, State) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT5_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT5_UART1ODE_MASK))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT5_UART1ODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableUart0OpenDrain + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables the open drain on UART0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of open drain on UART0. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_EnableUart0OpenDrain(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableUart0OpenDrain(PeripheralBase, State) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SIM_SOPT5_REG(PeripheralBase) & (uint32)(~(uint32)SIM_SOPT5_UART0ODE_MASK))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT5_UART0ODE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart1RxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 1 receive data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 1 receive data. The user should use one from the + * enumerated values. This parameter is of "Source of UART 1 RxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart1RxDataSource(_BASE_PTR, + * SIM_PDD_UART1_RX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart1RxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1RXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart1TxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 1 transmit data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 1 transmit data. The user should use one from + * the enumerated values. This parameter is of "Source of UART 1 TxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart1TxDataSource(_BASE_PTR, + * SIM_PDD_UART1_TX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart1TxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1TXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart0RxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 0 receive data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 0 receive data. The user should use one from the + * enumerated values. This parameter is of "Source of UART 0 RxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart0RxDataSource(_BASE_PTR, + * SIM_PDD_UART0_RX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart0RxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART0RXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectUart0TxDataSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the source for the UART 0 transmit data. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Source of UART 0 transmit data. The user should use one from + * the enumerated values. This parameter is of "Source of UART 0 TxD + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT5. + * @par Example: + * @code + * SIM_PDD_SelectUart0TxDataSource(_BASE_PTR, + * SIM_PDD_UART0_TX_PIN); + * @endcode + */ +#define SIM_PDD_SelectUart0TxDataSource(PeripheralBase, Source) ( \ + SIM_SOPT5_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT5_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT5_UART1TXSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1AlternateClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC1 alternate clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 alternate clock source. The user should use one from the + * enumerated values. This parameter is of "ADC1 alternate clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1AlternateClockSource(_BASE_PTR, + * SIM_PDD_ADC1_ALT_CLK_CORE_CLK_DIV_5); + * @endcode + */ +#define SIM_PDD_SelectAdc1AlternateClockSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1ALTCLKSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0AlternateClockSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects ADC0 alternate clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 alternate clock source. The user should use one from the + * enumerated values. This parameter is of "ADC0 alternate clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0AlternateClockSource(_BASE_PTR, + * SIM_PDD_ADC0_ALT_CLK_CORE_CLK_DIV_5); + * @endcode + */ +#define SIM_PDD_SelectAdc0AlternateClockSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0ALTCLKSRC_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAdc1AlternateTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables alternative conversion triggers for ADC1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ADC1 alternate trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_EnableAdc1AlternateTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableAdc1AlternateTrigger(PeripheralBase, State) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1ALTTRGEN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1PreTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC1 pre-trigger source when alternative triggers are + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 pre-trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC1 pre-trigger source constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1PreTriggerSource(_BASE_PTR, + * SIM_PDD_ADC1_PRE_TRIGGER_A); + * @endcode + */ +#define SIM_PDD_SelectAdc1PreTriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1PRETRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc1TriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC1 trigger source when alternative triggers are + * functional in Stop and VLPS modes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC1 trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC1 trigger source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc1TriggerSource(_BASE_PTR, + * SIM_PDD_ADC1_TRIGGER_EXTERNAL_PIN); + * @endcode + */ +#define SIM_PDD_SelectAdc1TriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC1TRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAdc0AlternateTrigger + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables alternative conversion triggers for ADC0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ADC0 alternate trigger. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_EnableAdc0AlternateTrigger(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableAdc0AlternateTrigger(PeripheralBase, State) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0ALTTRGEN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0PreTriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC0 pre-trigger source when alternative triggers are + * enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 pre-trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC0 pre-trigger source constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0PreTriggerSource(_BASE_PTR, + * SIM_PDD_ADC0_PRE_TRIGGER_A); + * @endcode + */ +#define SIM_PDD_SelectAdc0PreTriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0PRETRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectAdc0TriggerSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the ADC0 trigger source when alternative triggers are + * functional in Stop and VLPS modes. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source ADC0 trigger source. The user should use one from the + * enumerated values. This parameter is of "ADC0 trigger source constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT7. + * @par Example: + * @code + * SIM_PDD_SelectAdc0TriggerSource(_BASE_PTR, + * SIM_PDD_ADC0_TRIGGER_EXTERNAL_PIN); + * @endcode + */ +#define SIM_PDD_SelectAdc0TriggerSource(PeripheralBase, Source) ( \ + SIM_SOPT7_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_SOPT7_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_SOPT7_ADC0TRGSEL_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemOption8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system options 8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SOPT8. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadSystemOption8Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemOption8Reg(PeripheralBase) ( \ + SIM_SOPT8_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemOption8Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system options + * 8 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system options 8 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SOPT8. + * @par Example: + * @code + * SIM_PDD_WriteSystemOption8Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemOption8Reg(PeripheralBase, Value) ( \ + SIM_SOPT8_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetVFamilyDeviceId + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns the V-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "V-family ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetVFamilyDeviceId(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_GetVFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_FAMID_MASK) \ + ) +#else /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/** + * @brief Returns the W-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "V-family ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetVFamilyDeviceId(_BASE_PTR); + * @endcode + */ + #define SIM_PDD_GetVFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_FAMID_MASK) \ + ) +#endif /* (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ + +/* ---------------------------------------------------------------------------- + -- GetSubFamilyDeviceId + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the sub-family ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Sub-family ID constant." type. The value is cast + * to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSubFamilyDeviceId(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSubFamilyDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SUBFAMID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSeriesDeviceId + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the series ID of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Series ID constant." type. The value is cast to + * "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSeriesDeviceId(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSeriesDeviceId(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SERIERID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSystemSramSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the system SRAM size. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "System SRAM size constant." type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetSystemSramSize(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetSystemSramSize(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_SRAMSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceRevisionNumber + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns device revision number value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint8 result = SIM_PDD_GetDeviceRevisionNumber(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetDeviceRevisionNumber(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_REVID_MASK)) >> ( \ + SIM_SDID_REVID_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDeviceDieNumber + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns device die number value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint8 result = SIM_PDD_GetDeviceDieNumber(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetDeviceDieNumber(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_DIEID_MASK)) >> ( \ + SIM_SDID_DIEID_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPincountIndetification + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the pincount indetification of the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Pincount indetification constant." type. The + * value is cast to "uint32". + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_GetPincountIndetification(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetPincountIndetification(PeripheralBase) ( \ + (uint32)(SIM_SDID_REG(PeripheralBase) & SIM_SDID_PINID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemDeviceIdentificationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system device identification register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SDID. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemDeviceIdentificationReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemDeviceIdentificationReg(PeripheralBase) ( \ + SIM_SDID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl4Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl4Reg(PeripheralBase) ( \ + SIM_SCGC4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 4 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC4. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl4Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl4Reg(PeripheralBase, Value) ( \ + SIM_SCGC4_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl5Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl5Reg(PeripheralBase) ( \ + SIM_SCGC5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 5 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC5. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl5Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl5Reg(PeripheralBase, Value) ( \ + SIM_SCGC5_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl6Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl6Reg(PeripheralBase) ( \ + SIM_SCGC6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl6Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 6 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 6 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC6. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl6Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl6Reg(PeripheralBase, Value) ( \ + SIM_SCGC6_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockGatingControl7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock gating control 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_SCGC7. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockGatingControl7Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockGatingControl7Reg(PeripheralBase) ( \ + SIM_SCGC7_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockGatingControl7Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * gating control 7 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock gating control 7 + * register. This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_SCGC7. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockGatingControl7Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockGatingControl7Reg(PeripheralBase, Value) ( \ + SIM_SCGC7_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableClock5OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the clock 5 output divider control. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of clock 5 output divider control. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_EnableClock5OutputDivider(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableClock5OutputDivider(PeripheralBase, State) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV5EN_MASK)))) | ( \ + (uint32)((uint32)(State) << SIM_CLKDIV1_OUTDIV5EN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClock5OutputDivider + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock 5 output divider Value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divider New value of the clock 5 output divider. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_SetClock5OutputDivider(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_SetClock5OutputDivider(PeripheralBase, Divider) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_CLKDIV1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_CLKDIV1_OUTDIV5_MASK)))) | ( \ + (uint32)((uint32)(Divider) << SIM_CLKDIV1_OUTDIV5_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSystemClockDivider1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads system clock divider 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_ReadSystemClockDivider1Reg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadSystemClockDivider1Reg(PeripheralBase) ( \ + SIM_CLKDIV1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSystemClockDivider1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into system clock + * divider 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the system clock divider 1 register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_CLKDIV1. + * @par Example: + * @code + * SIM_PDD_WriteSystemClockDivider1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteSystemClockDivider1Reg(PeripheralBase, Value) ( \ + SIM_CLKDIV1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetProgramFlashSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the amount of program flash memory available on the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Program flash size constants." type. The value is + * cast to "uint32". + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * uint32 result = SIM_PDD_GetProgramFlashSize(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetProgramFlashSize(PeripheralBase) ( \ + (uint32)(SIM_FCFG1_REG(PeripheralBase) & SIM_FCFG1_PFSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashMemoryInDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the flash memory for the duration of doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of flash memory for the duration of doze mode. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_EnableFlashMemoryInDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableFlashMemoryInDozeMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SIM_FCFG1_REG(PeripheralBase) |= \ + SIM_FCFG1_FLASHDOZE_MASK) : ( \ + SIM_FCFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SIM_FCFG1_FLASHDOZE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFlashMemoryAccess + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the flash memory access. When flash accesses are + * disabled, the flash memory is placed in a low power state. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of flash memory access. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_FCFG1. + * @par Example: + * @code + * SIM_PDD_EnableFlashMemoryAccess(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SIM_PDD_EnableFlashMemoryAccess(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SIM_FCFG1_REG(PeripheralBase) |= \ + SIM_FCFG1_FLASHDIS_MASK) : ( \ + SIM_FCFG1_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SIM_FCFG1_FLASHDIS_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFirstInvalidAddressValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the first invalid address value of program flash. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_FCFG2. + * @par Example: + * @code + * uint32 result = + * SIM_PDD_GetFirstInvalidAddressValue(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_GetFirstInvalidAddressValue(PeripheralBase) ( \ + (uint32)((uint32)(SIM_FCFG2_REG(PeripheralBase) & SIM_FCFG2_MAXADDR_MASK) << 13U) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectWatchdogClocktSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the clock source of the watchdog. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source Watchdog clock source parameter. The user should use one from + * the enumerated values. This parameter is of "Watchdog clock source + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * SIM_PDD_SelectWatchdogClocktSource(_BASE_PTR, + * SIM_PDD_WDOG_INTERNAL_1KHZ); + * @endcode + */ +#define SIM_PDD_SelectWatchdogClocktSource(PeripheralBase, Source) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SIM_WDOGCTRL_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SIM_WDOGCTRL_WDOGCLKS_MASK)))) | ( \ + (uint32)(Source))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadWatchdogControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads watchdog control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * uint32 result = SIM_PDD_ReadWatchdogControlReg(_BASE_PTR); + * @endcode + */ +#define SIM_PDD_ReadWatchdogControlReg(PeripheralBase) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWatchdogControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into watchdog + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the watchdog control register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SIM_WDOGCTRL. + * @par Example: + * @code + * SIM_PDD_WriteWatchdogControlReg(_BASE_PTR, 1); + * @endcode + */ +#define SIM_PDD_WriteWatchdogControlReg(PeripheralBase, Value) ( \ + SIM_WDOGCTRL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(SIM_PDD_H_) */ + +/* SIM_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h new file mode 100644 index 0000000..a8870d8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SPI_PDD.h @@ -0,0 +1,3857 @@ +/* + PDD layer implementation for peripheral type SPI + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SPI_PDD_H_) +#define SPI_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SPI PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK10D5) /* SPI0 */ && \ + !defined(MCU_MK10D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK10F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK10DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK11D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK11D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MK12D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK20D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK20D5) /* SPI0 */ && \ + !defined(MCU_MK20D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK20F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK20DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK21D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK21D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MK21F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK21F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK22D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F12810) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK22F25612) /* SPI0, SPI1 */ && \ + !defined(MCU_MK22F51212) /* SPI0, SPI1 */ && \ + !defined(MCU_MK24F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK30D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK30D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK30DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK40DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK40X256VMD100) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK50D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK50D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK50DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK51D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK51D7) /* SPI0, SPI1 */ && \ + !defined(MCU_MK51DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK52D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK52DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK53D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK53DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60D10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60DZ10) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK60N512VMD100) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK61F15WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK63F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK63F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK64F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK65F18) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK65F18WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK66F18) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F12) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F15) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F12WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MK70F15WS) /* SPI0, SPI1, SPI2 */ && \ + !defined(MCU_MKE02Z2) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE02Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_SKEAZN642) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE04Z1284) /* SPI0, SPI1 */ && \ + !defined(MCU_MKE04Z4) /* SPI0 */ && \ + !defined(MCU_SKEAZN84) /* SPI0 */ && \ + !defined(MCU_MKE06Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL02Z4) /* SPI0 */ && \ + !defined(MCU_MKL03Z4) /* SPI0 */ && \ + !defined(MCU_MKL04Z4) /* SPI0 */ && \ + !defined(MCU_MKL05Z4) /* SPI0 */ && \ + !defined(MCU_MKL14Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL15Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL16Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL24Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL25Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL26Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL34Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL36Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKL46Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV10Z7) /* SPI0 */ && \ + !defined(MCU_MKV31F12810) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV31F25612) /* SPI0, SPI1 */ && \ + !defined(MCU_MKV31F51212) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW01Z4) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW21D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW21D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW22D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW22D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW24D5) /* SPI0, SPI1 */ && \ + !defined(MCU_MKW24D5WS) /* SPI0, SPI1 */ && \ + !defined(MCU_PCK20L4) /* SPI0 */ && \ + !defined(MCU_SKEAZ1284) /* SPI0, SPI1 */ + // Unsupported MCU is active + #error SPI PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Chip select masks. */ +#define SPI_PDD_CHIP_SELECT_0 0x1U /**< Chip select 0 mask. */ +#define SPI_PDD_CHIP_SELECT_1 0x2U /**< Chip select 1 mask. */ +#define SPI_PDD_CHIP_SELECT_2 0x4U /**< Chip select 2 mask. */ +#define SPI_PDD_CHIP_SELECT_3 0x8U /**< Chip select 3 mask. */ +#define SPI_PDD_CHIP_SELECT_4 0x10U /**< Chip select 4 mask. */ + +/* Interrupt/DMA masks */ +#define SPI_PDD_TRANSFER_COMPLETE_INT SPI_SR_TCF_MASK /**< Transfer complete interrupt mask. */ +#define SPI_PDD_QUEUE_FINISHED_INT SPI_SR_EOQF_MASK /**< Queue finished interrupt mask. */ +#define SPI_PDD_TX_FIFO_UNDERFLOW_INT SPI_SR_TFUF_MASK /**< Transmit FIFO underflow interrupt mask. */ +#define SPI_PDD_TX_FIFO_FILL_INT_DMA SPI_SR_TFFF_MASK /**< Transmit FIFO fill interrupt mask. */ +#define SPI_PDD_RX_FIFO_OVERFLOW_INT SPI_SR_RFOF_MASK /**< Receive FIFO overflow interrupt mask. */ +#define SPI_PDD_RX_FIFO_DRAIN_INT_DMA SPI_SR_RFDF_MASK /**< Receive FIFO drain interrupt mask. */ +#define SPI_PDD_ALL_INT 0x9A0A0000U /**< All interrupt masks. */ + +/* Request mask for DMA or interrupt selection */ +#define SPI_PDD_NO_DMA 0U /**< None DMA or interrupt request selection. */ +#define SPI_PDD_TX_FIFO_FILL_DMA SPI_RSER_TFFF_DIRS_MASK /**< Transmit FIFO fill DMA or interrupt request select. */ +#define SPI_PDD_RX_FIFO_DRAIN_DMA SPI_RSER_RFDF_DIRS_MASK /**< Receive FIFO drain DMA or interrupt request select. */ + +/* Rx buffer full (or fault) and Tx buffer empty interrupt masks constant. */ +#define SPI_PDD_RX_BUFFER_FULL_OR_FAULT SPI_C1_SPIE_MASK /**< Receiver buffer full and mode fault mask. */ +#define SPI_PDD_TX_BUFFER_EMPTY SPI_C1_SPTIE_MASK /**< Transmitter buffer empty mask. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_RX_BUFFER_FULL SPI_S_SPRF_MASK /**< Read buffer or FIFO full flag. */ +#define SPI_PDD_MATCH SPI_S_SPMF_MASK /**< SPI match flag. */ +#define SPI_PDD_TX_BUFFER_EMPTYG SPI_S_SPTEF_MASK /**< Transmit buffer or FIFO empty flag. */ +#define SPI_PDD_MASTER_FAULT SPI_S_MODF_MASK /**< Master mode fault flag. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_RX_FIFO_NEARLY_FULL SPI_S_RNFULLF_MASK /**< Receive FIFO nearly full flag. */ +#define SPI_PDD_TX_FIFO_NEARLY_EMPTY SPI_S_TNEAREF_MASK /**< Transmit FIFO nearly empty flag. */ +#define SPI_PDD_TX_BUFFER_FULL SPI_S_TXFULLF_MASK /**< Transmit FIFO full flag. */ +#define SPI_PDD_READ_FIFO_EMPTY SPI_S_RFIFOEF_MASK /**< SPI read FIFO empty flag. */ + +/* FIFO interrupt masks */ +#define SPI_PDD_TRANSMIT_FIFO_EMPTY SPI_C3_TNEARIEN_MASK /**< Transmit FIFO nearly empty mask. */ +#define SPI_PDD_RECEIVE_FIFO_FULL SPI_C3_RNFULLIEN_MASK /**< Receive FIFO nearly full mask. */ +#define SPI_PDD_TRANSMIT_RECEIVE_FIFO 0x6U /**< Receive FIFO nearly full 'or' transmit FIFO nearly empty masks. */ + +/* Status flags constants (for ReadStatusReg, GetInterruptFlags, + ClearInterruptFlags macros). */ +#define SPI_PDD_TX_FIFO_ERROR SPI_CI_TXFERR_MASK /**< Transmit FIFO error flag. */ +#define SPI_PDD_RX_FIFO_ERROR SPI_CI_RXFERR_MASK /**< Receive FIFO error flag. */ +#define SPI_PDD_TX_FIFO_OVERFLOW SPI_CI_TXFOF_MASK /**< Transmit FIFO overflow flag. */ +#define SPI_PDD_RX_FIFO_OVERFLOW SPI_CI_RXFOF_MASK /**< Receive FIFO overflow flag. */ + +/* FIFO interrupt masks */ +#define SPI_PDD_TX_FIFO_NEARLY_EMPTY_FLAG SPI_CI_TNEAREFCI_MASK /**< Transmit FIFO nearly empty flag mask. */ +#define SPI_PDD_RX_FIFO_NEARLY_FULL_FLAG SPI_CI_RNFULLFCI_MASK /**< Receive FIFO nearly full flag mask. */ +#define SPI_PDD_TX_FIFO_EMPTY_FLAG SPI_CI_SPTEFCI_MASK /**< Transmit FIFO empty flag mask. */ +#define SPI_PDD_RX_FIFO_FULL_FLAG SPI_CI_SPRFCI_MASK /**< Receive FIFO full flag mask. */ +#define SPI_PDD_CLEAR_ALL_FIFO_FLAGS 0xFU /**< All FIFO flags masks. */ + +/* SPI mode constants (for SetMasterSlaveMode). */ +#define SPI_PDD_MASTER_MODE 0x1U /**< Master mode. */ +#define SPI_PDD_SLAVE_MODE 0U /**< Slave mode. */ + +/* SPI clock polarity constants. */ +#define SPI_PDD_SPI_MODE 0U /**< SPI mode. */ + +/* SPI clock polarity constants. */ +#define SPI_PDD_SPI_PDD_0_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0U /**< 0 system clock between SCK edge and SIN sample. */ +#define SPI_PDD_SPI_PDD_1_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0x100U /**< 1 system clock between SCK edge and SIN sample. */ +#define SPI_PDD_SPI_PDD_2_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE 0x200U /**< 2 system clocks between SCK edge and SIN sample. */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI data shift order constants (for SetDataShiftOrder macro). */ + #define SPI_PDD_LSB_FIRST 0x1U /**< Data transfers start with least significant bit. */ + #define SPI_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI data shift order constants */ + #define SPI_PDD_LSB_FIRST 0x1000000U /**< Data transfers start with least significant bit */ + #define SPI_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* PCS to SCK delay prescaler constants (for SetPcsToSckDelayPrescaler macro). */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_1 0U /**< PCS to SCK Prescaler value is 1. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_3 0x1U /**< PCS to SCK Prescaler value is 3. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_5 0x2U /**< PCS to SCK Prescaler value is 5. */ +#define SPI_PDD_PCS_TO_SCK_PRESCALER_7 0x3U /**< PCS to SCK Prescaler value is 7. */ + +/* PCS to SCK delay prescaler constants (for SetDelayAfterTransferPrescaler, + SetAfterSckDelayPrescaler macros). */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_1 0U /**< Delay after Transfer Prescaler value is 1. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_3 0x1U /**< Delay after Transfer Prescaler value is 3. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_5 0x2U /**< Delay after Transfer Prescaler value is 5. */ +#define SPI_PDD_DELAY_AFTER_TRANSFER_PRESCALER_7 0x3U /**< Delay after Transfer Prescaler value is 7. */ + +/* Baud rate prescaler constats (for SetBaudRatePrescaler macro). */ +#define SPI_PDD_BAUD_RATE_PRESCALER_2 0U /**< Baud rate prescaler value is 2. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_3 0x1U /**< Baud rate prescaler value is 3. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_5 0x2U /**< Baud rate prescaler value is 5. */ +#define SPI_PDD_BAUD_RATE_PRESCALER_7 0x3U /**< Baud rate prescaler value is 7. */ + +/* PCS to SCK delay scaler constants (for SetPcsToSckDelayScaler, + SetAfterSckDelayScaler, SetDelayAfterTransferScaler macros). */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_2 0U /**< PCS to SCK delay scaler value is 2. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_4 0x1U /**< PCS to SCK delay scaler value is 4. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_8 0x2U /**< PCS to SCK delay scaler value is 8. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_16 0x3U /**< PCS to SCK delay scaler value is 16. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_32 0x4U /**< PCS to SCK delay scaler value is 32. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_64 0x5U /**< PCS to SCK delay scaler value is 64. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_128 0x6U /**< PCS to SCK delay scaler value is 128. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_256 0x7U /**< PCS to SCK delay scaler value is 256. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_512 0x8U /**< PCS to SCK delay scaler value is 512. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_1024 0x9U /**< PCS to SCK delay scaler value is 1024. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_2048 0xAU /**< PCS to SCK delay scaler value is 2048. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_4096 0xBU /**< PCS to SCK delay scaler value is 4096. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_8192 0xCU /**< PCS to SCK delay scaler value is 8192. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_16384 0xDU /**< PCS to SCK delay scaler value is 16384. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_32768 0xEU /**< PCS to SCK delay scaler value is 32768. */ +#define SPI_PDD_PCS_TO_SCK_DELAY_SCALER_65535 0xFU /**< PCS to SCK delay scaler value is 65535. */ + +/* Baud rate scaler constants (for SetBaudRateScaler macro). */ +#define SPI_PDD_BAUD_RATE_SCALER_2 0U /**< Baud rate scaler value is 2. */ +#define SPI_PDD_BAUD_RATE_SCALER_4 0x1U /**< Baud rate scaler value is 4. */ +#define SPI_PDD_BAUD_RATE_SCALER_6 0x2U /**< Baud rate scaler value is 6. */ +#define SPI_PDD_BAUD_RATE_SCALER_8 0x3U /**< Baud rate scaler value is 8. */ +#define SPI_PDD_BAUD_RATE_SCALER_16 0x4U /**< Baud rate scaler value is 16. */ +#define SPI_PDD_BAUD_RATE_SCALER_32 0x5U /**< Baud rate scaler value is 32. */ +#define SPI_PDD_BAUD_RATE_SCALER_64 0x6U /**< Baud rate scaler value is 64. */ +#define SPI_PDD_BAUD_RATE_SCALER_128 0x7U /**< Baud rate scaler value is 128. */ +#define SPI_PDD_BAUD_RATE_SCALER_256 0x8U /**< Baud rate scaler value is 256. */ +#define SPI_PDD_BAUD_RATE_SCALER_512 0x9U /**< Baud rate scaler value is 512. */ +#define SPI_PDD_BAUD_RATE_SCALER_1024 0xAU /**< Baud rate scaler value is 1024. */ +#define SPI_PDD_BAUD_RATE_SCALER_2048 0xBU /**< Baud rate scaler value is 2048. */ +#define SPI_PDD_BAUD_RATE_SCALER_4096 0xCU /**< Baud rate scaler value is 4096. */ +#define SPI_PDD_BAUD_RATE_SCALER_8192 0xDU /**< Baud rate scaler value is 8192. */ +#define SPI_PDD_BAUD_RATE_SCALER_16384 0xEU /**< Baud rate scaler value is 16384. */ +#define SPI_PDD_BAUD_RATE_SCALER_32768 0xFU /**< Baud rate scaler value is 32768. */ + +/* SPI transaction data size constants. */ +#define SPI_PDD_4_BITS 0x18000000U /**< 4-bits transaction data size */ +#define SPI_PDD_5_BITS 0x20000000U /**< 5-bits transaction data size */ +#define SPI_PDD_6_BITS 0x28000000U /**< 6-bits transaction data size */ +#define SPI_PDD_7_BITS 0x30000000U /**< 7-bits transaction data size */ +#define SPI_PDD_8_BITS 0x38000000U /**< 8-bits transaction data size */ +#define SPI_PDD_9_BITS 0x40000000U /**< 9-bits transaction data size */ +#define SPI_PDD_10_BITS 0x48000000U /**< 10-bits transaction data size */ +#define SPI_PDD_11_BITS 0x50000000U /**< 11-bits transaction data size */ +#define SPI_PDD_12_BITS 0x58000000U /**< 12-bits transaction data size */ +#define SPI_PDD_13_BITS 0x60000000U /**< 13-bits transaction data size */ +#define SPI_PDD_14_BITS 0x68000000U /**< 14-bits transaction data size */ +#define SPI_PDD_15_BITS 0x70000000U /**< 15-bits transaction data size */ +#define SPI_PDD_16_BITS 0x78000000U /**< 16-bits transaction data size */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI clock polarity constants (for SetClockPolarity macro). */ + #define SPI_PDD_ACTIVE_HIGH 0U /**< Active-high SPI clock (idles low). */ + #define SPI_PDD_ACTIVE_LOW 0x8U /**< Active-low SPI clock (idles high). */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI clock polarity constants. */ + #define SPI_PDD_ACTIVE_HIGH 0x4000000U /**< Active-high SPI clock (idles low, rising edge of SPI clock starts transaction) */ + #define SPI_PDD_ACTIVE_LOW 0U /**< Active-low SPI clock (idles high, falling edge of SPI clock starts transaction) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* SPI clock phase constants (for SetClockPhase macro). */ + #define SPI_PDD_FIRST_EDGE 0U /**< First edge on SPSCK occurs at the middle of the first cycle of a data transfer. */ + #define SPI_PDD_SECOND_EDGE 0x4U /**< First edge on SPSCK occurs at the start of the first cycle of a data transfer. */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI clock phase constants. */ + #define SPI_PDD_FIRST_EDGE 0U /**< First edge on SCK occurs at the middle of the first cycle of a data transfer */ + #define SPI_PDD_SECOND_EDGE 0x2000000U /**< First edge on SCK occurs at the start of the first cycle of a data transfer */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* SPI slave select pin function constants (for SetSlaveSelectPinFunction + macro). */ +#define SPI_PDD_SS_AS_GPIO 0U /**< Slave select pin configured as GPIO. */ +#define SPI_PDD_SS_FOR_FAULT_DETECT 0x1U /**< Slave select pin configured for fault detection. */ +#define SPI_PDD_SS_AUTOMATIC_OUTPUT 0x2U /**< Slave select pin configured for automatic SPI output. */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/* SPI data length constants (for SetWordLength, GetWordLength macro). */ + #define SPI_PDD_8_BIT 0U /**< 8-bit SPI shift register, match register and buffers. */ + #define SPI_PDD_16_BIT 0x40U /**< 16-bit SPI shift register, match register and buffers. */ + +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* SPI data length constants (for SetWordLength, GetWordLength macro). */ + #define SPI_PDD_8_BIT 0U /**< 8-bit SPI shift register, match register and buffers. */ + #define SPI_PDD_16_BIT 0x1U /**< 16-bit SPI shift register, match register and buffers. */ + +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/* Transmit FIFO nearly empty watermark constants (for SetTxFifoEmptyWatermark + macro). */ +#define SPI_PDD_16_BITS_OR_LESS 0U /**< 16 bits or less. */ +#define SPI_PDD_32_BITS_OR_LESS 0x20U /**< 32 bits or less. */ + +/* Receive FIFO nearly full watermark constants (for SetRxFifoFullWatermark + macro). */ +#define SPI_PDD_32_BITS_OR_MORE 0x10U /**< 32 bits or more. */ +#define SPI_PDD_48_BITS_OR_MORE 0U /**< 48 bits or more. */ + + +/* ---------------------------------------------------------------------------- + -- SetMasterSlaveMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Select master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode SPI mode value. The user should use one from the enumerated + * values. This parameter is of "SPI mode constants (for SetMasterSlaveMode)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMasterSlaveMode(_BASE_PTR, SPI_PDD_MASTER_MODE); + * @endcode + */ + #define SPI_PDD_SetMasterSlaveMode(PeripheralBase, Mode) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_MSTR_MASK))) | ( \ + (uint8)((uint8)(Mode) << SPI_C1_MSTR_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Select master or slave mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Device mode. This parameter is of "SPI mode constants (for + * SetMasterSlaveMode)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMasterSlaveMode(_BASE_PTR, SPI_PDD_MASTER_MODE); + * @endcode + */ + #define SPI_PDD_SetMasterSlaveMode(PeripheralBase, Mode) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_MSTR_MASK))) | ( \ + (uint32)((uint32)(Mode) << SPI_MCR_MSTR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableContinuousClock + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables continuous clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of continuous clock. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableContinuousClock(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableContinuousClock(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_CONT_SCKE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_CONT_SCKE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectModuleConfiguration + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects among the different configurations of the module. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Configuration SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectModuleConfiguration(_BASE_PTR, + * SPI_PDD_SPI_MODE); + * @endcode + */ +#define SPI_PDD_SelectModuleConfiguration(PeripheralBase, Configuration) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_DCONF_MASK))) | ( \ + (uint32)((uint32)(Configuration) << SPI_MCR_DCONF_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransfersInDebugMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables serial transfers in debug mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state in debug mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTransfersInDebugMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTransfersInDebugMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_FRZ_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_FRZ_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableModifiedTransferFormat + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables modified SPI transfer format. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state of modified SPI transfer format. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableModifiedTransferFormat(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableModifiedTransferFormat(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_MTFE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_MTFE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFifoOverflowOverwrite + ---------------------------------------------------------------------------- */ + +/** + * @brief Configures SPI module to ignore the incoming serial data or overwrite + * existing data if the receive FIFO is full and new data is received. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state of receive FIFO. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableRxFifoOverflowOverwrite(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableRxFifoOverflowOverwrite(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_ROOE_MASK))) | ( \ + (uint32)((uint32)(State) << SPI_MCR_ROOE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetChipSelectInactiveStateMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS))) +/** + * @brief Determines the inactive state of PCSx specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighMask Chip selects mask defining which inactive state of PCSx is + * high. Use constants from group "Chip select masks.". This parameter is 5 + * bits wide. + * @param LowMask Chip selects mask defining which inactive state of PCSx is + * low. Use constants from group "Chip select masks.". This parameter is 5 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetChipSelectInactiveStateMask(_BASE_PTR, + * SPI_PDD_CHIP_SELECT_0, SPI_PDD_CHIP_SELECT_0); + * @endcode + */ + #define SPI_PDD_SetChipSelectInactiveStateMask(PeripheralBase, HighMask, LowMask) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_MCR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)(LowMask) << SPI_MCR_PCSIS_SHIFT))))) | ( \ + (uint32)((uint32)(HighMask) << SPI_MCR_PCSIS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Determines the inactive state of PCSx specified by mask parameters. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param HighMask Chip selects mask defining which inactive state of PCSx is + * high. Use constants from group "Chip select masks.". This parameter is 6 + * bits wide. + * @param LowMask Chip selects mask defining which inactive state of PCSx is + * low. Use constants from group "Chip select masks.". This parameter is 6 + * bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetChipSelectInactiveStateMask(_BASE_PTR, + * SPI_PDD_CHIP_SELECT_0, SPI_PDD_CHIP_SELECT_0); + * @endcode + */ + #define SPI_PDD_SetChipSelectInactiveStateMask(PeripheralBase, HighMask, LowMask) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_MCR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)((uint32)(LowMask) << SPI_MCR_PCSIS_SHIFT))))) | ( \ + (uint32)((uint32)(HighMask) << SPI_MCR_PCSIS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableModuleInDozeMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SPI device operation in doze mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State State Requested state in doze mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableModuleInDozeMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableModuleInDozeMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DOZE_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DOZE_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables/disables SPI device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define SPI_PDD_EnableDevice(PeripheralBase, State) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_SPE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C1_SPE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE and + * PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR, SPI0_C1, SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define SPI_PDD_EnableDevice(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_MDIS_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_MDIS_MASK)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables transmit FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit FIFO. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTxFIFO(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DIS_TXF_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DIS_TXF_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables receive FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive FIFO. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableRxFIFO(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableRxFIFO(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_DIS_RXF_MASK) : ( \ + SPI_MCR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SPI_MCR_DIS_RXF_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Tx FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearTxFIFO(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearTxFIFO(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_CLR_TXF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearRxFIFO + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Rx FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearRxFIFO(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearRxFIFO(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) |= \ + SPI_MCR_CLR_RXF_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectSamplePoint + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the sample point. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Configuration SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectSamplePoint(_BASE_PTR, + * SPI_PDD_SPI_PDD_0_SYSTEM_CLK_BETWEEN_SCK_AND_SIN_SAMPLE); + * @endcode + */ +#define SPI_PDD_SelectSamplePoint(PeripheralBase, Configuration) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_SMPL_PT_MASK))) | ( \ + (uint32)(Configuration))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHaltMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables halt mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of halt mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableHaltMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableHaltMode(PeripheralBase, State) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_MCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_MCR_HALT_MASK))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModuleConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Module configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the module configuration register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteModuleConfigurationReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteModuleConfigurationReg(PeripheralBase, Value) ( \ + SPI_MCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModuleConfigurationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Module configuration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_MCR, SPI1_MCR, + * SPI2_MCR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadModuleConfigurationReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadModuleConfigurationReg(PeripheralBase) ( \ + SPI_MCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransferCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets transfer counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Parameter specifying new value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetTransferCounter(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetTransferCounter(PeripheralBase, Value) ( \ + SPI_TCR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_TCR_REG(PeripheralBase) & (uint32)(~(uint32)SPI_TCR_SPI_TCNT_MASK))) | ( \ + (uint32)((uint32)(Value) << SPI_TCR_SPI_TCNT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransferCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns transfer counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTransferCounter(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTransferCounter(PeripheralBase) ( \ + (uint16)(( \ + (uint32)(SPI_TCR_REG(PeripheralBase) & SPI_TCR_SPI_TCNT_MASK)) >> ( \ + SPI_TCR_SPI_TCNT_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransferCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Transfer count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the transfer count register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteTransferCountReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteTransferCountReg(PeripheralBase, Value) ( \ + SPI_TCR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransferCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Transfer count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_TCR, SPI1_TCR, + * SPI2_TCR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadTransferCountReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadTransferCountReg(PeripheralBase) ( \ + SPI_TCR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDoubleBaudRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables or disables SCK double baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param State Requested state of SCK double baud rate. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_EnableDoubleBaudRate(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableDoubleBaudRate(PeripheralBase, Index, State) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_DBR_MASK)))) | ( \ + (uint32)((uint32)(State) << SPI_CTAR_DBR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataShiftOrder + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order SPI data shift order value. The user should use one from the + * enumerated values. This parameter is of "SPI data shift order constants + * (for SetDataShiftOrder macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataShiftOrder(_BASE_PTR, SPI_PDD_LSB_FIRST); + * @endcode + */ + #define SPI_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_LSBFE_MASK))) | ( \ + (uint8)(Order))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Order SPI data shift order value. The user should use one from the + * enumerated values. This parameter is of "SPI data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataShiftOrder(_BASE_PTR, periphID, + * SPI_PDD_LSB_FIRST); + * @endcode + */ + #define SPI_PDD_SetDataShiftOrder(PeripheralBase, Index, Order) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_LSBFE_MASK)))) | ( \ + (uint32)(Order))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPcsToSckDelayPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets PCS to SCK delay prescaler value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK Delay Ppescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetPcsToSckDelayPrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetPcsToSckDelayPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PCSSCK_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PCSSCK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAfterSckDelayPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler value for the delay between the last edge of SCK + * and the negation of PCS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK Delay prescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetAfterSckDelayPrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetAfterSckDelayPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PASC_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PASC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDelayAfterTransferPrescaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the prescaler value for the delay between the negation of the PCS + * signal at the end of a frame and the assertion of PCS at the beginning of the + * next frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Delay after Transfer prescaler value[0..3]. This parameter is a + * 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetDelayAfterTransferPrescaler(_BASE_PTR, periphID, + * 1); + * @endcode + */ +#define SPI_PDD_SetDelayAfterTransferPrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PDT_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PDT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRatePrescaler + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI baud rate prescale divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler Baud rate prescale divisor value[0..7]. This parameter is a + * 3-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_BR, + * SPI1_BR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRatePrescaler(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetBaudRatePrescaler(PeripheralBase, Prescaler) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_BR_REG(PeripheralBase) & (uint8)(~(uint8)SPI_BR_SPPR_MASK))) | ( \ + (uint8)((uint8)(Prescaler) << SPI_BR_SPPR_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the prescaler value for the baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Baud rate prescaler value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_BR, + * SPI1_BR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRatePrescaler(_BASE_PTR, periphID, 1); + * @endcode + */ + #define SPI_PDD_SetBaudRatePrescaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PBR_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PBR_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetPcsToSckDelayScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the PCS to SCK delay scaler value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value PCS to SCK delay scaler value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetPcsToSckDelayScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetPcsToSckDelayScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CSSCK_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_CSSCK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetAfterSckDelayScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the scaler value for the after SCK delay. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Scaler value for the after SCK delay value[0..15]. This + * parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetAfterSckDelayScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetAfterSckDelayScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_ASC_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_ASC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDelayAfterTransferScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects the delay after transfer scaler. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Delay after transfer scaler value[0..15]. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetDelayAfterTransferScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetDelayAfterTransferScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(SPI_CTAR_REG(PeripheralBase,(Index)) & (uint32)(~(uint32)SPI_CTAR_DT_MASK))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_DT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateScaler + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the scaler value for the baud rate. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Baud rate prescaler value[0..3]. This parameter is a 2-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_SetBaudRateScaler(_BASE_PTR, periphID, 1); + * @endcode + */ +#define SPI_PDD_SetBaudRateScaler(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_PBR_MASK)))) | ( \ + (uint32)((uint32)(Value) << SPI_CTAR_PBR_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMasterClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for master mode to the Clock transfer attribute + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Value stored to the master clock transfer attribute register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * SPI_PDD_WriteMasterClockTransferAttributeReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define SPI_PDD_WriteMasterClockTransferAttributeReg(PeripheralBase, Index, Value) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMasterClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Clock transfer attribute register for + * master mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CTAR[Index]. + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadMasterClockTransferAttributeReg(_BASE_PTR, periphID); + * @endcode + */ +#define SPI_PDD_ReadMasterClockTransferAttributeReg(PeripheralBase, Index) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for slave mode to the Clock transfer attribute + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Value Value stored to the slave clock transfer attribute register. + * This parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR_SLAVE[Index]. + * @par Example: + * @code + * SPI_PDD_WriteSlaveClockTransferAttributeReg(_BASE_PTR, + * periphID, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveClockTransferAttributeReg(PeripheralBase, Index, Value) ( \ + SPI_CTAR_SLAVE_REG(PeripheralBase,(Index)) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSlaveClockTransferAttributeReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Clock transfer attribute register for slave + * mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: CTAR_SLAVE[Index]. + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadSlaveClockTransferAttributeReg(_BASE_PTR, periphID); + * @endcode + */ +#define SPI_PDD_ReadSlaveClockTransferAttributeReg(PeripheralBase, Index) ( \ + SPI_CTAR_SLAVE_REG(PeripheralBase,(Index)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetWordLength + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Sets the SPI word length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length SPI data length value. The user should use one from the + * enumerated values. This parameter is of "SPI data length constants (for + * SetWordLength, GetWordLength macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C2, + * SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetWordLength(_BASE_PTR, SPI_PDD_8_BIT); + * @endcode + */ + #define SPI_PDD_SetWordLength(PeripheralBase, Length) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_SPIMODE_MASK))) | ( \ + (uint8)(Length))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the number of bits transfered per frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Size SPI frame size value. The user should use one from the enumerated + * values. This parameter is of "SPI transaction data size constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C2, + * SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetWordLength(_BASE_PTR, periphID, SPI_PDD_4_BITS); + * @endcode + */ + #define SPI_PDD_SetWordLength(PeripheralBase, Index, Size) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_FMSZ_MASK)))) | ( \ + (uint32)(Size))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetClockPolarity + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI clock polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants (for + * SetClockPolarity macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPolarity(_BASE_PTR, SPI_PDD_ACTIVE_HIGH); + * @endcode + */ + #define SPI_PDD_SetClockPolarity(PeripheralBase, Polarity) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_CPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI clock polarity (intended for slave mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Polarity SPI polarity value. The user should use one from the + * enumerated values. This parameter is of "SPI clock polarity constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPolarity(_BASE_PTR, periphID, + * SPI_PDD_ACTIVE_HIGH); + * @endcode + */ + #define SPI_PDD_SetClockPolarity(PeripheralBase, Index, Polarity) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CPOL_MASK)))) | ( \ + (uint32)(Polarity))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetClockPhase + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the SPI clock phase. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Phase SPI phase value. The user should use one from the enumerated + * values. This parameter is of "SPI clock phase constants (for SetClockPhase + * macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPhase(_BASE_PTR, SPI_PDD_FIRST_EDGE); + * @endcode + */ + #define SPI_PDD_SetClockPhase(PeripheralBase, Phase) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C1_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C1_CPHA_MASK))) | ( \ + (uint8)(Phase))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the SPI clock phase (intended for slave mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Attribute index. This parameter is of index type. + * @param Phase SPI phase value. The user should use one from the enumerated + * values. This parameter is of "SPI clock phase constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: CTAR[Index], SPI0_C1, + * SPI1_C1 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetClockPhase(_BASE_PTR, periphID, + * SPI_PDD_FIRST_EDGE); + * @endcode + */ + #define SPI_PDD_SetClockPhase(PeripheralBase, Index, Phase) ( \ + SPI_CTAR_REG(PeripheralBase,(Index)) = \ + (uint32)(( \ + (uint32)(( \ + SPI_CTAR_REG(PeripheralBase,(Index))) & ( \ + (uint32)(~(uint32)SPI_CTAR_CPHA_MASK)))) | ( \ + (uint32)(Phase))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flags. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Interrupt/DMA masks" for processing return + * value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetInterruptFlags(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetInterruptFlags(PeripheralBase) ( \ + (uint32)(( \ + SPI_SR_REG(PeripheralBase)) & ( \ + (uint32)(( \ + SPI_SR_TCF_MASK) | (( \ + SPI_SR_EOQF_MASK) | (( \ + SPI_SR_TFUF_MASK) | (( \ + SPI_SR_TFFF_MASK) | (( \ + SPI_SR_RFOF_MASK) | ( \ + SPI_SR_RFDF_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag bits defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt flags to clear. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearInterruptFlags(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxRxActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns Tx/Rx active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetTxRxActiveFlag(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTxRxActiveFlag(PeripheralBase) ( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXRXS_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxRxActiveFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears Tx/Rx active flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_ClearTxRxActiveFlag(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ClearTxRxActiveFlag(PeripheralBase) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) | SPI_SR_TXRXS_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_RFDF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_RFOF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_TFFF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_TFUF_MASK)) & (( \ + (uint32)(~(uint32)SPI_SR_EOQF_MASK)) & ( \ + (uint32)(~(uint32)SPI_SR_TCF_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOCounter + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns transmit FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetTxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint16)(( \ + (uint16)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_TXCTR4_MASK)) >> ( \ + SPI_SREX_TXCTR4_SHIFT))) << ( \ + 4U))) | ( \ + (uint16)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXCTR_MASK)) >> ( \ + SPI_SR_TXCTR_SHIFT)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns transmit FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetTxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXCTR_MASK)) >> ( \ + SPI_SR_TXCTR_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOCounter + ---------------------------------------------------------------------------- */ + +#if (defined(MCU_MKV10Z7)) +/** + * @brief Returns receive FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetRxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint16)(( \ + (uint16)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_RXCTR4_MASK)) >> ( \ + SPI_SREX_RXCTR4_SHIFT))) << ( \ + 4U))) | ( \ + (uint16)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_RXCTR_MASK)) >> ( \ + SPI_SR_RXCTR_SHIFT)))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns receive FIFO counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_SREX (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxFIFOCounter(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_GetRxFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_RXCTR_MASK)) >> ( \ + SPI_SR_RXCTR_SHIFT)) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetTxNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns pointer to TX FIFO entry which is transmitted during the next + * transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetTxNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetTxNextPointer(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SR_REG(PeripheralBase) & SPI_SR_TXNXTPTR_MASK)) >> ( \ + SPI_SR_TXNXTPTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns pointer to RX FIFO entry which is transmitted during the next + * transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetRxNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetRxNextPointer(PeripheralBase) ( \ + (uint8)(SPI_SR_REG(PeripheralBase) & SPI_SR_POPNXTPTR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the status register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteStatusReg(PeripheralBase, Value) ( \ + SPI_SR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_S, SPI1_S (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadStatusReg(PeripheralBase) ( \ + SPI_S_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SR, SPI1_SR, + * SPI2_SR, SPI0_S, SPI1_S (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadStatusReg(PeripheralBase) ( \ + SPI_SR_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables DMA/interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableDmasInterrupts(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_EnableDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) |= \ + (uint32)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables DMA/interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group + * "Interrupt/DMA masks". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableDmasInterrupts(_BASE_PTR, + * SPI_PDD_TRANSFER_COMPLETE_INT); + * @endcode + */ +#define SPI_PDD_DisableDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) &= \ + (uint32)(~(uint32)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectDmasInterrupts + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects DMA or interrupt for request defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of DMA/interrupt requests. Use constants from group "Request + * mask for DMA or interrupt selection". This parameter is 32 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SelectDmasInterrupts(_BASE_PTR, SPI_PDD_NO_DMA); + * @endcode + */ +#define SPI_PDD_SelectDmasInterrupts(PeripheralBase, Mask) ( \ + SPI_RSER_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SPI_RSER_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)(SPI_RSER_TFFF_DIRS_MASK | SPI_RSER_RFDF_DIRS_MASK))))) | ( \ + (uint32)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDmaInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the DMA interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the DMA interrupt enable register. This + * parameter is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDmaInterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteDmaInterruptEnableReg(PeripheralBase, Value) ( \ + SPI_RSER_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDmaInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the DMA interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RSER, SPI1_RSER, + * SPI2_RSER (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * SPI_PDD_ReadDmaInterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadDmaInterruptEnableReg(PeripheralBase) ( \ + SPI_RSER_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMasterPushTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for master mode to the Push TX FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the master push Tx FIFO register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMasterPushTxFIFOReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteMasterPushTxFIFOReg(PeripheralBase, Value) ( \ + SPI_PUSHR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveData8Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 8 bits data value intended for slave mode to the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bits data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlaveData8Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveData8Bits(PeripheralBase, Data) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlaveData16Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bits data value intended for slave mode to the data + * registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bits data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlaveData16Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlaveData16Bits(PeripheralBase, Data) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteSlavePushTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value intended for slave mode to the Push TX FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the slave push Tx FIFO register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR_SLAVE, + * SPI1_PUSHR_SLAVE, SPI2_PUSHR_SLAVE (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteSlavePushTxFIFOReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteSlavePushTxFIFOReg(PeripheralBase, Value) ( \ + SPI_PUSHR_SLAVE_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData8Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 8 bits data value to the data registers (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bits data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData8Bits(PeripheralBase, Data) ( \ + *((uint16 *)&SPI_PUSHR_REG(PeripheralBase)) = (uint16)Data \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData16Bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bits data value to the data registers (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bits data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_PUSHR, SPI1_PUSHR, + * SPI2_PUSHR (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData16Bits(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData16Bits(PeripheralBase, Data) ( \ + *((uint16 *)&SPI_PUSHR_REG(PeripheralBase)) = (uint16)Data \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData8bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 8 bits value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bits(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData8bits(PeripheralBase) ( \ + (uint8)SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData16bits + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 16 bits value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_ReadData16bits(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData16bits(PeripheralBase) ( \ + (uint16)SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPopRxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Pop Rx FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_POPR, SPI1_POPR, + * SPI2_POPR (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadPopRxFIFOReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadPopRxFIFOReg(PeripheralBase) ( \ + SPI_POPR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOCommand + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the transfer attributes for the SPI data (intended for master + * mode). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTxFIFOCommand(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetTxFIFOCommand(PeripheralBase, Index) ( \ + (uint16)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index] >> 16) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFIFOData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns he SPI data to be shifted out. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_GetTxFIFOData(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetTxFIFOData(PeripheralBase, Index) ( \ + (uint16)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the transmit FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Transmit FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_TXFR0, SPI1_TXFR0, + * SPI2_TXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadTxFIFOReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_ReadTxFIFOReg(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_TXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFIFOData + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Receive FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RXFR0, SPI1_RXFR0, + * SPI2_RXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_GetRxFIFOData(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_GetRxFIFOData(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_RXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFIFOReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the receive FIFO register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Index Receive FIFO register index. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_RXFR0, SPI1_RXFR0, + * SPI2_RXFR0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadRxFIFOReg(_BASE_PTR, + * periphID); + * @endcode + */ +#define SPI_PDD_ReadRxFIFOReg(PeripheralBase, Index) ( \ + (uint32)(((uint32 *)&SPI_RXFR0_REG(PeripheralBase))[Index]) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Rx buffer + * full (or fault) and Tx buffer empty interrupt masks constant.". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableInterruptMask(_BASE_PTR, + * SPI_PDD_RX_BUFFER_FULL_OR_FAULT); + * @endcode + */ +#define SPI_PDD_EnableInterruptMask(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. Use constants from group "Rx buffer + * full (or fault) and Tx buffer empty interrupt masks constant.". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableInterruptMask(_BASE_PTR, + * SPI_PDD_RX_BUFFER_FULL_OR_FAULT); + * @endcode + */ +#define SPI_PDD_DisableInterruptMask(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSlaveSelectPinFunction + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SPI slave select pin function. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Function Slave select pin function. The user should use one from the + * enumerated values. This parameter is of "SPI slave select pin function + * constants (for SetSlaveSelectPinFunction macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI0_C2, + * SPI1_C1, SPI1_C2 (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetSlaveSelectPinFunction(_BASE_PTR, + * SPI_PDD_SS_AS_GPIO); + * @endcode + */ +#define SPI_PDD_SetSlaveSelectPinFunction(PeripheralBase, Function) ( \ + ((Function) == SPI_PDD_SS_AS_GPIO) ? ( \ + (SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C1_SSOE_MASK)), \ + (SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_MODFEN_MASK))) : ( \ + ((Function) == SPI_PDD_SS_FOR_FAULT_DETECT) ? ( \ + (SPI_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C1_SSOE_MASK)), \ + (SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_MODFEN_MASK)) : ( \ + (SPI_C1_REG(PeripheralBase) |= \ + SPI_C1_SSOE_MASK), \ + (SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_MODFEN_MASK)) \ + ) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataFeatures + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets data transmission features(shift order, clock polarity and phase) + * defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of data features requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetDataFeatures(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetDataFeatures(PeripheralBase, Mask) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + SPI_C1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(SPI_C1_LSBFE_MASK | (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK)))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl1Reg(PeripheralBase) ( \ + SPI_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C1, SPI1_C1 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + SPI_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables receive data buffer hardware match interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableMatchInterrupt(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_EnableMatchInterrupt(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_SPMIE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableMatchInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables receive data buffer hardware match interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_DisableMatchInterrupt(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_DisableMatchInterrupt(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_SPMIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOutputInBidirectionalMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables pin direction in a bidirectional mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of output pin in bidirectional mode. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableOutputInBidirectionalMode(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableOutputInBidirectionalMode(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_BIDIROE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_BIDIROE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOperateInWaitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables operate in wait mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device in wait mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableOperateInWaitMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableOperateInWaitMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + SPI_C2_REG(PeripheralBase) |= \ + SPI_C2_SPISWAI_MASK) : ( \ + SPI_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)SPI_C2_SPISWAI_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBidirectionalMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables bidirectional mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of bidirectional mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableBidirectionalMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableBidirectionalMode(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_SPC0_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl2Reg(PeripheralBase) ( \ + SPI_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateDivisor + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the SPI baud rate divisor. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Divisor Baud rate divisor value[0..15]. This parameter is a 4-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetBaudRateDivisor(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetBaudRateDivisor(PeripheralBase, Divisor) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_BR_REG(PeripheralBase) & (uint8)(~(uint8)SPI_BR_SPR_MASK))) | ( \ + (uint8)(Divisor))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadBaudRateReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadBaudRateReg(PeripheralBase) ( \ + SPI_BR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the baud rate register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value stored to the baud rate register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_BR, SPI1_BR + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteBaudRateReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteBaudRateReg(PeripheralBase, Value) ( \ + SPI_BR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData8Bit + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes 8 bit data value to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bit data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bit(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteData8Bit(PeripheralBase, Data) ( \ + SPI_DL_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes 8 bit data value to the data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 8 bit data value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData8Bit(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteData8Bit(PeripheralBase, Data) ( \ + SPI_D_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadData8bit + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Returns the content of the 8 bit data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bit(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadData8bit(PeripheralBase) ( \ + SPI_DL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Returns the content of the 8 bit data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadData8bit(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadData8bit(PeripheralBase) ( \ + SPI_D_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadDataLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Reads data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadDataLowReg(PeripheralBase) ( \ + SPI_DL_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads data low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadDataLowReg(PeripheralBase) ( \ + SPI_D_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteDataLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes new value specified by the Value parameter into data low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteDataLowReg(PeripheralBase, Value) ( \ + SPI_DL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into data low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_D, SPI1_D, SPI0_DL, + * SPI1_DL (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteDataLowReg(PeripheralBase, Value) ( \ + SPI_D_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetMatch8BitValue + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes 8 bit match value to the match register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 8 bit match value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch8BitValue(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetMatch8BitValue(PeripheralBase, Value) ( \ + SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes 8 bit match value to the match register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 8 bit match value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch8BitValue(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_SetMatch8BitValue(PeripheralBase, Value) ( \ + SPI_M_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadMatchLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Reads match low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadMatchLowReg(PeripheralBase) ( \ + SPI_ML_REG(PeripheralBase) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Reads match low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchLowReg(_BASE_PTR); + * @endcode + */ + #define SPI_PDD_ReadMatchLowReg(PeripheralBase) ( \ + SPI_M_REG(PeripheralBase) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- WriteMatchLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL16Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Writes new value specified by the Value parameter into match low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteMatchLowReg(PeripheralBase, Value) ( \ + SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Writes new value specified by the Value parameter into match low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match low register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_M, SPI1_M, SPI0_ML, + * SPI1_ML (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchLowReg(_BASE_PTR, 1); + * @endcode + */ + #define SPI_PDD_WriteMatchLowReg(PeripheralBase, Value) ( \ + SPI_M_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_TXDMAE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_TXDMAE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + SPI_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C2_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C2_RXDMAE_MASK))) | ( \ + (uint8)((uint8)(State) << SPI_C2_RXDMAE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetWordLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the current data word length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "SPI data length constants (for SetWordLength, + * GetWordLength macro)." type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_C2, SPI1_C2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_GetWordLength(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetWordLength(PeripheralBase) ( \ + (uint8)(SPI_C2_REG(PeripheralBase) & SPI_C2_SPIMODE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteData16Bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bit data value to the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data 16 bit data value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_DL, SPI0_DH, + * SPI1_DL, SPI1_DH (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteData16Bit(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteData16Bit(PeripheralBase, Data) ( \ + (SPI_DL_REG(PeripheralBase) = \ + (uint8)(Data)), \ + (SPI_DH_REG(PeripheralBase) = \ + (uint8)((uint16)(Data) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadData16bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 16 bit value of the data registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: SPI0_DL, SPI0_DH, + * SPI1_DL, SPI1_DH (depending on the peripheral). + * @par Example: + * @code + * uint16 result = SPI_PDD_ReadData16bit(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadData16bit(PeripheralBase) ( \ + (uint16)(( \ + SPI_DL_REG(PeripheralBase)) | ( \ + (uint16)((uint16)SPI_DH_REG(PeripheralBase) << 8U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads data high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_DH, SPI1_DH + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadDataHighReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadDataHighReg(PeripheralBase) ( \ + SPI_DH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into data high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data high register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_DH, SPI1_DH + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteDataHighReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteDataHighReg(PeripheralBase, Value) ( \ + SPI_DH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatch16BitValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes 16 bit match value to the match registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value 16 bit match value. This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_ML, SPI0_MH, + * SPI1_ML, SPI1_MH (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_SetMatch16BitValue(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_SetMatch16BitValue(PeripheralBase, Value) ( \ + (SPI_ML_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (SPI_MH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI0_MH, SPI1_MH + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadMatchHighReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadMatchHighReg(PeripheralBase) ( \ + SPI_MH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into match high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match high register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI0_MH, SPI1_MH + * (depending on the peripheral). + * @par Example: + * @code + * SPI_PDD_WriteMatchHighReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteMatchHighReg(PeripheralBase, Value) ( \ + SPI_MH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxFifoEmptyWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of transmit FIFO nearly empty watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Transmit FIFO nearly empty watermark value. The user should use + * one from the enumerated values. This parameter is of "Transmit FIFO + * nearly empty watermark constants (for SetTxFifoEmptyWatermark macro)." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_SetTxFifoEmptyWatermark(_BASE_PTR, + * SPI_PDD_16_BITS_OR_LESS); + * @endcode + */ +#define SPI_PDD_SetTxFifoEmptyWatermark(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_TNEAREF_MARK_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetRxFifoFullWatermark + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of receive FIFO nearly full watermark. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Receive FIFO nearly full watermark value. The user should use + * one from the enumerated values. This parameter is of "Receive FIFO nearly + * full watermark constants (for SetRxFifoFullWatermark macro)." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_SetRxFifoFullWatermark(_BASE_PTR, + * SPI_PDD_32_BITS_OR_MORE); + * @endcode + */ +#define SPI_PDD_SetRxFifoFullWatermark(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_RNFULLF_MARK_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables FIFO interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_EnableFifoInterruptMask(_BASE_PTR, + * SPI_PDD_TRANSMIT_FIFO_EMPTY); + * @endcode + */ +#define SPI_PDD_EnableFifoInterruptMask(PeripheralBase, Mask) ( \ + SPI_C3_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables FIFO interrupt requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_DisableFifoInterruptMask(_BASE_PTR, + * SPI_PDD_TRANSMIT_FIFO_EMPTY); + * @endcode + */ +#define SPI_PDD_DisableFifoInterruptMask(PeripheralBase, Mask) ( \ + SPI_C3_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables FIFO mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of FIFO mode. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_EnableFifoMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SPI_PDD_EnableFifoMode(PeripheralBase, State) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(SPI_C3_REG(PeripheralBase) & (uint8)(~(uint8)SPI_C3_FIFOMODE_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadControl3Reg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadControl3Reg(PeripheralBase) ( \ + SPI_C3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 3 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 3 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_C3. + * @par Example: + * @code + * SPI_PDD_WriteControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteControl3Reg(PeripheralBase, Value) ( \ + SPI_C3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg, + * GetInterruptFlags, ClearInterruptFlags macros)." for processing return + * value. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadFifoStatusReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadFifoStatusReg(PeripheralBase) ( \ + SPI_CI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFifoInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears FIFO interrupt flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. Use constants from group "FIFO + * interrupt masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * SPI_PDD_ClearFifoInterruptFlag(_BASE_PTR, + * SPI_PDD_TX_FIFO_NEARLY_EMPTY_FLAG); + * @endcode + */ +#define SPI_PDD_ClearFifoInterruptFlag(PeripheralBase, Mask) ( \ + SPI_CI_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClearInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clear interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * uint8 result = SPI_PDD_ReadClearInterruptReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadClearInterruptReg(PeripheralBase) ( \ + SPI_CI_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClearInterruptReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into clear interrupt + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clear interrupt register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SPI1_CI. + * @par Example: + * @code + * SPI_PDD_WriteClearInterruptReg(_BASE_PTR, 1); + * @endcode + */ +#define SPI_PDD_WriteClearInterruptReg(PeripheralBase, Value) ( \ + SPI_CI_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandFIFOCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the number of entries in the CMD FIFO. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 5-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint8 result = SPI_PDD_GetCommandFIFOCounter(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetCommandFIFOCounter(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_CMDCTR_MASK)) >> ( \ + SPI_SREX_CMDCTR_SHIFT)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCommandNextPointer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the command next pointer - indicates which CMD FIFO Entry is + * used during the next transfer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 4-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint8 result = SPI_PDD_GetCommandNextPointer(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_GetCommandNextPointer(PeripheralBase) ( \ + (uint8)(SPI_SREX_REG(PeripheralBase) & SPI_SREX_CMDNXTPTR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExtendedStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads extended status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SPI0_SREX. + * @par Example: + * @code + * uint32 result = SPI_PDD_ReadExtendedStatusReg(_BASE_PTR); + * @endcode + */ +#define SPI_PDD_ReadExtendedStatusReg(PeripheralBase) ( \ + SPI_SREX_REG(PeripheralBase) \ + ) +#endif /* #if defined(SPI_PDD_H_) */ + +/* SPI_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h new file mode 100644 index 0000000..c02d1c2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/SysTick_PDD.h @@ -0,0 +1,539 @@ +/* + PDD layer implementation for peripheral type SysTick + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(SysTick_PDD_H_) +#define SysTick_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error SysTick PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* SysTick */ && \ + !defined(MCU_MK10D5) /* SysTick */ && \ + !defined(MCU_MK10D7) /* SysTick */ && \ + !defined(MCU_MK10F12) /* SysTick */ && \ + !defined(MCU_MK10DZ10) /* SysTick */ && \ + !defined(MCU_MK11D5) /* SysTick */ && \ + !defined(MCU_MK11D5WS) /* SysTick */ && \ + !defined(MCU_MK12D5) /* SysTick */ && \ + !defined(MCU_MK20D10) /* SysTick */ && \ + !defined(MCU_MK20D5) /* SysTick */ && \ + !defined(MCU_MK20D7) /* SysTick */ && \ + !defined(MCU_MK20F12) /* SysTick */ && \ + !defined(MCU_MK20DZ10) /* SysTick */ && \ + !defined(MCU_MK21D5) /* SysTick */ && \ + !defined(MCU_MK21D5WS) /* SysTick */ && \ + !defined(MCU_MK21F12) /* SysTick */ && \ + !defined(MCU_MK21F12WS) /* SysTick */ && \ + !defined(MCU_MK22D5) /* SysTick */ && \ + !defined(MCU_MK22F12810) /* SysTick */ && \ + !defined(MCU_MK22F12) /* SysTick */ && \ + !defined(MCU_MK22F25612) /* SysTick */ && \ + !defined(MCU_MK22F51212) /* SysTick */ && \ + !defined(MCU_MK24F12) /* SysTick */ && \ + !defined(MCU_MK30D10) /* SysTick */ && \ + !defined(MCU_MK30D7) /* SysTick */ && \ + !defined(MCU_MK30DZ10) /* SysTick */ && \ + !defined(MCU_MK40D10) /* SysTick */ && \ + !defined(MCU_MK40D7) /* SysTick */ && \ + !defined(MCU_MK40DZ10) /* SysTick */ && \ + !defined(MCU_MK40X256VMD100) /* SysTick */ && \ + !defined(MCU_MK50D10) /* SysTick */ && \ + !defined(MCU_MK50D7) /* SysTick */ && \ + !defined(MCU_MK50DZ10) /* SysTick */ && \ + !defined(MCU_MK51D10) /* SysTick */ && \ + !defined(MCU_MK51D7) /* SysTick */ && \ + !defined(MCU_MK51DZ10) /* SysTick */ && \ + !defined(MCU_MK52D10) /* SysTick */ && \ + !defined(MCU_MK52DZ10) /* SysTick */ && \ + !defined(MCU_MK53D10) /* SysTick */ && \ + !defined(MCU_MK53DZ10) /* SysTick */ && \ + !defined(MCU_MK60D10) /* SysTick */ && \ + !defined(MCU_MK60F12) /* SysTick */ && \ + !defined(MCU_MK60F15) /* SysTick */ && \ + !defined(MCU_MK60DZ10) /* SysTick */ && \ + !defined(MCU_MK60N512VMD100) /* SysTick */ && \ + !defined(MCU_MK61F12) /* SysTick */ && \ + !defined(MCU_MK61F15) /* SysTick */ && \ + !defined(MCU_MK61F12WS) /* SysTick */ && \ + !defined(MCU_MK61F15WS) /* SysTick */ && \ + !defined(MCU_MK63F12) /* SysTick */ && \ + !defined(MCU_MK63F12WS) /* SysTick */ && \ + !defined(MCU_MK64F12) /* SysTick */ && \ + !defined(MCU_MK65F18) /* SysTick */ && \ + !defined(MCU_MK65F18WS) /* SysTick */ && \ + !defined(MCU_MK66F18) /* SysTick */ && \ + !defined(MCU_MK70F12) /* SysTick */ && \ + !defined(MCU_MK70F15) /* SysTick */ && \ + !defined(MCU_MK70F12WS) /* SysTick */ && \ + !defined(MCU_MK70F15WS) /* SysTick */ && \ + !defined(MCU_MKE02Z2) /* SysTick */ && \ + !defined(MCU_MKE02Z4) /* SysTick */ && \ + !defined(MCU_SKEAZN642) /* SysTick */ && \ + !defined(MCU_MKE04Z1284) /* SysTick */ && \ + !defined(MCU_MKE04Z4) /* SysTick */ && \ + !defined(MCU_SKEAZN84) /* SysTick */ && \ + !defined(MCU_MKE06Z4) /* SysTick */ && \ + !defined(MCU_MKL02Z4) /* SysTick */ && \ + !defined(MCU_MKL03Z4) /* SysTick */ && \ + !defined(MCU_MKL04Z4) /* SysTick */ && \ + !defined(MCU_MKL05Z4) /* SysTick */ && \ + !defined(MCU_MKL14Z4) /* SysTick */ && \ + !defined(MCU_MKL15Z4) /* SysTick */ && \ + !defined(MCU_MKL16Z4) /* SysTick */ && \ + !defined(MCU_MKL24Z4) /* SysTick */ && \ + !defined(MCU_MKL25Z4) /* SysTick */ && \ + !defined(MCU_MKL26Z4) /* SysTick */ && \ + !defined(MCU_MKL34Z4) /* SysTick */ && \ + !defined(MCU_MKL36Z4) /* SysTick */ && \ + !defined(MCU_MKL46Z4) /* SysTick */ && \ + !defined(MCU_MKV10Z7) /* SysTick */ && \ + !defined(MCU_MKV31F12810) /* SysTick */ && \ + !defined(MCU_MKV31F25612) /* SysTick */ && \ + !defined(MCU_MKV31F51212) /* SysTick */ && \ + !defined(MCU_MKW01Z4) /* SysTick */ && \ + !defined(MCU_MKW21D5) /* SysTick */ && \ + !defined(MCU_MKW21D5WS) /* SysTick */ && \ + !defined(MCU_MKW22D5) /* SysTick */ && \ + !defined(MCU_MKW22D5WS) /* SysTick */ && \ + !defined(MCU_MKW24D5) /* SysTick */ && \ + !defined(MCU_MKW24D5WS) /* SysTick */ && \ + !defined(MCU_PCK20L4) /* SysTick */ && \ + !defined(MCU_SKEAZ1284) /* SysTick */ + // Unsupported MCU is active + #error SysTick PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Clock source constants. */ + #define SysTick_PDD_CORE_CLOCK 0x1U /**< 1 */ + #define SysTick_PDD_CORE_CLOCK_DIV16 0U /**< 1 */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock source constants. */ + #define SysTick_PDD_CORE_CLOCK 0x1U /**< 1 */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_TICKINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_COUNTFLAG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the SysTick interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_EnableInterrupt(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) |= \ + SysTick_CSR_TICKINT_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the SysTick interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_DisableInterrupt(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SysTick_CSR_TICKINT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears SysTick interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ClearInterruptFlag(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) &= \ + (uint32)(~(uint32)SysTick_CSR_COUNTFLAG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the SysTick device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of SysTick device. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define SysTick_PDD_EnableDevice(PeripheralBase, State) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SysTick_CSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SysTick_CSR_ENABLE_MASK)))) | ( \ + (uint32)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current state of SysTick device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_ENABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClkSource + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param ClkSource New value of the clock source. Use constants from group + * "Clock source constants.". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_SetClkSource(_BASE_PTR, SysTick_PDD_CORE_CLOCK); + * @endcode + */ +#define SysTick_PDD_SetClkSource(PeripheralBase, ClkSource) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + SysTick_CSR_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)SysTick_CSR_CLKSOURCE_MASK)))) | ( \ + (uint32)((uint32)(ClkSource) << SysTick_CSR_CLKSOURCE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetClkSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL02Z4)) || (defined(MCU_MKL03Z4)) || (defined(MCU_MKL04Z4)) || (defined(MCU_MKL05Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Gets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Clock source constants." for processing + * return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint8 result = SysTick_PDD_GetClkSource(_BASE_PTR); + * @endcode + */ + #define SysTick_PDD_GetClkSource(PeripheralBase) ( \ + (uint8)(( \ + (uint32)(SysTick_CSR_REG(PeripheralBase) & SysTick_CSR_CLKSOURCE_MASK)) >> ( \ + SysTick_CSR_CLKSOURCE_SHIFT)) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Gets clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Clock source constants." for processing + * return value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint8 result = SysTick_PDD_GetClkSource(_BASE_PTR); + * @endcode + */ + #define SysTick_PDD_GetClkSource(PeripheralBase) ( \ + 0x1U \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the control and status register. This parameter + * is a 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * SysTick_PDD_WriteControlStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteControlStatusReg(PeripheralBase, Value) ( \ + SysTick_CSR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the control and status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CSR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_ReadControlStatusReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadControlStatusReg(PeripheralBase) ( \ + SysTick_CSR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteReloadValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the reload register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the reload register. This parameter is a 32-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_RVR. + * @par Example: + * @code + * SysTick_PDD_WriteReloadValueReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteReloadValueReg(PeripheralBase, Value) ( \ + SysTick_RVR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadReloadValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the reload register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_RVR. + * @par Example: + * @code + * uint32 result = SysTick_PDD_ReadReloadValueReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadReloadValueReg(PeripheralBase) ( \ + SysTick_RVR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCurrentValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the current value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the current value register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: SYST_CVR. + * @par Example: + * @code + * SysTick_PDD_WriteCurrentValueReg(_BASE_PTR, 1); + * @endcode + */ +#define SysTick_PDD_WriteCurrentValueReg(PeripheralBase, Value) ( \ + SysTick_CVR_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCurrentValueReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the current value register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CVR. + * @par Example: + * @code + * uint32 result = + * SysTick_PDD_ReadCurrentValueReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadCurrentValueReg(PeripheralBase) ( \ + SysTick_CVR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCalibrationReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the calibration register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: SYST_CALIB. + * @par Example: + * @code + * uint32 result = SysTick_PDD_ReadCalibrationReg(_BASE_PTR); + * @endcode + */ +#define SysTick_PDD_ReadCalibrationReg(PeripheralBase) ( \ + SysTick_CALIB_REG(PeripheralBase) \ + ) +#endif /* #if defined(SysTick_PDD_H_) */ + +/* SysTick_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h new file mode 100644 index 0000000..8616787 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/UART_PDD.h @@ -0,0 +1,5346 @@ +/* + PDD layer implementation for peripheral type UART + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(UART_PDD_H_) +#define UART_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error UART PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK10D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK10D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK10F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK10DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK11D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK11D5WS) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK12D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK20D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK20D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK20D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK20F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK20DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK21D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK21D5WS) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK21F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK21F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK22D5) /* UART0, UART1, UART2, UART3 */ && \ + !defined(MCU_MK22F12810) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK22F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK22F25612) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK22F51212) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MK24F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK30D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK30D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK30DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK40DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK40X256VMD100) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK50D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK50D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK50DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK51D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK51D7) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK51DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK52D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK52DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK53D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK53DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60D10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60DZ10) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK60N512VMD100) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK61F15WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK63F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK63F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK64F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK65F18) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK65F18WS) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK66F18) /* UART0, UART1, UART2, UART3, UART4 */ && \ + !defined(MCU_MK70F12) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F15) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F12WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MK70F15WS) /* UART0, UART1, UART2, UART3, UART4, UART5 */ && \ + !defined(MCU_MKE02Z2) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE02Z4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_SKEAZN642) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE04Z1284) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKE04Z4) /* UART0 */ && \ + !defined(MCU_SKEAZN84) /* UART0 */ && \ + !defined(MCU_MKE06Z4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKL14Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL15Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL16Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL24Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL25Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL26Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL34Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL36Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKL46Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKV10Z7) /* UART0, UART1 */ && \ + !defined(MCU_MKV31F12810) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKV31F25612) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKV31F51212) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW01Z4) /* UART1, UART2 */ && \ + !defined(MCU_MKW21D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW21D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW22D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW22D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW24D5) /* UART0, UART1, UART2 */ && \ + !defined(MCU_MKW24D5WS) /* UART0, UART1, UART2 */ && \ + !defined(MCU_PCK20L4) /* UART0, UART1, UART2 */ && \ + !defined(MCU_SKEAZ1284) /* UART0, UART1, UART2 */ + // Unsupported MCU is active + #error UART PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Interrupt masks */ +#define UART_PDD_INTERRUPT_TRANSMITTER UART_C2_TIE_MASK /**< Transmitter interrupt enable mask */ +#define UART_PDD_INTERRUPT_TRANSMITTER_COMPLETE UART_C2_TCIE_MASK /**< Transmitter complete interrupt enable mask */ +#define UART_PDD_INTERRUPT_RECEIVER UART_C2_RIE_MASK /**< Receiver interrupt enable mask */ +#define UART_PDD_INTERRUPT_IDLE UART_C2_ILIE_MASK /**< Idle interrupt enable mask */ +#define UART_PDD_INTERRUPT_PARITY_ERROR UART_C3_PEIE_MASK /**< Parity error interrupt enable mask */ +#define UART_PDD_INTERRUPT_FRAMING_ERROR UART_C3_FEIE_MASK /**< Framing error interrupt enable mask */ +#define UART_PDD_INTERRUPT_NOISE_ERROR UART_C3_NEIE_MASK /**< Noise error interrupt enable mask */ +#define UART_PDD_INTERRUPT_OVERRUN_ERROR UART_C3_ORIE_MASK /**< Overrun error interrupt enable mask */ + +/* Status flags constants. */ +#define UART_PDD_TX_DATA_EMPTY_FLAG UART_S1_TDRE_MASK /**< Transmitter FIFO word count is at or below watermark */ +#define UART_PDD_TX_IDLE_FLAG UART_S1_TC_MASK /**< No transmission in progress (transmission activity complete) */ +#define UART_PDD_RX_DATA_FULL_FLAG UART_S1_RDRF_MASK /**< Receiver FIFO word count is above watermark */ +#define UART_PDD_RX_IDLE_FLAG UART_S1_IDLE_MASK /**< Receiver input has become idle (after receiving a valid frame) */ +#define UART_PDD_RX_OVERRUN_FLAG UART_S1_OR_MASK /**< Receiver buffer overrun */ +#define UART_PDD_RX_NOISE_FLAG UART_S1_NF_MASK /**< Receiver input detect a noise. */ +#define UART_PDD_RX_FRAMING_ERROR_FLAG UART_S1_FE_MASK /**< Receiver framing error detect */ +#define UART_PDD_RX_PARITY_ERROR_FLAG UART_S1_PF_MASK /**< Receiver parity error detect */ + +/* Status 2 flags constants. */ +#define UART_PDD_LIN_BREAK_DETECT_FLAG UART_S2_LBKDIF_MASK /**< LIN break character is detected on the receiver input */ +#define UART_PDD_RXD_PIN_ACTIVE_EDGE_FLAG UART_S2_RXEDGIF_MASK /**< Active edge occurs on the RxD pin */ +#define UART_PDD_RECEIVER_ACTIVE_FLAG UART_S2_RAF_MASK /**< Receiver active, RxD input not idle */ + +/* Received data status constants. */ +#define UART_PDD_DATA_RECEIVED_WITH_NOISE UART_ED_NOISY_MASK /**< The data was received with noise */ +#define UART_PDD_DATA_RECEIVED_WITH_PARITY_ERROR UART_ED_PARITYE_MASK /**< The dataword was received with a parity error */ + +/* Enable FIFO masks */ +#define UART_PDD_TX_FIFO_ENABLE UART_PFIFO_TXFE_MASK /**< Transmitter FIFO enable mask */ +#define UART_PDD_RX_FIFO_ENABLE UART_PFIFO_RXFE_MASK /**< Receiver FIFO enable mask */ + +/* FIFO flush masks */ +#define UART_PDD_TX_FIFO_FLUSH UART_CFIFO_TXFLUSH_MASK /**< Transmitter FIFO flush command mask */ +#define UART_PDD_RX_FIFO_FLUSH UART_CFIFO_RXFLUSH_MASK /**< Receiver FIFO flush command mask */ + +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_PCK20L4))) +/* Rx buffer full, Tx buffer empty and error interrupt masks constant */ + #define UART_PDD_TX_FIFO_OVERFLOW_INT UART_CFIFO_TXOFE_MASK /**< Transmit FIFO overflow interrupt mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_INT UART_CFIFO_RXUFE_MASK /**< Receive FIFO underflow interrupt mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* Rx buffer full, Tx buffer empty and error interrupt masks constant */ + #define UART_PDD_RX_FIFO_OVERFLOW_INT UART_CFIFO_RXOFE_MASK /**< Receive FIFO overflow interrupt mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_INT UART_CFIFO_TXOFE_MASK /**< Transmit FIFO overflow interrupt mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_INT UART_CFIFO_RXUFE_MASK /**< Receive FIFO underflow interrupt mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +#if ((defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_PCK20L4))) +/* FIFO status flags constant */ + #define UART_PDD_TX_FIFO_EMPTY_FLAG UART_SFIFO_TXEMPT_MASK /**< Transmit buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_EMPTY_FLAG UART_SFIFO_RXEMPT_MASK /**< Receive buffer/FIFO empty mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_FLAG UART_SFIFO_TXOF_MASK /**< Transmit FIFO overflow flag mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_FLAG UART_SFIFO_RXUF_MASK /**< Receive FIFO underflow flag mask */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* FIFO status flags constant */ + #define UART_PDD_TX_FIFO_EMPTY_FLAG UART_SFIFO_TXEMPT_MASK /**< Transmit buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_EMPTY_FLAG UART_SFIFO_RXEMPT_MASK /**< Receive buffer/FIFO empty mask */ + #define UART_PDD_RX_FIFO_OVERFLOW_FLAG UART_SFIFO_RXOF_MASK /**< Receive FIFO overflow flag mask */ + #define UART_PDD_TX_FIFO_OVERFLOW_FLAG UART_SFIFO_TXOF_MASK /**< Transmit FIFO overflow flag mask */ + #define UART_PDD_RX_FIFO_UNDERFLOW_FLAG UART_SFIFO_RXUF_MASK /**< Receive FIFO underflow flag mask */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK50D10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) */ +/* ISO7816 Interrupt masks */ +#define UART_PDD_ISO7816_WAIT_TIMER_INT UART_IE7816_WTE_MASK /**< Wait timer interrupt mask */ +#define UART_PDD_ISO7816_CHAR_WAIT_TIMER_INT UART_IE7816_CWTE_MASK /**< Character wait timer interrupt mask */ +#define UART_PDD_ISO7816_BLOCK_WAIT_TIMER_INT UART_IE7816_BWTE_MASK /**< Block wait timer interrupt mask */ +#define UART_PDD_ISO7816_INITIAL_CHAR_DETECTED_INT UART_IE7816_INITDE_MASK /**< Initial character detected interrupt mask */ +#define UART_PDD_ISO7816_GUARD_TIMER_VIOLATED_INT UART_IE7816_GTVE_MASK /**< Guard timer violated interrupt mask */ +#define UART_PDD_ISO7816_TRANSMIT_THRESHOLD_EXCEED_INT UART_IE7816_TXTE_MASK /**< Transmit threshold exceeded interrupt mask */ +#define UART_PDD_ISO7816_RECEIVE_THRESHOLD_EXCEED_INT UART_IE7816_RXTE_MASK /**< Receive threshold exceeded interrupt mask */ + +/* ISO7816 interrupt flag masks */ +#define UART_PDD_ISO7816_WAIT_TIMER_FLAG UART_IS7816_WT_MASK /**< Wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_CHAR_WAIT_TIMER_FLAG UART_IS7816_CWT_MASK /**< Character wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_BLOCK_WAIT_TIMER_FLAG UART_IS7816_BWT_MASK /**< Block wait timer interrupt flag mask */ +#define UART_PDD_ISO7816_INITIAL_CHAR_DETECTED_FLAG UART_IS7816_INITD_MASK /**< Initial character detected interrupt flag mask */ +#define UART_PDD_ISO7816_GUARD_TIMER_VIOLATED_FLAG UART_IS7816_GTV_MASK /**< Guard timer violated interrupt flag mask */ +#define UART_PDD_ISO7816_TRANSMIT_THRESHOLD_EXCEED_FLAG UART_IS7816_TXT_MASK /**< Transmit threshold exceeded interrupt flag mask */ +#define UART_PDD_ISO7816_RECEIVE_THRESHOLD_EXCEED_FLAG UART_IS7816_RXT_MASK /**< Receive threshold exceeded interrupt flag mask */ + +/* CEA709.1-B interrupt masks constant */ +#define UART_PDD_CEA7091B_PREAMBLE_ERROR_FLAG UART_S3_PEF_MASK /**< Preamble error flag mask */ +#define UART_PDD_CEA7091B_WBASE_EXPIRED_FLAG UART_S3_WBEF_MASK /**< WBASE expired flag mask */ +#define UART_PDD_CEA7091B_INIT_SYNC_DETECTED_FLAG UART_S3_ISD_MASK /**< Initial sync detection flag mask */ +#define UART_PDD_CEA7091B_PACKED_RECEIVED_FLAG UART_S3_PRXF_MASK /**< Packet received flag mask */ +#define UART_PDD_CEA7091B_PACKED_TRANSMITTED_FLAG UART_S3_PTXF_MASK /**< Packet transmitted flag mask */ +#define UART_PDD_CEA7091B_PACKED_CYCLE_TIMER_FLAG UART_S3_PCTEF_MASK /**< Packet cycle timer expired flag mask */ +#define UART_PDD_CEA7091B_PREAMBLE_START_FLAG UART_S3_PSF_MASK /**< Preamble start flag mask */ +#define UART_PDD_CEA7091B_TRANSMISSION_FAIL_FLAG UART_S3_TXFF_MASK /**< Transmission fail flag mask */ + +/* CEA709.1-B interrupt masks constant */ +#define UART_PDD_CEA7091B_COLLISION_DETECTED_FLAG UART_S4_CDET_MASK /**< Collision detection flag mask */ +#define UART_PDD_CEA7091B_FRAMING_ERROR_FLAG UART_S4_FE_MASK /**< Framing error flag mask */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Loop mode */ + #define UART_PDD_LOOP_MODE_NORMAL 0U /**< Normal operation mode. No loopback selected. */ + #define UART_PDD_LOOP_MODE_LOCAL_LOOP 0x1U /**< Local loopback mode. */ + #define UART_PDD_LOOP_MODE_RX_TO_TX_PIN 0x2U /**< Receiver input connected to TXD pin (single wire operation) */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Loop mode */ + #define UART_PDD_LOOP_MODE_NORMAL 0U /**< Normal operation mode. No loopback selected */ + #define UART_PDD_LOOP_MODE_LOCAL_LOOP 0x80U /**< Local loopback mode. Receiver input internally connected to transmitter output */ + #define UART_PDD_LOOP_MODE_RX_TO_TX_PIN 0xA0U /**< Receiver input connected to TXD pin (single wire operation) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Data width */ + #define UART_PDD_WIDTH_8 0U /**< 8-bit communication */ + #define UART_PDD_WIDTH_9 0x10U /**< 9-bit communication */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Data width */ + #define UART_PDD_WIDTH_8 0U /**< 8-bit communication */ + #define UART_PDD_WIDTH_9 0x1U /**< 9-bit communication */ + #define UART_PDD_WIDTH_10 0x2U /**< 10-bit communication (10th bit can be used only as parity bit) */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Wake-up condition constants. */ +#define UART_PDD_BY_IDLE_LINE 0U /**< Idle line wake-up */ +#define UART_PDD_BY_ADDRESS_MARK 0x8U /**< Address mark wake-up */ + +/* Idle line type constants. */ +#define UART_PDD_AFTER_START_BIT 0U /**< Idle character bit count starts after start bit. */ +#define UART_PDD_AFTER_STOP_BIT 0x4U /**< Idle character bit count starts after stop bit. */ + +/* Parity types */ +#define UART_PDD_PARITY_NONE 0U /**< No parity */ +#define UART_PDD_PARITY_EVEN 0x2U /**< Even parity */ +#define UART_PDD_PARITY_ODD 0x3U /**< Even parity */ + +/* Receiver power states. */ +#define UART_PDD_POWER_NORMAL 0U /**< Normal operation. */ +#define UART_PDD_POWER_STANDBY 0x2U /**< Standby mode (waiting for a wakeup condition). */ + +/* UART data shift order constants */ +#define UART_PDD_LSB_FIRST 0x20U /**< Data transfers start with least significant bit */ +#define UART_PDD_MSB_FIRST 0U /**< Data transfers start with most significant bit */ + +/* Break transmit character length constants */ +#define UART_PDD_BREAK_CHARACTER_10_11_12_BITS 0U /**< Break character is 10, 11, or 12 bits long */ +#define UART_PDD_BREAK_CHARACTER_13_14_BITS 0x4U /**< Break character is 13 or 14 bits long */ + +/* Transmitter pin data direction (in single-wire mode) constants */ +#define UART_PDD_TX_PIN_IS_AN_INPUT 0U /**< TxD pin is an input in single wire mode */ +#define UART_PDD_TX_PIN_IS_AN_OUTPUT 0x20U /**< TxD pin is an output in single wire mode */ + +/* Position of a parity bit */ +#define UART_PDD_PARITY_BIT_POSITION_9 0U /**< Parity bit is the 9-th bit in the serial transmission */ +#define UART_PDD_PARITY_BIT_POSITION_10 0x20U /**< Parity bit is the 10-th bit in the serial transmission */ + +/* Request-to-send transmitter polarity constants */ +#define UART_PDD_RTS_ACTIVE_LOW 0U /**< Transmitter RTS is active low */ +#define UART_PDD_RTS_ACTIVE_HIGH 0x4U /**< Transmitter RTS is active high */ + +/* Parity types */ +#define UART_PDD_TX_NARROW_PULSE_3_DIV_16 0U /**< 3/16 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_16 0x1U /**< 1/16 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_32 0x2U /**< 1/32 narrow pulse */ +#define UART_PDD_TX_NARROW_PULSE_1_DIV_4 0x3U /**< 1/4 narrow pulse */ + +/* Transmit FIFO/Buffer depth constants. */ +#define UART_PDD_TX_FIFO_SIZE_1 0U /**< Transmit FIFO/Buffer depth = 1 dataword */ +#define UART_PDD_TX_FIFO_SIZE_4 0x10U /**< Transmit FIFO/Buffer depth = 4 datawords */ +#define UART_PDD_TX_FIFO_SIZE_8 0x20U /**< Transmit FIFO/Buffer depth = 8 datawords */ +#define UART_PDD_TX_FIFO_SIZE_16 0x30U /**< Transmit FIFO/Buffer depth = 16 datawords */ +#define UART_PDD_TX_FIFO_SIZE_32 0x40U /**< Transmit FIFO/Buffer depth = 32 datawords */ +#define UART_PDD_TX_FIFO_SIZE_64 0x50U /**< Transmit FIFO/Buffer depth = 64 datawords */ +#define UART_PDD_TX_FIFO_SIZE_128 0x60U /**< Transmit FIFO/Buffer depth = 128 datawords */ + +/* Receive FIFO/Buffer depth constants. */ +#define UART_PDD_RX_FIFO_SIZE_1 0U /**< Receive FIFO/Buffer depth = 1 dataword */ +#define UART_PDD_RX_FIFO_SIZE_4 0x1U /**< Receive FIFO/Buffer depth = 4 datawords */ +#define UART_PDD_RX_FIFO_SIZE_8 0x2U /**< Receive FIFO/Buffer depth = 8 datawords */ +#define UART_PDD_RX_FIFO_SIZE_16 0x3U /**< Receive FIFO/Buffer depth = 16 datawords */ +#define UART_PDD_RX_FIFO_SIZE_32 0x4U /**< Receive FIFO/Buffer depth = 32 datawords */ +#define UART_PDD_RX_FIFO_SIZE_64 0x5U /**< Receive FIFO/Buffer depth = 64 datawords */ +#define UART_PDD_RX_FIFO_SIZE_128 0x6U /**< Receive FIFO/Buffer depth = 128 datawords */ + +/* Transfer type constants */ +#define UART_PDD_ISO7816_TRANSFER_TYPE_T0 0U /**< T = 0 per the ISO-7816 specification */ +#define UART_PDD_ISO7816_TRANSFER_TYPE_T1 0x2U /**< T = 1 per the ISO-7816 specification */ + +/* Collision polarity constants */ +#define UART_PDD_CEA7091b_COLLISION_SIGNAL_LOW 0U /**< Collision signal is active low */ +#define UART_PDD_CEA7091b_COLLISION_SIGNAL_HIGH 0x10U /**< Collision signal is active high */ + +/* CEA709.1-B collision status constants. */ +#define UART_PDD_CEA7091B_NO_COLLISION 0U /**< No collision */ +#define UART_PDD_CEA7091B_COLLISION_PREAMBLE 0x4U /**< Collision occurred during preamble */ +#define UART_PDD_CEA7091B_COLLISION_SYNCH_OR_DATA 0x8U /**< Collision occurred during byte sync or data */ +#define UART_PDD_CEA7091B_COLLISION_LINE_CODE 0xCU /**< Collision occurred during line code violation */ + +/* Stop bit lengths */ +#define UART_PDD_STOP_BIT_LEN_1 0U /**< One stop bit. */ +#define UART_PDD_STOP_BIT_LEN_2 0x20U /**< Two stop bits. */ + + +/* ---------------------------------------------------------------------------- + -- SetBaudRate + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets new baud rate value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param BaudRate New baud rate value. This parameter is a 13-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART0_BDL, + * UART1_BDH, UART1_BDL, UART2_BDH, UART2_BDL, UART3_BDH, UART3_BDL, + * UART4_BDH, UART4_BDL, UART5_BDH, UART5_BDL (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBaudRate(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetBaudRate(PeripheralBase, BaudRate) ( \ + (UART_BDH_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_BDH_REG(PeripheralBase) & (uint8)(~(uint8)UART_BDH_SBR_MASK))) | ( \ + (uint8)((uint16)(BaudRate) >> 8U)))), \ + (UART_BDL_REG(PeripheralBase) = \ + (uint8)(BaudRate)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadBaudRateHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadBaudRateHighReg(PeripheralBase) ( \ + UART_BDH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into baud rate high + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate high register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteBaudRateHighReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteBaudRateHighReg(PeripheralBase, Value) ( \ + UART_BDH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBaudRateLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads baud rate low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_BDL, UART1_BDL, + * UART2_BDL, UART3_BDL, UART4_BDL, UART5_BDL (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadBaudRateLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadBaudRateLowReg(PeripheralBase) ( \ + UART_BDL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBaudRateLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into baud rate low + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the baud rate low register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDL, UART1_BDL, + * UART2_BDL, UART3_BDL, UART4_BDL, UART5_BDL (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteBaudRateLowReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteBaudRateLowReg(PeripheralBase, Value) ( \ + UART_BDL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetLoopMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects the loop mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param LoopMode Loop mode. This parameter is of "Loop mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetLoopMode(_BASE_PTR, UART_PDD_LOOP_MODE_NORMAL); + * @endcode + */ + #define UART_PDD_SetLoopMode(PeripheralBase, LoopMode) ( \ + ((LoopMode) == UART_PDD_LOOP_MODE_NORMAL) ? ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(( \ + (uint8)(~(uint8)UART_C1_LOOPS_MASK)) & ( \ + (uint8)(~(uint8)UART_C1_RSRC_MASK)))) : (((LoopMode) == UART_PDD_LOOP_MODE_LOCAL_LOOP) ? ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) | UART_C1_LOOPS_MASK)) & ( \ + (uint8)(~(uint8)UART_C1_RSRC_MASK)))) : ( \ + UART_C1_REG(PeripheralBase) |= \ + (uint8)(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK)) \ + ) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects the loop mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param LoopMode Loop mode. This parameter is of "Loop mode" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetLoopMode(_BASE_PTR, UART_PDD_LOOP_MODE_NORMAL); + * @endcode + */ + #define UART_PDD_SetLoopMode(PeripheralBase, LoopMode) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_C1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK))))) | ( \ + (uint8)(LoopMode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableOperateInWaitMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables operate in wait mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of device in wait mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableOperateInWaitMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableOperateInWaitMode(PeripheralBase, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_UARTSWAI_MASK) : ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C1_UARTSWAI_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataWidth + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets the communication width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data width. This parameter is of "Data width" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART0_C4, + * UART1_C1, UART1_C4, UART2_C1, UART2_C4, UART3_C1, UART3_C4, UART4_C1, + * UART4_C4, UART5_C1, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataWidth(_BASE_PTR, UART_PDD_WIDTH_8); + * @endcode + */ + #define UART_PDD_SetDataWidth(PeripheralBase, Width) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_M_MASK))) | ( \ + (uint8)(Width))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the communication width. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Width Data width. This parameter is of "Data width" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART0_C4, + * UART1_C1, UART1_C4, UART2_C1, UART2_C4, UART3_C1, UART3_C4, UART4_C1, + * UART4_C4, UART5_C1, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataWidth(_BASE_PTR, UART_PDD_WIDTH_8); + * @endcode + */ + #define UART_PDD_SetDataWidth(PeripheralBase, Width) ( \ + ( \ + ((Width) == UART_PDD_WIDTH_8) ? ( \ + UART_C1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C1_M_MASK)) : (((Width) == UART_PDD_WIDTH_9) ? ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_M_MASK) : ( \ + UART_C1_REG(PeripheralBase) |= \ + UART_C1_M_MASK) \ + )), \ + ( \ + ((Width) == UART_PDD_WIDTH_8) ? ( \ + UART_C4_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C4_M10_MASK)) : (((Width) == UART_PDD_WIDTH_9) ? ( \ + UART_C4_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C4_M10_MASK)) : ( \ + UART_C4_REG(PeripheralBase) |= \ + UART_C4_M10_MASK) \ + )) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetWakeupCondition + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the wake-up condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Condition Wake-up condition. This parameter is of "Wake-up condition + * constants." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetWakeupCondition(_BASE_PTR, + * UART_PDD_BY_IDLE_LINE); + * @endcode + */ +#define UART_PDD_SetWakeupCondition(PeripheralBase, Condition) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_WAKE_MASK))) | ( \ + (uint8)(Condition))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectIdleLineType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the idle line type, it determines when the receiver starts + * counting logic 1s as idle character bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Idle line type. This parameter is of "Idle line type constants." + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SelectIdleLineType(_BASE_PTR, + * UART_PDD_AFTER_START_BIT); + * @endcode + */ +#define UART_PDD_SelectIdleLineType(PeripheralBase, Type) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)UART_C1_ILT_MASK))) | ( \ + (uint8)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetParity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a communication parity type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Parity Parity type. This parameter is of "Parity types" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetParity(_BASE_PTR, UART_PDD_PARITY_NONE); + * @endcode + */ +#define UART_PDD_SetParity(PeripheralBase, Parity) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C1_REG(PeripheralBase) & (uint8)(~(uint8)0x3U))) | ( \ + (uint8)(Parity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl1Reg(PeripheralBase) ( \ + UART_C1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C1, UART1_C1, + * UART2_C1, UART3_C1, UART4_C1, UART5_C1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl1Reg(PeripheralBase, Value) ( \ + UART_C1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART0_C3, + * UART1_C2, UART1_C3, UART2_C2, UART2_C3, UART3_C2, UART3_C3, UART4_C2, + * UART4_C3, UART5_C2, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInterrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_EnableInterrupt(PeripheralBase, Mask) ( \ + (UART_C2_REG(PeripheralBase) |= \ + (uint8)((uint8)(Mask) & (uint8)(~(uint8)0xFU))), \ + (UART_C3_REG(PeripheralBase) |= \ + (uint8)((uint8)(Mask) & 0xFU)) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART0_C3, + * UART1_C2, UART1_C3, UART2_C2, UART2_C3, UART3_C2, UART3_C3, UART4_C2, + * UART4_C3, UART5_C2, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_DisableInterrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_DisableInterrupt(PeripheralBase, Mask) ( \ + (UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)((uint8)(Mask) & (uint8)(~(uint8)0xFU)))), \ + (UART_C3_REG(PeripheralBase) &= \ + (uint8)(~(uint8)((uint8)(Mask) & 0xFU))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxCompleteInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the transmiter complete interrupt enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetTxCompleteInterruptMask(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxCompleteInterruptMask(PeripheralBase) ( \ + (uint8)(UART_C2_REG(PeripheralBase) & UART_C2_TCIE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitter + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables UART transmitter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables transmitter. This parameter is of "Global + * enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitter(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitter(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_TE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C2_TE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiver + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables UART receiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receiver. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiver(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableReceiver(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_RE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C2_RE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetReceiverPowerState + ---------------------------------------------------------------------------- */ + +/** + * @brief Places the receiver in a standby state where it waits for automatic + * hardware detection of a selected wakeup condition. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Receiver power state to be set. This parameter is of "Receiver + * power states." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetReceiverPowerState(_BASE_PTR, + * UART_PDD_POWER_NORMAL); + * @endcode + */ +#define UART_PDD_SetReceiverPowerState(PeripheralBase, State) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C2_REG(PeripheralBase) & (uint8)(~(uint8)UART_C2_RWU_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Set the break signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SetBreak(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) |= \ + UART_C2_SBK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the break signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ClearBreak(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C2_SBK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Send the break character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SendBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SendBreak(PeripheralBase) ( \ + (UART_C2_REG(PeripheralBase) |= \ + UART_C2_SBK_MASK), \ + (UART_C2_REG(PeripheralBase) &= \ + (uint8)(~(uint8)UART_C2_SBK_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl2Reg(PeripheralBase) ( \ + UART_C2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C2, UART1_C2, + * UART2_C2, UART3_C2, UART4_C2, UART5_C2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl2Reg(PeripheralBase, Value) ( \ + UART_C2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus1Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus1Flags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus1Flags(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxCompleteStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the transmiter complete interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetTxCompleteStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxCompleteStatus(PeripheralBase) ( \ + (uint8)(UART_S1_REG(PeripheralBase) & UART_S1_TC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadInterruptStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadInterruptStatusReg(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBreak + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetBreak(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetBreak(PeripheralBase) ( \ + (( \ + (uint8)(UART_S1_REG(PeripheralBase) & (uint8)(UART_S1_FE_MASK | UART_S1_RDRF_MASK))) == ( \ + (uint8)(UART_S1_FE_MASK | UART_S1_RDRF_MASK))) ? ( \ + 0x1U) : ( \ + 0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1, UART3_S1, UART4_S1, UART5_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus1Reg(PeripheralBase) ( \ + UART_S1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatus2Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the flags of the status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus2Flags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus2Flags(PeripheralBase) ( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & ( \ + (uint8)(UART_S2_LBKDIF_MASK | (UART_S2_RXEDGIF_MASK | UART_S2_RAF_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStatus2Flags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the flags of the status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearStatus2Flags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearStatus2Flags(PeripheralBase, Mask) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)(UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK))))) | ( \ + (uint8)(Mask))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDataShiftOrder + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_MSBF_MASK))) | ( \ + (uint8)(Order))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_MSBF_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Order))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_MSBF_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Order))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets the UART data shift order. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Order UART data shift order value. The user should use one from the + * enumerated values. This parameter is of "UART data shift order constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetDataShiftOrder(_BASE_PTR, UART_PDD_LSB_FIRST); + * @endcode + */ + #define UART_PDD_SetDataShiftOrder(PeripheralBase, Order) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_MSBF_MASK))) | ( \ + (uint8)(Order))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDataInversion + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RXINV_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RXINV_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables receive data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive data inversion. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDataInversion(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDataInversion(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RXINV_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveWakeupIdleDetect + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RWUID_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RWUID_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_RWUID_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables receive wakeup idle detect. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables receive wakeup idle detect. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveWakeupIdleDetect(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveWakeupIdleDetect(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_RWUID_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_RWUID_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- SetBreakLength + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_BRK13_MASK))) | ( \ + (uint8)(Length))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_BRK13_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Length))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_BRK13_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)(Length))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Sets the break transmit character length. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Break transmit character length value. The user should use one + * from the enumerated values. This parameter is of "Break transmit + * character length constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBreakLength(_BASE_PTR, + * UART_PDD_BREAK_CHARACTER_10_11_12_BITS); + * @endcode + */ + #define UART_PDD_SetBreakLength(PeripheralBase, Length) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_BRK13_MASK))) | ( \ + (uint8)(Length))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- EnableLinBreakLongerCharacterDetection + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22F12))) +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + (PeripheralBase == UART0_BASE_PTR) ? ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_LBKDE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) : ( /* (PeripheralBase==UART1_BASE_PTR) || (PeripheralBase==UART2_BASE_PTR) || (PeripheralBase==UART3_BASE_PTR) || (PeripheralBase==UART4_BASE_PTR) || (PeripheralBase==UART5_BASE_PTR) */ \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_LBKDE_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) \ + ) +#elif ((defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212))) +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_S2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)UART_S2_LBKDE_MASK)) & (( \ + (uint8)(~(uint8)UART_S2_RXEDGIF_MASK)) & ( \ + (uint8)(~(uint8)UART_S2_LBKDIF_MASK)))))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ +/** + * @brief Enables LIN break detection for longer character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables LIN break detection for longer character. + * This parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakLongerCharacterDetection(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableLinBreakLongerCharacterDetection(PeripheralBase, State) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_S2_REG(PeripheralBase) & (uint8)(~(uint8)UART_S2_LBKDE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_S2_LBKDE_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84)) */ + +/* ---------------------------------------------------------------------------- + -- ReadStatus2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadStatus2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadStatus2Reg(PeripheralBase) ( \ + UART_S2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatus2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status 2 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S2, UART1_S2, + * UART2_S2, UART3_S2, UART4_S2, UART5_S2 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteStatus2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteStatus2Reg(PeripheralBase, Value) ( \ + UART_S2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChar9Bit + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the 9th bit of the character from the receive buffer shifted + * to its bit position (9th). Must be called prior to calling GetChar8 to read the + * whole 9-bit character. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 9-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = UART_PDD_GetChar9Bit(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetChar9Bit(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)(UART_C3_REG(PeripheralBase) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)) << ( \ + 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- PutChar9 + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts 9-bits character into the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Char 9-bits character to be written to the data register. This + * parameter is a 9-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART0_D, + * UART1_C3, UART1_D, UART2_C3, UART2_D, UART3_C3, UART3_D, UART4_C3, + * UART4_D, UART5_C3, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_PutChar9(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_PutChar9(PeripheralBase, Char) ( \ + (UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_T8_MASK))) | ( \ + (uint8)((uint8)((uint16)(Char) >> 8U) << UART_C3_T8_SHIFT)))), \ + (UART_D_REG(PeripheralBase) = \ + (uint8)(Char)) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTxPinDataDirection + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transmitter pin data direction in single-wire mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Direction Transmitter pin data direction value. The user should use + * one from the enumerated values. This parameter is of "Transmitter pin + * data direction (in single-wire mode) constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetTxPinDataDirection(_BASE_PTR, + * UART_PDD_TX_PIN_IS_AN_INPUT); + * @endcode + */ +#define UART_PDD_SetTxPinDataDirection(PeripheralBase, Direction) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_TXDIR_MASK))) | ( \ + (uint8)(Direction))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDataInversion + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables transmit data inversion. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables transmit data inversion. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDataInversion(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitDataInversion(PeripheralBase, State) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C3_REG(PeripheralBase) & (uint8)(~(uint8)UART_C3_TXINV_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C3_TXINV_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl3Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl3Reg(PeripheralBase) ( \ + UART_C3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into control 3 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 3 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C3, UART1_C3, + * UART2_C3, UART3_C3, UART4_C3, UART5_C3 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl3Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl3Reg(PeripheralBase, Value) ( \ + UART_C3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- PutChar8 + ---------------------------------------------------------------------------- */ + +/** + * @brief Puts 8-bits character into the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Char 8-bits character to be written to the data register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_PutChar8(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_PutChar8(PeripheralBase, Char) ( \ + UART_D_REG(PeripheralBase) = \ + (uint8)(Char) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChar8 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns a 8-bit character from the receive buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetChar8(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetChar8(PeripheralBase) ( \ + UART_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadDataReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadDataReg(PeripheralBase) ( \ + UART_D_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the data register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_D, UART1_D, + * UART2_D, UART3_D, UART4_D, UART5_D (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteDataReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteDataReg(PeripheralBase, Value) ( \ + UART_D_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMatchAddress1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns match address 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetMatchAddress1Value(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetMatchAddress1Value(PeripheralBase) ( \ + UART_MA1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatchAddress1Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a new match address 1 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Match address 1 value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetMatchAddress1Value(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetMatchAddress1Value(PeripheralBase, Address) ( \ + UART_MA1_REG(PeripheralBase) = \ + (uint8)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match address 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadMatchAddress1Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadMatchAddress1Reg(PeripheralBase) ( \ + UART_MA1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchAddress1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into match address 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match address 1 register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA1, UART1_MA1, + * UART2_MA1, UART3_MA1, UART4_MA1, UART5_MA1 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteMatchAddress1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteMatchAddress1Reg(PeripheralBase, Value) ( \ + UART_MA1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetMatchAddress2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns match address 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetMatchAddress2Value(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetMatchAddress2Value(PeripheralBase) ( \ + UART_MA2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetMatchAddress2Value + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a new match address 2 value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address Match address 2 value. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetMatchAddress2Value(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetMatchAddress2Value(PeripheralBase, Address) ( \ + UART_MA2_REG(PeripheralBase) = \ + (uint8)(Address) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadMatchAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads match address 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadMatchAddress2Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadMatchAddress2Reg(PeripheralBase) ( \ + UART_MA2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteMatchAddress2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into match address 2 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the match address 2 register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MA2, UART1_MA2, + * UART2_MA2, UART3_MA2, UART4_MA2, UART5_MA2 (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_WriteMatchAddress2Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteMatchAddress2Reg(PeripheralBase, Value) ( \ + UART_MA2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchAddress1Mode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables address 1 match mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables address 1 match mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableMatchAddress1Mode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableMatchAddress1Mode(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_MAEN1_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_MAEN1_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableMatchAddress2Mode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables address 2 match mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables address 2 match mode. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableMatchAddress2Mode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableMatchAddress2Mode(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_MAEN2_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_MAEN2_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPositionOfParityBit + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the position of the parity bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Position Position of a parity bit. This parameter is of "Position of a + * parity bit" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetPositionOfParityBit(_BASE_PTR, + * UART_PDD_PARITY_BIT_POSITION_9); + * @endcode + */ +#define UART_PDD_SetPositionOfParityBit(PeripheralBase, Position) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_M10_MASK))) | ( \ + (uint8)(Position))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetBaudRateFineAdjust + ---------------------------------------------------------------------------- */ + +/** + * @brief Set new baud rate fine adjust value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FineAdjust New baud rate fine adjust value. This parameter is a 5-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetBaudRateFineAdjust(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetBaudRateFineAdjust(PeripheralBase, FineAdjust) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_BRFA_MASK))) | ( \ + (uint8)(FineAdjust))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl4Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl4Reg(PeripheralBase) ( \ + UART_C4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl4Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control 4 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 4 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C4, UART1_C4, + * UART2_C4, UART3_C4, UART4_C4, UART5_C4 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl4Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl4Reg(PeripheralBase, Value) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitDma + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_TDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_TDMAS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables/disables a transmit DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmit DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableTransmitDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_TDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_TDMAS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableReceiveDma + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKL14Z4)) || (defined(MCU_MKL15Z4)) || (defined(MCU_MKL16Z4)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL34Z4)) || (defined(MCU_MKL36Z4)) || (defined(MCU_MKL46Z4)) || (defined(MCU_MKW01Z4))) +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + UART_C4_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C4_REG(PeripheralBase) & (uint8)(~(uint8)UART_C4_RDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C4_RDMAS_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables/disables a receive DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receive DMA request. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5, UART1_C4, UART2_C4 (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiveDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define UART_PDD_EnableReceiveDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_RDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_RDMAS_SHIFT))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadControl5Reg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadControl5Reg(PeripheralBase) ( \ + UART_C5_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControl5Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control 5 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control 5 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteControl5Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteControl5Reg(PeripheralBase, Value) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxDataExtendedStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the received data status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ED, UART1_ED, + * UART2_ED, UART3_ED, UART4_ED, UART5_ED (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetRxDataExtendedStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetRxDataExtendedStatus(PeripheralBase) ( \ + UART_ED_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadExtendedDataReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads extended data register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ED, UART1_ED, + * UART2_ED, UART3_ED, UART4_ED, UART5_ED (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadExtendedDataReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadExtendedDataReg(PeripheralBase) ( \ + UART_ED_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableReceiverRequestToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables receiver request-to-send, it allows the RTS output to + * control the CTS input of the transmitting device to prevent receiver overrun. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of receiver request-to-send. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableReceiverRequestToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableReceiverRequestToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_RXRTSE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_MODEM_RXRTSE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitterRequestToSendPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the polarity of the transmitter RTS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Request-to-send transmitter polarity. This parameter is of + * "Request-to-send transmitter polarity constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_SetTransmitterRequestToSendPolarity(_BASE_PTR, + * UART_PDD_RTS_ACTIVE_LOW); + * @endcode + */ +#define UART_PDD_SetTransmitterRequestToSendPolarity(PeripheralBase, Polarity) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXRTSPOL_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitterRequestToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transmitter request-to-send, it allows control RTS + * before and after a transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter request-to-send. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitterRequestToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitterRequestToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXRTSE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_MODEM_TXRTSE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTransmitterClearToSend + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables transmitter clear-to-send operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter clear-to-send operation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableTransmitterClearToSend(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableTransmitterClearToSend(PeripheralBase, State) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_MODEM_REG(PeripheralBase) & (uint8)(~(uint8)UART_MODEM_TXCTSE_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadModemReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads modem register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadModemReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadModemReg(PeripheralBase) ( \ + UART_MODEM_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteModemReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into modem register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the modem register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_MODEM, + * UART1_MODEM, UART2_MODEM, UART3_MODEM, UART4_MODEM, UART5_MODEM (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteModemReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteModemReg(PeripheralBase, Value) ( \ + UART_MODEM_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInfraredModulation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables infrared modulation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of infrared modulation. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInfraredModulation(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableInfraredModulation(PeripheralBase, State) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_IR_REG(PeripheralBase) & (uint8)(~(uint8)UART_IR_IREN_MASK))) | ( \ + (uint8)((uint8)(State) << UART_IR_IREN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTransmitterNarrowPulse + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets a transmitter narrow pulse. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Pulse narrow pulse. This parameter is of "Parity types" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetTransmitterNarrowPulse(_BASE_PTR, + * UART_PDD_TX_NARROW_PULSE_3_DIV_16); + * @endcode + */ +#define UART_PDD_SetTransmitterNarrowPulse(PeripheralBase, Pulse) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_IR_REG(PeripheralBase) & (uint8)(~(uint8)UART_IR_TNP_MASK))) | ( \ + (uint8)(Pulse))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadInfraredReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads infrared register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadInfraredReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadInfraredReg(PeripheralBase) ( \ + UART_IR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteInfraredReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into infrared register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the infrared register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IR, UART1_IR, + * UART2_IR, UART3_IR, UART4_IR, UART5_IR (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteInfraredReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteInfraredReg(PeripheralBase, Value) ( \ + UART_IR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifo + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables FIFO specified by the FifoMask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FifoMask Specifies receive or transmit FIFO. Use constants from group + * "Enable FIFO masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableFifo(_BASE_PTR, UART_PDD_TX_FIFO_ENABLE); + * @endcode + */ +#define UART_PDD_EnableFifo(PeripheralBase, FifoMask) ( \ + UART_PFIFO_REG(PeripheralBase) |= \ + (uint8)(FifoMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTxFifoSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the maximum number of transmit datawords that can be stored in + * the transmit buffer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Transmit FIFO/Buffer depth constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetTxFifoSize(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetTxFifoSize(PeripheralBase) ( \ + (uint8)(UART_PFIFO_REG(PeripheralBase) & UART_PFIFO_TXFIFOSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetRxFifoSize + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the maximum number of receive datawords that can be stored in + * the receive buffer before an overrun occurs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receive FIFO/Buffer depth constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_GetRxFifoSize(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetRxFifoSize(PeripheralBase) ( \ + (uint8)(UART_PFIFO_REG(PeripheralBase) & UART_PFIFO_RXFIFOSIZE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoParametersReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO parameters register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoParametersReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoParametersReg(PeripheralBase) ( \ + UART_PFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoParametersReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO parameters + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO parameters register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PFIFO, + * UART1_PFIFO, UART2_PFIFO, UART3_PFIFO, UART4_PFIFO, UART5_PFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoParametersReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoParametersReg(PeripheralBase, Value) ( \ + UART_PFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- FlushFifo + ---------------------------------------------------------------------------- */ + +/** + * @brief Flushes FIFO specified by the FifoMask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param FifoMask Specifies receive or transmit FIFO. Use constants from group + * "FIFO flush masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_FlushFifo(_BASE_PTR, UART_PDD_TX_FIFO_FLUSH); + * @endcode + */ +#define UART_PDD_FlushFifo(PeripheralBase, FifoMask) ( \ + UART_CFIFO_REG(PeripheralBase) |= \ + (uint8)(FifoMask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupt FIFO requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_EnableFifoInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_EnableFifoInterruptMask(PeripheralBase, Mask) ( \ + UART_CFIFO_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableFifoInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupt FIFO requests defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of FIFO interrupt requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_DisableFifoInterruptMask(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_DisableFifoInterruptMask(PeripheralBase, Mask) ( \ + UART_CFIFO_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoControlReg(PeripheralBase) ( \ + UART_CFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO control register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoControlReg(PeripheralBase, Value) ( \ + UART_CFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SFIFO, + * UART1_SFIFO, UART2_SFIFO, UART3_SFIFO, UART4_SFIFO, UART5_SFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoStatusFlags(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoStatusFlags(PeripheralBase) ( \ + UART_SFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearFifoStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears FIFO status flags defined by mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of flag requests. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SFIFO, + * UART1_SFIFO, UART2_SFIFO, UART3_SFIFO, UART4_SFIFO, UART5_SFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_ClearFifoStatusFlags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearFifoStatusFlags(PeripheralBase, Mask) ( \ + UART_SFIFO_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadFifoStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadFifoStatusReg(PeripheralBase) ( \ + UART_CFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFifoStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO status register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CFIFO, + * UART1_CFIFO, UART2_CFIFO, UART3_CFIFO, UART4_CFIFO, UART5_CFIFO (depending on + * the peripheral). + * @par Example: + * @code + * UART_PDD_WriteFifoStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteFifoStatusReg(PeripheralBase, Value) ( \ + UART_CFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO transmit watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TWFIFO, + * UART1_TWFIFO, UART2_TWFIFO, UART3_TWFIFO, UART4_TWFIFO, UART5_TWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadTxFifoWatermarkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadTxFifoWatermarkReg(PeripheralBase) ( \ + UART_TWFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO transmit + * watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO transmit watermark register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TWFIFO, + * UART1_TWFIFO, UART2_TWFIFO, UART3_TWFIFO, UART4_TWFIFO, UART5_TWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteTxFifoWatermarkReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteTxFifoWatermarkReg(PeripheralBase, Value) ( \ + UART_TWFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTxFifoCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO transmit count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TCFIFO, + * UART1_TCFIFO, UART2_TCFIFO, UART3_TCFIFO, UART4_TCFIFO, UART5_TCFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadTxFifoCountReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadTxFifoCountReg(PeripheralBase) ( \ + UART_TCFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO receive watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RWFIFO, + * UART1_RWFIFO, UART2_RWFIFO, UART3_RWFIFO, UART4_RWFIFO, UART5_RWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadRxFifoWatermarkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadRxFifoWatermarkReg(PeripheralBase) ( \ + UART_RWFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRxFifoWatermarkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into FIFO receive + * watermark register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the FIFO receive watermark register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_RWFIFO, + * UART1_RWFIFO, UART2_RWFIFO, UART3_RWFIFO, UART4_RWFIFO, UART5_RWFIFO (depending + * on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteRxFifoWatermarkReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteRxFifoWatermarkReg(PeripheralBase, Value) ( \ + UART_RWFIFO_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadRxFifoCountkReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads FIFO receive count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RCFIFO, + * UART1_RCFIFO, UART2_RCFIFO, UART3_RCFIFO, UART4_RCFIFO, UART5_RCFIFO (depending + * on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadRxFifoCountkReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadRxFifoCountkReg(PeripheralBase) ( \ + UART_RCFIFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGenerateNackOnOverflow + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating NACK if a receive buffer overrun. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state generating NACK on overflow. This parameter is + * of "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableGenerateNackOnOverflow(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableGenerateNackOnOverflow(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_ONACK_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_ONACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableGenerateNackOnError + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating NACK if a parity error occurs or if INIT + * is set and an invalid initial character is detected. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state generating NACK on error. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableGenerateNackOnError(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableGenerateNackOnError(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_ANACK_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_ANACK_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInitialCharDetection + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables generating initial char detection. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of initial char detection. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableInitialCharDetection(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableInitialCharDetection(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_INIT_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C7816_INIT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransferType + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the transfer type. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Type Transfer type. This parameter is of "Transfer type constants" + * type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransferType(_BASE_PTR, + * UART_PDD_ISO7816_TRANSFER_TYPE_T0); + * @endcode + */ +#define UART_PDD_SetIso7816TransferType(PeripheralBase, Type) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C7816_REG(PeripheralBase) & (uint8)(~(uint8)UART_C7816_TTYPE_MASK))) | ( \ + (uint8)(Type))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIso7816Functionality + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables ISO-7816 functionality. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of ISO-7816 functionality . This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableIso7816Functionality(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableIso7816Functionality(PeripheralBase, State) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_C7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_C7816_ISO_7816E_MASK)))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816ControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816ControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816ControlReg(PeripheralBase) ( \ + UART_C7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816ControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 control register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C7816, UART1_C7816 + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816ControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816ControlReg(PeripheralBase, Value) ( \ + UART_C7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIso7816Interrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables ISO7816 interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "ISO7816 Interrupt + * masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableIso7816Interrupt(_BASE_PTR, + * UART_PDD_ISO7816_WAIT_TIMER_INT); + * @endcode + */ +#define UART_PDD_EnableIso7816Interrupt(PeripheralBase, Mask) ( \ + UART_IE7816_REG(PeripheralBase) |= \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableIso7816Interrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables interrupts specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Interrupt masks". This + * parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_DisableIso7816Interrupt(_BASE_PTR, + * UART_PDD_INTERRUPT_TRANSMITTER); + * @endcode + */ +#define UART_PDD_DisableIso7816Interrupt(PeripheralBase, Mask) ( \ + UART_IE7816_REG(PeripheralBase) &= \ + (uint8)(~(uint8)(Mask)) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816InterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816InterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816InterruptEnableReg(PeripheralBase) ( \ + UART_IE7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816InterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 interrupt + * enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 interrupt enable register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE7816, + * UART1_IE7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816InterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816InterruptEnableReg(PeripheralBase, Value) ( \ + UART_IE7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadIso7816StatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ISO7816 status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "ISO7816 interrupt flag masks" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ReadIso7816StatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadIso7816StatusReg(PeripheralBase) ( \ + UART_IS7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearIso7816InterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears ISO7816 interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "ISO7816 interrupt flag masks". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_ClearIso7816InterruptFlags(_BASE_PTR, + * UART_PDD_ISO7816_WAIT_TIMER_FLAG); + * @endcode + */ +#define UART_PDD_ClearIso7816InterruptFlags(PeripheralBase, Mask) ( \ + UART_IS7816_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816InterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816InterruptStatusReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816InterruptStatusReg(PeripheralBase) ( \ + UART_IS7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816InterruptStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 interrupt + * status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 interrupt status register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IS7816, + * UART1_IS7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816InterruptStatusReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816InterruptStatusReg(PeripheralBase, Value) ( \ + UART_IS7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816WaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 wait timer interrupt value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 wait timer interrupt value[0..255]. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816WaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816WaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitTimerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait timer interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitTimerReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitTimerReg(PeripheralBase) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitTimerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait timer + * interrupt register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait timer interrupt register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T0, + * UART1_WP7816T0 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitTimerReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitTimerReg(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816CharacterWaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 character wait time integer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 character wait time integer value[0..15]. This parameter + * is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816CharacterWaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816CharacterWaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_WP7816_T_TYPE1_CWI_MASK)))) | ( \ + (uint8)((uint8)(Value) << UART_WP7816_T_TYPE1_CWI_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816BlockWaitTimerValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 block wait time integer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 block wait time integer value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816BlockWaitTimerValue(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816BlockWaitTimerValue(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_WP7816_T_TYPE1_BWI_MASK)))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitParameterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait parameter register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816WaitParameterReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitParameterReg(PeripheralBase) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitParameterReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait parameter + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait parameter register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WP7816T1, + * UART1_WP7816T1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitParameterReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitParameterReg(PeripheralBase, Value) ( \ + UART_WP7816_T_TYPE1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitNReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait N register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WN7816, + * UART1_WN7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitNReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitNReg(PeripheralBase) ( \ + UART_WN7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitNReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait N register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait N register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WN7816, + * UART1_WN7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitNReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitNReg(PeripheralBase, Value) ( \ + UART_WN7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816WaitFdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 wait FD register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WF7816, + * UART1_WF7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_Read7816WaitFdReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816WaitFdReg(PeripheralBase) ( \ + UART_WF7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816WaitFdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 wait FD + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 wait FD register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WF7816, + * UART1_WF7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816WaitFdReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816WaitFdReg(PeripheralBase, Value) ( \ + UART_WF7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransmitNackThreshold + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 transmit NAC threshold value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 transmit NACK threshold value[0..15]. This parameter is + * a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransmitNackThreshold(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816TransmitNackThreshold(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_ET7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_ET7816_TXTHRESHOLD_MASK)))) | ( \ + (uint8)((uint8)(Value) << UART_ET7816_TXTHRESHOLD_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816ReceiveNackThreshold + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 receive NAC threshold value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 receive NACK threshold value[0..15]. This parameter is a + * 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816ReceiveNackThreshold(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816ReceiveNackThreshold(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + UART_ET7816_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)UART_ET7816_RXTHRESHOLD_MASK)))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816ErrorThresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 error threshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816ErrorThresholdReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816ErrorThresholdReg(PeripheralBase) ( \ + UART_ET7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816ErrorThresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 error threshold + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the 7816 error threshold register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_ET7816, + * UART1_ET7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816ErrorThresholdReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816ErrorThresholdReg(PeripheralBase, Value) ( \ + UART_ET7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetIso7816TransmitLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the value of the ISO7816 transmit length value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value ISO7816 transmit length value[0..15]. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetIso7816TransmitLength(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetIso7816TransmitLength(PeripheralBase, Value) ( \ + UART_TL7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- Read7816TransmitLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads 7816 transmit length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = + * UART_PDD_Read7816TransmitLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_Read7816TransmitLengthReg(PeripheralBase) ( \ + UART_TL7816_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- Write7816TransmitLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into 7816 transmit length + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the transmit error length register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TL7816, + * UART1_TL7816 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_Write7816TransmitLengthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_Write7816TransmitLengthReg(PeripheralBase, Value) ( \ + UART_TL7816_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCea7091bMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the CEA709.1-B feature. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of transmitter clear-to-send operation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_EnableCea7091bMode(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableCea7091bMode(PeripheralBase, State) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_EN709_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C6_EN709_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SendCea7091bPacket + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts CEA709.1-B transmission. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_SendCea7091bPacket(_BASE_PTR); + * @endcode + */ +#define UART_PDD_SendCea7091bPacket(PeripheralBase) ( \ + UART_C6_REG(PeripheralBase) |= \ + UART_C6_TX709_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- IsCea7091bTransmittingPacket + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns if transmission CEA709.1-B packet is active. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * uint8 result = + * UART_PDD_IsCea7091bTransmittingPacket(_BASE_PTR); + * @endcode + */ +#define UART_PDD_IsCea7091bTransmittingPacket(PeripheralBase) ( \ + (uint8)(UART_C6_REG(PeripheralBase) & UART_C6_TX709_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCea7091bCollision + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables the collision detect functionality. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of collision detect functionality. This + * parameter is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_EnableCea7091bCollision(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableCea7091bCollision(PeripheralBase, State) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_CE_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C6_CE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bCollisionSignalPolarity + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the collision polarity. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Polarity Collision polarity. This parameter is of "Collision polarity + * constants" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_SetCea7091bCollisionSignalPolarity(_BASE_PTR, + * UART_PDD_CEA7091b_COLLISION_SIGNAL_LOW); + * @endcode + */ +#define UART_PDD_SetCea7091bCollisionSignalPolarity(PeripheralBase, Polarity) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C6_REG(PeripheralBase) & (uint8)(~(uint8)UART_C6_CP_MASK))) | ( \ + (uint8)(Polarity))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bControlReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bControlReg(PeripheralBase) ( \ + UART_C6_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B control + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C6. + * @par Example: + * @code + * UART_PDD_WriteCea7091bControlReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bControlReg(PeripheralBase, Value) ( \ + UART_C6_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bPacketCycleTimeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets EA709.1-B packet cycle time counter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value EA709.1-B packet cycle time counter value[0..65535]. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTL, UART0_PCTH + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetCea7091bPacketCycleTimeCounter(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetCea7091bPacketCycleTimeCounter(PeripheralBase, Value) ( \ + (UART_PCTL_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (UART_PCTH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bPacketCycleTimeCounter + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns EA709.1-B packet cycle time counter value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: UART0_PCTH, UART0_PCTL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * UART_PDD_GetCea7091bPacketCycleTimeCounter(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bPacketCycleTimeCounter(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)UART_PCTH_REG(PeripheralBase) << 8U)) | ( \ + (uint16)UART_PCTL_REG(PeripheralBase))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPacketCycleTimeCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B packet cycle time counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PCTH. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPacketCycleTimeCounterHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPacketCycleTimeCounterHighReg(PeripheralBase) ( \ + UART_PCTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPacketCycleTimeCounterHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B packet + * cycle time counter high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B packet cycle time counter + * high register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTH. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPacketCycleTimeCounterHighReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPacketCycleTimeCounterHighReg(PeripheralBase, Value) ( \ + UART_PCTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPacketCycleTimeCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B packet cycle time counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PCTL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPacketCycleTimeCounterLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPacketCycleTimeCounterLowReg(PeripheralBase) ( \ + UART_PCTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPacketCycleTimeCounterLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B packet + * cycle time counter low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B packet cycle time counter + * low register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PCTL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPacketCycleTimeCounterLowReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPacketCycleTimeCounterLowReg(PeripheralBase, Value) ( \ + UART_PCTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetCea7091bSecondaryDelayTimer + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets EA709.1-B secondary delay timer. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value EA709.1-B secondary delay timer value[0..65535]. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTL, UART0_SDTH + * (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_SetCea7091bSecondaryDelayTimer(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_SetCea7091bSecondaryDelayTimer(PeripheralBase, Value) ( \ + (UART_SDTL_REG(PeripheralBase) = \ + (uint8)(Value)), \ + (UART_SDTH_REG(PeripheralBase) = \ + (uint8)((uint16)(Value) >> 8U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bSecondaryDelayTimer + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns EA709.1-B secondary delay timer value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: UART0_SDTH, UART0_SDTL + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * UART_PDD_GetCea7091bSecondaryDelayTimer(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bSecondaryDelayTimer(PeripheralBase) ( \ + (uint16)(( \ + (uint16)((uint16)UART_SDTH_REG(PeripheralBase) << 8U)) | ( \ + (uint16)UART_SDTL_REG(PeripheralBase))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bSecondaryDelayTimerHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B secondary delay timer high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SDTH. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bSecondaryDelayTimerHighReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bSecondaryDelayTimerHighReg(PeripheralBase) ( \ + UART_SDTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bSecondaryDelayTimerHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B secondary + * delay timer high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B secondary delay timer high + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTH. + * @par Example: + * @code + * UART_PDD_WriteCea7091bSecondaryDelayTimerHighReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bSecondaryDelayTimerHighReg(PeripheralBase, Value) ( \ + UART_SDTH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bSecondaryDelayTimerLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B secondary delay timer low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_SDTL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bSecondaryDelayTimerLowReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bSecondaryDelayTimerLowReg(PeripheralBase) ( \ + UART_SDTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bSecondaryDelayTimerLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B secondary + * delay timer low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B secondary delay timer low + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_SDTL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bSecondaryDelayTimerLowReg(_BASE_PTR, + * 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bSecondaryDelayTimerLowReg(PeripheralBase, Value) ( \ + UART_SDTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bPreambleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B preamble register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_PRE. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bPreambleReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bPreambleReg(PeripheralBase) ( \ + UART_PRE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bPreambleReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B preamble + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B preamble register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_PRE. + * @par Example: + * @code + * UART_PDD_WriteCea7091bPreambleReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bPreambleReg(PeripheralBase, Value) ( \ + UART_PRE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bTxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B transmit packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_TPL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bTxPacketLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bTxPacketLengthReg(PeripheralBase) ( \ + UART_TPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bTxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B transmit + * packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B transmit packet length + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_TPL. + * @par Example: + * @code + * UART_PDD_WriteCea7091bTxPacketLengthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bTxPacketLengthReg(PeripheralBase, Value) ( \ + UART_TPL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_IE. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bInterruptEnableReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bInterruptEnableReg(PeripheralBase) ( \ + UART_IE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bInterruptEnableReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B interrupt + * enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B interrupt enable register. + * This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_IE. + * @par Example: + * @code + * UART_PDD_WriteCea7091bInterruptEnableReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bInterruptEnableReg(PeripheralBase, Value) ( \ + UART_IE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bWBaseReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B WBase register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_WB. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bWBaseReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bWBaseReg(PeripheralBase) ( \ + UART_WB_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bWBaseReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B WBase + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B WBase register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_WB. + * @par Example: + * @code + * UART_PDD_WriteCea7091bWBaseReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bWBaseReg(PeripheralBase, Value) ( \ + UART_WB_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bStatusReg0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the CEA709.1-B status register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "CEA709.1-B interrupt masks constant" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bStatusReg0(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bStatusReg0(PeripheralBase) ( \ + UART_S3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCea7091bInterruptFlags0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CEA709.1-B interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "CEA709.1-B interrupt masks constant". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * UART_PDD_ClearCea7091bInterruptFlags0(_BASE_PTR, + * UART_PDD_CEA7091B_PREAMBLE_ERROR_FLAG); + * @endcode + */ +#define UART_PDD_ClearCea7091bInterruptFlags0(PeripheralBase, Mask) ( \ + UART_S3_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bStatusReg0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B status + * register 0. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B status register 0. This + * parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S3. + * @par Example: + * @code + * uint8 result = + * UART_PDD_WriteCea7091bStatusReg0(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bStatusReg0(PeripheralBase, Value) ( \ + UART_S3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bStatusReg1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the CEA709.1-B status register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "CEA709.1-B interrupt masks constant" for + * processing return value. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = UART_PDD_ReadCea7091bStatusReg1(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bStatusReg1(PeripheralBase) ( \ + UART_S4_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCea7091bInterruptFlags1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears CEA709.1-B interrupt flags of interrupts specified by Mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of interrupt clear requests. Use constants from group + * "CEA709.1-B interrupt masks constant". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * UART_PDD_ClearCea7091bInterruptFlags1(_BASE_PTR, + * UART_PDD_CEA7091B_COLLISION_DETECTED_FLAG); + * @endcode + */ +#define UART_PDD_ClearCea7091bInterruptFlags1(PeripheralBase, Mask) ( \ + UART_S4_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCea7091bCollisionStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CEA709.1-B collision status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "CEA709.1-B collision status constants." type. The + * value is cast to "uint8". + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = + * UART_PDD_GetCea7091bCollisionStatus(_BASE_PTR); + * @endcode + */ +#define UART_PDD_GetCea7091bCollisionStatus(PeripheralBase) ( \ + (uint8)(UART_S4_REG(PeripheralBase) & UART_S4_CDET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bStatusReg1 + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B status + * register 1. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B status register 1. This + * parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S4. + * @par Example: + * @code + * uint8 result = + * UART_PDD_WriteCea7091bStatusReg1(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bStatusReg1(PeripheralBase, Value) ( \ + UART_S4_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bRxPacketLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B received packet length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RPL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bRxPacketLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bRxPacketLengthReg(PeripheralBase) ( \ + UART_RPL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bRxPreambleLengthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B received preamble length register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_RPREL. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bRxPreambleLengthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bRxPreambleLengthReg(PeripheralBase) ( \ + UART_RPREL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadCea7091bCollisionPulseWidthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads CEA709.1-B collision pulse width register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_CPW. + * @par Example: + * @code + * uint8 result = + * UART_PDD_ReadCea7091bCollisionPulseWidthReg(_BASE_PTR); + * @endcode + */ +#define UART_PDD_ReadCea7091bCollisionPulseWidthReg(PeripheralBase) ( \ + UART_CPW_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteCea7091bCollisionPulseWidthReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into CEA709.1-B collision + * pulse width register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the CEA709.1-B collision pulse width + * register. This parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_CPW. + * @par Example: + * @code + * UART_PDD_WriteCea7091bCollisionPulseWidthReg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteCea7091bCollisionPulseWidthReg(PeripheralBase, Value) ( \ + UART_CPW_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetStopBitLength + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the number of stop bits. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Length Stop bit length. This parameter is of "Stop bit lengths" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_BDH, UART1_BDH, + * UART2_BDH, UART3_BDH, UART4_BDH, UART5_BDH (depending on the + * peripheral). + * @par Example: + * @code + * UART_PDD_SetStopBitLength(_BASE_PTR, + * UART_PDD_STOP_BIT_LEN_1); + * @endcode + */ +#define UART_PDD_SetStopBitLength(PeripheralBase, Length) ( \ + UART_BDH_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_BDH_REG(PeripheralBase) & (uint8)(~(uint8)UART_BDH_SBNS_MASK))) | ( \ + (uint8)(Length))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLinBreakDetectDma + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables a LIN break detect DMA request. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of LIN break detect DMA request. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_C5, UART1_C5, + * UART2_C5, UART3_C5, UART4_C5, UART5_C5 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_EnableLinBreakDetectDma(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define UART_PDD_EnableLinBreakDetectDma(PeripheralBase, State) ( \ + UART_C5_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(UART_C5_REG(PeripheralBase) & (uint8)(~(uint8)UART_C5_LBKDDMAS_MASK))) | ( \ + (uint8)((uint8)(State) << UART_C5_LBKDDMAS_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the interrupt status flags specified by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Mask of the flags to be cleared. This parameter is a 8-bit value. + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = UART_PDD_ClearInterruptFlags(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_ClearInterruptFlags(PeripheralBase, Mask) ( \ + UART_S1_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatus1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status 1 + * register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status 1 register. This parameter is + * a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: UART0_S1, UART1_S1, + * UART2_S1 (depending on the peripheral). + * @par Example: + * @code + * UART_PDD_WriteStatus1Reg(_BASE_PTR, 1); + * @endcode + */ +#define UART_PDD_WriteStatus1Reg(PeripheralBase, Value) ( \ + UART_S1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(UART_PDD_H_) */ + +/* UART_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h new file mode 100644 index 0000000..0b4152f --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USBDCD_PDD.h @@ -0,0 +1,816 @@ +/* + PDD layer implementation for peripheral type USBDCD + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(USBDCD_PDD_H_) +#define USBDCD_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error USBDCD PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK20D10) /* USBDCD */ && \ + !defined(MCU_MK20D5) /* USBDCD */ && \ + !defined(MCU_MK20D7) /* USBDCD */ && \ + !defined(MCU_MK20F12) /* USBDCD */ && \ + !defined(MCU_MK20DZ10) /* USBDCD */ && \ + !defined(MCU_MK21D5) /* USBDCD */ && \ + !defined(MCU_MK21D5WS) /* USBDCD */ && \ + !defined(MCU_MK21F12) /* USBDCD */ && \ + !defined(MCU_MK21F12WS) /* USBDCD */ && \ + !defined(MCU_MK22D5) /* USBDCD */ && \ + !defined(MCU_MK22F12) /* USBDCD */ && \ + !defined(MCU_MK24F12) /* USBDCD */ && \ + !defined(MCU_MK40D10) /* USBDCD */ && \ + !defined(MCU_MK40D7) /* USBDCD */ && \ + !defined(MCU_MK40DZ10) /* USBDCD */ && \ + !defined(MCU_MK40X256VMD100) /* USBDCD */ && \ + !defined(MCU_MK50D10) /* USBDCD */ && \ + !defined(MCU_MK50D7) /* USBDCD */ && \ + !defined(MCU_MK50DZ10) /* USBDCD */ && \ + !defined(MCU_MK51D10) /* USBDCD */ && \ + !defined(MCU_MK51D7) /* USBDCD */ && \ + !defined(MCU_MK51DZ10) /* USBDCD */ && \ + !defined(MCU_MK52D10) /* USBDCD */ && \ + !defined(MCU_MK52DZ10) /* USBDCD */ && \ + !defined(MCU_MK53D10) /* USBDCD */ && \ + !defined(MCU_MK53DZ10) /* USBDCD */ && \ + !defined(MCU_MK60D10) /* USBDCD */ && \ + !defined(MCU_MK60F12) /* USBDCD */ && \ + !defined(MCU_MK60F15) /* USBDCD */ && \ + !defined(MCU_MK60DZ10) /* USBDCD */ && \ + !defined(MCU_MK60N512VMD100) /* USBDCD */ && \ + !defined(MCU_MK61F12) /* USBDCD */ && \ + !defined(MCU_MK61F15) /* USBDCD */ && \ + !defined(MCU_MK61F12WS) /* USBDCD */ && \ + !defined(MCU_MK61F15WS) /* USBDCD */ && \ + !defined(MCU_MK63F12) /* USBDCD */ && \ + !defined(MCU_MK63F12WS) /* USBDCD */ && \ + !defined(MCU_MK64F12) /* USBDCD */ && \ + !defined(MCU_MK65F18) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK65F18WS) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK66F18) /* USBDCD, USBHSDCD */ && \ + !defined(MCU_MK70F12) /* USBDCD */ && \ + !defined(MCU_MK70F15) /* USBDCD */ && \ + !defined(MCU_MK70F12WS) /* USBDCD */ && \ + !defined(MCU_MK70F15WS) /* USBDCD */ && \ + !defined(MCU_MKW22D5) /* USBDCD */ && \ + !defined(MCU_MKW22D5WS) /* USBDCD */ && \ + !defined(MCU_MKW24D5) /* USBDCD */ && \ + !defined(MCU_MKW24D5WS) /* USBDCD */ && \ + !defined(MCU_PCK20L4) /* USBDCD */ + // Unsupported MCU is active + #error USBDCD PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Status flags constants (for ReadStatusReg macro). */ +#define USBDCD_PDD_ACTIVE_STATUS_INDICATOR USBDCD_STATUS_ACTIVE_MASK /**< Active status indicator - indicates whether the sequence is running */ +#define USBDCD_PDD_TIMEOUT_FLAG USBDCD_STATUS_TO_MASK /**< Timeout flag */ +#define USBDCD_PDD_ERROR_FLAG USBDCD_STATUS_ERR_MASK /**< Error flag */ + +/* Receiver status bits constants */ +#define USBDCD_PDD_DATA_PIN_NOT_DETECTED 0U /**< The module is either not enabled, or the module is enabled but the data pins have not yet been detected */ +#define USBDCD_PDD_DATA_PIN_CONTACT_COMPLETE 0x40000U /**< Data pin contact detection complete */ +#define USBDCD_PDD_CHARGER_PORT_COMPLETE 0x80000U /**< Charger port detection complete */ +#define USBDCD_PDD_CHARGER_TYPE_COMPLETE 0xC0000U /**< Charger type detection complete */ + +/* Receiver status bits constants */ +#define USBDCD_PDD_NO_RESULTS_REPORTED 0U /**< No results to report */ +#define USBDCD_PDD_ATTACHED_TO_HOST 0x10000U /**< Attached to a standard host */ +#define USBDCD_PDD_ATTACHED_TO_CHARGING_PORT 0x20000U /**< Attached to a charging port */ +#define USBDCD_PDD_ATTACHED_TO_DEDICATED_CHARGER 0x30000U /**< Attached to a dedicated charger. */ + + +/* ---------------------------------------------------------------------------- + -- PerformSoftwareReset + ---------------------------------------------------------------------------- */ + +/** + * @brief Perform a software reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_PerformSoftwareReset(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_PerformSoftwareReset(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_SR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- StartChangeDetectionSequence + ---------------------------------------------------------------------------- */ + +/** + * @brief Initiate the charger detection sequence. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_StartChangeDetectionSequence(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_StartChangeDetectionSequence(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_START_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts to the system. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_EnableInterrupt(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_IE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disable interrupts to the system. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_DisableInterrupt(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) &= \ + (uint32)(~(uint32)USBDCD_CONTROL_IE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Gets the status of the interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint32)(USBDCD_CONTROL_REG(PeripheralBase) & USBDCD_CONTROL_IF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ClearInterruptFlag(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) |= \ + USBDCD_CONTROL_IACK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadControlReg(PeripheralBase) ( \ + USBDCD_CONTROL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the control register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CONTROL, + * USBHSDCD_CONTROL (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteControlReg(PeripheralBase, Value) ( \ + USBDCD_CONTROL_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSpeedInKhz + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the numerical value of clock speed in kHz. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Clock speed in kHz, value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetClockSpeedInKhz(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetClockSpeedInKhz(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_CLOCK_REG(PeripheralBase)) & (( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_SPEED_MASK)) & ( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_UNIT_MASK))))) | ( \ + (uint32)((uint32)(Value) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetClockSpeedInMhz + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the numerical value of clock speed in MHz. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Clock speed in MHz, value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetClockSpeedInMhz(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetClockSpeedInMhz(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_CLOCK_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_CLOCK_CLOCK_SPEED_MASK)))) | (( \ + (uint32)((uint32)(Value) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) | ( \ + USBDCD_CLOCK_CLOCK_UNIT_MASK))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadClockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads clock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadClockReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadClockReg(PeripheralBase) ( \ + USBDCD_CLOCK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteClockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into clock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the clock register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_CLOCK, + * USBHSDCD_CLOCK (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteClockReg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteClockReg(PeripheralBase, Value) ( \ + USBDCD_CLOCK_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStatusFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_GetStatusFlags(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetStatusFlags(PeripheralBase) ( \ + USBDCD_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChargerDetectionSequenceStatus + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns charger detection sequence status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receiver status bits constants" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * USBDCD_PDD_GetChargerDetectionSequenceStatus(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetChargerDetectionSequenceStatus(PeripheralBase) ( \ + (uint32)(USBDCD_STATUS_REG(PeripheralBase) & USBDCD_STATUS_SEQ_STAT_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetChargerDetectionSequenceResults + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns charger detection sequence status. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Receiver status bits constants" type. The value + * is cast to "uint32". + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = + * USBDCD_PDD_GetChargerDetectionSequenceResults(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetChargerDetectionSequenceResults(PeripheralBase) ( \ + (uint32)(USBDCD_STATUS_REG(PeripheralBase) & USBDCD_STATUS_SEQ_RES_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Status flags constants (for ReadStatusReg + * macro)." for processing return value. + * @remarks The macro accesses the following registers: USBDCD_STATUS, + * USBHSDCD_STATUS (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadStatusReg(PeripheralBase) ( \ + USBDCD_STATUS_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSequenceInitiationTime + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the system latency (in ms). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Time System latency (in ms) value[0..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetSequenceInitiationTime(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetSequenceInitiationTime(PeripheralBase, Time) ( \ + USBDCD_TIMER0_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER0_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER0_TSEQ_INIT_MASK)))) | ( \ + (uint32)((uint32)(Time) << USBDCD_TIMER0_TSEQ_INIT_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUnitConnectionTimerElapse + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns unit connection timer elapse value (in ms). + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 12-bit value. The value is cast to "uint16". + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * uint16 result = + * USBDCD_PDD_GetUnitConnectionTimerElapse(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_GetUnitConnectionTimerElapse(PeripheralBase) ( \ + (uint16)(USBDCD_TIMER0_REG(PeripheralBase) & USBDCD_TIMER0_TUNITCON_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer0Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer0Reg(PeripheralBase) ( \ + USBDCD_TIMER0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer0Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 0 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 0 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER0, + * USBHSDCD_TIMER0 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteTimer0Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer0Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER0_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodToDebounceDpSignal + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) to debounce the D+ signal during the data + * pin contact detection phase. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodToDebounceDpSignal(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodToDebounceDpSignal(PeripheralBase, Period) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER1_TDCD_DBNC_MASK)))) | ( \ + (uint32)((uint32)(Period) << USBDCD_TIMER1_TDCD_DBNC_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodComparator + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) comparator enabled. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodComparator(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodComparator(PeripheralBase, Period) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER1_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER1_TVDPSRC_ON_MASK)))) | ( \ + (uint32)(Period))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer1Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer1Reg(PeripheralBase) ( \ + USBDCD_TIMER1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 1 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER1, + * USBHSDCD_TIMER1 (depending on the peripheral). + * @par Example: + * @code + * USBDCD_PDD_WriteTimer1Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer1Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER1_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimePeriodBeforeEnablingDpPullup + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) before enabling D+ pullup. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Period Time period (in ms) value[1..1023]. This parameter is a 10-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_SetTimePeriodBeforeEnablingDpPullup(_BASE_PTR, + * 1); + * @endcode + */ +#define USBDCD_PDD_SetTimePeriodBeforeEnablingDpPullup(PeripheralBase, Period) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER2_TVDPSRC_CON_MASK)))) | ( \ + (uint32)((uint32)(Period) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTimeBeforeCheckDmLine + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets the time period (ms) before check D- line. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Time (in ms) value[1..15]. This parameter is a 4-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_SetTimeBeforeCheckDmLine(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_SetTimeBeforeCheckDmLine(PeripheralBase, Value) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(( \ + (uint32)(( \ + USBDCD_TIMER2_REG(PeripheralBase)) & ( \ + (uint32)(~(uint32)USBDCD_TIMER2_CHECK_DM_MASK)))) | ( \ + (uint32)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimer2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads timer 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * uint32 result = USBDCD_PDD_ReadTimer2Reg(_BASE_PTR); + * @endcode + */ +#define USBDCD_PDD_ReadTimer2Reg(PeripheralBase) ( \ + USBDCD_TIMER2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimer2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter into timer 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the timer 2 register. This parameter is a + * 32-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USBDCD_TIMER2. + * @par Example: + * @code + * USBDCD_PDD_WriteTimer2Reg(_BASE_PTR, 1); + * @endcode + */ +#define USBDCD_PDD_WriteTimer2Reg(PeripheralBase, Value) ( \ + USBDCD_TIMER2_REG(PeripheralBase) = \ + (uint32)(Value) \ + ) +#endif /* #if defined(USBDCD_PDD_H_) */ + +/* USBDCD_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h new file mode 100644 index 0000000..d68f514 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/USB_PDD.h @@ -0,0 +1,4849 @@ +/* + PDD layer implementation for peripheral type USB + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(USB_PDD_H_) +#define USB_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error USB PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK20D10) /* USB0 */ && \ + !defined(MCU_MK20D5) /* USB0 */ && \ + !defined(MCU_MK20D7) /* USB0 */ && \ + !defined(MCU_MK20F12) /* USB0 */ && \ + !defined(MCU_MK20DZ10) /* USB0 */ && \ + !defined(MCU_MK21D5) /* USB0 */ && \ + !defined(MCU_MK21D5WS) /* USB0 */ && \ + !defined(MCU_MK21F12) /* USB0 */ && \ + !defined(MCU_MK21F12WS) /* USB0 */ && \ + !defined(MCU_MK22D5) /* USB0 */ && \ + !defined(MCU_MK22F12810) /* USB0 */ && \ + !defined(MCU_MK22F12) /* USB0 */ && \ + !defined(MCU_MK22F25612) /* USB0 */ && \ + !defined(MCU_MK22F51212) /* USB0 */ && \ + !defined(MCU_MK24F12) /* USB0 */ && \ + !defined(MCU_MK40D10) /* USB0 */ && \ + !defined(MCU_MK40D7) /* USB0 */ && \ + !defined(MCU_MK40DZ10) /* USB0 */ && \ + !defined(MCU_MK40X256VMD100) /* USB0 */ && \ + !defined(MCU_MK50D10) /* USB0 */ && \ + !defined(MCU_MK50D7) /* USB0 */ && \ + !defined(MCU_MK50DZ10) /* USB0 */ && \ + !defined(MCU_MK51D10) /* USB0 */ && \ + !defined(MCU_MK51D7) /* USB0 */ && \ + !defined(MCU_MK51DZ10) /* USB0 */ && \ + !defined(MCU_MK52D10) /* USB0 */ && \ + !defined(MCU_MK52DZ10) /* USB0 */ && \ + !defined(MCU_MK53D10) /* USB0 */ && \ + !defined(MCU_MK53DZ10) /* USB0 */ && \ + !defined(MCU_MK60D10) /* USB0 */ && \ + !defined(MCU_MK60F12) /* USB0 */ && \ + !defined(MCU_MK60F15) /* USB0 */ && \ + !defined(MCU_MK60DZ10) /* USB0 */ && \ + !defined(MCU_MK60N512VMD100) /* USB0 */ && \ + !defined(MCU_MK61F12) /* USB0 */ && \ + !defined(MCU_MK61F15) /* USB0 */ && \ + !defined(MCU_MK61F12WS) /* USB0 */ && \ + !defined(MCU_MK61F15WS) /* USB0 */ && \ + !defined(MCU_MK63F12) /* USB0 */ && \ + !defined(MCU_MK63F12WS) /* USB0 */ && \ + !defined(MCU_MK64F12) /* USB0 */ && \ + !defined(MCU_MK65F18) /* USB0 */ && \ + !defined(MCU_MK65F18WS) /* USB0 */ && \ + !defined(MCU_MK66F18) /* USB0 */ && \ + !defined(MCU_MK70F12) /* USB0 */ && \ + !defined(MCU_MK70F15) /* USB0 */ && \ + !defined(MCU_MK70F12WS) /* USB0 */ && \ + !defined(MCU_MK70F15WS) /* USB0 */ && \ + !defined(MCU_MKL24Z4) /* USB0 */ && \ + !defined(MCU_MKL25Z4) /* USB0 */ && \ + !defined(MCU_MKL26Z4) /* USB0 */ && \ + !defined(MCU_MKL46Z4) /* USB0 */ && \ + !defined(MCU_MKW22D5) /* USB0 */ && \ + !defined(MCU_MKW22D5WS) /* USB0 */ && \ + !defined(MCU_MKW24D5) /* USB0 */ && \ + !defined(MCU_MKW24D5WS) /* USB0 */ && \ + !defined(MCU_PCK20L4) /* USB0 */ + // Unsupported MCU is active + #error USB PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Otg interrupt masks */ +#define USB_PDD_A_VBUS_CHG_INT USB_OTGICR_AVBUSEN_MASK /**< Vbus change interrupt mask */ +#define USB_PDD_B_SESS_CHG_INT USB_OTGICR_BSESSEN_MASK /**< B session change interrupt mask */ +#define USB_PDD_SESS_VLD_CHG_INT USB_OTGICR_SESSVLDEN_MASK /**< Session valid change interrupt mask */ +#define USB_PDD_LINE_STATE_CHG_INT USB_OTGICR_LINESTATEEN_MASK /**< Line state change interrupt mask */ +#define USB_PDD_1_MSEC_INT USB_OTGICR_ONEMSECEN_MASK /**< 1 ms interrupt mask */ +#define USB_PDD_ID_CHG_INT USB_OTGICR_IDEN_MASK /**< ID change interrupt mask */ + +/* Otg interrupt masks */ +#define USB_PDD_ALL_INT_FLAGS 0xFFU /**< Value used to mask all Otg interrupts */ + +/* Otg status masks */ +#define USB_PDD_A_VBUS_VALID USB_OTGSTAT_AVBUSVLD_MASK /**< A VBus valid signal mask */ +#define USB_PDD_B_SESSION_END USB_OTGSTAT_BSESSEND_MASK /**< B session end signal mask */ +#define USB_PDD_SESSION_VALID USB_OTGSTAT_SESS_VLD_MASK /**< Session valid signal mask */ +#define USB_PDD_LINE_STABLE USB_OTGSTAT_LINESTATESTABLE_MASK /**< Line stable signal mask */ +#define USB_PDD_ID USB_OTGSTAT_ID_MASK /**< ID signal mask */ + +/* Usb interrupt masks */ +#define USB_PDD_STALL_INT USB_INTEN_STALLEN_MASK /**< Stall interrupt mask */ +#define USB_PDD_ATTACH_INT USB_INTEN_ATTACHEN_MASK /**< Attach interrupt mask */ +#define USB_PDD_RESUME_INT USB_INTEN_RESUMEEN_MASK /**< Resume interrupt mask */ +#define USB_PDD_SLEEP_INT USB_INTEN_SLEEPEN_MASK /**< Sleed interrupt mask */ +#define USB_PDD_TOK_DNE_INT USB_INTEN_TOKDNEEN_MASK /**< Token done interrupt mask */ +#define USB_PDD_SOF_TOK_INT USB_INTEN_SOFTOKEN_MASK /**< Star of frame interrupt mask */ +#define USB_PDD_ERROR_INT USB_INTEN_ERROREN_MASK /**< Error interrupt mask */ +#define USB_PDD_USB_RST_INT USB_INTEN_USBRSTEN_MASK /**< Bus reset interrupt mask */ + +/* Error interrupt masks */ +#define USB_PDD_BTS_ERR_INT USB_ERREN_BTSERREN_MASK /**< BTS error interrupt mask */ +#define USB_PDD_DMA_ERR_INT USB_ERREN_DMAERREN_MASK /**< DNA error interrupt mask */ +#define USB_PDD_BTO_ERR_INT USB_ERREN_BTOERREN_MASK /**< BTO errot interrupt mask */ +#define USB_PDD_DFN8_INT USB_ERREN_DFN8EN_MASK /**< DFN8 error interrupt mask */ +#define USB_PDD_CRC16_INT USB_ERREN_CRC16EN_MASK /**< CRC16 interrupt mask */ +#define USB_PDD_CRC5_EOF_INT USB_ERREN_CRC5EOFEN_MASK /**< CRC5 or EOF error interrupt mask */ +#define USB_PDD_PID_ERR_INT USB_ERREN_PIDERREN_MASK /**< PID error interrupt mask */ + +/* Conrol register masks */ +#define USB_PDD_JSTATE USB_CTL_JSTATE_MASK /**< J state mask */ +#define USB_PDD_SE0 USB_CTL_SE0_MASK /**< SE0 mask */ + +/* Otg output signal masks */ +#define USB_PDD_DP_PU_SIGNAL USB_OBSERVE_DPPU_MASK /**< D+ pull-up signal mask */ +#define USB_PDD_DP_PD_SIGNAL USB_OBSERVE_DPPD_MASK /**< D+ pull-down signal mask */ +#define USB_PDD_DM_PD_SIGNAL USB_OBSERVE_DMPD_MASK /**< D- pull-down signal mask */ + +/* Otg input signal masks */ +#define USB_PDD_DEVICE_VBUS_DETECT_SIGNAL USB_CONTROL_DPPULLUPNONOTG_MASK /**< Device mode Vbus detect signal mask */ + +/* Bus speed */ +#define USB_PDD_LOW_SPEED 0U /**< Low speed constant */ +#define USB_PDD_FULL_SPEED 0x80U /**< Full speed constant */ +#define USB_PDD_RESET 0x40U /**< Bus reset state constant */ + + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralIdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral ID register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_PERID. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadPeripheralIdReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralIdReg(PeripheralBase) ( \ + USB_PERID_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralIdComplementReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral ID complement register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_IDCOMP. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadPeripheralIdComplementReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralIdComplementReg(PeripheralBase) ( \ + USB_IDCOMP_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPeripheralRevisionReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads peripheral revision register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_REV. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadPeripheralRevisionReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadPeripheralRevisionReg(PeripheralBase) ( \ + USB_REV_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAdditionalInfoReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads additional info register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ADDINFO. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadAdditionalInfoReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadAdditionalInfoReg(PeripheralBase) ( \ + USB_ADDINFO_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOtgInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetOtgInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetOtgInterruptFlags(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearOtgInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Otg interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearOtgInterruptFlags(_BASE_PTR, + * USB_PDD_A_VBUS_CHG_INT); + * @endcode + */ +#define USB_PDD_ClearOtgInterruptFlags(PeripheralBase, Mask) ( \ + USB_OTGISTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetIdChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ID changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetIdChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetIdChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_IDCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- Get1msInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the 1 ms interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_Get1msInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Get1msInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_ONEMSEC_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLineStateChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line state change flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetLineStateChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetLineStateChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_LINE_STATE_CHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Session valalid changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetSessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSessVldChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_SESSVLDCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBsessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the B session end changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetBsessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBsessVldChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_B_SESS_CHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAVbusChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the A Vbus changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetAVbusChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetAVbusChgInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_OTGISTAT_REG(PeripheralBase) & USB_OTGISTAT_AVBUSCHG_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearIdChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the ID changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearIdChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearIdChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_IDCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- Clear1msInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the 1 ms flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_Clear1msInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Clear1msInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_ONEMSEC_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearLineStateChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Line state changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearLineStateChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearLineStateChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_LINE_STATE_CHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Session valid changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearSessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSessVldChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_SESSVLDCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBsessVldChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the B session end changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearBsessVldChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBsessVldChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_B_SESS_CHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAVbusChgInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the A Vbus changed flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGISTAT. + * @par Example: + * @code + * USB_PDD_ClearAVbusChgInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearAVbusChgInterruptFlag(PeripheralBase) ( \ + USB_OTGISTAT_REG(PeripheralBase) |= \ + USB_OTGISTAT_AVBUSCHG_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetOtgInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * uint8 result = USB_PDD_GetOtgInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetOtgInterruptMask(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetOtgInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Otg interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_SetOtgInterruptMask(_BASE_PTR, + * USB_PDD_A_VBUS_CHG_INT); + * @endcode + */ +#define USB_PDD_SetOtgInterruptMask(PeripheralBase, Mask) ( \ + USB_OTGICR_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIdChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the ID changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableIdChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableIdChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_IDEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- Enable1msInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the 1 ms interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_Enable1msInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Enable1msInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_ONEMSECEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLineStateChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Line stable interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableLineStateChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableLineStateChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_LINESTATEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Session valid changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableSessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_SESSVLDEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBsessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the B session end changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableBsessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBsessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_BSESSEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAVbusChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the A Vbus changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_EnableAVbusChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableAVbusChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) |= \ + USB_OTGICR_AVBUSEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableIdChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the ID changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableIdChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableIdChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_IDEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- Disable1msInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the 1 ms interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_Disable1msInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_Disable1msInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_ONEMSECEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableLineStateChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Line state changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableLineStateChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableLineStateChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_LINESTATEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Session valid changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableSessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_SESSVLDEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBsessVldChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the B session end changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableBsessVldChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBsessVldChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_BSESSEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAVbusChgInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the A Vbus changed interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGICR. + * @par Example: + * @code + * USB_PDD_DisableAVbusChgInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableAVbusChgInterrupt(PeripheralBase) ( \ + USB_OTGICR_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_OTGICR_AVBUSEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Otg status masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgStatusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgStatusReg(PeripheralBase) ( \ + USB_OTGSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- BDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the ID bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_BDevice(_BASE_PTR); + * @endcode + */ +#define USB_PDD_BDevice(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_ID_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- LineStateStable + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line stable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_LineStateStable(_BASE_PTR); + * @endcode + */ +#define USB_PDD_LineStateStable(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_LINESTATESTABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SessionValid + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Session valid bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_SessionValid(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SessionValid(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_SESS_VLD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- BSessionEnd + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the B session end bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_BSessionEnd(_BASE_PTR); + * @endcode + */ +#define USB_PDD_BSessionEnd(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_BSESSEND_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- AVBusValid + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the A Vbus valid bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_AVBusValid(_BASE_PTR); + * @endcode + */ +#define USB_PDD_AVBusValid(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_AVBUSVLD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgStstusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgStstusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgStstusReg(PeripheralBase) ( \ + USB_OTGSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetLineStateStableState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the Line stable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetLineStateStableState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetLineStateStableState(PeripheralBase) ( \ + (uint8)(USB_OTGSTAT_REG(PeripheralBase) & USB_OTGSTAT_LINESTATESTABLE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgControlReg(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_WriteOtgControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgControlReg(PeripheralBase, Value) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDpPullUp + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D+ pull up. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDpPullUp(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDpPullUp(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DPHIGH_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DPHIGH_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDpPullDown + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D+ pull down. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDpPullDown(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDpPullDown(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DPLOW_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DPLOW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmPullDown + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables D- pull up. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDmPullDown(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDmPullDown(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_DMLOW_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_DMLOW_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVBUS + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBUS. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVBUS(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVBUS(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL__MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL__SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableOtgTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables OTG termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableOtgTermination(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableOtgTermination(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_OTGCTL_OTGEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_OTGCTL_OTGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVbusCharge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBus charge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVbusCharge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVbusCharge(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)((uint8)0x1U << 1U)))) | ( \ + (uint8)((uint8)(State) << 1U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableVbusDischarge + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables VBus discharge. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableVbusDischarge(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableVbusDischarge(PeripheralBase, State) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_OTGCTL_REG(PeripheralBase) & (uint8)(~(uint8)0x1U))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeviceModeFullSpeedTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets full speed device termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetDeviceModeFullSpeedTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetDeviceModeFullSpeedTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + USB_OTGCTL_REG(PeripheralBase)) | (( \ + USB_OTGCTL_DPHIGH_MASK) | ( \ + USB_OTGCTL_OTGEN_MASK)))) & (( \ + (uint8)(~(uint8)USB_OTGCTL_DPLOW_MASK)) & ( \ + (uint8)(~(uint8)USB_OTGCTL_DMLOW_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetHostModeTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets full speed host termination. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetHostModeTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetHostModeTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + 0x34U \ + ) + +/* ---------------------------------------------------------------------------- + -- SetNoTermination + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables all pull resistors. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OTGCTL, + * USB0_OTGCTL0 (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_SetNoTermination(_BASE_PTR); + * @endcode + */ +#define USB_PDD_SetNoTermination(PeripheralBase) ( \ + USB_OTGCTL_REG(PeripheralBase) = \ + 0x4U \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUsbInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Usb interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Usb interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetUsbInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetUsbInterruptFlags(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearUsbInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Usb interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearUsbInterruptFlags(_BASE_PTR, + * USB_PDD_STALL_INT); + * @endcode + */ +#define USB_PDD_ClearUsbInterruptFlags(PeripheralBase, Mask) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetStallInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Stall interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetStallInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetStallInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_STALL_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetAttachInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Attach interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetAttachInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetAttachInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_ATTACH_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetResumeInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResumeInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_RESUME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSuspendInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Suspend interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetSuspendInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSuspendInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_SLEEP_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTokenDoneInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Token done interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetTokenDoneInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTokenDoneInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_TOKDNE_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSofInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Sof interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetSofInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSofInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_SOFTOK_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_ERROR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusResetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returnes the Bus reset interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetBusResetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBusResetInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ISTAT_REG(PeripheralBase) & USB_ISTAT_USBRST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearStallInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Stall interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearStallInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearStallInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_STALL_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAttachInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Attach interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearAttachInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearAttachInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_ATTACH_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearResumeInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearResumeInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_RESUME_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSuspendInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Suspend interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearSuspendInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSuspendInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_SLEEP_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTokenDoneInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Token done interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearTokenDoneInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTokenDoneInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_TOKDNE_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearSofInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Sof interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearSofInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearSofInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_SOFTOK_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearErrorInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearErrorInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_ERROR_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBusResetInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the Bus reset interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ISTAT. + * @par Example: + * @code + * USB_PDD_ClearBusResetInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBusResetInterruptFlag(PeripheralBase) ( \ + USB_ISTAT_REG(PeripheralBase) = \ + USB_ISTAT_USBRST_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- GetUsbInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Usb interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Usb interrupt masks" for processing return + * value. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * uint8 result = USB_PDD_GetUsbInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetUsbInterruptMask(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetUsbInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Usb interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_SetUsbInterruptMask(_BASE_PTR, USB_PDD_STALL_INT); + * @endcode + */ +#define USB_PDD_SetUsbInterruptMask(PeripheralBase, Mask) ( \ + USB_INTEN_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableStallInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Stall interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableStallInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableStallInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_STALLEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableAttachInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Attach interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableAttachInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableAttachInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_ATTACHEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableResumeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Reume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableResumeInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableResumeInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_RESUMEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSuspendInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Suspend interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableSuspendInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSuspendInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_SLEEPEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableTokenDoneInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Token done interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableTokenDoneInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableTokenDoneInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_TOKDNEEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSofInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Sof interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableSofInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableSofInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_SOFTOKEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableErrorInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_ERROREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBusResetInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the Bus reset interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_EnableBusResetInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBusResetInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) |= \ + USB_INTEN_USBRSTEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableStallInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Stall interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableStallInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableStallInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_STALLEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableAttachInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Attach interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableAttachInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableAttachInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_ATTACHEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableResumeInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableResumeInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableResumeInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_RESUMEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSuspendInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Suspend interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableSuspendInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSuspendInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_SLEEPEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTokenDoneInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Token done interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableTokenDoneInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableTokenDoneInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_TOKDNEEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableSofInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Sof interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableSofInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableSofInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_SOFTOKEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableErrorInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableErrorInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableErrorInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_ERROREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBusResetInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the Bus reset interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_INTEN. + * @par Example: + * @code + * USB_PDD_DisableBusResetInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBusResetInterrupt(PeripheralBase) ( \ + USB_INTEN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_INTEN_USBRSTEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorsInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Error interrupt status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Error interrupt masks" for processing + * return value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorsInterruptFlags(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorsInterruptFlags(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearErrorsInterruptFlags + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears flags defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Error interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearErrorsInterruptFlags(_BASE_PTR, + * USB_PDD_BTS_ERR_INT); + * @endcode + */ +#define USB_PDD_ClearErrorsInterruptFlags(PeripheralBase, Mask) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBtsErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the BTS error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetBtsErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBtsErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_BTSERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDmaErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DMA error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDmaErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDmaErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_DMAERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBtoErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the BTO error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetBtoErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBtoErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_BTOERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDnf8ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the DNF8 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDnf8ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDnf8ErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_DFN8_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCrc16ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CRC16 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetCrc16ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetCrc16ErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_CRC16_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetCrc5EofErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the CRC5 or EOF error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetCrc5EofErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetCrc5EofErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_CRC5EOF_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetPidErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the PID error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetPidErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetPidErrInterruptFlag(PeripheralBase) ( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) & USB_ERRSTAT_PIDERR_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBtsErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the BTS error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearBtsErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBtsErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_BTSERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDmaErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the DMA error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearDmaErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearDmaErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_DMAERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearBtoErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the BTO error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearBtoErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearBtoErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearDnf8ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the DFN8 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearDnf8ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearDnf8ErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCrc16ErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the CRC16 error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearCrc16ErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearCrc16ErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearCrc5EofErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the CRC5 or EOF error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearCrc5EofErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearCrc5EofErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearPidErrInterruptFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears the PID error interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERRSTAT. + * @par Example: + * @code + * USB_PDD_ClearPidErrInterruptFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearPidErrInterruptFlag(PeripheralBase) ( \ + USB_ERRSTAT_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ERRSTAT_REG(PeripheralBase) | USB_ERRSTAT_PIDERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC5EOF_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_CRC16_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DFN8_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_BTOERR_MASK)) & (( \ + (uint8)(~(uint8)USB_ERRSTAT_DMAERR_MASK)) & ( \ + (uint8)(~(uint8)USB_ERRSTAT_BTSERR_MASK)))))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBtsErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the BTS error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableBtsErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBtsErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_BTSERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDmaErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DMA error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableDmaErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableDmaErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_DMAERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBtoErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the BTO error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableBtoErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableBtoErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_BTOERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDnf8ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the DNF8 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableDnf8ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableDnf8ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_DFN8EN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrc16ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CRC16 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableCrc16ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableCrc16ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_CRC16EN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableCrc5EofErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the CRC5 or EOF error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnableCrc5EofErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnableCrc5EofErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_CRC5EOFEN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- EnablePidErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables the PID error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_EnablePidErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_EnablePidErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) |= \ + USB_ERREN_PIDERREN_MASK \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBtsErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the BTS error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableBtsErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBtsErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_BTSERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDmaErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DMA error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableDmaErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableDmaErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_DMAERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableBtoErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the BTO error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableBtoErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableBtoErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_BTOERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableDnf8ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the DNF8 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableDnf8ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableDnf8ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_DFN8EN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableCrc16ErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CRC16 error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableCrc16ErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableCrc16ErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_CRC16EN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableCrc5EofErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the CRC5 or EOF error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisableCrc5EofErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableCrc5EofErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_CRC5EOFEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisablePidErrInterrupt + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables the PID error interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_DisablePidErrInterrupt(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisablePidErrInterrupt(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_ERREN_PIDERREN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Error interrupt enable register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Use constants from group "Error interrupt masks" for processing + * return value. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * uint8 result = USB_PDD_GetErrorInterruptMask(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetErrorInterruptMask(PeripheralBase) ( \ + USB_ERREN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetErrorInterruptMask + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables interrupts defined by the Mask parameter. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mask Interrupt mask. Use constants from group "Error interrupt masks". + * This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ERREN. + * @par Example: + * @code + * USB_PDD_SetErrorInterruptMask(_BASE_PTR, + * USB_PDD_BTS_ERR_INT); + * @endcode + */ +#define USB_PDD_SetErrorInterruptMask(PeripheralBase, Mask) ( \ + USB_ERREN_REG(PeripheralBase) = \ + (uint8)(Mask) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_STAT. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadStatusReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadStatusReg(PeripheralBase) ( \ + USB_STAT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTransmitIndicator + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the value of the TX bit in the Status register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_STAT. + * @par Example: + * @code + * uint8 result = USB_PDD_GetTransmitIndicator(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTransmitIndicator(PeripheralBase) ( \ + (uint8)(USB_STAT_REG(PeripheralBase) & USB_STAT_TX_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_ReadControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadControlReg(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Control register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_WriteControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteControlReg(PeripheralBase, Value) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetBusSpeed + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns current bus speed. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Bus speed" type. The value is cast to "uint8". + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetBusSpeed(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetBusSpeed(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)((uint8)0x3U << 6U)) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetSE0 + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the SEO signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetSE0(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetSE0(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_SE0_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Device mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDevice(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_USBENSOFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSof + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables SOF. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableSof(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableSof(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_USBENSOFEN_MASK))) | ( \ + (uint8)(State))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetBdtPingPong + ---------------------------------------------------------------------------- */ + +/** + * @brief Resets internal logic. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ResetBdtPingPong(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ResetBdtPingPong(PeripheralBase) ( \ + (USB_CTL_REG(PeripheralBase) |= \ + USB_CTL_ODDRST_MASK), \ + (USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_ODDRST_MASK)) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartResumeSignaling + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts/stops resume signaling. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_StartResumeSignaling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StartResumeSignaling(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_RESUME_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_RESUME_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResumeSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of resume enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetResumeSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResumeSignalState(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_RESUME_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableHost + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Host mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_EnableHost(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableHost(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_HOSTMODEEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_HOSTMODEEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- StartResetSignaling + ---------------------------------------------------------------------------- */ + +/** + * @brief Starts/stops reset signaling. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_StartResetSignaling(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StartResetSignaling(PeripheralBase, State) ( \ + USB_CTL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_CTL_REG(PeripheralBase) & (uint8)(~(uint8)USB_CTL_RESET_MASK))) | ( \ + (uint8)((uint8)(State) << USB_CTL_RESET_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetResetSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of reset enable bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetResetSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetResetSignalState(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_RESET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTxSuspendFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears TxSuspend flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ClearTxSuspendFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTxSuspendFlag(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearTokenBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Clears TokenBusy flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_ClearTokenBusyFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ClearTokenBusyFlag(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTokenBusyFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of TokenBusy flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = USB_PDD_GetTokenBusyFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetTokenBusyFlag(PeripheralBase) ( \ + (uint8)(USB_CTL_REG(PeripheralBase) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableModule + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables module. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CTL, USB0_CTL1 + * (depending on the peripheral). + * @par Example: + * @code + * USB_PDD_DisableModule(_BASE_PTR); + * @endcode + */ +#define USB_PDD_DisableModule(PeripheralBase) ( \ + USB_CTL_REG(PeripheralBase) = \ + 0U \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadAddressReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadAddressReg(PeripheralBase) ( \ + USB_ADDR_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteAddressReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Address register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Address register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_WriteAddressReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteAddressReg(PeripheralBase, Value) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableLowSpeed + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables low speed mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_EnableLowSpeed(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableLowSpeed(PeripheralBase, State) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ADDR_REG(PeripheralBase) & (uint8)(~(uint8)USB_ADDR_LSEN_MASK))) | ( \ + (uint8)((uint8)(State) << USB_ADDR_LSEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetDeviceAddress + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets device address. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Address New device address. This parameter is a 7-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_ADDR. + * @par Example: + * @code + * USB_PDD_SetDeviceAddress(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetDeviceAddress(PeripheralBase, Address) ( \ + USB_ADDR_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_ADDR_REG(PeripheralBase) & (uint8)(~(uint8)USB_ADDR_ADDR_MASK))) | ( \ + (uint8)(Address))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE1. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage1Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage1Reg(PeripheralBase) ( \ + USB_BDTPAGE1_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage1Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 1 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 1 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE1. + * @par Example: + * @code + * USB_PDD_WriteBdtPage1Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage1Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE1_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFrameNumberLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame number low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_FRMNUML. + * @par Example: + * @code + * uint8 result = USB_PDD_GetFrameNumberLow(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetFrameNumberLow(PeripheralBase) ( \ + USB_FRMNUML_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameNumberLow + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Frame number low register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the low part of the Frame number register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_FRMNUML. + * @par Example: + * @code + * USB_PDD_SetFrameNumberLow(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameNumberLow(PeripheralBase, Data) ( \ + USB_FRMNUML_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetFrameNumberHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame number high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_FRMNUMH. + * @par Example: + * @code + * uint8 result = USB_PDD_GetFrameNumberHigh(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetFrameNumberHigh(PeripheralBase) ( \ + USB_FRMNUMH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameNumberHigh + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Frame number high register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the high part of the Frame number register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_FRMNUMH. + * @par Example: + * @code + * USB_PDD_SetFrameNumberHigh(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameNumberHigh(PeripheralBase, Data) ( \ + USB_FRMNUMH_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTokenReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Token register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_TOKEN. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadTokenReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadTokenReg(PeripheralBase) ( \ + USB_TOKEN_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTokenReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Token register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Token register. This parameter is a 8-bit + * value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_TOKEN. + * @par Example: + * @code + * USB_PDD_WriteTokenReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteTokenReg(PeripheralBase, Data) ( \ + USB_TOKEN_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadSofTresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Sof treshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_SOFTHLD. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadSofTresholdReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadSofTresholdReg(PeripheralBase) ( \ + USB_SOFTHLD_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetSofTresholdReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the Sof theshold register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the Sof treshold register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_SOFTHLD. + * @par Example: + * @code + * USB_PDD_SetSofTresholdReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetSofTresholdReg(PeripheralBase, Data) ( \ + USB_SOFTHLD_REG(PeripheralBase) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE2. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage2Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage2Reg(PeripheralBase) ( \ + USB_BDTPAGE2_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage2Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 2 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 2 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE2. + * @par Example: + * @code + * USB_PDD_WriteBdtPage2Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage2Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE2_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadBdtPage3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads BDT page 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_BDTPAGE3. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadBdtPage3Reg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadBdtPage3Reg(PeripheralBase) ( \ + USB_BDTPAGE3_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteBdtPage3Reg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes data specified by the Value parameter BDT page 3 register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the BDT page 3 register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_BDTPAGE3. + * @par Example: + * @code + * USB_PDD_WriteBdtPage3Reg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteBdtPage3Reg(PeripheralBase, Value) ( \ + USB_BDTPAGE3_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadEp0CtrlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the EP0 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadEp0CtrlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadEp0CtrlReg(PeripheralBase) ( \ + USB_ENDPT_REG(PeripheralBase,0U) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteEp0CtrlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Data to the EP0 control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Data Value written to the EP0 control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * USB_PDD_WriteEp0CtrlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteEp0CtrlReg(PeripheralBase, Data) ( \ + USB_ENDPT_REG(PeripheralBase,0U) = \ + (uint8)(Data) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetEpCtrlRegAddr + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the address of the EP_x register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a 32-bit value. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * uint32 result = USB_PDD_GetEpCtrlRegAddr(_BASE_PTR, + * periphID); + * @endcode + */ +#define USB_PDD_GetEpCtrlRegAddr(PeripheralBase, EpNum) ( \ + (uint8 *)(void *)&(USB_ENDPT_REG(PeripheralBase,(EpNum))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableDirectLowSpeedDevice + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables direct low speed device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[]. + * @par Example: + * @code + * USB_PDD_EnableDirectLowSpeedDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableDirectLowSpeedDevice(PeripheralBase, State) ( \ + USB_ENDPT_REG(PeripheralBase,0U) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,0U)) & ( \ + (uint8)(~(uint8)USB_ENDPT_HOSTWOHUB_MASK)))) | ( \ + (uint8)((uint8)(State) << USB_ENDPT_HOSTWOHUB_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- StallControlEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Stall feature for given EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_StallControlEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_StallControlEP(PeripheralBase, EpNum, State) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)))) | ( \ + (uint8)((uint8)(State) << USB_ENDPT_EPSTALL_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableControlEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Control EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableControlEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableControlEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPCTLDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK)))))))) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPCTLDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)))))) | (( \ + USB_ENDPT_EPRXEN_MASK) | (( \ + USB_ENDPT_EPTXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBulkOrIntRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Bulk or Interrupt Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableBulkOrIntRxEP(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableBulkOrIntRxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | (( \ + USB_ENDPT_EPRXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableBulkOrIntTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Bulk or Interrupt Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableBulkOrIntTxEP(_BASE_PTR, periphID, + * PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableBulkOrIntTxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | (( \ + USB_ENDPT_EPTXEN_MASK) | ( \ + USB_ENDPT_EPHSHK_MASK))))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIsoRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Isochronous Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableIsoRxEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableIsoRxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK)))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | ( \ + USB_ENDPT_EPRXEN_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableIsoTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables Isochronous Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_EnableIsoTxEP(_BASE_PTR, periphID, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableIsoTxEP(PeripheralBase, EpNum, State) ( \ + ((State) == PDD_DISABLE) ? ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK)) : ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) = \ + (uint8)(( \ + (uint8)(( \ + USB_ENDPT_REG(PeripheralBase,(EpNum))) & (( \ + (uint8)(~(uint8)USB_ENDPT_HOSTWOHUB_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_RETRYDIS_MASK)) & (( \ + (uint8)(~(uint8)USB_ENDPT_EPSTALL_MASK)) & ( \ + (uint8)(~(uint8)USB_ENDPT_EPHSHK_MASK))))))) | (( \ + USB_ENDPT_EPCTLDIS_MASK) | ( \ + USB_ENDPT_EPTXEN_MASK)))) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableRxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Rx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_DisableRxEP(_BASE_PTR, periphID); + * @endcode + */ +#define USB_PDD_DisableRxEP(PeripheralBase, EpNum) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPRXEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- DisableTxEP + ---------------------------------------------------------------------------- */ + +/** + * @brief Disables Tx EP. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param EpNum Endpoint number. This parameter is of index type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: ENDPT[EpNum]. + * @par Example: + * @code + * USB_PDD_DisableTxEP(_BASE_PTR, periphID); + * @endcode + */ +#define USB_PDD_DisableTxEP(PeripheralBase, EpNum) ( \ + USB_ENDPT_REG(PeripheralBase,(EpNum)) &= \ + (uint8)(~(uint8)USB_ENDPT_EPTXEN_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadUsbControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the USB control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadUsbControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadUsbControlReg(PeripheralBase) ( \ + USB_USBCTRL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteUsbControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Usb control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Usb control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_WriteUsbControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteUsbControlReg(PeripheralBase, Value) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SuspendTransceiver + ---------------------------------------------------------------------------- */ + +/** + * @brief Suspends/Wakes up transceiver. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_SuspendTransceiver(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_SuspendTransceiver(PeripheralBase, State) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_USBCTRL_REG(PeripheralBase) & (uint8)(~(uint8)USB_USBCTRL_SUSP_MASK))) | ( \ + (uint8)((uint8)(State) << USB_USBCTRL_SUSP_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableWeakPullDowns + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables/disables week pull downs. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state. This parameter is of "Global enumeration used + * for specifying general enable/disable states (PDD_DISABLE and PDD_ENABLE + * defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBCTRL. + * @par Example: + * @code + * USB_PDD_EnableWeakPullDowns(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define USB_PDD_EnableWeakPullDowns(PeripheralBase, State) ( \ + USB_USBCTRL_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(USB_USBCTRL_REG(PeripheralBase) & (uint8)(~(uint8)USB_USBCTRL_PDE_MASK))) | ( \ + (uint8)((uint8)(State) << USB_USBCTRL_PDE_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgSignalObserveReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns content of the Otg observe register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgSignalObserveReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgSignalObserveReg(PeripheralBase) ( \ + USB_OBSERVE_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgSignalObservelReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the OTG observe register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg observel register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * USB_PDD_WriteOtgSignalObservelReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgSignalObservelReg(PeripheralBase, Value) ( \ + USB_OBSERVE_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDpPullUpSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D+ pull up signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = USB_PDD_GetDpPullUpSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDpPullUpSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DPPU_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDpPullDownSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D+ pull down signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetDpPullDownSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDpPullDownSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DPPD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetDmPullDownSignalState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the D- pull up signal. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_OBSERVE. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetDmPullDownSignalState(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetDmPullDownSignalState(PeripheralBase) ( \ + (uint8)(USB_OBSERVE_REG(PeripheralBase) & USB_OBSERVE_DMPD_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadOtgSignalControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Otg control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_CONTROL. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadOtgSignalControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadOtgSignalControlReg(PeripheralBase) ( \ + USB_CONTROL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteOtgSignalControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the OTG control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Otg control register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_CONTROL. + * @par Example: + * @code + * USB_PDD_WriteOtgSignalControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteOtgSignalControlReg(PeripheralBase, Value) ( \ + USB_CONTROL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTransceiverControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Transceiver control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * uint8 result = + * USB_PDD_ReadTransceiverControlReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadTransceiverControlReg(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTransceiverControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Transceiver control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Transceiver control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_WriteTransceiverControlReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteTransceiverControlReg(PeripheralBase, Value) ( \ + USB_USBTRC0_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ResetModule + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Starts module reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ResetModule(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ResetModule(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_USBRESET_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Starts module reset. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ResetModule(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ResetModule(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_USBRESET_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetModuleResetPendingFlag + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of module reset pending flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * uint8 result = + * USB_PDD_GetModuleResetPendingFlag(_BASE_PTR); + * @endcode + */ +#define USB_PDD_GetModuleResetPendingFlag(PeripheralBase) ( \ + (uint8)(USB_USBTRC0_REG(PeripheralBase) & USB_USBTRC0_USBRESET_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ClearAsyncResumeInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Clears asynchronous resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ClearAsyncResumeInterruptFlag(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ClearAsyncResumeInterruptFlag(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_SYNC_DET_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears asynchronous resume interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_ClearAsyncResumeInterruptFlag(_BASE_PTR); + * @endcode + */ + #define USB_PDD_ClearAsyncResumeInterruptFlag(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_SYNC_DET_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableAsyncResumeInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Enables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_EnableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_EnableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + (uint8)(USB_USBTRC0_USBRESMEN_MASK | 0x40U) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_EnableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_EnableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) |= \ + USB_USBTRC0_USBRESMEN_MASK \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableAsyncResumeInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MK20DZ10)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MKL24Z4)) || (defined(MCU_MKL25Z4)) || (defined(MCU_MKL26Z4)) || (defined(MCU_MKL46Z4))) +/** + * @brief Disables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_DisableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_DisableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + USB_USBTRC0_REG(PeripheralBase)) & ( \ + (uint8)(~(uint8)USB_USBTRC0_USBRESMEN_MASK)))) | ( \ + 0x40U)) \ + ) +#else /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables asynchronous resume interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBTRC0. + * @par Example: + * @code + * USB_PDD_DisableAsyncResumeInterrupt(_BASE_PTR); + * @endcode + */ + #define USB_PDD_DisableAsyncResumeInterrupt(PeripheralBase) ( \ + USB_USBTRC0_REG(PeripheralBase) &= \ + (uint8)(~(uint8)USB_USBTRC0_USBRESMEN_MASK) \ + ) +#endif /* (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK52D10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadFrameAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the Frame Adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * uint8 result = USB_PDD_ReadFrameAdjustmentReg(_BASE_PTR); + * @endcode + */ +#define USB_PDD_ReadFrameAdjustmentReg(PeripheralBase) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteFrameAdjustmentReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes Value to the Frame adjustment register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Frame adjustment register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * USB_PDD_WriteFrameAdjustmentReg(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_WriteFrameAdjustmentReg(PeripheralBase, Value) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetFrameAdjustment + ---------------------------------------------------------------------------- */ + +/** + * @brief Sets frame adjustment. In Host mode, the frame adjustment is a twos + * complement number that adjusts the period of each USB frame in 12-MHz clock + * periods. A SOF is normally generated every 12,000 12-MHz clock cycles. The Frame + * Adjust Register can adjust this by -128 to +127 to compensate for inaccuracies + * in the USB 48-MHz clock. Changes to the ADJ bit take effect at the next start + * of the next frame. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value written to the Frame adjustment register. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: USB0_USBFRMADJUST. + * @par Example: + * @code + * USB_PDD_SetFrameAdjustment(_BASE_PTR, 1); + * @endcode + */ +#define USB_PDD_SetFrameAdjustment(PeripheralBase, Value) ( \ + USB_USBFRMADJUST_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(USB_PDD_H_) */ + +/* USB_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h new file mode 100644 index 0000000..302124e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/VREF_PDD.h @@ -0,0 +1,413 @@ +/* + PDD layer implementation for peripheral type VREF + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(VREF_PDD_H_) +#define VREF_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error VREF PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* VREF */ && \ + !defined(MCU_MK10D5) /* VREF */ && \ + !defined(MCU_MK10D7) /* VREF */ && \ + !defined(MCU_MK10F12) /* VREF */ && \ + !defined(MCU_MK10DZ10) /* VREF */ && \ + !defined(MCU_MK11D5) /* VREF */ && \ + !defined(MCU_MK11D5WS) /* VREF */ && \ + !defined(MCU_MK12D5) /* VREF */ && \ + !defined(MCU_MK20D10) /* VREF */ && \ + !defined(MCU_MK20D5) /* VREF */ && \ + !defined(MCU_MK20D7) /* VREF */ && \ + !defined(MCU_MK20F12) /* VREF */ && \ + !defined(MCU_MK20DZ10) /* VREF */ && \ + !defined(MCU_MK21D5) /* VREF */ && \ + !defined(MCU_MK21D5WS) /* VREF */ && \ + !defined(MCU_MK21F12) /* VREF */ && \ + !defined(MCU_MK21F12WS) /* VREF */ && \ + !defined(MCU_MK22D5) /* VREF */ && \ + !defined(MCU_MK22F12810) /* VREF */ && \ + !defined(MCU_MK22F12) /* VREF */ && \ + !defined(MCU_MK22F25612) /* VREF */ && \ + !defined(MCU_MK22F51212) /* VREF */ && \ + !defined(MCU_MK24F12) /* VREF */ && \ + !defined(MCU_MK30D10) /* VREF */ && \ + !defined(MCU_MK30D7) /* VREF */ && \ + !defined(MCU_MK30DZ10) /* VREF */ && \ + !defined(MCU_MK40D10) /* VREF */ && \ + !defined(MCU_MK40D7) /* VREF */ && \ + !defined(MCU_MK40DZ10) /* VREF */ && \ + !defined(MCU_MK40X256VMD100) /* VREF */ && \ + !defined(MCU_MK50D10) /* VREF */ && \ + !defined(MCU_MK50D7) /* VREF */ && \ + !defined(MCU_MK50DZ10) /* VREF */ && \ + !defined(MCU_MK51D10) /* VREF */ && \ + !defined(MCU_MK51D7) /* VREF */ && \ + !defined(MCU_MK51DZ10) /* VREF */ && \ + !defined(MCU_MK52D10) /* VREF */ && \ + !defined(MCU_MK52DZ10) /* VREF */ && \ + !defined(MCU_MK53D10) /* VREF */ && \ + !defined(MCU_MK53DZ10) /* VREF */ && \ + !defined(MCU_MK60D10) /* VREF */ && \ + !defined(MCU_MK60F12) /* VREF */ && \ + !defined(MCU_MK60F15) /* VREF */ && \ + !defined(MCU_MK60DZ10) /* VREF */ && \ + !defined(MCU_MK60N512VMD100) /* VREF */ && \ + !defined(MCU_MK61F12) /* VREF */ && \ + !defined(MCU_MK61F15) /* VREF */ && \ + !defined(MCU_MK61F12WS) /* VREF */ && \ + !defined(MCU_MK61F15WS) /* VREF */ && \ + !defined(MCU_MK63F12) /* VREF */ && \ + !defined(MCU_MK63F12WS) /* VREF */ && \ + !defined(MCU_MK64F12) /* VREF */ && \ + !defined(MCU_MK65F18) /* VREF */ && \ + !defined(MCU_MK65F18WS) /* VREF */ && \ + !defined(MCU_MK66F18) /* VREF */ && \ + !defined(MCU_MK70F12) /* VREF */ && \ + !defined(MCU_MK70F15) /* VREF */ && \ + !defined(MCU_MK70F12WS) /* VREF */ && \ + !defined(MCU_MK70F15WS) /* VREF */ && \ + !defined(MCU_MKL03Z4) /* VREF */ && \ + !defined(MCU_MKV31F12810) /* VREF */ && \ + !defined(MCU_MKV31F25612) /* VREF */ && \ + !defined(MCU_MKV31F51212) /* VREF */ && \ + !defined(MCU_PCK20L4) /* VREF */ + // Unsupported MCU is active + #error VREF PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +/* Position of a parity bit */ +#define VREF_PDD_DISABLED_OR_NOT_STABLE 0U /**< The module is disabled or not stable. */ +#define VREF_PDD_STABLE 0x4U /**< The module is stable. */ + +/* Type of the buffer mode. */ +#define VREF_PDD_BANDGAP_ON_ONLY 0U /**< Bandgap on only, for stabilization and startup. */ +#define VREF_PDD_HIGH_POWER_BUFFER 0x1U /**< High power buffer mode enabled. */ +#define VREF_PDD_LOW_POWER_BUFFER 0x2U /**< Low power buffer mode enabled. */ + + +/* ---------------------------------------------------------------------------- + -- EnableChopOscillator + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables chop oscillator. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables chop oscillator. This parameter is of + * "Global enumeration used for specifying general enable/disable states + * (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_EnableChopOscillator(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableChopOscillator(PeripheralBase, State) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & (uint8)(~(uint8)VREF_TRM_CHOPEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_TRM_CHOPEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetTrimValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Set trim value for voltage reference correction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Trim value. This parameter is a 6-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_SetTrimValue(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_SetTrimValue(PeripheralBase, Value) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & (uint8)(~(uint8)VREF_TRM_TRIM_MASK))) | ( \ + (uint8)(Value))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetTrimValue + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns trim value for voltage reference correction. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 6-bit value. The value is cast to "uint8". + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * uint8 result = VREF_PDD_GetTrimValue(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_GetTrimValue(PeripheralBase) ( \ + (uint8)(VREF_TRM_REG(PeripheralBase) & VREF_TRM_TRIM_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * uint8 result = VREF_PDD_ReadTrimReg(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_ReadTrimReg(PeripheralBase) ( \ + VREF_TRM_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTrimReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into trim register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the trim register. This parameter is a + * 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_TRM. + * @par Example: + * @code + * VREF_PDD_WriteTrimReg(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_WriteTrimReg(PeripheralBase, Value) ( \ + VREF_TRM_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableInternalVoltageReference + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables internal voltage reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables internal voltage reference. This parameter + * is of "Global enumeration used for specifying general enable/disable + * states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableInternalVoltageReference(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableInternalVoltageReference(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_VREFEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_VREFEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableRegulator + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables regulator. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables regulator. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableRegulator(_BASE_PTR, PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableRegulator(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_REGEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_REGEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- EnableSecondOrderCurvatureCompensation + ---------------------------------------------------------------------------- */ + +/** + * @brief Enables second order curvature compensation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Enables or disables second order curvature compensation. This + * parameter is of "Global enumeration used for specifying general + * enable/disable states (PDD_DISABLE and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_EnableSecondOrderCurvatureCompensation(_BASE_PTR, + * PDD_DISABLE); + * @endcode + */ +#define VREF_PDD_EnableSecondOrderCurvatureCompensation(PeripheralBase, State) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_ICOMPEN_MASK))) | ( \ + (uint8)((uint8)(State) << VREF_SC_ICOMPEN_SHIFT))) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInternalVoltageReferenceState + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns state of the internal voltage reference. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of "Position of a parity bit" type. The value is cast + * to "uint8". + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * uint8 result = + * VREF_PDD_GetInternalVoltageReferenceState(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_GetInternalVoltageReferenceState(PeripheralBase) ( \ + (uint8)(VREF_SC_REG(PeripheralBase) & VREF_SC_VREFST_MASK) \ + ) + +/* ---------------------------------------------------------------------------- + -- SelectBufferMode + ---------------------------------------------------------------------------- */ + +/** + * @brief Selects buffer mode. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode Type of the match operation. This parameter is of "Type of the + * buffer mode." type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_SelectBufferMode(_BASE_PTR, + * VREF_PDD_BANDGAP_ON_ONLY); + * @endcode + */ +#define VREF_PDD_SelectBufferMode(PeripheralBase, Mode) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(VREF_SC_REG(PeripheralBase) & (uint8)(~(uint8)VREF_SC_MODE_LV_MASK))) | ( \ + (uint8)(Mode))) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Reads status and control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * uint8 result = VREF_PDD_ReadStatusControlReg(_BASE_PTR); + * @endcode + */ +#define VREF_PDD_ReadStatusControlReg(PeripheralBase) ( \ + VREF_SC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteStatusControlReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes new value specified by the Value parameter into status and + * control register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Value to be written to the status and control register. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: VREF_SC. + * @par Example: + * @code + * VREF_PDD_WriteStatusControlReg(_BASE_PTR, 1); + * @endcode + */ +#define VREF_PDD_WriteStatusControlReg(PeripheralBase, Value) ( \ + VREF_SC_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#endif /* #if defined(VREF_PDD_H_) */ + +/* VREF_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h new file mode 100644 index 0000000..e1ce443 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/PDD/WDOG_PDD.h @@ -0,0 +1,1526 @@ +/* + PDD layer implementation for peripheral type WDOG + (C) 2013 Freescale, Inc. All rights reserved. + + This file is static and it is generated from API-Factory +*/ + +#if !defined(WDOG_PDD_H_) +#define WDOG_PDD_H_ + +/* ---------------------------------------------------------------------------- + -- Test if supported MCU is active + ---------------------------------------------------------------------------- */ + +#if !defined(MCU_ACTIVE) + // No MCU is active + #error WDOG PDD library: No derivative is active. Place proper #include with PDD memory map before including PDD library. +#elif \ + !defined(MCU_MK10D10) /* WDOG */ && \ + !defined(MCU_MK10D5) /* WDOG */ && \ + !defined(MCU_MK10D7) /* WDOG */ && \ + !defined(MCU_MK10F12) /* WDOG */ && \ + !defined(MCU_MK10DZ10) /* WDOG */ && \ + !defined(MCU_MK11D5) /* WDOG */ && \ + !defined(MCU_MK11D5WS) /* WDOG */ && \ + !defined(MCU_MK12D5) /* WDOG */ && \ + !defined(MCU_MK20D10) /* WDOG */ && \ + !defined(MCU_MK20D5) /* WDOG */ && \ + !defined(MCU_MK20D7) /* WDOG */ && \ + !defined(MCU_MK20F12) /* WDOG */ && \ + !defined(MCU_MK20DZ10) /* WDOG */ && \ + !defined(MCU_MK21D5) /* WDOG */ && \ + !defined(MCU_MK21D5WS) /* WDOG */ && \ + !defined(MCU_MK21F12) /* WDOG */ && \ + !defined(MCU_MK21F12WS) /* WDOG */ && \ + !defined(MCU_MK22D5) /* WDOG */ && \ + !defined(MCU_MK22F12810) /* WDOG */ && \ + !defined(MCU_MK22F12) /* WDOG */ && \ + !defined(MCU_MK22F25612) /* WDOG */ && \ + !defined(MCU_MK22F51212) /* WDOG */ && \ + !defined(MCU_MK24F12) /* WDOG */ && \ + !defined(MCU_MK30D10) /* WDOG */ && \ + !defined(MCU_MK30D7) /* WDOG */ && \ + !defined(MCU_MK30DZ10) /* WDOG */ && \ + !defined(MCU_MK40D10) /* WDOG */ && \ + !defined(MCU_MK40D7) /* WDOG */ && \ + !defined(MCU_MK40DZ10) /* WDOG */ && \ + !defined(MCU_MK40X256VMD100) /* WDOG */ && \ + !defined(MCU_MK50D10) /* WDOG */ && \ + !defined(MCU_MK50D7) /* WDOG */ && \ + !defined(MCU_MK50DZ10) /* WDOG */ && \ + !defined(MCU_MK51D10) /* WDOG */ && \ + !defined(MCU_MK51D7) /* WDOG */ && \ + !defined(MCU_MK51DZ10) /* WDOG */ && \ + !defined(MCU_MK52D10) /* WDOG */ && \ + !defined(MCU_MK52DZ10) /* WDOG */ && \ + !defined(MCU_MK53D10) /* WDOG */ && \ + !defined(MCU_MK53DZ10) /* WDOG */ && \ + !defined(MCU_MK60D10) /* WDOG */ && \ + !defined(MCU_MK60F12) /* WDOG */ && \ + !defined(MCU_MK60F15) /* WDOG */ && \ + !defined(MCU_MK60DZ10) /* WDOG */ && \ + !defined(MCU_MK60N512VMD100) /* WDOG */ && \ + !defined(MCU_MK61F12) /* WDOG */ && \ + !defined(MCU_MK61F15) /* WDOG */ && \ + !defined(MCU_MK61F12WS) /* WDOG */ && \ + !defined(MCU_MK61F15WS) /* WDOG */ && \ + !defined(MCU_MK63F12) /* WDOG */ && \ + !defined(MCU_MK63F12WS) /* WDOG */ && \ + !defined(MCU_MK64F12) /* WDOG */ && \ + !defined(MCU_MK65F18) /* WDOG */ && \ + !defined(MCU_MK65F18WS) /* WDOG */ && \ + !defined(MCU_MK66F18) /* WDOG */ && \ + !defined(MCU_MK70F12) /* WDOG */ && \ + !defined(MCU_MK70F15) /* WDOG */ && \ + !defined(MCU_MK70F12WS) /* WDOG */ && \ + !defined(MCU_MK70F15WS) /* WDOG */ && \ + !defined(MCU_MKE02Z2) /* WDOG */ && \ + !defined(MCU_MKE02Z4) /* WDOG */ && \ + !defined(MCU_SKEAZN642) /* WDOG */ && \ + !defined(MCU_MKE04Z1284) /* WDOG */ && \ + !defined(MCU_MKE04Z4) /* WDOG */ && \ + !defined(MCU_SKEAZN84) /* WDOG */ && \ + !defined(MCU_MKE06Z4) /* WDOG */ && \ + !defined(MCU_MKV10Z7) /* WDOG */ && \ + !defined(MCU_MKV31F12810) /* WDOG */ && \ + !defined(MCU_MKV31F25612) /* WDOG */ && \ + !defined(MCU_MKV31F51212) /* WDOG */ && \ + !defined(MCU_MKW21D5) /* WDOG */ && \ + !defined(MCU_MKW21D5WS) /* WDOG */ && \ + !defined(MCU_MKW22D5) /* WDOG */ && \ + !defined(MCU_MKW22D5WS) /* WDOG */ && \ + !defined(MCU_MKW24D5) /* WDOG */ && \ + !defined(MCU_MKW24D5WS) /* WDOG */ && \ + !defined(MCU_PCK20L4) /* WDOG */ && \ + !defined(MCU_SKEAZ1284) /* WDOG */ + // Unsupported MCU is active + #error WDOG PDD library: Unsupported derivative is active. +#endif + +#include "PDD_Types.h" + +/* ---------------------------------------------------------------------------- + -- Method symbol definitions + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Windowing mode constants */ + #define WDOG_PDD_WINDOWING_DISABLED 0U /**< Disabled */ + #define WDOG_PDD_WINDOWING_ENABLED WDOG_CS2_WIN_MASK /**< Enabled */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Windowing mode constants */ + #define WDOG_PDD_WINDOWING_DISABLED 0U /**< Disabled */ + #define WDOG_PDD_WINDOWING_ENABLED WDOG_STCTRLH_WINEN_MASK /**< Enabled */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Clock source constants. */ + #define WDOG_PDD_SOURCE_BUSCLOCK 0U /**< Use bus clock as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_LPOCLK 0x1U /**< Use 1 kHz internal low-power oscillator as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_ICSIRCLK 0x2U /**< Use 32 kHz internal oscillator as a clock source for the watchdog counter */ + #define WDOG_PDD_SOURCE_ERCLK 0x3U /**< Use external clock as a clock source for the watchdog counter */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Clock source constants. */ + #define WDOG_PDD_SOURCE_DEDICATED 0U /**< Dedicated */ + #define WDOG_PDD_SOURCE_ALTERNATE WDOG_STCTRLH_CLKSRC_MASK /**< Alternate */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Refresh constants */ + #define WDOG_PDD_KEY_1 0x2A6U /**< First key of the refresh sequence */ + #define WDOG_PDD_KEY_2 0x80B4U /**< Second key of the refresh sequence */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Refresh constants */ + #define WDOG_PDD_KEY_1 0xA602U /**< First key of the refresh sequence */ + #define WDOG_PDD_KEY_2 0xB480U /**< Second key of the refresh sequence */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Unlock constants */ + #define WDOG_PDD_UNLOCK_1 0x20C5U /**< First key of the unlock sequence */ + #define WDOG_PDD_UNLOCK_2 0x28D9U /**< Second key of the unlock sequence */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Unlock constants */ + #define WDOG_PDD_UNLOCK_1 0xC520U /**< First key of the unlock sequence */ + #define WDOG_PDD_UNLOCK_2 0xD928U /**< Second key of the unlock sequence */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/* Reference clock prescaler constants */ + #define WDOG_PDD_DIVIDE_1 0U /**< Prescaler factor 1 */ + #define WDOG_PDD_DIVIDE_256 0x1U /**< Prescaler factor 256 */ + +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/* Reference clock prescaler constants */ + #define WDOG_PDD_DIVIDE_1 0U /**< Prescaler factor 1 */ + #define WDOG_PDD_DIVIDE_2 0x1U /**< Prescaler factor 2 */ + #define WDOG_PDD_DIVIDE_3 0x2U /**< Prescaler factor 3 */ + #define WDOG_PDD_DIVIDE_4 0x3U /**< Prescaler factor 4 */ + #define WDOG_PDD_DIVIDE_5 0x4U /**< Prescaler factor 5 */ + #define WDOG_PDD_DIVIDE_6 0x5U /**< Prescaler factor 6 */ + #define WDOG_PDD_DIVIDE_7 0x6U /**< Prescaler factor 7 */ + #define WDOG_PDD_DIVIDE_8 0x7U /**< Prescaler factor 8 */ + +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetAllowUpdateStatus + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns non-zero if watchdog registers can be unlocked. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetAllowUpdateStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetAllowUpdateStatus(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_UPDATE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns non-zero if watchdog registers can be unlocked. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetAllowUpdateStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetAllowUpdateStatus(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_ALLOWUPDATE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableUpdate + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief No further updates allowed to WDOG write once registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableUpdate(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableUpdate(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)WDOG_CS1_UPDATE_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief No further updates allowed to WDOG write once registers. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableUpdate(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableUpdate(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) &= \ + (uint16)(~(uint16)WDOG_STCTRLH_ALLOWUPDATE_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SetWindowingMode + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Configures the windowing mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Windowing mode + * constants". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetWindowingMode(_BASE_PTR, + * WDOG_PDD_WINDOWING_DISABLED); + * @endcode + */ + #define WDOG_PDD_SetWindowingMode(PeripheralBase, Mode) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + WDOG_CS2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)WDOG_CS2_WIN_MASK)) & ( \ + (uint8)(~(uint8)WDOG_CS2_FLG_MASK))))) | ( \ + (uint8)(Mode))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Configures the windowing mode operation. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Mode New value of the mode. Use constants from group "Windowing mode + * constants". This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetWindowingMode(_BASE_PTR, + * WDOG_PDD_WINDOWING_DISABLED); + * @endcode + */ + #define WDOG_PDD_SetWindowingMode(PeripheralBase, Mode) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_WINEN_MASK)))) | ( \ + (uint16)(Mode))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetInterruptMask + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_INT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt mask. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetInterruptMask(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptMask(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_IRQRSTEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_EnableInterrupt(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) |= \ + WDOG_CS1_INT_MASK \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_EnableInterrupt(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) |= \ + WDOG_STCTRLH_IRQRSTEN_MASK \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- DisableInterrupt + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Disables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableInterrupt(PeripheralBase) ( \ + WDOG_CS1_REG(PeripheralBase) &= \ + (uint8)(~(uint8)WDOG_CS1_INT_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Disables the WDOG interrupt. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_DisableInterrupt(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_DisableInterrupt(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) &= \ + (uint16)(~(uint16)WDOG_STCTRLH_IRQRSTEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- SelectClockSource + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Clock source + * constants.". This parameter is 8 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SelectClockSource(_BASE_PTR, + * WDOG_PDD_SOURCE_BUSCLOCK); + * @endcode + */ + #define WDOG_PDD_SelectClockSource(PeripheralBase, Source) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(( \ + WDOG_CS2_REG(PeripheralBase)) & (( \ + (uint8)(~(uint8)WDOG_CS2_CLK_MASK)) & ( \ + (uint8)(~(uint8)WDOG_CS2_FLG_MASK))))) | ( \ + (uint8)(Source))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Selects clock source. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Source New value of the source. Use constants from group "Clock source + * constants.". This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SelectClockSource(_BASE_PTR, + * WDOG_PDD_SOURCE_DEDICATED); + * @endcode + */ + #define WDOG_PDD_SelectClockSource(PeripheralBase, Source) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_CLKSRC_MASK)))) | ( \ + (uint16)(Source))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- EnableDevice + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Enables the WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of WDOG device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define WDOG_PDD_EnableDevice(PeripheralBase, State) ( \ + WDOG_CS1_REG(PeripheralBase) = \ + (uint8)(( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & (uint8)(~(uint8)WDOG_CS1_EN_MASK))) | ( \ + (uint8)((uint8)(State) << WDOG_CS1_EN_SHIFT))) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Enables the WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param State Requested state of WDOG device. This parameter is of "Global + * enumeration used for specifying general enable/disable states (PDD_DISABLE + * and PDD_ENABLE defined in PDD_Types.h)" type. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_EnableDevice(_BASE_PTR, PDD_DISABLE); + * @endcode + */ + #define WDOG_PDD_EnableDevice(PeripheralBase, State) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)(( \ + WDOG_STCTRLH_REG(PeripheralBase)) & ( \ + (uint16)(~(uint16)WDOG_STCTRLH_WDOGEN_MASK)))) | ( \ + (uint16)(State))) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- GetEnableDeviceStatus + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns current state of WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint8)(WDOG_CS1_REG(PeripheralBase) & WDOG_CS1_EN_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns current state of WDOG device. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH, WDOG_CS1 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetEnableDeviceStatus(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetEnableDeviceStatus(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLH_REG(PeripheralBase) & WDOG_STCTRLH_WDOGEN_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog status and control register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog status and control register high. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLH. + * @par Example: + * @code + * WDOG_PDD_WriteControlHighReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteControlHighReg(PeripheralBase, Value) ( \ + WDOG_STCTRLH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog status and control register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadControlHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadControlHighReg(PeripheralBase) ( \ + WDOG_STCTRLH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- GetInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 8-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * uint8 result = WDOG_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint8)(WDOG_CS2_REG(PeripheralBase) & WDOG_CS2_FLG_MASK) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Returns interrupt flag bit. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * uint16 result = WDOG_PDD_GetInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_GetInterruptFlag(PeripheralBase) ( \ + (uint16)(WDOG_STCTRLL_REG(PeripheralBase) & WDOG_STCTRLL_INTFLG_MASK) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ClearInterruptFlag + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_ClearInterruptFlag(PeripheralBase) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)(WDOG_CS2_FLG_MASK | 0x1U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Clears interrupt flag. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_ClearInterruptFlag(_BASE_PTR); + * @endcode + */ + #define WDOG_PDD_ClearInterruptFlag(PeripheralBase) ( \ + WDOG_STCTRLL_REG(PeripheralBase) = \ + (uint16)(WDOG_STCTRLL_INTFLG_MASK | 0x1U) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WriteControlLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog status and control register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog status and control register low. + * This parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_STCTRLL. + * @par Example: + * @code + * WDOG_PDD_WriteControlLowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteControlLowReg(PeripheralBase, Value) ( \ + WDOG_STCTRLL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadControlLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog status and control register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_STCTRLL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadControlLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadControlLowReg(PeripheralBase) ( \ + WDOG_STCTRLL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register high. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutHighReg(PeripheralBase, Value) ( \ + WDOG_TOVALH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register high. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutHighReg(PeripheralBase, Value) ( \ + WDOG_TOVALH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTimeOutHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog time-out value register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TOVALH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimeOutHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimeOutHighReg(PeripheralBase) ( \ + WDOG_TOVALH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register low. This + * parameter is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutLowReg(PeripheralBase, Value) ( \ + WDOG_TOVALL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register low. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteTimeOutLowReg(PeripheralBase, Value) ( \ + WDOG_TOVALL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadTimeOutLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog time-out value register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TOVALL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimeOutLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimeOutLowReg(PeripheralBase) ( \ + WDOG_TOVALL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowHighReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register high. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * WDOG_PDD_WriteWindowHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowHighReg(PeripheralBase, Value) ( \ + WDOG_WINH_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register high. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * WDOG_PDD_WriteWindowHighReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowHighReg(PeripheralBase, Value) ( \ + WDOG_WINH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWindowHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog window register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_WINH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadWindowHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadWindowHighReg(PeripheralBase) ( \ + WDOG_WINH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowLowReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register low. This parameter + * is a 8-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * WDOG_PDD_WriteWindowLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowLowReg(PeripheralBase, Value) ( \ + WDOG_WINL_REG(PeripheralBase) = \ + (uint8)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register low. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * WDOG_PDD_WriteWindowLowReg(_BASE_PTR, 1); + * @endcode + */ + #define WDOG_PDD_WriteWindowLowReg(PeripheralBase, Value) ( \ + WDOG_WINL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadWindowLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog window register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_WINL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadWindowLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadWindowLowReg(PeripheralBase) ( \ + WDOG_WINL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteRefreshReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. Use constants from group "Refresh constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_REFRESH, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteRefreshReg(_BASE_PTR, WDOG_PDD_KEY_1); + * @endcode + */ + #define WDOG_PDD_WriteRefreshReg(PeripheralBase, Value) ( \ + WDOG_CNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Service constant. Use constants from group "Refresh constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_REFRESH, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteRefreshReg(_BASE_PTR, WDOG_PDD_KEY_1); + * @endcode + */ + #define WDOG_PDD_WriteRefreshReg(PeripheralBase, Value) ( \ + WDOG_REFRESH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadRefreshReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_REFRESH. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadRefreshReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadRefreshReg(PeripheralBase) ( \ + WDOG_REFRESH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteUnlockReg + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Writes value to the watchdog refresh register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Unlock constant. Use constants from group "Unlock constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_UNLOCK, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteUnlockReg(_BASE_PTR, WDOG_PDD_UNLOCK_1); + * @endcode + */ + #define WDOG_PDD_WriteUnlockReg(PeripheralBase, Value) ( \ + WDOG_CNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Writes value to the watchdog unlock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value Unlock constant. Use constants from group "Unlock constants". + * This parameter is 16 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_UNLOCK, WDOG_CNT + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_WriteUnlockReg(_BASE_PTR, WDOG_PDD_UNLOCK_1); + * @endcode + */ + #define WDOG_PDD_WriteUnlockReg(PeripheralBase, Value) ( \ + WDOG_UNLOCK_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- ReadUnlockReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog unlock register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_UNLOCK. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadUnlockReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadUnlockReg(PeripheralBase) ( \ + WDOG_UNLOCK_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerOutputHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog timer output register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog timer output register high. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TMROUTH. + * @par Example: + * @code + * WDOG_PDD_WriteTimerOutputHighReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimerOutputHighReg(PeripheralBase, Value) ( \ + WDOG_TMROUTH_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerOutputHighReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog timer output register high. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TMROUTH. + * @par Example: + * @code + * uint16 result = + * WDOG_PDD_ReadTimerOutputHighReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimerOutputHighReg(PeripheralBase) ( \ + WDOG_TMROUTH_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimerOutputLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog timer output register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog timer output register low. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TMROUTL. + * @par Example: + * @code + * WDOG_PDD_WriteTimerOutputLowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimerOutputLowReg(PeripheralBase, Value) ( \ + WDOG_TMROUTL_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadTimerOutputLowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog timer output register low. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_TMROUTL. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadTimerOutputLowReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadTimerOutputLowReg(PeripheralBase) ( \ + WDOG_TMROUTL_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteResetCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog reset count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog reset count register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_RSTCNT. + * @par Example: + * @code + * WDOG_PDD_WriteResetCountReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteResetCountReg(PeripheralBase, Value) ( \ + WDOG_RSTCNT_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadResetCountReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog reset count register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_RSTCNT. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadResetCountReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadResetCountReg(PeripheralBase) ( \ + WDOG_RSTCNT_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- SetPrescaler + ---------------------------------------------------------------------------- */ + +#if ((defined(MCU_MKE02Z2)) || (defined(MCU_MKE02Z4)) || (defined(MCU_MKE04Z1284)) || (defined(MCU_MKE04Z4)) || (defined(MCU_MKE06Z4)) || (defined(MCU_SKEAZ1284)) || (defined(MCU_SKEAZN642)) || (defined(MCU_SKEAZN84))) +/** + * @brief Sets prescale value of the watchdog counter reference clock. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Reference clock prescaler constants". This parameter is 1 bit wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetPrescaler(_BASE_PTR, WDOG_PDD_DIVIDE_1); + * @endcode + */ + #define WDOG_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + WDOG_CS2_REG(PeripheralBase) = \ + (uint8)((uint8)((uint8)(Prescaler) << WDOG_CS2_PRES_SHIFT) | 0x1U) \ + ) +#else /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ +/** + * @brief Sets prescale value. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Prescaler New value of the prescaler. Use constants from group + * "Reference clock prescaler constants". This parameter is 3 bits wide. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC, WDOG_CS2 + * (depending on the peripheral). + * @par Example: + * @code + * WDOG_PDD_SetPrescaler(_BASE_PTR, WDOG_PDD_DIVIDE_1); + * @endcode + */ + #define WDOG_PDD_SetPrescaler(PeripheralBase, Prescaler) ( \ + WDOG_PRESC_REG(PeripheralBase) = \ + (uint16)((uint16)(Prescaler) << WDOG_PRESC_PRESCVAL_SHIFT) \ + ) +#endif /* (defined(MCU_MK10D10)) || (defined(MCU_MK10D5)) || (defined(MCU_MK10D7)) || (defined(MCU_MK10DZ10)) || (defined(MCU_MK10F12)) || (defined(MCU_MK11D5)) || (defined(MCU_MK11D5WS)) || (defined(MCU_MK12D5)) || (defined(MCU_MK20D10)) || (defined(MCU_MK20D5)) || (defined(MCU_MK20D7)) || (defined(MCU_MK20DZ10)) || (defined(MCU_MK20F12)) || (defined(MCU_MK21D5)) || (defined(MCU_MK21D5WS)) || (defined(MCU_MK21F12)) || (defined(MCU_MK21F12WS)) || (defined(MCU_MK22D5)) || (defined(MCU_MK22F12)) || (defined(MCU_MK22F12810)) || (defined(MCU_MK22F25612)) || (defined(MCU_MK22F51212)) || (defined(MCU_MK24F12)) || (defined(MCU_MK30D10)) || (defined(MCU_MK30D7)) || (defined(MCU_MK30DZ10)) || (defined(MCU_MK40D10)) || (defined(MCU_MK40D7)) || (defined(MCU_MK40DZ10)) || (defined(MCU_MK40X256VMD100)) || (defined(MCU_MK50D10)) || (defined(MCU_MK50D7)) || (defined(MCU_MK50DZ10)) || (defined(MCU_MK51D10)) || (defined(MCU_MK51D7)) || (defined(MCU_MK51DZ10)) || (defined(MCU_MK52D10)) || (defined(MCU_MK52DZ10)) || (defined(MCU_MK53D10)) || (defined(MCU_MK53DZ10)) || (defined(MCU_MK60D10)) || (defined(MCU_MK60DZ10)) || (defined(MCU_MK60F12)) || (defined(MCU_MK60F15)) || (defined(MCU_MK60N512VMD100)) || (defined(MCU_MK61F12)) || (defined(MCU_MK61F12WS)) || (defined(MCU_MK61F15)) || (defined(MCU_MK61F15WS)) || (defined(MCU_MK63F12)) || (defined(MCU_MK63F12WS)) || (defined(MCU_MK64F12)) || (defined(MCU_MK65F18)) || (defined(MCU_MK65F18WS)) || (defined(MCU_MK66F18)) || (defined(MCU_MK70F12)) || (defined(MCU_MK70F12WS)) || (defined(MCU_MK70F15)) || (defined(MCU_MK70F15WS)) || (defined(MCU_MKV10Z7)) || (defined(MCU_MKV31F12810)) || (defined(MCU_MKV31F25612)) || (defined(MCU_MKV31F51212)) || (defined(MCU_MKW21D5)) || (defined(MCU_MKW21D5WS)) || (defined(MCU_MKW22D5)) || (defined(MCU_MKW22D5WS)) || (defined(MCU_MKW24D5)) || (defined(MCU_MKW24D5WS)) || (defined(MCU_PCK20L4)) */ + +/* ---------------------------------------------------------------------------- + -- WritePrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog prescaler register. This parameter + * is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_PRESC. + * @par Example: + * @code + * WDOG_PDD_WritePrescalerReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WritePrescalerReg(PeripheralBase, Value) ( \ + WDOG_PRESC_REG(PeripheralBase) = \ + (uint16)(Value) \ + ) + +/* ---------------------------------------------------------------------------- + -- ReadPrescalerReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Returns the content of the watchdog prescaler register. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @return Returns a 16-bit value. + * @remarks The macro accesses the following registers: WDOG_PRESC. + * @par Example: + * @code + * uint16 result = WDOG_PDD_ReadPrescalerReg(_BASE_PTR); + * @endcode + */ +#define WDOG_PDD_ReadPrescalerReg(PeripheralBase) ( \ + WDOG_PRESC_REG(PeripheralBase) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteTimeOutReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog time-out value register. Because the WDOG + * peripheral is big endian, the conversion to the little endian is done in this + * macro. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog time-out value register. This + * parameter is a 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_TOVAL. + * @par Example: + * @code + * WDOG_PDD_WriteTimeOutReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteTimeOutReg(PeripheralBase, Value) ( \ + WDOG_TOVAL_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)((uint16)((uint16)(Value) & 0xFFU) << 8U)) | ( \ + (uint16)((uint16)(Value) >> 8U))) \ + ) + +/* ---------------------------------------------------------------------------- + -- WriteWindowReg + ---------------------------------------------------------------------------- */ + +/** + * @brief Writes value to the watchdog window register. Because the WDOG + * peripheral is big endian, the conversion to the little endian is done in this macro. + * @param PeripheralBase Pointer to a peripheral registers structure (peripheral + * base address). You can use the constant defined in the registers + * definition header file (_BASE_PTR) or the constant defined in + * the peripheral initialization component header file + * (_DEVICE). + * @param Value New content of the watchdog window register. This parameter is a + * 16-bit value. + * @return Returns a value of void type. + * @remarks The macro accesses the following registers: WDOG_WIN. + * @par Example: + * @code + * WDOG_PDD_WriteWindowReg(_BASE_PTR, 1); + * @endcode + */ +#define WDOG_PDD_WriteWindowReg(PeripheralBase, Value) ( \ + WDOG_WIN_REG(PeripheralBase) = \ + (uint16)(( \ + (uint16)((uint16)((uint16)(Value) & 0xFFU) << 8U)) | ( \ + (uint16)((uint16)(Value) >> 8U))) \ + ) +#endif /* #if defined(WDOG_PDD_H_) */ + +/* WDOG_PDD.h, eof. */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c new file mode 100644 index 0000000..36034c5 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.c @@ -0,0 +1,556 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CDC1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_CDC_Device +** Version : Component 01.031, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** Component name : CDC1 +** CPU : Kinetis K20D72 +** CDC Settings : Enabled +** .inf ClassGuid : 4D36E978-E325-11CE-BFC1-08002BE10318 +** .inf VID : 2504 +** .inf PID : 0300 +** .inf PRVDR : Freescale +** .inf MFGNAME : My Company +** .inf DESCRIPTION : Freescale CDC Device +** .inf SERVICE : Virtual Com Driver +** Bus reported device : FSL CDC DEVICE +** Bus reported vendor : FREESCALE INC. +** Send Buffer : RingBuffer +** Receive Buffer : RingBuffer +** Use Timeout : Disabled +** Contents : +** ClearRxBuffer - void CDC1_ClearRxBuffer(void); +** ClearTxBuffer - void CDC1_ClearTxBuffer(void); +** GetFreeInTxBuf - word CDC1_GetFreeInTxBuf(void); +** GetCharsInTxBuf - word CDC1_GetCharsInTxBuf(void); +** GetCharsInRxBuf - word CDC1_GetCharsInRxBuf(void); +** GetChar - byte CDC1_GetChar(CDC1_TComData *Chr); +** RecvChar - byte CDC1_RecvChar(CDC1_TComData *Chr); +** SendChar - byte CDC1_SendChar(CDC1_TComData Chr); +** SendString - byte CDC1_SendString(CDC1_TComData *Chr); +** SendBlock - byte CDC1_SendBlock(byte *data, word dataSize); +** PutBufferChecked - byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +** App_Callback - void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +** Notify_Callback - void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +** App_Task - byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +** Init - byte CDC1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013 +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file CDC1.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CDC1_module CDC1 module documentation +** @{ +*/ + +/* MODULE CDC1. */ + +#include "CDC1.h" +#include "hidef.h" /* for EnableInterrupts; macro */ +#include "hal/derivative.h" /* include peripheral declarations */ +#include "usb_cdc.h" /* USB CDC Class Header File */ +#include +/* skip the inclusion in dependency state */ +#ifndef __NO_SETJMP + #include +#endif +#include +#include + +#define CONTROLLER_ID (0) /* ID to identify USB CONTROLLER */ + +#if HIGH_SPEED_DEVICE +static uint_32 g_cdcBuffer[DIC_BULK_OUT_ENDP_PACKET_SIZE>>1]; +#endif + +/* Virtual COM Application start Init Flag */ +static volatile boolean start_app = FALSE; + +/* Virtual COM Application Carrier Activate Flag */ +static volatile boolean start_transactions = FALSE; + +static volatile boolean transactionOngoing = FALSE; +/* +** =================================================================== +** Method : CDC1_GetFreeInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of free character in the send buffer +** Parameters : None +** Returns : +** --- - Number of free character in the receive +** buffer. +** =================================================================== +*/ +/* +word CDC1_GetFreeInTxBuf(void) +{ + *** Implemented as macro in the header file +} +*/ + +/* +** =================================================================== +** Method : CDC1_GetCharsInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the send buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ +/* +word CDC1_GetCharsInTxBuf(void) +{ + *** implemented as macro in the header file + return (word)Tx1_NofElements(); +} +*/ + +/* +** =================================================================== +** Method : CDC1_GetCharsInRxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the receive buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ +word CDC1_GetCharsInRxBuf(void) +{ + static uint8 txBuf[CDC1_DATA_BUFF_SIZE]; + + if(CDC1_App_Task(txBuf, sizeof(txBuf))!=ERR_OK) { /* call USB handler: if active, then this will empty the buffer */ + } + return (word)Rx1_NofElements(); +} + +/* +** =================================================================== +** Method : CDC1_GetChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is not +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ +/** +byte CDC1_GetChar(CDC1_TComData *Chr) +{ + *** implemented as macro in the header file + return Rx1_Get(Chr); +} +*/ +/* +** =================================================================== +** Method : CDC1_RecvChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ +byte CDC1_RecvChar(CDC1_TComData *Chr) +{ + while(Rx1_Get(Chr)!=ERR_OK) { + /* retry receiving until success */ + } + return ERR_OK; +} + +/* +** =================================================================== +** Method : CDC1_SendChar (component FSL_USB_CDC_Device) +** Description : +** Method to send a character to the USB interface. Method is +** non-blocking: If the output buffer is full, it tries to send +** it over USB. If this fails or buffer is still full, the +** character will be lost. If OnError() event is enabled, the +** error event will be called in case of error. +** Parameters : +** NAME - DESCRIPTION +** Chr - Character to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendChar(CDC1_TComData Chr) +{ + static uint8 txBuf[CDC1_DATA_BUFF_SIZE]; + + if(Tx1_Put(Chr)==ERR_TXFULL) { /* retry once, otherwise throw it away */ + if(CDC1_App_Task(txBuf, sizeof(txBuf))!=ERR_OK) { /* call USB handler: if active, then this will empty the buffer */ + return ERR_TXFULL; + } else { /* retry, as USB App_Task() should have sent the buffer */ + return Tx1_Put(Chr); /* retry. If buffer is still full, we will lose the character */ + } + } + return ERR_OK; +} + +/* +** =================================================================== +** Method : CDC1_SendBlock (component FSL_USB_CDC_Device) +** Description : +** Method to send a data block to the USB interface. Method is +** non-blocking: if data cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * data - Pointer to data to send. +** dataSize - Size of data in bytes +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendBlock(byte *data, word dataSize) +{ + byte res = ERR_OK; + + while(dataSize > 0) { + if(CDC1_SendChar(*data)!=ERR_OK) { + res = ERR_TXFULL; + } + dataSize--; data++; + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_SendString (component FSL_USB_CDC_Device) +** Description : +** Method to send a string to the USB interface. Method is +** non-blocking: if string cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to string to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ +byte CDC1_SendString(CDC1_TComData *Chr) +{ + byte res = ERR_OK; + + while(*Chr != '\0') { + if(CDC1_SendChar(*Chr)!=ERR_OK) { + res = ERR_TXFULL; + } + Chr++; + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_App_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle class callbacks from USB +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - gives the configuration value +** Returns : Nothing +** =================================================================== +*/ +void CDC1_App_Callback(byte controller_ID, byte event_type, void *val) +{ + UNUSED(controller_ID); + UNUSED(val); + if(event_type == USB_APP_BUS_RESET) { + start_app = FALSE; + } else if(event_type == USB_APP_ENUM_COMPLETE) { +#if HIGH_SPEED_DEVICE + /* prepare for the next receive event */ + USB_Class_CDC_Interface_DIC_Recv_Data(&controller_ID, + (uint_8_ptr)g_cdcBuffer, + DIC_BULK_OUT_ENDP_PACKET_SIZE); +#endif + start_app = TRUE; + } else if((event_type == USB_APP_DATA_RECEIVED)&&(start_transactions==TRUE)) { + /* Copy Received Data buffer to Application Buffer */ + USB_PACKET_SIZE BytesToBeCopied; + APP_DATA_STRUCT *dp_rcv = (APP_DATA_STRUCT*)val; + uint_8 index; + + BytesToBeCopied = (USB_PACKET_SIZE)((dp_rcv->data_size > CDC1_DATA_BUFF_SIZE) ? CDC1_DATA_BUFF_SIZE:dp_rcv->data_size); + for(index = 0; indexdata_ptr[index])!=ERR_OK) { + /* Failed to put byte into buffer. Is the buffer to small? Then increase the Rx buffer. + Otherwise not much we could do here, so we are loosing byte here. + */ + /* Enable OnError() event so this event will be called here */ + } + } + (void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, NULL, 0); /* see http://eprints.utar.edu.my/143/1/BI-2011-0708672-1.pdf, page 131 */ + } else if((event_type == USB_APP_SEND_COMPLETE)&&(start_transactions==TRUE)) { + transactionOngoing = FALSE; + /* Previous Send is complete. Queue next receive */ +#if HIGH_SPEED_DEVICE + //(void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, g_cdcBuffer, 0); +#else + (void)USB_Class_CDC_Interface_DIC_Recv_Data(CONTROLLER_ID, NULL, 0); +#endif + } else if(event_type == USB_APP_ERROR) { /* detach? */ + start_app = FALSE; + start_transactions = FALSE; + } +} + +/* +** =================================================================== +** Method : CDC1_Notify_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle PSTN Sub Class callbacks +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - +** Returns : Nothing +** =================================================================== +*/ +void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val) +{ + UNUSED(controller_ID); + UNUSED(val); + if(start_app == TRUE) { + if(event_type == USB_APP_CDC_CARRIER_ACTIVATED) { + start_transactions = TRUE; + } else if(event_type == USB_APP_CDC_CARRIER_DEACTIVATED) { + start_transactions = FALSE; + } + } + start_transactions = TRUE; /* ??? see http://forums.freescale.com/t5/Freescale-MQX-trade-USB-Host/Cant-get-CDC-virtual-com-demo-to-work-with-VB2005-on-xp-sp3/m-p/92713#M302 */ +} + +/* +** =================================================================== +** Method : CDC1_RunUsbEngine (component FSL_USB_CDC_Device) +** +** Description : +** Runs the USB polling engine +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void CDC1_RunUsbEngine(void) +{ + /* not needed */ +} + +/* +** =================================================================== +** Method : CDC1_SendDataBlock (component FSL_USB_CDC_Device) +** +** Description : +** Sends a USB data block +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +byte CDC1_SendDataBlock(byte *data, word dataSize) +{ + uint8 res = ERR_OK; + + transactionOngoing = TRUE; + if(USB_Class_CDC_Interface_DIC_Send_Data(CONTROLLER_ID, data, dataSize)!=USB_OK) { + transactionOngoing = FALSE; + return ERR_FAULT; + } + /* wait for transaction finish */ + while(transactionOngoing) { /* wait until transaction is finished */ + CDC1_RunUsbEngine(); + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_App_Task (component FSL_USB_CDC_Device) +** Description : +** Application task to be called periodically from the main +** task. +** Parameters : +** NAME - DESCRIPTION +** * txBuf - Pointer to temporary buffer used to +** transmit data over USB. Should be equal or +** greater than the endpoint buffer size. Data +** will be sent in an asynchronous way, so +** make sure the buffer is *not* on the stack. +** This buffer must be available until the +** next transmission. +** txBufSize - Size of the buffer in bytes +** Returns : +** --- - Error code, returns ERR_OK if USB +** enumeration has been finished, error code +** otherwise. +** =================================================================== +*/ +byte CDC1_App_Task(byte *txBuf, size_t txBufSize) +{ + uint8 i, res; + + /* device is Kinetis K20D72 */ + CDC1_RunUsbEngine(); + /* call the periodic task function */ + USB_Class_CDC_Periodic_Task(); + /* check whether enumeration is complete or not */ + if((start_app==TRUE) && (start_transactions==TRUE)) { + if(Tx1_NofElements()!=0) { + i = 0; + while(iCDC1_GetFreeInTxBuf()) { /* no room at the Inn... */ + res = ERR_TXFULL; + } else { + res = ERR_OK; + while(bufSize>0 && res==ERR_OK) { + res = Tx1_Put(*buf); + bufSize--; + buf++; + } + } + return res; +} + +/* +** =================================================================== +** Method : CDC1_ClearRxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the receiver buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/** +void CDC1_ClearRxBuffer(void) +{ + Implemented as macro in the header file +} +*/ + +/* +** =================================================================== +** Method : CDC1_ClearTxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the transmit buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/** +void CDC1_ClearTxBuffer(void) +{ + Implemented as macro in the header file +} +*/ + +/* END CDC1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h new file mode 100644 index 0000000..d0f14fa --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CDC1.h @@ -0,0 +1,379 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CDC1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_CDC_Device +** Version : Component 01.031, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** Component name : CDC1 +** CPU : Kinetis K20D72 +** CDC Settings : Enabled +** .inf ClassGuid : 4D36E978-E325-11CE-BFC1-08002BE10318 +** .inf VID : 2504 +** .inf PID : 0300 +** .inf PRVDR : Freescale +** .inf MFGNAME : My Company +** .inf DESCRIPTION : Freescale CDC Device +** .inf SERVICE : Virtual Com Driver +** Bus reported device : FSL CDC DEVICE +** Bus reported vendor : FREESCALE INC. +** Send Buffer : RingBuffer +** Receive Buffer : RingBuffer +** Use Timeout : Disabled +** Contents : +** ClearRxBuffer - void CDC1_ClearRxBuffer(void); +** ClearTxBuffer - void CDC1_ClearTxBuffer(void); +** GetFreeInTxBuf - word CDC1_GetFreeInTxBuf(void); +** GetCharsInTxBuf - word CDC1_GetCharsInTxBuf(void); +** GetCharsInRxBuf - word CDC1_GetCharsInRxBuf(void); +** GetChar - byte CDC1_GetChar(CDC1_TComData *Chr); +** RecvChar - byte CDC1_RecvChar(CDC1_TComData *Chr); +** SendChar - byte CDC1_SendChar(CDC1_TComData Chr); +** SendString - byte CDC1_SendString(CDC1_TComData *Chr); +** SendBlock - byte CDC1_SendBlock(byte *data, word dataSize); +** PutBufferChecked - byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +** App_Callback - void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +** Notify_Callback - void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +** App_Task - byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +** Init - byte CDC1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013 +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file CDC1.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CDC1_module CDC1 module documentation +** @{ +*/ + +#ifndef __CDC1_H +#define __CDC1_H + +/* MODULE CDC1. */ + +/* Include shared modules, which are used for whole project */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "Tx1.h" +#include "Rx1.h" +#include /* for size_t */ + +//#include "Cpu.h" + + +#ifndef __BWUserType_CDC1_TComData +#define __BWUserType_CDC1_TComData + typedef byte CDC1_TComData ; /* User type for communication data type. */ +#endif + +/* + DATA_BUFF_SIZE should be greater than or equal to the endpoint buffer size, + otherwise there will be data loss. For MC9S08JS16, maximum DATA_BUFF_SIZE + supported is 16 Bytes +*/ +#define CDC1_DATA_BUFF_SIZE 64 + +#define CDC1_USB_ERR_SEND 1 /* Error while sending */ +#define CDC1_USB_ERR_BUSOFF 2 /* Bus not ready */ +#define CDC1_USB_ERR_INIT 3 /* USB initialization error */ +#define CDC1_USB_ERR_TX_CHAR 4 /* Error sending character */ +#define CDC1_USB_ERR_TX_STRING 5 /* Error sending string */ +#define CDC1_USB_ERR_CHECKED_TXFULL 6 /* Error during sending a checked block */ +#define CDC1_USB_ERR_RECEIVE 7 /* Error while starting an receive transaction */ +#define CDC1_USB_ERR_RX_PUT 8 /* Error while putting RX byte into buffer */ +#define CDC1_USB_ERR_TX_BLOCK 9 /* Error sending data block */ +#define CDC1_USB_TIMEOUT_SEND 10 /* Timeout while sending */ + + +#define CDC1_GetFreeInTxBuf() \ + Tx1_NofFreeElements() +/* +** =================================================================== +** Method : CDC1_GetFreeInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of free character in the send buffer +** Parameters : None +** Returns : +** --- - Number of free character in the receive +** buffer. +** =================================================================== +*/ + +byte CDC1_RecvChar(CDC1_TComData *Chr); +/* +** =================================================================== +** Method : CDC1_RecvChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ + +byte CDC1_SendChar(CDC1_TComData Chr); +/* +** =================================================================== +** Method : CDC1_SendChar (component FSL_USB_CDC_Device) +** Description : +** Method to send a character to the USB interface. Method is +** non-blocking: If the output buffer is full, it tries to send +** it over USB. If this fails or buffer is still full, the +** character will be lost. If OnError() event is enabled, the +** error event will be called in case of error. +** Parameters : +** NAME - DESCRIPTION +** Chr - Character to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +#define CDC1_GetCharsInTxBuf() \ + Tx1_NofElements() +/* +** =================================================================== +** Method : CDC1_GetCharsInTxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the send buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ + +word CDC1_GetCharsInRxBuf(void); +/* +** =================================================================== +** Method : CDC1_GetCharsInRxBuf (component FSL_USB_CDC_Device) +** Description : +** Returns the number of character in the receive buffer +** Parameters : None +** Returns : +** --- - Number of character in the receive buffer. +** =================================================================== +*/ + +byte CDC1_Init(void); +/* +** =================================================================== +** Method : CDC1_Init (component FSL_USB_CDC_Device) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte CDC1_App_Task(byte *txBuf, size_t txBufSize); +/* +** =================================================================== +** Method : CDC1_App_Task (component FSL_USB_CDC_Device) +** Description : +** Application task to be called periodically from the main +** task. +** Parameters : +** NAME - DESCRIPTION +** * txBuf - Pointer to temporary buffer used to +** transmit data over USB. Should be equal or +** greater than the endpoint buffer size. Data +** will be sent in an asynchronous way, so +** make sure the buffer is *not* on the stack. +** This buffer must be available until the +** next transmission. +** txBufSize - Size of the buffer in bytes +** Returns : +** --- - Error code, returns ERR_OK if USB +** enumeration has been finished, error code +** otherwise. +** =================================================================== +*/ + +byte CDC1_SendString(CDC1_TComData *Chr); +/* +** =================================================================== +** Method : CDC1_SendString (component FSL_USB_CDC_Device) +** Description : +** Method to send a string to the USB interface. Method is +** non-blocking: if string cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to string to send. +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +#define CDC1_GetChar(Chr) \ + Rx1_Get(Chr) + +/* +** =================================================================== +** Method : CDC1_GetChar (component FSL_USB_CDC_Device) +** Description : +** Receives a character from the USB interface. Function is not +** blocking if there is no character in the input buffer. +** Parameters : +** NAME - DESCRIPTION +** * Chr - Pointer to where to store the character +** received +** Returns : +** --- - Error code, ERR_OK for success, +** ERR_RXEMPTY if nothing is in RX buffer. +** =================================================================== +*/ + +byte CDC1_PutBufferChecked(byte *buf, size_t bufSize); +/* +** =================================================================== +** Method : CDC1_PutBufferChecked (component FSL_USB_CDC_Device) +** Description : +** Puts a data block into the output buffer, but does not send +** it. If there is not enough size available, then ERR_TXFULL +** is returned, otherwise ERR_OK. The application then needs to +** call USB_App_Callback() to actually send the buffer. +** Parameters : +** NAME - DESCRIPTION +** * buf - Pointer to buffer to be sent +** bufsize - Buffer size in bytes +** Returns : +** --- - Error code +** =================================================================== +*/ + +void CDC1_App_Callback(byte controller_ID, byte event_type, void *val); +/* +** =================================================================== +** Method : CDC1_App_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle class callbacks from USB +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - gives the configuration value +** Returns : Nothing +** =================================================================== +*/ + +void CDC1_Notify_Callback(byte controller_ID, byte event_type, void *val); +/* +** =================================================================== +** Method : CDC1_Notify_Callback (component FSL_USB_CDC_Device) +** Description : +** Method to handle PSTN Sub Class callbacks +** Parameters : +** NAME - DESCRIPTION +** controller_ID - controller ID +** event_type - value of the event +** val - +** Returns : Nothing +** =================================================================== +*/ + +#define CDC1_ClearRxBuffer() \ + Rx1_Clear() +/* +** =================================================================== +** Method : CDC1_ClearRxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the receiver buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CDC1_ClearTxBuffer() \ + Tx1_Clear() +/* +** =================================================================== +** Method : CDC1_ClearTxBuffer (component FSL_USB_CDC_Device) +** Description : +** Clears the transmit buffer content +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void CDC1_RunUsbEngine(void); +/* +** =================================================================== +** Method : CDC1_RunUsbEngine (component FSL_USB_CDC_Device) +** +** Description : +** Runs the USB polling engine +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +byte CDC1_SendBlock(byte *data, word dataSize); +/* +** =================================================================== +** Method : CDC1_SendBlock (component FSL_USB_CDC_Device) +** Description : +** Method to send a data block to the USB interface. Method is +** non-blocking: if data cannot be sent, it will be lost. If +** OnError() event is enabled, the error event will be called +** in case of error. +** Parameters : +** NAME - DESCRIPTION +** * data - Pointer to data to send. +** dataSize - Size of data in bytes +** Returns : +** --- - Error code. ERR_OK for success and +** ERR_FAILED otherwise. +** =================================================================== +*/ + +byte CDC1_SendDataBlock(byte *data, word dataSize); +/* +** =================================================================== +** Method : CDC1_SendDataBlock (component FSL_USB_CDC_Device) +** +** Description : +** Sends a USB data block +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END CDC1. */ + +#endif +/* ifndef __CDC1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c new file mode 100644 index 0000000..cf55876 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.c @@ -0,0 +1,103 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CS1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : CriticalSection +** Version : Component 01.006, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** +** Contents : +** CriticalVariable - void CS1_CriticalVariable(void); +** EnterCritical - void CS1_EnterCritical(void); +** ExitCritical - void CS1_ExitCritical(void); +** +** License : Open Source (LGPL) +** Copyright : Erich Styger, 2014, all rights reserved. +** Web : www.mcuoneclipse.com +** This an open source software implementing a driver using Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file CS1.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CS1_module CS1 module documentation +** @{ +*/ + +/* MODULE CS1. */ + +#include "CS1.h" + +/* +** =================================================================== +** Method : CS1_CriticalVariable (component CriticalSection) +** Description : +** Defines a variable if necessary. This is a macro. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_CriticalVariable(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* +** =================================================================== +** Method : CS1_EnterCritical (component CriticalSection) +** Description : +** Enters a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_EnterCritical(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* +** =================================================================== +** Method : CS1_ExitCritical (component CriticalSection) +** Description : +** Exits a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void CS1_ExitCritical(void) +{ + *** Implemented as macro in the header file CS1.h +} +*/ + +/* END CS1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h new file mode 100644 index 0000000..d66cf32 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/CS1.h @@ -0,0 +1,126 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : CS1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : CriticalSection +** Version : Component 01.006, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** +** Settings : +** +** Contents : +** CriticalVariable - void CS1_CriticalVariable(void); +** EnterCritical - void CS1_EnterCritical(void); +** ExitCritical - void CS1_ExitCritical(void); +** +** License : Open Source (LGPL) +** Copyright : Erich Styger, 2014, all rights reserved. +** Web : www.mcuoneclipse.com +** This an open source software implementing a driver using Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file CS1.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup CS1_module CS1 module documentation +** @{ +*/ + +#ifndef __CS1_H +#define __CS1_H + +/* MODULE CS1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ + +//#include "Cpu.h" + + +/* workaround macros for wrong EnterCritical()/ExitCritical() in the low level drivers. Will be removed once PEx is fixed */ +#define CS1_CriticalVariableDrv() \ + CS1_CriticalVariable() +#define CS1_EnterCriticalDrv() \ + CS1_EnterCritical() +#define CS1_ExitCriticalDrv() \ + CS1_ExitCritical() + +#define CS1_CriticalVariable() \ + uint8 cpuSR; /* variable to store current status */ + +/* +** =================================================================== +** Method : CS1_CriticalVariable (component CriticalSection) +** Description : +** Defines a variable if necessary. This is a macro. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CS1_EnterCritical() \ + do { \ + asm ( \ + "MRS R0, PRIMASK\n\t" \ + "CPSID I\n\t" \ + "STRB R0, %[output]" \ + : [output] "=m" (cpuSR) :: "r0"); \ + } while(0) + +/* +** =================================================================== +** Method : CS1_EnterCritical (component CriticalSection) +** Description : +** Enters a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define CS1_ExitCritical() \ + do{ \ + asm ( \ + "ldrb r0, %[input]\n\t" \ + "msr PRIMASK,r0;\n\t" \ + ::[input] "m" (cpuSR) : "r0"); \ + } while(0) + +/* +** =================================================================== +** Method : CS1_ExitCritical (component CriticalSection) +** Description : +** Exits a critical section +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END CS1. */ + +#endif +/* ifndef __CS1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h new file mode 100644 index 0000000..b39e5d0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/FSL_USB_Stack_Config.h @@ -0,0 +1,12 @@ +/****************************************************************************** + * Configuration file for the FSL USB stack created with Processor Expert. + *****************************************************************************/ +#ifndef __FSL_USB_STACK_CONFIG_ +#define __FSL_USB_STACK_CONFIG_ + +/* Overwrite initialization values from Processor Expert Init() component. These are 'known working values'. + * Otherwise you have to setup the bits (e.g. Pull-up/pull-down resistors! + * */ +#define USB_USER_CONFIG_USE_STACK_INIT 1 /* value set by component property 'Use USB Stack Initialization' */ + +#endif /* __FSL_USB_STACK_CONFIG_ */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h new file mode 100644 index 0000000..08bf3b0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Const.h @@ -0,0 +1,96 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Const +** Version : Driver 01.00 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Const.h +** @version 01.00 +** @brief +** This component "PE_Const" contains internal definitions +** of the constants. +*/ +/*! +** @addtogroup PE_Const_module PE_Const module documentation +** @{ +*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + + +/* Reset cause constants */ +#define RSTSRC_WAKEUP 0x01U /*!< LLWU module wakeup reset */ +#define RSTSRC_LVD 0x02U /*!< Low-voltage detect reset */ +#define RSTSRC_LOC 0x04U /*!< Loss-of-clock reset */ +#define RSTSRC_LOL 0x08U /*!< Loss-of-lock reset */ +#define RSTSRC_COP 0x20U /*!< Watchdog reset */ +#define RSTSRC_WDOG 0x20U /*!< Watchdog reset */ +#define RSTSRC_PIN 0x40U /*!< External pin reset */ +#define RSTSRC_POR 0x80U /*!< Power-on reset */ +#define RSTSRC_JTAG 0x0100U /*!< JTAG reset pin */ +#define RSTSRC_LOCKUP 0x0200U /*!< Core Lock-up reset */ +#define RSTSRC_SW 0x0400U /*!< Software reset */ +#define RSTSRC_MDM_AP 0x0800U /*!< Reset caused by host debugger system */ +#define RSTSRC_EZPT 0x1000U /*!< EzPort reset */ +#define RSTSRC_SACKERR 0x2000U /*!< Stop Mode Acknowledge Error Reset */ + + +/* Low voltage interrupt cause constants */ +#define LVDSRC_LVD 0x01U /*!< Low voltage detect */ +#define LVDSRC_LVW 0x02U /*!< Low-voltage warning */ + +#endif /* _PE_Const_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h new file mode 100644 index 0000000..c53525e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Error.h @@ -0,0 +1,128 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Error +** Version : Driver 01.00 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component "PE_Error" contains internal definitions +** of the error constants. +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Error.h +** @version 01.00 +** @brief +** This component "PE_Error" contains internal definitions +** of the error constants. +*/ +/*! +** @addtogroup PE_Error_module PE_Error module documentation +** @{ +*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0x00U /*!< OK */ +#define ERR_SPEED 0x01U /*!< This device does not work in the active speed mode. */ +#define ERR_RANGE 0x02U /*!< Parameter out of range. */ +#define ERR_VALUE 0x03U /*!< Parameter of incorrect value. */ +#define ERR_OVERFLOW 0x04U /*!< Timer overflow. */ +#define ERR_MATH 0x05U /*!< Overflow during evaluation. */ +#define ERR_ENABLED 0x06U /*!< Device is enabled. */ +#define ERR_DISABLED 0x07U /*!< Device is disabled. */ +#define ERR_BUSY 0x08U /*!< Device is busy. */ +#define ERR_NOTAVAIL 0x09U /*!< Requested value or method not available. */ +#define ERR_RXEMPTY 0x0AU /*!< No data in receiver. */ +#define ERR_TXFULL 0x0BU /*!< Transmitter is full. */ +#define ERR_BUSOFF 0x0CU /*!< Bus not available. */ +#define ERR_OVERRUN 0x0DU /*!< Overrun error is detected. */ +#define ERR_FRAMING 0x0EU /*!< Framing error is detected. */ +#define ERR_PARITY 0x0FU /*!< Parity error is detected. */ +#define ERR_NOISE 0x10U /*!< Noise error is detected. */ +#define ERR_IDLE 0x11U /*!< Idle error is detected. */ +#define ERR_FAULT 0x12U /*!< Fault error is detected. */ +#define ERR_BREAK 0x13U /*!< Break char is received during communication. */ +#define ERR_CRC 0x14U /*!< CRC error is detected. */ +#define ERR_ARBITR 0x15U /*!< A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 0x16U /*!< Protection error is detected. */ +#define ERR_UNDERFLOW 0x17U /*!< Underflow error is detected. */ +#define ERR_UNDERRUN 0x18U /*!< Underrun error is detected. */ +#define ERR_COMMON 0x19U /*!< Common error of a device. */ +#define ERR_LINSYNC 0x1AU /*!< LIN synchronization error is detected. */ +#define ERR_FAILED 0x1BU /*!< Requested functionality or process failed. */ +#define ERR_QFULL 0x1CU /*!< Queue is full. */ +#define ERR_PARAM_MASK 0x80U /*!< Invalid mask. */ +#define ERR_PARAM_MODE 0x81U /*!< Invalid mode. */ +#define ERR_PARAM_INDEX 0x82U /*!< Invalid index. */ +#define ERR_PARAM_DATA 0x83U /*!< Invalid data. */ +#define ERR_PARAM_SIZE 0x84U /*!< Invalid size. */ +#define ERR_PARAM_VALUE 0x85U /*!< Invalid value. */ +#define ERR_PARAM_RANGE 0x86U /*!< Invalid parameter's range or parameters' combination. */ +#define ERR_PARAM_LOW_VALUE 0x87U /*!< Invalid value (LOW part). */ +#define ERR_PARAM_HIGH_VALUE 0x88U /*!< Invalid value (HIGH part). */ +#define ERR_PARAM_ADDRESS 0x89U /*!< Invalid address. */ +#define ERR_PARAM_PARITY 0x8AU /*!< Invalid parity. */ +#define ERR_PARAM_WIDTH 0x8BU /*!< Invalid width. */ +#define ERR_PARAM_LENGTH 0x8CU /*!< Invalid length. */ +#define ERR_PARAM_ADDRESS_TYPE 0x8DU /*!< Invalid address type. */ +#define ERR_PARAM_COMMAND_TYPE 0x8EU /*!< Invalid command type. */ +#define ERR_PARAM_COMMAND 0x8FU /*!< Invalid command. */ +#define ERR_PARAM_RECIPIENT 0x90U /*!< Invalid recipient. */ +#define ERR_PARAM_BUFFER_COUNT 0x91U /*!< Invalid buffer count. */ +#define ERR_PARAM_ID 0x92U /*!< Invalid ID. */ +#define ERR_PARAM_GROUP 0x93U /*!< Invalid group. */ +#define ERR_PARAM_CHIP_SELECT 0x94U /*!< Invalid chip select. */ +#define ERR_PARAM_ATTRIBUTE_SET 0x95U /*!< Invalid set of attributes. */ +#define ERR_PARAM_SAMPLE_COUNT 0x96U /*!< Invalid sample count. */ +#define ERR_PARAM_CONDITION 0x97U /*!< Invalid condition. */ +#define ERR_PARAM_TICKS 0x98U /*!< Invalid ticks parameter. */ + +#endif /* __PE_Error_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h new file mode 100644 index 0000000..a7325ba --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/PE_Types.h @@ -0,0 +1,2586 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : PE_Types +** Version : Driver 01.01 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** PE_Types.h - contains definitions of basic types, +** register access macros and hardware specific macros +** which can be used in user application. +** Settings : +** Contents : +** No public methods +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file PE_Types.h +** @version 01.01 +** @brief +** PE_Types.h - contains definitions of basic types, +** register access macros and hardware specific macros +** which can be used in user application. +*/ +/*! +** @addtogroup PE_Types_module PE_Types module documentation +** @{ +*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +/* Standard ANSI C types */ +#include +#include "hal/derivative.h" +//#ifndef FALSE +// #define FALSE 0x00u /* Boolean value FALSE. FALSE is defined always as a zero value. */ +//#endif +//#ifndef TRUE // zentrale Definition in TMCM. +// #define TRUE 0x01u /* Boolean value TRUE. TRUE is defined always as a non zero value. */ +//#endif + +#ifndef NULL + #define NULL 0x00u +#endif + +/* PE types definition */ +#ifndef __cplusplus + #ifndef bool +typedef unsigned char bool; + #endif +#endif +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long dword; +typedef unsigned long long dlong; +typedef unsigned char TPE_ErrCode; +#ifndef TPE_Float +typedef float TPE_Float; +#endif +#ifndef char_t +typedef char char_t; +#endif + +/**********************************************************/ +/* Uniform multiplatform 8-bits peripheral access macros */ +/**********************************************************/ + +/* Enable maskable interrupts */ +#define __EI()\ + do {\ + /*lint -save -e950 Disable MISRA rule (1.1) checking. */\ + __asm("CPSIE f");\ + /*lint -restore Enable MISRA rule (1.1) checking. */\ + } while(0) + +/* Disable maskable interrupts */ +#define __DI() \ + do {\ + /*lint -save -e950 Disable MISRA rule (1.1) checking. */\ + __asm ("CPSID f");\ + /*lint -restore Enable MISRA rule (1.1) checking. */\ + } while(0) + + + +/* Save status register and disable interrupts */ +#define EnterCritical() \ + do {\ + uint8 SR_reg_local;\ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm ( \ + "MRS R0, FAULTMASK\n\t" \ + "CPSID f\n\t" \ + "STRB R0, %[output]" \ + : [output] "=m" (SR_reg_local)\ + :: "r0");\ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\ + if(++SR_lock == 1u) {\ + SR_reg = SR_reg_local;\ + }\ + } while(0) + + +/* Restore status register */ +#define ExitCritical() \ + do {\ + if(--SR_lock == 0u) { \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm ( \ + "ldrb r0, %[input]\n\t"\ + "msr FAULTMASK,r0;\n\t" \ + ::[input] "m" (SR_reg) \ + : "r0"); \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\ + }\ + } while(0) + + +#define PE_DEBUGHALT() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm( "BKPT 255") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + +#define PE_NOP() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm( "NOP") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + +#define PE_WFI() \ + /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\ + __asm("WFI") \ + /*lint -restore Enable MISRA rule (2.1,1.1) checking. */ + + +/* Interrupt definition template */ +/* For some reason GCC doesn't like this macro and gives out a warning, even when the compiled code works as intended + *#if !defined(PE_ISR) + * #define PE_ISR(ISR_name) \ + * void __attribute__ ((interrupt)) ISR_name(void) + *#endif +*/ +/* Logical Device Drivers (LDD) types */ + +/*! Logical Device Driver API version */ +#define PE_LDD_VERSION 0x0100U + +/* LDD driver states */ +#define PE_LDD_DRIVER_DISABLED_IN_CLOCK_CONFIGURATION 0x01U /*!< LDD driver is disabled in the selected clock configuration */ +#define PE_LDD_DRIVER_DISABLED_BY_USER 0x02U /*!< LDD driver is disabled by the user */ +#define PE_LDD_DRIVER_BUSY 0x04U /*!< LDD driver is busy */ + +/*! Macro to register component device structure */ +#define PE_LDD_RegisterDeviceStructure(ComponentIndex, DeviceStructure) (PE_LDD_DeviceDataList[ComponentIndex] = DeviceStructure) + +/*! Macro to unregister component device structure */ +#define PE_LDD_UnregisterDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex] = NULL) + +/*! Macro to get the component device structure */ +#define PE_LDD_GetDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex]) + +/* +** =========================================================================== +** LDD component ID specifying the component instance in the project. This ID +** is used internally as an index to the array of LDD device structures. +** =========================================================================== +*/ +#define PE_LDD_COMPONENT_BitIoLdd1_ID 0x00U +#define PE_LDD_COMPONENT_BitIoLdd2_ID 0x01U + +/* +** =================================================================== +** Global HAL types and constants +** =================================================================== +*/ +typedef uint32 LDD_TPinMask; /*!< Pin mask type. */ +typedef uint16 LDD_TError; /*!< Error type. */ +typedef uint32 LDD_TEventMask; /*!< Event mask type. */ +typedef uint8 LDD_TClockConfiguration; /*!< CPU clock configuration type. */ +typedef void LDD_TDeviceData; /*!< Pointer to private device structure managed and used by HAL components. */ +typedef void* LDD_TDeviceDataPtr; /*!< Obsolete type for backward compatibility. */ +typedef void LDD_TData; /*!< General pointer to data. */ +typedef void LDD_TUserData; /*!< Pointer to this type specifies the user or RTOS specific data will be passed as an event or callback parameter. */ + +/*! Driver operation mode type. */ +typedef enum { + DOM_NONE, + DOM_RUN, + DOM_WAIT, + DOM_SLEEP, + DOM_STOP +} LDD_TDriverOperationMode; + +typedef uint16 LDD_TDriverState; /*!< Driver state type. */ +typedef void LDD_TCallbackParam; /*!< Pointer to this type specifies the user data to be passed as a callback parameter. */ +typedef void (* LDD_TCallback)(LDD_TCallbackParam *CallbackParam); /*!< Callback type used for definition of callback functions. */ + +extern LDD_TDeviceData *PE_LDD_DeviceDataList[]; /*!< Array of LDD component device structures */ + + +/* Fills a memory area block by a specified value. Function defined in PE_LDD.c */ +extern void PE_FillMemory(register void* SourceAddressPtr, register uint8 c, register uint32 len); + + +/* +** =================================================================== +** RTOS specific types and constants +** =================================================================== +*/ +/* {Default RTOS Adapter} RTOS specific definition of type of Ioctl() command constants */ + + +/* +** =================================================================== +** Published RTOS settings and constants +** =================================================================== +*/ +/* {Default RTOS Adapter} No published RTOS settings */ + + +/* +** =================================================================== +** TimerUnit device types and constants +** =================================================================== +*/ +#define LDD_TIMERUNIT_ON_CHANNEL_0 0x01u /*!< OnChannel0 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_1 0x02u /*!< OnChannel1 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_2 0x04u /*!< OnChannel2 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_3 0x08u /*!< OnChannel3 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_4 0x10u /*!< OnChannel4 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_5 0x20u /*!< OnChannel5 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_6 0x40u /*!< OnChannel6 event mask value */ +#define LDD_TIMERUNIT_ON_CHANNEL_7 0x80u /*!< OnChannel7 event mask value */ +#define LDD_TIMERUNIT_ON_COUNTER_RESTART 0x0100u /*!< OnCounterRestart event mask value */ + +/*! Direction of counting */ +typedef enum { + DIR_UP, /*!< UP */ + DIR_DOWN /*!< DOWN */ +} LDD_TimerUnit_TCounterDirection; + +/*! Output action type (flip-flop action on overrun or compare match) */ +typedef enum { + OUTPUT_NONE, /*!< NONE */ + OUTPUT_TOGGLE, /*!< TOGGLE */ + OUTPUT_CLEAR, /*!< CLEAR */ + OUTPUT_SET /*!< SET */ +} LDD_TimerUnit_TOutAction; + +/*! Input edge type */ +typedef enum { + EDGE_NONE, /*!< NONE */ + EDGE_RISING, /*!< RISING */ + EDGE_FALLING, /*!< FALLING */ + EDGE_BOTH /*!< BOTH */ +} LDD_TimerUnit_TEdge; + +typedef float LDD_TimerUnit_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** CMT device types and constants +** =================================================================== +*/ +#define LDD_CMT_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** PPG device types and constants +** =================================================================== +*/ +#define LDD_PPG_ON_END 0x01u /*!< OnEnd event mask value */ + +typedef float LDD_PPG_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** PWM types and constants +** =================================================================== +*/ +#define LDD_PWM_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** Capture types and constants +** =================================================================== +*/ +#define LDD_CAPTURE_ON_CAPTURE 0x01u /*!< OnCapture event mask value */ +#define LDD_CAPTURE_ON_OVERRUN 0x02u /*!< OnOverrun event mask value */ + +/* +** =================================================================== +** TimerInt types and constants +** =================================================================== +*/ +#define LDD_TIMERINT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** TimerOut types and constants +** =================================================================== +*/ +#define LDD_TIMEROUT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** EventCntr types and constants +** =================================================================== +*/ +#define LDD_EVENTCNTR_ON_END 0x01u /*!< OnEnd event mask value */ + +/* +** =================================================================== +** FreeCntr types and constants +** =================================================================== +*/ +#define LDD_FREECNTR_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */ + +/* +** =================================================================== +** RealTime types and constants +** =================================================================== +*/ + +typedef float LDD_RealTime_Tfloat; /*!< Float type */ + +/* +** =================================================================== +** TimeDate types and constants +** =================================================================== +*/ +#define LDD_TIMEDATE_ON_ALARM 0x01u /*!< OnAlarm event mask value */ +#define LDD_TIMEDATE_ON_SECOND 0x02u /*!< OnSecond event mask value */ + +/*!< Time struct */ +typedef struct { + uint16 Hour; /*!< Hours (0 - 23) */ + uint16 Min; /*!< Minutes (0 - 59) */ + uint16 Sec; /*!< Seconds (0 - 59) */ + uint16 Sec100; /*!< Hundredths of seconds (0 - 99) */ +} LDD_TimeDate_TTimeRec; + +/*!< Date struct */ +typedef struct { + uint16 Year; /*!< Years (1998 - 2099) */ + uint16 Month; /*!< Months (1 - 12) */ + uint16 Day; /*!< Days (1 - 31) */ + uint16 DayOfWeek; /*!< Day of week (0-Sunday, .. 6-Saturday) */ +} LDD_TimeDate_TDateRec; + +/* +** =================================================================== +** UART device types and constants +** =================================================================== +*/ +#define LDD_SERIAL_RX_PIN 0x01u /*!< Receiver pin mask */ +#define LDD_SERIAL_TX_PIN 0x02u /*!< Transmitter pin mask */ +#define LDD_SERIAL_CTS_PIN 0x04u /*!< CTS pin mask */ +#define LDD_SERIAL_RTS_PIN 0x08u /*!< RTS pin mask */ + +#define LDD_SERIAL_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */ +#define LDD_SERIAL_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */ +#define LDD_SERIAL_ON_BREAK 0x04u /*!< OnBreak event mask */ +#define LDD_SERIAL_ON_TXCOMPLETE 0x08u /*!< OnTxComplete event mask */ +#define LDD_SERIAL_ON_ERROR 0x10u /*!< OnError event mask */ + +#define LDD_SERIAL_RX_OVERRUN 0x01u /*!< Receiver overrun */ +#define LDD_SERIAL_PARITY_ERROR 0x02u /*!< Parity error */ +#define LDD_SERIAL_FRAMING_ERROR 0x04u /*!< Framing error */ +#define LDD_SERIAL_NOISE_ERROR 0x08u /*!< Noise error */ + +typedef uint32 LDD_SERIAL_TError; /*!< Serial communication error type */ + +typedef uint8 LDD_SERIAL_TDataWidth; /*!< Bit length type. The number of bits transmitted by one character. */ + +typedef uint16 LDD_SERIAL_TSize; /*!< Type specifying the length of the data or buffer. */ + +typedef uint8 LDD_SERIAL_TBaudMode; /*!< Type specifying the baud mode. */ + +/*! Type specifying the parity. */ +typedef enum { + LDD_SERIAL_PARITY_UNDEF, /*!< Undefined parity */ + LDD_SERIAL_PARITY_NONE, /*!< Parity none */ + LDD_SERIAL_PARITY_ODD, /*!< Parity odd */ + LDD_SERIAL_PARITY_EVEN, /*!< Parity even */ + LDD_SERIAL_PARITY_MARK, /*!< Parity mark */ + LDD_SERIAL_PARITY_SPACE /*!< Parity space */ +} LDD_SERIAL_TParity; + +/*! Type specifying the stop bit length. */ +typedef enum { + LDD_SERIAL_STOP_BIT_LEN_UNDEF, /*!< Undefined bit length */ + LDD_SERIAL_STOP_BIT_LEN_1, /*!< 1 bit length */ + LDD_SERIAL_STOP_BIT_LEN_1_5, /*!< 1.5 bit length */ + LDD_SERIAL_STOP_BIT_LEN_2 /*!< 2 bit length */ +} LDD_SERIAL_TStopBitLen; + +/*! Communication statistics */ +typedef struct { + uint32 ReceivedChars; /*!< Number of received characters */ + uint32 SentChars; /*!< Number of transmitted characters */ + uint32 ReceivedBreaks; /*!< Number of received break characters */ + uint32 ParityErrors; /*!< Number of receiver parity errors */ + uint32 FramingErrors; /*!< Number of receiver framing errors */ + uint32 OverrunErrors; /*!< Number of receiver overrun errors */ + uint32 NoiseErrors; /*!< Number of receiver noise errors */ +} LDD_SERIAL_TStats; + +/*! Type specifying the loop mode operation. */ +typedef enum { + LOOPMODE_UNDEF, /*!< Undefined loop mode */ + LOOPMODE_NORMAL, /*!< Normal operation */ + LOOPMODE_AUTO_ECHO, /*!< Auto echo mode */ + LOOPMODE_LOCAL_LOOPBACK, /*!< Local loopback mode */ + LOOPMODE_REMOTE_LOOPBACK /*!< Remote loopback mode */ +} LDD_SERIAL_TLoopMode; + + +/* +** =================================================================== +** ADC device types and constants +** =================================================================== +*/ + +#define LDD_ADC_CHANNEL_0_PIN 0x01u /*!< Channel 0 pin mask */ +#define LDD_ADC_CHANNEL_1_PIN 0x02u /*!< Channel 1 pin mask */ +#define LDD_ADC_CHANNEL_2_PIN 0x04u /*!< Channel 2 pin mask */ +#define LDD_ADC_CHANNEL_3_PIN 0x08u /*!< Channel 3 pin mask */ +#define LDD_ADC_CHANNEL_4_PIN 0x10u /*!< Channel 4 pin mask */ +#define LDD_ADC_CHANNEL_5_PIN 0x20u /*!< Channel 5 pin mask */ +#define LDD_ADC_CHANNEL_6_PIN 0x40u /*!< Channel 6 pin mask */ +#define LDD_ADC_CHANNEL_7_PIN 0x80u /*!< Channel 7 pin mask */ +#define LDD_ADC_CHANNEL_8_PIN 0x0100u /*!< Channel 8 pin mask */ +#define LDD_ADC_CHANNEL_9_PIN 0x0200u /*!< Channel 9 pin mask */ +#define LDD_ADC_CHANNEL_10_PIN 0x0400u /*!< Channel 10 pin mask */ +#define LDD_ADC_CHANNEL_11_PIN 0x0800u /*!< Channel 11 pin mask */ +#define LDD_ADC_CHANNEL_12_PIN 0x1000u /*!< Channel 12 pin mask */ +#define LDD_ADC_CHANNEL_13_PIN 0x2000u /*!< Channel 13 pin mask */ +#define LDD_ADC_CHANNEL_14_PIN 0x4000u /*!< Channel 14 pin mask */ +#define LDD_ADC_CHANNEL_15_PIN 0x8000u /*!< Channel 15 pin mask */ +#define LDD_ADC_CHANNEL_16_PIN 0x00010000u /*!< Channel 16 pin mask */ +#define LDD_ADC_CHANNEL_17_PIN 0x00020000u /*!< Channel 17 pin mask */ +#define LDD_ADC_CHANNEL_18_PIN 0x00040000u /*!< Channel 18 pin mask */ +#define LDD_ADC_CHANNEL_19_PIN 0x00080000u /*!< Channel 19 pin mask */ +#define LDD_ADC_CHANNEL_20_PIN 0x00100000u /*!< Channel 20 pin mask */ +#define LDD_ADC_CHANNEL_21_PIN 0x00200000u /*!< Channel 21 pin mask */ +#define LDD_ADC_CHANNEL_22_PIN 0x00400000u /*!< Channel 22 pin mask */ +#define LDD_ADC_CHANNEL_23_PIN 0x00800000u /*!< Channel 23 pin mask */ +#define LDD_ADC_CHANNEL_24_PIN 0x01000000u /*!< Channel 24 pin mask */ +#define LDD_ADC_CHANNEL_25_PIN 0x02000000u /*!< Channel 25 pin mask */ +#define LDD_ADC_CHANNEL_26_PIN 0x04000000u /*!< Channel 26 pin mask */ +#define LDD_ADC_CHANNEL_27_PIN 0x08000000u /*!< Channel 27 pin mask */ +#define LDD_ADC_CHANNEL_28_PIN 0x10000000u /*!< Channel 28 pin mask */ +#define LDD_ADC_CHANNEL_29_PIN 0x20000000u /*!< Channel 29 pin mask */ +#define LDD_ADC_CHANNEL_30_PIN 0x40000000u /*!< Channel 30 pin mask */ +#define LDD_ADC_CHANNEL_31_PIN 0x80000000u /*!< Channel 31 pin mask */ +#define LDD_ADC_CHANNEL_32_PIN 0x01u /*!< Channel 32 pin mask */ +#define LDD_ADC_CHANNEL_33_PIN 0x02u /*!< Channel 33 pin mask */ +#define LDD_ADC_CHANNEL_34_PIN 0x04u /*!< Channel 34 pin mask */ +#define LDD_ADC_CHANNEL_35_PIN 0x08u /*!< Channel 35 pin mask */ +#define LDD_ADC_CHANNEL_36_PIN 0x10u /*!< Channel 36 pin mask */ +#define LDD_ADC_CHANNEL_37_PIN 0x20u /*!< Channel 37 pin mask */ +#define LDD_ADC_CHANNEL_38_PIN 0x40u /*!< Channel 38 pin mask */ +#define LDD_ADC_CHANNEL_39_PIN 0x80u /*!< Channel 39 pin mask */ +#define LDD_ADC_CHANNEL_40_PIN 0x0100u /*!< Channel 40 pin mask */ +#define LDD_ADC_CHANNEL_41_PIN 0x0200u /*!< Channel 41 pin mask */ +#define LDD_ADC_CHANNEL_42_PIN 0x0400u /*!< Channel 42 pin mask */ +#define LDD_ADC_CHANNEL_43_PIN 0x0800u /*!< Channel 43 pin mask */ +#define LDD_ADC_CHANNEL_44_PIN 0x1000u /*!< Channel 44 pin mask */ +#define LDD_ADC_CHANNEL_45_PIN 0x2000u /*!< Channel 45 pin mask */ +#define LDD_ADC_CHANNEL_46_PIN 0x4000u /*!< Channel 46 pin mask */ +#define LDD_ADC_CHANNEL_47_PIN 0x8000u /*!< Channel 47 pin mask */ +#define LDD_ADC_CHANNEL_48_PIN 0x00010000u /*!< Channel 48 pin mask */ +#define LDD_ADC_CHANNEL_49_PIN 0x00020000u /*!< Channel 49 pin mask */ +#define LDD_ADC_CHANNEL_50_PIN 0x00040000u /*!< Channel 50 pin mask */ +#define LDD_ADC_CHANNEL_51_PIN 0x00080000u /*!< Channel 51 pin mask */ +#define LDD_ADC_CHANNEL_52_PIN 0x00100000u /*!< Channel 52 pin mask */ +#define LDD_ADC_CHANNEL_53_PIN 0x00200000u /*!< Channel 53 pin mask */ +#define LDD_ADC_CHANNEL_54_PIN 0x00400000u /*!< Channel 54 pin mask */ +#define LDD_ADC_CHANNEL_55_PIN 0x00800000u /*!< Channel 55 pin mask */ +#define LDD_ADC_CHANNEL_56_PIN 0x01000000u /*!< Channel 56 pin mask */ +#define LDD_ADC_CHANNEL_57_PIN 0x02000000u /*!< Channel 57 pin mask */ +#define LDD_ADC_CHANNEL_58_PIN 0x04000000u /*!< Channel 58 pin mask */ +#define LDD_ADC_CHANNEL_59_PIN 0x08000000u /*!< Channel 59 pin mask */ +#define LDD_ADC_CHANNEL_60_PIN 0x10000000u /*!< Channel 60 pin mask */ +#define LDD_ADC_CHANNEL_61_PIN 0x20000000u /*!< Channel 61 pin mask */ +#define LDD_ADC_CHANNEL_62_PIN 0x40000000u /*!< Channel 62 pin mask */ +#define LDD_ADC_CHANNEL_63_PIN 0x80000000u /*!< Channel 63 pin mask */ + +#define LDD_ADC_TRIGGER_0_PIN 0x01u /*!< Trigger 0 pin mask */ +#define LDD_ADC_TRIGGER_1_PIN 0x02u /*!< Trigger 1 pin mask */ + +#define LDD_ADC_LOW_VOLT_REF_PIN 0x01u /*!< Low voltage reference pin mask */ +#define LDD_ADC_HIGH_VOLT_REF_PIN 0x02u /*!< High voltage reference pin mask */ + +#define LDD_ADC_ON_MEASUREMENT_COMPLETE 0x40u /*!< OnMeasurementComplete event mask */ +#define LDD_ADC_ON_ERROR 0x80u /*!< OnError event mask */ + +#define LDD_ADC_DMA_ERROR 0x01u /*!< DMA error mask */ + +typedef uint32 LDD_ADC_TErrorMask; /*!< ADC error type */ + +/*! Structure pins for pin connection method */ +typedef struct { + uint32 Channel0_31PinMask; /*!< Channel pin mask for channels 0 through 31 */ + uint32 Channel32_63PinMask; /*!< Channel pin mask for channels 32 through 63 */ + uint16 TriggerPinMask; /*!< Trigger pin mask */ + uint8 VoltRefPinMask; /*!< Voltage reference pin mask */ +} LDD_ADC_TPinMask; + +/*! Structure used to describing one sample */ +typedef struct { + uint8 ChannelIdx; /*!< Channel index */ +} LDD_ADC_TSample; + +/*! Type specifying the ADC compare mode */ +typedef enum { + LDD_ADC_LESS_THAN = 0x00u, /*!< Compare true if the result is less than the Low compare value */ + LDD_ADC_GREATER_THAN_OR_EQUAL = 0x01u, /*!< Compare true if the result is greater than or equal to Low compare value */ + LDD_ADC_INSIDE_RANGE_INCLUSIVE = 0x02u, /*!< Compare true if the result is greater than or equal to Low compare value and the result is less than or equal to High compare value */ + LDD_ADC_INSIDE_RANGE_NOT_INCLUSIVE = 0x03u, /*!< Compare true if the result is greater than Low compare value and the result is less than High compare value */ + LDD_ADC_OUTSIDE_RANGE_INCLUSIVE = 0x04u, /*!< Compare true if the result is less than or equal to Low compare value or the result is greater than or equal to High compare value */ + LDD_ADC_OUTSIDE_RANGE_NOT_INCLUSIVE = 0x05u /*!< Compare true if the result is less than Low compare value or the result is greater than High compare value */ +} LDD_ADC_TCompareMode; + +/* +** =================================================================== +** I2C device types and constants +** =================================================================== +*/ + +#define LDD_I2C_SDA_PIN 0x01u /*!< SDA pin mask */ +#define LDD_I2C_SCL_PIN 0x02u /*!< SCL pin mask */ + +#define LDD_I2C_ON_MASTER_BLOCK_SENT 0x0001u /*!< OnMasterBlockSent event mask */ +#define LDD_I2C_ON_MASTER_BLOCK_RECEIVED 0x0002u /*!< OnMasterBlockReceived event mask */ +#define LDD_I2C_ON_SLAVE_BLOCK_SENT 0x0004u /*!< OnSlaveBlockSent event mask */ +#define LDD_I2C_ON_SLAVE_BLOCK_RECEIVED 0x0008u /*!< OnSlaveBlockReceived event mask */ +#define LDD_I2C_ON_SLAVE_TX_REQUEST 0x0010u /*!< OnSlaveTxRequest event mask */ +#define LDD_I2C_ON_SLAVE_RX_REQUEST 0x0020u /*!< OnSlaveRxRequest event mask */ +#define LDD_I2C_ON_ERROR 0x0040u /*!< OnError event mask */ +#define LDD_I2C_ON_SLAVE_SM_BUS_CALL_ADDR 0x0080u /*!< OnSlaveSMBusCallAddr event mask */ +#define LDD_I2C_ON_SLAVE_SM_BUS_ALERT_RESPONSE 0x0100u /*!< OnSlaveSMBusAlertResponse event mask */ +#define LDD_I2C_ON_SLAVE_GENERAL_CALL_ADDR 0x0200u /*!< OnSlaveGeneralCallAddr event mask */ +#define LDD_I2C_ON_MASTER_BYTE_RECEIVED 0x0400u /*!< OnMasterByteReceived event mask */ +#define LDD_I2C_ON_SLAVE_BYTE_RECEIVED 0x0800u /*!< OnMasterByteReceived event mask */ +#define LDD_I2C_ON_BUS_START_DETECTED 0x1000u /*!< OnBusStartDetected event mask */ +#define LDD_I2C_ON_BUS_STOP_DETECTED 0x2000u /*!< OnBusStopDetected event mask */ + +#define LDD_I2C_SLAVE_TX_UNDERRUN 0x0001u /*!< SlaveTxUnderrun error mask */ +#define LDD_I2C_SLAVE_RX_OVERRUN 0x0002u /*!< SlaveRxOverrun error mask */ +#define LDD_I2C_ARBIT_LOST 0x0004u /*!< ArbitLost error mask */ +#define LDD_I2C_MASTER_NACK 0x0008u /*!< MasterNACK error mask */ +#define LDD_I2C_SCL_LOW_TIMEOUT 0x0010u /*!< SCLLowTimeout error mask */ +#define LDD_I2C_SDA_LOW_TIMEOUT 0x0020u /*!< SDALowTimeout error mask */ +#define LDD_I2C_SLAVE_NACK 0x0040u /*!< SlaveNACK error mask */ + +typedef uint16 LDD_I2C_TSize; /*!< Type specifying the length of the data or buffer. */ +typedef uint16 LDD_I2C_TAddr; /*!< Type specifying the address variable */ +typedef uint16 LDD_I2C_TErrorMask; /*!< Type specifying the error mask type. */ +typedef bool LDD_I2C_TMode; /*!< Type specifynng the Actual operating mode */ + +/*! Type specifying the address type */ +typedef enum { + LDD_I2C_ADDRTYPE_7BITS, /*!< 7 bits address */ + LDD_I2C_ADDRTYPE_10BITS, /*!< 10 bits address */ + LDD_I2C_ADDRTYPE_GENERAL_CALL /*!< General call address */ +} LDD_I2C_TAddrType; + +/*! Type specifying generate the stop condition */ +typedef enum { + LDD_I2C_NO_SEND_STOP, /*!< Do not send stop signal */ + LDD_I2C_SEND_STOP /*!< Send stop signal */ +} LDD_I2C_TSendStop; + +/*! Type specifying the I2C state of BUS. */ +typedef enum { + LDD_I2C_BUSY, /*!< The bus is busy */ + LDD_I2C_IDLE /*!< The bus is idle */ +} LDD_I2C_TBusState; + +/*! Type specifying the I2C byte acknowledge response. */ +typedef enum { + LDD_I2C_ACK_BYTE, /*!< Byte acknowledged */ + LDD_I2C_NACK_BYTE /*!< Byte not acknowledged */ +} LDD_I2C_TAckType; + +/*! Communication statistics */ +typedef struct { + uint32 MasterSentChars; /*!< Number of master transmitted characters. */ + uint32 MasterReceivedChars; /*!< Number of master received characters. */ + uint32 MasterNacks; /*!< Number of no acknowledges. */ + uint32 ArbitLost; /*!< Number of lost the bus arbitration. */ + uint32 SlaveSentChars; /*!< Number of slave transmitted characters. */ + uint32 SlaveReceivedChars; /*!< Number of slave received characters. */ + uint32 SlaveTxUnderrun; /*!< Number of slave underrun. */ + uint32 SlaveRxOverrun; /*!< Number of slave overrun. */ + uint32 SlaveGeneralCallAddr; /*!< Number of a general call address. */ + uint32 SlaveSmBusCallAddr; /*!< Number of a SMBus call address. */ + uint32 SlaveSmBusAlertResponse; /*!< Number of slave SMBus alert response received. */ + uint32 SCLLowTimeout; /*!< Number of SCL low timeout occur. */ + uint32 SDALowTimeout; /*!< Number of SCL low timeout occur. */ +} LDD_I2C_TStats; + + +/* +** =================================================================== +** SegLCD device types and constants +** =================================================================== +*/ + +#define LDD_SEGLCD_ON_FRAME_FREQUENCY 0x0001u /*!< OnFrameFrequency event mask */ +#define LDD_SEGLCD_ON_FAULT_DETECT_COMPLETE 0x0002u /*!< OnFaultDetectComplete event mask */ + +typedef uint8 LDD_SegLCD_TPinIndex; /*!< Type specifying the segment LCD pin index variable */ +typedef uint8 LDD_SegLCD_TFrontplaneData; /*!< Type specifying the frontplane/backplane segment variable */ +typedef uint8 LDD_SegLCD_TFaultValue; /*!< Type specifying the frontplane/backplane segment variable */ + +/*! Types specifying the segment LCD blinking. */ +typedef enum { + LDD_SEGLCD_BLINK_OFF, /*!< Disables display blinking */ + LDD_SEGLCD_BLINK_ALL, /*!< Display blank during the blink period */ + LDD_SEGLCD_BLINK_ALL_ALTERNATE /*!< Blinking between alternate backplane */ +} LDD_SegLCD_TBlinking; + +/*! Segment LCD blank state type. */ +typedef enum { + LDD_SEGLCD_BLANK_STATE, /*!< Blank display mode */ + LDD_SEGLCD_NORMAL_STATE, /*!< Normal display mode */ + LDD_SEGLCD_ALTERNATE_STATE /*!< Alternate display mode */ +} LDD_SegLCD_TSetBlank; + +/*! Segment LCD pin type (frontplane/backplane) */ +typedef enum { + LDD_SEGLCD_BACKPLANE_PIN, /*!< Backplane pin */ + LDD_SEGLCD_FRONTPLANE_PIN /*!< Frontplane pin */ +} LDD_SegLCD_TPinType; + + +/* +** =================================================================== +** GPIO device types and constants +** =================================================================== +*/ + +#define LDD_GPIO_PIN_0 0x01u /*!< Pin 0 inside the port */ +#define LDD_GPIO_PIN_1 0x02u /*!< Pin 1 inside the port */ +#define LDD_GPIO_PIN_2 0x04u /*!< Pin 2 inside the port */ +#define LDD_GPIO_PIN_3 0x08u /*!< Pin 3 inside the port */ +#define LDD_GPIO_PIN_4 0x10u /*!< Pin 4 inside the port */ +#define LDD_GPIO_PIN_5 0x20u /*!< Pin 5 inside the port */ +#define LDD_GPIO_PIN_6 0x40u /*!< Pin 6 inside the port */ +#define LDD_GPIO_PIN_7 0x80u /*!< Pin 7 inside the port */ +#define LDD_GPIO_PIN_8 0x0100u /*!< Pin 8 inside the port */ +#define LDD_GPIO_PIN_9 0x0200u /*!< Pin 9 inside the port */ +#define LDD_GPIO_PIN_10 0x0400u /*!< Pin 10 inside the port */ +#define LDD_GPIO_PIN_11 0x0800u /*!< Pin 11 inside the port */ +#define LDD_GPIO_PIN_12 0x1000u /*!< Pin 12 inside the port */ +#define LDD_GPIO_PIN_13 0x2000u /*!< Pin 13 inside the port */ +#define LDD_GPIO_PIN_14 0x4000u /*!< Pin 14 inside the port */ +#define LDD_GPIO_PIN_15 0x8000u /*!< Pin 15 inside the port */ +#define LDD_GPIO_PIN_16 0x00010000u /*!< Pin 16 inside the port */ +#define LDD_GPIO_PIN_17 0x00020000u /*!< Pin 17 inside the port */ +#define LDD_GPIO_PIN_18 0x00040000u /*!< Pin 18 inside the port */ +#define LDD_GPIO_PIN_19 0x00080000u /*!< Pin 19 inside the port */ +#define LDD_GPIO_PIN_20 0x00100000u /*!< Pin 20 inside the port */ +#define LDD_GPIO_PIN_21 0x00200000u /*!< Pin 21 inside the port */ +#define LDD_GPIO_PIN_22 0x00400000u /*!< Pin 22 inside the port */ +#define LDD_GPIO_PIN_23 0x00800000u /*!< Pin 23 inside the port */ +#define LDD_GPIO_PIN_24 0x01000000u /*!< Pin 24 inside the port */ +#define LDD_GPIO_PIN_25 0x02000000u /*!< Pin 25 inside the port */ +#define LDD_GPIO_PIN_26 0x04000000u /*!< Pin 26 inside the port */ +#define LDD_GPIO_PIN_27 0x08000000u /*!< Pin 27 inside the port */ +#define LDD_GPIO_PIN_28 0x10000000u /*!< Pin 28 inside the port */ +#define LDD_GPIO_PIN_29 0x20000000u /*!< Pin 29 inside the port */ +#define LDD_GPIO_PIN_30 0x40000000u /*!< Pin 30 inside the port */ +#define LDD_GPIO_PIN_31 0x80000000u /*!< Pin 31 inside the port */ + +#define LDD_GPIO_ON_PORT_EVENT 0x01u /*!< OnPortEvent event mask */ + +typedef uint32 LDD_GPIO_TBitField; /*!< Abstract type specifying the bit field within the port. */ + +/*! Defines condition when event is invoked. */ +typedef enum { + LDD_GPIO_DISABLED = 0x00u, /*!< Event doesn't invoke */ + LDD_GPIO_LOW = 0x00080000u, /*!< Event when logic zero */ + LDD_GPIO_HIGH = 0x000C0000u, /*!< Event when logic one */ + LDD_GPIO_RISING = 0x00090000u, /*!< Event on rising edge */ + LDD_GPIO_FALLING = 0x000A0000u, /*!< Event on falling edge */ + LDD_GPIO_BOTH = 0x000B0000u /*!< Event on rising and falling edge */ +} LDD_GPIO_TEventCondition; /*!< Defines condition when event is invoked. */ + +#define LDD_GPIO_EVENT_CONDITIONS_MASK 0x000F0000u + +/* +** =================================================================== +** BITSIO device types and constants +** =================================================================== +*/ +#define LDD_BITSIO_PIN_0 0x01U /*!< Pin 0 inside pin list of component */ +#define LDD_BITSIO_PIN_1 0x02U /*!< Pin 1 inside pin list of component */ +#define LDD_BITSIO_PIN_2 0x04U /*!< Pin 2 inside pin list of component */ +#define LDD_BITSIO_PIN_3 0x08U /*!< Pin 3 inside pin list of component */ +#define LDD_BITSIO_PIN_4 0x10U /*!< Pin 4 inside pin list of component */ +#define LDD_BITSIO_PIN_5 0x20U /*!< Pin 5 inside pin list of component */ +#define LDD_BITSIO_PIN_6 0x40U /*!< Pin 6 inside pin list of component */ +#define LDD_BITSIO_PIN_7 0x80U /*!< Pin 7 inside pin list of component */ +#define LDD_BITSIO_PIN_8 0x0100U /*!< Pin 8 inside pin list of component */ +#define LDD_BITSIO_PIN_9 0x0200U /*!< Pin 9 inside pin list of component */ +#define LDD_BITSIO_PIN_10 0x0400U /*!< Pin 10 inside pin list of component */ +#define LDD_BITSIO_PIN_11 0x0800U /*!< Pin 11 inside pin list of component */ +#define LDD_BITSIO_PIN_12 0x1000U /*!< Pin 12 inside pin list of component */ +#define LDD_BITSIO_PIN_13 0x2000U /*!< Pin 13 inside pin list of component */ +#define LDD_BITSIO_PIN_14 0x4000U /*!< Pin 14 inside pin list of component */ +#define LDD_BITSIO_PIN_15 0x8000U /*!< Pin 15 inside pin list of component */ +#define LDD_BITSIO_PIN_16 0x00010000U /*!< Pin 16 inside pin list of component */ +#define LDD_BITSIO_PIN_17 0x00020000U /*!< Pin 17 inside pin list of component */ +#define LDD_BITSIO_PIN_18 0x00040000U /*!< Pin 18 inside pin list of component */ +#define LDD_BITSIO_PIN_19 0x00080000U /*!< Pin 19 inside pin list of component */ +#define LDD_BITSIO_PIN_20 0x00100000U /*!< Pin 20 inside pin list of component */ +#define LDD_BITSIO_PIN_21 0x00200000U /*!< Pin 21 inside pin list of component */ +#define LDD_BITSIO_PIN_22 0x00400000U /*!< Pin 22 inside pin list of component */ +#define LDD_BITSIO_PIN_23 0x00800000U /*!< Pin 23 inside pin list of component */ +#define LDD_BITSIO_PIN_24 0x01000000U /*!< Pin 24 inside pin list of component */ +#define LDD_BITSIO_PIN_25 0x02000000U /*!< Pin 25 inside pin list of component */ +#define LDD_BITSIO_PIN_26 0x04000000U /*!< Pin 26 inside pin list of component */ +#define LDD_BITSIO_PIN_27 0x08000000U /*!< Pin 27 inside pin list of component */ +#define LDD_BITSIO_PIN_28 0x10000000U /*!< Pin 28 inside pin list of component */ +#define LDD_BITSIO_PIN_29 0x20000000U /*!< Pin 29 inside pin list of component */ +#define LDD_BITSIO_PIN_30 0x40000000U /*!< Pin 30 inside pin list of component */ +#define LDD_BITSIO_PIN_31 0x80000000U /*!< Pin 31 inside pin list of component */ + +/* +** =================================================================== +** Ethernet device types and constants +** =================================================================== +*/ + +#define LDD_ETH_MDC_PIN 0x01u /*!< MDC pin mask */ +#define LDD_ETH_MDIO_PIN 0x02u /*!< MDIO pin mask */ +#define LDD_ETH_COL_PIN 0x04u /*!< COL pin mask */ +#define LDD_ETH_CRS_PIN 0x08u /*!< CRS pin mask */ +#define LDD_ETH_TXCLK_PIN 0x10u /*!< TXCLK pin mask */ +#define LDD_ETH_TXD0_PIN 0x20u /*!< TXD0 pin mask */ +#define LDD_ETH_TXD1_PIN 0x40u /*!< TXD1 pin mask */ +#define LDD_ETH_TXD2_PIN 0x80u /*!< TXD2 pin mask */ +#define LDD_ETH_TXD3_PIN 0x0100u /*!< TXD3 pin mask */ +#define LDD_ETH_TXEN_PIN 0x0200u /*!< TXEN pin mask */ +#define LDD_ETH_TXER_PIN 0x0400u /*!< TXER pin mask */ +#define LDD_ETH_RXCLK_PIN 0x0800u /*!< RXCLK pin mask */ +#define LDD_ETH_RXDV_PIN 0x1000u /*!< RXDV pin mask */ +#define LDD_ETH_RXD0_PIN 0x2000u /*!< RXD0 pin mask */ +#define LDD_ETH_RXD1_PIN 0x4000u /*!< RXD1 pin mask */ +#define LDD_ETH_RXD2_PIN 0x8000u /*!< RXD2 pin mask */ +#define LDD_ETH_RXD3_PIN 0x00010000u /*!< RXD3 pin mask */ +#define LDD_ETH_RXER_PIN 0x00020000u /*!< RXER pin mask */ + +#define LDD_ETH_ON_FRAME_TRANSMITTED 0x01u /*!< OnFrameTransmitted event mask */ +#define LDD_ETH_ON_FRAME_TRANSMITTED_TIMESTAMPED 0x02u /*!< OnFrameTransmittedTimestamped event mask */ +#define LDD_ETH_ON_FRAME_RECEIVED 0x04u /*!< OnFrameReceived event mask */ +#define LDD_ETH_ON_FRAME_RECEIVED_TIMESTAMPED 0x08u /*!< OnFrameReceivedTimestamped event mask */ +#define LDD_ETH_ON_MII_FINISHED 0x10u /*!< OnMIIFinished event mask */ +#define LDD_ETH_ON_FATAL_ERROR 0x20u /*!< OnFatalError event mask */ +#define LDD_ETH_ON_WAKE_UP 0x40u /*!< OnWakeUp event mask */ + +typedef uint8 LDD_ETH_TMACAddress[6]; /*!< Ethernet MAC address */ + +/*! Ethernet duplex mode */ +typedef enum { + LDD_ETH_FULL_DUPLEX, /*!< Full duplex mode */ + LDD_ETH_HALF_DUPLEX /*!< Half duplex mode */ +} LDD_ETH_TDuplexMode; + +/*! Ethernet address filter mode options */ +typedef enum { + LDD_ETH_PROMISC, /*!< Promiscuous mode */ + LDD_ETH_REJECT_BC, /*!< Reject broadcast frames */ + LDD_ETH_ACCEPT_BC /*!< Accept broadcast frames */ +} LDD_ETH_TFilterMode; + +/*! Ethernet sleep mode options */ +typedef enum { + LDD_ETH_ENABLED, /*!< Sleep mode enabled */ + LDD_ETH_ENABLED_WITH_WAKEUP, /*!< Sleep mode enabled, waiting for wake-up */ + LDD_ETH_DISABLED /*!< Sleep mode disabled */ +} LDD_ETH_TSleepMode; + +/*! Ethernet frame buffer (fragment) descriptor */ +typedef struct { + uint8 *DataPtr; /*!< Pointer to buffer data */ + uint16 Size; /*!< Buffer data size */ +} LDD_ETH_TBufferDesc; + +typedef LDD_ETH_TBufferDesc* LDD_ETH_TBufferDescPtr; /*!< Frame buffer descriptor pointer type */ + +/*! Ethernet communication statistics */ +typedef struct { + uint32 TxRMONDropEvents; /*!< Count of frames not counted correctly */ + uint32 TxRMONOctets; /*!< Octet count for frames transmitted without error */ + uint32 TxRMONPackets; /*!< Transmitted packet count */ + uint32 TxRMONBroadcastPackets; /*!< Transmitted broadcast packets */ + uint32 TxRMONMulticastPackets; /*!< Transmitted multicast packets */ + uint32 TxRMONCRCAlignErrors; /*!< Transmitted packets with CRC or alignment error */ + uint32 TxRMONUndersizePackets; /*!< Transmitted packets smaller than 64 bytes with good CRC */ + uint32 TxRMONOversizePackets; /*!< Transmitted packets greater than max. frame length with good CRC */ + uint32 TxRMONFragments; /*!< Transmitted packets smaller than 64 bytes with bad CRC */ + uint32 TxRMONJabbers; /*!< Transmitted packets greater than max. frame length with bad CRC */ + uint32 TxRMONCollisions; /*!< Transmit collision count */ + uint32 TxRMONPackets64Octets; /*!< Transmitted 64 byte packets */ + uint32 TxRMONPackets65To127Octets; /*!< Transmitted 65 to 127 byte packets */ + uint32 TxRMONPackets128To255Octets; /*!< Transmitted 128 to 255 byte packets */ + uint32 TxRMONPackets256To511Octets; /*!< Transmitted 256 to 511 byte packets */ + uint32 TxRMONPackets512To1023Octets; /*!< Transmitted 512 to 1023 byte packets */ + uint32 TxRMONPackets1024To2047Octets; /*!< Transmitted 1024 to 2047 byte packets */ + uint32 TxRMONPacketsGreaterThan2048Octets; /*!< Transmitted packets greater than 2048 byte */ + uint32 TxIEEEDrop; /*!< Count of frames not counted correctly */ + uint32 TxIEEEFrameOK; /*!< Frames transmitted OK */ + uint32 TxIEEESingleCollision; /*!< Frames transmitted with single collision */ + uint32 TxIEEEMultipleCollisions; /*!< Frames transmitted with multiple collisions */ + uint32 TxIEEEDeferralDelay; /*!< Frames transmitted after deferral delay */ + uint32 TxIEEELateCollision; /*!< Frames transmitted with late collision */ + uint32 TxIEEEExcessiveCollision; /*!< Frames transmitted with excessive collisions */ + uint32 TxIEEEFIFOUnderrun; /*!< Frames transmitted with transmit FIFO underrun */ + uint32 TxIEEECarrierSenseError; /*!< Frames transmitted with carrier sense error */ + uint32 TxIEEESQEError; /*!< Frames transmitted with SQE error */ + uint32 TxIEEEPauseFrame; /*!< Flow control pause frames transmitted */ + uint32 TxIEEEOctetsOK; /*!< Octet count for frames transmitted without error */ + uint32 RxRMONDropEvents; /*!< Count of frames not counted correctly */ + uint32 RxRMONOctets; /*!< Octet count for frames recieved without error */ + uint32 RxRMONPackets; /*!< Received packet count */ + uint32 RxRMONBroadcastPackets; /*!< Received broadcast packets */ + uint32 RxRMONMulticastPackets; /*!< Received multicast packets */ + uint32 RxRMONCRCAlignErrors; /*!< Received packets with CRC or alignment error */ + uint32 RxRMONUndersizePackets; /*!< Received packets smaller than 64 bytes with good CRC */ + uint32 RxRMONOversizePackets; /*!< Received packets greater than max. frame length with good CRC */ + uint32 RxRMONFragments; /*!< Received packets smaller than 64 bytes with bad CRC */ + uint32 RxRMONJabbers; /*!< Received packets greater than max. frame length with bad CRC */ + uint32 RxRMONPackets64Octets; /*!< Received 64 byte packets */ + uint32 RxRMONPackets65To127Octets; /*!< Received 65 to 127 byte packets */ + uint32 RxRMONPackets128To255Octets; /*!< Received 128 to 255 byte packets */ + uint32 RxRMONPackets256To511Octets; /*!< Received 256 to 511 byte packets */ + uint32 RxRMONPackets512To1023Octets; /*!< Received 512 to 1023 byte packets */ + uint32 RxRMONPackets1024To2047Octets; /*!< Received 1024 to 2047 byte packets */ + uint32 RxRMONPacketsGreaterThan2048Octets; /*!< Received packets greater than 2048 byte */ + uint32 RxIEEEDrop; /*!< Count of frames not counted correctly */ + uint32 RxIEEEFrameOK; /*!< Frames received OK */ + uint32 RxIEEECRCError; /*!< Frames received with CRC error */ + uint32 RxIEEEAlignmentError; /*!< Frames received with alignment error */ + uint32 RxIEEEFIFOOverflow; /*!< Receive FIFO overflow count */ + uint32 RxIEEEPauseFrame; /*!< Flow control pause frames received */ + uint32 RxIEEEOctetsOK; /*!< Octet count for frames received without error */ +} LDD_ETH_TStats; + +/* +** =================================================================== +** FlexCAN device types and constants +** =================================================================== +*/ + +typedef uint8 LDD_CAN_TMBIndex; /*!< CAN message buffer index */ +typedef uint32 LDD_CAN_TAccMask; /*!< Type specifying the acceptance mask variable. */ +typedef uint32 LDD_CAN_TMessageID; /*!< Type specifying the ID mask variable. */ +typedef uint8 LDD_CAN_TErrorCounter; /*!< Type specifying the error counter variable. */ +typedef uint32 LDD_CAN_TErrorMask; /*!< Type specifying the error mask variable. */ +typedef uint16 LDD_CAN_TBufferMask; /*!< Type specifying the message buffer mask variable. */ +#define LDD_CAN_RX_PIN 0x01U /*!< Rx pin mask */ +#define LDD_CAN_TX_PIN 0x02U /*!< Tx pin mask */ + +#define LDD_CAN_ON_FULL_RXBUFFER 0x01U /*!< OnFullRxBuffer event mask */ +#define LDD_CAN_ON_FREE_TXBUFFER 0x02U /*!< OnFreeTxBuffer event mask */ +#define LDD_CAN_ON_BUSOFF 0x04U /*!< OnBusOff event mask */ +#define LDD_CAN_ON_TXWARNING 0x08U /*!< OnTransmitterWarning event mask */ +#define LDD_CAN_ON_RXWARNING 0x10U /*!< OnReceiverWarning event mask */ +#define LDD_CAN_ON_ERROR 0x20U /*!< OnError event mask */ +#define LDD_CAN_ON_WAKEUP 0x40U /*!< OnWakeUp event mask */ + +#define LDD_CAN_BIT0_ERROR 0x4000UL /*!< Bit0 error detect error mask */ +#define LDD_CAN_BIT1_ERROR 0x8000UL /*!< Bit1 error detect error mask */ +#define LDD_CAN_ACK_ERROR 0x2000UL /*!< Acknowledge error detect error mask */ +#define LDD_CAN_CRC_ERROR 0x1000UL /*!< Cyclic redundancy check error detect error mask */ +#define LDD_CAN_FORM_ERROR 0x0800UL /*!< Message form error detect error mask */ +#define LDD_CAN_STUFFING_ERROR 0x0400UL /*!< Bit stuff error detect error mask */ + +#define LDD_CAN_MESSAGE_ID_EXT 0x80000000UL /*!< Value specifying extended Mask, ID */ + +/*! Type specifying the CAN frame type. */ +typedef enum { + LDD_CAN_MB_RX_NOT_ACTIVE = 0x00U, + LDD_CAN_MB_RX_FULL = 0x02U, + LDD_CAN_MB_RX_EMPTY = 0x04U, + LDD_CAN_MB_RX_OVERRUN = 0x06U, + LDD_CAN_MB_RX_BUSY = 0x01U, + LDD_CAN_MB_RX_RANSWER = 0x0AU +} LDD_CAN_TRxBufferState; + +/*! Type specifying the CAN frame type. */ +typedef enum { + LDD_CAN_DATA_FRAME, /*!< Data frame type received or transmitted */ + LDD_CAN_REMOTE_FRAME, /*!< Remote frame type */ + LDD_CAN_RESPONSE_FRAME /*!< Response frame type - Tx buffer send data after receiving remote frame with the same ID */ +} LDD_CAN_TFrameType; + +/*! Type specifying the CAN communication statistics. */ +typedef struct { + uint32 TxFrames; /*!< Transmitted frame counter */ + uint32 TxWarnings; /*!< Transmission warning counter */ + uint32 RxFrames; /*!< Received frame counter */ + uint32 RxWarnings; /*!< Reception warning counter */ + uint32 BusOffs; /*!< Bus off counter */ + uint32 Wakeups; /*!< Wakeup counter */ + uint32 Bit0Errors; /*!< Bit0 error counter */ + uint32 Bit1Errors; /*!< Bit1 error counter */ + uint32 AckErrors; /*!< ACK error counter */ + uint32 CrcErrors; /*!< CRC error counter */ + uint32 FormErrors; /*!< Message form error counter */ + uint32 BitStuffErrors; /*!< Bit stuff error counter */ + uint32 Errors; /*!< Error counter */ +} LDD_CAN_TStats; + +/*! Type specifying the CAN frame features. */ +typedef struct { + LDD_CAN_TMessageID MessageID; /*!< Message ID */ + LDD_CAN_TFrameType FrameType; /*!< Type of the frame DATA/REMOTE */ + uint8 *Data; /*!< Message data buffer */ + uint8 Length; /*!< Message length */ + uint16 TimeStamp; /*!< Message time stamp */ + uint8 LocPriority; /*!< Local Priority Tx Buffers */ +} LDD_CAN_TFrame; + +/* +** =================================================================== +** USB device types and constants +** =================================================================== +*/ + +/* Events' masks */ +#define LDD_USB_ON_DEVICE_RESET 0x00000001u /*!< OnDeviceReset event mask */ +#define LDD_USB_ON_DEVICE_SPEED_DETECT 0x00000002u /*!< OnDeviceSpeedDetect event mask */ +#define LDD_USB_ON_DEVICE_SUSPEND 0x00000004u /*!< OnDeviceSuspend event mask */ +#define LDD_USB_ON_DEVICE_RESUME 0x00000008u /*!< OnDeviceResume event mask */ +#define LDD_USB_ON_DEVICE_SETUP_PACKET 0x00000010u /*!< OnDeviceSetupPacket event mask */ +#define LDD_USB_ON_DEVICE_SOF 0x00000020u /*!< OnDeviceSof event mask */ +#define LDD_USB_ON_DEVICE_1MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */ +#define LDD_USB_ON_DEVICE_1_MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */ +#define LDD_USB_ON_DEVICE_ERROR 0x00000080u /*!< OnDeviceError event mask */ +#define LDD_USB_ON_HOST_DEVICE_DEATTACH 0x00000100u /*!< OnHostDeviceAttach event mask */ +#define LDD_USB_ON_HOST_RESET_RECOVERY 0x00000200u /*!< OnHostResetRecovery event mask */ +#define LDD_USB_ON_HOST_RESUME_RECOVERY 0x00000400u /*!< OnHostResumeRecovery event mask */ +#define LDD_USB_ON_HOST_1MS_TIMER 0x00000800u /*!< 1 ms timer event mask */ +#define LDD_USB_ON_HOST_1_MS_TIMER 0x00000800u /*!< 1 ms timer event mask */ +#define LDD_USB_ON_HOST_ERROR 0x00001000u /*!< OnHostError event mask */ +#define LDD_USB_ON_OTG_DEVICE 0x00002000u /*!< OnOtgDevice event mask */ +#define LDD_USB_ON_OTG_HOST 0x00004000u /*!< OnOtgHost event mask */ +#define LDD_USB_ON_OTG_STATE_CHANGE 0x00008000u /*!< OnOtgStageChange event mask */ +#define LDD_USB_ON_SIGNAL_CHANGE 0x00010000u /*!< OnSignalChange event mask */ + +/* Data pins' masks */ +#define LDD_USB_DP_PIN 0x00000001u /*!< Data+ pin mask */ +#define LDD_USB_DM_PIN 0x00000002u /*!< Data- pin mask */ + +/* Pullup/pulldown pin masks */ +#define LDD_USB_DP_PU_PIN 0x00000004u /*!< Data+ pull-up pin mask */ +#define LDD_USB_DM_PU_PIN 0x00000008u /*!< Data- pull-up pin mask */ +#define LDD_USB_DP_PD_PIN 0x00000010u /*!< Data+ pull-down pin mask */ +#define LDD_USB_DM_PD_PIN 0x00000020u /*!< Data- pull-down pin mask */ + +/* VBUS pins' mask */ +#define LDD_USB_DEVICE_VBUS_DETECT_PIN 0x00000040u /*!< VBUS detect pin mask */ +#define LDD_USB_HOST_VBUS_ENABLE_PIN 0x00000080u /*!< VBUS enable pin mask */ +#define LDD_USB_HOST_VBUS_OVERCURRENT_PIN 0x00000100u /*!< VBUS overcurrent pin mask */ + +/* OTG pins' masks */ +#define LDD_USB_OTG_ID_PIN 0x00000200u /*!< ID pin mask */ +#define LDD_USB_OTG_VBUS_VALID_PIN 0x00000400u /*!< VBUS valid pin mask */ +#define LDD_USB_OTG_SESSION_VALID_PIN 0x00000800u /*!< SESSION valid pin mask */ +#define LDD_USB_OTG_B_SESSION_END_PIN 0x00004000u /*!< B SESSION end pin mask */ +#define LDD_USB_OTG_VBUS_ENABLE_PIN 0x00008000u /*!< VBUS drive pin mask */ +#define LDD_USB_OTG_VBUS_CHARGE_PIN 0x00010000u /*!< VBUS charge pin mask */ +#define LDD_USB_OTG_VBUS_DISCHARGE_PIN 0x00020000u /*!< VBUS discharge pin mask */ + +/* ULPI pins' masks */ +#define LDD_USB_ULPI_CLK_PIN 0x00080000u /*!< ULPI_CLK pin mask */ +#define LDD_USB_ULPI_DIR_PIN 0x00100000u /*!< ULPI_DIR pin mask */ +#define LDD_USB_ULPI_NXT_PIN 0x00200000u /*!< ULPI_NXT pin mask */ +#define LDD_USB_ULPI_STP_PIN 0x00400000u /*!< ULPI_STOP pin mask */ +#define LDD_USB_ULPI_DATA_0_PIN 0x00800000u /*!< ULPI_DATA_0 pin mask */ +#define LDD_USB_ULPI_DATA_1_PIN 0x01000000u /*!< ULPI_DATA_1 pin mask */ +#define LDD_USB_ULPI_DATA_2_PIN 0x02000000u /*!< ULPI_DATA_2 pin mask */ +#define LDD_USB_ULPI_DATA_3_PIN 0x04000000u /*!< ULPI_DATA_3 pin mask */ +#define LDD_USB_ULPI_DATA_4_PIN 0x08000000u /*!< ULPI_DATA_4 pin mask */ +#define LDD_USB_ULPI_DATA_5_PIN 0x10000000u /*!< ULPI_DATA_5 pin mask */ +#define LDD_USB_ULPI_DATA_6_PIN 0x20000000u /*!< ULPI_DATA_6 pin mask */ +#define LDD_USB_ULPI_DATA_7_PIN 0x40000000u /*!< ULPI_DATA_7 pin mask */ + +/* Alternate clock pin*/ +#define LDD_USB_CLKIN_PIN 0x80000000u /*!< Alternate clock pin mask */ +#define LDD_USB_ALT_CLK_PIN 0x80000000u /*!< Alternate clock pin mask */ + +/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Cmd/CmdStatusPtr param. values */ +#define LDD_USB_CMD_GET_EP_STATUS 0x00u /*!< Get endpoint status command ID */ +#define LDD_USB_CMD_SET_EP_HALT_FATURE 0x01u /*!< Set endpoint HALT feature command ID */ +#define LDD_USB_CMD_CLR_EP_HALT_FATURE 0x02u /*!< Clear endpoint HALT feature command ID */ + +#define LDD_USB_CMD_EP_STATUS_HALT_MASK 0x01u /*!< Endpoint halt status mask */ + + +/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Recipient param. values */ +/* (see USB 2.0, chapter 9.3.4 wIndex description)*/ +#define LDD_USB_ID_EP0_OUT 0x00u /*!< EP0 OUT component ID */ +#define LDD_USB_ID_EP0_IN 0x80u /*!< EP0 IN component ID */ +#define LDD_USB_ID_EP1_OUT 0x01u /*!< EP1 OUT component ID */ +#define LDD_USB_ID_EP1_IN 0x81u /*!< EP1 IN component ID */ +#define LDD_USB_ID_EP2_OUT 0x02u /*!< EP2 OUT component ID */ +#define LDD_USB_ID_EP2_IN 0x82u /*!< EP2 IN component ID */ +#define LDD_USB_ID_EP3_OUT 0x03u /*!< EP3 OUT component ID */ +#define LDD_USB_ID_EP3_IN 0x83u /*!< EP3 IN component ID */ +#define LDD_USB_ID_EP4_OUT 0x04u /*!< EP4 OUT component ID */ +#define LDD_USB_ID_EP4_IN 0x84u /*!< EP4 IN component ID */ +#define LDD_USB_ID_EP5_OUT 0x05u /*!< EP5 OUT component ID */ +#define LDD_USB_ID_EP5_IN 0x85u /*!< EP5 IN component ID */ +#define LDD_USB_ID_EP6_OUT 0x06u /*!< EP6 OUT component ID */ +#define LDD_USB_ID_EP6_IN 0x86u /*!< EP6 IN component ID */ +#define LDD_USB_ID_EP7_OUT 0x07u /*!< EP7 OUT component ID */ +#define LDD_USB_ID_EP7_IN 0x87u /*!< EP7 IN component ID */ +#define LDD_USB_ID_EP8_OUT 0x08u /*!< EP8 OUT component ID */ +#define LDD_USB_ID_EP8_IN 0x88u /*!< EP8 IN component ID */ +#define LDD_USB_ID_EP9_OUT 0x09u /*!< EP9 OUT component ID */ +#define LDD_USB_ID_EP9_IN 0x89u /*!< EP9 IN component ID */ +#define LDD_USB_ID_EP10_OUT 0x0Au /*!< EP10 OUT component ID */ +#define LDD_USB_ID_EP10_IN 0x8Au /*!< EP10 IN component ID */ +#define LDD_USB_ID_EP11_OUT 0x0Bu /*!< EP11 OUT component ID */ +#define LDD_USB_ID_EP11_IN 0x8Bu /*!< EP11 IN component ID */ +#define LDD_USB_ID_EP12_OUT 0x0Cu /*!< EP12 OUT component ID */ +#define LDD_USB_ID_EP12_IN 0x8Cu /*!< EP12 IN component ID */ +#define LDD_USB_ID_EP13_OUT 0x0Du /*!< EP13 OUT component ID */ +#define LDD_USB_ID_EP13_IN 0x8Du /*!< EP13 IN component ID */ +#define LDD_USB_ID_EP14_OUT 0x0Eu /*!< EP14 OUT component ID */ +#define LDD_USB_ID_EP14_IN 0x8Eu /*!< EP14 IN component ID */ +#define LDD_USB_ID_EP15_OUT 0x0Fu /*!< EP15 OUT component ID */ +#define LDD_USB_ID_EP15_IN 0x8Fu /*!< EP15 IN component ID */ +#define LDD_USB_ID_EP_MASK 0x8Fu /*!< EP15 IN component ID */ + +/* Token PID */ +#define LDD_USB_PID_OUT 0x01u /*!< OUT */ +#define LDD_USB_PID_IN 0x09u /*!< IN */ +#define LDD_USB_PID_SOF 0x05u /*!< SOF */ +#define LDD_USB_PID_SETUP 0x0Du /*!< SETUP */ +/* Data PID */ +#define LDD_USB_PID_DATA0 0x03u /*!< DATA0 */ +#define LDD_USB_PID_DATA1 0x0Bu /*!< DATA1 */ +#define LDD_USB_PID_DATA2 0x07u /*!< DATA2 */ +#define LDD_USB_PID_MDATA 0x0Fu /*!< MDATA */ +/* Handshake PID */ +#define LDD_USB_PID_ACK 0x02u /*!< ACK */ +#define LDD_USB_PID_NACK 0x0Au /*!< NACK */ +#define LDD_USB_PID_STALL 0x0Eu /*!< STALL */ +#define LDD_USB_PID_NYET 0x06u /*!< NYET */ +/* Special PID */ +#define LDD_USB_PID_PRE 0x0Cu /*!< PRE */ +#define LDD_USB_PID_ERR 0x0Cu /*!< ERR */ +#define LDD_USB_PID_SPLIT 0x08u /*!< SPLIT */ +#define LDD_USB_PID_PING 0x04u /*!< PING */ + +/* Data direction */ +#define LDD_USB_DIR_OUT 0x00u /*!< Recipient is Device */ +#define LDD_USB_DIR_IN 0x80u /*!< Recipient is Host */ +#define LDD_USB_DIR_MASK 0x80u /*!< Bit mask for data transfer direction */ + +/* Flags used in the TD.Head.Flags variable */ + +/* The following flag can be used to force zero-length termination(ZLT) of the transfer. + Note: ZLT can be set for all transfer during the initialization of the endpoint. +*/ +#define LDD_USB_DEVICE_TRANSFER_FLAG_ZLT 0x01u + +/* If the TRANSFER_FLAG_EXT_PARAM is defined all variables of the TD are used + and TD must NOT be freed until transfer is done or is cancelled + (TransferState != LDD_USB_TRANSFER_PENDING) + If not defined only the Head member of TD is used and TD can be freed after + Send/Recv() method returns. +*/ +#define LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM 0x02u + + +#define ERR_COMPONET_SPECIFIC 0x100u + +/* Device mode USB specific error codes */ +#define ERR_USB_DEVICE_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Device mode is disabled (by the user or by the clock configuration) */ +#define ERR_USB_DEVICE_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Device mode is disabled by the OTG driver */ +#define ERR_USB_DEVICE_VBUS_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< No VBUS is detected */ +#define ERR_USB_DEVICE_VBUS_ON (ERR_COMPONET_SPECIFIC + 0x03u) /*!< VBUS is detected */ +#define ERR_USB_DEVICE_ENABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is enabled */ +#define ERR_USB_DEVICE_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Device is suspended */ +#define ERR_USB_DEVICE_SUSPENDED_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Device is suspended and ready to generate resume signaling */ +#define ERR_USB_DEVICE_RESUME_PENDING (ERR_COMPONET_SPECIFIC + 0x07u) /*!< Device generates resume signaling */ + +/* Host mode USB specific error codes */ +#define ERR_USB_HOST_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Host mode is disabled (by the user or by the clock configuration) */ +#define ERR_USB_HOST_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Host mode is disabled by the OTG driver */ +#define ERR_USB_HOST_PORT_POWERED_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< Port is power off */ +#define ERR_USB_HOST_PORT_DISCONNECTED (ERR_COMPONET_SPECIFIC + 0x03u) /*!< Port is power on */ +#define ERR_USB_HOST_PORT_DISABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is connected to the port */ +#define ERR_USB_HOST_PORT_RESETING (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Port generates reset signaling */ +#define ERR_USB_HOST_PORT_RESET_RECOVERING (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Port waits 10ms for reset recovery */ +#define ERR_USB_HOST_PORT_ENABLED (ERR_COMPONET_SPECIFIC + 0x07u) /*!< PortDevice is connected, reset and ready to use */ +#define ERR_USB_HOST_PORT_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x08u) /*!< Port is suspended */ +#define ERR_USB_HOST_PORT_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x09u) /*!< Port can generate resume signaling */ +#define ERR_USB_HOST_PORT_RESUMING (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< Port generates resume signaling */ +#define ERR_USB_HOST_PORT_RESUME_RECOVERING (ERR_COMPONET_SPECIFIC + 0x0Bu) /*!< Port generates resume signaling */ + +/* OTG mode USB specific error codes */ +#define ERR_USB_OTG_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< OTG device is DISABLED state */ +#define ERR_USB_OTG_ENABLED_PENDING (ERR_COMPONET_SPECIFIC + 0x01u) /*!< OTG device is in ENABLED_PENDING state */ +#define ERR_USB_OTG_A_IDLE (ERR_COMPONET_SPECIFIC + 0x02u) /*!< OTG device is in A_IDLE state */ +#define ERR_USB_OTG_A_WAIT_VRISE (ERR_COMPONET_SPECIFIC + 0x03u) /*!< OTG device is in WAIT_VRISE state */ +#define ERR_USB_OTG_A_WAIT_VFALL (ERR_COMPONET_SPECIFIC + 0x05u) /*!< OTG device is in A_WAIT_VFALL state */ +#define ERR_USB_OTG_A_WAIT_BCON (ERR_COMPONET_SPECIFIC + 0x07u) /*!< OTG device is in A_WAIT_BCON state */ +#define ERR_USB_OTG_A_VBUS_ERROR (ERR_COMPONET_SPECIFIC + 0x09u) /*!< OTG device is in A_VBUS_ERROR state */ +#define ERR_USB_OTG_A_SUSPEND (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< OTG device is in A_SUSPEND state */ + +#define ERR_USB_OTG_B_IDLE (ERR_COMPONET_SPECIFIC + 0x0Cu) /*!< OTG device is in B_IDLE state */ +#define ERR_USB_OTG_B_SRP_INIT (ERR_COMPONET_SPECIFIC + 0x0Eu) /*!< OTG device is in B_SRP_INIT state */ +#define ERR_USB_OTG_B_WAIT_ACON (ERR_COMPONET_SPECIFIC + 0x0Fu) /*!< OTG device is in B_WAIT_ACON state */ + +#define ERR_USB_OTG_A_HOST (ERR_COMPONET_SPECIFIC + 0x10u) /*!< OTG device is in A_HOST state */ +#define ERR_USB_OTG_A_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x11u) /*!< OTG device is in A_PERIPHERAL state */ +#define ERR_USB_OTG_B_HOST (ERR_COMPONET_SPECIFIC + 0x12u) /*!< OTG device is in B_HOST state */ +#define ERR_USB_OTG_B_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x13u) /*!< OTG device is in B_PERIPHERAL state */ + +/*! Device speed symbolic names */ +typedef enum { + LDD_USB_LOW_SPEED = 0x00u, /*!< Low-speed - 6 Mb/s mode */ + LDD_USB_FULL_SPEED = 0x01u, /*!< Full-speed - 12 Mb/s mode */ + LDD_USB_HIGH_SPEED = 0x02u, /*!< High-speed - 480 Mb/s mode */ + LDD_USB_SPEED_UNKNOWN = 0xFFu /*!< Unkown speed mode */ +} LDD_USB_TBusSpeed; + +/*! Transfer type symbolic names */ +typedef enum { + LDD_USB_CONTROL = 0x00u, /*!< Conrol transfer type */ + LDD_USB_ISOCHRONOUS = 0x01u, /*!< Isochronous transfer type */ + LDD_USB_BULK = 0x02u, /*!< Bulk transfer type */ + LDD_USB_INTERRUPT = 0x03u /*!< Interrupt transfer type */ +} LDD_USB_TTransferType; + +/*! Transfer state symbolic names */ +typedef enum { + LDD_USB_TRANSFER_NONE = 0x00u, /*!< Default valeu for new TD */ + LDD_USB_TRANSFER_DONE = 0x01u, /*!< Transfer done */ + LDD_USB_TRANSFER_ERROR_CANCELLED = 0x02u, /*!< Transfer cancelled by the user */ + LDD_USB_TRANSFER_ERROR_STALLED = 0x03u, /*!< Transfer stalled */ + LDD_USB_TRANSFER_ERROR_BUS_TIMEOUT = 0x04u, /*!< Bus timeute detected */ + LDD_USB_TRANSFER_ERROR_DATA = 0x05u, /*!< Data error deteceted */ + LDD_USB_TRANSFER_ERROR_PID = 0x06u, /*!< PID error deteceted */ + LDD_USB_TRANSFER_ERROR_EOF = 0x07u, /*!< EOF error deteceted */ + LDD_USB_TRANSFER_ERROR_CRC16 = 0x08u, /*!< CRC16 error deteceted */ + LDD_USB_TRANSFER_ERROR_DFN8 = 0x09u, /*!< DFN8 error deteceted */ + LDD_USB_TRANSFER_ERROR_DMA = 0x0Au, /*!< DMA error deteceted */ + LDD_USB_TRANSFER_ERROR_BTS = 0x0Bu, /*!< BTS error deteceted */ + LDD_USB_TRANSFER_ERROR = 0x0Fu, /*!< Transfer error deteceted */ + LDD_USB_TRANSFER_QUEUED = 0x10u, /*!< Transfer queued */ + LDD_USB_TRANSFER_PENDING = 0x30u /*!< Transfer in proggress */ +} LDD_USB_TTransferState; + +/*! Setup data packet structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TSDP_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request code */ + uint16 wValue; /*!< Word-sized field that varies according to request */ + uint16 wIndex; /*!< Word-sized field that varies according to request, typically used to pass an index or offset */ + uint16 wLength; /*!< Number of bytes to transfer if there is a data stage */ +} LDD_USB_TSDP; + +/*! Endpoint descriptor structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TEpDescriptor_Struct { + uint8 bLength; /*!< Size of this descriptor in bytes */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint8 bEndpointAddress; /*!< Endpoint address */ + uint8 bmAttributes; /*!< Endpoint attributes */ + uint16 wMaxPacketSize; /*!< Maximum packet size the endpoint is capable of sending or receiving */ + uint8 bInterval; /*!< Interval for polling endpoint for data transfers */ +} LDD_USB_TEpDescriptor; + +/*! Standard device descriptor structure, uint16 items must be in little-endian format */ +typedef struct LDD_USB_TDevDescriptor_Struct { + uint8 bLength; /*!< Size of this descriptor in bytes */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint16 bcdUSB; /*!< USB specification release number in binary-coded Decimal */ + uint8 bDeviceClass; /*!< Class code (assigned by the USB-IF) */ + uint8 bDeviceSubClass; /*!< Subclass code (assigned by the USB-IF) */ + uint8 bDeviceProtocol; /*!< Protocol code (assigned by the USB-IF) */ + uint8 bMaxPacketSize0; /*!< Maximum packet size for endpoint zero */ + uint16 idVendor; /*!< Vendor ID (assigned by the USB-IF) */ + uint16 idProduct; /*!< Product ID (assigned by the manufacturer) */ + uint16 bcdDevice; /*!< Device release number in binary-coded decimal */ + uint8 iManufacturer; /*!< Index of string descriptor describing manufacturer */ + uint8 iProduct; /*!< Index of string descriptor describing product */ + uint8 iSerialNumber; /*!< Index of string descriptor describing the devices serial number */ + uint8 bNumConfigurations; /*!< Number of possible configurations */ +} LDD_USB_TDevDescriptor; + + +/*! Device transfer descriptor structure forward declaration */ +struct LDD_USB_Device_TTD_Struct; + +/*! Device transfer done callback prototype */ +typedef void (LDD_USB_Device_TTransferDoneCalback)(LDD_TDeviceData *DevDataPtr, struct LDD_USB_Device_TTD_Struct *TrParamPtr); + +/*! Device transfer descriptor structure - head part */ +typedef struct LDD_USB_Device_TTD_Head_Struct { + uint8 EpNum; /*!< Endpoint number */ + LDD_TData *BufferPtr; /*!< Buffer address */ + uint16 BufferSize; /*!< Buffer size */ + uint8 Flags; /*!< Transfer flags - see constants definition */ +} LDD_USB_Device_TTD_Head; + +/*! Device transfer descriptor structure */ +typedef struct LDD_USB_Device_TTD_Struct { + /* Requierd variables */ + LDD_USB_Device_TTD_Head Head; /*!< Td head data, not changed by the driver */ + /* Optional items - the following items are used */ + /* only if Head.Flags & LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM != 0 */ + LDD_USB_TTransferState TransferState; /*!< Transfer state. Set by the driver */ + uint16 TransmittedDataSize; /*!< Transmitted data size. Set by the driver */ + LDD_USB_Device_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */ + uint8 *ParamPtr; /*!< User parameter. Not changed by the driver */ +} LDD_USB_Device_TTD; + +/*! USB device states symbolic names */ +typedef enum { + LDD_USB_DEVICE_DISABLED = ERR_USB_DEVICE_DISABLED, /*!< Device mode is disabled (by the user or by the clock configuration) */ + LDD_USB_DEVICE_DISABLED_BY_OTG = ERR_USB_DEVICE_DISABLED_BY_OTG, /*!< Device mode is disabled by the OTG driver */ + LDD_USB_DEVICE_VBUS_OFF = ERR_USB_DEVICE_VBUS_OFF, /*!< No VBUS is detected */ + LDD_USB_DEVICE_VBUS_ON = ERR_USB_DEVICE_VBUS_ON, /*!< VBUS is detected */ + LDD_USB_DEVICE_ENABLED = ERR_USB_DEVICE_ENABLED, /*!< Device is enabled - reset by the host */ + LDD_USB_DEVICE_SUSPENDED = ERR_USB_DEVICE_SUSPENDED, /*!< Device is suspended - Bus is idle more then 3 ms */ + LDD_USB_DEVICE_SUSPENDED_RESUME_READY = ERR_USB_DEVICE_SUSPENDED_RESUME_READY, /*!< Device can generate resume signaling - Bus is idle more then 5 ms. */ + LDD_USB_DEVICE_RESUME_PENDING = ERR_USB_DEVICE_RESUME_PENDING /*!< Device generates resume signaling */ +} LDD_USB_Device_TState; + +/*! USB host mode states symbolic names */ +typedef enum { + LDD_USB_HOST_DISABLED = ERR_USB_HOST_DISABLED, /*!< Host mode is disabled (by the user or by the clock configuration) */ + LDD_USB_HOST_DISABLED_BY_OTG = ERR_USB_HOST_DISABLED_BY_OTG, /*!< Host mode is disabled by the OTG driver */ + LDD_USB_HOST_PORT_POWERED_OFF = ERR_USB_HOST_PORT_POWERED_OFF, /*!< Port is powered-off */ + LDD_USB_HOST_PORT_DISCONNECTED = ERR_USB_HOST_PORT_DISCONNECTED, /*!< No device is connected */ + LDD_USB_HOST_PORT_DISABLED = ERR_USB_HOST_PORT_DISABLED, /*!< Device is connected to the port */ + LDD_USB_HOST_PORT_RESETING = ERR_USB_HOST_PORT_RESETING, /*!< Port generates reset signaling */ + LDD_USB_HOST_PORT_RESET_RECOVERING = ERR_USB_HOST_PORT_RESET_RECOVERING, /*!< Port waits 10 ms for reset recovery */ + LDD_USB_HOST_PORT_ENABLED = ERR_USB_HOST_PORT_ENABLED, /*!< Device is connected, reset and ready to use */ + LDD_USB_HOST_PORT_SUSPENDED = ERR_USB_HOST_PORT_SUSPENDED, /*!< Port is suspended */ + LDD_USB_HOST_PORT_RESUME_READY = ERR_USB_HOST_PORT_RESUME_READY, /*!< Port is ready to generate resume signaling */ + LDD_USB_HOST_PORT_RESUMING = ERR_USB_HOST_PORT_RESUMING, /*!< Port generates resume signaling */ + LDD_USB_HOST_PORT_RESUME_RECOVERING = ERR_USB_HOST_PORT_RESUME_RECOVERING /*!< Port waits 10 ms for resume recovery */ +} LDD_USB_Host_TState; + +/*! USB otg mode states symbolic names */ +typedef enum { + LDD_USB_OTG_DISABLED = ERR_USB_OTG_DISABLED, /*!< OTG device is in DISABLED state */ + LDD_USB_OTG_ENABLED = ERR_USB_OTG_ENABLED_PENDING, /*!< OTG device is in ENABLED_PENDING state */ + LDD_USB_OTG_A_IDLE = ERR_USB_OTG_A_IDLE, /*!< OTG device is in A_IDLE state */ + LDD_USB_OTG_A_WAIT_VRISE = ERR_USB_OTG_A_WAIT_VRISE, /*!< OTG device is in A_WAIT_VRISE state */ + LDD_USB_OTG_A_WAIT_VFALL = ERR_USB_OTG_A_WAIT_VFALL, /*!< OTG device is in A_WAIT_VFALL state */ + LDD_USB_OTG_A_WAIT_BCON = ERR_USB_OTG_A_WAIT_BCON, /*!< OTG device is in A_WAIT_BCON state */ + LDD_USB_OTG_A_VBUS_ERROR = ERR_USB_OTG_A_VBUS_ERROR, /*!< OTG device is in A_VBUS_ERROR state */ + LDD_USB_OTG_A_SUSPEND = ERR_USB_OTG_A_SUSPEND, /*!< OTG device is in A_SUSPEND state */ + LDD_USB_OTG_B_IDLE = ERR_USB_OTG_B_IDLE, /*!< OTG device is in B_IDLE state */ + LDD_USB_OTG_B_SRP_INIT = ERR_USB_OTG_B_SRP_INIT, /*!< OTG device is in B_SRP_INIT state */ + LDD_USB_OTG_B_WAIT_ACON = ERR_USB_OTG_B_WAIT_ACON, /*!< OTG device is in B_WAIT_ACON state */ + LDD_USB_OTG_A_HOST = ERR_USB_OTG_A_HOST, /*!< OTG device is in A_HOST state */ + LDD_USB_OTG_A_PERIPHERAL = ERR_USB_OTG_A_PERIPHERAL, /*!< OTG device is in A_PERIPHERAL state */ + LDD_USB_OTG_B_HOST = ERR_USB_OTG_B_HOST, /*!< OTG device is in B_HOST state */ + LDD_USB_OTG_B_PERIPHERAL = ERR_USB_OTG_B_PERIPHERAL /*!< OTG device is in B_PERIPHERAL state */ +} LDD_USB_Otg_TState; + +/*! USB Otg commands symbolic names */ +typedef enum { + LDD_USB_OTG_CMD_SET_A_BUS_REQUEST, /*!< A-device application wants to use the bus */ + LDD_USB_OTG_CMD_CLR_A_BUS_REQUEST, /*!< A-device application doesn't want to use the bus */ + LDD_USB_OTG_CMD_SET_B_BUS_REQUEST, /*!< B-device application wants to use the bus */ + LDD_USB_OTG_CMD_CLR_B_BUS_REQUEST, /*!< B-device application doesn't want to use the bus */ + LDD_USB_OTG_CMD_SET_A_BUS_DROP, /*!< A-device application needs to power down the bus */ + LDD_USB_OTG_CMD_CLR_A_BUS_DROP, /*!< A-device application doesn't need to power down the bus */ + LDD_USB_OTG_CMD_SET_A_SUSPEND_REQUEST, /*!< A-device application wants to suspend the bus */ + LDD_USB_OTG_CMD_CLR_A_SUSPEND_REQUEST, /*!< A-device application doesn't want to suspend the bus */ + LDD_USB_OTG_CMD_SET_A_SET_B_HNP_EN_REQUEST, /*!< A-device sets HNP enabled feature on B-device */ + LDD_USB_OTG_CMD_CLR_A_SET_B_HNP_EN_REQUEST, /*!< A-device clears HNP enabled feature on B-device */ + LDD_USB_OTG_CMD_SET_B_HNP_EN_REQUEST, /*!< Enable B-device HNP */ + LDD_USB_OTG_CMD_CLR_B_HNP_EN_REQUEST /*!< Disable B-device HNP */ +} LDD_USB_Otg_TCmd; + +/*! USB host port control commands symbolic names */ +typedef enum { + LDD_USB_HOST_PORT_CMD_POWER_ON, /*!< Power-on the bus */ + LDD_USB_HOST_PORT_CMD_POWER_OFF, /*!< Power-off the bus */ + LDD_USB_HOST_PORT_CMD_RESET, /*!< Perform the bus reset signaling and call event after the reset recovery interval elapse */ + LDD_USB_HOST_PORT_CMD_RESUME, /*!< Perform the bus resume signaling and call event after the resume recovery interval elapse */ + LDD_USB_HOST_PORT_CMD_SUSPEND, /*!< Suspend the bus and transceiver */ + LDD_USB_HOST_PORT_CMD_DISABLE /*!< Disable the port */ +} LDD_USB_Host_TPortControlCmd; + +/*! USB host handle prototypes */ +typedef void LDD_USB_Host_TPipeHandle; /*!< Pipe handle prototype */ +typedef void LDD_USB_Host_TTransferHandle; /*!< Transfer handle prototype */ + +/*! USB host pipe descriptor structure */ +typedef struct LDD_USB_Host_TPipeDescr_Struct { + uint8 DevAddress; /*!< Device address */ + LDD_USB_TBusSpeed DevSpeed; /*!< Device speed */ + uint8 EpNumber; /*!< EP number */ + uint8 EpDir; /*!< EP direction */ + LDD_USB_TTransferType TransferType; /*!< EP Transfer type */ + uint16 MaxPacketSize; /*!< EP max. packet size */ + uint8 TrPerUFrame; /*!< Transaction pre microframe */ + uint32 Interval; /*!< Interval for polling endpoint for data transfers */ + uint32 NAKCount; /*!< NAK count */ + uint8 Flags; /*!< 1 = ZLT */ +} LDD_USB_Host_TPipeDescr; + +/*! USB host transfer done callback prototype */ +typedef void (LDD_USB_Host_TTransferDoneCalback)( + LDD_TDeviceData *DevDataPtr, /*!< User value passed as parameter of the Init() method */ + LDD_TData *BufferPtr, /*!< Buffer address */ + uint16 BufferSize, /*!< Transferred data size */ + uint8 *ParamPtr, /*!< User value passed in Send()/Recv() method */ + LDD_USB_TTransferState Status /*!< Transfer status */ +); + +/*! USB host transfer descriptor structure */ +typedef struct LDD_USB_Host_TTD_Struct { + LDD_TData *BufferPtr; /*!< Buffer address */ + uint16 BufferSize; /*!< Buffer size */ + uint8 Flags; /*!< Transfer flags */ + LDD_USB_Host_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */ + uint8 *ParamPtr; /*!< User parameter. Not changed by the driver */ + LDD_USB_TSDP *SDPPrt; /*!< Setup data buffer pointer */ +} LDD_USB_Host_TTD; + +/*! Following USB constants and types are for test purpose only */ + +/* Request types */ +#define LDD_USB_REQ_TYPE_STANDARD 0x00u /*!< Standard request */ +#define LDD_USB_REQ_TYPE_CLASS 0x20u /*!< Class request */ +#define LDD_USB_REQ_TYPE_VENDOR 0x40u /*!< Vendor request */ +#define LDD_USB_REQ_TYPE_MASK 0x60u /*!< Bit mask for request type (bmRequestType) */ + +/* Request recepient */ +#define LDD_USB_REQ_RECP_DEVICE 0x00u /*!< Recipient = Device */ +#define LDD_USB_REQ_RECP_INTERFACE 0x01u /*!< Recipient = Interface */ +#define LDD_USB_REQ_RECP_ENDPOINT 0x02u /*!< Recipient = Endpoint */ +#define LDD_USB_REQ_RECP_OTHER 0x03u /*!< Recipient = Other */ +#define LDD_USB_REQ_RECP_MASK 0x03u /*!< Bit mask for recipient */ + +/* Standard request codes (bRequest) */ +#define LDD_USB_REQ_GET_STATUS 0x00u /*!< GET_STATUS request code */ +#define LDD_USB_REQ_CLEAR_FEATURE 0x01u /*!< CLEAR_FEATURE request code */ +#define LDD_USB_REQ_SET_FEATURE 0x03u /*!< SET_FEATURE request code */ +#define LDD_USB_REQ_GET_STATE 0x04u /*!< GET_STATE request code (for Hub Class only)*/ +#define LDD_USB_REQ_SET_ADDRESS 0x05u /*!< SET_ADDRESS request code */ +#define LDD_USB_REQ_GET_DESCRIPTOR 0x06u /*!< GET_DESCRIPTOR request code */ +#define LDD_USB_REQ_SET_DESCRIPTOR 0x07u /*!< SET_DESCRIPTOR request code, this request is not supported */ +#define LDD_USB_REQ_GET_CONFIGURATION 0x08u /*!< GET_CONFIGURATION request code */ +#define LDD_USB_REQ_SET_CONFIGURATION 0x09u /*!< SET_CONFIGURATION request code */ +#define LDD_USB_REQ_GET_INTERFACE 0x0Au /*!< GET_INTERFACE request code */ +#define LDD_USB_REQ_SET_INTERFACE 0x0Bu /*!< SET_INTERFACE request code */ +#define LDD_USB_REQ_SYNCH_FRAME 0x0Cu /*!< SYNCH_FRAME request code */ + +/* Standard request words for device (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_DEV_STATUS 0x0080u /*!< GET_DEVICE_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_DEV_FEATURE 0x0100u /*!< CLEAR_DEVICE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_DEV_FEATURE 0x0300u /*!< SET_DEVICE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_ADDRESS 0x0500u /*!< SET_DEVICE_ADDRESS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_DESCRIPTOR 0x0680u /*!< GET_DESCRIPTOR bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_DESCRIPTOR 0x0700u /*!< SET_DESCRIPTOR bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_CONFIGURATION 0x0880u /*!< GET_DEVICE_CONFIGURATION bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_CONFIGURATION 0x0900u /*!< SET_DEVICE_CONFIGURATION bmRequestType and bRequest word */ + +/* Standard request words for interface (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_INT_STATUS 0x0081u /*!< GET_INTERFACE_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_INT_FEATURE 0x0101u /*!< CLEAR_INTERFACE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_INT_FEATURE 0x0301u /*!< SET_INTERFACE_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_GET_INTERFACE 0x0A81u /*!< GET_DEVICE_INTERFACE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_INTERFACE 0x0B01u /*!< SET_DEVICE_INTERFACE bmRequestType and bRequest word */ + +/* Standard request words for endpoint (bmRequestType | bRequest) */ +#define LDD_USB_STD_REQ_GET_EP_STATUS 0x0082u /*!< GET_ENDPOINT_STATUS bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_CLR_EP_FEATURE 0x0102u /*!< CLEAR_ENDPOINT_FEATURE bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SET_EP_FEATURE 0x0302u /*!< ENDPOINT_ bmRequestType and bRequest word */ +#define LDD_USB_STD_REQ_SYNCH_FRAME 0x0C12u /*!< SYNCH_DEVICE_FRAME bmRequestType and bRequest code */ + +#define LDD_USB_STATUS_DEVICE_SELF_POWERED_MASK 0x01u +#define LDD_USB_STATUS_DEVICE_REMOTE_WAKEUP_MASK 0x02u + +/* Standard descriptors */ +#define LDD_USB_DT_DEVICE 0x01u /*!< Device descriptor */ +#define LDD_USB_DT_CONFIGURATION 0x02u /*!< Configuration descriptor */ +#define LDD_USB_DT_STRING 0x03u /*!< String descriptor */ +#define LDD_USB_DT_INTERFACE 0x04u /*!< Interface descriptor */ +#define LDD_USB_DT_ENDPOINT 0x05u /*!< Endpoint descriptor */ +#define LDD_USB_DT_DEVICE_QUALIFIER 0x06u /*!< Device qualifier descriptor */ +#define LDD_USB_DT_OTHER_SPEED_CONFIGURATION 0x07u /*!< Other speed configuration descriptor */ +#define LDD_USB_DT_INTERFACE_POWER 0x08u /*!< Interface-level power management descriptor */ +#define LDD_USB_DT_OTG 0x09u /*!< OTG descriptor */ +#define LDD_USB_DT_DEBUG 0x0Au /*!< Debug descriptor */ +#define LDD_USB_DT_INTERFACE_ASSOCIATION 0x0Bu /*!< Interface association descriptor */ + +/* Standard feature selectors */ +#define LDD_USB_FEATURE_EP_HALT 0x00u /*!< Endpoint HALT feature selector */ +#define LDD_USB_FEATURE_DEV_REMOTE_WAKEUP 0x01u /*!< Remote Wake-up feature selector */ +#define LDD_USB_FEATURE_DEV_TEST_MODE 0x02u /*!< Test mode feature selector */ + +/*! Get decriptor request structure */ +typedef struct LDD_USB_TGetDecriptorRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 bDescriptorIndex; /*!< Descriptor index */ + uint8 bDescriptorType; /*!< Descriptor type */ + uint16 wLanguageID; /*!< Language ID */ + uint16 wLength; /*!< Requested data size */ +} LDD_USB_TGetDecriptorRequest; + +/*! Get endpoint status request structure */ +typedef struct LDD_USB_TEndpointStatusRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wValue; /*!< Not used, should be set to zero */ + uint8 bEndpoint; /*!< Endpoint address */ + uint8 bIndexHigh; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Reqested data size, should be set to 2 */ +} LDD_USB_TEndpointStatusRequest; + +/*! Clear/Set endpoint feature request structure */ +typedef struct LDD_USB_TEndpointFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint8 bEndpoint; /*!< Endpoint address */ + uint8 bIndexHigh; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TEndpointFeatureRequest; + +/*! Clear/Set interface request structure */ +typedef struct LDD_USB_TInterfaceFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TInterfaceFeatureRequest; + +/*! Clear/Set device request structure */ +typedef struct LDD_USB_TDeviceFeatureRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wFeatureSelector; /*!< Feature selector */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TDeviceFeatureRequest; + +/*! Get interface request structure */ +typedef struct LDD_USB_TGetInterfaceRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wWalue; /*!< Not used, should be zero */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Reqested data size, should be set to 1 */ +} LDD_USB_TGetInterfaceRequest; + +/*! Set interface request structure */ +typedef struct LDD_USB_TSetInterfaceRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint16 wAltSet; /*!< Alternate setting */ + uint16 wInterface; /*!< Interface index */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetInterfaceRequest; + +/*! Set address request structure */ +typedef struct LDD_USB_TSetAddressRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 DeviceAddress; /*!< Device address */ + uint8 bValueHigh; /*!< Not used, should be set to zero */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetAddressRequest; + +/*! Set address request structure */ +typedef struct LDD_USB_TSetConfigRequest_Struct { + uint8 bmRequestType; /*!< Characteristics of request */ + uint8 bRequest; /*!< Request ID */ + uint8 bValueHigh; /*!< Not used, should be set to zero */ + uint8 ConfigNumber; /*!< Configuration number */ + uint16 wIndex; /*!< Not used, should be set to zero */ + uint16 wLength; /*!< Not used, should be set to zero */ +} LDD_USB_TSetConfigRequest; + +/* +** =================================================================== +** DAC device types and constants +** =================================================================== +*/ +#define LDD_DAC_OUTPUT_PIN_0 0x01u /*!< DAC output pin 0 mask */ + +#define LDD_DAC_ON_BUFFER_END 0x01U /*!< OnBufferEnd event mask */ +#define LDD_DAC_ON_BUFFER_START 0x02U /*!< OnBufferStart event mask */ +#define LDD_DAC_ON_BUFFER_WATERMARK 0x04U /*!< OnBufferWatermark event mask */ +#define LDD_DAC_ON_COMPLETE LDD_DMA_ON_COMPLETE /*!< OnComplete event mask */ +#define LDD_DAC_ON_ERROR LDD_DMA_ON_ERROR /*!< OnError event mask */ + +/*! Type specifying the DAC buffer work mode */ +typedef enum { + LDD_DAC_BUFFER_NORMAL_MODE = 0x00U, /*!< Normal (cyclic) mode */ + LDD_DAC_BUFFER_SWING_MODE = 0x01U, /*!< Swing mode */ + LDD_DAC_BUFFER_SCAN_MODE = 0x02U /*!< One-time scan mode */ +} LDD_DAC_TBufferMode; + +/*! Type specifying the DAC buffer watermark levels */ +typedef enum { + LDD_DAC_BUFFER_WATERMARK_L1 = 0x00U, + LDD_DAC_BUFFER_WATERMARK_L2 = 0x01U, + LDD_DAC_BUFFER_WATERMARK_L3 = 0x02U, + LDD_DAC_BUFFER_WATERMARK_L4 = 0x03U +} LDD_DAC_TBufferWatermark; + +#define LDD_DAC_DMA_ERROR 0x01u /*!< DMA error mask */ + +typedef void* LDD_DAC_TDataPtr; /*!< Type specifying the pointer to the DAC data variable */ +typedef uint32 LDD_DAC_TData; /*!< The DAC data variable type */ +typedef uint32 LDD_DAC_TErrorMask; /*!< Error mask */ +typedef uint32 LDD_DAC_TArrayLength; /*!< Array length type */ + +/* +** =================================================================== +** FLASH device types and constants +** =================================================================== +*/ +#define LDD_FLASH_ON_OPERATION_COMPLETE 0x02u /*!< OnOperationComplete event mask */ +#define LDD_FLASH_ON_ERROR 0x04u /*!< OnError event mask */ + +#define LDD_FLASH_READ_COLLISION_ERROR 0x40u /*!< Read collision error flag's mask */ +#define LDD_FLASH_ACCESS_ERROR 0x20u /*!< Access error flag's mask */ +#define LDD_FLASH_PROTECTION_VIOLATION 0x10u /*!< Protection violation error flag's mask */ +#define LDD_FLASH_ERASE_VERIFICATION_ERROR 0x08u /*!< Erase verification error flag's mask */ +#define LDD_FLASH_MULTIPLE_WRITE_ERROR 0x04u /*!< Multiple write to one flash memory location error flag's mask */ + +/*! Type specifying HW commands for a flash device */ +typedef enum { + LDD_FLASH_READ_1S_BLOCK = 0x00u, /*!< Checks if an entire program flash or data flash logical block has been erased to the specified margin level */ + LDD_FLASH_READ_1S_SECTION = 0x01u, /*!< Checks if a section of program flash or data flash memory is erased to the specified read margin level */ + LDD_FLASH_WRITE_BYTE = 0x04u, /*!< Program byte */ + LDD_FLASH_WRITE_WORD = 0x05u, /*!< Program word */ + LDD_FLASH_WRITE_LONG_WORD = 0x06u, /*!< Program long word */ + LDD_FLASH_WRITE_PHRASE = 0x07u, /*!< Program phrase */ + LDD_FLASH_ERASE_FLASH_BLOCK = 0x08u, /*!< Erase flash memory block */ + LDD_FLASH_ERASE_SECTOR = 0x09u, /*!< Erase sector */ + LDD_FLASH_ERASE_ALL_FLASH_BLOCKS = 0x44u /*!< Erase all flash memory blocks */ +} LDD_FLASH_TCommand; + +/*! Type specifying possible FLASH component operation types */ +typedef enum { + LDD_FLASH_NO_OPERATION, /*!< No operation - initial state */ + LDD_FLASH_READ, /*!< Read operation */ + LDD_FLASH_WRITE, /*!< Write operation */ + LDD_FLASH_ERASE, /*!< Erase operation */ + LDD_FLASH_ERASE_BLOCK, /*!< Erase block operation */ + LDD_FLASH_VERIFY_ERASED_BLOCK /*!< Verify erased block operation */ +} LDD_FLASH_TOperationType; + +/*! Type specifying possible FLASH component operation states */ +typedef enum { + LDD_FLASH_FAILED = 0x00u, /*!< Operation has failed */ + LDD_FLASH_STOP = 0x01u, /*!< The operation has been stopped */ + LDD_FLASH_IDLE = 0x02u, /*!< No operation in progress */ + LDD_FLASH_STOP_REQ = 0x03u, /*!< The operation is in the STOP request mode */ + LDD_FLASH_START = 0x04u, /*!< Start of the operation, no operation steps have been done yet */ + LDD_FLASH_RUNNING = 0x05u /*!< Operation is in progress */ +} LDD_FLASH_TOperationStatus; + +typedef uint8 LDD_FLASH_TErrorFlags; /*!< Type specifying FLASH component's error flags bit field */ + +typedef uint32 LDD_FLASH_TAddress; /*!< Type specifying the Address parameter used by the FLASH component's methods */ + +typedef uint32 LDD_FLASH_TDataSize; /*!< Type specifying the Size parameter used by the FLASH component's methods */ + +typedef uint16 LDD_FLASH_TErasableUnitSize; /*!< Type specifying the Size output parameter of the GetErasableUnitSize method (pointer to a variable of this type is passed to the method) */ + +/*! Type specifying the FLASH component's rrror status information */ +typedef struct { + LDD_FLASH_TOperationType CurrentOperation; /*!< Current operation */ + LDD_FLASH_TCommand CurrentCommand; /*!< Last flash controller command */ + LDD_FLASH_TErrorFlags CurrentErrorFlags; /*!< Bitfield with error flags. See FLASH2.h for details */ + LDD_FLASH_TAddress CurrentAddress; /*!< Address of the flash memory location the error status is related to */ + LDD_TData *CurrentDataPtr; /*!< Pointer to current input data the error status is related to */ + LDD_FLASH_TDataSize CurrentDataSize; /*!< Size of the current input data to be programmed or erased in bytes */ +} LDD_FLASH_TErrorStatus; + +/* +** =================================================================== +** HSCMP device types and constants +** =================================================================== +*/ + +#define LDD_ANALOGCOMP_ON_COMPARE 0x01u /*!< OnCompare event mask */ + +/* Positive input pin masks */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_0_MASK 0x01U /*!< Mask for positive input pin 0 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_1_MASK 0x02U /*!< Mask for positive input pin 1 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_2_MASK 0x04U /*!< Mask for positive input pin 2 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_3_MASK 0x08U /*!< Mask for positive input pin 3 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_4_MASK 0x10U /*!< Mask for positive input pin 4 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_5_MASK 0x20U /*!< Mask for positive input pin 5 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_6_MASK 0x40U /*!< Mask for positive input pin 6 */ +#define LDD_ANALOGCOMP_POSITIVE_INPUT_7_MASK 0x80U /*!< Mask for positive input pin 7 */ + +/* Negative input pin masks */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_0_MASK 0x0100U /*!< Mask for negative input pin 0 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_1_MASK 0x0200U /*!< Mask for negative input pin 1 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_2_MASK 0x0400U /*!< Mask for negative input pin 2 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_3_MASK 0x0800U /*!< Mask for negative input pin 3 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_4_MASK 0x1000U /*!< Mask for negative input pin 4 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_5_MASK 0x2000U /*!< Mask for negative input pin 5 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_6_MASK 0x4000U /*!< Mask for negative input pin 6 */ +#define LDD_ANALOGCOMP_NEGATIVE_INPUT_7_MASK 0x8000U /*!< Mask for negative input pin 7 */ + +/* Output pin masks */ +#define LDD_ANALOGCOMP_OUTPUT_PIN_MASK 0x00010000U /*!< Mask for output pin */ + +/* Window Sample pin masks */ +#define LDD_ANALOGCOMP_WINDOWSAMPLE_PIN_MASK 0x00020000UL + +/*! Type specifying comparator input number */ +typedef enum { + LDD_ANALOGCOMP_INPUT_0 = 0x00U, /*!< Analog input 0 selected */ + LDD_ANALOGCOMP_INPUT_1 = 0x01U, /*!< Analog input 1 selected */ + LDD_ANALOGCOMP_INPUT_2 = 0x02U, /*!< Analog input 2 selected */ + LDD_ANALOGCOMP_INPUT_3 = 0x03U, /*!< Analog input 3 selected */ + LDD_ANALOGCOMP_INPUT_4 = 0x04U, /*!< Analog input 4 selected */ + LDD_ANALOGCOMP_INPUT_5 = 0x05U, /*!< Analog input 5 selected */ + LDD_ANALOGCOMP_INPUT_6 = 0x06U, /*!< Analog input 6 selected */ + LDD_ANALOGCOMP_INPUT_7 = 0x07U, /*!< Analog input 7 selected */ + LDD_ANALOGCOMP_INPUT_DISABLED = 0x08U /*!< Analog input disabled */ +} LDD_AnalogComp_TComparatorInput; + +/*! Type specifying current comparator output status */ +typedef enum { + LDD_ANALOGCOMP_NO_EDGE = 0x00U, /*!< No edge detected on output */ + LDD_ANALOGCOMP_FALLING_EDGE = 0x02U, /*!< Falling edge detected on output */ + LDD_ANALOGCOMP_RISING_EDGE = 0x04U, /*!< Rising edge detected on output */ + LDD_ANALOGCOMP_BOTH_EDGES = 0x06U /*!< Both edges detected on output */ +} LDD_AnalogComp_TCompareStatus; + +/*! Type specifying requested comparator mode */ +typedef enum { + LDD_ANALOGCOMP_RISING_EDGE_MODE = 0x10U, /*!< Rising edge detection */ + LDD_ANALOGCOMP_FALLING_EDGE_MODE = 0x08U, /*!< Falling edge detection */ + LDD_ANALOGCOMP_BOTH_EDGES_MODE = 0x18U /*!< Both edges detection */ +} LDD_AnalogComp_TComparatorMode; + +typedef uint8 LDD_AnalogComp_TOutputValue; /*!< Type specifying comparator output value */ + +/* +** =================================================================== +** SDHC component types and constants +** =================================================================== +*/ + +#define LDD_SDHC_CARD_DATA_WIDTH_1_BIT 0x01u /*!< Card supports 1 bit data bus */ +#define LDD_SDHC_CARD_DATA_WIDTH_4_BIT 0x02u /*!< Card supports 4 bit data bus */ +#define LDD_SDHC_CARD_DATA_WIDTH_8_BIT 0x04u /*!< Card supports 8 bit data bus */ +#define LDD_SDHC_CARD_BLOCK_READ 0x01u /*!< Card supports block reading */ +#define LDD_SDHC_CARD_BLOCK_WRITE 0x04u /*!< Card supports block writing */ +#define LDD_SDHC_CARD_ERASE 0x08u /*!< Card supports block erasion */ +#define LDD_SDHC_CARD_WRITE_PROTECTION 0x10u /*!< Card supports write protection */ +#define LDD_SDHC_CARD_IO 0x80u /*!< Card supports IO */ + +#define LDD_SDHC_CLK_PIN 0x01u /*!< SD clock pin mask */ +#define LDD_SDHC_CMD_PIN 0x02u /*!< SD command line pin mask */ +#define LDD_SDHC_DAT0_PIN 0x04u /*!< SD data line 0 pin mask */ +#define LDD_SDHC_DAT1_PIN 0x08u /*!< SD data line 1 pin mask */ +#define LDD_SDHC_DAT2_PIN 0x10u /*!< SD data line 2 pin mask */ +#define LDD_SDHC_DAT3_PIN 0x20u /*!< SD data line 3 pin mask */ +#define LDD_SDHC_DAT4_PIN 0x40u /*!< SD data line 4 pin mask */ +#define LDD_SDHC_DAT5_PIN 0x80u /*!< SD data line 5 pin mask */ +#define LDD_SDHC_DAT6_PIN 0x0100u /*!< SD data line 6 pin mask */ +#define LDD_SDHC_DAT7_PIN 0x0200u /*!< SD data line 7 pin mask */ +#define LDD_SDHC_CD_PIN 0x0400u /*!< SD card detection pin mask */ +#define LDD_SDHC_WP_PIN 0x0800u /*!< SD write protection pin mask */ +#define LDD_SDHC_LCTL_PIN 0x1000u /*!< SD LED control pin mask */ +#define LDD_SDHC_VS_PIN 0x2000u /*!< SD voltage control pin mask */ + +#define LDD_SDHC_ON_CARD_INSERTED 0x01u /*!< OnCardInserted event mask */ +#define LDD_SDHC_ON_CARD_REMOVED 0x02u /*!< OnCardRemoved event mask */ +#define LDD_SDHC_ON_FINISHED 0x04u /*!< OnFinished event mask */ + +/*! Card types */ +typedef enum { + LDD_SDHC_SD, /*!< Secure Digital memory card */ + LDD_SDHC_SDIO, /*!< Secure Digital IO card */ + LDD_SDHC_SDCOMBO, /*!< Combined Secure Digital memory and IO card */ + LDD_SDHC_MMC, /*!< MultiMediaCard memory card */ + LDD_SDHC_CE_ATA /*!< Consumer Electronics ATA card */ +} LDD_SDHC_TCardType; + +/*! Card access properties */ +typedef struct { + uint16 MaxBlockLength; /*!< Max. transferable block length */ + bool MisalignBlock; /*!< Indicates if the data block can be spread over more than one physical block of the memory device */ + bool PartialBlock; /*!< Indicates whether partial block sizes can be used in block access */ +} LDD_SDHC_TCardAccess; + +/*! Card erasion properties */ +typedef struct { + uint16 SectorSize; /*!< The size of an erasable unit */ + uint8 Pattern; /*!< Memory content after erase */ +} LDD_SDHC_TCardErase; + +/*! Card write protection properties */ +typedef struct { + uint16 GroupSize; /*!< The size of write protected group in number of erase groups */ + bool Permanent; /*!< Indicates whether card is permanently write protected (read-only) */ +} LDD_SDHC_TCardWriteProtect; + +/*! Card capabilities */ +typedef struct { + uint8 DataWidths; /*!< Bit mask of supported data bus widths */ + uint8 Operations; /*!< Bit mask of supported operations */ + bool HighSpeed; /*!< Indicates whether the card supports high clock configuration (SD bus clock frequency higher than about 25MHz) */ + bool HighCapacity; /*!< Indicates whether the card requires block addressing instead of byte addressing */ + bool LowVoltage; /*!< Indicates whether the card supports the host's low voltage range */ + LDD_SDHC_TCardAccess Read; /*!< Card data read access capabilities */ + LDD_SDHC_TCardAccess Write; /*!< Card data write access capabilities */ + LDD_SDHC_TCardErase Erase; /*!< Card data erasion capabilities */ + LDD_SDHC_TCardWriteProtect WriteProtect; /*!< Write protection properties */ +} LDD_SDHC_TCardCaps; + +/*! Card features description */ +typedef struct { + LDD_SDHC_TCardType Type; /*!< Card type */ + uint16 BlockLength; /*!< Physical memory block length */ + uint32 BlockCount; /*!< Number of physical memory blocks */ + LDD_SDHC_TCardCaps Caps; /*!< Card capabilities */ +} LDD_SDHC_TCardInfo; + +/*! Transfer operations */ +typedef enum { + LDD_SDHC_READ, /*!< Read operation */ + LDD_SDHC_WRITE /*!< Write operation */ +} LDD_SDHC_TTransferOperation; + +/*! Transfer buffer descriptor */ +typedef struct { + uint16 Size; /*!< Buffer data size */ + uint8 *DataPtr; /*!< Pointer to buffer data */ +} LDD_SDHC_TBufferDesc; + +/*! Voltage options */ +typedef enum { + LDD_SDHC_LOW_VOLTAGE, /*!< Low voltage */ + LDD_SDHC_HIGH_VOLTAGE /*!< High voltage */ +} LDD_SDHC_TVoltage; + +/*! Write protection types */ +typedef enum { + LDD_SDHC_GROUP, /*!< Write protection by groups */ + LDD_SDHC_CARD /*!< Whole card write protection */ +} LDD_SDHC_TWriteProtectType; + +/*! Component states */ +typedef enum { + LDD_SDHC_DISABLED, /*!< Disabled */ + LDD_SDHC_RESET, /*!< Resetting card */ + LDD_SDHC_IDLE, /*!< Idling */ + LDD_SDHC_VOLTAGE_VALIDATION, /*!< Validating voltage */ + LDD_SDHC_CARD_REGISTRATION, /*!< Registrating card */ + LDD_SDHC_CARD_SELECTION, /*!< Selecting card */ + LDD_SDHC_CARD_INFO_RETRIEVAL, /*!< Retrieving card info */ + LDD_SDHC_TRANSFER, /*!< Transferring data */ + LDD_SDHC_ERASION, /*!< Erasing blocks */ + LDD_SDHC_IO_REG_TRANSFER, /*!< Transferring IO registers */ + LDD_SDHC_DATA_WIDTH_SELECTION, /*!< Selecting data width */ + LDD_SDHC_BUS_CLOCK_SELECTION, /*!< Selecting bus clock */ + LDD_SDHC_WRITE_PROTECTION_SETUP, /*!< Setting up write protection */ + LDD_SDHC_WRITE_PROTECTION_RETRIEVAL /*!< Retrieving write protection configuration */ +} LDD_SDHC_TStatus; + +/*! Operation completion error codes */ +typedef enum { + LDD_SDHC_ERR_OK, /*!< No error */ + LDD_SDHC_ERR_DMA, /*!< DMA or block size error */ + LDD_SDHC_ERR_NOT_SUPPORTED, /*!< Initiated operation is not supported by the card (supported operations are contained in the card information structure) */ + LDD_SDHC_ERR_TIMEOUT, /*!< Command or data timeout */ + LDD_SDHC_ERR_COMMAND_CRC, /*!< Command CRC check failed */ + LDD_SDHC_ERR_DATA_CRC, /*!< Data CRC check failed */ + LDD_SDHC_ERR_ADDRESS_OUT_OF_RANGE, /*!< The card address is beyond the card capacity */ + LDD_SDHC_ERR_ADDRESS_MISALIGN, /*!< The card address does not align with physical blocks of the card */ + LDD_SDHC_ERR_BLOCK_LEN_ERROR, /*!< Block length exceeds the maximum value for the card */ + LDD_SDHC_ERR_WP_VIOLATION, /*!< Attempt to program a write protected block */ + LDD_SDHC_ERR_CARD_IS_LOCKED, /*!< The card is locked by the host */ + LDD_SDHC_ERR_WP_ERASE_SKIP, /*!< Only partial address space was erased due to existing write protected blocks */ + LDD_SDHC_ERR_INTERNAL_FAILURE, /*!< Internal component error */ + LDD_SDHC_ERR_CARD_FAILURE /*!< The card was unable to complete the operation */ +} LDD_SDHC_TError; + +/* +** =================================================================== +** DMA device types and constants +** =================================================================== +*/ + +#define LDD_DMA_ON_COMPLETE 0x01U /*!< OnTransferComplete event mask. */ +#define LDD_DMA_ON_ERROR 0x02U /*!< OnError event mask. */ + +#define LDD_DMA_UNKNOWN_ERROR 0x80000000U /*!< Unknown error. */ +#define LDD_DMA_CHANNEL_PRIORITY_ERROR 0x4000U /*!< Channel priority error. */ +#define LDD_DMA_SOURCE_ADDRESS_ERROR 0x80U /*!< Address inconsistency with transfer size error. */ +#define LDD_DMA_SOURCE_OFFSET_ERROR 0x40U /*!< Offset inconsistency with transfer size error. */ +#define LDD_DMA_DESTINATION_ADDRESS_ERROR 0x20U /*!< Address inconsistency with transfer size error. */ +#define LDD_DMA_DESTINATION_OFFSET_ERROR 0x10U /*!< Offset inconsistency with transfer size error. */ +#define LDD_DMA_COUNT_ERROR 0x08U /*!< Byte count inconsistency with transfer sizes or transfer count error. */ +#define LDD_DMA_SCATTER_GATHER_ERROR 0x04U /*!< Scatter/gather configuration error. */ +#define LDD_DMA_SOURCE_BUS_ERROR 0x02U /*!< Bus error on a source read. */ +#define LDD_DMA_DESTINATION_BUS_ERROR 0x01U /*!< Bus error on a destination write. */ + +#define LDD_DMA_CHANNEL_0_MASK 0x01UL /*!< DMA channel 0 mask. */ +#define LDD_DMA_CHANNEL_1_MASK 0x02UL /*!< DMA channel 1 mask. */ +#define LDD_DMA_CHANNEL_2_MASK 0x04UL /*!< DMA channel 2 mask. */ +#define LDD_DMA_CHANNEL_3_MASK 0x08UL /*!< DMA channel 3 mask. */ +#define LDD_DMA_CHANNEL_4_MASK 0x10UL /*!< DMA channel 4 mask. */ +#define LDD_DMA_CHANNEL_5_MASK 0x20UL /*!< DMA channel 5 mask. */ +#define LDD_DMA_CHANNEL_6_MASK 0x40UL /*!< DMA channel 6 mask. */ +#define LDD_DMA_CHANNEL_7_MASK 0x80UL /*!< DMA channel 7 mask. */ +#define LDD_DMA_CHANNEL_8_MASK 0x0100UL /*!< DMA channel 8 mask. */ +#define LDD_DMA_CHANNEL_9_MASK 0x0200UL /*!< DMA channel 9 mask. */ +#define LDD_DMA_CHANNEL_10_MASK 0x0400UL /*!< DMA channel 10 mask. */ +#define LDD_DMA_CHANNEL_11_MASK 0x0800UL /*!< DMA channel 11 mask. */ +#define LDD_DMA_CHANNEL_12_MASK 0x1000UL /*!< DMA channel 12 mask. */ +#define LDD_DMA_CHANNEL_13_MASK 0x2000UL /*!< DMA channel 13 mask. */ +#define LDD_DMA_CHANNEL_14_MASK 0x4000UL /*!< DMA channel 14 mask. */ +#define LDD_DMA_CHANNEL_15_MASK 0x8000UL /*!< DMA channel 15 mask. */ +#define LDD_DMA_CHANNEL_16_MASK 0x00010000UL /*!< DMA channel 16 mask. */ +#define LDD_DMA_CHANNEL_17_MASK 0x00020000UL /*!< DMA channel 17 mask. */ +#define LDD_DMA_CHANNEL_18_MASK 0x00040000UL /*!< DMA channel 18 mask. */ +#define LDD_DMA_CHANNEL_19_MASK 0x00080000UL /*!< DMA channel 19 mask. */ +#define LDD_DMA_CHANNEL_20_MASK 0x00100000UL /*!< DMA channel 21 mask. */ +#define LDD_DMA_CHANNEL_21_MASK 0x00200000UL /*!< DMA channel 22 mask. */ +#define LDD_DMA_CHANNEL_22_MASK 0x00400000UL /*!< DMA channel 23 mask. */ +#define LDD_DMA_CHANNEL_23_MASK 0x00800000UL /*!< DMA channel 24 mask. */ +#define LDD_DMA_CHANNEL_24_MASK 0x01000000UL /*!< DMA channel 25 mask. */ +#define LDD_DMA_CHANNEL_25_MASK 0x02000000UL /*!< DMA channel 26 mask. */ +#define LDD_DMA_CHANNEL_26_MASK 0x04000000UL /*!< DMA channel 27 mask. */ +#define LDD_DMA_CHANNEL_27_MASK 0x08000000UL /*!< DMA channel 28 mask. */ +#define LDD_DMA_CHANNEL_28_MASK 0x10000000UL /*!< DMA channel 29 mask. */ +#define LDD_DMA_CHANNEL_29_MASK 0x20000000UL /*!< DMA channel 30 mask. */ +#define LDD_DMA_CHANNEL_30_MASK 0x40000000UL /*!< DMA channel 31 mask. */ +#define LDD_DMA_CHANNEL_31_MASK 0x80000000UL /*!< DMA channel 32 mask. */ + +/* Action executed after request and transfer service completes */ +#define LDD_DMA_NO_ACTION 0x00U /*!< No action performed after request serviced. */ +#define LDD_DMA_DESTINATION_ADDRESS_ADJUSTMENT 0x01U /*!< Destination address adjustment after request serviced. */ +#define LDD_DMA_SOURCE_ADDRESS_ADJUSTMENT 0x02U /*!< Source address adjustment after request serviced. */ +#define LDD_DMA_ADDRESS_ADJUSTMENT 0x01U /*!< Address adjustment after transfer completed. */ +#define LDD_DMA_SCATTER_GATHER 0x02U /*!< Scatter/gather performed after transfer completed. */ + +typedef void LDD_DMA_TData; +typedef uint8 LDD_DMA_TTransactionSize; /* Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint32 LDD_DMA_TTransactionCount; +typedef uint32 LDD_DMA_TRequestCount; +typedef uint32 LDD_DMA_TTransferDataSize; + +typedef uint32 LDD_DMA_TAddress; /*!< Type specifying the address parameter used by the DMA component's methods. */ +typedef int32 LDD_DMA_TAddressOffset; /*!< Type specifying the address signed offset parameter used by the DMA component's methods. */ +typedef uint32 LDD_DMA_TByteCount; /*!< Type specifying the byte count/minor loop count parameter used by the DMA component's methods. */ +typedef uint8 LDD_DMA_TTransferSize; /*!< Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint8 LDD_DMA_TModuloSize; /*!< Type specifying the modulo size parameter used by the DMA component's methods. */ + /*!< This value power of two represents size of used circular buffer (0U - buffer disabled). See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TTriggerSource; /*!< Type specifying the trigger source signal number. See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TChannelNumber; /*!< Type specifying the DMA channel number. See the MCU manual for detail description of allowed values. */ +typedef uint8 LDD_DMA_TRecordNumber; /*!< Type specifying the DMA descriptor record number. */ +typedef uint32 LDD_DMA_TChannelMask; /*!< Type specifying the DMA channel mask. For possible values see channel mask constants. */ +typedef uint8 LDD_DMA_TChannelPriority; /*!< Type specifying the DMA channel priority number. See the MCU manual for detail description of allowed values. */ +typedef uint16 LDD_DMA_TOuterLoopCount; /*!< Type specifying the transfer outer/major loop count. */ +typedef uint8 LDD_DMA_TAfterRequest; /*!< Type specifying the operation executed after request service is completed. */ +typedef uint8 LDD_DMA_TAfterTransfer; /*!< Type specifying the operation executed after transfer service is completed. */ +typedef uint8 LDD_DMA_TBandwidthControl; /*!< Type specifying the bandwidth control. See the DMA_PDD header file for detail description of allowed values. */ +typedef uint32 LDD_DMA_TErrorFlags; /*!< DMA controller error flags. See the DMA_LDD component's header file for detail description of allowed values. */ + +/*! Type specifying a DMA channel status. */ +typedef enum { + LDD_DMA_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */ + LDD_DMA_BUSY, /*!< Channel is active, request is serviced. */ + LDD_DMA_DONE, /*!< Transfer is completed, waiting to start of next transfer. */ + LDD_DMA_ERROR /*!< Error detected. */ +} LDD_DMA_TChannelStatus; + +/*! Type specifying a DMA transfer state. */ +typedef enum { + LDD_DMA_TRANSFER_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */ + LDD_DMA_TRANSFER_BUSY, /*!< Channel is active, request is serviced. */ + LDD_DMA_TRANSFER_ERROR /*!< Error detected. */ +} LDD_DMA_TTransferState; + +/*! Type specifying the DMA transfer mode. */ +typedef enum { + LDD_DMA_CYCLE_STEAL_TRANSFERS, /*!< Only single read/write transfer is done per one service request. */ + LDD_DMA_SINGLE_TRANSFER, /*!< Transfer of all bytes defined by Data size is done after single service request. */ + LDD_DMA_NESTED_TRANSFERS /*!< Sequence of transfers triggered by service requests. One request transfers number of bytes defined by Byte count value. */ +} LDD_DMA_TTransferMode; + +/*! Type specifying the DMA trigger source type. */ +typedef enum { + LDD_DMA_SW_TRIGGER, /*!< Explicit software trigger. */ + LDD_DMA_HW_TRIGGER, /*!< Peripheral device trigger. */ + LDD_DMA_ALWAYS_ENABLED_TRIGGER /*!< Always enabled trigger. */ +} LDD_DMA_TTriggerType; + +/*! Type specifying the DMA error information structure. */ +typedef struct { + LDD_DMA_TChannelNumber ChannelNumber; /*!< Last error recorded channel number. */ + LDD_DMA_TErrorFlags ErrorFlags; /*!< Channel error flags. */ +} LDD_DMA_TError; + +/*! Type specifying the DMA Transfer descriptor information structure. */ +typedef struct { + LDD_TUserData *UserDataPtr; /*!< User device data structure pointer to be returned by the DMA_LDD component's ISR to the dynamic callback of this transfer descriptor. */ + LDD_DMA_TAddress SourceAddress; /*!< Address of a DMA transfer source data. */ + LDD_DMA_TAddressOffset SourceAddressOffset; /*!< Offset to be added to the source address after each elemental read operation. */ + LDD_DMA_TTransferSize SourceTransferSize; /*!< Source data transfer size (size of a elemental read operation). See the DMA_PDD header file for detail description of allowed values. */ + LDD_DMA_TModuloSize SourceModuloSize; /*!< Source address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */ + LDD_DMA_TAddress DestinationAddress; /*!< Address of a DMA transfer destination. */ + LDD_DMA_TAddressOffset DestinationAddressOffset; /*!< Offset to be added to the destination address after each elemental write operation. */ + LDD_DMA_TTransferSize DestinationTransferSize; /*!< Destination data transfer size (size of a elemental write operation). See the DMA_PDD header file for detail description of allowed values. */ + LDD_DMA_TModuloSize DestinationModuloSize; /*!< Destination address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */ + LDD_DMA_TTransferMode TransferMode; /*!< Selects DMA transfer mode. For the description of allowed values see the LDD_DMA_TTransferMode type declaration. */ + LDD_DMA_TByteCount ByteCount; /*!< Size of data in bytes to be transferred in single transfer. */ + LDD_DMA_TOuterLoopCount OuterLoopCount; /*!< Number of the outer loop iteration in the Nested operation mode, otherwise should have value of one. */ + bool InnerLoopChannelLink; /*!< TRUE - Inner loop channel linking enabled (if the nested operation is used, then this item enables the minor (inner) loop channel linking). */ + LDD_DMA_TChannelNumber InnerLoopLinkedChannel; /*!< Linked DMA channel number (used only if the InnerLoopChannelLink item is set TRUE) */ + bool OuterLoopChannelLink; /*!< TRUE - Outer (major) loop channel linking is enabled. Enables channel linking after transfer completes. */ + LDD_DMA_TChannelNumber OuterLoopLinkedChannel; /*!< Outer (major) loop linked DMA channel number (used only if the OuterLoopChannelLink item is set TRUE). */ + LDD_DMA_TAfterRequest AfterRequestComplete; /*!< Type of an action after the elemental read/write operation is done. For the description of allowed values see the LDD_DMA_TAfterRequest type declaration. */ + LDD_DMA_TAddressOffset AddressOffset; /*!< Address offset value. Address specified in AfterRequestComplete item is adjusted by stored value. See the LDD_DMA_TAfterRequest type declaration. */ + LDD_DMA_TAfterTransfer AfterTransferComplete; /*!< Type of an action executed after the last transfer operation is done. For the description of allowed values see the LDD_DMA_TAfterTransfer type declaration. */ + LDD_DMA_TAddressOffset SourceAddressAdjustment; /*!< Source address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */ + LDD_DMA_TAddressOffset DestinationAddressAdjustment; /*!< Destination address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */ + LDD_DMA_TAddress ScatterGatherAddress; /*!< Scatter / gather address. Used only if the AfterTransferComplete item is set to LDD_DMA_SCATTER_GATHER. */ + LDD_DMA_TBandwidthControl BandwidthControl; /*!< DMA channel bandwidth control. See the DMA_PDD header file for detail description of allowed values. */ + bool ChannelAutoSelection; /*!< TRUE - DMA channel autoselection engine is used. FALSE - DMA fixed channel is used. */ + LDD_DMA_TChannelNumber ChannelNumber; /*!< If ChannelAutoSelection is FALSE this item contains fixed channel number. If ChannelAutoSelection is TRUE then after allocation this item is filled by autoselected channel number. */ + LDD_DMA_TTriggerType TriggerType; /*!< DMA transfer trigger type. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */ + LDD_DMA_TTriggerSource TriggerSource; /*!< Trigger source number. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */ + bool PeriodicTrigger; /*!< TRUE - periodic trigger is required, FALSE - periodic trigger is not required. */ + bool DisableAfterRequest; /*!< TRUE - DMA transfer request is automatically disabled after transfer complete. */ + bool Interrupts; /*!< TRUE - interrupts are requested. */ + bool OnComplete; /*!< TRUE - event is enabled during initialization. */ + bool OnHalfComplete; /*!< TRUE - event is enabled during initialization. */ + bool OnError; /*!< TRUE - event is enabled during initialization. */ + void (*OnCompleteEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnComplete event, NULL if event is not used. */ + void (*OnErrorEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnError event, NULL if event is not used. */ + bool ChannelEnabled; /*!< TRUE - DMA channel is allocated and used by DMATransfer component. */ +} LDD_DMA_TTransferDescriptor; + +typedef LDD_DMA_TTransferDescriptor *LDD_DMA_TTransferDescriptorPtr; /*!< Type specifying address of the DMA Transfer descriptor structure. */ + +/* +** =================================================================== +** SPI device types and constants - SPIMaster_LDD +** =================================================================== +*/ + +#define LDD_SPIMASTER_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SPIMASTER_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SPIMASTER_CLK_PIN 0x04U /*!< Clock pin mask */ +#define LDD_SPIMASTER_CS_0_PIN 0x08U /*!< Chip select 0 pin mask */ +#define LDD_SPIMASTER_CS_1_PIN 0x10U /*!< Chip select 1 pin mask */ +#define LDD_SPIMASTER_CS_2_PIN 0x20U /*!< Chip select 2 pin mask */ +#define LDD_SPIMASTER_CS_3_PIN 0x40U /*!< Chip select 3 pin mask */ +#define LDD_SPIMASTER_CS_4_PIN 0x80U /*!< Chip select 4 pin mask */ +#define LDD_SPIMASTER_CS_5_PIN 0x0100U /*!< Chip select 5 pin mask */ +#define LDD_SPIMASTER_CS_6_PIN 0x0200U /*!< Chip select 6 pin mask */ +#define LDD_SPIMASTER_CS_7_PIN 0x0400U /*!< Chip select 7 pin mask */ +#define LDD_SPIMASTER_CSS_PIN 0x0800U /*!< Chip select strobe pin mask */ + +#define LDD_SPIMASTER_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */ +#define LDD_SPIMASTER_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */ +#define LDD_SPIMASTER_ON_ERROR 0x04U /*!< OnError event mask */ + +#define LDD_SPIMASTER_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SPIMASTER_PARITY_ERROR 0x02U /*!< Parity error */ +#define LDD_SPIMASTER_RX_DMA_ERROR 0x04U /*!< Receive DMA channel error */ +#define LDD_SPIMASTER_TX_DMA_ERROR 0x08U /*!< Transmit DMA channel error */ + +typedef uint32 LDD_SPIMASTER_TError; /*!< Communication error type */ + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxParityErrors; /*!< Number of receiver parity errors, which have occured */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ +} LDD_SPIMASTER_TStats; + +/* +** =================================================================== +** SPI device types and constants - SPISlave_LDD +** =================================================================== +*/ + +#define LDD_SPISLAVE_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SPISLAVE_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SPISLAVE_CLK_PIN 0x04U /*!< Clock pin mask */ +#define LDD_SPISLAVE_SS_PIN 0x08U /*!< Slave select pin mask */ + +#define LDD_SPISLAVE_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */ +#define LDD_SPISLAVE_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */ +#define LDD_SPISLAVE_ON_ERROR 0x04U /*!< OnError event mask */ + +#define LDD_SPISLAVE_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SPISLAVE_TX_UNDERFLOW 0x02U /*!< Transmitter underflow */ +#define LDD_SPISLAVE_PARITY_ERROR 0x04U /*!< Parity error */ +#define LDD_SPISLAVE_RX_DMA_ERROR 0x08U /*!< Receive DMA channel error */ +#define LDD_SPISLAVE_TX_DMA_ERROR 0x10U /*!< Transmit DMA channel error */ + +typedef uint32 LDD_SPISLAVE_TError; /*!< Communication error type */ + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxParityErrors; /*!< Number of receiver parity errors, which have occured */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ + uint32 TxUnderruns; /*!< Number of transmitter underruns, which have occured */ +} LDD_SPISLAVE_TStats; + +/* +** =================================================================== +** I2S device types and constants +** =================================================================== +*/ + +#define LDD_SSI_INPUT_PIN 0x01U /*!< Input pin mask */ +#define LDD_SSI_OUTPUT_PIN 0x02U /*!< Output pin mask */ +#define LDD_SSI_RX_CLK_PIN 0x04U /*!< Rx clock pin mask */ +#define LDD_SSI_TX_CLK_PIN 0x08U /*!< Tx clock pin mask */ +#define LDD_SSI_RX_FS_PIN 0x10U /*!< Rx frame sync pin mask */ +#define LDD_SSI_TX_FS_PIN 0x20U /*!< Tx frame sync pin mask */ +#define LDD_SSI_MCLK_PIN 0x40U /*!< Master clock pin mask */ +#define LDD_SSI_INPUT_PIN_CHANNEL_0 0x80U /*!< Input pin mask for data channel 0 */ +#define LDD_SSI_INPUT_PIN_CHANNEL_1 0x0100U /*!< Input pin mask for data channel 1 */ +#define LDD_SSI_OUTPUT_PIN_CHANNEL_0 0x0200U /*!< Output pin mask for data channel 0 */ +#define LDD_SSI_OUTPUT_PIN_CHANNEL_1 0x0400U /*!< Output pin mask for data channel 1 */ + +#define LDD_SSI_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */ +#define LDD_SSI_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */ +#define LDD_SSI_ON_ERROR 0x04u /*!< OnError event mask */ +#define LDD_SSI_ON_BLOCK_RECEIVED_1 0x08u /*!< OnBlockReceived event mask for second channel */ +#define LDD_SSI_ON_BLOCK_SENT_1 0x10u /*!< OnBlockSent event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_FRAME_SYNC 0x20u /*!< OnReceiveFrameSync event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_FRAME_SYNC 0x40u /*!< OnTransmitFrameSync event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_LAST_SLOT 0x80u /*!< OnReceiveLastSlot event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_LAST_SLOT 0x0100u /*!< OnTransmitLastSlot event mask for second channel */ +#define LDD_SSI_ON_RECEIVE_COMPLETE 0x0200u /*!< OnReceiveComplete event mask for second channel */ +#define LDD_SSI_ON_TRANSMIT_COMPLETE 0x0400u /*!< OnTransmitComplete event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */ +#define LDD_SSI_ON_A_C_9_7_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */ +#define LDD_SSI_ON_AC_97_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */ + +#define LDD_SSI_RECEIVER 0x01U /*!< Receive section of the device. */ +#define LDD_SSI_TRANSMITTER 0x02U /*!< Transmit section of the device. */ + +#define LDD_SSI_RX_OVERFLOW 0x01U /*!< Receiver overflow */ +#define LDD_SSI_RX_OVERFLOW_1 0x02U /*!< Receiver overflow 1 */ +#define LDD_SSI_RX_SYNC_ERROR 0x04U /*!< Receiver frame sync error */ +#define LDD_SSI_RX_DMA_ERROR 0x08U /*!< Receiver DMA error */ + +#define LDD_SSI_TX_UNDERFLOW 0x10U /*!< Transmitter underflow */ +#define LDD_SSI_TX_UNDERFLOW_1 0x20U /*!< Transmitter underflow 1 */ +#define LDD_SSI_TX_SYNC_ERROR 0x40U /*!< Transmitter frame sync error */ +#define LDD_SSI_TX_DMA_ERROR 0x80U /*!< Transmitter DMA error */ + +#define LDD_SSI_RX_FRAME_COMPLETE 0x01U /*!< Receive frame is finished after disabling transfer */ +#define LDD_SSI_TX_FRAME_COMPLETE 0x02U /*!< Transmit frame is finished after disabling transfer */ +#define LDD_SSI_RX_FRAME_SYNC 0x04U /*!< Receiver frame sync */ +#define LDD_SSI_TX_FRAME_SYNC 0x08U /*!< Transmit frame sync */ +#define LDD_SSI_RX_LAST_SLOT 0x10U /*!< Receive last time slot */ +#define LDD_SSI_TX_LAST_SLOT 0x20U /*!< Transmit last time slot */ +#define LDD_SSI_AC97_TAG 0x40U /*!< AC97 tag updated */ +#define LDD_SSI_AC97_COMMAND_ADDRESS 0x80U /*!< AC97 command address updated */ +#define LDD_SSI_AC97_COMMAND_DATA 0x0100U /*!< AC97 command data updated */ + +typedef uint8 LDD_SSI_TSectionMask; /*!< Device section type */ + +typedef uint32 LDD_SSI_TError; /*!< Communication error type */ + +typedef uint32 LDD_SSI_TComStatus; /*!< Communication status type */ + +/*! Group of pointers to data blocks. */ +typedef struct { + LDD_TData *Channel0Ptr; /*!< Pointer to data block to send/received via data channel 0 */ + LDD_TData *Channel1Ptr; /*!< Pointer to data block to send/received via data channel 1 */ +} LDD_SSI_TDataBlocks; + +/*! Command type */ +typedef enum { + LDD_SSI_READ_COMMAND = 0x08u, + LDD_SSI_WRITE_COMMAND = 0x10u +} LDD_SSI_TAC97CommandType; + +/*! AC97 command */ +typedef struct { + LDD_SSI_TAC97CommandType Type; /*!< Command type */ + uint32 Address; /*!< Command address */ + uint32 Data; /*!< Command data */ +} LDD_SSI_TAC97Command; + +/*! Communication statistics */ +typedef struct { + uint32 RxChars; /*!< Number of received characters */ + uint32 TxChars; /*!< Number of transmitted characters */ + uint32 RxOverruns; /*!< Number of receiver overruns, which have occured */ + uint32 TxUnderruns; /*!< Number of transmitter underruns, which have occured */ + uint32 RxChars1; /*!< Number of received characters for second channel */ + uint32 TxChars1; /*!< Number of transmitted characters for second channel */ + uint32 RxOverruns1; /*!< Number of receiver overruns, which have occured for second channel */ + uint32 TxUnderruns1; /*!< Number of transmitter underruns, which have occured for second channel */ +} LDD_SSI_TStats; + +/* +** =================================================================== +** RTC device types and constants +** =================================================================== +*/ + +#define LDD_RTC_ON_SECOND 0x10u /*!< OnSecond event mask */ +#define LDD_RTC_ON_MONOTONIC_OVERFLOW 0x08u /*!< OnMonotonicCounter event mask */ +#define LDD_RTC_ON_ALARM 0x04u /*!< OnAlarm event mask */ +#define LDD_RTC_ON_TIME_OVERFLOW 0x02u /*!< OnTimeOverflow event mask */ +#define LDD_RTC_ON_TIME_INVALID 0x01u /*!< OnTimeInvalid event mask */ +#define LDD_RTC_ON_STOPWATCH 0x0100u /*!< OnStopwatch event mask */ + +/*! Structure used for time operation */ +typedef struct { + uint32 Second; /*!< seconds (0 - 59) */ + uint32 Minute; /*!< minutes (0 - 59) */ + uint32 Hour; /*!< hours (0 - 23) */ + uint32 DayOfWeek; /*!< day of week (0-Sunday, .. 6-Saturday) */ + uint32 Day; /*!< day (1 - 31) */ + uint32 Month; /*!< month (1 - 12) */ + uint32 Year; /*!< year */ +} LDD_RTC_TTime; + + + +/* +** =================================================================== +** CRC device types and constants +** =================================================================== +*/ + +#define LDD_CRC_16_SEED_LOW 0x00U /*!< CRC 16bit seed low */ +#define LDD_CRC_16_POLY_LOW 0x8005U /*!< CRC 16bit poly low */ +#define LDD_CRC_32_SEED_LOW 0xFFFFU /*!< CRC 32bit seed low */ +#define LDD_CRC_32_SEED_HIGH 0xFFFFU /*!< CRC 32bit seed high */ +#define LDD_CRC_32_POLY_LOW 0x1DB7U /*!< CRC 32bit poly low */ +#define LDD_CRC_32_POLY_HIGH 0x04C1U /*!< CRC 32bit poly high */ +#define LDD_CRC_CCITT_SEED_LOW 0xFFFFU /*!< CRC CCITT seed low */ +#define LDD_CRC_CCITT_POLY_LOW 0x1021U /*!< CRC CCITT poly low */ +#define LDD_CRC_MODBUS_16_SEED_LOW 0xFFFFU /*!< CRC MODBUS16 seed low */ +#define LDD_CRC_MODBUS_16_POLY_LOW 0x8005U /*!< CRC MODBUS16 poly low */ +#define LDD_CRC_KERMIT_SEED_LOW 0x00U /*!< CRC KERMIT seed low */ +#define LDD_CRC_KERMIT_POLY_LOW 0x1021U /*!< CRC KERMIT poly low */ +#define LDD_CRC_DNP_SEED_LOW 0x00U /*!< CRC DNP seed low */ +#define LDD_CRC_DNP_POLY_LOW 0x3D65U /*!< CRC DNP poly low */ + +/*! Transpose type */ +typedef enum { + LDD_CRC_NO_TRANSPOSE = 0, /*!< No transposition */ + LDD_CRC_BITS = 1, /*!< Bits are transposed */ + LDD_CRC_BITS_AND_BYTES = 2, /*!< Bits and bytes are transposed */ + LDD_CRC_BYTES = 3 /*!< Bytes are transposed */ +} LDD_CRC_TTransposeType; + +/*! CRC standard */ +typedef enum { + LDD_CRC_16, /*!< CRC16 standard */ + LDD_CRC_CCITT, /*!< CCITT standard */ + LDD_CRC_MODBUS_16, /*!< MODBUS16 standard */ + LDD_CRC_KERMIT, /*!< KERMIT standard */ + LDD_CRC_DNP, /*!< DNP standard */ + LDD_CRC_32, /*!< CRC32 standard */ + LDD_CRC_USER /*!< User defined type */ +} LDD_CRC_TCRCStandard; + +/*! User CRC standard */ +typedef struct { + bool Width32bit; /*!< 32bit CRC? */ + bool ResultXORed; /*!< Result XORed? */ + uint16 SeedLow; /*!< Seed low value */ + uint16 SeedHigh; /*!< Seed high value */ + uint16 PolyLow; /*!< Poly low value */ + uint16 PolyHigh; /*!< Poly high value */ + LDD_CRC_TTransposeType InputTransposeMode; /*!< Input transpose type */ + LDD_CRC_TTransposeType OutputTransposeMode; /*!< Output transpose type */ +} LDD_CRC_TUserCRCStandard; + +/* +** =================================================================== +** RNG device types and constants +** =================================================================== +*/ + + +#define LDD_RNG_LFSR_ERROR 0x01U /*!< Linear feedback shift register error */ +#define LDD_RNG_OSCILLATOR_ERROR 0x02U /*!< Oscillator error */ +#define LDD_RNG_SELF_TEST_ERROR 0x04U /*!< Self test error */ +#define LDD_RNG_STATISTICAL_ERROR 0x08U /*!< LStatistical test error */ +#define LDD_RNG_FIFO_UNDERFLOW_ERROR 0x10U /*!< FIFO underflow error */ + +#define LDD_RNG_SELF_TETS_RESEED_ERROR 0x00200000U /*!< Reseed self test fail */ +#define LDD_RNG_SELF_TEST_PRNG_ERROR 0x00400000U /*!< PRNG self test fail */ +#define LDD_RNG_SELF_TEST_TRNG_ERROR 0x00800000U /*!< TRNG self test fail */ +#define LDD_RNG_MONOBIT_TEST_ERROR 0x01000000U /*!< Monobit test fail */ +#define LDD_RNG_LENGTH_1_RUN_TEST_ERROR 0x02000000U /*!< Length 1 run test fail */ +#define LDD_RNG_LENGTH_2_RUN_TEST_ERROR 0x04000000U /*!< Length 2 run test fail */ +#define LDD_RNG_LENGTH_3_RUN_TEST_ERROR 0x08000000U /*!< Length 3 run test fail */ +#define LDD_RNG_LENGTH_4_RUN_TEST_ERROR 0x10000000U /*!< Length 4 run test fail */ +#define LDD_RNG_LENGTH_5_RUN_TEST_ERROR 0x20000000U /*!< Length 5 run test fail */ +#define LDD_RNG_LENGTH_6_RUN_TEST_ERROR 0x40000000U /*!< Length 6 run test fail */ +#define LDD_RNG_LONG_RUN_TEST_ERROR 0x80000000U /*!< Long run test fail */ + +#define LDD_RNG_ON_SEED_GENERATION_DONE 0x01U /*!< OnSeedGenerationDone event mask */ +#define LDD_RNG_ON_SELF_TEST_DONE 0x02U /*!< OnSelfTestDone event mask */ +#define LDD_RNG_ON_ERROR_LFSR 0x04U /*!< OnErrorLFSR event mask */ +#define LDD_RNG_ON_OSC_ERROR 0x08U /*!< OnOscError event mask */ +#define LDD_RNG_ON_SELF_TEST_ERROR 0x10U /*!< OnSelfTestError event mask */ +#define LDD_RNG_ON_STATISTICAL_ERROR 0x20U /*!< OnStatisticalError event mask */ +#define LDD_RNG_ON_FIFO_UNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */ +#define LDD_RNG_ON_FIFOUNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */ + +#define LDD_RNG_STATUS_ERROR 0xFFFFU /*!< Error in RNG module flag */ +#define LDD_RNG_STATUS_NEW_SEED_DONE 0x40U /*!< New seed done flag */ +#define LDD_RNG_STATUS_SEED_DONE 0x20U /*!< Seed done flag */ +#define LDD_RNG_STATUS_SELF_TEST_DONE 0x10U /*!< Self test done flag */ +#define LDD_RNG_STATUS_RESEED_NEEDED 0x08U /*!< Reseed needed flag */ +#define LDD_RNG_STATUS_SLEEP 0x04U /*!< RNG in sleep mode */ +#define LDD_RNG_STATUS_BUSY 0x02U /*!< RNG busy flag */ + + +/* +** =================================================================== +** RNGA device types and constants +** =================================================================== +*/ + +#define LDD_RNG_ON_ERROR 0x01U /*!< OnError event mask */ + +#define LDD_RNG_STATUS_SECURITY_VIOLATION 0x01U /*!< Security violation occured */ +#define LDD_RNG_STATUS_LAST_READ_UNDERFLOW 0x02U /*!< Last read from RNGA caused underflow error */ +#define LDD_RNG_STATUS_OUT_REG_UNDERFLOW 0x04U /*!< The RNGA Output Register has been read while empty since last read of the RNGA Status Register. */ +#define LDD_RNG_STATUS_ERR_INT_PENDING 0x08U /*!< Error interrupt pending */ +#define LDD_RNG_STATUS_SLEEP_MODE 0x10U /*!< Sleep mode enabled */ + +/*! RNGA sleep mode */ +typedef enum { + LDD_RNG_SLEEP_ENABLED, /*!< RNGA is in sleep mode */ + LDD_RNG_SLEEP_DISABLED /*!< RNGA is running */ +} LDD_RNG_TSleepMode; + +/* +** =================================================================== +** DryIce device types and constants +** =================================================================== +*/ + +#define LDD_DRY_ON_TAMPER_DETECTED 0x01U /*!< OnTamperDetected event mask */ + +/* Tamper flags */ +#define LDD_DRY_TIME_OVERFLOW 0x04U /*!< RTC time overflow has occurred. */ +#define LDD_DRY_MONOTONIC_OVERFLOW 0x08U /*!< RTC monotonic overflow has occurred. */ +#define LDD_DRY_VOLTAGE_TAMPER 0x10U /*!< VBAT voltage is outside of the valid range. */ +#define LDD_DRY_CLOCK_TAMPER 0x20U /*!< The 32.768 kHz clock source is outside the valid range. */ +#define LDD_DRY_TEMPERATURE_TAMPER 0x40U /*!< The junction temperature is outside of specification. */ +#define LDD_DRY_SECURITY_TAMPER 0x80U /*!< The (optional) security module asserted its tamper detect. */ +#define LDD_DRY_FLASH_SECURITY 0x0100U /*!< The flash security is disabled. */ +#define LDD_DRY_TEST_MODE 0x0200U /*!< Any test mode has been entered. */ +/* Tamper flags indicating that the pin does not equal its expected value and was not filtered by the glitch filter (if enabled). */ +#define LDD_DRY_TAMPER_PIN_0 0x00010000U /*!< Mismatch on tamper pin 0. */ +#define LDD_DRY_TAMPER_PIN_1 0x00020000U /*!< Mismatch on tamper pin 1. */ +#define LDD_DRY_TAMPER_PIN_2 0x00040000U /*!< Mismatch on tamper pin 2. */ +#define LDD_DRY_TAMPER_PIN_3 0x00080000U /*!< Mismatch on tamper pin 3. */ +#define LDD_DRY_TAMPER_PIN_4 0x00100000U /*!< Mismatch on tamper pin 4. */ +#define LDD_DRY_TAMPER_PIN_5 0x00200000U /*!< Mismatch on tamper pin 5. */ +#define LDD_DRY_TAMPER_PIN_6 0x00400000U /*!< Mismatch on tamper pin 6. */ +#define LDD_DRY_TAMPER_PIN_7 0x00800000U /*!< Mismatch on tamper pin 7. */ + +#define LDD_DRY_SECURE_KEY_WORD_0 0x01U /*!< Secure key word 0 mask */ +#define LDD_DRY_SECURE_KEY_WORD_1 0x02U /*!< Secure key word 1 mask */ +#define LDD_DRY_SECURE_KEY_WORD_2 0x04U /*!< Secure key word 2 mask */ +#define LDD_DRY_SECURE_KEY_WORD_3 0x08U /*!< Secure key word 3 mask */ +#define LDD_DRY_SECURE_KEY_WORD_4 0x10U /*!< Secure key word 4 mask */ +#define LDD_DRY_SECURE_KEY_WORD_5 0x20U /*!< Secure key word 5 mask */ +#define LDD_DRY_SECURE_KEY_WORD_6 0x40U /*!< Secure key word 6 mask */ +#define LDD_DRY_SECURE_KEY_WORD_7 0x80U /*!< Secure key word 7 mask */ + +/* +** =================================================================== +** NFC device types and constants +** =================================================================== +*/ + +/* Events' masks */ +#define LDD_NFC_ON_CMD_ERROR 0x01U /*!< OnCmdError event mask */ +#define LDD_NFC_ON_CMD_DONE 0x02U /*!< OnCmdDone event mask */ + +/* Pins' masks */ +#define LDD_NFC_CE0_PIN 0x01U /*!< CE0 pin mask */ +#define LDD_NFC_RB0_PIN 0x02U /*!< RB0 pin mask */ +#define LDD_NFC_CE1_PIN 0x04U /*!< CE1 pin mask */ +#define LDD_NFC_RB1_PIN 0x08U /*!< RB1 pin mask */ +#define LDD_NFC_CE2_PIN 0x10U /*!< CE2 pin mask */ +#define LDD_NFC_RB2_PIN 0x20U /*!< RB2 pin mask */ +#define LDD_NFC_CE3_PIN 0x40U /*!< CE3 pin mask */ +#define LDD_NFC_RB3_PIN 0x80U /*!< RB3 pin mask */ +#define LDD_NFC_ALE_PIN 0x0100U /*!< ALE pin mask */ +#define LDD_NFC_CLE_PIN 0x0200U /*!< CLE pin mask */ +#define LDD_NFC_RE_PIN 0x0400U /*!< RE pin mask */ +#define LDD_NFC_WE_PIN 0x0800U /*!< WE pin mask */ +#define LDD_NFC_D0_PIN 0x00010000U /*!< D0 pin mask */ +#define LDD_NFC_D1_PIN 0x00020000U /*!< D1 pin mask */ +#define LDD_NFC_D2_PIN 0x00040000U /*!< D2 pin mask */ +#define LDD_NFC_D3_PIN 0x00080000U /*!< D3 pin mask */ +#define LDD_NFC_D4_PIN 0x00100000U /*!< D4 pin mask */ +#define LDD_NFC_D5_PIN 0x00200000U /*!< D5 pin mask */ +#define LDD_NFC_D6_PIN 0x00400000U /*!< D6 pin mask */ +#define LDD_NFC_D7_PIN 0x00800000U /*!< D7 pin mask */ +#define LDD_NFC_D8_PIN 0x01000000U /*!< D8 pin mask */ +#define LDD_NFC_D9_PIN 0x02000000U /*!< D9 pin mask */ +#define LDD_NFC_D10_PIN 0x04000000U /*!< D10 pin mask */ +#define LDD_NFC_D11_PIN 0x08000000U /*!< D11 pin mask */ +#define LDD_NFC_D12_PIN 0x10000000U /*!< D12 pin mask */ +#define LDD_NFC_D13_PIN 0x20000000U /*!< D13 pin mask */ +#define LDD_NFC_D14_PIN 0x40000000U /*!< D14 pin mask */ +#define LDD_NFC_D15_PIN 0x80000000U /*!< D15 pin mask */ + +typedef uint32 LDD_NFC_TTargetID; /*!< NFC target ID type */ + +/*! NCF command codes */ +typedef enum { + LDD_NFC_CMD_NONE = 0x00U, /* No command */ + LDD_NFC_CMD_RESET = 0x01U, /* Reset command */ + LDD_NFC_CMD_ERASE = 0x02U, /* Erase command */ + LDD_NFC_CMD_READ_ID = 0x03U, /* Read ID command */ + LDD_NFC_CMD_READ_PAGES = 0x04U, /* Read pages command */ + LDD_NFC_CMD_WRITE_PAGES = 0x05U, /* Write pages command */ + LDD_NFC_CMD_ERASE_BLOCKS = 0x06U, /* Erase page command */ + LDD_NFC_CMD_READ_RAW_PAGE = 0x07U, /* Read raw page command */ + LDD_NFC_CMD_WRITE_RAW_PAGE = 0x08U /* Write raw page command */ +} LDD_NFC_TeCmd; + +/* +** =================================================================== +** LCDC device types and constants +** =================================================================== +*/ + +#define LDD_LCDC_ON_ERROR 0x01U /*!< OnError event mask */ +#define LDD_LCDC_ON_START_OF_FRAME 0x02U /*!< OnStartOfFrame event mask */ +#define LDD_LCDC_ON_END_OF_FRAME 0x04U /*!< OnEndOfFrame event mask */ + +#define LDD_LCDC_NO_ERR 0x00U /*!< No error */ +#define LDD_LCDC_PLANE_0_UNDERRUN_ERR 0x01U /*!< Plane 0 underrurn error */ +#define LDD_LCDC_PLANE_1_UNDERRUN_ERR 0x02U /*!< Plane 1 underrurn error */ + +#define LDD_LCDC_REVERSED_VERTICAL_SCAN 0x8000U /*!< Enable reversed vertical scan (flip along x-axis) */ + +/*! Bitmap description */ +typedef struct { + LDD_TData *Address; /*!< Bitmap starting address */ + uint16 Width; /*!< Bitmap width */ + uint16 Height; /*!< Bitmap height */ + uint16 Format; /*!< Bitmap format */ +} LDD_LCDC_TBitmap; + +/*! Window description */ +typedef struct { + uint16 X; /*!< Window position in bitmap - X */ + uint16 Y; /*!< Window position in bitmap - Y */ + uint16 Width; /*!< Window width */ + uint16 Height; /*!< Window height */ +} LDD_LCDC_TWindow; + +/*! Cursor type */ +typedef enum { + LDD_LCDC_DISABLED = 0, /*!< Cursor disabled */ + LDD_LCDC_ALWAYS_1, /*!< Cursor 1''s, monochrome display only. */ + LDD_LCDC_ALWAYS_0, /*!< Cursor 0''s, monochrome display only. */ + LDD_LCDC_COLOR, /*!< Defined cursor color, color display only. */ + LDD_LCDC_INVERTED, /*!< Inverted background, monochrome display only. */ + LDD_LCDC_INVERTED_COLOR, /*!< Inverted cursor color, color display only. */ + LDD_LCDC_AND, /*!< Cursor color AND backgroun, color display only. */ + LDD_LCDC_OR, /*!< Cursor color OR backgroun, color display only. */ + LDD_LCDC_XOR +} LDD_LCDC_CursorOperation; + +/*! Plane identification */ +typedef enum { + LDD_LCDC_PLANE_COMMON, /*!< Common for all planes */ + LDD_LCDC_PLANE_0, /*!< Plane (layer) 0 */ + LDD_LCDC_PLANE_1 /*!< Plane (layer) 1 */ +} LDD_LCDC_TPlaneID; + + +/* +** =================================================================== +** Interrupt vector constants +** =================================================================== +*/ +#define LDD_ivIndex_INT_Initial_Stack_Pointer 0x00u +#define LDD_ivIndex_INT_Initial_Program_Counter 0x01u +#define LDD_ivIndex_INT_NMI 0x02u +#define LDD_ivIndex_INT_Hard_Fault 0x03u +#define LDD_ivIndex_INT_Mem_Manage_Fault 0x04u +#define LDD_ivIndex_INT_Bus_Fault 0x05u +#define LDD_ivIndex_INT_Usage_Fault 0x06u +#define LDD_ivIndex_INT_Reserved7 0x07u +#define LDD_ivIndex_INT_Reserved8 0x08u +#define LDD_ivIndex_INT_Reserved9 0x09u +#define LDD_ivIndex_INT_Reserved10 0x0Au +#define LDD_ivIndex_INT_SVCall 0x0Bu +#define LDD_ivIndex_INT_DebugMonitor 0x0Cu +#define LDD_ivIndex_INT_Reserved13 0x0Du +#define LDD_ivIndex_INT_PendableSrvReq 0x0Eu +#define LDD_ivIndex_INT_SysTick 0x0Fu +#define LDD_ivIndex_INT_DMA0 0x10u +#define LDD_ivIndex_INT_DMA1 0x11u +#define LDD_ivIndex_INT_DMA2 0x12u +#define LDD_ivIndex_INT_DMA3 0x13u +#define LDD_ivIndex_INT_DMA4 0x14u +#define LDD_ivIndex_INT_DMA5 0x15u +#define LDD_ivIndex_INT_DMA6 0x16u +#define LDD_ivIndex_INT_DMA7 0x17u +#define LDD_ivIndex_INT_DMA8 0x18u +#define LDD_ivIndex_INT_DMA9 0x19u +#define LDD_ivIndex_INT_DMA10 0x1Au +#define LDD_ivIndex_INT_DMA11 0x1Bu +#define LDD_ivIndex_INT_DMA12 0x1Cu +#define LDD_ivIndex_INT_DMA13 0x1Du +#define LDD_ivIndex_INT_DMA14 0x1Eu +#define LDD_ivIndex_INT_DMA15 0x1Fu +#define LDD_ivIndex_INT_DMA_Error 0x20u +#define LDD_ivIndex_INT_MCM 0x21u +#define LDD_ivIndex_INT_FTFL 0x22u +#define LDD_ivIndex_INT_Read_Collision 0x23u +#define LDD_ivIndex_INT_LVD_LVW 0x24u +#define LDD_ivIndex_INT_LLW 0x25u +#define LDD_ivIndex_INT_Watchdog 0x26u +#define LDD_ivIndex_INT_Reserved39 0x27u +#define LDD_ivIndex_INT_I2C0 0x28u +#define LDD_ivIndex_INT_I2C1 0x29u +#define LDD_ivIndex_INT_SPI0 0x2Au +#define LDD_ivIndex_INT_SPI1 0x2Bu +#define LDD_ivIndex_INT_SPI2 0x2Cu +#define LDD_ivIndex_INT_CAN0_ORed_Message_buffer 0x2Du +#define LDD_ivIndex_INT_CAN0_Bus_Off 0x2Eu +#define LDD_ivIndex_INT_CAN0_Error 0x2Fu +#define LDD_ivIndex_INT_CAN0_Tx_Warning 0x30u +#define LDD_ivIndex_INT_CAN0_Rx_Warning 0x31u +#define LDD_ivIndex_INT_CAN0_Wake_Up 0x32u +#define LDD_ivIndex_INT_I2S0_Tx 0x33u +#define LDD_ivIndex_INT_I2S0_Rx 0x34u +#define LDD_ivIndex_INT_CAN1_ORed_Message_buffer 0x35u +#define LDD_ivIndex_INT_CAN1_Bus_Off 0x36u +#define LDD_ivIndex_INT_CAN1_Error 0x37u +#define LDD_ivIndex_INT_CAN1_Tx_Warning 0x38u +#define LDD_ivIndex_INT_CAN1_Rx_Warning 0x39u +#define LDD_ivIndex_INT_CAN1_Wake_Up 0x3Au +#define LDD_ivIndex_INT_Reserved59 0x3Bu +#define LDD_ivIndex_INT_UART0_LON 0x3Cu +#define LDD_ivIndex_INT_UART0_RX_TX 0x3Du +#define LDD_ivIndex_INT_UART0_ERR 0x3Eu +#define LDD_ivIndex_INT_UART1_RX_TX 0x3Fu +#define LDD_ivIndex_INT_UART1_ERR 0x40u +#define LDD_ivIndex_INT_UART2_RX_TX 0x41u +#define LDD_ivIndex_INT_UART2_ERR 0x42u +#define LDD_ivIndex_INT_UART3_RX_TX 0x43u +#define LDD_ivIndex_INT_UART3_ERR 0x44u +#define LDD_ivIndex_INT_UART4_RX_TX 0x45u +#define LDD_ivIndex_INT_UART4_ERR 0x46u +#define LDD_ivIndex_INT_Reserved71 0x47u +#define LDD_ivIndex_INT_Reserved72 0x48u +#define LDD_ivIndex_INT_ADC0 0x49u +#define LDD_ivIndex_INT_ADC1 0x4Au +#define LDD_ivIndex_INT_CMP0 0x4Bu +#define LDD_ivIndex_INT_CMP1 0x4Cu +#define LDD_ivIndex_INT_CMP2 0x4Du +#define LDD_ivIndex_INT_FTM0 0x4Eu +#define LDD_ivIndex_INT_FTM1 0x4Fu +#define LDD_ivIndex_INT_FTM2 0x50u +#define LDD_ivIndex_INT_CMT 0x51u +#define LDD_ivIndex_INT_RTC 0x52u +#define LDD_ivIndex_INT_RTC_Seconds 0x53u +#define LDD_ivIndex_INT_PIT0 0x54u +#define LDD_ivIndex_INT_PIT1 0x55u +#define LDD_ivIndex_INT_PIT2 0x56u +#define LDD_ivIndex_INT_PIT3 0x57u +#define LDD_ivIndex_INT_PDB0 0x58u +#define LDD_ivIndex_INT_USB0 0x59u +#define LDD_ivIndex_INT_USBDCD 0x5Au +#define LDD_ivIndex_INT_Reserved91 0x5Bu +#define LDD_ivIndex_INT_Reserved92 0x5Cu +#define LDD_ivIndex_INT_Reserved93 0x5Du +#define LDD_ivIndex_INT_Reserved94 0x5Eu +#define LDD_ivIndex_INT_Reserved95 0x5Fu +#define LDD_ivIndex_INT_SDHC 0x60u +#define LDD_ivIndex_INT_DAC0 0x61u +#define LDD_ivIndex_INT_Reserved98 0x62u +#define LDD_ivIndex_INT_TSI0 0x63u +#define LDD_ivIndex_INT_MCG 0x64u +#define LDD_ivIndex_INT_LPTimer 0x65u +#define LDD_ivIndex_INT_Reserved102 0x66u +#define LDD_ivIndex_INT_PORTA 0x67u +#define LDD_ivIndex_INT_PORTB 0x68u +#define LDD_ivIndex_INT_PORTC 0x69u +#define LDD_ivIndex_INT_PORTD 0x6Au +#define LDD_ivIndex_INT_PORTE 0x6Bu +#define LDD_ivIndex_INT_Reserved108 0x6Cu +#define LDD_ivIndex_INT_Reserved109 0x6Du +#define LDD_ivIndex_INT_SWI 0x6Eu +#define LDD_ivIndex_INT_Reserved111 0x6Fu +#define LDD_ivIndex_INT_Reserved112 0x70u +#define LDD_ivIndex_INT_Reserved113 0x71u +#define LDD_ivIndex_INT_Reserved114 0x72u +#define LDD_ivIndex_INT_Reserved115 0x73u +#define LDD_ivIndex_INT_Reserved116 0x74u +#define LDD_ivIndex_INT_Reserved117 0x75u +#define LDD_ivIndex_INT_Reserved118 0x76u +#define LDD_ivIndex_INT_Reserved119 0x77u + +#endif /* __PE_Types_H */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld new file mode 100644 index 0000000..dabf117 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/ProcessorExpert.ld @@ -0,0 +1,223 @@ +/* ################################################################### */ +/*## +/*## This component module is generated by Processor Expert. Do not modify it. */ +/*## */ +/*## Filename : ProcessorExpert.ld */ +/*## */ +/*## Project : Landungsbruecke_KDS_v2.0.0 */ +/*## */ +/*## Processor : MK20DN512VLL10 */ +/*## */ +/*## Compiler : GNU C Compiler */ +/*## */ +/*## Date/Time : 2015-01-09, 16:27, # CodeGen: 0 */ +/*## */ +/*## Abstract : */ +/*## */ +/*## This file is used by the linker. It describes files to be linked, */ +/*## memory ranges, stack size, etc. For detailed description about linker */ +/*## command files see compiler documentation. This file is generated by default. */ +/*## You can switch off generation by setting the property "Generate linker file = no" */ +/*## in the "Build options" tab of the CPU component and then modify this file as needed. */ +/*## +/*## */ +/*## ###################################################################*/ + + +/* Entry Point */ +ENTRY(__thumb_startup) + +/* Highest address of the user mode stack */ +_estack = 0x20000000; /* end of m_data */ +__SP_INIT = _estack; + +/* Generate a link error if heap and stack don't fit into RAM */ +__heap_size = 0x00; /* required amount of heap */ +__stack_size = 0x0400; /* required amount of stack */ + +MEMORY { + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000001E0 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_20000000 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + m_cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into INTERNAL_FLASH */ + .interrupts : + { + __vector_table = .; + . = ALIGN(4); + KEEP(*(.vectortable)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .cfmprotect : + { + . = ALIGN(4); + KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_cfmprotrom + + /* The program code and other data goes into INTERNAL_FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + + _etext = .; /* define a global symbols at end of code */ + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + + ___ROM_AT = .; + } > m_text + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT(___ROM_AT) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + + _edata = .; /* define a global symbol at data end */ + } > m_data + + ___data_size = _edata - _sdata; + ___m_data_20000000_ROMStart = ___ROM_AT + SIZEOF(.data); + .m_data_20000000 : AT(___m_data_20000000_ROMStart) + { + . = ALIGN(4); + ___m_data_20000000_RAMStart = .; + *(.m_data_20000000) /* This is an User defined section */ + ___m_data_20000000_RAMEnd = .; + . = ALIGN(4); + } > m_data_20000000 + ___m_data_20000000_ROMSize = ___m_data_20000000_RAMEnd - ___m_data_20000000_RAMStart; + + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + __START_BSS = .; + PROVIDE ( __bss_start__ = __START_BSS ); + + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + __END_BSS = .; + PROVIDE ( __bss_end__ = __END_BSS ); + } > m_data + + _romp_at = ___ROM_AT + SIZEOF(.data) +SIZEOF(.m_data_20000000); + .romp : AT(_romp_at) + { + __S_romp = _romp_at; + LONG(___ROM_AT); + LONG(_sdata); + LONG(___data_size); + LONG(___m_data_20000000_ROMStart); + LONG(___m_data_20000000_RAMStart); + LONG(___m_data_20000000_ROMSize); + LONG(0); + LONG(0); + LONG(0); + } > m_data + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + __heap_addr = .; + __HeapBase = .; + . = . + __heap_size; + __HeapLimit = .; + . = . + __stack_size; + . = ALIGN(4); + } > m_data + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c new file mode 100644 index 0000000..862de15 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.c @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Rx1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Rx1 +** Buffer Size : 1 +** Contents : +** Clear - void Rx1_Clear(void); +** Put - byte Rx1_Put(Rx1_ElementType elem); +** Get - byte Rx1_Get(Rx1_ElementType *elemP); +** NofElements - Rx1_BufSizeType Rx1_NofElements(void); +** NofFreeElements - Rx1_BufSizeType Rx1_NofFreeElements(void); +** Init - void Rx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Rx1.c +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Rx1_module Rx1 module documentation +** @{ +*/ + +/* MODULE Rx1. */ + +#include "Rx1.h" + +#if Rx1_IS_REENTRANT + #define Rx1_DEFINE_CRITICAL() CS1_CriticalVariable() + #define Rx1_ENTER_CRITICAL() CS1_EnterCritical() + #define Rx1_EXIT_CRITICAL() CS1_ExitCritical() +#else + #define Rx1_DEFINE_CRITICAL() /* nothing */ + #define Rx1_ENTER_CRITICAL() /* nothing */ + #define Rx1_EXIT_CRITICAL() /* nothing */ +#endif +static Rx1_ElementType Rx1_buffer[Rx1_BUF_SIZE]; /* ring buffer */ +static Rx1_BufSizeType Rx1_inIdx; /* input index */ +static Rx1_BufSizeType Rx1_outIdx; /* output index */ +static Rx1_BufSizeType Rx1_inSize; /* size data in buffer */ +/* +** =================================================================== +** Method : Rx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Rx1_Put(Rx1_ElementType elem) +{ + byte res = ERR_OK; + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + if(Rx1_inSize==Rx1_BUF_SIZE) { + res = ERR_TXFULL; + } else { + Rx1_buffer[Rx1_inIdx] = elem; + Rx1_inSize++; + Rx1_inIdx++; + if(Rx1_inIdx==Rx1_BUF_SIZE) { + Rx1_inIdx = 0; + } + } + Rx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Rx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Rx1_Get(Rx1_ElementType *elemP) +{ + byte res = ERR_OK; + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + if(Rx1_inSize==0) { + res = ERR_RXEMPTY; + } else { + *elemP = Rx1_buffer[Rx1_outIdx]; + Rx1_inSize--; + Rx1_outIdx++; + if(Rx1_outIdx==Rx1_BUF_SIZE) { + Rx1_outIdx = 0; + } + } + Rx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Rx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Rx1_BufSizeType Rx1_NofElements(void) +{ + return Rx1_inSize; +} + +/* +** =================================================================== +** Method : Rx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Rx1_BufSizeType Rx1_NofFreeElements(void) +{ + return (Rx1_BufSizeType)(Rx1_BUF_SIZE-Rx1_inSize); +} + +/* +** =================================================================== +** Method : Rx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Rx1_Init(void) +{ + Rx1_inIdx = 0; + Rx1_outIdx = 0; + Rx1_inSize = 0; +} + +/* +** =================================================================== +** Method : Rx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Rx1_Clear(void) +{ + Rx1_DEFINE_CRITICAL(); + + Rx1_ENTER_CRITICAL(); + Rx1_Init(); + Rx1_EXIT_CRITICAL(); +} + +/* END Rx1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h new file mode 100644 index 0000000..f39cdee --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Rx1.h @@ -0,0 +1,167 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Rx1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Rx1 +** Buffer Size : 1 +** Contents : +** Clear - void Rx1_Clear(void); +** Put - byte Rx1_Put(Rx1_ElementType elem); +** Get - byte Rx1_Get(Rx1_ElementType *elemP); +** NofElements - Rx1_BufSizeType Rx1_NofElements(void); +** NofFreeElements - Rx1_BufSizeType Rx1_NofFreeElements(void); +** Init - void Rx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Rx1.h +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Rx1_module Rx1 module documentation +** @{ +*/ + +#ifndef __Rx1_H +#define __Rx1_H + +/* MODULE Rx1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "CS1.h" + +//#include "Cpu.h" + + +#define Rx1_BUF_SIZE 64 /* number of elements in the buffer */ +#define Rx1_ELEM_SIZE 1 /* size of a single element in bytes */ + #define Rx1_IS_REENTRANT 0 /* 0: Critical section NOT used for accessing shared data, 1 otherwise */ +#if Rx1_ELEM_SIZE==1 + typedef uint8 Rx1_ElementType; /* type of single element */ +#elif Rx1_ELEM_SIZE==2 + typedef uint16 Rx1_ElementType; /* type of single element */ +#elif Rx1_ELEM_SIZE==4 + typedef uint32 Rx1_ElementType; /* type of single element */ +#else + #error "illegal element type size in properties" +#endif +#if Rx1_BUF_SIZE<=256 + typedef uint8 Rx1_BufSizeType; /* up to 256 elements (index 0x00..0xFF) */ +#else + typedef uint16 Rx1_BufSizeType; /* more than 256 elements, up to 2^16 */ +#endif + +byte Rx1_Put(Rx1_ElementType elem); +/* +** =================================================================== +** Method : Rx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte Rx1_Get(Rx1_ElementType *elemP); +/* +** =================================================================== +** Method : Rx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ + +Rx1_BufSizeType Rx1_NofElements(void); +/* +** =================================================================== +** Method : Rx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Rx1_Init(void); +/* +** =================================================================== +** Method : Rx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +Rx1_BufSizeType Rx1_NofFreeElements(void); +/* +** =================================================================== +** Method : Rx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Rx1_Clear(void); +/* +** =================================================================== +** Method : Rx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Rx1. */ + +#endif +/* ifndef __Rx1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c new file mode 100644 index 0000000..b4ba188 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.c @@ -0,0 +1,202 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Tx1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Tx1 +** Buffer Size : 1 +** Contents : +** Clear - void Tx1_Clear(void); +** Put - byte Tx1_Put(Tx1_ElementType elem); +** Get - byte Tx1_Get(Tx1_ElementType *elemP); +** NofElements - Tx1_BufSizeType Tx1_NofElements(void); +** NofFreeElements - Tx1_BufSizeType Tx1_NofFreeElements(void); +** Init - void Tx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Tx1.c +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Tx1_module Tx1 module documentation +** @{ +*/ + +/* MODULE Tx1. */ + +#include "Tx1.h" + +#if Tx1_IS_REENTRANT + #define Tx1_DEFINE_CRITICAL() CS1_CriticalVariable() + #define Tx1_ENTER_CRITICAL() CS1_EnterCritical() + #define Tx1_EXIT_CRITICAL() CS1_ExitCritical() +#else + #define Tx1_DEFINE_CRITICAL() /* nothing */ + #define Tx1_ENTER_CRITICAL() /* nothing */ + #define Tx1_EXIT_CRITICAL() /* nothing */ +#endif +static Tx1_ElementType Tx1_buffer[Tx1_BUF_SIZE]; /* ring buffer */ +static Tx1_BufSizeType Tx1_inIdx; /* input index */ +static Tx1_BufSizeType Tx1_outIdx; /* output index */ +static Tx1_BufSizeType Tx1_inSize; /* size data in buffer */ +/* +** =================================================================== +** Method : Tx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Tx1_Put(Tx1_ElementType elem) +{ + byte res = ERR_OK; + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + if(Tx1_inSize==Tx1_BUF_SIZE) { + res = ERR_TXFULL; + } else { + Tx1_buffer[Tx1_inIdx] = elem; + Tx1_inSize++; + Tx1_inIdx++; + if(Tx1_inIdx==Tx1_BUF_SIZE) { + Tx1_inIdx = 0; + } + } + Tx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Tx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ +byte Tx1_Get(Tx1_ElementType *elemP) +{ + byte res = ERR_OK; + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + if(Tx1_inSize==0) { + res = ERR_RXEMPTY; + } else { + *elemP = Tx1_buffer[Tx1_outIdx]; + Tx1_inSize--; + Tx1_outIdx++; + if(Tx1_outIdx==Tx1_BUF_SIZE) { + Tx1_outIdx = 0; + } + } + Tx1_EXIT_CRITICAL(); + return res; +} + +/* +** =================================================================== +** Method : Tx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Tx1_BufSizeType Tx1_NofElements(void) +{ + return Tx1_inSize; +} + +/* +** =================================================================== +** Method : Tx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ +Tx1_BufSizeType Tx1_NofFreeElements(void) +{ + return (Tx1_BufSizeType)(Tx1_BUF_SIZE-Tx1_inSize); +} + +/* +** =================================================================== +** Method : Tx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Tx1_Init(void) +{ + Tx1_inIdx = 0; + Tx1_outIdx = 0; + Tx1_inSize = 0; +} + +/* +** =================================================================== +** Method : Tx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void Tx1_Clear(void) +{ + Tx1_DEFINE_CRITICAL(); + + Tx1_ENTER_CRITICAL(); + Tx1_Init(); + Tx1_EXIT_CRITICAL(); +} + +/* END Tx1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h new file mode 100644 index 0000000..a5a2a0e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/Tx1.h @@ -0,0 +1,167 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Tx1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : RingBuffer +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a ring buffer for different integer data type. +** Settings : +** Component name : Tx1 +** Buffer Size : 1 +** Contents : +** Clear - void Tx1_Clear(void); +** Put - byte Tx1_Put(Tx1_ElementType elem); +** Get - byte Tx1_Get(Tx1_ElementType *elemP); +** NofElements - Tx1_BufSizeType Tx1_NofElements(void); +** NofFreeElements - Tx1_BufSizeType Tx1_NofFreeElements(void); +** Init - void Tx1_Init(void); +** +** License : Open Source (LGPL) +** Copyright : (c) Copyright Erich Styger, 2014, all rights reserved. +** Web: http://www.mcuoneclipse.com +** This an open source software of an embedded component for Processor Expert. +** This is a free software and is opened for education, research and commercial developments under license policy of following terms: +** * This is a free software and there is NO WARRANTY. +** * No restriction on use. You can use, modify and redistribute it for personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +** * Redistributions of source code must retain the above copyright notice. +** ###################################################################*/ +/*! +** @file Tx1.h +** @version 01.00 +** @brief +** This component implements a ring buffer for different integer data type. +*/ +/*! +** @addtogroup Tx1_module Tx1 module documentation +** @{ +*/ + +#ifndef __Tx1_H +#define __Tx1_H + +/* MODULE Tx1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "CS1.h" + +//#include "Cpu.h" + + +#define Tx1_BUF_SIZE 64 /* number of elements in the buffer */ +#define Tx1_ELEM_SIZE 1 /* size of a single element in bytes */ + #define Tx1_IS_REENTRANT 0 /* 0: Critical section NOT used for accessing shared data, 1 otherwise */ +#if Tx1_ELEM_SIZE==1 + typedef uint8 Tx1_ElementType; /* type of single element */ +#elif Tx1_ELEM_SIZE==2 + typedef uint16 Tx1_ElementType; /* type of single element */ +#elif Tx1_ELEM_SIZE==4 + typedef uint32 Tx1_ElementType; /* type of single element */ +#else + #error "illegal element type size in properties" +#endif +#if Tx1_BUF_SIZE<=256 + typedef uint8 Tx1_BufSizeType; /* up to 256 elements (index 0x00..0xFF) */ +#else + typedef uint16 Tx1_BufSizeType; /* more than 256 elements, up to 2^16 */ +#endif + +byte Tx1_Put(Tx1_ElementType elem); +/* +** =================================================================== +** Method : Tx1_Put (component RingBuffer) +** Description : +** Puts a new element into the buffer +** Parameters : +** NAME - DESCRIPTION +** elem - New element to be put into the buffer +** Returns : +** --- - Error code +** =================================================================== +*/ + +byte Tx1_Get(Tx1_ElementType *elemP); +/* +** =================================================================== +** Method : Tx1_Get (component RingBuffer) +** Description : +** Removes an element from the buffer +** Parameters : +** NAME - DESCRIPTION +** * elemP - Pointer to where to store the received +** element +** Returns : +** --- - Error code +** =================================================================== +*/ + +Tx1_BufSizeType Tx1_NofElements(void); +/* +** =================================================================== +** Method : Tx1_NofElements (component RingBuffer) +** Description : +** Returns the actual number of elements in the buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Tx1_Init(void); +/* +** =================================================================== +** Method : Tx1_Init (component RingBuffer) +** Description : +** Initializes the data structure +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +Tx1_BufSizeType Tx1_NofFreeElements(void); +/* +** =================================================================== +** Method : Tx1_NofFreeElements (component RingBuffer) +** Description : +** Returns the actual number of free elements/space in the +** buffer. +** Parameters : None +** Returns : +** --- - Number of elements in the buffer. +** =================================================================== +*/ + +void Tx1_Clear(void); +/* +** =================================================================== +** Method : Tx1_Clear (component RingBuffer) +** Description : +** Clear (empty) the ring buffer. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Tx1. */ + +#endif +/* ifndef __Tx1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c new file mode 100644 index 0000000..7c61997 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.c @@ -0,0 +1,396 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB0.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : Init_USB_OTG +** Version : Component 01.004, Driver 01.04, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +** Settings : +** Component name : USB0 +** Device : USB0 +** Settings : +** Clock gate : Enabled +** Clock settings : +** Clock divider : +** Clock divider source : PLL/FLL clock +** Clock divider input frequency : 96 MHz +** Clock divider fraction : multiply by 1 +** Clock divider divisor : divide by 2 +** Module clock source : Clock divider output +** Module clock frequency : 48 MHz +** Pull-up/pull-down settings : +** Weak pulldowns : Enabled +** Pull-up/pull-down control : Mode dependent +** D+ pull-up : Disabled +** D+ pull-down : Disabled +** D- pull-down : Disabled +** D+ pull-up for non-OTG mode : Disabled +** Endpoints : +** EP0 : Disabled +** Direct low speed : Disabled +** Retry : Enabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP1 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP2 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP3 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP4 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP5 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP6 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP7 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP8 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP9 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP10 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP11 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP12 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP13 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP14 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP15 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** Buffer descriptor table : +** External object declaration : extern uint8 g_Mem[]; +** Address : ((uint32)&g_Mem[0]) +** SOF threshold : 0 +** Pins : +** Alternate clock source : Disabled +** SOF output : Disabled +** Data plus : Enabled +** Pin : USB0_DP +** Pin signal : +** Data minus : Enabled +** Pin : USB0_DM +** Pin signal : +** Interrupts : +** USB : +** Interrupt : INT_USB0 +** Interrupt request : Disabled +** Interrupt priority : 0 (Highest) +** ISR Name : USB_ISR +** Stall : Enabled +** Attach : Enabled +** Resume : Enabled +** Sleep : Enabled +** Token OK : Enabled +** Start of frame : Enabled +** Error interrupt : Enabled +** USB reset : Enabled +** Asynchronous Resume interrupt : Enabled +** Error interrupts : +** Bit stuff error : Disabled +** DMA error : Disabled +** Bus turnaround timeout : Disabled +** Data length error : Disabled +** CRC16 error : Disabled +** CRC5 or EOF : Disabled +** PID error : Disabled +** OTG interrupts : +** ID pin changed : Disabled +** 1 ms interrupt : Disabled +** Line stage change : Disabled +** Session valid : Disabled +** "B" session end : Disabled +** "A" bus valid : Disabled +** Initialization : +** Mode : Device +** USB transceiver suspend state : Enabled +** Call Init method : yes +** Contents : +** Init - void USB0_Init(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file USB0.c +** @version 01.04 +** @brief +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +*/ +/*! +** @addtogroup USB0_module USB0 module documentation +** @{ +*/ + +/* MODULE USB0. */ + +#include "USB0.h" + /* Including shared modules, which are used in the whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "hal/derivative.h" + + +/* +** =================================================================== +** Method : USB0_Init (component Init_USB_OTG) +** Description : +** This method initializes registers of the USB_OTG module +** according to the Peripheral Initialization settings. +** Call this method in user code to initialize the module. By +** default, the method is called by PE automatically; see "Call +** Init method" property of the component for more details. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +extern uint8 g_Mem[]; +void USB0_Init(void) +{ + /* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ + SIM_CLKDIV2 = (uint32)((SIM_CLKDIV2 & (uint32)~(uint32)( + SIM_CLKDIV2_USBDIV(0x06) | + SIM_CLKDIV2_USBFRAC_MASK + )) | (uint32)( + SIM_CLKDIV2_USBDIV(0x01) + )); + /* SIM_SOPT2: USBSRC=1 */ + SIM_SOPT2 |= SIM_SOPT2_USBSRC_MASK; + /* SIM_SCGC4: USBOTG=1 */ + SIM_SCGC4 |= SIM_SCGC4_USBOTG_MASK; + /* USB0_CTL: ODDRST=1 */ + USB0_CTL |= USB_CTL_ODDRST_MASK; + /* USB0_USBCTRL: SUSP=1,PDE=1,??=0,??=0,??=0,??=0,??=0,??=0 */ + USB0_USBCTRL = (USB_USBCTRL_SUSP_MASK | USB_USBCTRL_PDE_MASK); + /* USB0_OTGISTAT: IDCHG=1,ONEMSEC=1,LINE_STATE_CHG=1,??=1,SESSVLDCHG=1,B_SESS_CHG=1,??=1,AVBUSCHG=1 */ + USB0_OTGISTAT = USB_OTGISTAT_IDCHG_MASK | + USB_OTGISTAT_ONEMSEC_MASK | + USB_OTGISTAT_LINE_STATE_CHG_MASK | + USB_OTGISTAT_SESSVLDCHG_MASK | + USB_OTGISTAT_B_SESS_CHG_MASK | + USB_OTGISTAT_AVBUSCHG_MASK | + 0x12U; + /* USB0_ISTAT: STALL=1,ATTACH=1,RESUME=1,SLEEP=1,TOKDNE=1,SOFTOK=1,ERROR=1,USBRST=1 */ + USB0_ISTAT = USB_ISTAT_STALL_MASK | + USB_ISTAT_ATTACH_MASK | + USB_ISTAT_RESUME_MASK | + USB_ISTAT_SLEEP_MASK | + USB_ISTAT_TOKDNE_MASK | + USB_ISTAT_SOFTOK_MASK | + USB_ISTAT_ERROR_MASK | + USB_ISTAT_USBRST_MASK; + /* USB0_ERRSTAT: BTSERR=1,??=1,DMAERR=1,BTOERR=1,DFN8=1,CRC16=1,CRC5EOF=1,PIDERR=1 */ + USB0_ERRSTAT = USB_ERRSTAT_BTSERR_MASK | + USB_ERRSTAT_DMAERR_MASK | + USB_ERRSTAT_BTOERR_MASK | + USB_ERRSTAT_DFN8_MASK | + USB_ERRSTAT_CRC16_MASK | + USB_ERRSTAT_CRC5EOF_MASK | + USB_ERRSTAT_PIDERR_MASK | + 0x40U; + /* USB0_INTEN: STALLEN=1,ATTACHEN=1,RESUMEEN=1,SLEEPEN=1,TOKDNEEN=1,SOFTOKEN=1,ERROREN=1,USBRSTEN=1 */ + USB0_INTEN = USB_INTEN_STALLEN_MASK | + USB_INTEN_ATTACHEN_MASK | + USB_INTEN_RESUMEEN_MASK | + USB_INTEN_SLEEPEN_MASK | + USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SOFTOKEN_MASK | + USB_INTEN_ERROREN_MASK | + USB_INTEN_USBRSTEN_MASK; + /* USB0_ERREN: BTSERREN=0,??=0,DMAERREN=0,BTOERREN=0,DFN8EN=0,CRC16EN=0,CRC5EOFEN=0,PIDERREN=0 */ + USB0_ERREN = 0x00U; + /* USB0_USBTRC0: USBRESET=0,??=1,USBRESMEN=1,??=0,??=0,??=0,SYNC_DET=0,USB_RESUME_INT=0 */ + USB0_USBTRC0 = (USB_USBTRC0_USBRESMEN_MASK | 0x40U); + /* USB0_OTGICR: IDEN=0,ONEMSECEN=0,LINESTATEEN=0,??=0,SESSVLDEN=0,BSESSEN=0,??=0,AVBUSEN=0 */ + USB0_OTGICR = 0x00U; + /* USB0_ADDR: LSEN=0,ADDR=0 */ + USB0_ADDR = USB_ADDR_ADDR(0x00); + /* USB0_ENDPT0: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT0 = 0x00U; + /* USB0_ENDPT1: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT1 = 0x00U; + /* USB0_ENDPT2: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT2 = 0x00U; + /* USB0_ENDPT3: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT3 = 0x00U; + /* USB0_ENDPT4: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT4 = 0x00U; + /* USB0_ENDPT5: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT5 = 0x00U; + /* USB0_ENDPT6: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT6 = 0x00U; + /* USB0_ENDPT7: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT7 = 0x00U; + /* USB0_ENDPT8: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT8 = 0x00U; + /* USB0_ENDPT9: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT9 = 0x00U; + /* USB0_ENDPT10: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT10 = 0x00U; + /* USB0_ENDPT11: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT11 = 0x00U; + /* USB0_ENDPT12: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT12 = 0x00U; + /* USB0_ENDPT13: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT13 = 0x00U; + /* USB0_ENDPT14: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT14 = 0x00U; + /* USB0_ENDPT15: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */ + USB0_ENDPT15 = 0x00U; + USB0_BDTPAGE1 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x08) & 0xFEU); + USB0_BDTPAGE2 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x10) & 0xFFU); + USB0_BDTPAGE3 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x18) & 0xFFU); + /* USB0_SOFTHLD: CNT=0 */ + USB0_SOFTHLD = USB_SOFTHLD_CNT(0x00); + /* USB0_OTGCTL: DPHIGH=0,??=0,DPLOW=0,DMLOW=0,??=0,OTGEN=0,??=0,??=0 */ + USB0_OTGCTL = 0x00U; + /* USB0_CONTROL: ??=0,??=0,??=0,DPPULLUPNONOTG=0,??=0,??=0,??=0,??=0 */ + USB0_CONTROL = 0x00U; + /* USB0_CTL: TXSUSPENDTOKENBUSY=0,HOSTMODEEN=0,ODDRST=0,USBENSOFEN=1 */ + USB0_CTL = (uint8)((USB0_CTL & (uint8)~(uint8)( + USB_CTL_TXSUSPENDTOKENBUSY_MASK | + USB_CTL_HOSTMODEEN_MASK | + USB_CTL_ODDRST_MASK + )) | (uint8)( + USB_CTL_USBENSOFEN_MASK + )); +} + +/* +** ################################################################### +** +** The interrupt service routine(s) must be implemented +** by user in one of the following user modules. +** +** If the "Generate ISR" option is enabled, Processor Expert generates +** ISR templates in the CPU event module. +** +** User modules: +** main.c +** Events.c +** +** ################################################################### +PE_ISR(USB_ISR) +{ +// NOTE: The routine should include actions to clear the appropriate +// interrupt flags. +// +} +*/ + + +/* END USB0. */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h new file mode 100644 index 0000000..269de05 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB0.h @@ -0,0 +1,279 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB0.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : Init_USB_OTG +** Version : Component 01.004, Driver 01.04, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +** Settings : +** Component name : USB0 +** Device : USB0 +** Settings : +** Clock gate : Enabled +** Clock settings : +** Clock divider : +** Clock divider source : PLL/FLL clock +** Clock divider input frequency : 96 MHz +** Clock divider fraction : multiply by 1 +** Clock divider divisor : divide by 2 +** Module clock source : Clock divider output +** Module clock frequency : 48 MHz +** Pull-up/pull-down settings : +** Weak pulldowns : Enabled +** Pull-up/pull-down control : Mode dependent +** D+ pull-up : Disabled +** D+ pull-down : Disabled +** D- pull-down : Disabled +** D+ pull-up for non-OTG mode : Disabled +** Endpoints : +** EP0 : Disabled +** Direct low speed : Disabled +** Retry : Enabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP1 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP2 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP3 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP4 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP5 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP6 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP7 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP8 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP9 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP10 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP11 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP12 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP13 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP14 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** EP15 : Disabled +** Setup transfers : Enabled +** Handshake : Disabled +** Rx transfer : Disabled +** Tx transfer : Disabled +** Force stall : Disabled +** Buffer descriptor table : +** External object declaration : extern uint8 g_Mem[]; +** Address : ((uint32)&g_Mem[0]) +** SOF threshold : 0 +** Pins : +** Alternate clock source : Disabled +** SOF output : Disabled +** Data plus : Enabled +** Pin : USB0_DP +** Pin signal : +** Data minus : Enabled +** Pin : USB0_DM +** Pin signal : +** Interrupts : +** USB : +** Interrupt : INT_USB0 +** Interrupt request : Disabled +** Interrupt priority : 0 (Highest) +** ISR Name : USB_ISR +** Stall : Enabled +** Attach : Enabled +** Resume : Enabled +** Sleep : Enabled +** Token OK : Enabled +** Start of frame : Enabled +** Error interrupt : Enabled +** USB reset : Enabled +** Asynchronous Resume interrupt : Enabled +** Error interrupts : +** Bit stuff error : Disabled +** DMA error : Disabled +** Bus turnaround timeout : Disabled +** Data length error : Disabled +** CRC16 error : Disabled +** CRC5 or EOF : Disabled +** PID error : Disabled +** OTG interrupts : +** ID pin changed : Disabled +** 1 ms interrupt : Disabled +** Line stage change : Disabled +** Session valid : Disabled +** "B" session end : Disabled +** "A" bus valid : Disabled +** Initialization : +** Mode : Device +** USB transceiver suspend state : Enabled +** Call Init method : yes +** Contents : +** Init - void USB0_Init(void); +** +** Copyright : 1997 - 2014 Freescale Semiconductor, Inc. +** All Rights Reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** ###################################################################*/ +/*! +** @file USB0.h +** @version 01.04 +** @brief +** This file implements the USB_OTG (USB0) module initialization +** according to the Peripheral Initialization settings, and +** defines interrupt service routines prototypes. +*/ +/*! +** @addtogroup USB0_module USB0 module documentation +** @{ +*/ + +#ifndef USB0_H_ +#define USB0_H_ + +/* MODULE USB0. */ + +/* Including shared modules, which are used in the whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +//#include "Cpu.h" + +/* Peripheral base address parameter */ +#define USB0_DEVICE USB0_BASE_PTR + + +/* +** =================================================================== +** Method : USB0_Init (component Init_USB_OTG) +** Description : +** This method initializes registers of the USB_OTG module +** according to the Peripheral Initialization settings. +** Call this method in user code to initialize the module. By +** default, the method is called by PE automatically; see "Call +** Init method" property of the component for more details. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void USB0_Init(void); +/* +** =================================================================== +** The interrupt service routine must be implemented by user in one +** of the user modules (see USB0.c file for more information). +** =================================================================== +*/ +//PE_ISR(USB_ISR); +void __attribute((interrupt)) USB_ISR(void); + + +/* END USB0. */ +#endif /* #ifndef __USB0_H_ */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c new file mode 100644 index 0000000..962305f --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.c @@ -0,0 +1,112 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB1.c +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_Stack +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a wrapper to the FSL USB Stack. +** Settings : +** Component name : USB1 +** Freescale USB Stack Version : v4.1.1 +** USB : Init_USB_OTG_VAR0 +** Device Class : CDC Device +** CDC Device : Enabled +** CDCDevice : FSL_USB_CDC_Device +** HID Keyboard Device : Disabled +** MSD Host : Disabled +** Call Init Method : yes +** Contents : +** Init - byte USB1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013-2014. +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file USB1.c +** @version 01.00 +** @brief +** This component implements a wrapper to the FSL USB Stack. +*/ +/*! +** @addtogroup USB1_module USB1 module documentation +** @{ +*/ + +/* MODULE USB1. */ + +#include "USB1.h" +#include "hal/derivative.h" /* include peripheral declarations */ + +/* +** =================================================================== +** Method : USB1_usb_int_dis (component FSL_USB_Stack) +** +** Description : +** Disables USB interrupts (if supported) +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void USB1_usb_int_dis(void) +{ + /* Kinetis K20D72 */ + NVICISER1 = (1<<9); /* Disable interrupts from USB module (Interrupt Clear-Enable Register) */ +} + +/* +** =================================================================== +** Method : USB1_usb_int_en (component FSL_USB_Stack) +** +** Description : +** Enables USB interrupts (if supported). +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ +void USB1_usb_int_en(void) +{ + /* Kinetis K20D72 */ + NVICICPR2 = (1<<9); /* Clear any pending interrupts on USB (Interrupt Clear-Pending Register) */ + NVICISER2 = (1<<9); /* Enable interrupts from USB module (Interrupt Set-Enable Register) */ +} + +/* +** =================================================================== +** Method : USB1_Init (component FSL_USB_Stack) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ +byte USB1_Init(void) +{ + byte err; + + /* Initialize the USB interface */ + err = CDC1_Init(); + if(err != ERR_OK) { + /* Error initializing USB Class */ + return ERR_FAILED; + } + USB1_usb_int_en(); + return ERR_OK; +} + +/* END USB1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h new file mode 100644 index 0000000..dea3004 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB1.h @@ -0,0 +1,132 @@ +/* ################################################################### +** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : USB1.h +** Project : Landungsbruecke_KDS_v2.0.0 +** Processor : MK20DN512VLL10 +** Component : FSL_USB_Stack +** Version : Component 01.025, Driver 01.00, CPU db: 3.00.000 +** Compiler : GNU C Compiler +** Date/Time : 2015-01-09, 16:27, # CodeGen: 0 +** Abstract : +** This component implements a wrapper to the FSL USB Stack. +** Settings : +** Component name : USB1 +** Freescale USB Stack Version : v4.1.1 +** USB : Init_USB_OTG_VAR0 +** Device Class : CDC Device +** CDC Device : Enabled +** CDCDevice : FSL_USB_CDC_Device +** HID Keyboard Device : Disabled +** MSD Host : Disabled +** Call Init Method : yes +** Contents : +** Init - byte USB1_Init(void); +** +** (c) Copyright Freescale, all rights reserved, 2013-2014. +** Ported as Processor Expert component: Erich Styger +** http: www.mcuoneclipse.com +** ###################################################################*/ +/*! +** @file USB1.h +** @version 01.00 +** @brief +** This component implements a wrapper to the FSL USB Stack. +*/ +/*! +** @addtogroup USB1_module USB1 module documentation +** @{ +*/ + +#ifndef __USB1_H +#define __USB1_H + +/* MODULE USB1. */ + +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "MK20D10.h" +/* Include inherited beans */ +#include "USB0.h" +#include "CDC1.h" +#include /* for size_t */ + +/* Interfaces/wrappers to the CDC device class, needed by FSShell: */ +#define USB1_SendString(str) CDC1_SendString(str) +#define USB1_RecvChar(chr) CDC1_GetChar(chr) +#define USB1_SendChar(chr) CDC1_SendChar(chr) +#define USB1_GetCharsInRxBuf() CDC1_GetCharsInRxBuf() + +//#include "Cpu.h" + + +#ifndef __BWUserType_USB1_TComData +#define __BWUserType_USB1_TComData + typedef byte USB1_TComData ; /* User type for communication data type. */ +#endif + +/* + DATA_BUFF_SIZE should be greater than or equal to the endpoint buffer size, + otherwise there will be data loss. For MC9S08JS16, maximum DATA_BUFF_SIZE + supported is 16 Bytes +*/ +#define USB1_DATA_BUFF_SIZE 64 /* data buffer size as specified in the properties */ + +#define USB1_USB_ERR_SEND 1 /* Error while sending */ +#define USB1_USB_ERR_BUSOFF 2 /* Bus not ready */ +#define USB1_USB_ERR_INIT 3 /* USB initialization error */ +#define USB1_USB_ERR_TX_CHAR 4 /* Error sending character */ +#define USB1_USB_ERR_TX_STRING 5 /* Error sending string */ +#define USB1_USB_ERR_CHECKED_TXFULL 6 /* Error during sending a checked block */ +#define USB1_USB_ERR_RECEIVE 7 /* Error while starting a receive transaction */ + +byte USB1_Init(void); +/* +** =================================================================== +** Method : USB1_Init (component FSL_USB_Stack) +** Description : +** Initializes the driver +** Parameters : None +** Returns : +** --- - Error code +** =================================================================== +*/ + +void USB1_usb_int_dis(void); +/* +** =================================================================== +** Method : USB1_usb_int_dis (component FSL_USB_Stack) +** +** Description : +** Disables USB interrupts (if supported) +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +void USB1_usb_int_en(void); +/* +** =================================================================== +** Method : USB1_usb_int_en (component FSL_USB_Stack) +** +** Description : +** Enables USB interrupts (if supported). +** This method is internal. It is used by Processor Expert only. +** =================================================================== +*/ + +/* END USB1. */ + +#endif +/* ifndef __USB1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.4 [05.11] +** for the Freescale Kinetis series of microcontrollers. +** +** ################################################################### +*/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h new file mode 100644 index 0000000..e2e8dbf --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/USB_Config.h @@ -0,0 +1,211 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file USB_Config.h + * + * @author B14088 + * + * @version + * + * @date Oct 31, 2010 + * + * @brief + *****************************************************************************/ + +#ifndef USB_CONFIG_H_ +#define USB_CONFIG_H_ + +/*****************************************************************************/ +/* Includes Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Typedef Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Function's Prototypes */ +/*****************************************************************************/ +/* CDC class services */ +extern void USB_Class_CDC_Service_Dic_Bulk_In (PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_Class_CDC_Service_Dic_Bulk_Out(PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_Class_CDC_Service_Cic_Notify(PTR_USB_DEV_EVENT_STRUCT event); +extern void USB_NULL_CALLBACK (PTR_USB_DEV_EVENT_STRUCT event); + +/*****************************************************************************/ +/* Defines & Macros Section */ +/*****************************************************************************/ + +#define REMOTE_WAKEUP_SUPPORT (TRUE) + +/* CDC specific configuration parameters */ +#define DATA_CLASS_SUPPORT (TRUE) +#define CIC_NOTIF_ELEM_SUPPORT (TRUE) /* Mandatory */ +#define DIC_ISOCHRONOUS_SETTING (FALSE) +#define IMPLEMENT_QUEUING (FALSE) + +/* Hardware components configuration */ +#define USB_HW_VREG_EN TRUE +#define USB_HW_PU_EN TRUE + +/* Event callbacks assignation */ +#define USB_EP0_CALLBACK USB_Control_Service + +#if DIC_ISOCHRONOUS_SETTING +#define USB_EP1_CALLBACK USB_Class_CDC_Service_Dic_Iso_In +#define USB_EP2_CALLBACK USB_Class_CDC_Service_Dic_Iso_Out +#else +#define USB_EP1_CALLBACK USB_Class_CDC_Service_Dic_Bulk_In +#define USB_EP2_CALLBACK USB_Class_CDC_Service_Dic_Bulk_Out +#endif + +#define USB_EP3_CALLBACK USB_Class_CDC_Service_Cic_Notify +#define USB_EP4_CALLBACK USB_NULL_CALLBACK +#define USB_EP5_CALLBACK USB_NULL_CALLBACK +#define USB_EP6_CALLBACK USB_NULL_CALLBACK +#define USB_EP7_CALLBACK USB_NULL_CALLBACK +#define USB_EP8_CALLBACK USB_NULL_CALLBACK +#define USB_EP9_CALLBACK USB_NULL_CALLBACK +#define USB_EP10_CALLBACK USB_NULL_CALLBACK +#define USB_EP11_CALLBACK USB_NULL_CALLBACK +#define USB_EP12_CALLBACK USB_NULL_CALLBACK +#define USB_EP13_CALLBACK USB_NULL_CALLBACK +#define USB_EP14_CALLBACK USB_NULL_CALLBACK +#define USB_EP15_CALLBACK USB_NULL_CALLBACK + +#define USB_BUS_RESET_CALLBACK USB_Reset_Service +#define USB_SUSPEND_CALLBACK USB_Suspend_Service +#define USB_SOF_CALLBACK USB_Sof_Service +#define USB_RESUME_CALLBACK USB_Resume_Service +#define USB_SLEEP_CALLBACK USB_Suspend_Service +#define USB_SPEED_DETECTION_CALLBACK USB_NULL_CALLBACK +#define USB_ERROR_CALLBACK USB_Error_Service +#define USB_STALL_CALLBACK USB_Stall_Service + +/* Endpoints configuration */ +#define USB_EP0_ENABLE TRUE +#define USB_EP0_DIR EP_CTRL +#define USB_EP0_HSHK TRUE +#define USB_EP0_SIZE 32 + +#if DIC_ISOCHRONOUS_SETTING +#define USB_EP1_ENABLE TRUE +#define USB_EP1_DIR USB_DIR_IN +#define USB_EP1_HSHK FALSE +#define USB_EP1_SIZE 64 + +#define USB_EP2_ENABLE TRUE +#define USB_EP2_DIR EP_OUT +#define USB_EP2_HSHK FALSE +#define USB_EP2_SIZE 64 +#else +#define USB_EP1_ENABLE TRUE +#define USB_EP1_DIR EP_IN +#define USB_EP1_HSHK TRUE +#define USB_EP1_SIZE 32 + +#define USB_EP2_ENABLE TRUE +#define USB_EP2_DIR EP_OUT +#define USB_EP2_HSHK TRUE +#define USB_EP2_SIZE 32 +#endif + +#define USB_EP3_ENABLE TRUE +#define USB_EP3_DIR EP_IN +#define USB_EP3_HSHK TRUE +#define USB_EP3_SIZE 32 + +#define USB_EP4_ENABLE FALSE +#define USB_EP4_DIR NA +#define USB_EP4_HSHK TRUE +#define USB_EP4_SIZE 0 + +#define USB_EP5_ENABLE FALSE +#define USB_EP5_DIR NA +#define USB_EP5_HSHK TRUE +#define USB_EP5_SIZE 0 + +#define USB_EP6_ENABLE FALSE +#define USB_EP6_DIR NA +#define USB_EP6_HSHK TRUE +#define USB_EP6_SIZE 0 + +#define USB_EP7_ENABLE FALSE +#define USB_EP7_DIR NA +#define USB_EP7_HSHK TRUE +#define USB_EP7_SIZE 0 + +#define USB_EP8_ENABLE FALSE +#define USB_EP8_DIR NA +#define USB_EP8_HSHK TRUE +#define USB_EP8_SIZE 0 + +#define USB_EP9_ENABLE FALSE +#define USB_EP9_DIR NA +#define USB_EP9_HSHK TRUE +#define USB_EP9_SIZE 0 + +#define USB_EP10_ENABLE FALSE +#define USB_EP10_DIR NA +#define USB_EP10_HSHK TRUE +#define USB_EP10_SIZE 0 + +#define USB_EP11_ENABLE FALSE +#define USB_EP11_DIR NA +#define USB_EP11_HSHK TRUE +#define USB_EP11_SIZE 0 + +#define USB_EP12_ENABLE FALSE +#define USB_EP12_DIR NA +#define USB_EP12_HSHK TRUE +#define USB_EP12_SIZE 0 + +#define USB_EP13_ENABLE FALSE +#define USB_EP13_DIR NA +#define USB_EP13_HSHK TRUE +#define USB_EP13_SIZE 0 + +#define USB_EP14_ENABLE FALSE +#define USB_EP14_DIR NA +#define USB_EP14_HSHK TRUE +#define USB_EP14_SIZE 0 + +#define USB_EP15_ENABLE FALSE +#define USB_EP15_DIR NA +#define USB_EP15_HSHK TRUE +#define USB_EP15_SIZE 0 + +/*****************************************************************************/ +/* Extern Variables Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Function Prototypes Section */ +/*****************************************************************************/ + + +/*****************************************************************************/ + +#endif /* USB_CONFIG_H_ */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h new file mode 100644 index 0000000..4512365 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/hidef.h @@ -0,0 +1,64 @@ +/******************************************************/ +/** +* @file hidef.h +* Machine/compiler dependent declarations. +*/ +/*---------------------------------------------------- + Copyright (c) Freescale DevTech + All rights reserved + Do not modify! + *****************************************************/ + +#ifndef _H_HIDEF_ +#define _H_HIDEF_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef EnableInterrupts + #ifndef DisableInterrupts + + #if defined(__CWCC__) + #pragma gcc_extensions on + + /**** Version for ColFire V1 */ + #include + #include "types.h" + + /*!< Macro to enable all interrupts. */ + #define EnableInterrupts asm ("CPSIE i") + + /*!< Macro to disable all interrupts. */ + #define DisableInterrupts asm ("CPSID i") + + #elif defined(__IAR_SYSTEMS_ICC__) + #include + + #define EnableInterrupts; __enable_interrupt() + #define DisableInterrupts __disable_interrupt() + + #elif defined (__CC_ARM) + #define EnableInterrupts __enable_irq() + #define DisableInterrupts __disable_irq() + + #elif defined (__GNUC__) + #include + #include "types.h" + + /*!< Macro to enable all interrupts. */ + #define EnableInterrupts asm ("CPSIE i") + + /*!< Macro to disable all interrupts. */ + #define DisableInterrupts asm ("CPSID i") + #endif + + #ifdef __cplusplus + } + #endif + + #endif + #endif /* #ifdef DisableInterrupts */ +#endif/* #ifdef EnableInterrupts */ +/*****************************************************/ +/* end hidef.h */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h new file mode 100644 index 0000000..f119a4b --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/types.h @@ -0,0 +1,180 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file types.h + * + * @author + * + * @version + * + * @date + * + * @brief The file contains definitions of datatypes. + * + *****************************************************************************/ + + +#ifndef _TYPES_H +#define _TYPES_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define LSB(a) ((a)._byte.byte0) +#define MSB(a) ((a)._byte.byte1) + +#define LOWER_LSB(a) ((a)._byte.byte0) +#define LOWER_MSB(a) ((a)._byte.byte1) +#define UPPER_LSB(a) ((a)._byte.byte2) +#define UPPER_MSB(a) ((a)._byte.byte3) + +#define _PTR_ * +#define _CODE_PTR_ * + +#ifndef TRUE +#define FALSE 0 +#define TRUE 1 +#endif + +#define BYTESWAP16(x) (uint_16)((((x) & 0xFF00) >> 0x8) | (((x) & 0xFF) << 0x8)) +#define BYTESWAP32(val) (uint_32)((BYTESWAP16((uint_32)(val) & (uint_32)0xFFFF) << 0x10) | \ + (BYTESWAP16((uint_32)((val) >> 0x10)))) + +#ifdef CPU_LITTLE_ENDIAN /* << EST: defined by Processor Expert CPU.h for Kinetis devices */ + #ifndef LITTLE_ENDIAN /* might be defined already on the compiler command line? */ + #define LITTLE_ENDIAN + #endif +#endif + +#ifndef LITTLE_ENDIAN +#define ieee_htons(x) (uint_16)(x) +#define ieee_htonl(x) (uint_32)(x) +#define ieee_ntohs(x) (uint_16)(x) +#define ieee_ntohl(x) (uint_32)(x) +#else +#define ieee_htons(x) BYTESWAP16(x) +#define ieee_htonl(x) BYTESWAP32(x) +#define ieee_ntohs(x) BYTESWAP16(x) +#define ieee_ntohl(x) BYTESWAP32(x) +#endif + +#ifndef UNUSED + #define UNUSED(x) (void)(x); +#endif +/****************************************************************************** + * Types + *****************************************************************************/ +typedef void _PTR_ pointer; /* Machine representation of a pointer */ +typedef unsigned char uint_8; /* 8-bit*/ +typedef signed char int_8; /* 8-bit*/ + +typedef unsigned short uint_16; /* 16-bit*/ +typedef signed short int_16; /* 16-bit*/ + +typedef unsigned long uint_32; /* 32-bit*/ +typedef signed long int_32; /* 32-bit*/ + +typedef unsigned char boolean; /* 8-bit*/ + +typedef uint_8* uint_8_ptr; /* ptr to 8-bit*/ +typedef uint_16* uint_16_ptr; /* ptr to 16-bit */ +typedef uint_32* uint_32_ptr; /* ptr to 32-bit*/ + +typedef uint_8_ptr uint8_ptr; /* ptr to 8-bit*/ + +/* definition of 8 bit word */ +typedef union _BYTE +{ + uint_8 _byte; + struct + { + unsigned b0:1; + unsigned b1:1; + unsigned b2:1; + unsigned b3:1; + unsigned b4:1; + unsigned b5:1; + unsigned b6:1; + unsigned b7:1; + }Bit; +} BYTE; + +/* definition of 16 bit word */ +typedef union _WORD +{ + uint_16 _word; + struct + { + uint_8 byte1; + uint_8 byte0; + }_byte; + struct + { + BYTE HighB; + BYTE LowB; + }_Byte; +} WORD; + +/* definition of 32 bit word */ +typedef union _DWORD +{ + uint_32 _dword; + struct + { + uint_8 byte3; + uint_8 byte2; + uint_8 byte1; + uint_8 byte0; + }_byte; + struct + { + uint_16 word1; + uint_16 word0; + }_word; + struct + { + BYTE Byte3; + BYTE Byte2; + BYTE Byte1; + BYTE Byte0; + }_Byte; + struct + { + WORD Word1; + WORD Word0; + }_Word; +} DWORD; + +/****************************************************************************** + * Global Functions - None + *****************************************************************************/ + +#endif + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h new file mode 100644 index 0000000..d9f24bb --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_bdt_kinetis.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_bdt_kinetis.h + * + * @author + * + * @version + * + * @date Jun-05-2009 + * + * @brief The file contains definitions of Buffer Descriptor Table. + * + *****************************************************************************/ + +#ifndef _USBBDT_H +#define _USBBDT_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +/* Buffer Descriptor Status Register Initialization Parameters */ +#define _BDTSTALL (0x04) /* Buffer Stall enable */ +#define _DATA0 (0x00) /* DATA0 packet expected next */ +#define _DATA1 (0x40) /* DATA1 packet expected next */ +#define _DTS (0x08) /* DTS Mask */ +#define _SIE (0x80) /* SIE owns buffer */ +#define _CPU (0x00) /* CPU owns buffer */ +#define _KEEP (0x20) /* keep bit */ + +#define MAX_BDT_INDEX (64) /* Maximum BDT Indexes */ + + +/****************************************************************************** + * Types + *****************************************************************************/ + /* This structure is an exact replica of the BDT MAP in the USB RAM + The BDT_STAT defines the stat byte of the buffer descriptor vector. + McuCtlBit structure defines the bits that have a meaning from CPU + point of view.SieCtlBit structure defines the bits that have a + meaning from USB controller point of view. + */ + +#if defined(__CWCC__) +#pragma align_array_members on +#endif +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) +typedef struct _MCU_CTL_BIT{ + uint_8 :1; + uint_8 :1; + uint_8 bdtstall:1; /* Buffer Stall Enable */ + uint_8 dts:1; /* Data Toggle Synch Enable */ + uint_8 keep:1; /* Address Increment Disable */ + uint_8 ninc:1; /* BD Keep Enable */ + uint_8 data:1; /* Data Toggle Synch Value */ + uint_8 own:1; /* USB Ownership */ +}MCU_CTL_BIT; /* read Stat */ + +typedef struct _SIE_CTL_BIT{ + uint_8 :1; + uint_8 :1; + uint_8 pid0:1; /* Packet Identifier bit 0 */ + uint_8 pid1:1; /* Packet Identifier bit 1 */ + uint_8 pid2:1; /* Packet Identifier bit 2 */ + uint_8 pid3:1; /* Packet Identifier bit 3 */ + uint_8 :1; + uint_8 own:1; +}SIE_CTL_BIT; /* write Stat */ + +typedef struct _REC_PID{ + uint_8 :2; + uint_8 pid:4; /* Packet Identifier */ + uint_8 :2; +}REC_PID; + +typedef union _BD_STAT +{ + uint_8 _byte; + MCU_CTL_BIT McuCtlBit; + SIE_CTL_BIT SieCtlBit; + REC_PID RecPid; +} BD_STAT; /* Buffer Descriptor Status Register */ + +typedef struct _BUFF_DSC +{ + BD_STAT Stat; + uint_8 reserved1; + uint_16 cnt; /* Count of bytes receieved or sent */ + /* six MSB bits are reserved ones */ + uint_32 addr; /* Buffer Address */ +} BUFF_DSC, *P_BUFF_DSC; /* Buffer Descriptor Table */ + +typedef struct _g_bdtmap { + + BUFF_DSC ep_dsc[MAX_BDT_INDEX]; /* Endpoint Descriptor */ +}BDTMAP; +#if defined(__CWCC__) +#pragma align_array_members off +#pragma options align=reset +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma pack() +#else /* e.g. gcc */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#endif +/****************************************************************************** + * Global Functions - None + *****************************************************************************/ + +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c new file mode 100644 index 0000000..b2b02c8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.c @@ -0,0 +1,809 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack CDC layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_cdc.h" /* USB CDC Class Header File */ +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ +#ifdef _MC9S08JS16_H +#pragma DATA_SEG APP_DATA +#endif + +/* CDC Class Callback Function Pointer */ +static USB_CLASS_CALLBACK g_cdc_class_callback = NULL; + +/* CDC Class Vendor Callback Function Pointer */ +static USB_REQ_FUNC g_vendor_req_callback = NULL; + +/* CDC endpoint info array */ +#ifndef COMPOSITE_DEV +static USB_CLASS_CDC_ENDPOINT g_cdc_ep[CDC_DESC_ENDPOINT_COUNT]; +#else +static USB_CLASS_CDC_ENDPOINT g_cdc_ep[COMPOSITE_DESC_ENDPOINT_COUNT]; +#endif +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +#if CIC_NOTIF_ELEM_SUPPORT +void USB_Class_CDC_Service_Cic_Notify(PTR_USB_DEV_EVENT_STRUCT event); +#endif +#if !DIC_ISOCHRONOUS_SETTING +void USB_Class_CDC_Service_Dic_Bulk_In(PTR_USB_DEV_EVENT_STRUCT event); +void USB_Class_CDC_Service_Dic_Bulk_Out(PTR_USB_DEV_EVENT_STRUCT event); +#else +static void USB_Class_CDC_Service_Dic_Iso_In(PTR_USB_DEV_EVENT_STRUCT event); +static void USB_Class_CDC_Service_Dic_Iso_Out(PTR_USB_DEV_EVENT_STRUCT event); +#endif +#ifndef COMPOSITE_DEV +static uint_8 USB_Other_Requests( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +#endif + void USB_Class_CDC_Event( + uint_8 controller_ID, + uint_8 event, + void* val); + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + + /***************************************************************************** + * Local Functions + *****************************************************************************/ +#if CIC_NOTIF_ELEM_SUPPORT +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Cic_Notify + * + * @brief The function is callback function of CIC Notification endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower layer when data on CIC Endpoint is sent + *****************************************************************************/ +void USB_Class_CDC_Service_Cic_Notify ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + break; + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + + if(g_cdc_class_callback != NULL) + { + uint_8 event_type = USB_APP_SEND_COMPLETE; + + if(event->errors != 0) + { + event_type = USB_APP_ERROR; + } + g_cdc_class_callback(event->controller_ID, event_type, + (uint_8*)(&(event->errors))); + } +} +#endif + +#if !DIC_ISOCHRONOUS_SETTING +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Bulk_In + * + * @brief The function is callback function of DIC Bulk In Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC SEND Interface is sent + *****************************************************************************/ +void USB_Class_CDC_Service_Dic_Bulk_In ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT bulk_in_recv; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + bulk_in_recv.data_ptr = event->buffer_ptr; + bulk_in_recv.data_size = event->len; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + break; + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_SEND_COMPLETE, + (void*)&bulk_in_recv); + } + } +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Bulk_Out + * + * @brief The function is callback function of DIC Bulk Out Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC RECV Interface is received + *****************************************************************************/ +void USB_Class_CDC_Service_Dic_Bulk_Out ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ APP_DATA_STRUCT bulk_out_recv; + + bulk_out_recv.data_ptr = event->buffer_ptr; + bulk_out_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_DATA_RECEIVED, + (void*)&bulk_out_recv); + } + } +} + +#else +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Iso_In + * + * @brief The function is callback function of DIC Isochronous In Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC SEND Interface is sent + *****************************************************************************/ +static void USB_Class_CDC_Service_Dic_Iso_In ( + PTR_USB_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT iso_in_recv; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(event->controller_ID); + + USB_CLASS_CDC_QUEUE queue; + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == event->ep_num) + { + break; + } + } + + producer = g_cdc_ep[index].bin_producer; + + /* if there are no errors de-queue the queue and decrement the no. of + transfers left, else send the same data again */ + if(event->errors == 0) + { + g_cdc_ep[index].bin_consumer++; + } + + consumer = g_cdc_ep[index].bin_consumer; + + if(consumer != producer) + {/*if bin is not empty */ + + queue = g_cdc_ep[index].queue[consumer%MAX_QUEUE_ELEMS]; + + (void)USB_Class_Send_Data(queue.controller_ID, queue.channel, + queue.app_data.data_ptr, queue.app_data.data_size); + } +#endif + + iso_in_recv.data_ptr = event->buffer_ptr; + iso_in_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_SEND_COMPLETE, + (void*)&iso_in_recv); + } + } +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Service_Dic_Iso_Out + * + * @brief This is a callback function of DIC Isochronous Out Endpoint + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * Called by Lower Layer when Data on DIC RECV Interface is received + *****************************************************************************/ +static void USB_Class_CDC_Service_Dic_Iso_Out ( + PTR_USB_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + APP_DATA_STRUCT iso_out_recv; + + iso_out_recv.data_ptr = event->buffer_ptr; + iso_out_recv.data_size = event->len; + + if(g_cdc_class_callback != NULL) + { + if(event->errors != 0) + { + g_cdc_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + } + else + { + g_cdc_class_callback(event->controller_ID, USB_APP_DATA_RECEIVED, + (void*)&iso_out_recv); + } + } +} +#endif +/**************************************************************************//*! + * + * @name USB_Class_CDC_Event + * + * @brief The function initializes CDC endpoints + * + * @param controller_ID : Controller ID + * @param event : Event Type + * @param val : Pointer to configuration Value + * + * @return None + * + ****************************************************************************** + * + *****************************************************************************/ +void USB_Class_CDC_Event ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 event, /* [IN] Event Type */ + void* val /* [OUT] Pointer to configuration Value */ +) +{ + uint_8 index; + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(controller_ID); + + if(event == USB_APP_ENUM_COMPLETE) + { + uint_8 count = 0,ep_count = 0; + uint_8 index_num = 0; + +#ifdef COMPOSITE_DEV + DEV_ARCHITECTURE_STRUCT_PTR dev_arc_ptr; + CLASS_ARC_STRUCT_PTR dev_class_ptr; + dev_arc_ptr = (DEV_ARCHITECTURE_STRUCT *)USB_Desc_Get_Class_Architecture(controller_ID); + for(count = 0; count < dev_arc_ptr->cl_count; count++) + { + dev_class_ptr = (CLASS_ARC_STRUCT_PTR)dev_arc_ptr->value[count]; + /* Initializes sub_classes */ + ep_count = dev_class_ptr->value[0]; + if(dev_class_ptr->class_type == 0x02/*CDC_CC*/) + break; + index_num +=dev_class_ptr->value[0]; + } +#else + ep_count = usb_ep_data->count; +#endif + + for(count=index_num; countep[count]); // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + (void)_usb_device_deinit_endpoint(&controller_ID, + ep_struct_ptr->ep_num, ep_struct_ptr->direction); + } + + /* intialize all non control endpoints */ + for(count=index_num; countep[count]); // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + + (void)_usb_device_init_endpoint(&controller_ID, ep_struct->ep_num, + ep_struct->size, ep_struct->direction, ep_struct->type, FALSE); + + /* register callback service for Non Control EndPoints */ + switch(ep_struct->type) + { +#if CIC_NOTIF_ELEM_SUPPORT + case USB_INTERRUPT_PIPE : + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Cic_Notify); + break; +#endif +#if !DIC_ISOCHRONOUS_SETTING + case USB_BULK_PIPE : +#ifdef MULTIPLE_DEVICES + if(ep_struct->direction == USB_RECV) + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Bulk_Out); + } + else + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Bulk_In); + } +#endif + break; +#else + case USB_ISOCHRONOUS_PIPE : + if(ep_struct->direction == USB_RECV) + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Iso_Out); + } + else + { + (void)_usb_device_register_service(controller_ID, + (uint_8)(USB_SERVICE_EP0+ep_struct->ep_num), + USB_Class_CDC_Service_Dic_Iso_In); + } + break; +#endif + default: + break; + } + /* set the EndPoint Status as Idle in the device layer */ + (void)_usb_device_set_status(&controller_ID, + (uint_8)(USB_STATUS_ENDPOINT | ep_struct->ep_num | + (ep_struct->direction << USB_COMPONENT_DIRECTION_SHIFT)), + (uint_8)USB_STATUS_IDLE); + } + } + else if(event == USB_APP_BUS_RESET) + { +#if IMPLEMENT_QUEUING + for(index = 0; index < usb_ep_data->count; index++) + { + g_cdc_ep[index].bin_consumer = 0x00; + g_cdc_ep[index].bin_producer = 0x00; + } +#endif + } + if(g_cdc_class_callback != NULL) + { + g_cdc_class_callback(controller_ID, event, val); + } +} + +/**************************************************************************//*! + * + * @name USB_Other_Requests + * + * @brief The function provides flexibilty to add class and vendor specific + * requests + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data: : Data to be send back + * @param size: : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * Handles CDC Class requests and forwards vendor specific request to the + * application + *****************************************************************************/ +#ifndef COMPOSITE_DEV +static uint_8 USB_Other_Requests +#else +uint_8 USB_CDC_Other_Requests +#endif +( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet,/* [IN] Pointer to Setup Packet Received */ + uint_8_ptr *data, /* [OUT] Pointer to Data Buffer to be sent */ + USB_PACKET_SIZE *size /* [OUT] Size of Data buffer */ +) +{ + uint_8 status = USBERR_INVALID_REQ_TYPE; + if((setup_packet->request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_CLASS) + { + /* class request so handle it here */ + status=USB_OK; + + /* call for class/subclass specific requests */ + switch(setup_packet->request) + { + case SEND_ENCAPSULATED_COMMAND : + /* Add code to transfer Request and Acknowledgement */ + *size=0; + break; + case GET_ENCAPSULATED_RESPONSE : + /* + Add code for handling Transfer Response/Requests and + Notification + */ + *size=0; + break; + case SET_COMM_FEATURE : + status = USB_Class_CDC_PSTN_Set_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case GET_COMM_FEATURE : + status = USB_Class_CDC_PSTN_Get_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case CLEAR_COMM_FEATURE : /* Verify this implementation */ + *size = COMM_FEATURE_DATA_SIZE; + **data = 0x00; *(++(*data)) = 0x00;/* clear both feature bytes */ + status = USB_Class_CDC_PSTN_Set_Comm_Feature(controller_ID, + setup_packet, data, size); + break; + case GET_LINE_CODING : + status = USB_Class_CDC_PSTN_Get_Line_Coding(controller_ID, + setup_packet, data, size); + break; + case SET_LINE_CODING : + status = USB_Class_CDC_PSTN_Set_Line_Coding(controller_ID, + setup_packet, data, size); + break; + case SET_CONTROL_LINE_STATE : + status = USB_Class_CDC_PSTN_Set_Ctrl_Line_State(controller_ID, + setup_packet, data, size); + break; + case SEND_BREAK : + status = USB_Class_CDC_PSTN_Send_Break(controller_ID, + setup_packet, data, size); + break; + default: + *size=0; + break; + } + } + else if((setup_packet->request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_VENDOR) + { + /* vendor specific request */ + if(g_vendor_req_callback != NULL) + { + status = g_vendor_req_callback(controller_ID, setup_packet, data, + size); + } + } + return status; +} + + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +/**************************************************************************//*! + * + * @name USB_Class_CDC_Init + * + * @brief The function initializes the Device and Controller layer + * + * @param controller_ID: Controller ID + * @param cdc_class_callback: CDC Class Callback + * @param vendor_req_callback: vendor specific class request callback + * @param param_callback: PSTN Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * This function initializes the CDC Class layer and layers it is dependent upon + *****************************************************************************/ +uint_8 USB_Class_CDC_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK cdc_class_callback, /* [IN] CDC Class Callback */ + USB_REQ_FUNC vendor_req_callback, /* [IN] Vendor Request Callback */ + USB_CLASS_CALLBACK pstn_callback, /* [IN] PSTN Callback */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ + uint_8 index,status = USB_OK; + USB_ENDPOINTS *usb_ep_data = + (USB_ENDPOINTS *)USB_Desc_Get_Endpoints(controller_ID); +#ifndef COMPOSITE_DEV + /* Initialize the device layer*/ + status = _usb_device_init(controller_ID, NULL, + (uint_8)(usb_ep_data->count+1), bVregEn); + /* +1 is for Control Endpoint */ + + if(status == USB_OK) + { + /* Initialize the generic class functions */ + status = USB_Class_Init(controller_ID,USB_Class_CDC_Event, + USB_Other_Requests); +#endif +#if IMPLEMENT_QUEUING + for(index = 0; index < usb_ep_data->count; index++) + { + g_cdc_ep[index].endpoint = usb_ep_data->ep[index].ep_num; + g_cdc_ep[index].type = usb_ep_data->ep[index].type; + g_cdc_ep[index].bin_consumer = 0x00; + g_cdc_ep[index].bin_producer = 0x00; + } +#endif +#if PSTN_SUBCLASS_NOTIF_SUPPORT + /* Initialize the pstn subclass functions */ + status = USB_Class_CDC_Pstn_Init(controller_ID,pstn_callback); +#endif + if(status == USB_OK) + { + /* save the callback pointer */ + g_cdc_class_callback = cdc_class_callback; + + /* save the callback pointer */ + g_vendor_req_callback = vendor_req_callback; + } +#ifndef COMPOSITE_DEV + } +#endif + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_DeInit + * + * @brief The function de-initializes the Device and Controller layer + * + * @param controller_ID : Controller ID + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + *This function de-initializes the CDC Class layer + *****************************************************************************/ +uint_8 USB_Class_CDC_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 status = USB_OK; +#ifdef COMPOSITE_DEV + UNUSED(controller_ID); +#endif + /* save the callback pointer */ + g_cdc_class_callback = NULL; + + /* free the vendor request callback pointer */ + g_vendor_req_callback = NULL; + +#ifndef COMPOSITE_DEV + /* call common class deinit function */ + status = USB_Class_DeInit(controller_ID); + + if(status == USB_OK) + /* Call device deinit function */ + status = _usb_device_deinit(); +#endif + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Send_Data + * + * @brief This function is used to send data from CDC Class over send endpoints + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param app_buff : Buffer to send + * @param size : Length of the transfer + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Helper function. Sends DATA over CIC and DIC Interfaces to Host + *****************************************************************************/ +uint_8 USB_Class_CDC_Send_Data ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8_ptr app_buff, /* Pointer to Application Buffer */ + USB_PACKET_SIZE size /* Size of Application Buffer */ +) +{ + uint_8 status = USB_OK; + +#if IMPLEMENT_QUEUING + uint_8 index; + uint_8 producer, consumer; + + USB_ENDPOINTS *usb_ep_data = (USB_ENDPOINTS *) + USB_Desc_Get_Endpoints(controller_ID); + + /* map the endpoint num to the index of the endpoint structure */ + for(index = 0; index < usb_ep_data->count; index++) + { + if(usb_ep_data->ep[index].ep_num == ep_num) + { + break; + } + } + + producer = g_cdc_ep[index].bin_producer; + consumer = g_cdc_ep[index].bin_consumer; + + if(((uint_8)(producer - consumer)) != (uint_8)(MAX_QUEUE_ELEMS)) + { + /* the bin is not full*/ + + uint_8 queue_num = (uint_8)(producer % MAX_QUEUE_ELEMS); + + /* put all send request parameters in the endpoint data structure */ + g_cdc_ep[index].queue[queue_num].controller_ID = controller_ID; + g_cdc_ep[index].queue[queue_num].channel = ep_num; + g_cdc_ep[index].queue[queue_num].app_data.data_ptr = app_buff; + g_cdc_ep[index].queue[queue_num].app_data.data_size = size; + + /* increment producer bin by 1*/ + g_cdc_ep[index].bin_producer = ++producer; + + if((uint_8)(producer - consumer) == (uint_8)1) + { +#endif + status = USB_Class_Send_Data(controller_ID, ep_num, app_buff,size); +#if IMPLEMENT_QUEUING + } + } + else /* bin is full */ + { + status = USBERR_DEVICE_BUSY; + } +#endif + return status; +} + +/* EOF */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h new file mode 100644 index 0000000..89f27ab --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc.h @@ -0,0 +1,202 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack CDC class layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_CDC_H +#define _USB_CDC_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_descriptor.h" +#include "usb_class.h" +#include "usb_cdc_pstn.h" +#include "usb_devapi.h" +#ifdef COMPOSITE_DEV +#include "usb_composite.h" +#endif + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +/* Class specific request Codes */ +#define SEND_ENCAPSULATED_COMMAND (0x00) +#define GET_ENCAPSULATED_RESPONSE (0x01) +#define SET_COMM_FEATURE (0x02) +#define GET_COMM_FEATURE (0x03) +#define CLEAR_COMM_FEATURE (0x04) +#define SET_AUX_LINE_STATE (0x10) +#define SET_HOOK_STATE (0x11) +#define PULSE_SETUP (0x12) +#define SEND_PULSE (0x13) +#define SET_PULSE_TIME (0x14) +#define RING_AUX_JACK (0x15) +#define SET_LINE_CODING (0x20) +#define GET_LINE_CODING (0x21) +#define SET_CONTROL_LINE_STATE (0x22) +#define SEND_BREAK (0x23) +#define SET_RINGER_PARAMS (0x30) +#define GET_RINGER_PARAMS (0x31) +#define SET_OPERATION_PARAM (0x32) +#define GET_OPERATION_PARAM (0x33) +#define SET_LINE_PARAMS (0x34) +#define GET_LINE_PARAMS (0x35) +#define DIAL_DIGITS (0x36) +#define SET_UNIT_PARAMETER (0x37) +#define GET_UNIT_PARAMETER (0x38) +#define CLEAR_UNIT_PARAMETER (0x39) +#define GET_PROFILE (0x3A) +#define SET_ETHERNET_MULTICAST_FILTERS (0x40) +#define SET_ETHERNET_POW_PATTER_FILTER (0x41) +#define GET_ETHERNET_POW_PATTER_FILTER (0x42) +#define SET_ETHERNET_PACKET_FILTER (0x43) +#define GET_ETHERNET_STATISTIC (0x44) +#define SET_ATM_DATA_FORMAT (0x50) +#define GET_ATM_DEVICE_STATISTICS (0x51) +#define SET_ATM_DEFAULT_VC (0x52) +#define GET_ATM_VC_STATISTICS (0x53) +#define MDLM_SPECIFIC_REQUESTS_MASK (0x7F) + +/* Class Specific Notification Codes */ +#define NETWORK_CONNECTION_NOTIF (0x00) +#define RESPONSE_AVAIL_NOTIF (0x01) +#define AUX_JACK_HOOK_STATE_NOTIF (0x08) +#define RING_DETECT_NOTIF (0x09) +#define SERIAL_STATE_NOTIF (0x20) +#define CALL_STATE_CHANGE_NOTIF (0x28) +#define LINE_STATE_CHANGE_NOTIF (0x29) +#define CONNECTION_SPEED_CHANGE_NOTIF (0x2A) +#define MDLM_SPECIFIC_NOTIF_MASK (0x5F) + +/* Events to the Application */ /* 0 to 4 are reserved for class events */ +#define USB_APP_CDC_CARRIER_DEACTIVATED (0x21) +#define USB_APP_CDC_CARRIER_ACTIVATED (0x22) + +/* other macros */ +#define NOTIF_PACKET_SIZE (0x08) +#define NOTIF_REQUEST_TYPE (0xA1) + +/* macros for queuing */ +#define MAX_QUEUE_ELEMS (4) + +#if CIC_NOTIF_ELEM_SUPPORT +#define CIC_SEND_ENDPOINT CIC_NOTIF_ENDPOINT +#endif + +#if DIC_ISOCHRONOUS_SETTING + #define DIC_SEND_ENDPOINT DIC_ISO_IN_ENDPOINT + #define DIC_RECV_ENDPOINT DIC_ISO_OUT_ENDPOINT +#else + #define DIC_SEND_ENDPOINT DIC_BULK_IN_ENDPOINT + #define DIC_RECV_ENDPOINT DIC_BULK_OUT_ENDPOINT +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ +#ifndef COMPOSITE_DEV +typedef struct _app_data_struct +{ + uint_8_ptr data_ptr; /* pointer to buffer */ + USB_PACKET_SIZE data_size; /* buffer size of endpoint */ +}APP_DATA_STRUCT; +#endif + +/* structure to hold a request in the endpoint queue */ +typedef struct _usb_class_cdc_queue +{ + uint_8 controller_ID; /* Controller ID */ + uint_8 channel; /* Endpoint Number */ + APP_DATA_STRUCT app_data; /* Application Data Structure */ +}USB_CLASS_CDC_QUEUE, *PTR_USB_CLASS_CDC_QUEUE; + +/* USB class cdc endpoint data */ +typedef struct _usb_class_cdc_endpoint +{ + uint_8 endpoint; /* endpoint num */ + uint_8 type; /* type of endpoint (interrupt, bulk or isochronous) */ + uint_8 bin_consumer;/* the num of queued elements */ + uint_8 bin_producer;/* the num of de-queued elements */ + USB_CLASS_CDC_QUEUE queue[MAX_QUEUE_ELEMS]; /* queue data */ +}USB_CLASS_CDC_ENDPOINT; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Class_CDC_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK cdc_class_callback, /* [IN] CDC Class Callback */ + USB_REQ_FUNC vendor_req_callback, /* [IN] Vendor Request Callback */ + USB_CLASS_CALLBACK pstn_callback, /* [IN] PSTN Callback */ + uint_8 bVregEn /* Enables or disables internal regulator */ +); + +#ifdef COMPOSITE_DEV +extern uint_8 USB_CDC_Other_Requests(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +#endif + +extern uint_8 USB_Class_CDC_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Class_CDC_Send_Data ( + uint_8 controller_ID, + uint_8 ep_num, + uint_8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +#if CIC_NOTIF_ELEM_SUPPORT +#define USB_Class_CDC_Interface_CIC_Send_Data(a,b,c) \ + USB_Class_CDC_Send_Data(a,CIC_SEND_ENDPOINT,b,c) +#endif + +#define USB_Class_CDC_Interface_DIC_Send_Data(a,b,c) \ + USB_Class_CDC_Send_Data(a,DIC_SEND_ENDPOINT,b,c) +#define USB_Class_CDC_Interface_DIC_Recv_Data(a,b,c) \ + _usb_device_recv_data(a,DIC_RECV_ENDPOINT,b,c) +#define USB_Class_CDC_Interface_DIC_Get_Send_Buffer(a,b,c) \ + _usb_device_get_send_buffer(a,DIC_SEND_ENDPOINT,b,c) + +#define USB_Class_CDC_Periodic_Task USB_Class_Periodic_Task + +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c new file mode 100644 index 0000000..1674391 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.c @@ -0,0 +1,398 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc_pstn.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB CDC_PSTN Sub Class implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ + #include "usb_cdc_pstn.h" /* USB CDC PSTN Sub Class Header File */ + + /***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/***************************************************************************** + * Global Functions Prototypes + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables + *****************************************************************************/ +/* PSTN subclass callback pointer */ +static USB_CLASS_CALLBACK g_pstn_callback = NULL; +/* data terminal equipment present or not */ +static boolean g_dte_present = FALSE; +static uint_8 g_dte_status = 0; /* Status of DATA TERMINAL EQUIPMENT */ +static uint_16 g_break_duration = 0; /* Length of time in milliseconds of the + break signal */ +static uint_8 g_current_interface = 0; +static UART_BITMAP g_uart_bitmap; + +#if CIC_NOTIF_ELEM_SUPPORT +static uint_8 g_serial_state_buf[NOTIF_PACKET_SIZE+UART_BITMAP_SIZE] = +{ + NOTIF_REQUEST_TYPE,SERIAL_STATE_NOTIF, + 0x00,0x00,/*wValue*/ + 0x00,0x00,/*interface - modifies*/ + UART_BITMAP_SIZE,0x00,/* wlength*/ + 0x00,0x00 /*data initialized - modifies*/ +};/*uart bitmap*/ +#endif + /***************************************************************************** + * Local Functions + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_Class_CDC_Pstn_Init + * + * @brief The function initializes the PSTN Module + * + * @param controller_ID : Controller ID + * @param callback : PSTN Callback + * + * @return error + * USB_OK : Always + ****************************************************************************** + * PSTN Sub Class Initialization routine + *****************************************************************************/ +uint_8 USB_Class_CDC_Pstn_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK callback /* [IN] PSTN Callback */ +) +{ + uint_8 error = USB_OK; + UNUSED (controller_ID); + + /* save input parameters */ + g_pstn_callback = callback; + return error; +} +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Get_Line_Coding + * + * @brief This function is called in response to GetLineCoding request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data to be send + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE: When request for + * invalid Interface is presented + ****************************************************************************** + * Calls application to receive Line Coding Information + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Get_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data to be send */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + UNUSED (size); + g_current_interface = (uint_8)setup_packet->index ; + status = USB_Desc_Get_Line_Coding(controller_ID, g_current_interface, + data); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Line_Coding + * + * @brief This function is called in response to SetLineCoding request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Calls Applciation to update Line Coding Information + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + UNUSED(data); + + *size = 0; + + g_current_interface = (uint_8)setup_packet->index ; + status = USB_Desc_Set_Line_Coding(controller_ID, g_current_interface, + (uint_8_ptr *)&setup_packet); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Ctrl_Line_State + * + * @brief This function is called in response to Set Control Line State + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : Always + ****************************************************************************** + * Updates Control Line State + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Ctrl_Line_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + UNUSED(data); + *size = 0; + + g_dte_status = (uint_8)setup_packet->value ; + g_uart_bitmap._byte = 0x00; /* initialize */ + /* activate/deactivate Tx carrier */ + g_uart_bitmap.Bitmap_Uart.bTxCarrier = (g_dte_status & + CARRIER_ACTIVATION_CHECK) ? 1 : 0 ; + /* activate carrier and DTE */ + g_uart_bitmap.Bitmap_Uart.bRxCarrier = (g_dte_status & + CARRIER_ACTIVATION_CHECK) ? 1 : 0 ; + + /* Indicates to DCE if DTE is present or not */ + g_dte_present = (boolean)((g_dte_status & DTE_PRESENCE_CHECK) ? + TRUE : FALSE); + UNUSED(g_dte_present); +#if CIC_NOTIF_ELEM_SUPPORT + /* Send Notification to Host - Parameter on Device side has changed */ + USB_Class_CDC_PSTN_Send_Serial_State(controller_ID); +#endif + if(g_pstn_callback != NULL) + { + if(g_dte_status & CARRIER_ACTIVATION_CHECK) + { + g_pstn_callback(controller_ID, USB_APP_CDC_CARRIER_ACTIVATED, + NULL); + } + else + { + g_pstn_callback(controller_ID, USB_APP_CDC_CARRIER_DEACTIVATED, + NULL); + } + } + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Send_Break + * + * @brief This function is called in response to Set Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : Always + ****************************************************************************** + * Updates Break Duration Information from Host + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Send_Break ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + UNUSED (controller_ID); + UNUSED (data); + *size = 0; + + g_break_duration = setup_packet->value; + UNUSED(g_break_duration); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Get_Comm_Feature + * + * @brief This function is called in response to GetCommFeature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data to be send + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Returns the status of the get comm feature request + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Get_Comm_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data to send */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ uint_8 status; + + status = USB_OK; + *size = COMM_FEATURE_DATA_SIZE; + g_current_interface = (uint_8)setup_packet->index ; + if(setup_packet->value == ABSTRACT_STATE_FEATURE) + { + status = USB_Desc_Get_Abstract_State(controller_ID, + g_current_interface, data); + } + else if(setup_packet->value == COUNTRY_SETTING_FEATURE) + { + status = USB_Desc_Get_Country_Setting(controller_ID, + g_current_interface, data); + } + else + { + *size = 0; /* for Reserved/Invalid Feature Selector Value */ + } + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Set_Comm_Feature + * + * @brief This function is called in response to SetCommFeature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Pointer to setup packet + * @param data : Pointer to Data + * @param size : Pointer to Size of Data + * + * @return status: + * USB_OK : When Successfull + * USBERR_INVALID_REQ_TYPE : When request for invalid + * Interface is presented + ****************************************************************************** + * Sets the comm feature specified by Host + *****************************************************************************/ +uint_8 USB_Class_CDC_PSTN_Set_Comm_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Pointer to setup packet */ + uint_8_ptr *data, /* [OUT] Pointer to Data */ + USB_PACKET_SIZE *size /* [OUT] Pointer to Size of Data */ +) +{ + uint_8 status; + status = USB_OK; + *size = COMM_FEATURE_DATA_SIZE; + g_current_interface = (uint_8)setup_packet->index ; + if(setup_packet->value == ABSTRACT_STATE_FEATURE) + { + status = USB_Desc_Set_Abstract_State(controller_ID, + g_current_interface, data); + } + else if(setup_packet->value == COUNTRY_SETTING_FEATURE) + { + status = USB_Desc_Set_Country_Setting(controller_ID, + g_current_interface, data); + } + else + { + *size = 0; /* for Reserved/Invalid Feature Selector Value */ + } + return status; +} + +#if CIC_NOTIF_ELEM_SUPPORT +/**************************************************************************//*! + * + * @name USB_Class_CDC_PSTN_Send_Serial_State + * + * @brief This function is called to send serial state notification + * + * @param controller_ID : Controller ID + * + * @return NONE + ****************************************************************************** + * Returns the Serial State + *****************************************************************************/ +void USB_Class_CDC_PSTN_Send_Serial_State ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + /* update array for current interface */ + g_serial_state_buf[4] = g_current_interface; + /* Lower byte of UART BITMAP */ + g_serial_state_buf[NOTIF_PACKET_SIZE+UART_BITMAP_SIZE-2] = + g_uart_bitmap._byte; + (void)USB_Class_CDC_Interface_CIC_Send_Data(controller_ID, + g_serial_state_buf, (NOTIF_PACKET_SIZE + UART_BITMAP_SIZE)); +} +#endif + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h new file mode 100644 index 0000000..223c475 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_cdc_pstn.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_cdc_pstn.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB CDC_PSTN Sub Class API header function + * + *****************************************************************************/ + +#ifndef _USB_CDC_PSTN_H +#define _USB_CDC_PSTN_H + +/****************************************************************************** + * Includes + *****************************************************************************/ + #include "usb_cdc.h" /* USB CDC Class Header File */ +/****************************************************************************** + * Constants - None + *****************************************************************************/ +#ifdef __MCF52xxx_H__ +#pragma reverse_bitfields on +#endif +typedef struct _BITMAP_UART +{ + uint_8 bRxCarrier : 1; /* Receive Carrier Activation Flag */ + uint_8 bTxCarrier : 1; /* Transmit Carrier Activation Flag */ + uint_8 bBreak : 1; /* Break Flag */ + uint_8 bRingSignal : 1; /* Ring Signal Flag */ + uint_8 bFraming : 1; /* Frame Flag */ + uint_8 bParity : 1; /* Parity Flag */ + uint_8 bOverRun : 1; /* OverRun Flag */ + uint_8 reserved1 : 1; /* Reserved */ +}BITMAP_UART; +#ifdef __MCF52xxx_H__ +#pragma reverse_bitfields off +#endif + + +typedef union _UART_BITMAP +{ + uint_8 _byte; + BITMAP_UART Bitmap_Uart; +}UART_BITMAP; /* UART STATE BITMAP */ + + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define UART_BITMAP_SIZE (0x02) +#define ABSTRACT_STATE_FEATURE (0x01) +#define COUNTRY_SETTING_FEATURE (0x02) +#define CARRIER_ACTIVATION_CHECK (0x02) +#define DTE_PRESENCE_CHECK (0x01) + +extern uint_8 USB_Class_CDC_Pstn_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK callback +); + +extern uint_8 USB_Class_CDC_PSTN_Get_Line_Coding ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Line_Coding ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Ctrl_Line_State ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Send_Break ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Get_Comm_Feature ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Class_CDC_PSTN_Set_Comm_Feature ( + uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +#if CIC_NOTIF_ELEM_SUPPORT +extern void USB_Class_CDC_PSTN_Send_Serial_State (uint_8 controller_ID); +#endif +#endif + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c new file mode 100644 index 0000000..8f4730a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.c @@ -0,0 +1,493 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_class.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains USB stack Class module implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_class.h" /* USB class Header File */ +#include "usb_devapi.h" /* USB device Header file */ +#include "usb_framework.h" /* USB framework module header file */ +#include "hidef.h" /* for EnableInterrupts; macro */ + +#if 0 /* << EST */ +#if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) +#include "exceptions.h" +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + /* Class callback pointer */ +static USB_CLASS_CALLBACK g_class_callback = NULL; +/* save the device state before device goes to suspend state */ +static uint_8 g_device_state_before_suspend; +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +void USB_Suspend_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Resume_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Stall_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Sof_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Reset_Service (PTR_USB_DEV_EVENT_STRUCT event ); +void USB_Error_Service (PTR_USB_DEV_EVENT_STRUCT event ); + +/***************************************************************************** + * Local Variables + *****************************************************************************/ + + /***************************************************************************** + * Local Functions - None + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/**************************************************************************//*! + * + * @name USB_Suspend_Service + * + * @brief The function is called when host suspends the USB port + * + * @param event : Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Sets the device state as USB_STATE_SUSPEND + *****************************************************************************/ +void USB_Suspend_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* Get the status of the device before suspend, so that on resume we + can get back to the same state */ + (void)_usb_device_get_status(&(event->controller_ID), + USB_STATUS_DEVICE_STATE, &g_device_state_before_suspend); + /* Set the device state in the Device Layer to SUSPEND */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + USB_STATE_SUSPEND); + + /* let the application know that bus suspend has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_SUSPEND, NULL); + + return; +} + +/**************************************************************************//*! + * + * @name USB_Resume_Service + * + * @brief The function is called when host resumes the USB port + * + * @param event : Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Restore the state of the device before suspend + *****************************************************************************/ +void USB_Resume_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_8 device_state; + (void)_usb_device_get_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + &device_state); + if(device_state == USB_STATE_SUSPEND) + { + /* + Set the device state in the Device Layer to the state + before suspend + */ + (void)_usb_device_set_status(&(event->controller_ID), + USB_STATUS_DEVICE_STATE, g_device_state_before_suspend); + } + + /* let the application know that bus resume has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_RESUME, NULL); + + return; +} + +/**************************************************************************//*! + * + * @name USB_Stall_Service + * + * @brief The function is called when endpoint is stalled + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * This function sends STALL Packet for the endpoint to be stalled. Also, sets + * the status of Endpoint as STALLED + *****************************************************************************/ +void USB_Stall_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + if(event->ep_num == CONTROL_ENDPOINT) + { + /* Update the Endpoint Status in the Device Layer to Idle */ + (void)_usb_device_set_status(&(event->controller_ID), + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (event->direction << USB_COMPONENT_DIRECTION_SHIFT)), + (uint_16)USB_STATUS_IDLE); + } + return; +} + +/**************************************************************************//*! + * + * @name USB_Sof_Service + * + * @brief The function is called when SOF flag is set (from ISR) + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * This function is called when SOF token is received by controller. Updates + * SOF Count status. + *****************************************************************************/ +void USB_Sof_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_16 sof_count; + + /* update SOF */ + sof_count = event->buffer_ptr[0]; + sof_count <<= SOF_HIGH_BYTE_SHIFT; + sof_count |= event->buffer_ptr[1]; + + /* write SOF to status */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_SOF_COUNT, + (uint_8)sof_count); + return; +} +/**************************************************************************//*! + * + * @name USB_Reset_Service + * + * @brief The function is called upon a bus reset event. + Initializes the control endpoint. + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Reset Callback function. This function re-initializes CONTROL Endpoint + *****************************************************************************/ +void USB_Reset_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + + USB_EP_STRUCT ep_struct; + uint_8 err; + + /* Initialize the endpoint 0 in both directions */ + ep_struct.direction = USB_SEND; + ep_struct.ep_num = CONTROL_ENDPOINT; + ep_struct.size = CONTROL_MAX_PACKET_SIZE; + ep_struct.type = USB_CONTROL_PIPE; + + /* Deinit Endpoint in case its already initialized */ + err = _usb_device_deinit_endpoint(&(event->controller_ID), + ep_struct.ep_num, ep_struct.direction); + /* now initialize the endpoint */ + err = _usb_device_init_endpoint(&(event->controller_ID), + ep_struct.ep_num, (uint_16)ep_struct.size, ep_struct.direction, ep_struct.type, TRUE); + + ep_struct.direction = USB_RECV; + /* Deinit Endpoint in case its already initialized */ + (void)_usb_device_deinit_endpoint(&(event->controller_ID), + ep_struct.ep_num, ep_struct.direction); + /* now initialize the endpoint */ + (void)_usb_device_init_endpoint(&(event->controller_ID), + ep_struct.ep_num, (uint_16)ep_struct.size, ep_struct.direction, ep_struct.type, TRUE); + + /* set the default device state */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + USB_STATE_DEFAULT); + + /* set the default device state */ + (void)_usb_device_set_status(&(event->controller_ID), USB_STATUS_DEVICE, + SELF_POWERED >> SELF_POWER_BIT_SHIFT); + + /* set the EndPoint Status as Idle in the device layer */ + (void)_usb_device_set_status(&(event->controller_ID), + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (USB_SEND << USB_COMPONENT_DIRECTION_SHIFT)), + USB_STATUS_IDLE); + /* let the application know that bus reset has taken place */ + g_class_callback(event->controller_ID, USB_APP_BUS_RESET, NULL); + + UNUSED(err); + return; +} + +/**************************************************************************//*! + * + * @name USB_Error_Service + * + * @brief The function is called when an error has been detected + * + * @param event: Pointer to USB Event Structure + * + * @return None + ****************************************************************************** + * Calls application with the error code received from the lower layer + *****************************************************************************/ +void USB_Error_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* notify the application of the error */ + g_class_callback(event->controller_ID, USB_APP_ERROR, + (uint_8*)(&(event->errors))); + return; +} + + +/**************************************************************************//*! + * + * @name USB_Class_Init + * + * @brief The function initializes the Class Module + * + * @param controller_ID : Controller ID + * @param class_callback : Class callback + * @param other_req_callback : Other Requests Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Initializes USB Class Module + *****************************************************************************/ +uint_8 USB_Class_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK class_callback, /* [IN] Class Callback */ + USB_REQ_FUNC other_req_callback /* [IN] Other Requests Callback */ +) +{ + uint_8 status = USB_Framework_Init(controller_ID,class_callback, + other_req_callback); + + /* save callback address */ + g_class_callback = class_callback; + + if(status == USB_OK) + { + /* Register all the services here */ + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_BUS_RESET, USB_Reset_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_SOF,USB_Sof_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_SLEEP,USB_Suspend_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_RESUME,USB_Resume_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_STALL,USB_Stall_Service); + status |= _usb_device_register_service(controller_ID, + USB_SERVICE_ERROR,USB_Error_Service); + + /* set the device state as powered */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE,USB_STATE_POWERED); + g_device_state_before_suspend = USB_STATE_POWERED; + } + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_DeInit + * + * @brief The function De-initializes the Class Module + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * De-initializes USB Class Module + *****************************************************************************/ +uint_8 USB_Class_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 status = USB_OK; + /* Free class_callback */ + g_class_callback = NULL; + + /* Unegister all the services here */ + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_BUS_RESET); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_SOF); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_SLEEP); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_RESUME); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_STALL); + status |= _usb_device_unregister_service(&controller_ID,USB_SERVICE_ERROR); + + if(status == USB_OK) + /* Call Framework deinit function */ + status = USB_Framework_DeInit(controller_ID); + + return status; +} + +/**************************************************************************//*! + * + * @name USB_Class_Initiate_Resume + * + * @brief The function initiates resume procedure + * + * @param controller_ID : Controller ID + * + * @return device_state + ******************************************************************************/ +uint_8 USB_Class_Initiate_Resume( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 device_state, state; + + (void)_usb_device_get_status(&controller_ID, USB_STATUS_DEVICE_STATE, + &device_state); + (void)_usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &state); + if((device_state == USB_STATE_SUSPEND) && + (state & REMOTE_WAKEUP_STATUS_MASK ) && + (USB_Frame_Remote_Wakeup(controller_ID) == TRUE)) + { + DisableInterrupts; +#if 0 + #if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) + usb_int_dis(); + #endif +#else /* << EST */ + /* device is Kinetis K20D72 << EST */ +#endif + /* Resume the bus */ + _usb_device_assert_resume(&controller_ID); + + device_state = USB_STATE_CONFIG; + /* Set the device state in the Device Layer to DEFAULT */ + (void)_usb_device_set_status(&controller_ID, USB_STATUS_DEVICE_STATE, + USB_STATE_CONFIG); + EnableInterrupts;; + #if (defined _MCF51MM256_H) || (defined _MCF51JE256_H) + usb_int_en(); + #endif + } + return device_state; +} + +/**************************************************************************//*! + * + * @name USB_Class_Send_Data + * + * @brief The function calls the device to send data upon receiving an IN token + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param buff_ptr : Buffer to send + * @param size : Length of transfer + * + * @return status + * USB_OK : When Successfull + * Others : Errors + ****************************************************************************** + * Used by Application to send Data on USB Bus if not suspended + *****************************************************************************/ +uint_8 USB_Class_Send_Data ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8_ptr buff_ptr, /* [IN] Buffer to send */ + USB_PACKET_SIZE size /* [IN] Length of the transfer */ +) +{ + + uint_8 status = USB_OK; + uint_8 device_state; + + device_state = USB_Class_Initiate_Resume(controller_ID); + + if(device_state != USB_STATE_SUSPEND) + { /* if not suspended */ + status = _usb_device_send_data(&controller_ID, ep_num, buff_ptr, size); + } + + return status; + } + +/**************************************************************************//*! + * + * @name USB_Class_Periodic_Task + * + * @brief The function calls for periodic tasks + * + * @param None + * + * @return None + ****************************************************************************** + * Called to check for any pending requests + *****************************************************************************/ +void USB_Class_Periodic_Task (void) +{ +#ifdef DELAYED_PROCESSING + USB_Framework_Periodic_Task(); +#endif +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h new file mode 100644 index 0000000..d791d4c --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_class.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_class.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB stack class layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_CLASS_H +#define _USB_CLASS_H + + +/*#define DELAYED_PROCESSING 1 This define is used to delay the control + processing and not have it executed as part + of the interrupt routine */ +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define SOF_HIGH_BYTE_SHIFT (8) +#define GET_STATUS_DEVICE_MASK (0x0003) +#ifdef OTG_BUILD +#define GET_STATUS_OTG_MASK (0x0001) +#endif +#define REMOTE_WAKEUP_STATUS_MASK (0x0002) +#define BUS_POWERED (0x80) +#define SELF_POWERED (0x40) +#define SELF_POWER_BIT_SHIFT (6) + +/* Events to the Application */ +#define USB_APP_BUS_RESET (0) +#define USB_APP_CONFIG_CHANGED (1) +#define USB_APP_ENUM_COMPLETE (2) +#define USB_APP_SEND_COMPLETE (3) +#define USB_APP_DATA_RECEIVED (4) +#define USB_APP_ERROR (5) +#define USB_APP_GET_DATA_BUFF (6) +#define USB_APP_EP_STALLED (7) +#define USB_APP_EP_UNSTALLED (8) +#define USB_APP_GET_TRANSFER_SIZE (9) +#define USB_APP_BUS_SUSPEND (0x0A) +#define USB_APP_BUS_RESUME (0x0B) + +/* max packet size for the control endpoint */ + +/* USB Specs define CONTROL_MAX_PACKET_SIZE for High Speed device as only 64, + whereas for FS its allowed to be 8, 16, 32 or 64 */ + +#if HIGH_SPEED_DEVICE +#define CONTROL_MAX_PACKET_SIZE (64) /* max supported value is 64*/ +#else +#define CONTROL_MAX_PACKET_SIZE (16) /* max supported value is 16*/ +#endif + +/* identification values and masks to identify request types */ +#define USB_REQUEST_CLASS_MASK (0x60) +#define USB_REQUEST_CLASS_STRD (0x00) +#define USB_REQUEST_CLASS_CLASS (0x20) +#define USB_REQUEST_CLASS_VENDOR (0x40) + +/****************************************************************************** + * Types + *****************************************************************************/ +/* eight byte usb setup packet structure */ +typedef struct _USB_SETUP_STRUCT { + uint_8 request_type; /* bmRequestType */ + uint_8 request; /* Request code */ + uint_16 value; /* wValue */ + uint_16 index; /* wIndex */ + uint_16 length; /* Length of the data */ +} USB_SETUP_STRUCT; + +/* callback function pointer structure for Application to handle events */ +typedef void(_CODE_PTR_ USB_CLASS_CALLBACK)(uint_8, uint_8, void*); + +/* callback function pointer structure to handle USB framework request */ +typedef uint_8 (_CODE_PTR_ USB_REQ_FUNC)(uint_8, USB_SETUP_STRUCT *, + uint_8_ptr*, + USB_PACKET_SIZE*); + +/*callback function pointer structure for application to provide class params*/ +typedef uint_8 (_CODE_PTR_ USB_CLASS_SPECIFIC_HANDLER_FUNC)( + uint_8, + uint_16, + uint_16, // Application needs to know which Interface is being communicated with + uint_8_ptr*, + USB_PACKET_SIZE*); + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Class_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK class_callback, + USB_REQ_FUNC other_req_callback +); + +extern uint_8 USB_Class_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Class_Initiate_Resume( + uint_8 controller_ID +); + +extern uint_8 USB_Class_Send_Data ( + uint_8 controller_ID, + uint_8 ep_num, + uint_8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern void USB_Class_Periodic_Task(void); + +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c new file mode 100644 index 0000000..ff4febb --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.c @@ -0,0 +1,2954 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2012 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dci_kinetis.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains Kinetis USB stack controller layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include +#include "usb_dciapi.h" /* USB DCI API Header File */ +#include "usb_devapi.h" /* USB Device API Header File */ +#include "usb_dci_kinetis.h" /* USB DCI Header File */ +#include "usb_bdt_kinetis.h" /* USB BDT Structure Header File */ +#include "wdt_kinetis.h" +#include "usb_class.h" + +/***************************************************************************** + * Constant and Macro's - None + *****************************************************************************/ +/**************************************************************************** + * Global Variables + ****************************************************************************/ +#ifdef USE_FEEDBACK_ENDPOINT + extern uint_32 feedback_data; + extern uint_32 gNrSamples; +#endif + +/* location for BDT Table and buff */ +#if (defined(__CWCC__)||defined(__GNUC__)) + __attribute__((__aligned__(512))) +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma data_alignment = 512 +#endif + +#if !HIGH_SPEED_DEVICE + #if defined __CC_ARM + __align(512) uint_8 g_Mem[BYTES_1024]; + #else +#if 0 + static uint_8 g_Mem[BYTES_1024]; +#else + uint_8 g_Mem[BYTES_1024]; +#endif + #endif + /* Pointer to BDT Map Structure */ + BDTMAP *g_bdtmap = NULL; + /* per endpoint per direction bdt index structure */ + static BDT_ELEM g_bdt_elem[MAX_BDT_INDEX >> 1]; +#endif +/* stores Controller ID */ +static uint_8 g_dci_controller_Id = 0; +#if HIGH_SPEED_DEVICE +static uint_8 g_dci_address_state = 0; +#endif /* HIGH_SPEED_DEVICE */ + +#if !HIGH_SPEED_DEVICE +/* Start BDT buffer Address */ +static uint_32 g_bdt_address; +#endif /* HIGH_SPEED_DEVICE */ +/* Transfer direction */ +static uint_8 g_trf_direction = USB_TRF_UNKNOWN; + + +// HIGH_SPEED_DEVICE +#if HIGH_SPEED_DEVICE + #define MAX_DTDS_PER_EP 5 // maximum number of transfer descriptors + #define DTD_FREE 0 + #define DTD_BUSY 1 + #define MAX_ENDPOINT_NUMBER 4 + + // QH structures are 64-byte aligned + #define TOTAL_QHD_SIZE (SIZE_OF_QHD * (MAX_ENDPOINT_NUMBER * 2)) + // TD structures are 64-byte aligned + #define TOTAL_QTD_SIZE ((SIZE_OF_DTD0) * (MAX_ENDPOINT_NUMBER * 2) * MAX_DTDS_PER_EP) + + #ifdef __CWCC__ + #pragma define_section usb_dqh ".usb_dqh" RW + __declspec(usb_dqh) uint_8 g_usbd_qh_buf[TOTAL_QHD_SIZE]; // 512 + #pragma define_section usb_dtd ".usb_dtd" RW + __declspec(usb_dtd) uint_8 g_usbd_td_buf[TOTAL_QTD_SIZE]; // 1280 + #else + #pragma data_alignment=(0x1000) + uint_8 g_usbd_qh_buf[TOTAL_QHD_SIZE]; // 512 + #pragma data_alignment=(0x800) + uint_8 g_usbd_td_buf[TOTAL_QTD_SIZE]; // 1280 + #endif + + + /* flag status for td */ + static struct _td_status + { + uint_8 status; // DTD_BUSY or DTD_FREE + unsigned int total_bytes; // Original total bytes to transfer (not used by EP0) + volatile struct dtd_setup_t *phys_td; // Pointer to physical TD (not used by EP0) + } g_usbd_td_flag[MAX_ENDPOINT_NUMBER * 2][MAX_DTDS_PER_EP]; + static struct dtd_setup_t *g_usbd_qh_tail[MAX_ENDPOINT_NUMBER * 2]; +#endif // HIGH_SPEED_DEVICE + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +static void USB_Bus_Reset_Handler(void); +#if !HIGH_SPEED_DEVICE +static uint_8 USB_DCI_Get_BDT_Index(uint_8 ep_num, + uint_8 direction, + boolean odd); +static uint_8 USB_DCI_Validate_Param(uint_8 ep_num, + uint_8 direction, + boolean odd); +#ifdef LONG_SEND_TRANSACTION +static void USB_DCI_Prepare_Send_Data(P_BUFF_DSC buffer_dsc, + P_BDT_ELEM bdt_elem); +#endif /* LONG_SEND_TRANSACTION */ +static void USB_Bus_Token_Cpl_Handler(uint_8 stat, + USB_DEV_EVENT_STRUCT* event); +#endif /* HIGH_SPEED_DEVICE */ + +// HIGH_SPEED_DEVICE +#if HIGH_SPEED_DEVICE +static uint_8 K70_ULPI_SetDeviceMode(uint_8 controller_ID); +static void usbd_ep_qh_init(uint_8 controller_ID, + unsigned char endpt_number, unsigned char direction, + unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult, uint_32 next_dtd); +static void usbd_setup_qhead(struct dqh_t *qhead); +static void usbd_setup_td(struct dtd_t *td); +static unsigned int usbd_get_dqh(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction); +static void usbd_ep_setup(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned char ep_type); +static void usbd_ep_complete_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_setup_packet_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_read_setup_packet(uint_8 controller_ID, unsigned char *setup_packet); +static void usbd_port_change( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +); +static void usbd_ep0_complete(USB_DEV_EVENT_STRUCT* event); +static void usbd_dtd_complete(USB_DEV_EVENT_STRUCT* event); +static usb_status_t usbd_receive_data_ep0out(uint_8 controller_ID, unsigned int ep0_data_buffer, unsigned int sz); +static usb_status_t usbd_receive_data_epxout(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz); +static void usbd_add_td(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td); +static void usbd_prime_ep(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td); +static usb_status_t usbd_send_data_epxin(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz); +static usb_status_t usbd_send_data_ep0in(uint_8 controller_ID, + unsigned int ep0_data_buffer, unsigned int sz, + unsigned char zlt_enable); + +#endif +#ifdef USB_LOWPOWERMODE + static void Enter_StopMode(STOP_MODE stop_mode); +#endif +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_Bus_Reset_Handler + * + * @brief The function handles Bus Reset Interrupt + * + * @param None + * + * @return None + * + ****************************************************************************** + * This functions is called when USB Bus Reset event is received on USB Bus. + * This function clears all the errors conditions and reinit Global data + * structures. Also resets USB device controller. + *****************************************************************************/ +static void USB_Bus_Reset_Handler (void) +{ +#if !HIGH_SPEED_DEVICE + USB0_ERRSTAT = ERR_STAT_CLEAR_ALL; /* clear USB error flag */ + USB0_CTL |= USB_CTL_ODDRST_MASK; /* Reset to Even buffer */ + USB0_ADDR = 0; /* reset to default address */ + /* Select System Clock and Disable Weak Pull Downs */ + USB0_USBCTRL = 0x00; + + /* Clear bdt elem structure */ + Clear_Mem((uint_8_ptr)(g_bdt_elem), + (sizeof(BDT_ELEM) * (MAX_BDT_INDEX >> 1)), + (uint_8)UNINITIALISED_VAL); + + /* Clear Memory for BDT and buffer Data */ + Clear_Mem((uint_8_ptr)g_bdtmap,(uint_32) BYTES_1024, (uint_8)0); + + /* Initialize BDT buffer address */ + g_bdt_address = ((uint_32)g_bdtmap + BYTES_512); + + g_trf_direction = USB_TRF_UNKNOWN; + + USB0_CTL &= ~USB_CTL_ODDRST_MASK; + USB0_USBTRC0 |= 0x40; /* attach CFv1 core to USB bus */ + + USB0_ERREN = ERR_ENB_ENABLE_ALL; /* Enable All Error Interrupts */ + USB0_INTEN = INTENB_BUS_RESET_VAL; /* Enable All Interrupts except RESUME */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + +#else + uint_32 reg; + + //Clear the device address + USBHS_DEVICEADDR &= ~USBHS_DEVICEADDR_USBADR_MASK; + + // 1. Clear all setup token semaphores + reg = USBHS_EPSETUPSR; + USBHS_EPSETUPSR = reg; + + // 2. Clear all the endpoint complete status bits + reg = USBHS_EPCOMPLETE; + USBHS_EPCOMPLETE = reg; + + // 3. Cancel all primed status + while(USBHS_EPPRIME); + USBHS_EPFLUSH = 0xFFFFFFFF; + + // 4. If reset bit is not cleared at this point force reset device + if(!(USBHS_PORTSC1 & USBHS_PORTSC1_PR_MASK)){ + USBHS_USBCMD |= USBHS_USBCMD_RST_MASK; + } + + // 5. Free(reset) all allocated dTDs + memset(g_usbd_td_buf, 0, TOTAL_QTD_SIZE); + memset(g_usbd_td_flag, + 0, + MAX_ENDPOINT_NUMBER * 2 * MAX_DTDS_PER_EP * sizeof(g_usbd_td_flag)/sizeof(*g_usbd_td_flag) + ); + + g_trf_direction = USB_TRF_UNKNOWN; + UNUSED(g_trf_direction); +#endif +} + +#if !HIGH_SPEED_DEVICE +/**************************************************************************//*! + * + * @name USB_DCI_Get_BDT_Index + * + * @brief The function maps endpoint number and direction to bdt index + * + * @param ep_num : Endpoint Number + * @param direction: Endpoint direction + * @param odd : Odd or even buffer + * + * @return bdt index : Mapped bdt index + * INVALID_BDT_INDEX : In case of error + * + ****************************************************************************** + * This function returns BDT Index from Endpoint number, direction, + * odd/even buffer + *****************************************************************************/ +static uint_8 USB_DCI_Get_BDT_Index ( + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8 direction, /* [IN] Endpoint direction */ + boolean odd /* [IN] Odd or even buffer */ +) +{ + uint_8 bdt_index = INVALID_BDT_INDEX; + + if(ep_num < MAX_SUPPORTED_ENDPOINTS) + { + /* per endpoint 4 bdt_index -- 2 for recv 2 for send */ + bdt_index=(uint_8)((ep_num * 4) + (uint_8)odd); + + if(direction == USB_SEND) + { + bdt_index += 2; + } + } + return bdt_index; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Validate_Param + * + * @brief The function validates endpoint number & direction parameters + * and returns bdt index. + * + * @param ep_num : Endpoint Number + * @param direction: Endpoint direction + * @param odd : odd or even buffer + * + * @return bdt index : mapped bdt index + * INVALID_BDT_INDEX : incase of error + * + ****************************************************************************** + * This function validates endpoint parameters and returns bdt index + *****************************************************************************/ +static uint_8 USB_DCI_Validate_Param ( + uint_8 ep_num, /* [IN] Endpoint Number */ + uint_8 direction, /* [IN] Endpoint direction */ + boolean odd /* [IN] Odd or even buffer */ +) +{ + /* Get bdt index mapped to endpoint number-direction and odd/even buffer */ + uint_8 bdt_index = USB_DCI_Get_BDT_Index(ep_num, direction, odd); + + if((bdt_index != INVALID_BDT_INDEX) && + (g_bdt_elem[TRANSFER_INDEX(bdt_index)].len == + (uint_16)UNINITIALISED_VAL)) + { + /* Incase length in bdt_elem is uninitialised return invalid index */ + bdt_index = INVALID_BDT_INDEX; + } + return bdt_index; +} +#endif /* HIGH_SPEED_DEVICE */ + +#ifdef LONG_SEND_TRANSACTION +#if !HIGH_SPEED_DEVICE +/**************************************************************************//*! + * + * @name USB_DCI_Prepare_Send_Data + * + * @brief The function sets up the BDT for Send + * + * @param buffer_dsc : Pointer to buffer descriptor element in USB_RAM + * @param bdt_elem : Pointer to per endpoint/direction structure + * + * @return None + * + ****************************************************************************** + * This functions configures Buffer Descriptor (Address and Count) + *****************************************************************************/ +static void USB_DCI_Prepare_Send_Data ( + P_BUFF_DSC buffer_dsc, /* [OUT] Pointer to buffer descriptor + element in USB_RAM */ + P_BDT_ELEM bdt_elem /* [IN] Pointer to per endpoint/direction + structure */ +) +{ + uint_8_ptr buff_ptr = bdt_elem->app_buffer + bdt_elem->curr_offset; + uint_16 current_count = 0; + + /* adjust size based on the input at the init endpoint */ + if((bdt_elem->app_len - bdt_elem->curr_offset) > bdt_elem->len) + { + /* If size of packet is greater than endpoint buffer size */ + current_count = bdt_elem->len; + } + else + { + /* If size of packet is smaller than endpoint buffer size */ + current_count = (uint_16)(bdt_elem->app_len - bdt_elem->curr_offset); + } + + buffer_dsc->cnt = SWAP16(current_count); + + buffer_dsc->addr = SWAP32((uint_32)buff_ptr); +} +#endif /* HIGH_SPEED_DEVICE */ +#endif /* LONG_SEND_TRANSACTION */ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + +/**************************************************************************//*! + * + * @name USB_DCI_Init + * + * @brief The function initializes the Controller layer + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : Always + ****************************************************************************** + * Initializes the USB controller + *****************************************************************************/ +uint_8 USB_DCI_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ +#if !HIGH_SPEED_DEVICE +#if USB_USER_CONFIG_USE_STACK_INIT + /* Select System Clock and Disable Weak Pull Downs */ + USB0_USBCTRL = 0x00; +#endif + + /* save the controller_ID for future use */ + g_dci_controller_Id = controller_ID; + + /* Clear bdt elem structure */ + Clear_Mem((uint_8_ptr)(g_bdt_elem), + (sizeof(BDT_ELEM) * (MAX_BDT_INDEX >> 1)), + (uint_8)UNINITIALISED_VAL); + g_bdtmap = (BDTMAP *)((uint_32)g_Mem); + + /* Clear Memory for BDT and buffer Data */ + Clear_Mem((uint_8_ptr)g_bdtmap,(uint_32) BYTES_1024, (uint_8)0); + + #ifndef OTG_BUILD + #if 1 /* hardware bug workaround */ /* << EST: need to keep this workaround for FRDM-KL25Z */ + /* Hard Reset to the USB Module */ + USB0_USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + + /* loop till the Reset bit clears */ + while((USB0_USBTRC0 & USB_USBTRC0_USBRESET_MASK)) + { + }; + #if !USB_USER_CONFIG_USE_STACK_INIT + { + /* need to re-init USB, as the hard reset above has reset the whole module! */ + void USB0_Init(void); /* prototype */ + USB0_Init(); /* call Processor Expert Init_USB_OTG Init() */ + } + #endif + + #endif + #endif + + g_trf_direction = USB_TRF_UNKNOWN; + +#if USB_USER_CONFIG_USE_STACK_INIT + /* Asynchronous Resume Interrupt Enable */ + USB0_USBTRC0 |= 0x40; /* undocumented bit???? */ +#endif + if(bVregEn) + { + SIM_SOPT1 |= SIM_SOPT1_USBREGEN_MASK; // enable usb voltage regulator + } + else + { + SIM_SOPT1 &= ~SIM_SOPT1_USBREGEN_MASK; // disable usb voltage regulator + } + + /* Set the BDT Table address, Need to be on 512 byte boundary */ + /* D8 Bit is masked in BDT_PAGE_01 */ + USB0_BDTPAGE1 = (uint_8)(((uint_32)g_bdtmap >> 8)& 0xFE); + USB0_BDTPAGE2 = (uint_8)((uint_32)g_bdtmap >> 16); + USB0_BDTPAGE3 = (uint_8)((uint_32)g_bdtmap >> 24); + + /* Initialized BDT buffer address */ + g_bdt_address = ((uint_32)g_bdtmap + BYTES_512); + +#if USB_USER_CONFIG_USE_STACK_INIT + #ifndef OTG_BUILD + /* Pull Up configuration */ + USB0_CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK; + #endif +#endif + USB0_CTL = USB_CTL_USBENSOFEN_MASK; /* Enable USB module */ + USB0_ISTAT = INT_STAT_CLEAR_ALL; /* Clear USB interrupts*/ + + /* Remove suspend state */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + +#if USB_USER_CONFIG_USE_STACK_INIT + /* Enable USB RESET Interrupt */ + USB0_INTEN |= USB_INTEN_USBRSTEN_MASK; + + /* Enable USB Sleep Interrupt */ + USB0_INTEN |= USB_INTEN_SLEEPEN_MASK; + + USB0_OTGCTL = USB_OTGCTL_DPHIGH_MASK | USB_OTGCTL_OTGEN_MASK; +#endif /* USB_USER_CONFIG_USE_STACK_INIT */ +#else // HIGH_SPEED_DEVICE + /* save the controller_ID for future use */ + g_dci_controller_Id = controller_ID; + memset(g_usbd_qh_buf, 0, TOTAL_QHD_SIZE); + memset(g_usbd_td_buf, 0, TOTAL_QTD_SIZE); + + // initialize module in device mode + uint_8 status; + status = K70_ULPI_SetDeviceMode(controller_ID); + if(status != USB_OK) + return status; + + // initialize endpoint 0 + usbd_ep_qh_init(controller_ID, EP0, IN, 64, 0, 0, 1); + usbd_ep_qh_init(controller_ID, EP0, OUT, 64, 0, 0, 1); + + // setup interrupts + USBHS_USBINTR = USBHS_USBINTR_UE_MASK // USB interrupt + | USBHS_USBINTR_UEE_MASK // USB error + | USBHS_USBINTR_PCE_MASK // Port change + | USBHS_USBINTR_URE_MASK // Reset enable + | USBHS_USBINTR_SRE_MASK // SOF received + | USBHS_USBINTR_SLE_MASK // suspend received + | USBHS_USBINTR_SEE_MASK; // System error + + // enable pullup on DP and initiate attach event + USBHS_USBCMD |= USBHS_USBCMD_RS_MASK; +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_DeInit + * + * @brief The function de-initializes the Controller layer + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : Always + ****************************************************************************** + * Initializes the USB controller + *****************************************************************************/ +uint_8 USB_DCI_DeInit(void) +{ +#if !HIGH_SPEED_DEVICE + +#ifdef MCU_MK70F12 +#if 0 /* hardware bug workaround */ + // Reset module + USB0_USBTRC0 |= USB_USBTRC0_USBRESET_MASK; + + // Wait for reset to complete + while((USB0_USBTRC0 & USB_USBTRC0_USBRESET_MASK)); +#endif + +#else + /* Detach CFv1 core to USB bus*/ + USB0_USBTRC0 &= ~0x40; +#endif + + + /* Clear USB interrupts*/ + USB0_ISTAT = INT_STAT_CLEAR_ALL; + + /* Disable USB RESET Interrupt */ + USB0_INTEN &= ~USB_INTEN_USBRSTEN_MASK; + + /* Disable USB module */ + USB0_CTL &= ~USB_CTL_USBENSOFEN_MASK; + + USB0_OTGCTL &= ~(USB_OTGCTL_DPHIGH_MASK | USB_OTGCTL_OTGEN_MASK); +#else // HIGH_SPEED_DEVICE + +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Init_EndPoint + * + * @brief The function initializes an endpoint + * + * @param controller_ID : Controller ID + * @param ep_ptr : Pointer to EndPoint Structures + * @param flag : Zero Termination + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_INIT_FAILED : When Error + ****************************************************************************** + * + * This function initializes an endpoint and the Bufffer Descriptor Table + * entry associated with it. Incase the input parameters are invalid it will + * return USBERR_EP_INIT_FAILED error. + * + *****************************************************************************/ +uint_8 USB_DCI_Init_EndPoint ( + uint_8 controller_ID,/* [IN] Controller ID */ + USB_EP_STRUCT_PTR ep_ptr, /* [IN] Pointer to Endpoint structure, + (endpoint number, + endpoint type, + endpoint direction, + max packet size) */ + boolean flag /* [IN] Zero Termination */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_8 bdtmap_index; + uint_8 bdtelem_index; + uint_8 ep_num = ep_ptr->ep_num; + uint_8 direction = ep_ptr->direction; + uint_32 ep_ctrl[2] = {EP_OUT, EP_IN}; + P_BUFF_DSC temp; + P_BDT_ELEM bdt_elem; + UNUSED(controller_ID); + + /* if the max packet size is greater than the max buffer size */ + if(ep_ptr->size > MAX_EP_BUFFER_SIZE) + { + ep_ptr->size = MAX_EP_BUFFER_SIZE; + } + + /* Get the bdt index correspoding to the endpoint */ + bdtmap_index = USB_DCI_Get_BDT_Index(ep_num, direction, + USB_RAM_EVEN_BUFFER); + bdtelem_index = (uint_8)TRANSFER_INDEX(bdtmap_index); + + /* + incase the bdtmap_index is invalid + or already initialised return with an error + */ + if((bdtmap_index == INVALID_BDT_INDEX) || + (g_bdt_elem[bdtelem_index].len != (uint_16)UNINITIALISED_VAL) || + (ep_ptr->type > USB_INTERRUPT_PIPE) || + (ep_ptr->direction > USB_SEND)) + { + return USBERR_EP_INIT_FAILED; + } + + bdt_elem = &g_bdt_elem[bdtelem_index]; + /* Reset Handler resets bdtmap_index to UNINITIALISED_VAL */ + if(bdt_elem->bdtmap_index == (uint_8)UNINITIALISED_VAL) + { + bdt_elem->bdtmap_index = 0; + } + + /* update bdt element structure */ + bdt_elem->len = (uint_16)ep_ptr->size; + bdt_elem->flag = flag; + /* preserving even/odd buffer bit */ + bdt_elem->bdtmap_index &= 0x01; + bdt_elem->bdtmap_index |= ((direction << 1) | (ep_num << 2)); + bdt_elem->addr = g_bdt_address; + bdt_elem->type = ep_ptr->type; + bdt_elem->direction = direction; + + temp = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + + /* Update BDTMAP for endpoint's EVEN Buffer */ + temp->cnt = SWAP16((uint_16)ep_ptr->size); + temp->addr = SWAP32(g_bdt_address); + temp->Stat._byte = (_CPU | _DATA0 | _DTS); + + /* Update BDTMAP for endpoint's ODD Buffer */ + temp = &g_bdtmap->ep_dsc[(uint8)((bdt_elem->bdtmap_index) ^ 1)]; + + temp->cnt = SWAP16((uint_16)ep_ptr->size); + temp->addr = SWAP32(g_bdt_address); + temp->Stat._byte = (_CPU | _DATA1 | _DTS); + + /* update the buffer address for the next endpoint */ + g_bdt_address += ep_ptr->size; + + if(direction == USB_RECV) + { + /* + For Recv Endpoints + Give SIE Control to DATA0 + */ + temp = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + temp->Stat._byte |= _SIE; + } + + /* enable handshake for Non-Isochronous Endpoints */ + ep_ctrl[direction] |= ((ep_ptr->type != USB_ISOCHRONOUS_PIPE) ? + HSHK_EN:0x00); + /* set the EndPoint Control MCU Register*/ + *((&USB0_ENDPT0) + (4 * ep_num)) |= ep_ctrl[direction]; +#else /* HIGH_SPEED_DEVICE */ + unsigned char mult; + + /* No need to initialize EP0 */ + if(ep_ptr->ep_num == CONTROL_ENDPOINT) + return USB_OK; + + switch (ep_ptr->type & 0x3) { + case EP_TRANSFER_TYPE_CONTROL: + case EP_TRANSFER_TYPE_BULK: + case EP_TRANSFER_TYPE_INTERRUPT: + mult = 0; + break; + case EP_TRANSFER_TYPE_ISOCHRONOUS: + /* Calculate the ISO transfer High-Bandwidth Pipe Multiplier + * The ISO endpoints, must set Mult 1, 2, 3 for high speed + * and only 1 for full speed + */ +#ifdef ULPI_FORCE_FULLSPEED + mult = 1; +#else + mult = (unsigned char)(1 + (((ep_ptr->size) >> 11) & 0x03)); +#endif + } + + /* setup dQH */ + usbd_ep_qh_init(controller_ID, ep_ptr->ep_num, ep_ptr->direction, ep_ptr->size, flag, mult, 0xDEAD0001); + + /* enable endpoint */ + usbd_ep_setup(controller_ID, ep_ptr->ep_num, ep_ptr->direction, ep_ptr->type); +#endif /* HIGH_SPEED_DEVICE */ + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Cancel_Transfer + * + * @brief The function cancels any pending Transfers which ahve not been sent + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USBERR_NOT_SUPPORTED : Always + ****************************************************************************** + * This function just returns Error Code not supported + *****************************************************************************/ +uint_8 USB_DCI_Cancel_Transfer ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ +#if !HIGH_SPEED_DEVICE +#ifdef LONG_TRANSACTION + uint_8 status= USBERR_UNKNOWN_ERROR; + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + uint_8 bdtelem_index = (uint_8)TRANSFER_INDEX(bdt_index); + UNUSED(handle); + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + P_BDT_ELEM bdt_elem = &g_bdt_elem[bdtelem_index]; + P_BUFF_DSC buffer_dsc = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index]; + P_BUFF_DSC buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_elem->bdtmap_index ^ 1]; + /* Clear SIE Control Bit for both buffers*/ + buffer_dsc->Stat._byte &= ~_SIE; + buffer_dsc_alt->Stat._byte &= ~_SIE; + bdt_elem->app_len = (USB_PACKET_SIZE)UNINITIALISED_VAL; + + status = USB_OK; + } + return status; +#else + return USBERR_NOT_SUPPORTED; +#endif +#else // HIGH_SPEED_DEVICE +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif + return USBERR_NOT_SUPPORTED; +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Deinit_EndPoint + * + * @brief The function de initializes an endpoint + * + * @param controller_ID : Controller ID + * @param ep_num : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USB_OK : When successfull + * USBERR_EP_DEINIT_FAILED : When unsuccessfull + ****************************************************************************** + * + * This function un-intializes the endpoint by clearing the corresponding + * endpoint control register and then clearing the bdt elem. + * + *****************************************************************************/ +uint_8 USB_DCI_Deinit_EndPoint ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (ep_num, direction, + USB_RAM_EVEN_BUFFER); + uint_8 bdtelem_index = (uint_8)TRANSFER_INDEX(bdt_index); + + /* in case the bdt_index is invalid*/ + if(bdt_index == INVALID_BDT_INDEX) + { + return USBERR_EP_DEINIT_FAILED; + } + USB_DCI_Cancel_Transfer(&controller_ID, ep_num, direction); + /* delete buffer space for both even and odd buffers */ + g_bdt_address -= (g_bdt_elem[bdtelem_index].len); + + /* Disable endpoint */ + *((&USB0_ENDPT0) + (4 * ep_num)) = EP_DISABLE; + + /* un-initialize the bdt_elem structure for this endpoint */ + g_bdt_elem[bdtelem_index].len = (uint_16)UNINITIALISED_VAL; + g_bdt_elem[bdtelem_index].addr = (uint_32)UNINITIALISED_VAL; +#else // HIGH SPEED + uint_32 reg; + + if(ep_num<1) + return USB_INVALID; + + // clear qhd + dqh_setup_t *dqh_word = (dqh_setup_t*)usbd_get_dqh(controller_ID, ep_num, direction); + memset((void *)dqh_word, 0, SIZE_OF_QHD); + + // clear endpoint register + reg = USBHS_EPCR(ep_num-1); + USBHS_EPCR(ep_num-1) &= ~reg; + + // flush endpoint Tx(IN) buffer + if(direction) + USBHS_EPFLUSH |= USBHS_EPFLUSH_FETB(ep_num-1); + // flush endpoint Rx(OUT) buffer + else + USBHS_EPFLUSH |= USBHS_EPFLUSH_FERB(ep_num-1); +#endif + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Stall_EndPoint + * + * @brief The function stalls an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function stalls the endpoint by setting Endpoint BDT + *****************************************************************************/ +void USB_DCI_Stall_EndPoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number to stall */ + uint_8 direction /* [IN] Direction to stall */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + bdt_index = bdt_elem->bdtmap_index; + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + (void)USB_DCI_Cancel_Transfer(handle, endpoint_number, direction); + + /* Stall endpoint */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte |= (_SIE | _BDTSTALL); + } +#else // HIGH SPEED + // check if it is control endpoint + if(endpoint_number == 0){ + // stall both directions + USBHS_EPCR0 |= USBHS_EPCR0_TXS_MASK|USBHS_EPCR0_RXS_MASK; + }else{ + + USBHS_EPCR(endpoint_number-1) |= direction?USBHS_EPCR0_TXS_MASK:USBHS_EPCR0_RXS_MASK; + } +#endif + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Unstall_EndPoint + * + * @brief The function unstalls an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function unstalls the endpoint by clearing Endpoint Control Register + * and BDT + *****************************************************************************/ +void USB_DCI_Unstall_EndPoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number to unstall */ + uint_8 direction /* [IN] Direction to unstall */ +) +{ +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + bdt_index = bdt_elem->bdtmap_index; + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + volatile ENDPT0STR *endpoint = (volatile ENDPT0STR*)(&USB0_ENDPT0 + (4 * endpoint_number)); + + /* Enable ENDPTx for non control endpoints */ + /* For Control Endpoint the default Value 0x0D */ + if(endpoint_number != CONTROL_ENDPOINT) + { + uint_8 endpt; + /* Enable handshaking for non isochronous endpoint */ + endpt = (uint_8)((bdt_elem->type != USB_ISOCHRONOUS_PIPE) ? + HSHK_EN:0); + /* + Enable the endpoint in the specified direction and disable + control tranfers (valid only in case the endpoint is + bidirectional) + */ + endpt |= (uint_8)(EP_CTL_DIS | + ((direction == USB_SEND)?EP_IN:EP_OUT)); + endpoint->Byte |= endpt; + } + /* Clear Endpoint Stall bit is endpoint control register */ + endpoint->Bits.EP_STALL = 0; + + /* Unstall endpoint by clearing stall bit in BDT */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte &= ~(_SIE | _BDTSTALL); + /* We Require DATA0 PID to be zero on unstall */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte = _DATA0; + if(direction == USB_RECV) + { + /* Initiate Next receive Transfer */ + USB_DCI_Recv_Data(handle, endpoint_number, NULL, 0); + } + } +#else + // todo //: Dieses To-do hatte kein Kommentar - ist das noch notwendig? (LH) + // This function unstalls the endpoint by clearing Endpoint Control Register + // and QH + if(endpoint_number == 0){ + // unstall both directions + USBHS_EPCR0 &= ~(direction ? USBHS_EPCR0_TXS_MASK:USBHS_EPCR0_RXS_MASK); + }else{ + USBHS_EPCR(endpoint_number-1) &= ~(direction?USBHS_EPCR_TXS_MASK:USBHS_EPCR_RXS_MASK); + } +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif +#endif + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Get_Setup_Data + * + * @brief The function copies Setup Packet from USB RAM to application buffer + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * + * @return None + * + ****************************************************************************** + * Copies setup packet from USB RAM to Application Buffer + *****************************************************************************/ +void USB_DCI_Get_Setup_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number for the transaction */ + uint_8_ptr buffer_ptr /* [IN] Pointer to the buffer into which to read data */ +) +{ + +#if !HIGH_SPEED_DEVICE + uint_8_ptr addr; + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_RECV, + USB_RAM_EVEN_BUFFER); + + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + UNUSED(handle); + bdt_index = bdt_elem->bdtmap_index; + + /* address correponding to the endpoint */ + addr = (uint_8_ptr)SWAP32(g_bdtmap->ep_dsc[bdt_index].addr); + + /* copy bdt buffer to application buffer */ + (void)memcpy(buffer_ptr, addr, USB_SETUP_PKT_SIZE); + return; +#else // HIGH SPEED +#if USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Get_Transfer_Status + * + * @brief The function retrieves the Transfer status of an endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USBERR_TR_FAILED : When unsuccessful + * USB_STATUS_IDLE : No transfer on endpoint + * USB_STATUS_DISABLED : endpoint is disabled + * USB_STATUS_STALLED : endpoint is stalled + * USB_STATUS_TRANSFER_IN_PROGRESS : When SIE has control of BDT + ****************************************************************************** + * + * This function retrieves the transfer status of the endpoint by checking the + * BDT as well as the endpoint control register + * + *****************************************************************************/ +uint_8 USB_DCI_Get_Transfer_Status ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ + uint_8 status = USB_STATUS_DISABLED; + +#if !HIGH_SPEED_DEVICE + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, direction, + USB_RAM_EVEN_BUFFER); + UNUSED(handle); + + /* Check for valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + uint_8 ep_control = (uint_8)(*((&USB0_ENDPT0)+4*endpoint_number)); + + status = USB_STATUS_IDLE; + + /* Check for direction in endpoint control register */ + if((ep_control & (EP_IN|EP_OUT)) == EP_DISABLE) + { + status = USB_STATUS_DISABLED; + } + /* Check for stall bit in endpoint control register */ + else if((ep_control & EPCTL_STALL) == EPCTL_STALL) + { + status = USB_STATUS_STALLED ; + } + /* Check whether SIE has control of BDT */ + else if((g_bdtmap->ep_dsc[bdt_index].Stat.SieCtlBit.own == 1) + || (g_bdtmap->ep_dsc[bdt_index ^ 1].Stat.SieCtlBit.own == 1)) + { + status = USB_STATUS_TRANSFER_IN_PROGRESS; + } + } +#else +#if USART_DEBUG + printf("%s, ep_num is %d\n", __func__, endpoint_number); +#endif /* USART_DEBUG */ + status = USB_OK; +#endif /* HIGH_SPEED_DEVICE */ + return status; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Clear_DATA0_Endpoint + * + * @brief The function clear the DATA0/1 bit + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return None + * + ****************************************************************************** + * This function clear the DATA0/1 bit + *****************************************************************************/ +void USB_DCI_Clear_DATA0_Endpoint ( + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Endpoint direction */ +) +{ + +#if !HIGH_SPEED_DEVICE + + uint_8 bdt_index = USB_DCI_Validate_Param(endpoint_number, direction, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + bdt_index = bdt_elem->bdtmap_index; + + /*Check for a valid bdt index */ + if(bdt_index != INVALID_BDT_INDEX) + { + //ENDPT0STR *endpoint = (ENDPT0STR*)(&USB0_ENDPT0 + (4 * endpoint_number)); /* << EST not used */ + g_bdtmap->ep_dsc[bdt_index].Stat._byte = _DATA0; + } + return; +#else // HIGH SPEED +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Recv_Data + * + * @brief The function retrieves data received on an RECV endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * @param size : Size of the buffer + * + * @return status + * USB_OK : When successful + * USBERR_RX_FAILED : When unsuccessful + ****************************************************************************** + * This function retrieves data received data on a RECV endpoint by copying it + * from USB RAM to application buffer + *****************************************************************************/ +uint_8 USB_DCI_Recv_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number for the transaction */ + uint8_ptr buffer_ptr, /* [OUT] Pointer to the buffer into which to receive data */ + uint_32 size /* [IN] Number of bytes to receive */ +) +{ + uint_8 status = USBERR_RX_FAILED; +#if !HIGH_SPEED_DEVICE + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_RECV, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + UNUSED(handle); + + /* For selecting even/odd buffer */ + bdt_index = bdt_elem->bdtmap_index; + + if(bdt_index != INVALID_BDT_INDEX) + { + P_BUFF_DSC buffer_dsc = &g_bdtmap->ep_dsc[bdt_index ^ 1]; + P_BUFF_DSC buffer_dsc_alt = NULL; + + /* Check for valid bdt index */ + if(bdt_elem->len != (uint_16)UNINITIALISED_VAL) + { + /* Does MCU owns it */ + if(buffer_dsc->Stat.SieCtlBit.own == FALSE) + { + if(size == 0) + { + /* + Give control to the other buffer to recv the next + packet + */ + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt->cnt = SWAP16(bdt_elem->len); + buffer_dsc_alt->addr = SWAP32(bdt_elem->addr); + + /* Give the ownership to SIE and TOGGLE DATA BIT */ + buffer_dsc_alt->Stat._byte = (uint_8)( + (buffer_dsc_alt->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + return USB_OK; + } + /* adjust size based on the input at the init endpoint */ +#ifdef LONG_RECEIVE_TRANSACTION + /* Initialise transfer */ + bdt_elem->app_len = size; + bdt_elem->app_buffer = buffer_ptr; +#endif + if(size > bdt_elem->len) + { + size = bdt_elem->len; + } + +#ifdef LONG_RECEIVE_TRANSACTION + bdt_elem->curr_offset = 0; +#endif + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt->cnt = SWAP16(size); + buffer_dsc_alt->addr = SWAP32((uint_32)buffer_ptr); + buffer_dsc_alt->Stat._byte = (uint_8)( + (buffer_dsc_alt->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + status = USB_OK; + } + } + } + return status; +#else + if(endpoint_number != 0) + { + status = usbd_receive_data_epxout(0, (unsigned int)buffer_ptr, endpoint_number, size); + } + else + status = usbd_receive_data_ep0out(0, (unsigned int)buffer_ptr, size); + + if(status != USB_SUCCESS) + { + return USBERR_RX_FAILED; + } + else + { + return USB_OK; + } +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Send_Data + * + * @brief The function configures Controller to send data on an SEND endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param buffer_ptr : Application buffer pointer + * @param size : Size of the buffer + * + * @return status + * USB_OK : When successfull + * USBERR_TX_FAILED : When unsuccessfull + ****************************************************************************** + * This function configures Controller to send data on a SEND endpoint by + * setting the BDT to send data. + *****************************************************************************/ +uint_8 USB_DCI_Send_Data ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint8_ptr buffer_ptr, /* [IN] Application buffer pointer */ + uint_32 size /* [IN] Size of the buffer */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_8 status = USBERR_TX_FAILED; + P_BUFF_DSC buffer_dsc; + + /* validate params and get the bdt index */ + uint_8 bdt_index = USB_DCI_Validate_Param (endpoint_number, USB_SEND, USB_RAM_EVEN_BUFFER); + P_BDT_ELEM bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + UNUSED(handle); + + if(bdt_index == INVALID_BDT_INDEX) + return USBERR_TX_FAILED; + + /* Send Data After Toggling Buffer */ + bdt_index = (uint_8)bdt_elem->bdtmap_index; + + buffer_dsc = &g_bdtmap->ep_dsc[bdt_index]; + + /* Does MCU owns it and it is not stalled */ + if(!((buffer_dsc->Stat.SieCtlBit.own) ||/* For MCU: own is 0 */ + (*(&USB0_ENDPT0 + (endpoint_number * 4)) & ENDPT_EP_STALL_MASK))) + { + /* Now configure buffer_dsc->addr and buffer_dsc->cnt */ +#ifdef LONG_SEND_TRANSACTION + /* Initialize transfer */ + bdt_elem->app_len = size; + bdt_elem->app_buffer = buffer_ptr; + bdt_elem->curr_offset = 0; + + /* Prepare for send */ + USB_DCI_Prepare_Send_Data(buffer_dsc, bdt_elem); +#else + buffer_dsc->addr = SWAP32(buffer_ptr); + + /* Adjust size based on the input at the init endpoint */ + if((uint_16)size > bdt_elem->len) + { + buffer_dsc->cnt = SWAP16(bdt_elem->len); + } + else + { + buffer_dsc->cnt = SWAP16((uint_16)size); + } +#endif + if(endpoint_number == CONTROL_ENDPOINT) + { + /* Set up the control endpoint bdt for next packet */ + buffer_dsc->Stat._byte = (_SIE | _DATA1 | _DTS); + } + else + { + buffer_dsc->Stat._byte = (uint_8)( + (buffer_dsc->Stat.McuCtlBit.data << 6) | + _SIE | _DTS); + } + + status = USB_OK; + } /* Does MCU own IN BDT */ + return status; +#else // HIGH SPEED + usb_status_t status; + + if(endpoint_number != 0) { + status = usbd_send_data_epxin(0, (unsigned int)buffer_ptr, endpoint_number, size); + } + + /* Send descriptor - Data Phase */ + //zlt is false=>not zero length packet, send dev descriptor to host. + else + status = usbd_send_data_ep0in(0, (unsigned int)buffer_ptr, size, 0); + + if(status != USB_SUCCESS) + return USBERR_TX_FAILED; + + return USB_OK; +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Set_Address + * + * @brief The function configures Controller to send data on an SEND endpoint + * + * @param handle : USB Device handle + * @param address : Controller Address + * + * @return None + * + ****************************************************************************** + * Assigns the Address to the Controller + *****************************************************************************/ +void USB_DCI_Set_Address ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 address /* [IN] Address of the USB device */ +) +{ + + UNUSED(handle); + + /* set the address */ +#if !HIGH_SPEED_DEVICE + USB0_ADDR = address; +#else + USBHS_DEVICEADDR = USBHS_DEVICEADDR_USBADR(address); +#endif + + _usb_device_set_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + USB_STATE_ADDRESS); + return; +} + +/**************************************************************************//*! + * + * @name USB_DCI_Shutdown + * + * @brief The function shuts down the controller + * + * @param handle : USB Device handle + * + * @return None + * + ****************************************************************************** + * Resets USB Device Controller + *****************************************************************************/ +void USB_DCI_Shutdown ( + _usb_device_handle handle /* [IN] USB Device handle */ +) +{ + UNUSED(handle); +#if !HIGH_SPEED_DEVICE + /* Reset the Control Register */ + USB0_CTL = 0; + /* Initiate Reset in the USB Control0 Register */ + #ifndef OTG_BUILD + + USB0_USBTRC0 = _USBRESET; + #endif + + _usb_device_set_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + USB_STATE_UNKNOWN); + return; +#else +#if USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_DCI_Assert_Resume + * + * @brief The function makes the Controller start USB RESUME signaling + * + * @param handle : USB Device handle + * + * @return None + * + ****************************************************************************** + * + * This function starts RESUME signalling and then stops it after some delay. + * In this delay make sure that COP is reset. + * + *****************************************************************************/ +void USB_DCI_Assert_Resume ( + _usb_device_handle handle /* [IN] USB Device handle */ +) +{ +#if !HIGH_SPEED_DEVICE + uint_16 delay_count; + + /* Clear SUSP Bit from USB_CTRL */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + + (void)handle; + + /* Reset Low Power RESUME enable */ + USB0_USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + + USB_DCI_WAKEUP + + USB0_CTL |= USB_CTL_RESUME_MASK; /* Start RESUME signaling and make SUSPEND bit 0*/ + + delay_count = ASSERT_RESUME_DELAY_COUNT; /* Set RESUME line for 1-15 ms*/ + + do + { + delay_count--; + Watchdog_Reset(); /* Reset the COP */ + }while(delay_count); + + USB0_CTL &= ~USB_CTL_RESUME_MASK; /* Stop RESUME signalling */ + + return; +#else +#ifdef USART_DEBUG + printf("%s\n", __func__); +#endif /* USART_DEBUG */ +#endif +} + +/**************************************************************************//*! + * + * @name USB_Bus_Token_Cpl_Handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param stat : BDT stat byte + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +#if !HIGH_SPEED_DEVICE +void USB_Bus_Token_Cpl_Handler ( + uint_8 stat, /* [IN] Value of STAT register */ + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + uint_8 bdt_index = 0 ; + P_BUFF_DSC buffer_dsc = NULL; + P_BUFF_DSC buffer_dsc_alt = NULL;/* stores data of alternate buffer */ + P_BDT_ELEM bdt_elem = NULL; + boolean odd = (boolean)((stat & 0x04) >> 2); + + /* Get the direction from STAT register */ + event->direction = (uint_8)((stat & ENDPOINT_DIRECTION_MASK) >> + ENDPOINT_DIRECTION_SHIFT); + + + /* Get bdt index corresponding to endpoint number and direction */ + bdt_index = USB_DCI_Get_BDT_Index(event->ep_num,event->direction, odd); + + buffer_dsc = &g_bdtmap->ep_dsc[bdt_index]; + buffer_dsc_alt = &g_bdtmap->ep_dsc[bdt_index ^ 1]; + + bdt_elem = &g_bdt_elem[TRANSFER_INDEX(bdt_index)]; + + /* Get address from BDT */ + event->buffer_ptr = (uint_8_ptr)SWAP32(buffer_dsc->addr); + + /* Get len from BDT */ + event->len = SWAP16(buffer_dsc->cnt); + + /* Prepare for Next USB Transaction */ + bdt_index = (uint_8)(bdt_elem->bdtmap_index ^ 1); + bdt_elem->bdtmap_index = bdt_index; + + /* Toggle Data PID*/ + buffer_dsc_alt->Stat._byte = (uint_8)((buffer_dsc->Stat.McuCtlBit.data ^ 1) << 6); + + if(event->direction == USB_SEND) + { + if(event->ep_num == CONTROL_ENDPOINT) + { + /* for Control Endpoint */ + /* For Transfer Direction Host to Device */ + if(g_trf_direction == USB_RECV) + { + /* + Enters here for first time after Set_Address TRANSFER + Completed + */ + /* make Transfer Direction UNKNOWN */ + g_trf_direction = USB_TRF_UNKNOWN; + /* Cancel any pending Transfers on RECV Control Endpoint*/ + USB_DCI_Cancel_Transfer(&(event->controller_ID), (uint_8)CONTROL_ENDPOINT, + (uint_8)USB_RECV); + /* We Require DATA0 PID for Setup Token */ + buffer_dsc_alt->Stat._byte = _DATA0; + /* Prepare for Next SETUP PACKET Receive */ + USB_DCI_Recv_Data(&(event->controller_ID), + CONTROL_ENDPOINT, + NULL,0); + + } + }/* ep_num is CONTROL ENDPOINT */ + +#ifdef LONG_SEND_TRANSACTION + if( (g_trf_direction == USB_SEND) || + (event->ep_num != CONTROL_ENDPOINT) ) + { + /* update the request */ + bdt_elem->curr_offset += event->len; + /* + Initiate next USB SEND if: + 1. More Data is still pending OR + 2. Send Data == Endpoint Size AND + 3. Zero Termination Flag is TRUE + */ + if((bdt_elem->app_len > bdt_elem->curr_offset) || + (((uint_8)event->len == bdt_elem->len) && (bdt_elem->flag == TRUE)) + ) + { + /* send next Req */ + USB_DCI_Prepare_Send_Data(buffer_dsc_alt, bdt_elem); + + /* give the ownership to SIE and TOGGLE DATA BIT */ + buffer_dsc_alt->Stat._byte = (uint_8)( + ((buffer_dsc_alt->Stat.McuCtlBit.data) << 6) | + _SIE | _DTS);; + return; + } + else + { + event->buffer_ptr = bdt_elem->app_buffer; + event->len = bdt_elem->curr_offset; + } + } +#endif + }/* End of SEND loop */ + else /* direction IS USB_RECV */ + { + if(event->ep_num == CONTROL_ENDPOINT) + { + /* for Control Endpoint */ + if(buffer_dsc->Stat.RecPid.pid == USB_SETUP_TOKEN) + { + /* set setup phase */ + event->setup = TRUE; + /* Transfer direction of next packet */ + g_trf_direction = (uint_8)((uint_8) + (event->buffer_ptr[0]) >> 7); + } + else if(g_trf_direction == USB_SEND) + { + /* make Transfer Direction UNKNOWN */ + g_trf_direction = USB_TRF_UNKNOWN; + /* Cancel any pending Transfers on SEND Control Endpoint*/ + USB_DCI_Cancel_Transfer(&(event->controller_ID), (uint_8)CONTROL_ENDPOINT, + (uint_8)USB_SEND); + /* We Require DATA0 PID for Setup Token */ + buffer_dsc_alt->Stat._byte = _DATA0; + /* Prepare for Next SETUP PACKET Receive */ + USB_DCI_Recv_Data(&(event->controller_ID), + CONTROL_ENDPOINT, + NULL,0); + } + } /* ep_num is CONTROL ENDPOINT */ + +#ifdef LONG_RECEIVE_TRANSACTION + /* For NON CONTROL ENDPOINT only */ + if(bdt_elem->app_len != (USB_PACKET_SIZE)UNINITIALISED_VAL) + { + /* on control endpoint the data is only 8 bytes */ + USB_PACKET_SIZE size = event->len; + bdt_elem->curr_offset += size; + + /* + Initiate next USB RECV if: + 1. More Data is still pending OR + 2. Received Data == Endpoint Size AND + 3. Zero Termination Flag is TRUE + */ + if( + ( (size == bdt_elem->len) && + (bdt_elem->app_len > bdt_elem->curr_offset) + ) || + ( (bdt_elem->app_len)&& + (!(bdt_elem->app_len % bdt_elem->len)) && + (bdt_elem->flag == TRUE) + ) + ) + { + /* send next IO */ + uint_16 count; + count = (uint_16)(((bdt_elem->app_len - bdt_elem->curr_offset) + > bdt_elem->len) ? bdt_elem->len : + (bdt_elem->app_len - bdt_elem->curr_offset)); + if(count == 0) + { + /* For Zero byte Packet Receive */ + buffer_dsc_alt->addr = SWAP32(bdt_elem->addr); + buffer_dsc_alt->cnt = 0; + } + else + { + buffer_dsc_alt->addr = SWAP32((uint_32)(bdt_elem->app_buffer + bdt_elem->curr_offset)); + buffer_dsc_alt->cnt = SWAP16(count); + } + + /* give the ownership to SIE and Toggle DATA bit*/ + buffer_dsc_alt->Stat._byte = (uint_8)(( + (buffer_dsc_alt->Stat.McuCtlBit.data) << 6) | + _SIE | _DTS); + return; + } + else /* request completed */ + { + /* populate buffer structure */ + event->buffer_ptr = bdt_elem->app_buffer; + event->len = bdt_elem->curr_offset; + bdt_elem->app_len = (USB_PACKET_SIZE)UNINITIALISED_VAL; + } + } +#endif + } /* End of RECV loop */ + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); + + return; +} +#endif // HIGH_SPEED_DEVICE + +#if HIGH_SPEED_DEVICE +/**************************************************************************//*! + * */ +uint_32 sof_counter = 0; +static uint_32 micro_sof_counter = 0; +void USBHS_ISR(void){ + uint_32 usbsts; + uint_32 reg; + USB_DEV_EVENT_STRUCT event; + + // get interrupt status + reg = USBHS_USBINTR; + usbsts = USBHS_USBSTS & reg; + + // clear interrupt status + USBHS_USBSTS |= usbsts; + + // initialize event structure + event.controller_ID = g_dci_controller_Id; + event.setup = FALSE; + event.buffer_ptr = NULL; + event.len = 0; + event.direction = USB_RECV; + event.errors = NO_ERRORS; + event.ep_num = (uint_8)UNINITIALISED_VAL; + + // handle SOF + if(usbsts & USBHS_USBSTS_SRI_MASK){ + //USBHS_USBSTS |= USBHS_USBSTS_SRI_MASK; +#ifdef ULPI_FORCE_FULLSPEED + sof_counter++; +#else + if(++micro_sof_counter == 8){ + //sof_counter++; + //micro_sof_counter = 0; + } +#endif + } + + // handle Suspend + if(usbsts & USBHS_USBSTS_SLI_MASK){ + USB_Device_Call_Service(USB_SERVICE_SUSPEND, &event); + return; + } + + // handle Bus Reset + if(usbsts & USBHS_USBSTS_URI_MASK){ + // handle reset + USB_Bus_Reset_Handler(); + + // notify device layer + USB_Device_Call_Service(USB_SERVICE_BUS_RESET, &event); + return; + } + + // handle Transaction Complete + if(usbsts & USBHS_USBSTS_UI_MASK){ + if(!USBHS_EPSETUPSR && !USBHS_EPCOMPLETE){ +#ifdef USART_DEBUG + printf("Warning: unexpected UI interrupt\n"); +#endif /* USART_DEBUG */ + } + + // Handle dTD complete interrupt. + // Must process EP complete events first, because setup complete events + // trigger stack to re-prime endpoints. + if(USBHS_EPCOMPLETE) + usbd_ep_complete_handler(&event); + + // Handle setup compete packet interrupt + if(USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(1)) + usbd_setup_packet_handler(&event); + + // + if( (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(2))|| + (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(4))|| + (USBHS_EPSETUPSR & USBHS_EPSETUPSR_EPSETUPSTAT(8))){ +#if USART_DEBUG + printf(""); +#endif /* USART_DEBUG */ + } + } + + // handle Port Change + if(usbsts & USBHS_USBSTS_PCI_MASK){ + usbd_port_change(&event); + } + + // handle USB Error + if(usbsts & USBHS_USBSTS_UEI_MASK){ +#ifdef USART_DEBUG + printf("USBHS: Error\n"); +#endif + // Notify Device Layer of ERROR Event to error service + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + } + + // handle USB System Error + if(usbsts & USBHS_USBSTS_SEI_MASK){ +#ifdef USART_DEBUG + printf("USBHS: System Error\n"); +#endif + // Notify Device Layer of ERROR Event to error service + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + } + +} +#endif // HIGH_SPEED_DEVICE + +/**************************************************************************//*! + * + * @name USB_ISR + * + * @brief The function handles USB interrupts on the bus. + * + * @param None + * + * @return None + * + ****************************************************************************** + * This function is hooked onto interrupt 69 and handles the USB interrupts. + * After handling the interrupt it calls the Device Layer to notify it about + * the event. + *****************************************************************************/ +#if !HIGH_SPEED_DEVICE +void USB_ISR(void) +{ + /* Which interrupt occured and also was enabled */ + uint_8 v1 = USB0_ISTAT; + uint_8 v2 = USB0_INTEN; + uint_8 intr_stat = (uint_8)(v1 & v2); + uint_8 stat = (uint_8)USB0_STAT; + USB_DEV_EVENT_STRUCT event; + uint_8 dev_state = USB_STATUS_UNKNOWN; + + /* initialize event structure */ + event.controller_ID = g_dci_controller_Id; + event.setup = FALSE; + event.buffer_ptr = NULL; + event.len = 0; + event.direction = USB_RECV; + event.errors = NO_ERRORS; + + event.ep_num = (uint_8)UNINITIALISED_VAL; + + /* Get the device state from the Device Layer */ + (void)_usb_device_get_status(&g_dci_controller_Id, USB_STATUS_DEVICE_STATE, + &dev_state); + + /* if current device state is SUSPEND and Low Power Resume Flag set */ + if((USB0_USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) && (dev_state == USB_STATE_SUSPEND)) + { + /* Clear SUSP Bit from USB_CTRL */ + USB0_USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + + /* Reset Low Power RESUME enable */ + USB0_USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + } + + /* SOF received */ + if(SOF_TOKEN_FLAG(intr_stat)) + { + uint_16 sof_count; + uint_16 tmp1, tmp2, tmp3; + tmp1 = USB0_FRMNUMH; + tmp2 = FRAME_HIGH_BYTE_SHIFT; + tmp3 = USB0_FRMNUML; + /* Clear SOF Interrupt */ + USB0_ISTAT = USB_ISTAT_SOFTOK_MASK; + sof_count = (uint_16)((tmp1 << tmp2) | tmp3); + /*address of Lower byte of Frame number*/ + event.buffer_ptr = (uint_8_ptr)(&sof_count); + /* Notify Device Layer of SOF Event */ + (void)USB_Device_Call_Service(USB_SERVICE_SOF, &event); + +#ifdef USE_FEEDBACK_ENDPOINT + // set feedback rate info number + if(gNrSamples!=0) + feedback_data = gNrSamples; + gNrSamples = 0; +#endif + } + + if(BUS_RESET_FLAG(intr_stat)) + { + /* Clear Reset Flag */ + USB0_ISTAT = USB_ISTAT_USBRST_MASK; + + /* Handle RESET Interrupt */ + USB_Bus_Reset_Handler(); + + /* Notify Device Layer of RESET Event */ + (void)USB_Device_Call_Service(USB_SERVICE_BUS_RESET, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + + /* No need to process other interrupts */ + return; + } + + if(TOKEN_COMPL_FLAG(intr_stat)) + { + /* Clear TOKEN Interrupt */ + USB0_ISTAT = USB_ISTAT_TOKDNE_MASK; + + event.ep_num = (uint_8)((stat & ENDPOINT_NUMBER_MASK) >> + ENDPOINT_NUMBER_SHIFT); + + USB_Bus_Token_Cpl_Handler(stat, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + + if(ERROR_FLAG(intr_stat)) + { + /* Clear ERROR Interrupt */ + USB0_ISTAT = USB_ISTAT_ERROR_MASK; + + v1 = USB0_ERRSTAT; + v2 = USB0_ERREN; + event.errors = (uint_8)(v1 & v2); + + /* Notify Device Layer of ERROR Event to error service */ + (void)USB_Device_Call_Service(USB_SERVICE_ERROR, &event); + + USB0_ERRSTAT = ERR_STAT_CLEAR_ALL; /*clear all errors*/ + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + + if(SLEEP_FLAG(intr_stat)) + { + /* Clear RESUME Interrupt if Pending */ + USB0_ISTAT = USB_ISTAT_RESUME_MASK; + + /* Clear SLEEP Interrupt */ + USB0_ISTAT = USB_ISTAT_SLEEP_MASK; + + /* Notify Device Layer of SLEEP Event */ + (void)USB_Device_Call_Service(USB_SERVICE_SLEEP, &event); + + /* Set Low Power RESUME enable */ + USB0_USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; + + /* Set SUSP Bit in USB_CTRL */ + USB0_USBCTRL |= USB_USBCTRL_SUSP_MASK; + + /* Enable RESUME Interrupt */ + USB0_INTEN |= USB_INTEN_RESUMEEN_MASK; +#ifdef USB_LOWPOWERMODE + /* Enter Stop3 Mode*/ + Enter_StopMode(STOP_MODE3); +#endif + } + + if(RESUME_FLAG(intr_stat)) + { + /* Clear RESUME Interrupt */ + USB0_ISTAT = USB_ISTAT_RESUME_MASK; + + /* Notify Device Layer of RESUME Event */ + (void)USB_Device_Call_Service(USB_SERVICE_RESUME, &event); + + /* Disable RESUME Interrupt */ + USB0_INTEN &= ~USB_INTEN_RESUMEEN_MASK; + } + + if(STALL_FLAG(intr_stat)) + { + uint_8 endp_status; + event.ep_num = (uint_8)UNINITIALISED_VAL; + + /* If Control Endpoint is stalled then unstall it. + For other endpoints host issues clear endpoint feature request + to unstall them */ + + /* Get Control Endpoint Status*/ + (void)_usb_device_get_status(&(event.controller_ID), + (USB_STATUS_ENDPOINT|CONTROL_ENDPOINT), + &endp_status); + if(endp_status == USB_STATUS_STALLED) + { + event.ep_num = CONTROL_ENDPOINT; + event.direction = USB_SEND; + } + + /* Clear STALL Interrupt */ + USB0_ISTAT = USB_ISTAT_STALL_MASK; + + /* Notify Device Layer of STALL Event */ + (void)USB_Device_Call_Service(USB_SERVICE_STALL, &event); + + /* Clearing this bit allows the SIE to continue token processing + and clear suspend condition */ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + } + return; +} +#endif // HIGH_SPEED_DEVICE + +/**************************************************************************//*! + * + * @name Clear_Mem + * + * @brief The function clears memory starting from start_addr till count bytes + * + * @param start_addr : Buffer Start address + * @param count : Count of Bytes + * @param val : Value to be set + * + * @return None + ****************************************************************************** + * This function is an implementation of memset + *****************************************************************************/ +void Clear_Mem ( + uint_8_ptr start_addr, /* [OUT] Buffer Start address */ + uint_32 count, /* [IN] Count of Bytes */ + uint_8 val /* [IN] Value to be set */ +) +{ + (void)memset(start_addr, val, count); + return; +} + +#ifdef USB_LOWPOWERMODE +/**************************************************************************//*! + * + * @name Enter_StopMode + * + * @brief The function configures STOP Mode + * + * @param stop_mode : STOP MODE to be entered + * + * @return None + ****************************************************************************** + * This function configures different STOP MODES defined by the controller. + * Used to put controller into low power mode. Only STOP MODE 3 is implemented + *****************************************************************************/ +static void Enter_StopMode(STOP_MODE stop_mode) +{ + switch(stop_mode) + { + case STOP_MODE1: + /* + We enter Default Stop Mode + */ + break; + case STOP_MODE2: + /* Save IO Pin Status in a global variable + IO Pin Status is to be restored at POR. + Check if PPDC + */ + /* Set PPDC */ + break; + case STOP_MODE3: + /* Clear PPDC */ + SPMSC2_PPDC = 0; + /* Disable Low Voltage Detect */ + SPMSC1_LVDSE = 0; + break; + case STOP_MODE4: + break; + } + /* Enter STOP Mode*/ + _Stop; +} + +#endif + + +/* HIGH_SPEED_DEVICE */ +#if HIGH_SPEED_DEVICE + +extern void delay(int delayloop); + +static uint_8 K70_ULPI_SetDeviceMode(uint_8 controller_ID){ + // device init + unsigned int count = 10000; + unsigned int reg; + + // reset usb controller + reg = USBHS_USBCMD; + reg |= USBHS_USBCMD_RST_MASK; + USBHS_USBCMD = reg; + // check if reset done, port is enabled + while(USBHS_USBCMD & USBHS_USBCMD_RST_MASK); + + // enable USB work in device mode + reg = USBHS_USBMODE; + reg &= ~0x3; + reg |= 0x2; // device mode + + // Disable Setup Lockout by writing '1' to SLOM in USBMODE + reg &= ~(USBHS_USBMODE_SDIS_MASK); + // Setup Lockouts Off + reg |= USBHS_USBMODE_SLOM_MASK; + // this register can only be written once after reset + USBHS_USBMODE = reg; + + // wait for mode to be set + while(((USBHS_USBMODE & 0x3) != 0x2) && (--count)) ; + + if(count == 0) + return USBERR_INIT_FAILED; //timeout + +#ifdef ULPI_FORCE_FULLSPEED + reg = USBHS_PORTSC1; + reg |= USBHS_PORTSC1_PFSC_MASK; + USBHS_PORTSC1 = reg; /* force full speed */ +#endif + + // Configure ENDPOINTLISTADDR Pointer + USBHS_EPLISTADDR = (unsigned int)g_usbd_qh_buf & 0xFFFFF800; + + // Set OTG termination, controls the pulldown on DM + reg = USBHS_OTGSC; + reg |= (0x1 << 3); + USBHS_OTGSC = reg; + + // clear the usb intr status + USBHS_USBSTS = 0xFFFFFFFF; + + return USB_OK; +} + +/*! + * Initialize the USB device endpoint queue head structure + */ +static void usbd_ep_qh_init(uint_8 controller_ID, + unsigned char endpt_number, unsigned char direction, unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult, uint_32 next_dtd) +{ + struct dqh_t qhead; + unsigned int total_bytes; + + memset((void*)&qhead, 0, sizeof(qhead)); + + // Initialize device queue head in system memory + if(endpt_number == CONTROL_ENDPOINT) + total_bytes = 8; // 8 bytes for the 1st setup packet + else + total_bytes = max_pkt_len; + qhead.dqh_base = usbd_get_dqh(controller_ID, endpt_number, direction); + qhead.next_link_ptr = next_dtd; + qhead.zlt = zlt; + qhead.mps = max_pkt_len; + qhead.ios = IOS_SET; + // todo LOW CHECK 2: check this + qhead.terminate = TERMINATE; + qhead.total_bytes = total_bytes; + qhead.ioc = IOC_SET; + qhead.status = NO_STATUS; + qhead.mult = mult; + qhead.buffer_ptr0 = 0; + qhead.current_offset = 0; + qhead.buffer_ptr1 = 0; + qhead.buffer_ptr2 = 0; + qhead.buffer_ptr3 = 0; + qhead.buffer_ptr4 = 0; + + /* Set Device Queue Head */ + usbd_setup_qhead(&qhead); + // Initialize TD list to empty + g_usbd_qh_tail[(endpt_number * 2) + direction] = NULL; +} + +/*! + * Setup the queue head for the USB device + * + * @param qhead The queue head data structure that contains the necessary configuration data + */ +static void usbd_setup_qhead(struct dqh_t *qhead) +{ + volatile struct dqh_setup_t *dqh_word = (volatile struct dqh_setup_t *)qhead->dqh_base; + + // 0x0 + // Bit31:30 Mult; Bit29 zlt; Bit26:16 mps; Bit15 ios + dqh_word->dqh_word0 = + (((uint_32)((qhead->zlt) << 29)) | + ((uint_32)((qhead->mps) << 16)) | + (((uint_32)(qhead->ios) <<15)) | + (uint_32)((qhead->mult) << 30)); + + // 0x4 + // Current dTD Pointer => for hw use, not modified by DCD software + dqh_word->dqh_word1 = 0x0; + + // 0x8 + // Next dTD Pointer + dqh_word->dqh_word2 = (((qhead->next_link_ptr) & 0xFFFFFFE0) | qhead->terminate); + + // 0xC + // Bit30:16 total_bytes; Bit15 ioc; Bit11:10 MultO; Bit7:0 status + dqh_word->dqh_word3 = + ((((uint_32)(qhead->total_bytes) & 0x7FFF) << 16) | + ((uint_32)(qhead->ioc) << 15) | + (qhead->status)); + + // 0x10 + // Bit31:12 Buffer Pointer (Page 0) + dqh_word->dqh_word4 = + ((qhead->buffer_ptr0 & 0xFFFFF000) | + (qhead->current_offset & 0xFFF)); + + // 0x14 + // Bit31:12 Buffer Pointer (Page 1) + dqh_word->dqh_word5 = (qhead->buffer_ptr1 & 0xFFFFF000); + + // 0x18 + // Bit31:12 Buffer Pointer (Page 2) + dqh_word->dqh_word6 = (qhead->buffer_ptr2 & 0xFFFFF000); + + // 0x1C + // Bit31:12 Buffer Pointer (Page 3) + dqh_word->dqh_word7 = (qhead->buffer_ptr3 & 0xFFFFF000); + + // 0x20 + // Bit31:12 Buffer Pointer (Page 4) + dqh_word->dqh_word8 = (qhead->buffer_ptr4 & 0xFFFFF000); + + // 0x24 + // Reserved + dqh_word->dqh_word9 = 0; + + // 0x28 + // Setup Buffer 0 + dqh_word->dqh_word10 = 0; + + // 0x2C + // Setup Buffer 1 + dqh_word->dqh_word11 = 0; +} + +/*! + * Setup the transfer descriptor + * + * @param td The TD data sturcture that contains the necessary configuration data + */ +static void usbd_setup_td(struct dtd_t *td) +{ + volatile struct dtd_setup_t *dtd_word = (volatile struct dtd_setup_t *)td->dtd_base; + + /* Bit31:5 Next Link Pointer ; Bit0 terminate */ + dtd_word->dtd_word0 = ((td->next_link_ptr & 0xFFFFFFE0) | td->terminate); + + /* Bit30:16 total_bytes, Bit15 ioc, Bit7:0 status */ + dtd_word->dtd_word1 = ((unsigned int)td->total_bytes & 0x7FFF) << 16; + dtd_word->dtd_word1 |= ((unsigned int)td->ioc << 15) | (td->status); + + /* Bit31:12 Buffer Pointer Page 0 ; Bit11:0 Current Offset */ + dtd_word->dtd_word2 = ((td->buffer_ptr0 & 0xFFFFF000) | (td->current_offset & 0xFFF)); + + /* Bit31:12 Buffer Pointer Page 1 ; Bit10:0 Frame Number */ + dtd_word->dtd_word3 = (td->buffer_ptr1 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 2 ; */ + dtd_word->dtd_word4 = (td->buffer_ptr2 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 3 ; */ + dtd_word->dtd_word5 = (td->buffer_ptr3 & 0xFFFFF000); + + /* Bit31:12 Buffer Pointer Page 4 ; */ + dtd_word->dtd_word6 = (td->buffer_ptr4 & 0xFFFFF000); + +} +/*! + * Get the offset of DQH from the QH buffer base + * + * @param endpt_number The end point number, start from 0 + * @param direction The In or Out endpoint + * + * @return The relative offset of DQH + * @return 0 if can't find a free DTD + */ +static unsigned int usbd_get_dqh(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction) +{ + + unsigned char *qh_buf = g_usbd_qh_buf; + + /* direction OUT = 0 and IN = 1 */ + return (unsigned int)(qh_buf + (SIZE_OF_QHD * (endpt_number * 2 + direction))); +} + +/*! + * Get the offset of DTD from the TD buffer base + * + * @param endpt_number The end point number, start from 0 + * @param direction The In or Out endpoint + * + * @return The relative offset of DTD + */ +static unsigned int usbd_get_dtd(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned int sz) +{ + /* If Maximum EPs supported in n then EPno will range from 0 to (n-1) */ + unsigned int i; + unsigned char *td_buf = g_usbd_td_buf; + + int td_index = (endpt_number * 2) + direction; + + for(i = 0; i < MAX_DTDS_PER_EP; i++) { + + if(g_usbd_td_flag[td_index][i].status == DTD_FREE || + g_usbd_td_flag[td_index][i].total_bytes == 0) { + g_usbd_td_flag[td_index][i].status = DTD_BUSY; + // printf("ep%d direction%d alloc = %d\n", endpt_number, direction, i); + g_usbd_td_flag[td_index][i].phys_td = (volatile struct dtd_setup_t *) + ((unsigned int) td_buf + + (SIZE_OF_DTD0) *(td_index) * MAX_DTDS_PER_EP + + i * (SIZE_OF_DTD0)); + g_usbd_td_flag[td_index][i].total_bytes = sz; +#if USART_DEBUG + if(endpt_number == 1){ + printf("usbd_get_dtd ep1\n"); + } + if(endpt_number == 2){ + printf("usbd_get_dtd ep2\n"); + } + if(endpt_number == 3){ + printf("usbd_get_dtd ep3\n"); + } +#endif /* USART_DEBUG */ + return (unsigned int)g_usbd_td_flag[td_index][i].phys_td ; + } + } + // todo LOW 3: clear dtd and g_usbd_td_flag and point to first item +#ifdef USART_DEBUG + printf("Cannot get dTD!\n"); +#endif + return 0; +} + +static void usbd_ep_setup(uint_8 controller_ID, unsigned char endpt_number, unsigned char direction, unsigned char ep_type) +{ + if(endpt_number == CONTROL_ENDPOINT){ + return; + } + + unsigned int temp = 0; + + if(direction) { + //if(endpt_number) + temp |= USBHS_EPCR_TXR_MASK; + temp |= USBHS_EPCR_TXE_MASK; + temp |= ((unsigned int)(ep_type) << USBHS_EPCR_TXT_SHIFT); + /* configure RX endpoint as bulk(see K70 RM) */ + temp |= ((unsigned int)(2) << USBHS_EPCR_RXT_SHIFT); + } else { +// /if(endpt_number) + temp |= USBHS_EPCR_RXR_MASK; + temp |= USBHS_EPCR_RXE_MASK; + temp |= ((unsigned int)(ep_type) << USBHS_EPCR_RXT_SHIFT); + /* configure TX endpoint as bulk(see K70 RM) */ + temp |= ((unsigned int)(2) << USBHS_EPCR_TXT_SHIFT); + } + + // Initialize endpoints 1-3 + USBHS_EPCR(endpt_number-1) = temp; +} + +/**************************************************************************//*! + * + * @name usbd_setup_packet_handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +static void usbd_setup_packet_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + unsigned char setup_packet[8]; + + // Clear setup complete register + USBHS_EPSETUPSR = USBHS_EPSETUPSR; + + // Read setup packet + usbd_read_setup_packet(event->controller_ID, setup_packet); + + // Assume EP0 + event->ep_num = CONTROL_ENDPOINT; + + // Direction of setup complete is always Receive + event->direction = USB_RECV; + event->buffer_ptr = setup_packet; + event->len = sizeof(setup_packet); + event->setup = TRUE; + + /* Transfer direction of next packet */ + g_trf_direction = (uint_8)((uint_8) + (event->buffer_ptr[0]) >> 7); + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); +} + +// Read in setup packet. Assumes EP0. +static void usbd_read_setup_packet(uint_8 controller_ID, unsigned char *setup_packet) +{ + dqh_setup_t *dqh_word; + uint_32 dqh_address; + uint_32 reg; + uint_32 count = 10000; + int i; + usb_standard_device_request_t *setup_struct; + + // a. Clear setup complete register + reg = USBHS_EPSETUPSR; + USBHS_EPSETUPSR = reg; + + /* Get the Device Queue Head Address for EP0 OUT */ + dqh_address = usbd_get_dqh(controller_ID, EP0, OUT); + dqh_word = (dqh_setup_t *) dqh_address; + + do { + // b. Setup tripwire bit + USBHS_USBCMD |= USBHS_USBCMD_SUTW_MASK; + + // c. Copy the SetupBuffer into local software byte array + reg = (dqh_word->dqh_word10); + + /* This is due to the simulator bug for word variant access on EMI but actually design has word invariant access */ + for(i = 0; i < 4; i++) { + setup_packet[i] = (unsigned int)((reg >> (8 * i)) & 0xFF); + } + reg = (dqh_word->dqh_word11); + for(i = 0; i < 4; i++) { + setup_packet[i + 4] = (unsigned int)((reg >> (8 * i)) & 0xFF); + } + + // todo LOW 3: change to processor speed independent count + // d. Read USBCMD[SUTW] bit (if set, continue, else goto step b) + } while(!(USBHS_USBCMD & USBHS_USBCMD_SUTW_MASK) && (--count)); + + if(!count){ +#ifdef USART_DEBUG + printf("error getting setup buffer\n"); +#endif /* USART_DEBUG */ + } + + // e. Clear USBCMD[SUTW] bit + USBHS_USBCMD &= ~USBHS_USBCMD_SUTW_MASK; + + setup_struct = (usb_standard_device_request_t *)setup_packet; + if(setup_struct->bRequest == SET_ADDRESS) { + g_dci_address_state = 1; + } +} + + +static void usbd_port_change( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +){ +} + + +/**************************************************************************//*! + * + * @name usbd_dtd_handler + * + * @brief The function handles Token Complete USB interrupts on the bus. + * + * @param event : Pointer to USB EVENT Structure + * + * @return None + ****************************************************************************** + * This function handles Token Complete USB interrupts on the bus. + *****************************************************************************/ +static void usbd_ep_complete_handler( + USB_DEV_EVENT_STRUCT* event /* [IN] Pointer to USB EVENT Structure */ +) +{ + int i; + unsigned int ep_complete; + + // todo LOW CHECK 2: check this +#if USART_DEBUG + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(2)){ + printf("ep1: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(4)){ + printf("ep2: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ERCE(8)){ + printf("ep3: RECV\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(2)){ + printf("ep1: SEND\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(4)){ + printf("ep2: SEND\n"); + } + if(USBHS_EPCOMPLETE&USBHS_EPCOMPLETE_ETCE(8)){ + printf("ep3: SEND\n"); + } +#endif /* USART_DEBUG */ + // Get and clear endpoint complete register + ep_complete = USBHS_EPCOMPLETE; + USBHS_EPCOMPLETE = ep_complete; + + // Handle all ep bits set in ep complete register + for(i = 0; i < 16; i++) + { + // Determine bit position in ep complete register + // (skip over the reserved bits) + unsigned int ep_bit = (i < 8) ? i : (i + 8); + + if(ep_complete & (1 << ep_bit)) + { + if(ep_bit < 8) + { + // Endpoint Receive Complete Event + event->direction = USB_RECV; + event->ep_num = i; + } + else + { + // Endpoint Transmit Complete Event + event->direction = USB_SEND; + event->ep_num = ep_bit - 16; + } + + if(event->ep_num == CONTROL_ENDPOINT) + { + // Control endpoint handling + usbd_ep0_complete(event); + } + else + { + // Non-control endpoint handling + usbd_dtd_complete(event); + } + } + } +} + +// Control endpoint complete handling +static void usbd_ep0_complete(USB_DEV_EVENT_STRUCT* event) +{ + volatile struct dtd_setup_t *dtd_word; + unsigned int i; + unsigned int endpt_number = event->ep_num; + unsigned int direction = event->direction; + + // Walk the TD status array to find the next completed TD + for(i = 0; i < MAX_DTDS_PER_EP; i++) + { + unsigned int td_index = (endpt_number * 2) + direction; + + // Get dTD associated with this endpoint and direction + dtd_word = g_usbd_td_flag[td_index][i].phys_td; + + // Determine if dTD is busy (not free) and completed (not active) + if((g_usbd_td_flag[td_index][i].status == DTD_BUSY) && ((dtd_word->dtd_word1 & 0x80) != 0x80)) + { + // Mark dTD as free + g_usbd_td_flag[td_index][i].status = DTD_FREE; + + if(g_dci_address_state ==1) { + event->ep_num = CONTROL_ENDPOINT; + event->buffer_ptr = 0; + event->len = 0; + g_dci_address_state =0; + } + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); + } + } +} + +// Handle endpoint dTD complete +static void usbd_dtd_complete(USB_DEV_EVENT_STRUCT* event) +{ + volatile struct dtd_setup_t *dtd_word; + unsigned int i; + unsigned int endpt_number = event->ep_num; + unsigned int direction = event->direction; + + // todo LOW CHECK 2: check this +#if USART_DEBUG + if(event->ep_num == 1){ + printf("usbd_dtd_complete ep1\n"); + } + if(event->ep_num == 2){ + printf("usbd_dtd_complete ep2\n"); + } + if(event->ep_num == 3){ + printf("usbd_dtd_complete ep3\n"); + } +#endif /*USART_DEBUG */ + // Walk the TD status array to find the next completed TD + for(i = 0; i < MAX_DTDS_PER_EP; i++) + { + unsigned int td_index = (endpt_number * 2) + direction; + + // Get dTD associated with this endpoint and direction + dtd_word = g_usbd_td_flag[td_index][i].phys_td; + + // Determine if dTD is busy (not free) and completed (not active) + if((g_usbd_td_flag[td_index][i].status == DTD_BUSY) && ((dtd_word->dtd_word1 & 0x80) != 0x80)) + { + // Get original number of bytes to transfer + unsigned int total_bytes = g_usbd_td_flag[td_index][i].total_bytes; + // Subtract number of remaining bytes not transferred + event->len = total_bytes - (dtd_word->dtd_word1 >> 16) & 0x7FFF; + event->buffer_ptr = (uint_8 *)dtd_word->dtd_word2 - event->len; + + // Mark dTD as free + g_usbd_td_flag[td_index][i].status = DTD_FREE; + + // If this was the tail, mark list as empty + if(dtd_word == g_usbd_qh_tail[td_index]) + g_usbd_qh_tail[td_index] = NULL; + + /* Notify Device Layer of Data Received or Sent Event */ + (void)USB_Device_Call_Service(event->ep_num, event); +// break; + } + } +} + +/*! + * Receive data through EPx + * + * @param epx_data_buffer EPx receive buffer + * @param sz Number of bytes to receive + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_receive_data_epxout(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int direction = OUT; + + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, ep_num, direction, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get the total bytes to be received */ + total_bytes = sz; + +#if USART_DEBUG + if(total_bytes > 20 * 1024) + printf("Error!!! %s, size is %d\n", __func__, sz); +#endif /* USART_DEBUG */ + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = epx_data_buffer; + td.current_offset = (epx_data_buffer & 0xFFF); + td.buffer_ptr1 = (epx_data_buffer & 0xFFFFF000) + 0x1000; + td.buffer_ptr2 = (epx_data_buffer & 0xFFFFF000) + 0x2000; + td.buffer_ptr3 = (epx_data_buffer & 0xFFFFF000) + 0x3000; + td.buffer_ptr4 = (epx_data_buffer & 0xFFFFF000) + 0x4000; + + /* Set the Transfer Descriptor */ + usbd_setup_td(&td); + + // Add TD to TD list for this endpoint + direction + usbd_add_td(controller_ID, ep_num, direction, &td); + + return USB_SUCCESS; +} + +/*! + * Receive data through EP0 + * + * @param ep0_data_buffer EP0 receive buffer + * @param sz Number of bytes to receive + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_receive_data_ep0out(uint_8 controller_ID, unsigned int ep0_data_buffer, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int dqh_address; + unsigned int temp; + +// printf_info("%s, size is %d\n", __func__, sz); + + // Yi if(ep0_data_buffer != NULL) + // memset((void *)ep0_data_buffer, 0x0, 256); // todo LOW 2: hard-coded size + + /* Get Device Device Queue Head of the requested endpoint */ + dqh_address = usbd_get_dqh(controller_ID, EP0, OUT); + + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, EP0, OUT, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get the total bytes to be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = dtd_address + 0x20; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = ep0_data_buffer; + td.current_offset = (ep0_data_buffer & 0xFFF); + td.buffer_ptr1 = 0; + td.buffer_ptr2 = 0; + td.buffer_ptr3 = 0; + td.buffer_ptr4 = 0; + + /* Set the Transfer Descriptor */ + usbd_setup_td(&td); + + //Yi + //(*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = dtd_address; + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + /* 3. prime endpoint by writing '1' in ENDPTPRIME */ + temp = USBHS_EPPRIME; + temp |= EPOUT_PRIME; + USBHS_EPPRIME = temp; + while(USBHS_EPPRIME & EPOUT_PRIME) ; //wait prime end + + return USB_SUCCESS; +} + +// Prime endpoint +static void usbd_prime_ep(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td) +{ + unsigned int temp; + + unsigned int ep_mask = (direction == OUT ? EPOUT_PRIME : EPIN_PRIME); + // Get Device Device Queue Head of the requested endpoint + unsigned int dqh_address = usbd_get_dqh(controller_ID, ep_num, direction); + + /* Enable ZLT when data size is in multiple of Maximum Packet Size */ + /* set ZLT enable */ + if(direction == IN) + { + (*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + } + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = td->dtd_base; + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + /* 3. prime endpoint by writing '1' in ENDPTPRIME */ + temp = USBHS_EPPRIME; + temp |= ep_mask << ep_num; + USBHS_EPPRIME = temp; +} + +// Add TD to TD list and prime endpoint based on this algorithm: +// Appendix +// 5.5.3 Executing A Transfer Descriptor +// To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device +// controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. +// Determine whether the link list is empty: +// Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets +// are outstanding). +// Case 1: Link list is empty +// 1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. +// 2. Clear active & halt bit in dQH (in case set from a previous error). +// 3. Prime endpoint by writing '1' to correct bit position in ENDPTPRIME. +// Case 2: Link list is not empty +// 1. Add dTD to end of linked list. +// 2. Read correct prime bit in ENDPTPRIME - if '1' DONE. +// 3. Set ATDTW bit in USBCMD register to '1'. +// 4. Read correct status bit in ENDPTPRIME. (store in tmp. variable for later) [[this should be ENDPTSTATUS, not ENDPTPRIME]} +// 5. Read ATDTW bit in USBCMD register. +// If '0' goto 3. +// If '1' continue to 6. +// 6. Write ATDTW bit in USBCMD register to '0'. +// 7. If status bit read in (4) is '1' DONE. +// 8. If status bit read in (4) is '0' then Goto Case 1: Step 1. +// +static void usbd_add_td(uint_8 controller_ID, unsigned char ep_num, unsigned char direction, struct dtd_t *td) +{ + // Get the index into the TD list for this endpoint + direction + int td_index = (ep_num * 2) + direction; + + if(g_usbd_qh_tail[td_index] == NULL) + { + // Case 1: Link list is empty + + usbd_prime_ep(controller_ID, ep_num, direction, td); + } + else + { + // Case 2: Link list is not empty + + unsigned int ep_mask = (direction == OUT ? EPOUT_PRIME : EPIN_PRIME); + + // Add TD to tail next_link_ptr + // Clear Terminate bit to indicate pointer is valid + g_usbd_qh_tail[td_index]->dtd_word0 = td->dtd_base & 0xFFFFFFE0; + + // If EP is already primed, we are done + if(!(USBHS_EPPRIME & (ep_mask << ep_num))) + { + // EP not primed, check if it is active + unsigned int ep_status = 0; + unsigned int temp; + + // Use Add dTD Tripwire to properly read endpoint status register + do + { + /* write '1' to Add Tripwire (ATDTW) in USBCMD register */ + temp = USBHS_USBCMD; + temp |= (0x1 << USBHS_USBCMD_ATDTW_SHIFT); + USBHS_USBCMD = temp; + + // Read endpoint status + ep_status = USBHS_EPSR & (ep_mask << ep_num); + + } while(!USBHS_USBCMD & (0x1 << USBHS_USBCMD_ATDTW_SHIFT)); + + /* write '0' to Add Tripwire (ATDTW) in USBCMD register */ + temp = USBHS_USBCMD; + temp &= ~(0x1 << USBHS_USBCMD_ATDTW_SHIFT); + USBHS_USBCMD = temp; + + if(!ep_status) + { + // Status is inactive, so need to prime EP + usbd_prime_ep(controller_ID, ep_num, direction, td); + } + } + } + + // Make this TD the tail + g_usbd_qh_tail[td_index] = (struct dtd_setup_t *)td->dtd_base; +} + +/*! + * Send data through endpoint x + * + * @param epx_data_buffer EPx send buffer + * @param sz Number of bytes to send + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_send_data_epxin(uint_8 controller_ID, unsigned int epx_data_buffer, uint_8 ep_num, unsigned int sz) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address; + unsigned int direction = IN; + + /* verify Endpoint Number and address */ + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, ep_num, direction, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get Total Bytes to Be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = epx_data_buffer; + td.current_offset = (epx_data_buffer & 0xFFF); + td.buffer_ptr1 = (epx_data_buffer & 0xFFFFF000) + 0x1000; + td.buffer_ptr2 = (epx_data_buffer & 0xFFFFF000) + 0x2000; + td.buffer_ptr3 = (epx_data_buffer & 0xFFFFF000) + 0x3000; + td.buffer_ptr4 = (epx_data_buffer & 0xFFFFF000) + 0x4000; + + /* Set the transfer descriptor */ + usbd_setup_td(&td); + + // Add TD to TD list for this endpoint + direction + usbd_add_td(controller_ID, ep_num, direction, &td); + + return USB_SUCCESS; +} + +/*! + * Send data through endpoint 0 + * + * @param ep0_data_buffer EP0 send buffer + * @param sz Number of bytes to send + * @param zlt_enable If ZLT is enabled + * + * @return SUCCESS on success, otherwise FAIL when timeout + */ +static usb_status_t usbd_send_data_ep0in(uint_8 controller_ID, + unsigned int ep0_data_buffer, unsigned int sz, + unsigned char zlt_enable) +{ + struct dtd_t td; + unsigned int total_bytes; + unsigned int dtd_address, dqh_address; + + /* varify Endpoint Number and address */ + /* Get Device Transfer Descriptor of the requested endpoint */ + dtd_address = usbd_get_dtd(controller_ID, EP0, IN, sz); + if(!dtd_address) + { + return USB_FAILURE; + } + + /* Get Device Queue head of the requested endpoint */ + dqh_address = usbd_get_dqh(controller_ID, EP0, IN); + + /* Get Total Bytes to Be received */ + total_bytes = sz; + + td.dtd_base = dtd_address; + td.next_link_ptr = 0; + td.terminate = TERMINATE; + td.total_bytes = total_bytes; + td.ioc = IOC_SET; + td.status = ACTIVE; + td.buffer_ptr0 = ep0_data_buffer; + td.current_offset = (ep0_data_buffer & 0xFFF); + td.buffer_ptr1 = 0; + td.buffer_ptr2 = 0; + td.buffer_ptr3 = 0; + td.buffer_ptr4 = 0; + + /* Set the transfer descriptor */ + usbd_setup_td(&td); + + /* Enable ZLT when data size is in multiple of Maximum Packet Size */ + /* set ZLT enable */ + (*(volatile unsigned int *)(dqh_address)) &= ~0x20000000; + + /* 1. write dQH next ptr and dQH terminate bit to 0 */ + *(volatile unsigned int *)(dqh_address + 0x8) = (dtd_address); + + /* 2. clear active & halt bit in dQH */ + *(volatile unsigned int *)(dqh_address + 0xC) &= ~0xFF; + + USBHS_EPPRIME |= EPIN_PRIME; + + /* 4. wait for prime complete */ + while(USBHS_EPPRIME & EPIN_PRIME); + + return USB_SUCCESS; +} +#endif /* HIGH_SPEED_DEVICE */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h new file mode 100644 index 0000000..79d50ff --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dci_kinetis.h @@ -0,0 +1,311 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dci_kinetis.h + * + * @author + * + * @version + * + * @date + * + * @brief The file contains Macro's and functions needed by the DCI layer. + * + *****************************************************************************/ + +#ifndef _USB_DCI_H +#define _USB_DCI_H +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "hal/derivative.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define BYTES_1024 (1024) +#define BYTES_512 (512) +#define ENDPT_EP_STALL_MASK (0x02) +#define FRAME_HIGH_BYTE_SHIFT (8) + +#ifdef USB_LOWPOWERMODE +typedef enum _stopmode +{ + STOP_MODE1 = 1, /* STOP MODE 1 */ + STOP_MODE2 = 2, /* STOP MODE 2 */ + STOP_MODE3 = 3, /* STOP MODE 3 */ + STOP_MODE4 = 4 /* STOP MODE 4 */ +}STOP_MODE; +#endif + +/* USBTRC0 Initialization Parameters */ +#define _USBPHYEN (0x01) /* Use internal transceiver */ +#define _USBPUEN (0x40) /* Use internal pull-up resistor */ +#define _USBREGEN (0x04) /* Use the internal regulator */ +#define _USBRESET (0x80) + +#define UCFG_VAL (_USBPUEN|_USBREGEN) + +#define CTL_RESET_VAL (0) /* value programmed to the CTL + register in RESET */ + +#define EP_CTRL (0x0C) /* Cfg Control pipe for this endpoint */ +// HIGH_SPEED_DEVICE +#if !HIGH_SPEED_DEVICE +#define EP_OUT (0x08) /* Cfg OUT only pipe for this endpoint*/ +#define EP_IN (0x04) /* Cfg IN only pipe for this endpoint */ +#endif +#define HSHK_EN (0x01) /* Enable handshake packet */ + /* Handshake should be disable for + isochorous transfer */ +#define EP_CTL_DIS (0x10) + +#define EP_DISABLE (0) + +#define TRANSFER_INDEX(x) (x>>1) + +#define MAX_EP_BUFFER_SIZE USB_MAX_EP_BUFFER_SIZE /*Max Endpoint Buffer Size*/ + +/* Macro's to check whether corresponding INT_STAT bit is set */ +#define BUS_RESET_FLAG(x) ((x) & 1) +#define ERROR_FLAG(x) ((x) & 2) +#define SOF_TOKEN_FLAG(x) ((x) & 4) +#define SLEEP_FLAG(x) ((x) & 0x10) +#define RESUME_FLAG(x) ((x) & 0x20) +#define STALL_FLAG(x) ((x) & 0x80) +#define TOKEN_COMPL_FLAG(x) ((x) & 8) + +/* Setup the controller for Remote Wakeup */ +#define USB_DCI_WAKEUP \ +{ \ + USB0_ISTAT |= USB_ISTAT_RESUME_MASK; \ + USB0_INTEN &= ~USB_INTEN_RESUMEEN_MASK; \ + USB0_CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; \ +} + +/* control endpoint transfer types */ +#define USB_TRF_UNKNOWN (0xFF) + + +#define BDT_MIN_BUFFER_SIZE (16) /* space occupied by smallest + buffer in BDT */ + +#define BDT_MIN_BUFFER_ADDR_INC (4) /* min offset increment + correspoding to min buffer + size */ + +#define BDT_OFFSET_SHIFT (4) /* bdt offset shift */ + +#define INVALID_BDT_INDEX (0xFF)/* invalid bdt index */ + +#define ENDPOINT_NUMBER_SHIFT (4) /* endpoint shift & mask to */ +#define ENDPOINT_NUMBER_MASK (0xF0)/* use in setting and getting + status */ + +#define ENDPOINT_DIRECTION_SHIFT (3) /* direction shift & mask to */ +#define ENDPOINT_DIRECTION_MASK (0x08)/* be used for STAT byte + in BDT */ + +#define SEND_CONTROL_ENDPOINT_BDT_INDEX (2) /* BDT Index for Control Endpoint + SEND direction */ +#define RECV_CONTROL_ENDPOINT_BDT_INDEX (0) /* BDT Index for Control Endpoint + RECV direction */ + +#define EPCTL_STALL (0x02)/* Stall bit in Endpoint + Control Reg */ + +#define USB_SETUP_TOKEN (0x0d)/* Setup Token PID */ +#define USB_SETUP_DIRECTION (0x80)/* Data xfer direction + for Setup packet */ + +#define INT_STAT_CLEAR_ALL (0xBF)/* Value to clear + all Interrupts */ +#define ERR_STAT_CLEAR_ALL (0xBF)/* Value to clear + all Errors */ +#define ERR_ENB_ENABLE_ALL (0xBF)/* Value to enable + all Error Interrupts */ +#define INTENB_BUS_RESET_VAL (0x9F)/* Value to enable + Interrupts in Bus Reset */ +#define INTENB_DISABLE_ALL_VAL (0x00)/* Value to disable all + Interrupts */ + +#define MAX_USB_RAM_BUFFER_INDEX (14) /* MAX possible RAM buffer + Index */ + +#define EP_START_BUFFER_ADDR (0x08)/* First USB_RAM buffer offset*/ + +#define ASSERT_RESUME_DELAY_COUNT (20000)/* Delay for assert resume, 48MHz clock */ + +#define NO_ERRORS (0) /* Init value for error */ + +#define USB_RAM_EVEN_BUFFER (0) +#define USB_RAM_ODD_BUFFER (1) + +#define SWAP16(val) (val) + +#define SWAP32(val) (val) + +/****************************************************************************** + * Types + *****************************************************************************/ +#ifdef LONG_SEND_TRANSACTION + #define LONG_TRANSACTION +#endif + +#ifdef LONG_RECEIVE_TRANSACTION + #define LONG_TRANSACTION +#endif + +typedef union { + uint_8 Byte; + struct { + uint_8 EP_HSHK :1; /* When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous */ + uint_8 EP_STALL :1; /* When set this bit indicates that the endpoint is stalled */ + uint_8 EP_TX_EN :1; /* This bit, when set, enables the endpoint for TX transfers */ + uint_8 EP_RX_EN :1; /* This bit, when set, enables the endpoint for RX transfers */ + uint_8 EP_CTRL_DIS :1; /* This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set */ + uint_8 :1; + uint_8 RETRY_DIS :1; /* This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) */ + uint_8 HOST_WO_HUB :1; /* This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) */ + } Bits; +} ENDPT0STR; + +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) +/* This structure is used to hold endpoint paramaetes and the + transaction parameters on the IO's happening on them */ +typedef struct _BDT_ELEM +{ + uint_16 len; /* endpoint max buffer len */ + uint_32 addr; /* endpoint buffer addr in USB_RAM */ +#ifdef LONG_TRANSACTION + uint_8_ptr app_buffer; /* application buffer pointer */ + USB_PACKET_SIZE app_len; /* application buffer len */ + USB_PACKET_SIZE curr_offset; /* current offset for long transactions */ +#endif + uint_8 flag; /* zero termination flag */ + uint_8 bdtmap_index; /* Corresponding to the buffer */ + uint_8 direction; /* Direction (Send/Receive) */ + uint_8 type; /* Type of Endpoint */ +} BDT_ELEM, *P_BDT_ELEM; +#if defined(__CWCC__) + #pragma options align = reset +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma pack() +#else /* gcc */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#endif + + +uint_8 USB_DCI_DeInit(void); + + /***************************************************************************** + * Global Functions + *****************************************************************************/ +//extern uint_8 USB_Device_Call_Service( +// uint_8 type, +// PTR_USB_DEV_EVENT_STRUCT event +//); + +#ifndef OTG_BUILD +void USB_ISR(void); +#endif + +#if HIGH_SPEED_DEVICE + /* Device Queue Head and Device Transfer Descriptor Related Defination */ + #define SIZE_OF_QHD 0x40 + #define SIZE_OF_DTD0 0x20 + #define SIZE_OF_DTD1 0x20 + #define dTD_SIZE_EPIN (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 + #define dTD_SIZE_EPOUT (SIZE_OF_DTD0 + SIZE_OF_DTD1) //0x40 + #define BUFFER_USED_PER_EP ((SIZE_OF_QHD + dTD_SIZE_EPIN) +(SIZE_OF_QHD + dTD_SIZE_EPOUT)) //0x100 + #define ZLT_ENABLE 0 + #define ZLT_DISABLE 1 + #define IOS_NOTSET 0 + #define IOS_SET 1 + #define IOC_NOTSET 0 + #define IOC_SET 1 + #define TERMINATE 1 + #define NOT_TERMINATE 0 + #define NO_STATUS 0 + #define ACTIVE 0x00000080 + #define EPOUT_COMPLETE 0x00000001 + #define EPIN_COMPLETE 0x00010000 + #define EPOUT_PRIME 0x00000001 + #define EPIN_PRIME 0x00010000 + #define EPOUT_ENABLE 0x00000080 + #define EPIN_ENABLE 0x00800000 + #define STALL_RX 0x00000001 + #define STALL_TX 0x00010000 + + /* Maximum packet size defination */ + #define MPS_8 8 + #define MPS_64 64 + + /* enum for endpoint numbers */ + enum { + EP0, + EP1, + EP2, + EP3, + EP4, + EP5 + }; + + enum { + OUT, + IN + }; + + /* enum for data transfer type on endpoints */ + enum { + CONTROL, + ISOCHRONOUS, + BULK, + INTERRUPT + }; + + /* Status of all transaction on USB */ + typedef enum { + USB_SUCCESS, + USB_FAILURE, + USB_INVALID = -1 /* Always Keep this entry in last */ + } usb_status_t; + + /* USB Device State which are handled by DCD */ + typedef enum { + USB_DEV_DUMMY_STATE, + USB_DEV_DEFAULT_STATE, + USB_DEV_ADDRESSED_STATE, + USB_DEV_CONFIGURED_STATE + } usb_state_t; +#endif // HIGH_SPEED_DEVICE + +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h new file mode 100644 index 0000000..1e7ec1d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_dciapi.h @@ -0,0 +1,262 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_dciapi.h + * + * @author + * + * @version + * + * @date Jun-05-2009 + * + * @brief The file contains DCI api function definetions . + * + *****************************************************************************/ + +#ifndef _USB_DCIAPI_H +#define _USB_DCIAPI_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_devapi.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define MAX_SUPPORTED_ENDPOINTS (USB_SERVICE_MAX_EP + 1) + /* Maximum endpoints supported */ +#define MIN_SUPPORTED_ENDPOINTS (1) /* Minimum endpoints supported */ +#define DOUBLE_BUFFERED_ENPOINT_NUMBER (0) /* First double buffered endpoint */ + +#ifdef MCU_MK70F12 +#define NUM_USB_CONTROLLERS (2) +#else +#define NUM_USB_CONTROLLERS (1) +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef enum USB_Controllers_t +{ + MAX3353, + ULPI +}USB_Controllers_t; + +#if HIGH_SPEED_DEVICE +typedef struct dqh_setup_t { + unsigned int dqh_word0; + unsigned int dqh_word1; + unsigned int dqh_word2; + unsigned int dqh_word3; + unsigned int dqh_word4; + unsigned int dqh_word5; + unsigned int dqh_word6; + unsigned int dqh_word7; + unsigned int dqh_word8; + unsigned int dqh_word9; + unsigned int dqh_word10; + unsigned int dqh_word11; +} dqh_setup_t; + +typedef struct dtd_setup_t { + unsigned int dtd_word0; + unsigned int dtd_word1; + unsigned int dtd_word2; + unsigned int dtd_word3; + unsigned int dtd_word4; + unsigned int dtd_word5; + unsigned int dtd_word6; + unsigned int dtd_word7; +} dtd_setup_t; + +typedef struct dqh_t { + unsigned int dqh_base; + unsigned int next_link_ptr; + unsigned int buffer_ptr0; + unsigned int buffer_ptr1; + unsigned int buffer_ptr2; + unsigned int buffer_ptr3; + unsigned int buffer_ptr4; + unsigned short total_bytes; + unsigned short mps; + unsigned short current_offset; + unsigned char zlt; + unsigned char ios; + unsigned char terminate; + unsigned char ioc; + unsigned char status; + unsigned char mult; +} dqh_t; + +typedef struct dtd_t { + unsigned int dtd_base; + unsigned int next_link_ptr; + unsigned int buffer_ptr0; + unsigned int buffer_ptr1; + unsigned int buffer_ptr2; + unsigned int buffer_ptr3; + unsigned int buffer_ptr4; + unsigned short total_bytes; + unsigned short current_offset; + unsigned char terminate; + unsigned char ioc; + unsigned char status; +} dtd_t; + +typedef struct { + unsigned int ep_dqh_base_addrs; /* Base Address of Queue Header */ + unsigned int ep_dtd_base_addrs; /* Base Address of Transfer Descriptor */ + unsigned int ep0_buffer_addrs; /* Buffer Addres for EP0 IN */ + unsigned int buffer1_address; /* Buffer1 address for bulk transfer */ + unsigned int buffer1_status; /* Status of Buffer1 */ + unsigned int buffer2_address; /* Buffer2 address for bulk transfer */ + unsigned int buffer2_status; /* Status of Buffer2 */ +} buffer_map_t; + +/* USB standard device request*/ +typedef struct usb_standrd_device_request { + unsigned char bmRequestType; + unsigned char bRequest; + unsigned short wValue; + unsigned short wIndex; + unsigned short wLength; +} usb_standard_device_request_t; + +#endif // HIGH_SPEED_DEVICE + + /***************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_DCI_Init( + uint_8 controller_ID, + uint_8 bVregEn +); + +extern uint_8 USB_DCI_Init_EndPoint( + uint_8 controller_ID, + USB_EP_STRUCT_PTR ep_ptr, + boolean flag +); + +extern uint_8 USB_DCI_Cancel_Transfer( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern uint_8 USB_DCI_Deinit_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Stall_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Unstall_EndPoint( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Get_Setup_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr +); + +extern uint_8 USB_DCI_Get_Transfer_Status( + uint_8 controller_ID, + uint_8 ep_num, + uint_8 direction +); + +extern void USB_DCI_Clear_DATA0_Endpoint( + uint_8 ep_num, + uint_8 direction +); + +extern uint_8 USB_DCI_Recv_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern uint_8 USB_DCI_Send_Data( + uint_8 controller_ID, + uint_8 ep_num, + uint8_ptr buff_ptr, + USB_PACKET_SIZE size +); + +extern void USB_DCI_Set_Address( + uint_8 controller_ID, + uint_8 address +); + +extern void USB_DCI_Shutdown( + uint_8 controller_ID +); + +extern void USB_DCI_Assert_Resume( + uint_8 controller_ID +); + +extern void Clear_Mem(uint_8* start_addr,uint_32 count, uint_8 val); + +#define USB_DCI_Cancel_Transfer _usb_device_cancel_transfer + +#define USB_DCI_Recv_Data _usb_device_recv_data + +#define USB_DCI_Send_Data _usb_device_send_data + +#define USB_DCI_Shutdown _usb_device_shutdown + +#define USB_DCI_Stall_EndPoint _usb_device_stall_endpoint + +#define USB_DCI_Unstall_EndPoint _usb_device_unstall_endpoint + +#define USB_DCI_Get_Transfer_Status _usb_device_get_transfer_status + +#define USB_DCI_Clear_DATA0_Endpoint _usb_device_clear_data0_endpoint + +#define USB_DCI_Get_Setup_Data _usb_device_read_setup_data + +#define USB_DCI_Set_Address _usb_device_set_address + +#define USB_DCI_Assert_Resume _usb_device_assert_resume + +#endif + + + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c new file mode 100644 index 0000000..2f938c2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.c @@ -0,0 +1,889 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_descriptor.c + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief This file contains USB descriptors for Virtual COM Loopback + * Application + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "hal/derivative.h" +#include "types.h" +#include "usb_class.h" +#include "usb_descriptor.h" + +#if (defined __MCF52xxx_H__)||(defined __MK_xxx_H__) +/* Put CFV2 descriptors in RAM */ +#define USB_DESC_CONST +#else +#define USB_DESC_CONST const +#endif + +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ +/* structure containing details of all the endpoints used by this device */ +USB_DESC_CONST USB_ENDPOINTS usb_desc_ep = +{ + CDC_DESC_ENDPOINT_COUNT, + { + #if DATA_CLASS_SUPPORT + #if DIC_ISOCHRONOUS_SETTING + { + DIC_ISO_IN_ENDPOINT, + USB_ISOCHRONOUS_PIPE, + USB_SEND, + DIC_ISO_IN_ENDP_PACKET_SIZE + }, + { + DIC_ISO_OUT_ENDPOINT, + USB_ISOCHRONOUS_PIPE, + USB_RECV, + DIC_ISO_OUT_ENDP_PACKET_SIZE + } + #else + { + DIC_BULK_IN_ENDPOINT, + USB_BULK_PIPE, + USB_SEND, + DIC_BULK_IN_ENDP_PACKET_SIZE + }, + { + DIC_BULK_OUT_ENDPOINT, + USB_BULK_PIPE, + USB_RECV, + DIC_BULK_OUT_ENDP_PACKET_SIZE + } + #endif + #endif + #if CIC_NOTIF_ELEM_SUPPORT + , + { + CIC_NOTIF_ENDPOINT, + USB_INTERRUPT_PIPE, + USB_SEND, + CIC_NOTIF_ENDP_PACKET_SIZE + } + #endif + + } +}; + +uint_8 USB_DESC_CONST g_device_descriptor[DEVICE_DESCRIPTOR_SIZE] = +{ + DEVICE_DESCRIPTOR_SIZE, /* Device Descriptor Size */ + USB_DEVICE_DESCRIPTOR, /* Device Type of descriptor */ + 0x00, 0x02, /* BCD USB version */ + 0x02, /* Device Class is indicated in + the interface descriptors */ + 0x00, /* Device Subclass is indicated + in the interface descriptors */ + 0x00, /* Device Protocol */ + CONTROL_MAX_PACKET_SIZE, /* Max Packet size */ + (0x2A3C&0xFF),((0x2A3C>>8)&0xFF), /* Vendor ID "Trinamic" */ + (0x0700&0xFF),((0x0700>>8)&0xFF), /* "TRINAMIC Evaluation Device" */ + 0x02,0x00, /* BCD Device version */ + 0x01, /* Manufacturer string index */ + 0x02, /* Product string index */ + 0x00, /* Serial number string index */ + 0x01 /* Number of configurations */ +}; + +uint_8 USB_DESC_CONST g_config_descriptor[CONFIG_DESC_SIZE] = +{ + CONFIG_ONLY_DESC_SIZE, /* Configuration Descriptor Size */ + USB_CONFIG_DESCRIPTOR, /* "Configuration" type of descriptor */ + CONFIG_DESC_SIZE, 0x00, /* Total length of the Configuration descriptor */ + (uint_8)(1+DATA_CLASS_SUPPORT),/*NumInterfaces*/ + 0x01, /* Configuration Value */ + 0x00, /* Configuration Description String Index*/ + BUS_POWERED|SELF_POWERED|(REMOTE_WAKEUP_SUPPORT<> 0) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>> 8) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>>16) & 0x000000FF, + (LINE_CODE_DTERATE_IFACE0>>24) & 0x000000FF, + /*e.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */ + LINE_CODE_CHARFORMAT_IFACE0, + LINE_CODE_PARITYTYPE_IFACE0, + LINE_CODE_DATABITS_IFACE0 + } +}; + +static uint_8 g_abstract_state[USB_MAX_SUPPORTED_INTERFACES][COMM_FEATURE_DATA_SIZE] = +{ + { (STATUS_ABSTRACT_STATE_IFACE0>>0) & 0x00FF, + (STATUS_ABSTRACT_STATE_IFACE0>>8) & 0x00FF + } +}; + +static uint_8 g_country_code[USB_MAX_SUPPORTED_INTERFACES][COMM_FEATURE_DATA_SIZE] = +{ + { (COUNTRY_SETTING_IFACE0>>0) & 0x00FF, + (COUNTRY_SETTING_IFACE0>>8) & 0x00FF + } +}; + +static uint_8 g_alternate_interface[USB_MAX_SUPPORTED_INTERFACES]; + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + + + /***************************************************************************** + * Local Functions - None + *****************************************************************************/ + +/***************************************************************************** + * Global Functions + *****************************************************************************/ +/**************************************************************************//*! + * + * @name USB_Desc_Get_Descriptor + * + * @brief The function returns the correponding descriptor + * + * @param controller_ID : Controller ID + * @param type : type of descriptor requested + * @param sub_type : string index for string descriptor + * @param index : string descriptor language Id + * @param descriptor : output descriptor pointer + * @param size : size of descriptor returned + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is used to pass the pointer to the requested descriptor + *****************************************************************************/ +uint_8 USB_Desc_Get_Descriptor ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 type, /* [IN] type of descriptor requested */ + uint_8 str_num, /* [IN] string index for string descriptor */ + uint_16 index, /* [IN] string descriptor language Id */ + uint_8_ptr *descriptor, /* [OUT] output descriptor pointer */ + USB_PACKET_SIZE *size /* [OUT] size of descriptor returned */ +) +{ + UNUSED (controller_ID); + + /* string descriptors are handled saperately */ + if(type == USB_STRING_DESCRIPTOR) + { + if(index == 0) + { + /* return the string and size of all languages */ + *descriptor = (uint_8_ptr) (unsigned long) g_languages.languages_supported_string; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + *size = g_languages.languages_supported_size; + } else + { + uint_8 lang_id=0; + uint_8 lang_index=USB_MAX_LANGUAGES_SUPPORTED; + + for(;lang_id< USB_MAX_LANGUAGES_SUPPORTED;lang_id++) + { + /* check whether we have a string for this language */ + if(index == g_languages.usb_language[lang_id].language_id) + { /* check for max descriptors */ + if(str_num < USB_MAX_STRING_DESCRIPTORS) + { /* setup index for the string to be returned */ + lang_index=str_num; + } + + break; + } + + } + + /* set return val for descriptor and size */ + *descriptor = (uint_8_ptr) (unsigned long) g_languages.usb_language[lang_id]. // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + lang_desc[lang_index]; + *size = g_languages.usb_language[lang_id]. + lang_desc_size[lang_index]; + } + + } + else if(type < USB_MAX_STD_DESCRIPTORS+1) + { + /* Set return val for descriptor and size */ + *descriptor = (uint_8_ptr) (unsigned long) g_std_descriptors [type]; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const + + /* if there is no descriptor then return error */ + if(*descriptor == NULL) + { + return USBERR_INVALID_REQ_TYPE; + } + + *size = g_std_desc_size[type]; + } + else /* invalid descriptor */ + { + return USBERR_INVALID_REQ_TYPE; + } + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Interface + * + * @brief The function returns the alternate interface + * + * @param controller_ID : Controller Id + * @param interface : Interface number + * @param alt_interface : Output alternate interface + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is called by the framework module to get the current interface + *****************************************************************************/ +uint_8 USB_Desc_Get_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] interface number */ + uint_8_ptr alt_interface /* [OUT] output alternate interface */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get alternate interface*/ + *alt_interface = g_alternate_interface[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Interface + * + * @brief The function sets the alternate interface + * + * @param controller_ID : Controller Id + * @param interface : Interface number + * @param alt_interface : Input alternate interface + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * This function is called by the framework module to set the interface + *****************************************************************************/ +uint_8 USB_Desc_Set_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] interface number */ + uint_8 alt_interface /* [IN] input alternate interface */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set alternate interface*/ + g_alternate_interface[interface]=alt_interface; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Valid_Configation + * + * @brief The function checks whether the configuration parameter + * input is valid or not + * + * @param controller_ID : Controller Id + * @param config_val : Configuration value + * + * @return TRUE When Valid + * FALSE When Error + ***************************************************************************** + * This function checks whether the configuration is valid or not + *****************************************************************************/ +boolean USB_Desc_Valid_Configation ( + uint_8 controller_ID,/*[IN] Controller ID */ + uint_16 config_val /*[IN] configuration value */ +) +{ + uint_8 loop_index=0; + UNUSED (controller_ID); + + /* check with only supported val right now */ + while(loop_index < (USB_MAX_CONFIG_SUPPORTED+1)) + { + if(config_val == g_valid_config_values[loop_index]) + { + return TRUE; + } + loop_index++; + } + + return FALSE; +} +/**************************************************************************//*! + * + * @name USB_Desc_Valid_Interface + * + * @brief The function checks whether the interface parameter + * input is valid or not + * + * @param controller_ID : Controller Id + * @param interface : Target interface + * + * @return TRUE When Valid + * FALSE When Error + ***************************************************************************** + * This function checks whether the interface is valid or not + *****************************************************************************/ +boolean USB_Desc_Valid_Interface ( + uint_8 controller_ID, /*[IN] Controller ID */ + uint_8 interface /*[IN] target interface */ +) +{ + uint_8 loop_index=0; + UNUSED (controller_ID); + + /* check with only supported val right now */ + while(loop_index < USB_MAX_SUPPORTED_INTERFACES) + { + if(interface == g_alternate_interface[loop_index]) + { + return TRUE; + } + loop_index++; + } + + return FALSE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Remote_Wakeup + * + * @brief The function checks whether the remote wakeup is supported or not + * + * @param controller_ID : Controller ID + * + * @return REMOTE_WAKEUP_SUPPORT (TRUE) - if remote wakeup supported + ***************************************************************************** + * This function returns remote wakeup is supported or not + *****************************************************************************/ +boolean USB_Desc_Remote_Wakeup ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return REMOTE_WAKEUP_SUPPORT; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Endpoints + * + * @brief The function returns with the list of all non control endpoints used + * + * @param controller_ID : Controller ID + * + * @return pointer to USB_ENDPOINTS + ***************************************************************************** + * This function returns the information about all the non control endpoints + * implemented + *****************************************************************************/ +void* USB_Desc_Get_Endpoints ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return (void*) (unsigned long) &usb_desc_ep; // cast to unsigned long before properly casting to prevent gcc from complaining about cast from const to non-const +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Line_Coding + * + * @brief The function returns the Line Coding/Configuraion + * + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param coding_data : Output line coding data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns current Line Coding Parameters + *****************************************************************************/ +uint_8 USB_Desc_Get_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *coding_data /* [OUT] Line Coding Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *coding_data = g_line_coding[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Line_Coding + * + * @brief The function sets the Line Coding/Configuraion + * + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param coding_data : Output line coding data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets Line Coding Structure with the HOST specified values + *****************************************************************************/ +uint_8 USB_Desc_Set_Line_Coding ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *coding_data /* [IN] Line Coding Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set line coding data*/ + for(count = 0; count < LINE_CODING_SIZE; count++) + { + g_line_coding[interface][count] = *((*coding_data + + USB_SETUP_PKT_SIZE) + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Abstract_State + * + * @brief The function gets the current setting for communication feature + * (ABSTRACT_STATE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns ABSTRACT STATE Communication Feature to the Host + *****************************************************************************/ +uint_8 USB_Desc_Get_Abstract_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *feature_data = g_abstract_state[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Get_Country_Setting + * + * @brief The function gets the current setting for communication feature + * (COUNTRY_CODE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Returns the country Code to the Host + *****************************************************************************/ +uint_8 USB_Desc_Get_Country_Setting ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + UNUSED (controller_ID); + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* get line coding data*/ + *feature_data = g_country_code[interface]; + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Abstract_State + * + * @brief The function gets the current setting for communication feature + * (ABSTRACT_STATE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets the ABSTRACT State specified by the Host + *****************************************************************************/ +uint_8 USB_Desc_Set_Abstract_State ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + /* set Abstract State Feature*/ + for(count = 0; count < COMM_FEATURE_DATA_SIZE; count++) + { + g_abstract_state[interface][count] = *(*feature_data + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} + +/**************************************************************************//*! + * + * @name USB_Desc_Set_Country_Setting + * + * @brief The function gets the current setting for communication feature + * (COUNTRY_CODE) + * @param controller_ID : Controller ID + * @param interface : Interface number + * @param feature_data : Output comm feature data + * + * @return USB_OK When Successfull + * USBERR_INVALID_REQ_TYPE when Error + ***************************************************************************** + * Sets the country code specified by the HOST + *****************************************************************************/ +uint_8 USB_Desc_Set_Country_Setting( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 interface, /* [IN] Interface Number */ + uint_8_ptr *feature_data /* [OUT] Output Comm Feature Data */ +) +{ + uint_8 count; + UNUSED (controller_ID); + + /* if interface valid */ + if(interface < USB_MAX_SUPPORTED_INTERFACES) + { + for(count = 0; count < COMM_FEATURE_DATA_SIZE; count++) + { + g_country_code[interface][count] = *(*feature_data + count); + } + return USB_OK; + } + + return USBERR_INVALID_REQ_TYPE; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h new file mode 100644 index 0000000..a7ac870 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_descriptor.h @@ -0,0 +1,301 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_descriptor.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file is a header file for USB Descriptors required for Virtual + * COM Loopback Application + *****************************************************************************/ + +#ifndef _USB_DESCRIPTOR_H +#define _USB_DESCRIPTOR_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_class.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define REMOTE_WAKEUP_SUPPORT (FALSE) +#define DATA_CLASS_SUPPORT (TRUE) +#define CIC_NOTIF_ELEM_SUPPORT (TRUE) /* Mandatory */ +#define DIC_ISOCHRONOUS_SETTING (FALSE) + +#define IMPLEMENT_QUEUING (TRUE) + +/* Communication Class SubClass Codes */ +#define DIRECT_LINE_CONTROL_MODEL (0x01) +#define ABSTRACT_CONTROL_MODEL (0x02) +#define TELEPHONE_CONTROL_MODEL (0x03) +#define MULTI_CHANNEL_CONTROL_MODEL (0x04) +#define CAPI_CONTROL_MOPDEL (0x05) +#define ETHERNET_NETWORKING_CONTROL_MODEL (0x06) +#define ATM_NETWORKING_CONTROL_MODEL (0x07) +#define WIRELESS_HANDSET_CONTROL_MODEL (0x08) +#define DEVICE_MANAGEMENT (0x09) +#define MOBILE_DIRECT_LINE_MODEL (0x0A) +#define OBEX (0x0B) +#define ETHERNET_EMULATION_MODEL (0x0C) + +/* Communication Class Protocol Codes */ +#define NO_CLASS_SPECIFIC_PROTOCOL (0x00) +#define AT_250_PROTOCOL (0x01) +#define AT_PCCA_101_PROTOCOL (0x02) +#define AT_PCCA_101_ANNEX_O (0x03) +#define AT_GSM_7_07 (0x04) +#define AT_3GPP_27_007 (0x05) +#define AT_TIA_CDMA (0x06) +#define ETHERNET_EMULATION_PROTOCOL (0x07) +#define EXTERNAL_PROTOCOL (0xFE) +#define VENDOR_SPECIFIC (0xFF) + +/* Data Class Protocol Codes */ +/* #define NO_CLASS_SPECIFIC_PROTOCOL (0x00) */ +#define PYHSICAL_INTERFACE_PROTOCOL (0x30) +#define HDLC_PROTOCOL (0x31) +#define TRANSPARENT_PROTOCOL (0x32) +#define MANAGEMENT_PROTOCOL (0x50) +#define DATA_LINK_Q931_PROTOCOL (0x51) +#define DATA_LINK_Q921_PROTOCOL (0x52) +#define DATA_COMPRESSION_V42BIS (0x90) +#define EURO_ISDN_PROTOCOL (0x91) +#define RATE_ADAPTION_ISDN_V24 (0x92) +#define CAPI_COMMANDS (0x93) +#define HOST_BASED_DRIVER (0xFD) +#define CDC_UNIT_FUNCTIONAL (0xFE) +/* #define VENDOR_SPECIFIC (0xFF) */ + +/* Descriptor SubType in Communications Class Functional Descriptors */ +#define HEADER_FUNC_DESC (0x00) +#define CALL_MANAGEMENT_FUNC_DESC (0x01) +#define ABSTRACT_CONTROL_FUNC_DESC (0x02) +#define DIRECT_LINE_FUNC_DESC (0x03) +#define TELEPHONE_RINGER_FUNC_DESC (0x04) +#define TELEPHONE_REPORT_FUNC_DESC (0x05) +#define UNION_FUNC_DESC (0x06) +#define COUNTRY_SELECT_FUNC_DESC (0x07) +#define TELEPHONE_MODES_FUNC_DESC (0x08) +#define USB_TERMINAL_FUNC_DESC (0x09) +#define NETWORK_CHANNEL_FUNC_DESC (0x0A) +#define PROTOCOL_UNIT_FUNC_DESC (0x0B) +#define EXTENSION_UNIT_FUNC_DESC (0x0C) +#define MULTI_CHANNEL_FUNC_DESC (0x0D) +#define CAPI_CONTROL_FUNC_DESC (0x0E) +#define ETHERNET_NETWORKING_FUNC_DESC (0x0F) +#define ATM_NETWORKING_FUNC_DESC (0x10) +#define WIRELESS_CONTROL_FUNC_DESC (0x11) +#define MOBILE_DIRECT_LINE_FUNC_DESC (0x12) +#define MDLM_DETAIL_FUNC_DESC (0x13) +#define DEVICE_MANAGEMENT_FUNC_DESC (0x14) +#define OBEX_FUNC_DESC (0x15) +#define COMMAND_SET_FUNC_DESC (0x16) +#define COMMAND_SET_DETAIL_FUNC_DESC (0x17) +#define TELEPHONE_CONTROL_FUNC_DESC (0x18) +#define OBEX_SERVICE_ID_FUNC_DESC (0x19) + + +#define CIC_SUBCLASS_CODE ABSTRACT_CONTROL_MODEL +#define CIC_PROTOCOL_CODE NO_CLASS_SPECIFIC_PROTOCOL +#define DIC_PROTOCOL_CODE NO_CLASS_SPECIFIC_PROTOCOL +#define CIC_ENDP_COUNT (0+(CIC_NOTIF_ELEM_SUPPORT & 0x01) * 1) +#define DIC_ENDP_COUNT (2) + +#define CIC_NOTIF_ENDPOINT (3) +#define CIC_NOTIF_ENDP_PACKET_SIZE (16) +#define DIC_BULK_IN_ENDPOINT (1) +#define DIC_BULK_IN_ENDP_PACKET_SIZE (16)/* max supported is 64 */ +#define DIC_BULK_OUT_ENDPOINT (2) +#define DIC_BULK_OUT_ENDP_PACKET_SIZE (16)/* max supported is 64*/ + +#if DIC_ISOCHRONOUS_SETTING +#define DIC_ISO_IN_ENDPOINT (1) +#define DIC_ISO_IN_ENDP_PACKET_SIZE (64) +#define DIC_ISO_OUT_ENDPOINT (2) +#define DIC_ISO_OUT_ENDP_PACKET_SIZE (64) +#endif +#define REMOTE_WAKEUP_SHIFT (5) + +/* Various descriptor sizes */ +#define DEVICE_DESCRIPTOR_SIZE (18) +#define CONFIG_ONLY_DESC_SIZE (9) +#define CONFIG_DESC_SIZE (CONFIG_ONLY_DESC_SIZE + 28 + \ + (CIC_NOTIF_ELEM_SUPPORT & 0x01) \ + * 7 + DATA_CLASS_SUPPORT * 23) +#define DEVICE_QUALIFIER_DESCRIPTOR_SIZE (10) +#define IFACE_ONLY_DESC_SIZE (9) +#define ENDP_ONLY_DESC_SIZE (7) + +/* Max descriptors provided by the Application */ +#define USB_MAX_STD_DESCRIPTORS (7) + +/* Max configuration supported by the Application */ +#define USB_MAX_CONFIG_SUPPORTED (1) + +/* Max string descriptors supported by the Application */ +#define USB_MAX_STRING_DESCRIPTORS (3) + +/* Max language codes supported by the USB */ +#define USB_MAX_LANGUAGES_SUPPORTED (1) + +/* string descriptors sizes */ +#define USB_STR_DESC_SIZE (2) +#define USB_STR_0_SIZE (2) +#define USB_STR_1_SIZE (56) +#define USB_STR_2_SIZE (36) +#define USB_STR_n_SIZE (32) + +/* descriptors codes */ +#define USB_DEVICE_DESCRIPTOR (1) +#define USB_CONFIG_DESCRIPTOR (2) +#define USB_STRING_DESCRIPTOR (3) +#define USB_IFACE_DESCRIPTOR (4) +#define USB_ENDPOINT_DESCRIPTOR (5) +#define USB_DEVQUAL_DESCRIPTOR (6) +#define USB_CS_INTERFACE (0x24) +#define USB_CS_ENDPOINT (0x25) + +#define USB_MAX_SUPPORTED_INTERFACES (2) + +/* Implementation Specific Macros */ +#define LINE_CODING_SIZE (0x07) +#define COMM_FEATURE_DATA_SIZE (0x02) + +#define LINE_CODE_DTERATE_IFACE0 (115200) /*e.g 9600 is 0x00002580 */ +#define LINE_CODE_CHARFORMAT_IFACE0 (0x00) /* 1 stop bit */ +#define LINE_CODE_PARITYTYPE_IFACE0 (0x00) /* No Parity */ +#define LINE_CODE_DATABITS_IFACE0 (0x08) /* Data Bits Format */ + +#define LINE_CODE_DTERATE_IFACE1 (9600) /*e.g. 115200 is 0x0001C200*/ +#define LINE_CODE_CHARFORMAT_IFACE1 (0x00) /* 1 stop bit */ +#define LINE_CODE_PARITYTYPE_IFACE1 (0x00) /* No Parity */ +#define LINE_CODE_DATABITS_IFACE1 (0x08) /* Data Bits Format */ + +#define STATUS_ABSTRACT_STATE_IFACE0 (0x0000) /* Disable Multiplexing + ENDP in this interface will + continue to accept/offer data*/ +#define STATUS_ABSTRACT_STATE_IFACE1 (0x0000) /* Disable Multiplexing + ENDP in this interface will + continue to accept/offer data*/ +#define COUNTRY_SETTING_IFACE0 (0x0000) /* Country Code in the format as + defined in [ISO3166] */ +#define COUNTRY_SETTING_IFACE1 (0x0000) /* Country Code in the format as + defined in [ISO3166] */ + +/* Notifications Support */ +#define PSTN_SUBCLASS_NOTIF_SUPPORT (TRUE) +#define WMC_SUBCLASS_NOTIF_SUPPORT (FALSE) +#define CDC_CLASS_NOTIF_SUPPORT (FALSE) + +#define CDC_DESC_ENDPOINT_COUNT (CIC_ENDP_COUNT+(DATA_CLASS_SUPPORT & 0x01) \ + *DIC_ENDP_COUNT) + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef const struct _USB_LANGUAGE +{ + uint_16 const language_id; /* Language ID */ + uint_8 const ** lang_desc; /* Language Descriptor String */ + uint_8 const * lang_desc_size; /* Language Descriptor Size */ +} USB_LANGUAGE; + +typedef const struct _USB_ALL_LANGUAGES +{ + /* Pointer to Supported Language String */ + uint_8 const *languages_supported_string; + /* Size of Supported Language String */ + uint_8 const languages_supported_size; + /* Array of Supported Languages */ + USB_LANGUAGE usb_language[USB_MAX_SUPPORTED_INTERFACES]; +}USB_ALL_LANGUAGES; + +typedef const struct _USB_ENDPOINTS +{ + /* Number of non control Endpoints */ + uint_8 count; + /* Array of Endpoints Structures */ + USB_EP_STRUCT ep[CDC_DESC_ENDPOINT_COUNT]; +}USB_ENDPOINTS; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_Desc_Get_Descriptor( + uint_8 controller_ID, + uint_8 type, + uint_8 str_num, + uint_16 index, + uint_8_ptr *descriptor, + USB_PACKET_SIZE *size); + +extern uint_8 USB_Desc_Get_Interface( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr alt_interface); + + +extern uint_8 USB_Desc_Set_Interface( + uint_8 controller_ID, + uint_8 interface, + uint_8 alt_interface); + +extern boolean USB_Desc_Valid_Configation( + uint_8 controller_ID, + uint_16 config_val); + +extern boolean USB_Desc_Valid_Interface( + uint_8 controller_ID, + uint_8 interface); + +extern boolean USB_Desc_Remote_Wakeup(uint_8 controller_ID); + +extern void* USB_Desc_Get_Endpoints(uint_8 controller_ID); + +extern uint_8 USB_Desc_Get_Line_Coding( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *coding_data); + +extern uint_8 USB_Desc_Set_Line_Coding( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *coding_data); + +extern uint_8 USB_Desc_Get_Abstract_State( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Get_Country_Setting( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Set_Abstract_State( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); +extern uint_8 USB_Desc_Set_Country_Setting( + uint_8 controller_ID, + uint_8 interface, + uint_8_ptr *feature_data); + +#endif + + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h new file mode 100644 index 0000000..80da323 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_devapi.h @@ -0,0 +1,480 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_devapi.h + * + * @author + * + * @version + * + * @date + * + * @brief This file contains S08 USB stack device layer API header function. + * + *****************************************************************************/ + +#ifndef _USB_DEVAPI_H +#define _USB_DEVAPI_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" /* User Defined Data Types */ +#include "hidef.h" /* for EnableInterrupts; macro */ +#include +#include "hal/derivative.h" /* include peripheral declarations */ +#include "usb_user_config.h" /* User Configuration File << EST 'user_config.h' conflicts with MQX Lite */ +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H +#define USB_MAX_EP_BUFFER_SIZE (512) +#else +#define USB_MAX_EP_BUFFER_SIZE (255) +#endif +#else +/* device is Kinetis K20D72 << EST */ +#define USB_MAX_EP_BUFFER_SIZE (512) +#endif +#ifndef CONTROL_ENDPOINT +#define CONTROL_ENDPOINT (0) +#endif + +#define USB_SETUP_PKT_SIZE (8) /* Setup Packet Size */ + +/* Error codes */ +#define USB_OK (0x00) +#define USBERR_ALLOC (0x81) +#define USBERR_BAD_STATUS (0x82) +#define USBERR_CLOSED_SERVICE (0x83) +#define USBERR_OPEN_SERVICE (0x84) +#define USBERR_TRANSFER_IN_PROGRESS (0x85) +#define USBERR_ENDPOINT_STALLED (0x86) +#define USBERR_ALLOC_STATE (0x87) +#define USBERR_DRIVER_INSTALL_FAILED (0x88) +#define USBERR_DRIVER_NOT_INSTALLED (0x89) +#define USBERR_INSTALL_ISR (0x8A) +#define USBERR_INVALID_DEVICE_NUM (0x8B) +#define USBERR_ALLOC_SERVICE (0x8C) +#define USBERR_INIT_FAILED (0x8D) +#define USBERR_SHUTDOWN (0x8E) +#define USBERR_INVALID_PIPE_HANDLE (0x8F) +#define USBERR_OPEN_PIPE_FAILED (0x90) +#define USBERR_INIT_DATA (0x91) +#define USBERR_SRP_REQ_INVALID_STATE (0x92) +#define USBERR_TX_FAILED (0x93) +#define USBERR_RX_FAILED (0x94) +#define USBERR_EP_INIT_FAILED (0x95) +#define USBERR_EP_DEINIT_FAILED (0x96) +#define USBERR_TR_FAILED (0x97) +#define USBERR_BANDWIDTH_ALLOC_FAILED (0x98) +#define USBERR_INVALID_NUM_OF_ENDPOINTS (0x99) +#define USBERR_NOT_SUPPORTED (0x9A) + +#define USBERR_DEVICE_NOT_FOUND (0xC0) +#define USBERR_DEVICE_BUSY (0xC1) +#define USBERR_NO_DEVICE_CLASS (0xC3) +#define USBERR_UNKNOWN_ERROR (0xC4) +#define USBERR_INVALID_BMREQ_TYPE (0xC5) +#define USBERR_GET_MEMORY_FAILED (0xC6) +#define USBERR_INVALID_MEM_TYPE (0xC7) +#define USBERR_NO_DESCRIPTOR (0xC8) +#define USBERR_NULL_CALLBACK (0xC9) +#define USBERR_NO_INTERFACE (0xCA) +#define USBERR_INVALID_CFIG_NUM (0xCB) +#define USBERR_INVALID_ANCHOR (0xCC) +#define USBERR_INVALID_REQ_TYPE (0xCD) + +/* Pipe Types */ +#define USB_CONTROL_PIPE (0x00) +#define USB_ISOCHRONOUS_PIPE (0x01) +#define USB_BULK_PIPE (0x02) +#define USB_INTERRUPT_PIPE (0x03) + +/* Device States */ +#define USB_STATE_UNKNOWN (0xFF) +#define USB_STATE_PENDING_ADDRESS (0x04) +#define USB_STATE_POWERED (0x03) +#define USB_STATE_DEFAULT (0x02) +#define USB_STATE_ADDRESS (0x01) +#define USB_STATE_CONFIG (0x00) +#define USB_STATE_SUSPEND (0x80) + +/* Get_Status Request information for DEVICE */ +#define USB_SELF_POWERED (0x01) +#define USB_REMOTE_WAKEUP (0x02) + +/* Get_Status Request information for OTG (WINDEX = 0xF000) */ +#ifdef OTG_BUILD +#define USB_OTG_HOST_REQUEST_FLAG (0x01) +#endif + +/* Bus Control values */ +#define USB_NO_OPERATION (0x00) +#define USB_ASSERT_BUS_RESET (0x01) +#define USB_DEASSERT_BUS_RESET (0x02) +#define USB_ASSERT_RESUME (0x03) +#define USB_DEASSERT_RESUME (0x04) +#define USB_SUSPEND_SOF (0x05) +#define USB_RESUME_SOF (0x06) + +/* possible values of Status */ +#define USB_STATUS_IDLE (0) +#define USB_STATUS_TRANSFER_ACCEPTED (6) +#define USB_STATUS_TRANSFER_PENDING (2) +#define USB_STATUS_TRANSFER_IN_PROGRESS (3) +#define USB_STATUS_ERROR (4) +#define USB_STATUS_DISABLED (5) +#define USB_STATUS_STALLED (1) +#define USB_STATUS_TRANSFER_QUEUED (7) + +#define USB_STATUS_UNKNOWN (0xFF) + +#define USB_CONTROL_ENDPOINT (0) + +#define USB_RECV (0) +#define USB_SEND (1) + +#define USB_DEVICE_DONT_ZERO_TERMINATE (0x1) + +#define USB_SETUP_DATA_XFER_DIRECTION (0x80) + +#define USB_SPEED_FULL (0) +#define USB_SPEED_LOW (1) +#define USB_SPEED_HIGH (2) + +#define USB_MAX_PKTS_PER_UFRAME (0x6) + +#define USB_TEST_MODE_TEST_PACKET (0x0400) + +/* Available service types */ +/* Services 0 through 15 are reserved for endpoints */ +#define USB_SERVICE_EP0 (0x00) +#define USB_SERVICE_EP1 (0x01) +#define USB_SERVICE_EP2 (0x02) +#define USB_SERVICE_EP3 (0x03) +#define USB_SERVICE_EP4 (0x04) +#define USB_SERVICE_EP5 (0x05) +#define USB_SERVICE_EP6 (0x06) +#define USB_SERVICE_EP7 (0x07) +#define USB_SERVICE_EP8 (0x08) +#define USB_SERVICE_EP9 (0x09) +#define USB_SERVICE_EP10 (0x0A) +#define USB_SERVICE_EP11 (0x0B) +#define USB_SERVICE_EP12 (0x0C) +#define USB_SERVICE_EP13 (0x0d) +#define USB_SERVICE_EP14 (0x0E) +#define USB_SERVICE_EP15 (0x0F) + +#define USB_SERVICE_BUS_RESET (0x10) +#define USB_SERVICE_SUSPEND (0x11) +#define USB_SERVICE_SOF (0x12) +#define USB_SERVICE_RESUME (0x13) +#define USB_SERVICE_SLEEP (0x14) +#define USB_SERVICE_SPEED_DETECTION (0x15) +#define USB_SERVICE_ERROR (0x16) +#define USB_SERVICE_STALL (0x17) +#define USB_SERVICE_MAX (0x18) + +#if 0 /* << EST */ +#if (defined(_MCF51JM128_H) ||defined(_MCF51MM256_H) || (defined _MCF51JE256_H)) + #define USB_SERVICE_MAX_EP USB_SERVICE_EP15 +#else + #ifdef DOUBLE_BUFFERING_USED + #define USB_SERVICE_MAX_EP USB_SERVICE_EP6 + #else + #define USB_SERVICE_MAX_EP USB_SERVICE_EP4 + #endif +#endif +#else +/* device is Kinetis K20D72 << EST */ +#ifdef DOUBLE_BUFFERING_USED + #define USB_SERVICE_MAX_EP USB_SERVICE_EP6 +#else + #define USB_SERVICE_MAX_EP USB_SERVICE_EP4 +#endif +#endif + +/* Informational Request/Set Types */ +/* component parameter in USB_Device_Get/Set_Status */ +#define USB_COMPONENT_DIRECTION_SHIFT (7) +#define USB_COMPONENT_DIRECTION_MASK (0x01) +#define USB_STATUS_DEVICE_STATE (0x01) +#define USB_STATUS_INTERFACE (0x02) +#define USB_STATUS_ADDRESS (0x03) +#define USB_STATUS_CURRENT_CONFIG (0x04) +#define USB_STATUS_SOF_COUNT (0x05) +#define USB_STATUS_DEVICE (0x06) + +// Endpoint attributes +#define EP_TRANSFER_TYPE_CONTROL (0x0<<0) +#define EP_TRANSFER_TYPE_ISOCHRONOUS (0x1<<0) +#define EP_TRANSFER_TYPE_BULK (0x2<<0) +#define EP_TRANSFER_TYPE_INTERRUPT (0x3<<0) + +/* Standard Request Code */ +#define GET_STATUS 0x0 +#define CLEAR_FEATURE 0x1 +#define SET_FEATURE 0x3 +#define SET_ADDRESS 0x5 +#define GET_DESCRIPTOR 0x6 +#define SET_DESCRIPTOR 0x7 +#define GET_CONFIGURATION 0x8 +#define SET_CONFIGURATION 0x9 +#define GET_INTERFACE 0xA +#define SET_INTERFACE 0xB +#define SYNCH_FRAME 0xC + +#ifdef OTG_BUILD + #define USB_STATUS_OTG (0x07) + #define USB_STATUS_TEST_MODE (0x08) +#else + #define USB_STATUS_TEST_MODE (0x07) +#endif + +#define USB_STATUS_ENDPOINT (0x10) +#define USB_STATUS_ENDPOINT_NUMBER_MASK (0x0F) + +#define UNINITIALISED_VAL (0xFFFFFFFF) + +#if 0 /* << EST */ +#if (defined MCU_MK40N512VMD100) || (defined MCU_MK53N512CMD100) || (defined MCU_MK60N512VMD100) || (defined MCU_MK70F12) + #define USB_DEVICE_ASSERT_RESUME() USB0_CTL |= USB_CTL_RESUME_MASK; + #define USB_DEVICE_DEASSERT_RESUME() USB0_CTL &= ~USB_CTL_RESUME_MASK; +#elif (defined _MC9S08JE128_H) || (defined _MC9S08JM16_H) || defined(_MC9S08JM60_H) || (defined _MC9S08JS16_H) || (defined _MC9S08MM128_H) + #define USB_DEVICE_ASSERT_RESUME() CTL_CRESUME = 1; + #define USB_DEVICE_DEASSERT_RESUME() CTL_CRESUME = 0; +#elif (defined _MCF51JE256_H) || (defined MCU_mcf51jf128) || defined(_MCF51MM256_H) + #define USB_DEVICE_ASSERT_RESUME() USBTRC0_USBRESMEN = 1; + #define USB_DEVICE_DEASSERT_RESUME() USBTRC0_USBRESMEN = 0; +#elif (defined __MCF52221_H__) || defined(__MCF52259_H__) + #define USB_DEVICE_ASSERT_RESUME() CTL |= MCF_USB_OTG_CTL_RESUME; + #define USB_DEVICE_DEASSERT_RESUME() CTL &= ~MCF_USB_OTG_CTL_RESUME; +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif + +#define USB_PROCESS_PENDING() ((gu8ProcessPendingFlag != 0) || (gtUSBEPEventFlags != 0)) + + +/****************************************************************************** + * Types + *****************************************************************************/ +typedef void _PTR_ _usb_device_handle; +typedef uint_8 T_EP_BITFIELD; + +#if 0 /* << EST */ +#if !(defined _MC9S08JE128_H) && !(defined _MC9S08JM16_H) && !defined(_MC9S08JM60_H) && !(defined _MC9S08JS16_H) && !(defined _MC9S08MM128_H) +#pragma pack (1) /* Enforce 1 byte struct alignment */ +#endif +#else +#ifndef __HIWARE__ +/* << EST pushing current packing */ +#pragma pack(push) +#pragma pack(1) /* Enforce 1 byte struct alignment */ +#endif +#endif + +#ifdef __MK_xxx_H__ + #if (defined(__CWCC__) || defined(__GNUC__)) + #define ALIGN __attribute__ ((packed)) + #elif((defined __IAR_SYSTEMS_ICC__) || (defined __CC_ARM)) + #define ALIGN + #else + #define ALIGN + #endif +#else + #define ALIGN +#endif + +typedef struct _USB_DEV_EVENT_STRUCT +{ + uint_8 controller_ID; /* controller ID */ + uint_8 ep_num; + boolean setup; /* is setup packet */ + boolean direction; /* direction of endpoint */ + uint_8* buffer_ptr; /* pointer to buffer */ + uint_8 errors; /* Any errors */ + USB_PACKET_SIZE len; /* buffer size of endpoint */ +}ALIGN USB_DEV_EVENT_STRUCT, *PTR_USB_DEV_EVENT_STRUCT; + +// Same endpoint can have multiple function assignments in g_usb_CB, depending on user input +#ifndef MULTIPLE_DEVICES + typedef void(_CODE_PTR_ const USB_SERVICE_CALLBACK)(PTR_USB_DEV_EVENT_STRUCT); +#else + typedef void(_CODE_PTR_ USB_SERVICE_CALLBACK)(PTR_USB_DEV_EVENT_STRUCT); +#endif + +typedef struct _USB_EP_STRUCT +{ + uint_8 ep_num; /* endpoint number */ + uint_8 type; /* type of endpoint */ + uint_8 direction; /* direction of endpoint */ + USB_PACKET_SIZE size ALIGN; /* buffer size of endpoint */ +}ALIGN USB_EP_STRUCT, *USB_EP_STRUCT_PTR; + +#if (defined(__CWCC__))/*||defined(__GNUC__))*/ /* << EST: that pragma does not exist for gcc */ + #pragma options align = reset +#elif defined(__GNUC__) /* << EST */ +/* << EST restoring previous packing */ +#pragma pack(pop) +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__CC_ARM) + #pragma pack() +#endif + + +extern volatile uint_8 gu8ProcessPendingFlag; +extern volatile T_EP_BITFIELD gtUSBEPEventFlags; + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 _usb_device_init ( + uint_8 device_number, + _usb_device_handle _PTR_ handle, + uint_8 number_of_endpoints, + uint_8 bVregEn +); + +extern uint_8 _usb_device_deinit(void); + +extern uint_8 _usb_device_init_endpoint( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_16 max_packet_size, + uint_8 direction, + uint_8 endpoint_type, + uint_8 flag +); + +extern uint_8 _usb_device_cancel_transfer ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern uint_8 _usb_device_deinit_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern uint_8 _usb_device_recv_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint8_ptr buffer_ptr, + uint_32 size +); + +extern uint_8 _usb_device_send_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint8_ptr buffer_ptr, + uint_32 size +); + +extern uint_8 _usb_device_get_send_buffer ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 ep_num, /* [IN] Endpoint number */ + uint_8_ptr *buff_ptr, /* [OUT] Buffer for IN endpoint */ + USB_PACKET_SIZE *size /* [OUT] Size of IN endpoint */ +); + +extern void _usb_device_shutdown ( + _usb_device_handle handle +); + +extern void _usb_device_stall_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_unstall_endpoint ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_read_setup_data ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8_ptr buffer_ptr +); + +extern uint_8 _usb_device_get_status ( + _usb_device_handle handle, + uint_8 component, + uint_8_ptr status +); + +extern uint_8 _usb_device_set_status ( + _usb_device_handle handle, + uint_8 component, + uint_8 setting +); + +extern void _usb_device_clear_data0_endpoint( + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_assert_resume ( + _usb_device_handle handle +); + +extern uint_8 _usb_device_register_service ( + uint_8 controller_ID, + uint_8 type, + USB_SERVICE_CALLBACK service +); + +extern uint_8 _usb_device_unregister_service ( + _usb_device_handle handle, + uint_8 event_endpoint +); + +extern uint_8 _usb_device_get_transfer_status ( + _usb_device_handle handle, + uint_8 endpoint_number, + uint_8 direction +); + +extern void _usb_device_set_address ( + _usb_device_handle handle, + uint_8 address +); + +extern uint_8 USB_Device_Call_Service( + uint_8 type, + PTR_USB_DEV_EVENT_STRUCT event +); + +extern void USB_Engine(void); + +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c new file mode 100644 index 0000000..a346225 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_driver.c @@ -0,0 +1,629 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_driver.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains S08 USB stack device layer implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "usb_devapi.h" /* USB Device Layer API Header File */ +#include "usb_dciapi.h" /* USB Controller API Header File */ +#ifdef _MK_xxx_H_ + #include "usb_dci_kinetis.h" +#endif +#ifndef MULTIPLE_DEVICES + #include "USB_Config.h" +#endif + +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ + + +/**************************************************************************** + * Global Variables + ****************************************************************************/ +extern void USB_Control_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Reset_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Sof_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Resume_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Suspend_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Error_Service (PTR_USB_DEV_EVENT_STRUCT event ); +extern void USB_Stall_Service (PTR_USB_DEV_EVENT_STRUCT event ); + +/* Array of USB Service pointers */ +#ifdef MULTIPLE_DEVICES + static USB_SERVICE_CALLBACK g_usb_CB[USB_SERVICE_MAX]; +#else + static USB_SERVICE_CALLBACK g_usb_CB[USB_SERVICE_MAX] = { + USB_EP0_CALLBACK, + USB_EP1_CALLBACK, + USB_EP2_CALLBACK, + USB_EP3_CALLBACK, + USB_EP4_CALLBACK, + USB_EP5_CALLBACK, + USB_EP6_CALLBACK, + USB_EP7_CALLBACK, + USB_EP8_CALLBACK, + USB_EP9_CALLBACK, + USB_EP10_CALLBACK, + USB_EP11_CALLBACK, + USB_EP12_CALLBACK, + USB_EP13_CALLBACK, + USB_EP14_CALLBACK, + USB_EP15_CALLBACK, + USB_BUS_RESET_CALLBACK, + USB_SUSPEND_CALLBACK, + USB_SOF_CALLBACK, + USB_RESUME_CALLBACK, + USB_SLEEP_CALLBACK, + USB_SPEED_DETECTION_CALLBACK, + USB_ERROR_CALLBACK, + USB_STALL_CALLBACK +}; +#endif +/* Array of USB Component Status */ +/* Test mode is the last service */ +static uint_8 g_usb_component_status[USB_STATUS_TEST_MODE]; +/* Array of USB Endpoint Status */ +static uint_8 g_usb_ep_status[MAX_SUPPORTED_ENDPOINTS]; +/* Current un-initialized non CONTROL Endpoint */ +static uint_8 g_EPn=0; +/* Maximum number of Non CONTROL Endpoint required by upper layer */ +static uint_8 g_EPn_max=0; + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes - None + *****************************************************************************/ +static void USB_Device_Init_Params(void); + +/***************************************************************************** + * Local Variables - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions + *****************************************************************************/ +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/***************************************************************************** + * Global Functions + *****************************************************************************/ +extern uint_8 USB_DCI_DeInit(void); + +/**************************************************************************//*! + * + * @name USB_Device_Init_Params + * + * @brief The function initializes the Device Layer Structures + * + * @param None + * + * @return None + * + ****************************************************************************** + * Initializes USB Device Layer Structures + *****************************************************************************/ +static void USB_Device_Init_Params(void) +{ + uint_8 loop_index=0; + + g_EPn= g_EPn_max; /* 1 control endpoint */ + + /* + Initialize USB_STATUS_DEVICE_STATE, USB_STATUS_INTERFACE, + USB_STATUS_ADDRESS, USB_STATUS_CURRENT_CONFIG, USB_STATUS_SOF_COUNT + and USB_STATUS_DEVICE to USB_STATUS_UNKNOWN + */ + for(loop_index = 0; loop_index < USB_STATUS_TEST_MODE; loop_index++) + { + #ifdef OTG_BUILD + if(loop_index != (USB_STATUS_OTG-1)) /* Do not initialize the OTG status with 0xFFFF */ + #endif + { + g_usb_component_status[loop_index] = USB_STATUS_UNKNOWN; + } + } + + /* Initialize status of All Endpoints to USB_STATUS_DISABLED */ + for(loop_index = 0; loop_index < MAX_SUPPORTED_ENDPOINTS; loop_index++) + { + g_usb_ep_status[loop_index] = USB_STATUS_DISABLED; + } +} + +/***************************************************************************** + * Global Functions + *****************************************************************************/ + + +/**************************************************************************//*! + * + * @name _usb_device_init + * + * @brief The function initializes the Device and Controller layer + * + * @param device_number : USB Device controller to initialize + * @param handle : pointer to USB Device handle + * @param number_of_endpoints : Endpoint count of the application + * + * @return status + * USB_OK : When Successfull + * USBERR_INVALID_NUM_OF_ENDPOINTS : When endpoints > max Supported + ****************************************************************************** + * This function initializes the Device layer and the Controller layer of the + * S08 USB stack. It initializes the variables used for this layer and then + * calls the controller layer initialize function + *****************************************************************************/ +uint_8 _usb_device_init ( + uint_8 device_number, /* [IN] USB Device controller to initialize */ + _usb_device_handle _PTR_ handle, /* [IN] Pointer to USB Device handle */ + uint_8 number_of_endpoints, /* [IN] Number of endpoints to initialize */ + uint_8 bVregEn /* Enables or disables internal regulator */ +) +{ + UNUSED(handle); + + /* validate endpoints param */ + if((number_of_endpoints > MAX_SUPPORTED_ENDPOINTS) || + (number_of_endpoints < MIN_SUPPORTED_ENDPOINTS)) + { + return USBERR_INVALID_NUM_OF_ENDPOINTS; + } + + /* init variables */ + g_EPn_max = (uint_8)(number_of_endpoints - 1); + + USB_Device_Init_Params(); + +#ifdef MULTIPLE_DEVICES + /* Initialize all services to null value */ + Clear_Mem((uint_8_ptr)g_usb_CB, + (uint_32)(sizeof(USB_SERVICE_CALLBACK) * USB_SERVICE_MAX), (uint_8)0); +#endif + /* Call controller layer initialization function */ + return USB_DCI_Init(device_number, bVregEn); + +} + +/**************************************************************************//*! + * + * @name _usb_device_deinit + * + * @brief The function de-initializes the Device and Controller layer + * + * @return status + * USB_OK : When Successfull + * USBERR_INVALID_NUM_OF_ENDPOINTS : When endpoints > max Supported + ****************************************************************************** + * This function de-initializes the Device layer and the Controller layer + *****************************************************************************/ +uint_8 _usb_device_deinit(void) +{ + g_EPn_max = 0; + /* Call controller layer de-initialization function */ + return USB_DCI_DeInit(); +} + +/**************************************************************************//*! + * + * @name _usb_device_init_endpoint + * + * @brief The function initializes the endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param max_packet_size : Maximum packet size (in bytes) for the endpoint + * @param direction : Direction of transfer + * @param endpoint_type : Type of endpoint + * @param flag : Zero termination flag + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_INIT_FAILED : When endpoints > max Supported + ****************************************************************************** + * + * This function initializes an endpoint the Device layer and the Controller + * layer in the S08 USB stack. It validate whether all endpoints have already + * been initialized or not and then calls the controller layer endpoint + * initialize function + * + *****************************************************************************/ +uint_8 _usb_device_init_endpoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number*/ + uint_16 max_packet_size, /* [IN] Maximum packet size (in bytes) for the endpoint */ + uint_8 direction, /* [IN] Direction of transfer */ + uint_8 endpoint_type, /* [IN] Type of endpoint */ + uint_8 flag /* [IN] Zero termination flag */ +) +{ + USB_EP_STRUCT ep_str; + + uint_8 status = USB_OK; + + /* check if all endpoint have already been initialised */ + if((g_EPn == 0) && (endpoint_number != CONTROL_ENDPOINT)) + { + return USBERR_EP_INIT_FAILED; + } + + ep_str.direction = direction; + ep_str.ep_num = endpoint_number; + +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H + ep_str.size = max_packet_size; +#else + ep_str.size = (char)max_packet_size; +#endif +#else +/* device is Kinetis K20D72 << EST */ + ep_str.size = max_packet_size; +#endif + + ep_str.type = endpoint_type; + + /* call controller layer for initiazation */ + status = USB_DCI_Init_EndPoint(*((uint_8*)handle), &ep_str, flag); + + /* if endpoint successfully initialised update counter */ + if((ep_str.ep_num != CONTROL_ENDPOINT) && (status == USB_OK)) + { + g_EPn--; + } + + return status; +} + + +/**************************************************************************//*! + * + * @name _usb_device_deinit_endpoint + * + * @brief The function de-initializes the endpoint + * + * @param handle : USB Device handle + * @param endpoint_number : Endpoint number + * @param direction : Endpoint direction + * + * @return status + * USB_OK : When Successfull + * USBERR_EP_DEINIT_FAILED : When endpoints > max Supported + ****************************************************************************** + * + * This function deinitializes an endpoint the Device layer and the Controller + * layer in the S08 USB stack. It validate whether all endpoints have already + * been deinitialized or not and then calls the controller layer endpoint + * deinitialize function + * + *****************************************************************************/ +uint_8 _usb_device_deinit_endpoint ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 endpoint_number, /* [IN] Endpoint number */ + uint_8 direction /* [IN] Direction */ +) +{ + uint_8 status=USB_OK; + + /* check if all endpoint have already been initialised */ + if((g_EPn == g_EPn_max) && (endpoint_number != CONTROL_ENDPOINT)) + { + return USBERR_EP_DEINIT_FAILED; + } + + /* call controller layer for initiazation */ + status = USB_DCI_Deinit_EndPoint(*((uint_8*)handle), endpoint_number, direction); + + /* if endpoint successfully deinitialised update counter */ + if((endpoint_number != CONTROL_ENDPOINT) && (status == USB_OK)) + { + g_EPn++; + } + + return status; +} + +/**************************************************************************//*! + * + * @name _usb_device_get_status + * + * @brief The function retrieves various endpoint as well as USB component status + * + * @param handle : USB Device handle + * @param component : USB component + * @param status : Pointer to 16 bit return value + * + * @return status + * USB_OK : When Successfull + * USBERR_BAD_STATUS : When error + * + ****************************************************************************** + * This function retrieves the endpoint as well USB component status which is + * stored by calling USB_Device_Set_Status. This function can be called by Ap- + * plication as well as the DCI layer. + *****************************************************************************/ +uint_8 _usb_device_get_status ( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 component, /* [IN] USB component */ + uint_8_ptr status /* [OUT] Pointer to 16 bit return value */ +) +{ + /* get the endpoint number from component input variable */ + uint_8 ep_num = (uint_8)(component & USB_STATUS_ENDPOINT_NUMBER_MASK); + UNUSED (handle); + + if((component <= USB_STATUS_TEST_MODE) && + (component >= USB_STATUS_DEVICE_STATE)) + { + /* Get the corresponding component status + -1 as components start from 1 */ + *status = g_usb_component_status[component-1]; + } + else if((component & USB_STATUS_ENDPOINT) && + (ep_num < MAX_SUPPORTED_ENDPOINTS)) + { + /* Get the corresponding endpoint status */ + *status = g_usb_ep_status[ep_num]; + } + else + { + return USBERR_BAD_STATUS; + } + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name _usb_device_set_status + * + * @brief The function saves status of endpoints as well as USB components. + * + * @param handle : USB Device handle + * @param component : USB component + * @param setting : Value to be set + * + * @return status + * USB_OK : When Successfull + * USBERR_BAD_STATUS : When error + * + ****************************************************************************** + * This function sets the endpoint as well USB component status which can be + * retrieved by calling _usb_device_get_status. This function can be called by + * Application as well as the DCI layer. + *****************************************************************************/ +uint_8 _usb_device_set_status( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 component, /* [IN] USB Component status to set */ + uint_8 setting /* [IN] Status to set */ +) +{ + /* get the endpoint number from component input variable */ + uint_8 ep_num = (uint_8)(component & USB_STATUS_ENDPOINT_NUMBER_MASK); + UNUSED (handle); + + if((component <= USB_STATUS_TEST_MODE) && + (component >= USB_STATUS_DEVICE_STATE)) + { + /* + Set the corresponding component setting + -1 as components start from 1 + */ + g_usb_component_status[component-1] = setting; + } + else if((component & USB_STATUS_ENDPOINT) && + (ep_num < MAX_SUPPORTED_ENDPOINTS)) + { + uint_8 direction = + (uint_8)((component >> USB_COMPONENT_DIRECTION_SHIFT) & + USB_COMPONENT_DIRECTION_MASK); + /* HALT Endpoint */ + if(setting == USB_STATUS_STALLED) + { + _usb_device_stall_endpoint(handle, ep_num, direction); + } + else if((setting == USB_STATUS_IDLE) && + (g_usb_ep_status[ep_num] == USB_STATUS_STALLED)) + { + _usb_device_unstall_endpoint(handle, ep_num, direction); + + if(ep_num == CONTROL_ENDPOINT) + { + direction = (uint_8)((direction == USB_SEND)? + (USB_RECV):(USB_SEND)); + _usb_device_unstall_endpoint(handle, ep_num, direction); + } + } + /* Set the corresponding endpoint setting */ + g_usb_ep_status[ep_num] = setting; + } + else + { + return USBERR_BAD_STATUS; + } + return USB_OK; +} + +/**************************************************************************//*! + * + * @name _usb_device_register_service + * + * @brief The function registers a callback function from the Application layer + * + * @param controller_ID : Controller ID + * @param type : event type or endpoint number + * @param service : callback function pointer + * + * @return status + * USB_OK : When Successfull + * USBERR_ALLOC_SERVICE : When invalid type or already registered + * + ****************************************************************************** + * This function registers a callback function from the application if it is + * called not already registered so that the registered callback function can + * be if the event of that type occurs + *****************************************************************************/ +uint_8 _usb_device_register_service( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 type, /* [IN] type of event or endpoint + number to service */ + USB_SERVICE_CALLBACK service /* [IN] pointer to callback + function */ +) +{ + UNUSED (controller_ID); + UNUSED (service); +#ifdef MULTIPLE_DEVICES + /* check if the type is valid and callback for the type + is not already registered */ + if(((type <= USB_SERVICE_MAX_EP) || + ((type < USB_SERVICE_MAX) && (type >= USB_SERVICE_BUS_RESET))) && + (g_usb_CB[type] == NULL)) + { + + /* register the callback function */ + g_usb_CB[type] = service; + return USB_OK; + } + else + { + return USBERR_ALLOC_SERVICE; + } +#else + UNUSED(type); + return USB_OK; +#endif + +} + +/**************************************************************************//*! + * + * @name _usb_device_unregister_service + * + * @brief The function unregisters an event or endpoint callback function + * + * @param handle : USB Device handle + * @param event_endpoint : event type or endpoint number + * + * @return status + * USB_OK : When Successfull + * USBERR_UNKNOWN_ERROR : When invalid type or not registered + * + ***************************************************************************** + * This function un registers a callback function which has been previously + * registered by the application layer + *****************************************************************************/ +uint_8 _usb_device_unregister_service( + _usb_device_handle handle, /* [IN] USB Device handle */ + uint_8 event_endpoint /* [IN] Endpoint (0 through 15) or event to service */ +) +{ + UNUSED (handle); + /* check if the type is valid and callback for the type + is already registered */ + if(((event_endpoint <= USB_SERVICE_MAX_EP) || + ((event_endpoint < USB_SERVICE_MAX) && (event_endpoint >= USB_SERVICE_BUS_RESET))) && + (g_usb_CB[event_endpoint] != NULL)) + { +#ifdef MULTIPLE_DEVICES + /* unregister the callback */ + g_usb_CB[event_endpoint] = NULL; +#endif + return USB_OK; + } + else + { + return USBERR_UNKNOWN_ERROR; + } +} + +/**************************************************************************//*! + * + * @name USB_Device_Call_Service + * + * @brief The function is a device layer event handler + * + * @param type : Type of service or endpoint + * @param event : Pointer to event structure + * + * @return status + * USB_OK : Always + * + ***************************************************************************** + * + * This function calls the registered service callback function of the applic- + * ation layer based on the type of event received. This function is called + * from the DCI layer. + * + *****************************************************************************/ +uint_8 USB_Device_Call_Service( + uint_8 type, /* [IN] Type of service or endpoint */ + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to event structure */ +) +{ + + if(type == USB_SERVICE_BUS_RESET) + { /* if it is an reset interrupt then reset all status structures */ + USB_Device_Init_Params(); + } + + /* check if the callback is registered or not */ + if(g_usb_CB[type] != NULL) + { + /* call the callback function */ + g_usb_CB[type](event); + } + + return USB_OK; +} + +void USB_NULL_CALLBACK (PTR_USB_DEV_EVENT_STRUCT event) +{ + UNUSED(event); + + #if (defined(__CWCC__) || defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)) + asm("nop"); + #elif defined (__CC_ARM) + __nop(); + #endif +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c new file mode 100644 index 0000000..e2239e7 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.c @@ -0,0 +1,1177 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_framework.c + * + * @author + * + * @version + * + * @date + * + * @brief The file contains USB stack framework module implementation. + * + *****************************************************************************/ + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" /* Contains User Defined Data Types */ +#include "usb_class.h" /* USB class Header File */ +#include "usb_framework.h" /* USB Framework Header File */ +#include "usb_descriptor.h" /* USB descriptor Header File */ +#if defined(__IAR_SYSTEMS_ICC__) +#include +#endif +#ifdef OTG_BUILD +#include "usb_otg_main.h" /* OTG header file */ +#endif +#include +/***************************************************************************** + * Constant and Macro's + *****************************************************************************/ +/**************************************************************************** + * Global Variables + ****************************************************************************/ +static USB_SETUP_STRUCT g_setup_pkt; + +/*is used to store the value of data which needs to be sent to the USB +host in response to the standard requests.*/ +static uint_16 g_std_framework_data; +/*used to store the address received in Set Address in the standard request.*/ +static uint_8 g_assigned_address; +/* Framework module callback pointer */ +static USB_CLASS_CALLBACK g_framework_callback=NULL; +/* Other Requests Callback pointer */ +static USB_REQ_FUNC g_other_req_callback=NULL; + +#ifdef DELAYED_PROCESSING +static USB_DEV_EVENT_STRUCT g_f_event; +/* initially no pending request */ +static boolean g_control_pending=FALSE; +#endif + + +boolean const g_validate_request[MAX_STRD_REQ][3] = +{ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Get_Status*/ + /* configured state: valid for existing interfaces/endpoints + address state : valid only for interface or endpoint 0 + default state : not specified + */ + {TRUE,TRUE,FALSE}, /* Clear Feature */ + /* configured state: valid only for device in configured state + address state : valid only for device (in address state), + interface and endpoint 0 + default state : not specified + */ + {FALSE,FALSE,FALSE}, /*reserved for future use*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ +#ifdef OTG_BUILD + {TRUE,TRUE,TRUE}, /* Set Feature */ + /* configured state: A B-device that supports OTG features + address state : shall be able to accept the SetFeature command + default state : in the Default, Addressed and Configured states + */ +#else + {TRUE,TRUE,FALSE}, /* Set Feature */ + /* configured state: valid only for device in configured state + address state : valid only for interface or endpoint 0 + default state : not specified + */ +#endif + + {FALSE,FALSE,FALSE},/*reserved for future use*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ + {FALSE,TRUE,TRUE}, /*USB_Strd_Req_Set_Address*/ + /* configured state: not specified + address state : changes to default state if specified addr == 0, + but uses newly specified address + default state : changes to address state if specified addr != 0 + */ + {TRUE,TRUE,TRUE}, /*USB_Strd_Req_Get_Descriptor*/ + /* configured state: valid request + address state : valid request + default state : valid request + */ + {FALSE,FALSE,FALSE}, /*Set Descriptor*/ + /* configured state: request not supported + address state : request not supported + default state : request not supported + */ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Get_Config*/ + /* configured state: bConfiguration Value of current config returned + address state : value zero must be returned + default state : not specified + */ + {TRUE,TRUE,FALSE}, /*USB_Strd_Req_Set_Config*/ + /* configured state: If the specified configuration value is zero, + then the device enters the Address state.If the + specified configuration value matches the + configuration value from a config descriptor, + then that config is selected and the device + remains in the Configured state. Otherwise, the + device responds with a Request Error. + + address state : If the specified configuration value is zero, + then the device remains in the Address state. If + the specified configuration value matches the + configuration value from a configuration + descriptor, then that configuration is selected + and the device enters the Configured state. + Otherwise,response is Request Error. + default state : not specified + */ + {TRUE,FALSE,FALSE}, /*USB_Strd_Req_Get_Interface*/ + /* configured state: valid request + address state : request error + default state : not specified + */ + {TRUE,FALSE,FALSE}, /*USB_Strd_Req_Set_Interface*/ + /* configured state: valid request + address state : request error + default state : not specified + */ + {TRUE,FALSE,FALSE} /*USB_Strd_Req_Sync_Frame*/ + /* configured state: valid request + address state : request error + default state : not specified + */ +}; +/***************************************************************************** + * Global Functions Prototypes - None + *****************************************************************************/ + +/***************************************************************************** + * Local Types - None + *****************************************************************************/ + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ +void USB_Control_Service (PTR_USB_DEV_EVENT_STRUCT event ); +static void USB_Control_Service_Handler(uint_8 controller_ID, + uint_8 status, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Status(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Feature(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Address(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Assign_Address(uint_8 controller_ID); +static uint_8 USB_Strd_Req_Get_Config(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Config(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Interface(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Set_Interface(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Sync_Frame(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); +static uint_8 USB_Strd_Req_Get_Descriptor(uint_8 controller_ID, + USB_SETUP_STRUCT * setup_packet, + uint_8_ptr *data, + USB_PACKET_SIZE *size); + +#ifdef DELAYED_PROCESSING +static void USB_Control_Service_Callback(PTR_USB_DEV_EVENT_STRUCT event ); +#endif + +/***************************************************************************** + * Local Functions Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Local Variables + *****************************************************************************/ + +/* used for extended OUT transactions on CONTROL ENDPOINT*/ +static USB_SETUP_STRUCT ext_req_to_host_setup; +static uint_8 ext_req_to_host_buffer[USB_OUT_PKT_SIZE]; + + +/***************************************************************************** + * Global Variables + *****************************************************************************/ +USB_REQ_FUNC +#if 0 /* << EST */ +#if ((!defined(_MC9S08MM128_H)) && (!defined(_MC9S08JE128_H))) +const +#endif +#else +/* device is Kinetis K20D72 << EST */ +const +#endif +g_standard_request[MAX_STRD_REQ] = +{ + USB_Strd_Req_Get_Status, + USB_Strd_Req_Feature, + NULL, + USB_Strd_Req_Feature, + NULL, + USB_Strd_Req_Set_Address, + USB_Strd_Req_Get_Descriptor, + NULL, + USB_Strd_Req_Get_Config, + USB_Strd_Req_Set_Config, + USB_Strd_Req_Get_Interface, + USB_Strd_Req_Set_Interface, + USB_Strd_Req_Sync_Frame +}; + +#if 0 /* << EST */ +#if (defined(_MC9S08MM128_H) || defined(_MC9S08JE128_H)) +#pragma CODE_SEG DEFAULT +#endif +#else +/* device is Kinetis K20D72 << EST */ +#endif +/**************************************************************************//*! + * + * @name USB_Framework_Init + * + * @brief The function initializes the Class Module + * + * @param controller_ID : Controller ID + * @param class_callback : Class callback pointer + * @param other_req_callback: Other Request Callback + * + * @return status + * USB_OK : When Successfull + * Others : Errors + * + ****************************************************************************** + * This function registers the service on the control endpoint + *****************************************************************************/ +uint_8 USB_Framework_Init ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_CLASS_CALLBACK class_callback, /* Class Callback */ + USB_REQ_FUNC other_req_callback /* Other Request Callback */ +) +{ + uint_8 error=USB_OK; + + /* save input parameters */ + g_framework_callback = class_callback; + g_other_req_callback = other_req_callback; + + /* Register CONTROL service */ + error = _usb_device_register_service(controller_ID, USB_SERVICE_EP0, + +#ifdef DELAYED_PROCESSING + USB_Control_Service_Callback +#else + USB_Control_Service +#endif + ); + + return error; +} + +/**************************************************************************//*! + * + * @name USB_Framework_DeInit + * + * @brief The function De-initializes the Class Module + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * Others : Errors + * + ****************************************************************************** + * This function unregisters control service + *****************************************************************************/ +uint_8 USB_Framework_DeInit +( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + uint_8 error; + /* Free framwork_callback */ + g_framework_callback = NULL; + + /* Free other_req_callback */ + g_other_req_callback = NULL; + + /* Unregister CONTROL service */ + error = _usb_device_unregister_service(&controller_ID, USB_SERVICE_EP0); + + /* Return error */ + return error; +} +#ifdef DELAYED_PROCESSING +/**************************************************************************//*! + * + * @name USB_Framework_Periodic_Task + * + * @brief The function is called to respond to any control request + * + * @param None + * + * @return None + * + ****************************************************************************** + * This function checks for any pending requests and handles them if any + *****************************************************************************/ +void USB_Framework_Periodic_Task(void) +{ + /* if control request pending to be completed */ + if(g_control_pending==TRUE) + { + /* handle pending control request */ + USB_Control_Service(&g_f_event); + g_control_pending = FALSE; + } +} +#endif +/**************************************************************************//*! + * + * @name USB_Framework_Reset + * + * @brief The function resets the framework + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK : When Successfull + * + ****************************************************************************** + * This function is used to reset the framework module + *****************************************************************************/ +uint_8 USB_Framework_Reset ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + UNUSED (controller_ID); + return USB_OK; +} + +#ifdef DELAYED_PROCESSING +/**************************************************************************//*! + * + * @name USB_Control_Service_Callback + * + * @brief The function can be used as a callback function to the service. + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * This function saves the event parameters and queues a pending request + *****************************************************************************/ +void USB_Control_Service_Callback ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + /* save the event parameters */ + g_f_event.buffer_ptr = event->buffer_ptr; + g_f_event.controller_ID = event->controller_ID; + g_f_event.ep_num = event->ep_num; + g_f_event.setup = event->setup; + g_f_event.len = event->len; + g_f_event.errors = event->errors; + + /* set the pending request flag */ + g_control_pending = TRUE; + +} +#endif + +/**************************************************************************//*! + * + * @name USB_Control_Service + * + * @brief Called upon a completed endpoint 0 transfer + * + * @param event : Pointer to USB Event Structure + * + * @return None + * + ****************************************************************************** + * This function handles the data sent or received on the control endpoint + *****************************************************************************/ +void USB_Control_Service ( + PTR_USB_DEV_EVENT_STRUCT event /* [IN] Pointer to USB Event Structure */ +) +{ + uint_8 device_state = 0; + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_8_ptr data = NULL; + USB_PACKET_SIZE size; + + /* get the device state */ + (void)_usb_device_get_status(&(event->controller_ID), USB_STATUS_DEVICE_STATE, + &device_state); + + if(event->setup == TRUE) + { + /* get the setup packet */ + (void)memcpy(&g_setup_pkt, event->buffer_ptr, USB_SETUP_PKT_SIZE); + + /* take care of endianess of the 16 bt fields correctly */ + g_setup_pkt.index = BYTE_SWAP16(g_setup_pkt.index); + g_setup_pkt.value = BYTE_SWAP16(g_setup_pkt.value); + g_setup_pkt.length = BYTE_SWAP16(g_setup_pkt.length); + + /* if the request is standard request */ + if((g_setup_pkt.request_type & USB_REQUEST_CLASS_MASK) == + USB_REQUEST_CLASS_STRD) + { + /* if callback is not NULL */ + if(g_standard_request[g_setup_pkt.request] != NULL) + { + /* if the request is valid in this device state */ + if((device_state < USB_STATE_POWERED) && + (g_validate_request[g_setup_pkt.request][device_state] + ==TRUE)) + { + /* Standard Request function pointers */ + status = g_standard_request[g_setup_pkt.request] + (event->controller_ID, &g_setup_pkt, &data, + (USB_PACKET_SIZE *)&size); + } + } + } + else /* for Class/Vendor requests */ + { + /*get the length from the setup_request*/ + size = (USB_PACKET_SIZE)g_setup_pkt.length; + if(size <= USB_OUT_PKT_SIZE) { + if( (size != 0) && + ((g_setup_pkt.request_type & USB_DATA_DIREC_MASK) == + USB_DATA_TO_DEVICE) ) + { + (void)memcpy(&ext_req_to_host_setup, &g_setup_pkt, USB_SETUP_PKT_SIZE); + + /* expecting host to send data (OUT TRANSACTION)*/ + (void)_usb_device_recv_data(&(event->controller_ID), + CONTROL_ENDPOINT, ext_req_to_host_buffer, + (USB_PACKET_SIZE)(size)); + return; + } + else if(g_other_req_callback != NULL)/*call class/vendor request*/ + { + status = g_other_req_callback(event->controller_ID, + &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + } + } + else + { + /* incase of error Stall endpoint */ + USB_Control_Service_Handler(event->controller_ID, + USBERR_INVALID_REQ_TYPE, &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + return; + } + } + + USB_Control_Service_Handler(event->controller_ID, + status, &g_setup_pkt, &data, (USB_PACKET_SIZE*)&size); + } + /* if its not a setup request */ + else if(device_state == USB_STATE_PENDING_ADDRESS) + { + /* Device state is PENDING_ADDRESS */ + /* Assign the new adddress to the Device */ + (void)USB_Strd_Req_Assign_Address(event->controller_ID); + return; + } + else if( ((g_setup_pkt.request_type & + USB_DATA_DIREC_MASK) == USB_DATA_TO_DEVICE) && + (event->direction == USB_RECV) ) + { + /* execution enters Control Service because of + OUT transaction on CONTROL_ENDPOINT*/ + if(g_other_req_callback != NULL) + { /* class or vendor request */ + size = (USB_PACKET_SIZE)(event->len + USB_SETUP_PKT_SIZE); + status = g_other_req_callback(event->controller_ID, + &ext_req_to_host_setup, &data, + &size); + } + + USB_Control_Service_Handler(event->controller_ID, + status, &g_setup_pkt, &data, + (USB_PACKET_SIZE*)&size); + } + return; +} + +/**************************************************************************//*! + * + * @name USB_Control_Service_Handler + * + * @brief The function is used to send a response to the Host based. + * + * @param controller_ID : Controller ID + * @param status : Status of request + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return None + * + ****************************************************************************** + * This function sends a response to the data received on the control endpoint. + * the request is decoded in the control service + *****************************************************************************/ +static void USB_Control_Service_Handler ( + uint_8 controller_ID, /* [IN] Controller ID */ + uint_8 status, /* [IN] Device Status */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + if(status == USBERR_INVALID_REQ_TYPE) + { + /* incase of error Stall endpoint */ + (void)_usb_device_set_status(&controller_ID, + (uint_8)(USB_STATUS_ENDPOINT | CONTROL_ENDPOINT | + (USB_SEND << USB_COMPONENT_DIRECTION_SHIFT)), + USB_STATUS_STALLED); + } + else /* Need to send Data to the USB Host */ + { + /* send the data prepared by the handlers.*/ + if(*size > setup_packet->length) + { + *size = (USB_PACKET_SIZE)setup_packet->length; + } + + /* send the data to the host */ + (void)USB_Class_Send_Data(controller_ID, + CONTROL_ENDPOINT, *data, *size); + if((setup_packet->request_type & USB_DATA_DIREC_MASK) == + USB_DATA_TO_HOST) + { /* Request was to Get Data from device */ + /* setup rcv to get status from host */ + (void)_usb_device_recv_data(&controller_ID, + CONTROL_ENDPOINT,NULL,0); + } + + } + return; +} +/*************************************************************************//*! + * + * @name USB_Strd_Req_Get_Status + * + * @brief This function is called in response to Get Status request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is called by the host to know the status of the + * device, the interface and the endpoint + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Status ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8_ptr pu8ConfigDesc = NULL; + uint_16 u16DescSize; + uint_8 interface, endpoint = 0; + uint_8 status; + uint_8 device_state = USB_STATE_POWERED; + + + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE_STATE, &device_state); + + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_DEVICE) + { + #ifdef OTG_BUILD + if(setup_packet->index == USB_WINDEX_OTG_STATUS_SEL) + { + uint_8 temp; + /* Request for Device */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_OTG, &temp); + g_std_framework_data = (uint_16)temp; + g_std_framework_data &= GET_STATUS_OTG_MASK; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *size = OTG_STATUS_SIZE; + } + else + #endif + { + uint_8 device_state1; + + /* Request for Device */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_state1); + g_std_framework_data = (uint_16)device_state1; + g_std_framework_data &= GET_STATUS_DEVICE_MASK; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + + /* Set Self Powered bit in device state according to configuration */ + status = USB_Desc_Get_Descriptor(controller_ID, USB_CONFIG_DESCRIPTOR, + 0, 0, &pu8ConfigDesc, (USB_PACKET_SIZE *)&u16DescSize); + + if((pu8ConfigDesc[7] & SELF_POWERED) != 0) + { + g_std_framework_data |= BYTE_SWAP16(0x0001); + } + else + { + g_std_framework_data &= BYTE_SWAP16(~0x0001); + } + *size = DEVICE_STATUS_SIZE; + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_INTERFACE) + { + /* Request for Interface */ + interface = (uint_8) setup_packet->index; + if((device_state == USB_STATE_ADDRESS) && (interface > 0)) + { + status = USBERR_INVALID_REQ_TYPE; + } + else + { + /* Interface requests always return 0 */ + g_std_framework_data = 0x0000; + *size = INTERFACE_STATUS_SIZE; + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_ENDPOINT) + { + /* Request for Endpoint */ + if((device_state == USB_STATE_ADDRESS) && (endpoint > 0)) + { + status = USBERR_INVALID_REQ_TYPE; + } + else + { + uint_8 device_state2; + endpoint = (uint_8)(((uint_8) setup_packet->index) | + USB_STATUS_ENDPOINT); + status = _usb_device_get_status(&controller_ID, + endpoint, + &device_state2); + g_std_framework_data = (uint_16)device_state2; + /* All other fields except HALT must be zero */ + g_std_framework_data &= 0x0001; /* LSB is for the HALT feature */ + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *size = ENDP_STATUS_SIZE; + } + } + + *data = (uint_8_ptr)&g_std_framework_data; + return status; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Feature + * + * @brief This function is called in response to Clear or Set Feature request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request, used to set/clear a feature on the device + * (device_remote_wakeup and test_mode) or on the endpoint(ep halt) + *****************************************************************************/ +static uint_8 USB_Strd_Req_Feature ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 device_status; + uint_8 set_request; + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_8 epinfo; + uint_8 event; + + UNUSED (data); + + *size=0; + /* Find whether its a clear feature request or a set feature request */ + set_request = (uint_8)((setup_packet->request & USB_SET_REQUEST_MASK) >> 1 ); + + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_DEVICE) + { + /* Request for Device */ + if(set_request == TRUE) + { + /* Standard Feature Selector */ + if((setup_packet->value == DEVICE_FEATURE_REMOTE_WAKEUP) || (setup_packet->value == DEVICE_FEATURE_TEST_MODE)) + { + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_status); + + if(status == USB_OK) + { + /* Add the request to be set to the device_status */ + device_status |= (uint_16)(1 << (uint_8)setup_packet->value); + + /* Set the status on the device */ + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE, device_status); + } + } + #ifdef OTG_BUILD + /* OTG Feature Selector */ + else if(setup_packet->value == DEVICE_SET_FEATURE_B_HNP_ENABLE) + { + OTG_DESCRIPTOR_PTR_T otg_desc_ptr; + USB_PACKET_SIZE size; + + status = USB_Desc_Get_Descriptor(controller_ID, USB_OTG_DESCRIPTOR,(uint_8)UNINITIALISED_VAL, + (uint_16)UNINITIALISED_VAL,(uint_8_ptr *)&otg_desc_ptr,&size); + if(status == USB_OK) + { + if(otg_desc_ptr->bmAttributes & USB_OTG_HNP_SUPPORT) + { + _usb_otg_hnp_enable(controller_ID, set_request); + } + } + } + #endif + else + { + status = USBERR_INVALID_REQ_TYPE; + } + } + else //(set_request == FALSE) it is a clear feature request + { + if(setup_packet->value == DEVICE_FEATURE_REMOTE_WAKEUP) + { + status = _usb_device_get_status(&controller_ID, USB_STATUS_DEVICE, &device_status); + + if(status == USB_OK) + { + /* Remove the request to be cleared from device_status */ + device_status &= (uint_16)~(1 << (uint_8)setup_packet->value); + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE, device_status); + } + } + else + { + status = USBERR_INVALID_REQ_TYPE; + } + } + } + else if((setup_packet->request_type & USB_REQUEST_SRC_MASK) == USB_REQUEST_SRC_ENDPOINT) + { + /* Request for Endpoint */ + epinfo = (uint_8)(setup_packet->index & 0x00FF); + status = _usb_device_set_status(&controller_ID, (uint_8)(epinfo|USB_STATUS_ENDPOINT), set_request); + + event = (uint_8)(set_request ? USB_APP_EP_STALLED : USB_APP_EP_UNSTALLED); + + if(setup_packet->request == CLEAR_FEATURE) + { + uint_8 epnum = epinfo & 0x0F; + uint_8 dir = (epinfo & 0x80) >> 7; + _usb_device_clear_data0_endpoint(epnum,dir); + event = USB_APP_EP_UNSTALLED; // as far as the application is concerned, this is an UNSTALL. + } + + /* Inform the upper layers of stall/unstall */ + g_framework_callback(controller_ID,event,(void*)&epinfo); + } + return status; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Address + * + * @brief This function is called in response to Set Address request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request, saves the new address in a global variable. this + * address is assigned to the device after this transaction completes + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Address ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + UNUSED (data); + *size=0; + /* update device state */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE, USB_STATE_PENDING_ADDRESS); + + /*store the address from setup_packet into assigned_address*/ + g_assigned_address = (uint_8)setup_packet->value; + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Assign_Address + * + * @brief This function assigns the address to the Device + * + * @param controller_ID : Controller ID + * + * @return status + * USB_OK: Always + * + ****************************************************************************** + * This function assigns the new address and is called (from the control + * service) after the set address transaction completes + *****************************************************************************/ +static uint_8 USB_Strd_Req_Assign_Address ( + uint_8 controller_ID /* [IN] Controller ID */ +) +{ + /* Set Device Address */ + (void)_usb_device_set_address(&controller_ID, g_assigned_address); + + /* Set Device state */ + (void)_usb_device_set_status(&controller_ID, + USB_STATUS_DEVICE_STATE, USB_STATE_ADDRESS); + /* Set Device state */ + (void)_usb_device_set_status(&controller_ID, USB_STATUS_ADDRESS, + g_assigned_address); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Get_Config + * + * @brief This function is called in response to Get Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : Always + * + ****************************************************************************** + * This is a ch9 request and is used to know the currently used configuration + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Config ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 device_status; + + UNUSED(setup_packet); + + *size = CONFIG_SIZE; + (void)_usb_device_get_status(&controller_ID, USB_STATUS_CURRENT_CONFIG, &device_status); + g_std_framework_data = (uint_16)device_status; + g_std_framework_data = BYTE_SWAP16(g_std_framework_data); + *data = (uint_8_ptr)(&g_std_framework_data); + + return USB_OK; +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Config + * + * @brief This function is called in response to Set Config request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used by the host to set the new configuration + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Config ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status = USBERR_INVALID_REQ_TYPE; + uint_16 config_val; + + UNUSED (data); + *size = 0; + status = USB_STATUS_ERROR; + config_val = setup_packet->value; + + if(USB_Desc_Valid_Configation(controller_ID, config_val)) + /*if valid configuration (fn returns boolean value)*/ + { + uint_8 device_state = USB_STATE_CONFIG; + + /* if config_val is 0 */ + if(!config_val) + { + device_state = USB_STATE_ADDRESS ; + } + + status = _usb_device_set_status(&controller_ID, USB_STATUS_DEVICE_STATE, + device_state); + status = _usb_device_set_status(&controller_ID, + USB_STATUS_CURRENT_CONFIG, (uint_8)config_val); + /* + Callback to the app. to let the application know about the new + Configuration + */ + g_framework_callback(controller_ID,USB_APP_CONFIG_CHANGED, + (void *)&config_val); + g_framework_callback(controller_ID,USB_APP_ENUM_COMPLETE, NULL); + } + + return status; + } + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Get_Interface + * + * @brief This function is called in response to Get Interface request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used to know the current interface + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + + /* Request type not for interface */ + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) != USB_REQUEST_SRC_INTERFACE) + { + return USB_STATUS_ERROR; + } + else + { + *size = INTERFACE_SIZE; + status = USB_Desc_Get_Interface(controller_ID,(uint_8)setup_packet->index, + (uint_8_ptr)&g_std_framework_data); + *data = (uint_8_ptr)&g_std_framework_data; + + return status; + } +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Set_Interface + * + * @brief This function is called in response to Set Interface request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : Always + * + ****************************************************************************** + * This is a ch9 request and is used by the host to set the interface + *****************************************************************************/ +static uint_8 USB_Strd_Req_Set_Interface ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + + UNUSED (data); + *size=0; + + /* Request type not for interface */ + if((setup_packet->request_type & USB_REQUEST_SRC_MASK) != USB_REQUEST_SRC_INTERFACE) + { + return USB_STATUS_ERROR; + } + else + { + /* Set Interface and alternate interface from setup_packet */ + status = USB_Desc_Set_Interface(controller_ID,(uint_8)setup_packet->index, + (uint_8)setup_packet->value); + + UNUSED (status); + + return USB_OK; + } +} + +/**************************************************************************//*! + * + * @name USB_Strd_Req_Sync_Frame + * + * @brief This function is called in response to Sync Frame request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This req is used to set and then report an ep's synchronization frame + *****************************************************************************/ +static uint_8 USB_Strd_Req_Sync_Frame ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 status; + uint_8 device_status; + + UNUSED(setup_packet); + *size = FRAME_SIZE; + + /* Get the frame number */ + status = _usb_device_get_status(&controller_ID, USB_STATUS_SOF_COUNT, + &device_status); + g_std_framework_data = (uint_16)device_status; + *data = (uint_8_ptr)&g_std_framework_data; + + return status; +} + + +/**************************************************************************//*! + * + * @name USB_Std_Req_Get_Descriptor + * + * @brief This function is called in response to Get Descriptor request + * + * @param controller_ID : Controller ID + * @param setup_packet : Setup packet received + * @param data : Data to be send back + * @param size : Size to be returned + * + * @return status: + * USB_OK : When Successfull + * Others : When Error + * + ****************************************************************************** + * This is a ch9 request and is used to send the descriptor requested by the + * host + *****************************************************************************/ +static uint_8 USB_Strd_Req_Get_Descriptor ( + uint_8 controller_ID, /* [IN] Controller ID */ + USB_SETUP_STRUCT * setup_packet, /* [IN] Setup packet received */ + uint_8_ptr *data, /* [OUT] Data to be send back */ + USB_PACKET_SIZE *size /* [OUT] Size to be returned */ +) +{ + uint_8 type = USB_uint_16_high(setup_packet->value); + uint_16 index = (uint_16)UNINITIALISED_VAL; + uint_8 str_num = (uint_8)UNINITIALISED_VAL; + uint_8 status; + + /* for string descriptor set the language and string number */ + index = setup_packet->index; + /*g_setup_pkt.lValue*/ + str_num = USB_uint_16_low(setup_packet->value); + + /* Call descriptor class to get descriptor */ + status = USB_Desc_Get_Descriptor(controller_ID, type, str_num, index, data, size); + + return status; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h new file mode 100644 index 0000000..b709830 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_framework.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file usb_framwork.h + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains USB Framework module API header function. + * + *****************************************************************************/ + +#ifndef _USB_FRAMEWORK_H +#define _USB_FRAMEWORK_H + +/****************************************************************************** + * Includes + *****************************************************************************/ +#include "types.h" +#include "usb_class.h" +#include "usb_descriptor.h" + +/****************************************************************************** + * Constants - None + *****************************************************************************/ + +/****************************************************************************** + * Macro's + *****************************************************************************/ +#define MAX_STRD_REQ (13) /* Max value of standard request */ +/* size of data to be returned for various Get Desc calls */ +#define DEVICE_STATUS_SIZE (2) +#ifdef OTG_BUILD +#define OTG_STATUS_SIZE (2) +#endif +#define INTERFACE_STATUS_SIZE (2) + +#define CONFIG_SIZE (1) +#define INTERFACE_SIZE (1) +#define FRAME_SIZE (2) +#define ENDP_STATUS_SIZE (2) + +#ifdef OTG_BUILD +#define DEVICE_SET_FEATURE_B_HNP_ENABLE (0x0003) /* B HNP enable SET/CLEAR feature value */ +#define DEVICE_SET_FEATURE_A_HNP_SUPPORT (0x0004) /* A HNP support SET/CLEAR feature value */ +#endif + +/* Standard Feature Selectors */ +#define DEVICE_FEATURE_REMOTE_WAKEUP (0x0001) +#define DEVICE_FEATURE_TEST_MODE (0x0002) +#define DEVICE_SET_FEATURE_MASK ((uint_16)((1<<(DEVICE_FEATURE_REMOTE_WAKEUP)) | (1<<(DEVICE_FEATURE_TEST_MODE)))) +#define DEVICE_CLEAR_FEATURE_MASK ((uint_16)(1<<(DEVICE_FEATURE_REMOTE_WAKEUP))) + + + +#define REPORT_DESCRIPTOR_TYPE (0x22) +#define STRING_DESCRIPTOR_TYPE (0x03) + +/* masks and values for provides of Get Desc information */ +#define USB_REQUEST_SRC_MASK (0x03) +#define USB_REQUEST_SRC_DEVICE (0x00) +#define USB_REQUEST_SRC_INTERFACE (0x01) +#define USB_REQUEST_SRC_ENDPOINT (0x02) + +#define USB_SET_REQUEST_MASK (0x02) + +/* wIndex values for GET_Status */ +#ifdef OTG_BUILD +#define USB_WINDEX_OTG_STATUS_SEL (0xF000) +#endif + +/* for transfer direction check */ +#define USB_DATA_TO_HOST (0x80) +#define USB_DATA_TO_DEVICE (0x00) +#define USB_DATA_DIREC_MASK (0x80) + +#define USB_uint_16_low(x) ((uint_8)x) /* lsb byte */ +#define USB_uint_16_high(x) ((uint_8)(x>>8)) /* msb byte */ + +#ifdef CPU_LITTLE_ENDIAN /* << EST: defined by Processor Expert CPU.h for Kinetis devices */ + #ifndef LITTLE_ENDIAN /* might be defined already on the compiler command line? */ + #define LITTLE_ENDIAN + #endif +#endif + +#if(defined LITTLE_ENDIAN) +#define BYTE_SWAP16(a) (a) +#else +#define BYTE_SWAP16(a) (uint_16)((((uint_16)(a)&0xFF00)>>8) | \ + (((uint_16)(a)&0x00FF)<<8)) +#endif + +/****************************************************************************** + * Types + *****************************************************************************/ + +/****************************************************************************** + * Global Functions + *****************************************************************************/ +extern boolean USB_Frame_Remote_Wakeup(uint_8 controller_ID); + +#define USB_Frame_Remote_Wakeup USB_Desc_Remote_Wakeup + +typedef struct _app_data_struct +{ + uint_8_ptr data_ptr; /* pointer to buffer */ + USB_PACKET_SIZE data_size; /* buffer size of endpoint */ +}APP_DATA_STRUCT; + +extern uint_8 USB_Framework_Init ( + uint_8 controller_ID, + USB_CLASS_CALLBACK callback, + USB_REQ_FUNC other_req_callback +); + +extern uint_8 USB_Framework_DeInit +( + uint_8 controller_ID +); + +extern uint_8 USB_Framework_Reset ( + uint_8 controller_ID +); +#ifdef DELAYED_PROCESSING +extern void USB_Framework_Periodic_Task(void); +#endif + +#endif + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h new file mode 100644 index 0000000..b58d26e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/usb_user_config.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + **************************************************************************//*! + * + * @file usb_user_config.h << EST 'user_config.h' conflicts with MQX Lite + * + * @author + * + * @version + * + * @date May-28-2009 + * + * @brief The file contains User Modifiable Macros for Virtual COM Loopback + * Application + * + *****************************************************************************/ +#if 0 /* << EST */ +#include "derivative.h" + +#if (defined MCU_MK70F12) || (defined __MCF52277_H__) + #define HIGH_SPEED_DEVICE (0) +#else + #define HIGH_SPEED_DEVICE (0) +#endif + +#if (defined MCU_MK20D7) || (defined MCU_MK40D7) + #define MCGOUTCLK_72_MHZ +#endif + +#if ((defined __MK_xxx_H__)||(defined MCU_mcf51jf128)) + #define KEY_PRESS_SIM_TMR_INTERVAL (1000) /* 2s between simulated key press events */ +#else + #ifdef __MCF52277_H__ + #define BUTTON_PRESS_SIMULATION (1) + #define KEY_PRESS_SIM_TMR_INTERVAL (2000) /* 2s between simulated key press events */ + #endif +#endif + +#else +#include "FSL_USB_Stack_Config.h" + +/* device is Kinetis K20D72 << EST */ +#define HIGH_SPEED_DEVICE (0) + + +#endif +/* + Below two MACROS are required for Virtual COM Loopback + Application to execute +*/ +#define LONG_SEND_TRANSACTION /* support to send large data pkts */ +#define LONG_RECEIVE_TRANSACTION /* support to receive large data pkts */ +#ifndef _MC9S08JS16_H +#define USB_OUT_PKT_SIZE 32 /* Define the maximum data length received from the host */ +#else +#define USB_OUT_PKT_SIZE 16 /* Define the maximum data length received from the host */ +#endif + +/* User Defined MACRO to set number of Timer Objects */ +#define MAX_TIMER_OBJECTS 5 + +#if MAX_TIMER_OBJECTS +/* When Enabled Timer Callback is invoked with an argument */ +#define TIMER_CALLBACK_ARG +#undef TIMER_CALLBACK_ARG +#endif + +#if 0 /* << EST */ +#ifndef _MC9S08JS16_H +#define USB_PACKET_SIZE uint_16 /* support 16/32 bit packet size */ +#else +#define USB_PACKET_SIZE uint_8 /* support 8 bit packet size */ +#endif +#else +/* device is Kinetis K20D72 << EST */ +#define USB_PACKET_SIZE uint_16 /* support 16/32 bit packet size */ +#endif + +#if 0 /* << EST */ +#ifndef _MCF51JM128_H +/* Use double buffered endpoints 5 & 6. To be only used with S08 cores */ +#define DOUBLE_BUFFERING_USED +#endif +#else +/* device is Kinetis K20D72 << EST */ +/* Use double buffered endpoints 5 & 6. To be only used with S08 cores */ +#define DOUBLE_BUFFERING_USED +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c new file mode 100644 index 0000000..ef4190d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.c @@ -0,0 +1,46 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file wdt_kinetis.c + * + * @author + * + * @version + * + * @date + * + * @brief This file contains the implementation of the Watchdog service routines on CFV2 + *****************************************************************************/ + +#include "types.h" /* User Defined Data Types */ +#include "hal/derivative.h" /* include peripheral declarations */ +#include "wdt_kinetis.h" /* own header with public declarations */ + +/*****************************************************************************/ +void Watchdog_Reset(void) +{ +#if defined(MCU_MKL25Z4) || defined(MCU_MKL26Z4) || defined(MCU_MKL46Z4) + (void)(RCM_SRS0 |= RCM_SRS0_WDOG_MASK); +#else + (void)(WDOG_REFRESH = 0xA602, WDOG_REFRESH = 0xB480); +#endif +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h new file mode 100644 index 0000000..1efdb26 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/USB_CDC/wdt_kinetis.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Freescale Semiconductor Inc. + * (c) Copyright 2004-2010 Freescale Semiconductor, Inc. + * ALL RIGHTS RESERVED. + * + ****************************************************************************** + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************//*! + * + * @file Wdt_kinetis.h + * + * @brief This is the header file for the Watchdog service routines on CFV2 + *****************************************************************************/ + + #ifndef _WDT_KINETIS_ + #define _WDT_KINETIS_ + + /***************************************************************************** + * Public functions + * + ****************************************************************************/ + extern void Watchdog_Reset(void); + + #endif /* _INIT_HW_ */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c new file mode 100644 index 0000000..9f22f30 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.c @@ -0,0 +1,302 @@ +/* + * kinetis_sysinit.c - Default init routines for Flycatcher + * Kinetis ARM systems + * Copyright © 2012 Freescale semiConductor Inc. All Rights Reserved. + */ + +#include "hal/derivative.h" +#include "kinetis_sysinit.h" + +/** + **=========================================================================== + ** External declarations + **=========================================================================== + */ +#if __cplusplus +extern "C" { +#endif +extern unsigned long _estack; +extern void __thumb_startup(void); +#if __cplusplus +} +#endif + +/** + **=========================================================================== + ** Default interrupt handler + **=========================================================================== + */ +void Default_Handler(void) +{ + // Uncomment this breakpoint instruction if you are debugging a hard + // fault during development. If this breakpoint is hit without a + // debugger attached a LOCKUP is triggered. For this processor this + // causes an immediate system reset. + //asm volatile ("bkpt"); + + while(1); + + /* Fault registers: + * 0xE000ED2C: HFSR (HardFault status register) + * 0xE000ED28: MMFSR (MemManage fault status register) + * 0xE000ED34: MMFAR (MemManage fault address register) + * 0xE000ED29: BFSR (BusFault status register) + * 0xE000ED38: BFAR (BusFault address register) + */ +} + +/* Weak definitions of handlers point to Default_Handler if not implemented */ +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); + +void DMA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 0 transfer complete interrupt */ +void DMA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 1 transfer complete interrupt */ +void DMA2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 2 transfer complete interrupt */ +void DMA3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 3 transfer complete interrupt */ +void DMA4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 4 transfer complete interrupt */ +void DMA5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 5 transfer complete interrupt */ +void DMA6_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 6 transfer complete interrupt */ +void DMA7_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 7 transfer complete interrupt */ +void DMA8_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 8 transfer complete interrupt */ +void DMA9_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 9 transfer complete interrupt */ +void DMA10_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 10 transfer complete interrupt */ +void DMA11_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 11 transfer complete interrupt */ +void DMA12_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 12 transfer complete interrupt */ +void DMA13_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 13 transfer complete interrupt */ +void DMA14_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 14 transfer complete interrupt */ +void DMA15_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA channel 15 transfer complete interrupt */ +void DMA_Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DMA error interrupt */ +void MCMNormal_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* MCM normal interrupt */ +void FlashCmd_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Flash memory command complete interrupt */ +void FlashReadErr_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Flash read collision interrupt */ +void LVD_LVW_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low Voltage Detect, Low Voltage Warning */ +void LLW_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low Leakage Wakeup */ +void Watchdog_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* WDOG or EVM interrupt (shared) */ +void Reserved39_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 39 */ +void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2C0 interrupt */ +void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2C1 interrupt */ +void SPI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI0 interrupt */ +void SPI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI1 interrupt */ +void SPI2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SPI 2 interrupt */ +void CAN0Msg_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 message buffer (0-15) interrupt */ +void CAN0BusOff_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Bus Off interrupt */ +void CAN0Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Error interrupt */ +void CAN0Xmit_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Transmit warning interrupt */ +void CAN0Rcv_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Recieve warning interrupt */ +void CAN0Wake_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN0 Wake Up interrupt */ +void I2S0_Tx_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2S0 transmit interrupt */ +void I2S0_Rx_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* I2S0 receive interrupt */ +void CAN1Msg_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Msg interrupt */ +void CAN1BusOff_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1BusOff interrupt */ +void CAN1Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Error interrupt */ +void CAN1Xmit_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Xmit interrupt */ +void CAN1Rcv_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Rcv interrupt */ +void CAN1Wake_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CAN1Wake interrupt */ +void Reserved59_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 59 */ +void UART0_LON_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 LON interrupt */ +void UART0_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 receive/transmit interrupt */ +void UART0Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART0 error interrupt */ +void UART1_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART1 receive/transmit interrupt */ +void UART1Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART1 error interrupt */ +void UART2_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART2 receive/transmit interrupt */ +void UART2Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART2 error interrupt */ +void UART3_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART3 receive/transmit interrupt */ +void UART3Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART3 error interrupt */ +void UART4_RX_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART4 receive/transmit interrupt */ +void UART4Error_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* UART4 error interrupt */ +void Reserved71_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 71 */ +void Reserved72_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 72 */ +void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* ADC0 interrupt */ +void ADC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* ADC1 interrupt */ +void CMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP0 interrupt */ +void CMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP1 interrupt */ +void CMP2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMP2 interrupt */ +void FTM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM0 fault, all sources interrupt */ +void FTM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM1 fault, all sources interrupt */ +void FTM2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* FTM2 fault, all sources interrupt */ +void CMT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* CMT interrupt */ +void RTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* RTC alarm interrupt */ +void RTCSeconds_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* RTC seconds interrupt */ +void PIT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 0 interrupt */ +void PIT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 1 interrupt */ +void PIT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 2 interrupt */ +void PIT3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PIT timer channel 3 interrupt */ +void PDB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* PDB0 interrupt */ +void USB_ISR(void) __attribute__ ((weak, alias("Default_Handler"))); /* USB OTG interrupt */ +void USBCharge_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* USB charger detect interrupt */ +void Reserved91_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 91 */ +void Reserved92_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 92 */ +void Reserved93_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 93 */ +void Reserved94_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 94 */ +void Reserved95_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 95 */ +void SDHC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* SDHC interrupt */ +void DAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* DAC0 interrupt */ +void Reserved98_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 98 */ +void TSI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* TSI all sources interrupt */ +void MCG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* MCG interrupt */ +void LPTimer_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Low-power Timer interrupt */ +void Reserved102_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 102 */ +void PORTA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port A pin detect interrupt */ +void PORTB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port B pin detect interrupt */ +void PORTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port C pin detect interrupt */ +void PORTD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port D pin detect interrupt */ +void PORTE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Port E pin detect interrupt */ +void Reserved108_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 108 */ +void Reserved109_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Reserved interrupt 109 */ +void SWI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); /* Software interrupt */ + +/* The Interrupt Vector Table */ +void (* const InterruptVector[])(void) __attribute__ ((section(".vectortable"))) = { + /* Processor exceptions */ + (void(*)(void)) &_estack, + __thumb_startup, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + + /* Interrupts */ + DMA0_IRQHandler, /* DMA channel 0 transfer complete interrupt */ + DMA1_IRQHandler, /* DMA channel 1 transfer complete interrupt */ + DMA2_IRQHandler, /* DMA channel 2 transfer complete interrupt */ + DMA3_IRQHandler, /* DMA channel 3 transfer complete interrupt */ + DMA4_IRQHandler, /* DMA channel 4 transfer complete interrupt */ + DMA5_IRQHandler, /* DMA channel 5 transfer complete interrupt */ + DMA6_IRQHandler, /* DMA channel 6 transfer complete interrupt */ + DMA7_IRQHandler, /* DMA channel 7 transfer complete interrupt */ + DMA8_IRQHandler, /* DMA channel 8 transfer complete interrupt */ + DMA9_IRQHandler, /* DMA channel 9 transfer complete interrupt */ + DMA10_IRQHandler, /* DMA channel 10 transfer complete interrupt */ + DMA11_IRQHandler, /* DMA channel 11 transfer complete interrupt */ + DMA12_IRQHandler, /* DMA channel 12 transfer complete interrupt */ + DMA13_IRQHandler, /* DMA channel 13 transfer complete interrupt */ + DMA14_IRQHandler, /* DMA channel 14 transfer complete interrupt */ + DMA15_IRQHandler, /* DMA channel 15 transfer complete interrupt */ + DMA_Error_IRQHandler, /* DMA error interrupt */ + MCMNormal_IRQHandler, /* MCM normal interrupt */ + FlashCmd_IRQHandler, /* Flash memory command complete interrupt */ + FlashReadErr_IRQHandler, /* Flash read collision interrupt */ + LVD_LVW_IRQHandler, /* Low Voltage Detect, Low Voltage Warning */ + LLW_IRQHandler, /* Low Leakage Wakeup */ + Watchdog_IRQHandler, /* WDOG or EVM interrupt (shared) */ + Reserved39_IRQHandler, /* Reserved interrupt 39 */ + I2C0_IRQHandler, /* I2C0 interrupt */ + I2C1_IRQHandler, /* I2C1 interrupt */ + SPI0_IRQHandler, /* SPI0 interrupt */ + SPI1_IRQHandler, /* SPI1 interrupt */ + SPI2_IRQHandler, /* SPI2 interrupt 44 */ + CAN0Msg_IRQHandler, /* CAN0 message buffer (0-15) interrupt */ + CAN0BusOff_IRQHandler, /* CAN0 Bus Off interrupt */ + CAN0Error_IRQHandler, /* CAN0 Error interrupt */ + CAN0Xmit_IRQHandler, /* CAN0 Transmit warning interrupt */ + CAN0Rcv_IRQHandler, /* CAN0 Recieve warning interrupt */ + CAN0Wake_IRQHandler, /* CAN0 Wake Up interrupt */ + I2S0_Tx_IRQHandler, /* I2S0 transmit interrupt */ + I2S0_Rx_IRQHandler, /* I2S0 receive interrupt */ + CAN1Msg_IRQHandler, /* Reserved interrupt 53 */ + CAN1BusOff_IRQHandler, /* Reserved interrupt 54 */ + CAN1Error_IRQHandler, /* Reserved interrupt 55 */ + CAN1Xmit_IRQHandler, /* Reserved interrupt 56 */ + CAN1Rcv_IRQHandler, /* Reserved interrupt 57 */ + CAN1Wake_IRQHandler, /* Reserved interrupt 58 */ + Reserved59_IRQHandler, /* Reserved interrupt 59 */ + UART0_LON_IRQHandler, /* UART0 LON interrupt */ + UART0_RX_TX_IRQHandler, /* UART0 receive/transmit interrupt */ + UART0Error_IRQHandler, /* UART0 error interrupt */ + UART1_RX_TX_IRQHandler, /* UART1 receive/transmit interrupt */ + UART1Error_IRQHandler, /* UART1 error interrupt */ + UART2_RX_TX_IRQHandler, /* UART2 receive/transmit interrupt */ + UART2Error_IRQHandler, /* UART2 error interrupt */ + UART3_RX_TX_IRQHandler, /* UART3 receive/transmit interrupt */ + UART3Error_IRQHandler, /* UART3 error interrupt */ + UART4_RX_TX_IRQHandler, /* UART4 receive/transmit */ + UART4Error_IRQHandler, /* UART4 error interrupt */ + Reserved71_IRQHandler, /* Reserved interrupt 71 */ + Reserved72_IRQHandler, /* Reserved interrupt 72 */ + ADC0_IRQHandler, /* ADC0 interrupt */ + ADC1_IRQHandler, /* ADC1 interrupt */ + CMP0_IRQHandler, /* CMP0 interrupt */ + CMP1_IRQHandler, /* CMP1 interrupt */ + CMP2_IRQHandler, /* CMP2 interrupt */ + FTM0_IRQHandler, /* FTM0 fault, all sources interrupt */ + FTM1_IRQHandler, /* FTM1 fault, all sources interrupt */ + FTM2_IRQHandler, /* FTM2 fault, all sources interrupt */ + CMT_IRQHandler, /* CMT interrupt */ + RTC_IRQHandler, /* RTC alarm interrupt */ + RTCSeconds_IRQHandler, /* RTC seconds interrupt */ + PIT0_IRQHandler, /* PIT timer channel 0 interrupt */ + PIT1_IRQHandler, /* PIT timer channel 1 interrupt */ + PIT2_IRQHandler, /* PIT timer channel 2 interrupt */ + PIT3_IRQHandler, /* PIT timer channel 3 interrupt */ + PDB0_IRQHandler, /* PDB0 interrupt */ + USB_ISR, /* USB OTG interrupt */ + USBCharge_IRQHandler, /* USB charger detect interrupt */ + Reserved91_IRQHandler, /* Reserved interrupt 91 */ + Reserved92_IRQHandler, /* Reserved interrupt 92 */ + Reserved93_IRQHandler, /* Reserved interrupt 93 */ + Reserved94_IRQHandler, /* Reserved interrupt 94 */ + Reserved95_IRQHandler, /* Reserved interrupt 95 */ + SDHC_IRQHandler, /* SDHC interrupt */ + DAC0_IRQHandler, /* DAC0 interrupt */ + Reserved98_IRQHandler, /* Reserved interrupt 98 */ + TSI_IRQHandler, /* TSI all sources interrupt */ + MCG_IRQHandler, /* MCG interrupt */ + LPTimer_IRQHandler, /* Low-power Timer interrupt */ + Reserved102_IRQHandler, /* Reserved interrupt 102 */ + PORTA_IRQHandler, /* Port A pin detect interrupt */ + PORTB_IRQHandler, /* Port B pin detect interrupt */ + PORTC_IRQHandler, /* Port C pin detect interrupt */ + PORTD_IRQHandler, /* Port D pin detect interrupt */ + PORTE_IRQHandler, /* Port E pin detect interrupt */ + Reserved108_IRQHandler, /* Reserved interrupt 108 */ + Reserved109_IRQHandler, /* Reserved interrupt 109 */ + SWI_IRQHandler /* Software interrupt */ +}; + +/** + **=========================================================================== + ** Reset handler + **=========================================================================== + */ +void __init_hardware(void) +{ + SCB_VTOR = (uint32)&InterruptVector[0]; /* Set the interrupt vector table position */ + + #if defined(MKL25Z128) + // Disable the Watchdog because it may reset the core before entering main(). + SIM_COPC = KINETIS_WDOG_DISABLED_CTRL; + + #elif defined(MKE02Z64) + // Disable the Watchdog because it may reset the core before entering main(). + WDOG_CNT = 0x20C5; + WDOG_CNT = 0x28D9; + WDOG_TOVAL = 0x28D9; + WDOG_CS2 = WDOG_CS2_CLK(0); + WDOG_CS1 = WDOG_CS1_UPDATE_MASK; //watchdog setting can be changed later + + #elif defined(MK20DN512) || defined(MK20DX256) + // Disable the Watchdog because it may reset the core before entering main(). + WDOG_UNLOCK = 0xC520; // Write 0xC520 to the unlock register + WDOG_UNLOCK = 0xD928; // Followed by 0xD928 to complete the unlock + WDOG_STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; // Clear the WDOGEN bit to disable the watchdog + #else + #error "MCU sub-model not supported!" + #endif +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h new file mode 100644 index 0000000..e224cc6 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/kinetis_sysinit.h @@ -0,0 +1,41 @@ +/* + FILE : kinetis_sysinit.h + PURPOSE : system initialization header for Kinetis ARM architecture + LANGUAGE: C + Copyright © 2012 Freescale semiConductor Inc. All Rights Reserved. +*/ +#ifndef KINETIS_SYSINIT_H +#define KINETIS_SYSINIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tmc/helpers/API_Header.h" + +/* Word to be written in SIM_COP in order to disable the Watchdog */ +#define KINETIS_WDOG_DISABLED_CTRL 0x0 + +/* + Initializes the Kinetis hardware: e.g. disables the Watchdog +*/ +void __init_hardware(void); + +/* +** =================================================================== +** Method : Default_Handler +** +** Description : +** The default interrupt handler. +** =================================================================== +*/ +void Default_Handler(void); + +void SetBASEPRI(uint32 Level) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef KINETIS_SYSINIT_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c new file mode 100644 index 0000000..9561129 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic-m4.c @@ -0,0 +1,134 @@ +#include "hal/derivative.h" + +/***********************************************************************/ +/* + * Initialize the NVIC to enable the specified IRQ. + * + * NOTE: The function only initializes the NVIC to enable a single IRQ. + * Interrupts will also need to be enabled in the ARM core. This can be + * done using the EnableInterrupts; macro. + * + * Parameters: + * irq irq number to be enabled (the irq number NOT the vector number) + */ + +void enable_irq (int irq) +{ + + int div; + + /* Make sure that the IRQ is an allowable number. Right now up to 91 is + * used. + */ + // if(irq > 91) + //printf("\nERR! Invalid IRQ value passed to enable irq function!\n"); + + /* Determine which of the NVICISERs corresponds to the irq */ + div = irq/32; + + switch (div) + { + case 0x0: + NVICICPR0 |= 1 << (irq%32); + NVICISER0 |= 1 << (irq%32); + break; + case 0x1: + NVICICPR1 |= 1 << (irq%32); + NVICISER1 |= 1 << (irq%32); + break; + case 0x2: + NVICICPR2 |= 1 << (irq%32); + NVICISER2 |= 1 << (irq%32); + break; + } +} +/***********************************************************************/ +/* + * Initialize the NVIC to disable the specified IRQ. + * + * NOTE: The function only initializes the NVIC to disable a single IRQ. + * If you want to disable all interrupts, then use the DisableInterrupts + * macro instead. + * + * Parameters: + * irq irq number to be disabled (the irq number NOT the vector number) + */ + +void disable_irq (int irq) +{ + + /* Make sure that the IRQ is an allowable number. Right now up to 32 is + * used. + * + * NOTE: If you are using the interrupt definitions from the header + * file, you MUST SUBTRACT 16!!! + */ + if(irq > 128) + { + /* Set the ICER register accordingly */ + NVICICER3 = 1 << (irq%32); + } + else if(irq > 64) + { + /* Set the ICER register accordingly */ + NVICICER2 = 1 << (irq%32); + } + else if(irq > 32) + { + /* Set the ICER register accordingly */ + NVICICER1 = 1 << (irq%32); + } + else + { + /* Set the ICER register accordingly */ + NVICICER0 = 1 << (irq%32); + } +} +/***********************************************************************/ +/* + * Initialize the NVIC to set specified IRQ priority. + * + * NOTE: The function only initializes the NVIC to set a single IRQ priority. + * Interrupts will also need to be enabled in the ARM core. This can be + * done using the EnableInterrupts; macro. + * + * Parameters: + * irq irq number to be enabled (the irq number NOT the vector number) + * prio irq priority. 0-3 levels. 0 max priority + */ + +void set_irq_priority (int irq, int prio) +{ + /*irq priority pointer*/ + uint32 *prio_reg; + uint8 err = 0; + uint8 div = 0; + uint8 off = 0; + + /* Make sure that the IRQ is an allowable number. Right now up to 32 is + * used. + * + * NOTE: If you are using the interrupt definitions from the header + * file, you MUST SUBTRACT 16!!! + */ + if(irq > 32) + { + err = 1; + } + + if(prio > 3) + { + err = 1; + } + + if(err != 1) + { + /* Determine which of the NVICIPx corresponds to the irq */ + div = irq / 4; + off = irq % 4; + prio_reg = (uint32 *)((uint32)&NVIC_IP(div)); + /* Assign priority to IRQ */ + *prio_reg |= ( (prio&0x3) << (8 - ARM_INTERRUPT_LEVEL_BITS) ) << (off * 8); + } +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h new file mode 100644 index 0000000..67ecca5 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/nvic.h @@ -0,0 +1,26 @@ +/* + * nvic.h + * + * Created on: Nov 6, 2012 + * Author: B34443 + */ + +#ifndef NVIC_H_ +#define NVIC_H_ + + /* ARM Cortex M0 implementation for interrupt priority shift */ + #define ARM_INTERRUPT_LEVEL_BITS 2 + +#ifndef EnableInterrupts + #define EnableInterrupts asm(" CPSIE i") +#endif + +#ifndef DisableInterrupts + #define DisableInterrupts asm(" CPSID i") +#endif + + void enable_irq(int); + void disable_irq(int); + void set_irq_priority(int, int); + +#endif /* NVIC_H_ */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S new file mode 100644 index 0000000..5cc3b34 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/freescale/startup.S @@ -0,0 +1,78 @@ +/******************************************************************************** + * \file startup.s + * \brief Startup file for Kinetis L (KL25Z). + * This module performs: + * - Set the initial SP + * - Set the initial PC == __thumb_startup, + * - Branches to main in the C library (which eventually + * calls main()). + ******************************************************************************/ + .syntax unified + .cpu cortex-m4 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. defined in linker script */ +.word ___ROM_AT +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word __START_BSS +/* end address for the .bss section. defined in linker script */ +.word __END_BSS + +/** + * \brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * \param None + * \retval : None +*/ + .section .text.__thumb_startup + .weak __thumb_startup + .type __thumb_startup, %function +__thumb_startup: +/* Call the C hardware init function (which also has to switch off the watchdog) */ + bl __init_hardware + +/* Copy the data segment initializers from flash to SRAM: */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =___ROM_AT + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =__START_BSS + b LoopFillZerobss + +/* Zero fill the bss segment: */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = __END_BSS + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point: */ + bl main + blx r0 /*Call the startup code of the application (address returned by the main() function of the boot loader)*/ + bx lr +.size __thumb_startup, .-__thumb_startup + +/****END OF FILE****/ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h b/TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h new file mode 100644 index 0000000..29fdd9d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/makeFor.h @@ -0,0 +1,9 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef Landungsbruecke + #define Landungsbruecke +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c new file mode 100644 index 0000000..f6fb5f2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/ADCs.c @@ -0,0 +1,236 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/ADCs.h" + +/* analog channel selection values (ADCx_SC1n Register, DIFF & ADCH fields) */ + +// ADCH // DIFF = 0 | DIFF = 1 +#define DAD0 0x00 // DADP0 | DAD0 +#define DAD1 0x01 // DADP1 | DAD1 +#define DAD2 0x02 // DADP2 | DAD2 +#define DAD3 0x03 // DADP3 | DAD3 +#define AD04 0x04 // AD4 | Reserved +#define AD05 0x05 // AD5 | Reserved +#define AD06 0x06 // AD6 | Reserved +#define AD07 0x07 // AD7 | Reserved +#define AD08 0x08 // AD8 | Reserved +#define AD09 0x09 // AD9 | Reserved +#define AD10 0x0A // AD10 | Reserved +#define AD11 0x0B // AD11 | Reserved +#define AD12 0x0C // AD12 | Reserved +#define AD13 0x0D // AD13 | Reserved +#define AD14 0x0E // AD14 | Reserved +#define AD15 0x0F // AD15 | Reserved +#define AD16 0x10 // AD16 | Reserved +#define AD17 0x11 // AD17 | Reserved +#define AD18 0x12 // AD18 | Reserved +#define AD19 0x13 // AD19 | Reserved +#define AD20 0x14 // AD20 | Reserved +#define AD21 0x15 // AD21 | Reserved +#define AD22 0x16 // AD22 | Reserved +#define AD23 0x17 // AD23 | Reserved +#define AD24 0x18 // Reserved | Reserved +#define AD25 0x19 // Reserved | Reserved +#define AD26 0x1A // Temp Sensor (single ended) | Temp Sensor (differential) +#define AD27 0x1B // Bandgap (single ended) | Bandgap (differential) +#define AD28 0x1C // Reserved | Reserved +#define AD29 0x1D // VRefSH | -VRefSH (differential) +#define AD30 0x1E // VRefSL | -VRefSL (differential) +#define AD31 0x1F // Module disabled | Module diabled + +static void init(void); +static void deInit(void); + +/* ADCs are scanned using two DMA channels. Upon ADC read complete, the first DMA channel (Channel 1 for ADC 0, Channel 3 for ADC 1) + * will write the result of the ADC measurement to the result array. Upon DMA completion the first channel triggers the + * second DMA channel (Channel 0 for ADC 0, Channel 2 for ADC 1) to write a new MUX value into the ADC's configuration register. + * This repeats, creating an infinite loop reading out 3 Samples per ADC. + * + * This loop gets initialised by an initial DMA request for the second Channel to write the first MUX value. + */ + +/* Result buffer indices: + * Input Signal, ADC Channel, Pin + * ADC0[0]: ADC0_DP1, DAD1, 14 + * ADC0[1]: ADC0_SE12, AD12, 55 + * ADC0[2]: ADC0_SE13, AD13, 56 + * ADC1[0]: ADC1_DP0, DAD0, 20 + * ADC1[1]: ADC1_DP1, DAD1, 16 + * ADC1[2]: ADC1_DP3, DAD3, 18 + */ + +// ADC Result buffers +volatile uint16_t adc0_result[3] = { 0 }; +volatile uint16_t adc1_result[3] = { 0 }; +// ADC Multiplexer selection +const uint8_t adc0_mux[3] = { DAD1, AD12, AD13 }; +const uint8_t adc1_mux[3] = { DAD0, DAD1, DAD3 }; + +ADCTypeDef ADCs = +{ + .AIN0 = &adc1_result[1], + .AIN1 = &adc1_result[2], + .AIN2 = &adc1_result[0], + .DIO4 = &adc0_result[1], + .DIO5 = &adc0_result[2], + .VM = &adc0_result[0], + .init = init, + .deInit = deInit +}; + +static void init(void) +{ + // === ADC initialization === + // enable clock for ADC0 & ADC1 + SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; + SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK; + + HAL.IOs->pins->DIO4.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO5.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->DIO4); + HAL.IOs->config->set(&HAL.IOs->pins->DIO5); + + // CFG1: set ADC clocks + ADC0_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + ADC1_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + + // CFG2: configuration for high speed conversions and selects the long sample time duration + ADC0_CFG2 = ADC_CFG2_ADLSTS(0); // use default longest sample time + ADC1_CFG2 = ADC_CFG2_ADLSTS(0); // use default longest sample time + + // SC2: conversion + ADC0_SC2 = ADC_SC2_DMAEN_MASK; // enable DMA + ADC1_SC2 = ADC_SC2_DMAEN_MASK; // enable DMA; + + // average over 4 samples, single measurement (trigger from having DMA write the MUX value to SC1A) + ADC0_SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0); + ADC1_SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0); + + ADC0_SC3 |= ADC_SC3_CAL_MASK; + while(ADC0_SC3 & ADC_SC3_CAL_MASK); + + uint16_t cal = 0; + cal += ADC0_CLP0; + cal += ADC0_CLP1; + cal += ADC0_CLP2; + cal += ADC0_CLP3; + cal += ADC0_CLP4; + cal += ADC0_CLPS; + cal >>= 1; + cal |= 1<<15; + + ADC0_PG = cal; + + ADC1_SC3 |= ADC_SC3_CAL_MASK; + while(ADC1_SC3 & ADC_SC3_CAL_MASK); + + cal = 0; + cal += ADC1_CLP0; + cal += ADC1_CLP1; + cal += ADC1_CLP2; + cal += ADC1_CLP3; + cal += ADC1_CLP4; + cal += ADC1_CLPS; + cal >>= 1; + cal |= 1<<15; + + ADC1_PG = cal; + + // === DMA initialization === + + // enable clock for DMA + SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; + + // enable clock for DMA mux + SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; + + // === setup DMA channels for ADC0 === + + // DMA channel 0, use for write ADC mux channel, from SRAM to ADC + DMAMUX_CHCFG0 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x36); // DMA source: DMA Mux channel 1 (Source Number 54) + DMA_TCD0_SADDR = (uint32_t) &adc0_mux[0]; // Source address: ADC Mux Settings Array + DMA_TCD0_SOFF = 0x01; // Source address increment (Added after each major loop step) + DMA_TCD0_SLAST = (uint32_t) -3; // Source address decrement (Added on major loop completion) + DMA_TCD0_DADDR = (uint32_t) &ADC0_SC1A; // Destination address: ADC0 control register (containing ADC Mux bitfield) + DMA_TCD0_DOFF = 0x00; // Destination address increment (Added after each major loop step) + DMA_TCD0_DLASTSGA = 0x00; // Destination address decrement (Added on major loop completion) + DMA_TCD0_NBYTES_MLNO = 0x01; // Number of bytes transferred per request (1 Byte ADC Setting) + DMA_TCD0_BITER_ELINKNO = 0x03; // Disable channel link, beginning major iteration count: 3 + DMA_TCD0_CITER_ELINKNO = 0x03; // Disable channel link, current major iteration count: 3 + DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); // Source and destination size: 8 bit + DMA_TCD0_CSR = DMA_CSR_START_MASK; // Request channel start, to initiate our readout loop + + // DMA channel 1, use for read ADC result data, from ADC to SRAM + DMAMUX_CHCFG1 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x28); // DMA source: ADC0 (Source Number 40) + DMA_TCD1_SADDR = (uint32_t) &ADC0_RA; // Source address: ADC0 result register + DMA_TCD1_SOFF = 0x00; // Source address increment (Added after each major loop step) + DMA_TCD1_SLAST = 0x00; // Source address decrement (Added on major loop completion) + DMA_TCD1_DADDR = (uint32_t) &adc0_result[0]; // Destination address: ADC0 result buffer + DMA_TCD1_DOFF = 0x02; // Destination address increment (Added after each major loop step) + DMA_TCD1_DLASTSGA = (uint32_t) -6; // Destination address decrement (Added on major loop completion) + DMA_TCD1_NBYTES_MLNO = 0x02; // Number of bytes transferred per request (2 Byte ADC Result) + DMA_TCD1_BITER_ELINKYES = (DMA_BITER_ELINKYES_ELINK_MASK|DMA_BITER_ELINKYES_LINKCH(0)|0x03); // Enable channel link (to channel 0) on major loop step, beginning major iteration count: 3 + DMA_TCD1_CITER_ELINKYES = (DMA_CITER_ELINKYES_ELINK_MASK|DMA_BITER_ELINKYES_LINKCH(0)|0x03); // Enable channel link (to channel 0) on major loop step, current major iteration count: 3 + DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1); // Source and destination size: 16 bit + DMA_TCD1_CSR = (DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK); // Major loop completion starts request for Channel 0 + + // Start the DMA Channel 1 + DMA_SERQ = 1; + + // === setup DMA channels for ADC1 === + + // DMA channel 2, use for write ADC mux channel, from SRAM to ADC + DMAMUX_CHCFG2 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x38); // DMA source: DMA Mux channel 2 (Source Number 56) + DMA_TCD2_SADDR = (uint32_t) &adc1_mux[0]; // Source address: ADC Mux Settings + DMA_TCD2_SOFF = 0x01; // Source address increment (Added after each major loop step) + DMA_TCD2_SLAST = (uint32_t) -3; // Source address decrement (Added on major loop completion) + DMA_TCD2_DADDR = (uint32_t) &ADC1_SC1A; // Destination address: ADC1 control register (containing ADC Mux bitfield) + DMA_TCD2_DOFF = 0x00; // Destination address increment (Added for each major loop step) + DMA_TCD2_DLASTSGA = 0x00; // Destination address decrement (Added on major loop completion) + DMA_TCD2_NBYTES_MLNO = 0x01; // Number of bytes transferred per request (1 Byte ADC Setting) + DMA_TCD2_BITER_ELINKNO = 0x03; // Disable channel link, beginning major iteration count: 3 + DMA_TCD2_CITER_ELINKNO = 0x03; // Disable channel link, current major iteration count: 3 + DMA_TCD2_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); // Source and destination size: 8 bit + DMA_TCD2_CSR = DMA_CSR_START_MASK; // Request channel start, to initiate our readout loop + + // DMA channel 3, use for read ADC result data, from ADC to SRAM + DMAMUX_CHCFG3 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x29); // DMA source: ADC1 (Source Number 41) + DMA_TCD3_SADDR = (uint32_t) &ADC1_RA; // Source address: ADC1 result register + DMA_TCD3_SOFF = 0x00; // Source address increment (Added after each major loop step) + DMA_TCD3_SLAST = 0x00; // Source address decrement (Added on major loop completion) + DMA_TCD3_DADDR = (uint32_t) &adc1_result[0]; // Destination address: ADC0 result buffer + DMA_TCD3_DOFF = 0x02; // Destination address increment (Added after each major loop step) + DMA_TCD3_DLASTSGA = (uint32_t) -6; // Destination address decrement (Added on major loop completion) + DMA_TCD3_NBYTES_MLNO = 0x02; // Number of bytes transferred per request (2 Byte ADC Result) + DMA_TCD3_BITER_ELINKYES = DMA_BITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(2) | 0x03; // Enable channel link (to channel 2) on major loop step, beginning major iteration count: 3 + DMA_TCD3_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(2) | 0x03; // Enable channel link (to channel 2) on major loop step, current major iteration count: 3 + DMA_TCD3_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1); // Source and destination size: 16 bit + DMA_TCD3_CSR = DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK; // Major loop completion starts request for Channel 2 + + // Start the DMA Channel 3 + DMA_SERQ = 3; + + EnableInterrupts; +} + +static void deInit() +{ + // disable clock for DMA + SIM_SCGC7 &= ~(SIM_SCGC7_DMA_MASK); + + // disable clock for DMA mux + SIM_SCGC6 &= ~(SIM_SCGC6_DMAMUX_MASK); + + // disable clock for ADC0/ADC1 + SIM_SCGC6 &= ~(SIM_SCGC6_ADC0_MASK); + SIM_SCGC3 &= ~(SIM_SCGC3_ADC1_MASK); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c new file mode 100644 index 0000000..fdbd2d4 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/HAL.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" + +static void init(void); +static void reset(uint8_t ResetPeripherals); +static void NVIC_init(void); +static void NVIC_DeInit(void); +static void get_hwid(void); + +uint8_t hwid; + +static const IOsFunctionsTypeDef IOFunctions = +{ + .config = &IOs, + .pins = &IOMap, +}; + +const HALTypeDef HAL = +{ + .init = init, + .reset = reset, + .NVIC_DeInit = NVIC_DeInit, + .SPI = &SPI, + .USB = &USB, + .LEDs = &LEDs, + .ADCs = &ADCs, + .IOs = &IOFunctions, + .RS232 = &RS232, + .WLAN = &WLAN, + .Timer = &Timer, + .UART = &UART +}; + +static void init(void) +{ + Cpu.initClocks(); + Cpu.initLowLevel(); + NVIC_init(); + EnableInterrupts;; + + systick_init(); + wait(100); + + IOs.init(); + IOMap.init(); + LEDs.init(); + ADCs.init(); + SPI.init(); + WLAN.init(); + RS232.init(); + USB.init(); + + // Determine HW version + get_hwid(); +} + +static void __attribute((noreturn)) reset(uint8_t ResetPeripherals) +{ + DisableInterrupts; + + if(ResetPeripherals) + SCB_AIRCR = SCB_AIRCR_VECTKEY(0x5FA) | SCB_AIRCR_SYSRESETREQ_MASK; + else + SCB_AIRCR = SCB_AIRCR_VECTKEY(0x5FA) | SCB_AIRCR_VECTRESET_MASK; + + // SYSRESETREQ does not happen instantly since peripheral reset timing is not specified. + // Trap execution here so nothing else happens until the reset completes. + while(1); +} + +static void NVIC_init(void) +{ + uint8_t i; + + // Disable all interrupts + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICER); i++) + { + // Interrupt clear-enable Registers + NVIC_ICER(i) = 0xFFFFFFFF; + } + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICPR); i++) + { + // Interrupt clear-pending Registers + NVIC_ICPR(i) = 0xFFFFFFFF; + } + + // Set all interrupt priorities to the same level + // The priority is stored in the uint8_t IP register, but not all of the + // bits are used. For the Processor of the Landungsbruecke the 4 upper bits + // are implemented. Here we set the interrupt priority to the middle of the + // available values to allow other code to increase or decrease specific + // interrupt priorities. + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->IP); i++) + { + // Interrupt priority registers + NVIC_IP(i) = 0x80; + } + + // Special interrupt priorities + // PortB interrupt - used for ID detection by measuring a pulse duration + // Needs to be the fastest interrupt to ensure correct measurement. + NVIC_IP(INT_PORTB-16) = 0x00; + // FTM1 interrupt - used by the StepDir generator. If this gets preempted + // the StepDir movement quality gets degraded. + NVIC_IP(INT_FTM1-16) = 0x10; + // USB interrupt - needed for communication + NVIC_IP(INT_USB0-16) = 0x20; +} + +static void NVIC_DeInit(void) +{ + uint8_t i; + + asm volatile("CPSID I\n"); // disable interrupts + + // Clear all NVIC interrupts + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICER); i++) + { + // Interrupt clear-enable Registers + NVIC_ICER(i) = 0xFFFFFFFF; + } + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->ICPR); i++) + { + // Interrupt clear-pending Registers + NVIC_ICPR(i) = 0xFFFFFFFF; + } + + // Reset interrupt priorities + for(i = 0; i < ARRAY_SIZE(NVIC_BASE_PTR->IP); i++) + { + // Interrupt priority registers + NVIC_IP(i) = 0x00; + } + + SYST_CSR = 0; // disable systick +} + +typedef enum { + STATE_Z = 0, + STATE_LOW = 1, + STATE_HIGH = 2 +} Tristate; + +// Helper for get_hwid() +static Tristate getTristate(IOPinTypeDef *pin) +{ + // Input with pulldown + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + pin->configuration.GPIO_OType = GPIO_OType_OD; + pin->configuration.GPIO_PuPd = GPIO_PuPd_DOWN; + HAL.IOs->config->set(pin); + + if (HAL.IOs->config->isHigh(pin)) { + // High despite pulldown -> High state + return STATE_HIGH; + } + + // Input with pullup + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + pin->configuration.GPIO_OType = GPIO_OType_OD; + pin->configuration.GPIO_PuPd = GPIO_PuPd_UP; + HAL.IOs->config->set(pin); + + if (HAL.IOs->config->isHigh(pin)) { + // High from pullup -> Z state + return STATE_Z; + } else { + // Low despite pullup -> Low state + return STATE_LOW; + } +} + +// Determines HW version of Landungsbruecke to distinct between 1.X and 2.0+ +static void get_hwid(void) +{ + static uint8_t hwid_map[27] = { + // Z Z Z L L L H H H <- ID_HW_1 + // Z L H Z L H Z L H <- ID_HW_0 + 1, 0, 0, 0, 0, 0, 0, 0, 0, // Z + 0, 0, 0, 0, 0, 0, 0, 2, 0, // L <- ID_HW_2 + 0, 0, 0, 0, 0, 0, 0, 0, 0 // H + }; + + uint8_t tmp; + tmp = getTristate(&HAL.IOs->pins->ID_HW_0) + + getTristate(&HAL.IOs->pins->ID_HW_1) * 3 + + getTristate(&HAL.IOs->pins->ID_HW_2) * (3*3); + + hwid = hwid_map[tmp]; +} + +void _exit(int32_t i) // function has the attribute noreturn per default +{ + UNUSED(i); + while(1) {}; +} + +void _kill(void) +{ +} + +void _getpid(void) +{ +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c new file mode 100644 index 0000000..88546d8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOMap.c @@ -0,0 +1,1228 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/IOMap.h" +#include "hal/Landungsbruecke/freescale/PDD/GPIO_PDD.h" + +static void init(); + +static IOPinTypeDef *_pins[] = +{ + &IOMap.ID_CLK, + &IOMap.ID_CH0, + &IOMap.ID_CH1, + &IOMap.DIO0, + &IOMap.DIO1, + &IOMap.DIO2, + &IOMap.DIO3, + &IOMap.DIO4, + &IOMap.DIO5, + &IOMap.DIO6, + &IOMap.DIO7, + &IOMap.DIO8, + &IOMap.DIO9, + &IOMap.DIO10, + &IOMap.DIO11, + &IOMap.CLK16, + &IOMap.SPI2_CSN0, + &IOMap.SPI2_CSN1, + &IOMap.SPI2_CSN2, + &IOMap.SPI2_SCK, + &IOMap.SPI2_SDO, + &IOMap.SPI2_SDI, + &IOMap.SPI1_CSN, + &IOMap.SPI1_SCK, + &IOMap.SPI1_SDI, + &IOMap.SPI1_SDO, + &IOMap.DIO12, + &IOMap.DIO13, + &IOMap.DIO14, + &IOMap.DIO15, + &IOMap.DIO16, + &IOMap.DIO17, + &IOMap.DIO18, + &IOMap.DIO19, + &IOMap.WIRELESS_TX, + &IOMap.WIRELESS_RX, + &IOMap.WIRELESS_NRST, + &IOMap.RS232_TX, + &IOMap.RS232_RX, + &IOMap.USB_V_BUS, + &IOMap.USB_V_DM, + &IOMap.USB_V_DP, + &IOMap.LED_STAT, + &IOMap.LED_ERROR, + &IOMap.EXTIO_2, + &IOMap.EXTIO_3, + &IOMap.EXTIO_4, + &IOMap.EXTIO_5, + &IOMap.EXTIO_6, + &IOMap.EXTIO_7, + &IOMap.EEPROM_SCK, + &IOMap.EEPROM_SI, + &IOMap.EEPROM_SO, + &IOMap.EEPROM_NCS, + &IOMap.MIXED0, + &IOMap.MIXED1, + &IOMap.MIXED2, + &IOMap.MIXED3, + &IOMap.MIXED4, + &IOMap.MIXED5, + &IOMap.MIXED6, + &IOMap.ID_HW_0, + &IOMap.ID_HW_1, + &IOMap.ID_HW_2, + &IOMap.DUMMY +}; + +IOPinMapTypeDef IOMap = +{ + .init = init, + .pins = &_pins[0], + .ID_CLK = // IOPinTypeDef ID_CLK + { + .setBitRegister = &(GPIOB_PSOR), // uint32_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // uint32_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // Peripheral Port Base Pointer + .GPIOBase = PTB_BASE_PTR, // Peripheral PTA base pointer, GPIO; + .bitWeight = GPIO_PDD_PIN_20, // uint32_t pinBitWeight Pin masks; + .bit = 20, // uint8_t bit; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_CH0 = // IOPinTypeDef ID_CH0 + { + .setBitRegister = &(GPIOB_PSOR), // uint32_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // uint32_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // Peripheral Port Base Pointer + .GPIOBase = PTB_BASE_PTR, // Peripheral PTA base pointer, GPIO; + .bitWeight = GPIO_PDD_PIN_18, // uint32_t pinBitWeight; + .bit = 18, // uint8_t bit; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_CH1 = // IOPinTypeDef ID_CH1 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_19, // uint32_t pinBitWeight; + .bit = 19, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO0 = // IOPinTypeDef DIO0 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_12, // uint32_t pinBitWeight; + .bit = 12, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO1 = // IOPinTypeDef DIO1 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_13, // uint32_t pinBitWeight; + .bit = 13, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO3 = // IOPinTypeDef DIO3 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO4 = // IOPinTypeDef DIO4 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO5 = // IOPinTypeDef DIO5 + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .DIO6 = // IOPinTypeDef DIO6 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO7 = // IOPinTypeDef DIO7 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO8 = // IOPinTypeDef DIO8 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO9 = // IOPinTypeDef DIO9 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO10 = // IOPinTypeDef DIO10 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_7, // uint32_t pinBitWeight; + .bit = 7, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO11 = // IOPinTypeDef DIO11 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .CLK16 = // IOPinTypeDef CLK16 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AF5, // GPIOMode_TypeDef GPIO_Mode; ?? + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN0 = // IOPinTypeDef SPI2_CSN0 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN1 = // IOPinTypeDef SPI2_CSN1 + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_CSN2 = // IOPinTypeDef SPI2_CSN2 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SCK = // IOPinTypeDef SPI2_SCK + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_21, // uint32_t pinBitWeight; + .bit = 21, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SDO = // IOPinTypeDef SPI2_SDO + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_23, // uint32_t pinBitWeight; + .bit = 23, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI2_SDI = // IOPinTypeDef SPI2_SDI + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_22, // uint32_t pinBitWeight; + .bit = 22, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_CSN = // IOPinTypeDef SPI1_CSN + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_10, // uint32_t pinBitWeight; + .bit = 10, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SCK = // IOPinTypeDef SPI1_SCK + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_11, // uint32_t pinBitWeight; + .bit = 11, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SDO = // IOPinTypeDef SPI1_SDO + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .SPI1_SDI = // IOPinTypeDef SPI1_SDI + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO12 = // IOPinTypeDef DIO12 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO13 = // IOPinTypeDef DIO13 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .DIO14 = // IOPinTypeDef DIO14 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_18, // uint32_t pinBitWeight; + .bit = 18, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO15 = // IOPinTypeDef DIO15 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO16 = // IOPinTypeDef DIO16 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO17 = // IOPinTypeDef DIO17 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO18 = // IOPinTypeDef DIO18 + { + .setBitRegister = &(GPIOD_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOD_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTD_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTD_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DIO19 = // IOPinTypeDef DIO19 + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_15, // uint32_t pinBitWeight; + .bit = 15, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_IN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .WIRELESS_TX = // IOPinTypeDef WIRELESS_TX + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_14, // uint32_t pinBitWeight; + .bit = 14, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .WIRELESS_RX = // IOPinTypeDef WIRELESS_RX + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_15, // uint32_t pinBitWeight; + .bit = 15, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .WIRELESS_NRST = // IOPinTypeDef WIRELESS_NRST + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_16, // uint32_t pinBitWeight; + .bit = 16, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .RS232_TX = // IOPinTypeDef RS232_TX + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_24, // uint32_t pinBitWeight; + .bit = 24, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .RS232_RX = // IOPinTypeDef RS232_RX + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_25, // uint32_t pinBitWeight; + .bit = 25, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .USB_V_BUS = // IOPinTypeDef USB_V_BU + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, // GPIO_TypeDef *port; + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_100MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .LED_STAT = // IOPinTypeDef LED_STAT + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .LED_ERROR = // IOPinTypeDef LED_ERROR + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_2 = // IOPinTypeDef EXTIO_2 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_0, // uint32_t pinBitWeight; + .bit = 0, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_3 = // IOPinTypeDef EXTIO_3 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_1, // uint32_t pinBitWeight; + .bit = 1, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + .EXTIO_4 = // IOPinTypeDef EXTIO_4 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_2, // uint32_t pinBitWeight; + .bit = 2, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + .EXTIO_5 = // IOPinTypeDef EXTIO_5 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_3, // uint32_t pinBitWeight; + .bit = 3, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_6 = // IOPinTypeDef EXTIO_6 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_4, // uint32_t pinBitWeight; + .bit = 4, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EXTIO_7= // IOPinTypeDef EXTIO_7 + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .EEPROM_SCK = // IOPinTypeDef EEPROM_SCK + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_5, // uint32_t pinBitWeight; + .bit = 5, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + + .EEPROM_SI = // IOPinTypeDef EEPROM_SI + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_7, // uint32_t pinBitWeight; + .bit = 7, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EEPROM_SO = // IOPinTypeDef EEPROM_SO + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .EEPROM_NCS = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_8, // uint32_t pinBitWeight; + .bit = 8, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED0 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_11, // uint32_t pinBitWeight; + .bit = 11, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED1 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_12, // uint32_t pinBitWeight; + .bit = 12, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_13, // uint32_t pinBitWeight; + .bit = 13, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED3 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_14, // uint32_t pinBitWeight; + .bit = 14, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED4 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_10, // uint32_t pinBitWeight; + .bit = 10, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED5 = // IOPinTypeDef + { + .setBitRegister = &(GPIOC_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOC_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTC_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTC_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_9, // uint32_t pinBitWeight; + .bit = 9, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .MIXED6 = // IOPinTypeDef + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_6, // uint32_t pinBitWeight; + .bit = 6, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_0 = // IOPinTypeDef + { + .setBitRegister = &(GPIOE_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOE_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTE_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTE_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_26, // uint32_t pinBitWeight; + .bit = 26, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_1 = // IOPinTypeDef + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_17, // uint32_t pinBitWeight; + .bit = 17, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .ID_HW_2 = // IOPinTypeDef + { + .setBitRegister = &(GPIOB_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOB_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTB_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTB_BASE_PTR, + .bitWeight = GPIO_PDD_PIN_9, // uint32_t pinBitWeight; + .bit = 9, // uint8_t pinBitWeight; + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + }, + + .DUMMY = // Dummy Pin + { + .setBitRegister = &(GPIOA_PSOR), // __IO uint16_t *setBitRegister; + .resetBitRegister = &(GPIOA_PCOR), // __IO uint16_t *resetBitRegister; + .portBase = PORTA_BASE_PTR, // GPIO_TypeDef *port; + .GPIOBase = PTA_BASE_PTR, + .bitWeight = DUMMY_BITWEIGHT, // invalid + .bit = -1, // invalid + .resetConfiguration = + { + .GPIO_Mode = GPIO_Mode_AN, // GPIOMode_TypeDef GPIO_Mode; + .GPIO_OType = GPIO_OType_PP, // GPIOSpeed_TypeDef GPIO_Speed; + .GPIO_Speed = GPIO_Speed_50MHz, // GPIOOType_TypeDef GPIO_OType; + .GPIO_PuPd = GPIO_PuPd_NOPULL // GPIOPuPd_TypeDef GPIO_PuPd; + } + } +}; + + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CLK); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO0); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO3); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO4); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO5); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO6); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO7); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO8); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO9); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO12); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO13); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO14); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO15); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO16); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO19); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIRELESS_NRST); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_BUS); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_2); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_3); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_4); + HAL.IOs->config->reset(&HAL.IOs->pins->EXTIO_5); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->reset(&HAL.IOs->pins->CLK16); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED0); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED1); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED2); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED3); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED4); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED5); + HAL.IOs->config->reset(&HAL.IOs->pins->MIXED6); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_1); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_HW_2); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c new file mode 100644 index 0000000..bc5153f --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/IOs.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/IOs.h" + +static void init(); +static void setPinConfiguration(IOPinTypeDef *pin); +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef*to); +static void resetPinConfiguration(IOPinTypeDef *pin); +static void setPin2Output(IOPinTypeDef *pin); +static void setPin2Input(IOPinTypeDef *pin); +static void setPinHigh(IOPinTypeDef *pin); +static void setPinLow(IOPinTypeDef *pin); +static void setPinState(IOPinTypeDef *pin, IO_States state); +static IO_States getPinState(IOPinTypeDef *pin); +static uint8_t isPinHigh(IOPinTypeDef *pin); + +IOsTypeDef IOs = +{ + .init = init, + .set = setPinConfiguration, + .reset = resetPinConfiguration, + .copy = copyPinConfiguration, + .toOutput = setPin2Output, + .toInput = setPin2Input, + .setHigh = setPinHigh, + .setLow = setPinLow, + .setToState = setPinState, + .getState = getPinState, + .isHigh = isPinHigh +}; + +static void init() +{ + // Set the Clock divider for core/system clock + // 96 MHz / 2 = 48 MHz + SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV1(1); + + SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK| SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |SIM_SCGC5_PORTD_MASK); + + // Ausgabe des 16Mhz Taktes auf den CLK16 Pin + SIM_SOPT2 &= ~SIM_SOPT2_CLKOUTSEL_MASK; + SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(6); + PORTC_PCR3 = PORT_PCR_MUX(5); +} + +static void setPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + uint32_t config = 0; + switch(pin->configuration.GPIO_Mode) + { + case GPIO_Mode_IN: + GPIO_PDD_SetPortInputDirectionMask(pin->GPIOBase, pin->bitWeight); + config |= PORT_PCR_MUX(1); + break; + case GPIO_Mode_OUT: + GPIO_PDD_SetPortOutputDirectionMask(pin->GPIOBase, pin->bitWeight); + config |= PORT_PCR_MUX(1); + break; + case GPIO_Mode_AN: config |= PORT_PCR_MUX(0); break; + case GPIO_Mode_AF1: config |= PORT_PCR_MUX(1); break; + case GPIO_Mode_AF2: config |= PORT_PCR_MUX(2); break; + case GPIO_Mode_AF3: config |= PORT_PCR_MUX(3); break; + case GPIO_Mode_AF4: config |= PORT_PCR_MUX(4); break; + case GPIO_Mode_AF5: config |= PORT_PCR_MUX(5); break; + case GPIO_Mode_AF6: config |= PORT_PCR_MUX(6); break; + case GPIO_Mode_AF7: config |= PORT_PCR_MUX(7); break; + } + + switch(pin->configuration.GPIO_OType) + { + case GPIO_OType_PP: + break; + case GPIO_OType_OD: + config |= PORT_PCR_ODE_MASK; // enable open drain + break; + } + switch(pin->configuration.GPIO_Speed) // die Auswahl der Frequenz bewirkt keine Änderung + { + case GPIO_Speed_2MHz: break; + case GPIO_Speed_25MHz: break; + case GPIO_Speed_50MHz: break; + case GPIO_Speed_100MHz: break; + } + + switch(pin->configuration.GPIO_PuPd) + { + case GPIO_PuPd_NOPULL: + config &= ~PORT_PCR_PE_MASK; + break; + case GPIO_PuPd_UP: + config |= PORT_PCR_PE_MASK; + config |= PORT_PCR_PS_MASK; + break; + case GPIO_PuPd_DOWN: + config |= PORT_PCR_PE_MASK; + config &= ~(PORT_PCR_PS_MASK); + break; + } + + PORT_PCR_REG(pin->portBase, pin->bit) = config; +} + +static void setPin2Output(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + setPinConfiguration(pin); +} + +static void setPin2Input(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_Mode_IN; + setPinConfiguration(pin); +} + +static void setPinState(IOPinTypeDef *pin, IO_States state) +{ + if(IS_DUMMY_PIN(pin)) + return; + + switch(state) + { + case IOS_LOW: + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + pin->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + pin->configuration.GPIO_OType = GPIO_OType_PP; + setPinConfiguration(pin); + *pin->resetBitRegister = pin->bitWeight; + break; + case IOS_HIGH: + pin->configuration.GPIO_Mode = GPIO_Mode_OUT; + pin->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + pin->configuration.GPIO_OType = GPIO_OType_PP; + setPinConfiguration(pin); + *pin->setBitRegister = pin->bitWeight; + break; + case IOS_OPEN: + pin->configuration.GPIO_Mode = GPIO_Mode_AN; + setPinConfiguration(pin); + break; + case IOS_NOCHANGE: + break; + } + + pin->state = state; + + setPinConfiguration(pin); +} + +static IO_States getPinState(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return IOS_OPEN; + + if(pin->configuration.GPIO_Mode == GPIO_Mode_AN) + pin->state = IOS_OPEN; + else if(GPIO_PDIR_REG(pin->GPIOBase) & pin->bitWeight) + pin->state = IOS_HIGH; + else + pin->state = IOS_LOW; + + return pin->state; +} + +static void setPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->setBitRegister = pin->bitWeight; + pin->state = IOS_HIGH; +} + +static void setPinLow(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->resetBitRegister = pin->bitWeight; + pin->state = IOS_LOW; +} + +static uint8_t isPinHigh(IOPinTypeDef *pin) // Die Abfrage eines Pins funktioniert nur, wenn der Pin AF1 ist +{ + if(IS_DUMMY_PIN(pin)) + return -1; + + return (GPIO_PDIR_REG(pin->GPIOBase) & pin->bitWeight)? 1 : 0; +} + +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef *to) +{ + if(IS_DUMMY_PIN(to)) + return; + + to->configuration.GPIO_Mode = from->GPIO_Mode; + to->configuration.GPIO_OType = from->GPIO_OType; + to->configuration.GPIO_PuPd = from->GPIO_PuPd; + to->configuration.GPIO_Speed = from->GPIO_Speed; + setPinConfiguration(to); +} + +static void resetPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + copyPinConfiguration(&(pin->resetConfiguration), pin); + + // Extra Reset Konfiguration für CLK16 + if(pin == &IOMap.CLK16) + { + SIM_SOPT2 &= ~SIM_SOPT2_CLKOUTSEL_MASK; + SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(6); + PORTC_PCR3 = PORT_PCR_MUX(5); + } +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c new file mode 100644 index 0000000..acdb2fa --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/LEDs.c @@ -0,0 +1,80 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/LEDs.h" + +static void init(); +static void onStat(); +static void onError(); +static void offStat(); +static void offError(); +static void toggleStat(); +static void toggleError(); + +LEDsTypeDef LEDs = +{ + .init = init, + .stat = + { + .on = onStat, + .off = offStat, + .toggle = toggleStat, + }, + .error = + { + .on = onError, + .off = offError, + .toggle = toggleError, + }, +}; + +static void init() +{ + HAL.IOs->pins->LED_ERROR.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->LED_ERROR.configuration.GPIO_OType = GPIO_OType_PP; + HAL.IOs->pins->LED_STAT.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->LED_STAT.configuration.GPIO_OType = GPIO_OType_PP; + + HAL.IOs->config->set(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->set(&HAL.IOs->pins->LED_STAT); + + LED_OFF(); + LED_ERROR_OFF(); +} + +static void onStat() +{ + LED_ON(); +} + +static void onError() +{ + LED_ERROR_ON(); +} + +static void offStat() +{ + LED_OFF(); +} + +static void offError() +{ + LED_ERROR_OFF(); +} + +static void toggleStat() +{ + LED_TOGGLE(); +} + +static void toggleError() +{ + LED_ERROR_TOGGLE(); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c new file mode 100644 index 0000000..fb2abfb --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RS232.c @@ -0,0 +1,188 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 5 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static volatile uint32_t available = 0; + +RXTXTypeDef RS232 = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd; + + SIM_SCGC1 |= (SIM_SCGC1_UART4_MASK); + + HAL.IOs->pins->RS232_RX.configuration.GPIO_Mode = GPIO_Mode_AF3; + HAL.IOs->pins->RS232_TX.configuration.GPIO_Mode = GPIO_Mode_AF3; + + HAL.IOs->config->set(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->set(&HAL.IOs->pins->RS232_TX); + /* Disable the transmitter and receiver */ + UART_C2_REG(UART4_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Configure the UART for 8-bit mode, no parity */ + /* We need all default settings, so entire register is cleared */ + UART_C1_REG(UART4_BASE_PTR) = 0; + + ubd = (CPU_BUS_CLK_HZ / 16) / (RS232.baudRate); + + UART_BDH_REG(UART4_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART4_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + + /* Enable receiver and transmitter */ + UART_C2_REG(UART4_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + + enable_irq(INT_UART4_RX_TX-16); +} + +static void deInit() +{ + SIM_SCGC1 &= ~(SIM_SCGC1_UART4_MASK); + + HAL.IOs->pins->RS232_RX.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->RS232_TX.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->set(&HAL.IOs->pins->RS232_TX); + + disable_irq(INT_UART4_RX_TX-16); + + clearBuffers(); +} + +void UART4_RX_TX_IRQHandler(void) +{ + uint32_t status = UART4_S1; + + if(status & UART_S1_RDRF_MASK) + { + buffers.rx.buffer[buffers.rx.wrote] = UART4_D; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + UART4_S1 &= ~(UART_S1_RDRF_MASK); + } + + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART4_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { // empty buffer -> turn off send interrupt + UART4_C2 &= ~UART_C2_TIE_MASK; + } + UART4_S1 &= ~(UART_S1_TDRE_MASK); + } +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + + // enable send interrupt + UART4_C2 |= UART_C2_TIE_MASK; +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + disable_irq(INT_UART4_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART4_RX_TX-16); +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c new file mode 100644 index 0000000..96026b3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/RXTX.c @@ -0,0 +1,27 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/RXTX.h" +#include "hal/WLAN.h" +#include "hal/UART.h" + +UART0_Interrupt uart0_interrupt = UART0_INTERRUPT_UART; + +void UART0_RX_TX_IRQHandler(void) +{ + switch(uart0_interrupt) { + case UART0_INTERRUPT_WLAN: + UART0_RX_TX_IRQHandler_WLAN(); + break; + case UART0_INTERRUPT_UART: + default: + UART0_RX_TX_IRQHandler_UART(); + break; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c new file mode 100644 index 0000000..8db3fca --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SPI.c @@ -0,0 +1,426 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" + +void init(); +void reset_ch1(); +void reset_ch2(); + +static void setTMCSPIParameters(SPI_MemMapPtr basePtr); + +static uint8_t readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); +static uint8_t spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer); +static uint8_t spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer); +static void spi_ch1_readWriteArray(uint8_t *data, size_t length); +static void spi_ch2_readWriteArray(uint8_t *data, size_t length); + +SPIChannelTypeDef *SPIChannel_1_default; +SPIChannelTypeDef *SPIChannel_2_default; + +static IOPinTypeDef IODummy = { .bitWeight = DUMMY_BITWEIGHT }; + +SPITypeDef SPI= +{ + .ch1 = + { + .periphery = SPI1_BASE_PTR, + .CSN = &IODummy, + .readWrite = spi_ch1_readWrite, + .readWriteArray = spi_ch1_readWriteArray, + .reset = reset_ch1 + }, + .ch2 = + { + .periphery = SPI2_BASE_PTR, + .CSN = &IODummy, + .readWrite = spi_ch2_readWrite, + .readWriteArray = spi_ch2_readWriteArray, + .reset = reset_ch2 + }, + .init = init +}; + + +void init() +{ + // SPI0 -> EEPROM + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; // enable clock for PORT C + SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK; // enable clock for SPI0 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI0 pins: + // SCK: Port C, Pin 5 + // SDI: Port C, Pin 6 + // SDO: Port C, Pin 7 + // CSN: Port C, Pin 8 + HAL.IOs->pins->EEPROM_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_SI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_SO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->EEPROM_NCS.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->set(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->setHigh(&HAL.IOs->pins->EEPROM_NCS); + + setTMCSPIParameters(SPI0_BASE_PTR); + + // SPI1 -> ch1 + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; // enable clock for PORT B + SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK; // enable clock for SPI1 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI1 pins: + // SCK: Port B, Pin 11 + // SDI: Port B, Pin 16 + // SDO: Port B, Pin 17 + // CSN: Port B, Pin 10 + HAL.IOs->pins->SPI1_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_SDI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_SDO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI1_CSN.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->set(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI1_CSN); + + setTMCSPIParameters(SPI1_BASE_PTR); + + // SPI2 -> ch2 + // ------------------------------------------------------------------------------- + SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; // enable clocks + SIM_SCGC3 |= SIM_SCGC3_SPI2_MASK; // enable clock for SPI2 + SIM_SCGC6 &= ~SIM_SCGC6_CRC_MASK; // disable clock for CRC module + + // configure SPI2 pins: + // SCK: Port B, Pin 21 + // SDI: Port B, Pin 22 + // SDO: Port B, Pin 23 + // CSN0: Port C, Pin 0 + // CSN1: Port A, Pin 5 + // CSN2: Port C, Pin 4 + HAL.IOs->pins->SPI2_SCK.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_SDI.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_SDO.configuration.GPIO_Mode = GPIO_Mode_AF2; + HAL.IOs->pins->SPI2_CSN0.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->SPI2_CSN1.configuration.GPIO_Mode = GPIO_Mode_OUT; + HAL.IOs->pins->SPI2_CSN2.configuration.GPIO_Mode = GPIO_Mode_OUT; + + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->set(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN2); + + setTMCSPIParameters(SPI2_BASE_PTR); + + // configure default SPI channel_1 + SPIChannel_1_default = &HAL.SPI->ch1; + SPIChannel_1_default->CSN = &HAL.IOs->pins->SPI1_CSN; + // configure default SPI channel_2 + SPIChannel_2_default = &HAL.SPI->ch2; + SPIChannel_2_default->CSN = &HAL.IOs->pins->SPI2_CSN0; +} + +void setTMCSPIParameters(SPI_MemMapPtr basePtr) +{ + // set SPI2 to STOP mode + SPI_MCR_REG(basePtr) = SPI_MCR_HALT_MASK; + + // set SPI2 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(basePtr) |= SPI_MCR_MSTR_MASK + | SPI_MCR_CLR_RXF_MASK + | SPI_MCR_CLR_TXF_MASK; + + // baudrate => 48MHz/18 = 2.66MHz + SPI_CTAR_REG(basePtr, 0) = SPI_CTAR_FMSZ(7) // duty cycle 50/50; 8bit frame(7+1); inactive SCK state low; capture->leading; MSB first; + | SPI_CTAR_DT(2) // CS a SCK = 21ns[2ns]; after SCK = 21ns [2ns]; After transfer*8= 168ns [50ns] + | SPI_CTAR_BR(2) // prescaler value: 6 (BR=2, PBR=1 => 2,66MHz) (BR=1, PBR=1 => 4MHz) (BR=0, PBR=1 => ?MHz) + | SPI_CTAR_PBR(1) // prescaler value: 3 + | SPI_CTAR_CPHA_MASK // clock phase + | SPI_CTAR_PCSSCK(1) // shift NCS->SCK + | SPI_CTAR_PASC(1) // shift NCS->SCK + | SPI_CTAR_CPOL_MASK; // clk high in idle + + // set SPI2 to RUNNING mode + SPI_SR_REG(basePtr) |= SPI_SR_EOQF_MASK; + SPI_MCR_REG(basePtr) &= ~SPI_MCR_HALT_MASK; + SPI_MCR_REG(basePtr) &= ~SPI_MCR_FRZ_MASK; +} + +void reset_ch1() +{ + // configure SPI1 pins PORTB_PCR11(SCK), PORTB_PCR17(SDI), PORTB_PCR15(SDO), PORTB_PCR10(CSN) + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(SPI.ch1.CSN); + + // set SPI0 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(SPI.ch1.periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; +} + +void reset_ch2() +{ +// // configure SPI2 pins PORTB_PCR21(SCK), PORTB_PCR23(SDI), PORTB_PCR22(SDO), PORTC_PCR0(CSN0), PORTA_PCR0(CSN5), PORTA_PCR4(CSN2) + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(SPI.ch2.CSN); + SPI.ch2.readWrite = spi_ch2_readWrite; + + // set SPI0 to master mode, set inactive state of chip select to HIGH, flush both FIFO buffer by clearing their counters (Tx FIFO, and Rx FIFO are enabled) + SPI_MCR_REG(SPI.ch2.periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; +} + +// Helper lookup tables +static uint8_t PBR_values[4] = { 2, 3, 5, 7 }; +static uint16_t BR_values[16] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768 }; + +uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel) +{ + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + uint8_t pbr = PBR_values[FIELD_GET(tmp, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR_SHIFT)]; + uint8_t br = BR_values[FIELD_GET(tmp, SPI_CTAR_BR_MASK, SPI_CTAR_BR_SHIFT)]; + + return CPU_BUS_CLK_HZ / pbr / br; +} + +// Set the SPI frequency to the next-best available frequency (rounding down). +// Returns the actual frequency set or 0 if no suitable frequency was found. +uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency) +{ + if (!SPIChannel) + return 0; + + uint32_t bestFrequency = 0; + uint8_t bestPBR = 0; + uint8_t bestBR = 0; + + // Find the highest frequency that is lower or equal to the desired frequency + for (uint32_t i = 0; i < ARRAY_SIZE(PBR_values); i++) + { + // For each possible PBR prescaler value... + uint8_t pbr = PBR_values[i]; + uint32_t pbrFreq = CPU_BUS_CLK_HZ / pbr; + + // Calculate the ideal divisor (rounding up to not exceed the desired frequency) + uint32_t divisor = (pbrFreq + desiredFrequency - 1) / desiredFrequency; + + // Find the next-largest available BR divisor + uint32_t j; + for (j = 0; j < ARRAY_SIZE(BR_values); j++) + { + if (BR_values[j] >= divisor) + break; + } + + // If no BR divisor value is larger, check the next PBR value + if (j == ARRAY_SIZE(BR_values)) + continue; + + // Calculate the resulting actual frequency + uint32_t actualFrequency = pbrFreq / BR_values[j]; + + // Sanity check: Verify that the actual frequency is smaller than the desired frequency + if (actualFrequency > desiredFrequency) + continue; + + // Check if the actual frequency is better than the previous ones + // and store the parameters if it is. + if (actualFrequency > bestFrequency) + { + bestFrequency = actualFrequency; + bestPBR = i; + bestBR = j; + } + } + + // If we couldn't find a suitable frequency, abort + if (bestFrequency == 0) + return 0; + + // Update the hardware parameters + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0) & ~(SPI_CTAR_DT_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_PBR_MASK); + tmp |= SPI_CTAR_DT(0); + tmp |= SPI_CTAR_PBR(bestPBR); + tmp |= SPI_CTAR_BR(bestBR); + SPI_CTAR_REG(SPIChannel->periphery, 0) = tmp; + + return bestFrequency; +} + +uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel) +{ + if (!SPIChannel) + return 0; + + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + uint8_t cpol = FIELD_GET(tmp, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL_SHIFT); + uint8_t cpha = FIELD_GET(tmp, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA_SHIFT); + + return (cpol << 1) | cpha; +} + +bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode) +{ + if (!SPIChannel) + return false; + + if (mode > 3) + return false; + + uint8_t cpol = (mode>>1) & 1; + uint8_t cpha = mode & 1; + + uint32_t tmp = SPI_CTAR_REG(SPIChannel->periphery, 0); + tmp &= ~(SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK); + tmp |= cpol ? SPI_CTAR_CPOL_MASK : 0; + tmp |= cpha ? SPI_CTAR_CPHA_MASK : 0; + SPI_CTAR_REG(SPIChannel->periphery, 0) = tmp; + + return true; +} + +int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address) +{ + // clear write bit + address &= 0x7F; + + SPIChannel->readWrite(address, false); + int value = SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, true); + + return value; +} + +int32_t spi_ch1_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_1_default, address); +} + +int32_t spi_ch2_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_2_default, address); +} + +void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value) +{ + SPIChannel->readWrite(address|0x80, false); + SPIChannel->readWrite(0xFF & (value>>24), false); + SPIChannel->readWrite(0xFF & (value>>16), false); + SPIChannel->readWrite(0xFF & (value>>8), false); + SPIChannel->readWrite(0xFF & (value>>0), true); +} + +void spi_ch1_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_1_default, address, value); +} + +void spi_ch2_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_2_default, address, value); +} + +uint8_t spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(&SPI.ch1, data, lastTransfer); +} + +uint8_t spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(&SPI.ch2, data, lastTransfer); +} + +static void spi_ch1_readWriteArray(uint8_t *data, size_t length) +{ + for(size_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch1, data[i], (i == (length - 1))? true:false); + } +} + +static void spi_ch2_readWriteArray(uint8_t *data, size_t length) +{ + for(size_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch2, data[i], (i == (length - 1))? true:false); + } +} + +uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(SPIChannel_1_default, data, lastTransfer); +} + +uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + return SPIChannel->readWrite(data, lastTransfer); +} + +uint8_t readWrite(SPIChannelTypeDef *SPIChannel, uint8_t writeData, uint8_t lastTransfer) +{ + uint8_t readData = 0; + + if(IS_DUMMY_PIN(SPIChannel->CSN)) + return 0; + + HAL.IOs->config->setLow(SPIChannel->CSN); // Chip Select + + if(lastTransfer) + { + // send last byte + SPI_PUSHR_REG(SPIChannel->periphery) = SPI_PUSHR_EOQ_MASK | SPI_PUSHR_TXDATA(writeData) ; + + while(!(SPI_SR_REG(SPIChannel->periphery) & SPI_SR_EOQF_MASK)) {} // wait until End Of Queue flag has been set -> transfer done + + SPI_SR_REG(SPIChannel->periphery) |= SPI_SR_EOQF_MASK; // clear EOQ Flag by writing a 1 to EOQF + + HAL.IOs->config->setHigh(SPIChannel->CSN); // reset CSN manual, falls Probleme Auftreten, dann diese Zeile unter die while Schleife + + // wait for an answer + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT) == 0) {} + + // read the data + readData = SPI_POPR_REG(SPIChannel->periphery); + + // clear TXF and RXF + SPI_MCR_REG(SPIChannel->periphery) |= SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK; + } else { + // continuous transfer + SPI_PUSHR_REG(SPIChannel->periphery) = SPI_PUSHR_CONT_MASK | SPI_PUSHR_TXDATA(writeData); // | SPI_PUSHR_PCS(0x0); + + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT) > 3) {} // wait if TX counter > 3 + + // wait for an answer + while(((SPI_SR_REG(SPIChannel->periphery) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT) == 0) {} + + // read the data + readData = SPI_POPR_REG(SPIChannel->periphery); + } + + return readData; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c new file mode 100644 index 0000000..f85f9c9 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/SysTick.c @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/SysTick.h" + +volatile uint32_t systick = 0; + +void __attribute__ ((interrupt)) SysTick_Handler(void); + +void SysTick_Handler(void) +{ + systick++; +} + +void systick_init() +{ + SYST_RVR = 48000; + SYST_CSR = 7; + + // Enable the DWT CYCCNT for the µs counter + DWT_CTRL |= 0x00000001; +} + +uint32_t systick_getTick() +{ + return systick; +} + +uint32_t systick_getMicrosecondTick() +{ + // 48 MHz CYCCNT / 48 -> µs counter + return DWT_CYCCNT / 48; +} + +/* Systick values are in milliseconds, accessing the value is faster. As a result + * we have a random invisible delay of less than a millisecond whenever we use + * systicks. This can result in a situation where we access the systick just before it changes: + * -> Access at 0,99ms gives systick 0ms + * -> Access at 1.01ms gives systick 1ms + * -> systick difference of 1ms, even though only 0.02 ms passed + * To prevent this, we generally apply a correction of -1 to any systick difference. + * In wait() this is done by using '<=' instead of '<' + * In timeDiff() the subtraction is carried out on the result. + * That subtraction is prevented from underflowing to UINT32_MAX, returning 0 in + * that case (Saturated subtraction). + * + */ +void wait(uint32_t delay) // wait for [delay] ms/systicks +{ + uint32_t startTick = systick; + while((systick-startTick) <= delay) {} +} + +uint32_t timeSince(uint32_t tick) // time difference since the [tick] timestamp in ms/systicks +{ + return timeDiff(systick, tick); +} + +uint32_t timeDiff(uint32_t newTick, uint32_t oldTick) // Time difference between newTick and oldTick timestamps +{ + uint32_t tickDiff = newTick - oldTick; + + // Prevent subtraction underflow - saturate to 0 instead + if(tickDiff != 0) + return tickDiff - 1; + else + return 0; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c new file mode 100644 index 0000000..496b530 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/Timer.c @@ -0,0 +1,271 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/Timer.h" + +#define MAX_ARR_HALF TIMER_MAX >> 1 + +void __attribute__ ((interrupt)) FTM0_IRQHandler(void); + +static void init(void); +static void deInit(void); +static void setDuty(timer_channel channel, float duty); +static float getDuty(timer_channel channel); +static void setModulo(timer_channel channel, uint16_t modulo); +static uint16_t getModulo(timer_channel channel); +static void setModuloMin(timer_channel channel, uint16_t modulo_min); +static void setFrequency(timer_channel channel, float freq); +static void setFrequencyMin(timer_channel channel, float freq_min); + +static uint16_t modulo_buf = 0; +static uint16_t modulo_min_buf = 0; +static float duty_buf[] = { .5f, .5f, .5f }; +static float freq_min_buf = 0.0f; + +TimerTypeDef Timer = +{ + .initialized = false, + .init = init, + .deInit = deInit, + .setDuty = setDuty, + .getDuty = getDuty, + .setPeriod = setModulo, + .getPeriod = getModulo, + .setPeriodMin = setModuloMin, + .setFrequency = setFrequency, + .setFrequencyMin = setFrequencyMin, + .overflow_callback = NULL +}; + +static void init(void) +{ + // enable clock for FTM0 + SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; + + // enable clock for port D + SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; + + // disable write protection + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + + // FAULTM = 1 - Fault control is enabled for all channels, + // FTMEN = 1 - all registers are available for use with no restrictions. + FTM0_MODE |= FTM_MODE_FAULTM_MASK | FTM_MODE_FTMEN_MASK; + + // setting for Center Aligned PWM in Combine Mode + FTM0_MOD = TIMER_MAX; // set PWM frequency + modulo_buf = TIMER_MAX; + FTM0_CNTIN = 0; // CTNMAX = 1 - PWM update at counter in max. value + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + + // SWSYNC = 1 - set PWM value update. This bit is cleared automatically. + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + + // disable all channels outputs using the OUTPUT MASK feature + FTM0_OUTMASK = FTM_OUTMASK_CH0OM_MASK | FTM_OUTMASK_CH1OM_MASK + | FTM_OUTMASK_CH4OM_MASK | FTM_OUTMASK_CH5OM_MASK + | FTM_OUTMASK_CH6OM_MASK | FTM_OUTMASK_CH7OM_MASK; + + /* COMBINE = 1 - combine mode set, COMP = 1 - complementary PWM set, + DTEN = 1 - deadtime enabled, SYNCEN = 1 - PWM update synchronization enabled, + FAULTEN = 1 - fault control enabled */ + FTM0_COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DTEN0_MASK + | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_COMBINE0_MASK + | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_DTEN2_MASK + | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_COMBINE2_MASK + | FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_DTEN3_MASK + | FTM_COMBINE_COMP3_MASK | FTM_COMBINE_COMBINE3_MASK; + + // initialize setting of value registers to duty cycle + FTM0_C0V = 0; + FTM0_C1V = (uint16_t)(duty_buf[1] * TIMER_MAX); + FTM0_C4V = 0; + FTM0_C5V = (uint16_t)(duty_buf[2] * TIMER_MAX); + FTM0_C6V = 0; + FTM0_C7V = (uint16_t)(duty_buf[0] * TIMER_MAX); + + // set channel mode to generate positive PWM + FTM0_C0SC |= FTM_CnSC_ELSB_MASK; + FTM0_C1SC |= FTM_CnSC_ELSB_MASK; + FTM0_C4SC |= FTM_CnSC_ELSB_MASK; + FTM0_C5SC |= FTM_CnSC_ELSB_MASK; + FTM0_C6SC |= FTM_CnSC_ELSB_MASK; + FTM0_C7SC |= FTM_CnSC_ELSB_MASK; + + // enable loading of the MOD, CNTIN, and CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + // enable the generation of the trigger when the FTM counter is equal to the CNTIN register + FTM0_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK; + FTM0_MODE |= FTM_MODE_INIT_MASK; + + // set system clock as source for FTM0 (CLKS[1:0] = 01) + FTM0_SC |= FTM_SC_CLKS(1); // Periodendauer 166,66us + + // initialize pwm pin for FTM0 + + + + + // ATTENTION The Pins had to configure as AF4 near the initialisation !!!!!! + + + + + // enable PWM outputs of FTM0 + FTM0_OUTMASK = 0; + + FTM0_SC |= (uint32_t)(FTM_SC_TOIE_MASK); + + enable_irq(INT_FTM0-16); + + Timer.initialized = true; +} + +static void deInit(void) +{ + disable_irq(INT_FTM0-16); + SIM_SCGC6 &= ~SIM_SCGC6_FTM0_MASK; +} + +static void setDuty(timer_channel channel, float duty) +{ + duty = (duty < 0.0f) ? 0.0f : duty; + duty = (duty > 1.0f) ? 1.0f : duty; + + switch(channel) { + case TIMER_CHANNEL_2: + duty_buf[1] = duty; + FTM0_C1V = (uint16_t) (duty * modulo_buf); + break; + case TIMER_CHANNEL_3: + duty_buf[2] = duty; + FTM0_C5V = (uint16_t) (duty * modulo_buf); + break; + case TIMER_CHANNEL_1: + default: + duty_buf[0] = duty; + FTM0_C7V = (uint16_t) (duty * modulo_buf); + break; + } + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +static float getDuty(timer_channel channel) +{ + uint16_t duty = 0; + switch(channel) { + case TIMER_CHANNEL_2: + duty = (FTM0_C1V - FTM0_C0V); + break; + case TIMER_CHANNEL_3: + duty = (FTM0_C5V - FTM0_C4V); + break; + case TIMER_CHANNEL_1: + default: + duty = (FTM0_C7V - FTM0_C6V); + break; + } + + return (((float)duty) / modulo_buf); +} + +static void setModulo(timer_channel channel, uint16_t modulo) +{ + UNUSED(channel); + disable_irq(INT_FTM0-16); + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + FTM0_MOD = modulo; + modulo_buf = modulo; + FTM0_CNTIN = 0; + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + enable_irq(INT_FTM0-16); +} + +static uint16_t getModulo(timer_channel channel) +{ + UNUSED(channel); + //return FTM0_MOD; + return modulo_buf; +} + +static void setModuloMin(timer_channel channel, uint16_t modulo_min) +{ + UNUSED(channel); + modulo_min_buf = modulo_min; +} + +static void setFrequencyMin(timer_channel channel, float freq_min) +{ + UNUSED(channel); + freq_min_buf = freq_min; +} + +static void setFrequency(timer_channel channel, float freq) +{ + UNUSED(channel); + + if(freq < freq_min_buf) + return; + + if(freq < ((float)CPU_BUS_CLK_HZ / ((1 << 0b111) * 0xFFFF))) + return; + + if(freq > (float)CPU_BUS_CLK_HZ) + return; + + disable_irq(INT_FTM0-16); + + uint8_t ps = 0b000; + uint16_t modulo = 0xFFFF; + + for(; ps < 0b111; ps++) + { + if(freq > ((float)CPU_BUS_CLK_HZ / ((1 << ps) * modulo))) + { + modulo = (float)CPU_BUS_CLK_HZ / ((1 << ps) * freq); + if((modulo < modulo_min_buf) && (ps > 0b000)) + modulo = (float)CPU_BUS_CLK_HZ / ((1 << (ps - 1)) * freq); + break; + } + } + + modulo_buf = modulo; + + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + FTM0_SC |= FTM_SC_PS(ps); + FTM0_MOD = modulo; + FTM0_CNTIN = 0; + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + setDuty(TIMER_CHANNEL_1, duty_buf[0]); + setDuty(TIMER_CHANNEL_2, duty_buf[1]); + setDuty(TIMER_CHANNEL_3, duty_buf[2]); + + enable_irq(INT_FTM0-16); +} + +void FTM0_IRQHandler() +{ + if(FTM0_SC & FTM_SC_TOF_MASK) + { + // overflow detected + if(Timer.overflow_callback) + Timer.overflow_callback(TIMER_CHANNEL_2); + FTM0_SC &= ~FTM_SC_TOF_MASK; + } + + // Stop the timer + //FTM2_SC &= ~FTM_SC_CLKS_MASK; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c new file mode 100644 index 0000000..e3ae77a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/UART.c @@ -0,0 +1,470 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/UART.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#define BUFFER_SIZE 32 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 +#define WRITE_READ_DELAY 10 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static volatile uint32_t available = 0; + +UART_Config UART = +{ + .mode = UART_MODE_DUAL_WIRE, + .pinout = UART_PINS_1, + .rxtx = + { + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable + } +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd = (CPU_BUS_CLK_HZ / 16) / UART.rxtx.baudRate; + + // One wire UART communication needs the TxD pin to be in open drain mode + // and a pull-up resistor on the RxD pin. + switch(UART.pinout) { + case UART_PINS_2: + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO10) + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO11) + HAL.IOs->pins->DIO10.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO11.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; + UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + UART_C1_REG(UART0_BASE_PTR) = 0; + UART_C4_REG(UART0_BASE_PTR) = 0; + UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + enable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; + UART_C1_REG(UART2_BASE_PTR) = 0; + switch(UART.mode) { + case UART_MODE_SINGLE_WIRE: + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + HAL.IOs->pins->DIO18.configuration.GPIO_OType = GPIO_OType_OD; // RxD as open drain output + HAL.IOs->pins->DIO17.configuration.GPIO_PuPd = GPIO_PuPd_UP; // TxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + // Enable single wire UART + UART_C1_REG(UART2_BASE_PTR) |= (UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK); + // Set TxD as output in single wire UART + UART_C3_REG(UART2_BASE_PTR) |= UART_C3_TXDIR_MASK; + break; + case UART_MODE_DUAL_WIRE: + case UART_MODE_DUAL_WIRE_PushPull: + default: + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + HAL.IOs->pins->DIO17.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO18.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + break; + } + UART_C2_REG(UART2_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + UART_BDH_REG(UART2_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART2_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + UART_C2_REG(UART2_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + enable_irq(INT_UART2_RX_TX-16); + break; + } + +// /* Disable the transmitter and receiver */ +// UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); +// +// /* Configure the UART for 8-bit mode, no parity */ +// /* We need all default settings, so entire register is cleared */ +// UART_C1_REG(UART0_BASE_PTR) = 0; +// +// ubd = (CPU_BUS_CLK_HZ / 16) / UART.baudRate; +// +// UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; +// UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); +// +// /* Enable receiver and transmitter */ +// UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + +} + +static void deInit() +{ + switch(UART.pinout) { + case UART_PINS_2: + SIM_SCGC4 &= ~(SIM_SCGC4_UART0_MASK); + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + disable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + SIM_SCGC4 &= ~(SIM_SCGC4_UART2_MASK); + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + disable_irq(INT_UART2_RX_TX-16); + break; + } + + clearBuffers(); +} + +void UART0_RX_TX_IRQHandler_UART(void) +{ + static uint8_t isSending = false; + uint32_t status = UART0_S1; + + // Receive interrupt + if(status & UART_S1_RDRF_MASK) + { + // One-wire UART communication: + buffers.rx.buffer[buffers.rx.wrote] = UART0_D; + if(!isSending) // Only move ring buffer index & available counter when the received byte wasn't the send echo + { + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(status & UART_S1_TC_MASK) + { + // Last bit has been sent + isSending = false; + UART0_C2 &= ~UART_C2_TCIE_MASK; + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART0_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + + isSending = true; // Ignore echo + UART0_C2 |= UART_C2_TCIE_MASK; // Turn on transmission complete interrupt + } + else + { + UART0_C2 &= ~UART_C2_TIE_MASK; // empty buffer -> turn off transmit buffer empty interrupt + } + } +} + +void UART2_RX_TX_IRQHandler(void) +{ + static uint8_t isSending = false; + uint32_t status = UART2_S1; + + // Receive interrupt + if(status & UART_S1_RDRF_MASK) + { + // One-wire UART communication: + buffers.rx.buffer[buffers.rx.wrote] = UART2_D; + if(!isSending) // Only move ring buffer index & available counter when the received byte wasn't the send echo + { + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(status & UART_S1_TC_MASK) + { + // Last bit has been sent + isSending = false; + UART2_C2 &= ~UART_C2_TCIE_MASK; + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART2_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + + isSending = true; // Ignore echo + UART2_C2 |= UART_C2_TCIE_MASK; // Turn on transmission complete interrupt + } + else + { + UART2_C2 &= ~UART_C2_TIE_MASK; // empty buffer -> turn off transmit buffer empty interrupt + } + } +} + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = systick_getTick(); + while(uart->rxtx.bytesAvailable() < readLength) + { + if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + { + // Abort on timeout + return -1; + } + } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value) +{ + uint8_t readData[8], dataRequest[4]; + uint32_t timeout; + + dataRequest[0] = 0x05; // Sync byte + dataRequest[1] = slave; // Slave address + dataRequest[2] = address; // Register address + dataRequest[3] = tmc_CRC8(dataRequest, 3, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + channel->rxtx.txN(dataRequest, ARRAY_SIZE(dataRequest)); + + // Wait for reply with timeout limit + timeout = systick_getTick(); + while(channel->rxtx.bytesAvailable() < ARRAY_SIZE(readData)) + if(timeSince(timeout) > UART_TIMEOUT_VALUE) // Timeout + return; + + channel->rxtx.rxN(readData, ARRAY_SIZE(readData)); + // Check if the received data is correct (CRC, Sync, Slave address, Register address) + // todo CHECK 2: Only keep CRC check? Should be sufficient for wrong transmissions (LH) #1 + if(readData[7] != tmc_CRC8(readData, 7, 1) || readData[0] != 0x05 || readData[1] != 0xFF || readData[2] != address) + return; + + *value = readData[3] << 24 | readData[4] << 16 | readData[5] << 8 | readData[6]; + return; +} + +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value) +{ + uint8_t writeData[8]; + + writeData[0] = 0x05; // Sync byte + writeData[1] = slave; // Slave address + writeData[2] = address | TMC_WRITE_BIT; // Register address with write bit set + writeData[3] = value >> 24; // Register Data + writeData[4] = value >> 16; // Register Data + writeData[5] = value >> 8; // Register Data + writeData[6] = value & 0xFF; // Register Data + writeData[7] = tmc_CRC8(writeData, 7, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + for(uint32_t i = 0; i < ARRAY_SIZE(writeData); i++) + channel->rxtx.tx(writeData[i]); + + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); +} + +void UART_setEnabled(UART_Config *channel, uint8_t enabled) +{ + switch(channel->pinout) + { + case UART_PINS_2: + if (enabled) + { + HAL.IOs->pins->DIO10.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO10) + HAL.IOs->pins->DIO11.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO11) + HAL.IOs->pins->DIO10.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO11.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + HAL.IOs->config->set(&HAL.IOs->pins->DIO10); + HAL.IOs->config->set(&HAL.IOs->pins->DIO11); + } + else + { + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + } + break; + case UART_PINS_1: + if (enabled) + { + HAL.IOs->pins->DIO17.configuration.GPIO_Mode = GPIO_Mode_AF3; // TxD (DIO17) + HAL.IOs->pins->DIO18.configuration.GPIO_Mode = GPIO_Mode_AF3; // RxD (DIO18) + + if (channel->mode == UART_MODE_SINGLE_WIRE) + { + HAL.IOs->pins->DIO18.configuration.GPIO_OType = GPIO_OType_OD; // RxD as open drain output + HAL.IOs->pins->DIO17.configuration.GPIO_PuPd = GPIO_PuPd_UP; // TxD with pull-up resistor + } + else + { + HAL.IOs->pins->DIO17.configuration.GPIO_OType = (UART.mode == UART_MODE_DUAL_WIRE_PushPull)? GPIO_OType_PP : GPIO_OType_OD; + HAL.IOs->pins->DIO18.configuration.GPIO_PuPd = GPIO_PuPd_UP; // RxD with pull-up resistor + } + + HAL.IOs->config->set(&HAL.IOs->pins->DIO17); + HAL.IOs->config->set(&HAL.IOs->pins->DIO18); + } + else + { + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + } + break; + default: + break; + + } +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + + // enable send interrupt + switch(UART.pinout) { + case UART_PINS_2: + UART0_C2 |= UART_C2_TIE_MASK; + break; + case UART_PINS_1: + default: + UART2_C2 |= UART_C2_TIE_MASK; + break; + } +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + switch(UART.pinout) { + case UART_PINS_2: + disable_irq(INT_UART0_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART0_RX_TX-16); + break; + case UART_PINS_1: + default: + disable_irq(INT_UART2_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART2_RX_TX-16); + break; + } +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c new file mode 100644 index 0000000..4157498 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/USB.c @@ -0,0 +1,114 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/USB.h" + +#include "hal/Landungsbruecke/freescale/USB_CDC/USB0.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/USB1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/Tx1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/Rx1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/CDC1.h" +#include "hal/Landungsbruecke/freescale/USB_CDC/CS1.h" + +#if USB_USE_UNIQUE_SERIAL_NUMBER +#error "Landungsbruecke and LandungsbrueckeSmall do not yet support unique serial numbers" +#endif + + +extern uint8_t USB_DCI_DeInit(void); +extern uint8_t USB_Class_CDC_DeInit(uint8_t controller_ID); +extern uint8_t USB_Class_DeInit(uint8_t controller_ID); + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +RXTXTypeDef USB = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +void init() +{ + USB0_Init(); + Tx1_Init(); + Rx1_Init(); + USB1_Init(); + enable_irq(INT_USB0-16); +} + +uint8_t rx(uint8_t *ch) +{ + return rxN(ch,1); +} + +uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(CDC1_GetCharsInRxBuf() >= number) + { + for(int32_t i = 0; i < number; i++) + { + if(CDC1_GetChar(&str[i])!= ERR_OK) + return false; + } + return true; + } + return false; +} + +void tx(uint8_t ch) +{ + CDC1_SendChar(ch); +} + +void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + { + tx(str[i]); + } +} + +static void clearBuffers(void) +{ + DisableInterrupts; + Tx1_Init(); + Rx1_Init(); + EnableInterrupts; +} + +static uint32_t bytesAvailable() +{ + return CDC1_GetCharsInRxBuf(); +} + +static void deInit(void) +{ + USB_DCI_DeInit(); + USB_Class_CDC_DeInit(0); + USB_Class_DeInit(0); + + SIM_SCGC4 &= ~SIM_SCGC4_USBOTG_MASK; + SIM_SCGC6 &= ~SIM_SCGC6_USBDCD_MASK; + SIM_SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c new file mode 100644 index 0000000..f7b24e1 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke/tmc/WLAN.c @@ -0,0 +1,349 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +//#include "hal/WLAN.h" +#include "hal/Landungsbruecke/freescale/Cpu.h" + +#include + +#define BUFFER_SIZE 1024 +#define WLAN_CMD_BUFFER_SIZE 128 // ascii command string buffer + +#define CMDBUFFER_END_CHAR '\0' + +#define INTR_PRI 6 + +#define UART_TIMEOUT_VALUE 5 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, uint8_t number); +static uint8_t rxN(uint8_t *ch, uint8_t number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +// ring buffers (used in BufferingTypedef struct) +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; + +static int8_t cmdBuffer[WLAN_CMD_BUFFER_SIZE]; +static uint32_t cmdBufferSize = 0; +static uint32_t cmdEnabledTime; // systick timestamp when command mode sequence has been sent + +static WLANStateTypedef wlanState = WLAN_DATA_MODE; + +static volatile uint32_t available = 0; + +uint32_t UART0_TimeoutTimer; + +RXTXTypeDef WLAN = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 57600, + .bytesAvailable = bytesAvailable + +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +static void init() +{ + register uint16_t ubd; + + HAL.IOs->config->toOutput(&HAL.IOs->pins->MIXED6); + HAL.IOs->config->setLow(&HAL.IOs->pins->MIXED6); + + SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; + + HAL.IOs->pins->WIRELESS_RX.configuration.GPIO_Mode = GPIO_Mode_AF3; + HAL.IOs->pins->WIRELESS_TX.configuration.GPIO_Mode = GPIO_Mode_AF3; + + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_TX); + /* Disable the transmitter and receiver */ + UART_C2_REG(UART0_BASE_PTR) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); + + /* Configure the UART for 8-bit mode, no parity */ + /* We need all default settings, so entire register is cleared */ + UART_C1_REG(UART0_BASE_PTR) = 0; + + ubd = (CPU_BUS_CLK_HZ / 16) / (WLAN.baudRate); + + UART_BDH_REG(UART0_BASE_PTR) = (ubd >> 8) & UART_BDH_SBR_MASK; + UART_BDL_REG(UART0_BASE_PTR) = (ubd & UART_BDL_SBR_MASK); + + /* Enable receiver and transmitter */ + UART_C2_REG(UART0_BASE_PTR) |= (UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK); + + enable_irq(INT_UART0_RX_TX-16); +} + +static void deInit() +{ + SIM_SCGC4 &= ~(SIM_SCGC4_UART0_MASK); + + HAL.IOs->pins->WIRELESS_RX.configuration.GPIO_Mode = GPIO_Mode_IN; + HAL.IOs->pins->WIRELESS_TX.configuration.GPIO_Mode = GPIO_Mode_IN; + + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIRELESS_TX); + + disable_irq(INT_UART0_RX_TX-16); + + clearBuffers(); +} + +void UART0_RX_TX_IRQHandler_WLAN(void) +{ + uint32_t status = UART0_S1; + + if(status & UART_S1_RDRF_MASK) + { + buffers.rx.buffer[buffers.rx.wrote] = UART0_D; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + // reset timeout value + UART0_TimeoutTimer = UART_TIMEOUT_VALUE; + UART0_S1 &= ~(UART_S1_RDRF_MASK); // Zurücksetzen InterruptFlag + } + + if(status & UART_S1_TDRE_MASK) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UART0_D = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else // empty buffer -> turn off send interrupt + { + UART0_C2 &= ~UART_C2_TIE_MASK; + } + UART0_S1 &= ~(UART_S1_TDRE_MASK); // Zurücksetzen InterruptFlag + } +} + +// Send without checking for CMD/Data mode +static void rawTx(uint8_t ch) +{ + if(wlanState == WLAN_INIT_CMD_MODE) + return; + + buffers.tx.buffer[buffers.tx.wrote] = ch; + + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; // Move ring buffer index + + // enable send interrupt + UART0_C2 |= UART_C2_TIE_MASK; +} + +// Wrapper for rawTx, will silently fail if we're not in data mode +// todo CHECK ADD 3: Should tx be given a return type in order to report failure to send? (LH) #1 +static void tx(uint8_t ch) +{ + if(checkReadyToSend()) + rawTx(ch); +} + +static uint8_t rawRx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; // Move ring buffer index + available--; + + return 1; +} + +static uint8_t rx(uint8_t *ch) +{ + if(wlanState != WLAN_DATA_MODE) + return 0; + + return rawRx(ch); +} + +// todo CHECK ADD 3: Should txN be given a return type in order to report failure to send? (LH) #2 +static void txN(uint8_t *str, uint8_t number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, uint8_t number) +{ + if(available < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + disable_irq(INT_UART0_RX_TX-16); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + enable_irq(INT_UART0_RX_TX-16); +} + +static uint32_t bytesAvailable() +{ + return available; +} + +uint32_t checkReadyToSend() +{ + if(checkCmdModeEnabled()) + { + return false; + } + else + { + return (wlanState == WLAN_INIT_CMD_MODE)? false:true; + } +} + +void enableWLANCommandMode() +{ /* To enable command mode, the escape character (default: $) needs to be sent 3 times. + * Additionally, both before and after that sequence there should be 250ms without data sent to the module + * Since the configuration mode is supposed to be used as a simple testing tool, + * there is no check for the time span before the write. If the switching fails due to that, + * an error will be returned upon attempted command execution, just try to reenter command mode then. + */ + wlanState = WLAN_CMD_MODE; // Block external write sources + + clearBuffers(); + rawTx('$'); // txN doesn't work, as WLAN_CMD_MODE prevents tx (which txN calls) from writing to the buffer) + rawTx('$'); + rawTx('$'); + wlanState = WLAN_INIT_CMD_MODE; // Block all writes + cmdEnabledTime = systick_getTick(); +} + +uint32_t checkCmdModeEnabled() +{ + if(wlanState == WLAN_CMD_MODE) + return true; + else if(wlanState == WLAN_DATA_MODE) + return false; + + uint8_t reply[4] = { 0 }; // expected reply: {'C','M','D'}, we're appending \0 so we have a NULL-terminated string that we can use in strcmp() + if(rxN(reply, 3)) + { + if(strcmp((const char *)reply, "CMD") == 0) + { + wlanState = WLAN_CMD_MODE; + return true; + } + else + { // Unexpected answer - going back to data mode + wlanState = WLAN_DATA_MODE; + return false; + } + } + else + { + if(timeSince(cmdEnabledTime) > 350) // 250 ms from chip spec + 100ms, just to be safe + { // Too much time passed since attempted cmd mode switching happened - assuming it failed + wlanState = WLAN_DATA_MODE; + return false; + } + else + { // Not enough time passed, we're not in command mode yet but we're still giving the chip time + return false; + } + } +} + +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value) +{ + switch(cmd) + { + case BUFFER_CLEAR: + cmdBufferSize = 0; + break; + case BUFFER_WRITE: + while((value & 0xFF) != CMDBUFFER_END_CHAR) + { + if(cmdBufferSize == WLAN_CMD_BUFFER_SIZE) + { + if((value & 0xFF) != 0) // Any value still remaining -> too much data for buffer -> return an error + return 1; + break; + } + cmdBuffer[cmdBufferSize] = value & 0xFF; + value >>= 8; + cmdBufferSize++; + } + break; + case BUFFER_EXECUTE: + // Abort if not in command mode. IDE/User should switch to command mode before executing + if(!checkCmdModeEnabled()) + return 1; + + for(uint32_t i = 0; i < cmdBufferSize; i++) + rawTx(cmdBuffer[i]); // Can't use txN since its blocked from sending while in command mode + rawTx('\r'); // End of command character + + cmdBufferSize = 0; + break; + } + + return 0; +} + +uint32_t getCMDReply() +{ + uint8_t cmdReply; + uint32_t result = 0; + + for(uint8_t i = 0; i < 4; i++) + { + if(rawRx(&cmdReply) == 0) + cmdReply = 0; + // First character is in the smallest byte of result + result |= cmdReply << 24; + result >>= 8; + } + + return result; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld new file mode 100644 index 0000000..30d0f5a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425-tmcm.ld @@ -0,0 +1,161 @@ +/* +***************************************************************************** +** +** File : gd32f425.ld +** +** Abstract : Linker script for GD32F425VG Device with +** 1024KByte FLASH, 192KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** +** Target : GigaDevice GD32F425 (with TMCM bootloader) +** +** Environment : GCC +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of 192K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 224K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* special area for data exchange between boot loader and application + at the beginning of the RAM*/ + .bldata (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.bldata)) + . = ALIGN(4); + } > RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld new file mode 100644 index 0000000..a70030a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/gd32f425.ld @@ -0,0 +1,152 @@ +/* +***************************************************************************** +** +** File : gd32f425.ld +** +** Abstract : Linker script for GD32F425VG Device with +** 1024KByte FLASH, 192KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** +** Target : GigaDevice GD32F425 +** +** Environment : GCC +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of 192K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h new file mode 100644 index 0000000..f319458 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4.h @@ -0,0 +1,1790 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h new file mode 100644 index 0000000..bee997e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h new file mode 100644 index 0000000..adb07b5 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h new file mode 100644 index 0000000..624c175 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h new file mode 100644 index 0000000..ca0ff97 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx.h @@ -0,0 +1,368 @@ +/*! + \file gd32f4xx.h + \brief general definitions for GD32F4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_H +#define GD32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* define GD32F4xx */ +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) + /* #define GD32F450 */ + /* #define GD32F405 */ + /* #define GD32F407 */ + /* #define GD32F470 */ + #define GD32F425 + /* #define GD32F427 */ +#endif /* define GD32F4xx */ + +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) + #error "Please select the target GD32F4xx device in gd32f4xx.h file" +#endif /* undefine GD32F4xx tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined (HXTAL_VALUE) +#define HXTAL_VALUE ((uint32_t)16000000) +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ +#if !defined (IRC16M_VALUE) +#define IRC16M_VALUE ((uint32_t)16000000) +#endif /* internal 16MHz RC oscillator value */ + +/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */ +#if !defined (IRC16M_STARTUP_TIMEOUT) +#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 16MHz RC oscillator startup timeout */ + +/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ +#if !defined (IRC32K_VALUE) +#define IRC32K_VALUE ((uint32_t)32000) +#endif /* internal 32KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* I2S external clock in selection */ +//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U + +/* GD32F4xx firmware library version number V1.0 */ +#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F4xx_STDPERIPH_VERSION_RC)) + +/* configuration of the cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +/* define interrupt number */ +typedef enum IRQn +{ + /* cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ + RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC_IRQn = 18, /*!< ADC interrupt */ + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ + DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ + +#if defined (GD32F450) || defined (GD32F470) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ + UART6_IRQn = 82, /*!< UART6 interrupt */ + UART7_IRQn = 83, /*!< UART7 interrupt */ + SPI3_IRQn = 84, /*!< SPI3 interrupt */ + SPI4_IRQn = 85, /*!< SPI4 interrupt */ + SPI5_IRQn = 86, /*!< SPI5 interrupt */ + TLI_IRQn = 88, /*!< TLI interrupt */ + TLI_ER_IRQn = 89, /*!< TLI error interrupt */ + IPA_IRQn = 90, /*!< IPA interrupt */ +#endif /* GD32F450 and GD32F470 */ + +#if defined (GD32F405) || defined (GD32F425) + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F405 and GD32F425 */ + +#if defined (GD32F407) || defined (GD32F427) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F407 and GD32F427 */ + +} IRQn_Type; + +/* includes */ +#include "core_cm4.h" +#include "system_gd32f4xx.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */ +#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */ + +/* EXMC memory map */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */ + +/* advanced peripheral bus 2 memory map */ +#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */ +#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */ +/* advanced high performance bus 1 memory map */ +#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */ +#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */ +#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */ +#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */ + +/* advanced high performance bus 2 memory map */ +#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */ +#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */ +#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */ +/* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +//#if !defined USE_STDPERIPH_DRIVER +//#define USE_STDPERIPH_DRIVER +//#endif +//#ifdef USE_STDPERIPH_DRIVER +#include "gd32f4xx_libopt.h" +//#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h new file mode 100644 index 0000000..3596924 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_adc.h @@ -0,0 +1,516 @@ +/*! + \file gd32f4xx_adc.h + \brief definitions for the ADC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_ADC_H +#define GD32F4XX_ADC_H + +#include "gd32f4xx.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x100U) +#define ADC2 (ADC_BASE + 0x200U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ +#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ +#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */ +#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ +#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */ +#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ +#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */ +#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */ +#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ + +/* ADC_SSTAT */ +#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ +#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ +#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ +#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ +#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ +#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ +#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ +#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ +#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ +#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ +#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ +#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ +#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ +#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ +#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ +#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ +#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ +#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ + +/* ADC_SYNCCTL */ +#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ +#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ +#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ +#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ +#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ +#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ +#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ + +/* ADC_SYNCDATA */ +#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */ + +/* constants definitions */ +/* ADC status flag */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */ +#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* ADC special function definitions */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* temperature sensor channel, internal reference voltage channel, VBAT channel */ +#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ +#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ + +/* ADC synchronization mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */ +#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */ +#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* external trigger mode for routine and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ + +/* ADC external trigger select for routine channel */ +#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ + +/* ADC external trigger select for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ + +/* ADC channel sample time */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +/* ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ + +/* ADC interrupt flag */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ + +/* configure the ADC clock for all the ADCs */ +#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ +#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ +#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ +#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ +#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ +#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ +#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ +#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ + +/* ADC synchronization delay */ +#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ +#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ +#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ +#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ +#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ +#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ +#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ +#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ +#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ +#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ +#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ +#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ +#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ +#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ +#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ +#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ + +/* ADC synchronization DMA mode selection */ +#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ +#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ +#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ + +/* end of conversion mode */ +#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */ +#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(void); +/* configure the ADC clock for all the ADCs */ +void adc_clock_config(uint32_t prescaler); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* configure temperature sensor and internal reference voltage channel or VBAT channel function */ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue); +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); +/* when DMA=1, the DMA engine issues a request at end of each routine conversion */ +void adc_dma_request_after_last_enable(uint32_t adc_periph); +/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ +void adc_dma_request_after_last_disable(uint32_t adc_periph); + +/* routine sequence and inserted sequence config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); +/* configure end of conversion mode */ +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); + +/* get channel data */ +/* read ADC routine data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); + +/* watchdog config */ +/* disable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_disable(uint32_t adc_periph ); +/* enable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); +/* configure ADC analog watchdog sequence */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); + +/* ADC synchronization */ +/* configure the ADC sync mode */ +void adc_sync_mode_config(uint32_t sync_mode); +/* configure the delay between 2 sampling phases in ADC sync modes */ +void adc_sync_delay_config(uint32_t sample_delay); +/* configure ADC sync DMA mode selection */ +void adc_sync_dma_config(uint32_t dma_mode ); +/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */ +void adc_sync_dma_request_after_last_enable(void); +/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ +void adc_sync_dma_request_after_last_disable(void); +/* read ADC sync routine data register */ +uint32_t adc_sync_routine_data_read(void); + +#endif /* GD32F4XX_ADC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h new file mode 100644 index 0000000..897dbc1 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_can.h @@ -0,0 +1,750 @@ +/*! + \file gd32f4xx_can.h + \brief definitions for the CAN + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_CAN_H +#define GD32F4XX_CAN_H + +#include "gd32f4xx.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive FIFO mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* constants definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum { + /* flags in STAT register */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + /* flags in TSTAT register */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; + +/* CAN interrupt flags */ +typedef enum { + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ + /* interrupt flags in ERR register */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +} can_interrupt_flag_enum; + +/* CAN initiliaze parameters structure */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode disable */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +} can_parameter_struct; + +/* CAN transmit message structure */ +typedef struct { + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +} can_trasnmit_message_struct; + +/* CAN receive message structure */ +typedef struct { + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters structure */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits */ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +} can_filter_parameter_struct; + +/* CAN errors */ +typedef enum { + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +} can_error_enum; + +/* transmit states */ +typedef enum { + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +typedef enum { + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +} can_struct_type_enum; + +/* CAN baudrate prescaler */ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1 */ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2 */ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width */ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode */ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number */ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier */ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier */ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier */ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) + +/* receive mailbox standard identifier */ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive FIFO */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive FIFO */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN structure */ +void can_struct_para_init(can_struct_type_enum type, void *p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +/* CAN filter initialization */ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); + +/* function configuration */ +/* set can1 filter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release FIFO */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error type */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* interrupt & flag functions */ +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F4XX_CAN_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h new file mode 100644 index 0000000..ef4d3ae --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_crc.h @@ -0,0 +1,81 @@ +/*! + \file gd32f4xx_crc.h + \brief definitions for the CRC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_CRC_H +#define GD32F4XX_CRC_H + +#include "gd32f4xx.h" + +/* CRC definitions */ +#define CRC CRC_BASE /*!< CRC base address */ + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F4XX_CRC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h new file mode 100644 index 0000000..0542676 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ctc.h @@ -0,0 +1,185 @@ +/*! + \file gd32f4xx_ctc.h + \brief definitions for the CTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_CTC_H +#define GD32F4XX_CTC_H + +#include "gd32f4xx.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ +#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ +#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t hardmode); + +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t reload_value); + +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t int_flag); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); + +#endif /* GD32F4XX_CTC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h new file mode 100644 index 0000000..cf0d7da --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dac.h @@ -0,0 +1,271 @@ +/*! + \file gd32f4xx_dac.h + \brief definitions for the DAC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DAC_H +#define GD32F4XX_DAC_H + +#include "gd32f4xx.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* DAC_STAT */ +#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ +#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +/* enable DAC concurrent interrupt */ +void dac_concurrent_interrupt_enable(void); +/* disable DAC concurrent interrupt */ +void dac_concurrent_interrupt_disable(void); + +/* DAC interrupt configuration */ +/* get the specified DAC flag(DAC DMA underrun flag) */ +FlagStatus dac_flag_get(uint32_t dac_periph); +/* clear the specified DAC flag(DAC DMA underrun flag) */ +void dac_flag_clear(uint32_t dac_periph); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); +/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +FlagStatus dac_interrupt_flag_get(uint32_t dac_periph); +/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +void dac_interrupt_flag_clear(uint32_t dac_periph); + +#endif /* GD32F4XX_DAC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h new file mode 100644 index 0000000..bd50df3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dbg.h @@ -0,0 +1,153 @@ +/*! + \file gd32f4xx_dbg.h + \brief definitions for the DBG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DBG_H +#define GD32F4XX_DBG_H + +#include "gd32f4xx.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ +#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ +#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ + +/* DBG_CTL1 */ +#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ +#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */ +#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */ + +/* DBG_CTL2 */ +#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */ +#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +enum dbg_reg_idx +{ + DBG_IDX_CTL0 = 0x04U, + DBG_IDX_CTL1 = 0x08U, + DBG_IDX_CTL2 = 0x0CU +}; + +typedef enum +{ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ + DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ + DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ + DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ + DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ +}dbg_periph_enum; + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); + +#endif /* GD32F4XX_DBG_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h new file mode 100644 index 0000000..4dfc811 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dci.h @@ -0,0 +1,239 @@ +/*! + \file gd32f4xx_dci.h + \brief definitions for the DCI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DCI_H +#define GD32F4XX_DCI_H + +#include "gd32f4xx.h" + +/* DCI definitions */ +#define DCI DCI_BASE + +/* registers definitions */ +#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */ +#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */ +#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */ +#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */ +#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */ +#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */ +#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */ +#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */ +#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */ +#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */ +#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */ + +/* bits definitions */ +/* DCI_CTL */ +#define DCI_CTL_CAP BIT(0) /*!< capture enable */ +#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ +#define DCI_CTL_WDEN BIT(2) /*!< window enable */ +#define DCI_CTL_JM BIT(3) /*!< JPEG mode */ +#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ +#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ +#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ +#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ +#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ +#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ +#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ + +/* DCI_STAT0 */ +#define DCI_STAT0_HS BIT(0) /*!< HS line status */ +#define DCI_STAT0_VS BIT(1) /*!< VS line status */ +#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */ + +/* DCI_STAT1 */ +#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */ +#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */ +#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */ +#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */ +#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */ + +/* DCI_INTEN */ +#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */ +#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */ +#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */ +#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */ +#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */ + +/* DCI_INTF */ +#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */ +#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */ + +/* DCI_INTC */ +#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */ +#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */ +#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */ +#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */ +#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */ + +/* DCI_SC */ +#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */ +#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */ +#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */ +#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */ + +/* DCI_SCUNMSK */ +#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */ +#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */ + +/* DCI_CWSPOS */ +#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */ +#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */ + +/* DCI_CWSZ */ +#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */ +#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ + +/* constants definitions */ +/* DCI parameter structure definitions */ +typedef struct +{ + uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ + uint32_t clock_polarity; /*!< clock polarity selection */ + uint32_t hsync_polarity; /*!< horizontal polarity selection */ + uint32_t vsync_polarity; /*!< vertical polarity selection */ + uint32_t frame_rate; /*!< frame capture rate */ + uint32_t interface_format; /*!< digital camera interface format */ +}dci_parameter_struct; + +#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ +#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ + +#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */ +#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */ + +#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ +#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */ + +#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ +#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) +#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ +#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ +#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ + +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ +#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ + +/* DCI interrupt constants definitions */ +#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ +#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ +#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ +#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ +#define DCI_INT_EL BIT(4) /*!< end of line interrupt */ + +/* DCI interrupt flag definitions */ +#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ +#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ + +/* DCI flag definitions */ +#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ +#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ +#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ +#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ +#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ +#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ +#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ +#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ + +/* function declarations */ +/* initialization functions */ +/* DCI deinit */ +void dci_deinit(void); +/* initialize DCI registers */ +void dci_init(dci_parameter_struct* dci_struct); + +/* enable DCI function */ +void dci_enable(void); +/* disable DCI function */ +void dci_disable(void); +/* enable DCI capture */ +void dci_capture_enable(void); +/* disable DCI capture */ +void dci_capture_disable(void); +/* enable DCI jpeg mode */ +void dci_jpeg_enable(void); +/* disable DCI jpeg mode */ +void dci_jpeg_disable(void); + +/* function configuration */ +/* enable cropping window function */ +void dci_crop_window_enable(void); +/* disable cropping window function */ +void dci_crop_window_disable(void); +/* configure DCI cropping window */ +void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); + +/* enable embedded synchronous mode */ +void dci_embedded_sync_enable(void); +/* disable embedded synchronous mode */ +void dci_embedded_sync_disable(void); +/* configure synchronous codes in embedded synchronous mode */ +void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); +/* configure synchronous codes unmask in embedded synchronous mode */ +void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); + +/* read DCI data register */ +uint32_t dci_data_read(void); + +/* interrupt & flag functions */ +/* get specified flag */ +FlagStatus dci_flag_get(uint32_t flag); +/* enable specified DCI interrupt */ +void dci_interrupt_enable(uint32_t interrupt); +/* disable specified DCI interrupt */ +void dci_interrupt_disable(uint32_t interrupt); + + +/* get specified interrupt flag */ +FlagStatus dci_interrupt_flag_get(uint32_t int_flag); +/* clear specified interrupt flag */ +void dci_interrupt_flag_clear(uint32_t int_flag); + +#endif /* GD32F4XX_DCI_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h new file mode 100644 index 0000000..cffbbf8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_dma.h @@ -0,0 +1,428 @@ +/*! + \file gd32f4xx_dma.h + \brief definitions for the DMA + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_DMA_H +#define GD32F4XX_DMA_H + +#include "gd32f4xx.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */ +#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */ +#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */ +#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */ +#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */ +#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */ +#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */ +#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */ +#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */ +#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */ +#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */ +#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */ +#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */ +#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */ +#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */ +#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */ +#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */ +#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */ + +#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */ +#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */ +#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */ +#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */ +#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */ +#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */ +#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */ +#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */ +#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */ +#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */ + +/* DMA_INTC */ +#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */ +#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */ +#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */ +#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */ +#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */ + +/* DMA_CHxCTL,x=0..7 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */ +#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */ +#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */ +#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */ +#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */ +#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */ +#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */ +#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */ +#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */ +#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */ +#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */ +#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */ +#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */ +#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */ +#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */ + +/* DMA_CHxCNT,x=0..7 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..7 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxM0ADDR,x=0..7 */ +#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ + +/* DMA_CHxM1ADDR,x=0..7 */ +#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ + +/* DMA_CHxFCTL,x=0..7 */ +#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ +#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */ +#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */ +#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel 0 */ + DMA_CH1, /*!< DMA Channel 1 */ + DMA_CH2, /*!< DMA Channel 2 */ + DMA_CH3, /*!< DMA Channel 3 */ + DMA_CH4, /*!< DMA Channel 4 */ + DMA_CH5, /*!< DMA Channel 5 */ + DMA_CH6, /*!< DMA Channel 6 */ + DMA_CH7 /*!< DMA Channel 7 */ +} dma_channel_enum; + +/* DMA peripheral select */ +typedef enum +{ + DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ + DMA_SUBPERI1, /*!< DMA Peripheral 1 */ + DMA_SUBPERI2, /*!< DMA Peripheral 2 */ + DMA_SUBPERI3, /*!< DMA Peripheral 3 */ + DMA_SUBPERI4, /*!< DMA Peripheral 4 */ + DMA_SUBPERI5, /*!< DMA Peripheral 5 */ + DMA_SUBPERI6, /*!< DMA Peripheral 6 */ + DMA_SUBPERI7 /*!< DMA Peripheral 7 */ +} dma_subperipheral_enum; + +/* DMA multidata mode initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t periph_inc; /*!< peripheral increasing mode */ + + uint32_t memory0_addr; /*!< memory 0 base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t memory_inc; /*!< memory increasing mode */ + + uint32_t memory_burst_width; /*!< multi data mode enable */ + uint32_t periph_burst_width; /*!< multi data mode enable */ + uint32_t critical_value; /*!< FIFO critical */ + + uint32_t circular_mode; /*!< DMA circular mode */ + uint32_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +}dma_multi_data_parameter_struct; + +/* DMA singledata mode initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_inc; /*!< peripheral increasing mode */ + + uint32_t memory0_addr; /*!< memory 0 base address */ + uint32_t memory_inc; /*!< memory increasing mode */ + + uint32_t periph_memory_width; /*!< transfer data size of peripheral */ + + uint32_t circular_mode; /*!< DMA circular mode */ + uint32_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +} dma_single_data_parameter_struct; + +#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */ +#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */ +#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* peripheral select */ +#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25)) +#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */ +#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */ +#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */ +#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */ +#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */ +#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */ +#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */ +#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */ + +/* burst type of memory */ +#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23)) +#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */ +#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */ +#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */ +#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */ + +/* burst type of peripheral */ +#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */ +#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */ +#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */ +#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* transfer data width of memory */ +#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */ + +/* transfer data width of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */ +#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */ +#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */ + +/* channel transfer mode */ +#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */ +#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */ + +/* FIFO counter critical value */ +#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */ +#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */ +#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */ +#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */ + +/* memory select */ +#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */ +#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */ + +/* DMA circular mode */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */ + +/* DMA flow controller select */ +#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */ +#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */ + +/* FIFO status */ +#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */ +#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */ +#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */ +#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */ +#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */ +#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ +#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + +/* flag bits */ +#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the DMA single data mode parameters struct with the default values */ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); +/* initialize the DMA multi data mode parameters struct with the default values */ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); +/* DMA single data mode initialize */ +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); +/* DMA multi data mode initialize */ +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA Memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); + +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); + +/* configure transfer burst beats of memory */ +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); +/* configure transfer burst beats of peripheral */ +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); +/* configure transfer data size of memory */ +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); + +/* configure next address increasement algorithm of memory */ +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); +/* configure next address increasement algorithm of peripheral */ +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); + +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); + +/* DMA switch buffer mode config */ +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); +/* DMA using memory get */ +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA channel peripheral select */ +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); +/* DMA flow controller configure */ +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); +/* DMA flow controller enable */ +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); +/* DMA FIFO status get */ +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* check DMA flag is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); + +#endif /* GD32F4XX_DMA_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h new file mode 100644 index 0000000..4363c43 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_enet.h @@ -0,0 +1,1681 @@ +/*! + \file gd32f4xx_enet.h + \brief definitions for the ENET + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_ENET_H +#define GD32F4XX_ENET_H + +#include "gd32f4xx.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +//#define SELECT_DESCRIPTORS_ENHANCED_MODE + +//#define USE_DELAY + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ +#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_DBG */ +#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ +#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ +#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ +#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ +#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ +#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ +#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ +#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ +#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ +#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ +#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ +#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ +#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ +#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ + +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ +#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ +#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ +#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ +#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ +#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ +#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ +#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ +#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ +#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ +#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDAND */ +#define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_PTP_TSF */ +#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ +#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ + +/* ENET_PTP_PPSCTL */ +#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ +#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ + +/* ENET_DMA_RSWDC */ +#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Tx descriptor TDES6 */ +#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES7 */ +#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Rx descriptor RDES4 */ +#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ +#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ +#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ +#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ +#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ +#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ +#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ +#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ +#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ + +/* ENET DMA Rx descriptor RDES6 */ +#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ + +/* ENET DMA Rx descriptor RDES7 */ +#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ + +#define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ + +#define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum +{ + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_PTP_TSF register */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum +{ + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +}enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum +{ + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum +{ + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +}enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum +{ + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +}enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum +{ + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +}enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum +{ + ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +}enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum +{ + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +}enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum +{ + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +}enet_frmrecept_enum; + +/* register group value get */ +typedef enum +{ + ALL_MAC_REG = 0U, /*!< MAC register group */ + ALL_MSC_REG = 22U, /*!< MSC register group */ + ALL_PTP_REG = 33U, /*!< PTP register group */ + ALL_DMA_REG = 44U, /*!< DMA register group */ +}enet_registers_type_enum; + +/* dma direction select */ +typedef enum +{ + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +}enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum +{ + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +}enet_phydirection_enum; + +/* register operation direction select */ +typedef enum +{ + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +}enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum +{ + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +}enet_macaddress_enum; + +/* descriptor information */ +typedef enum +{ + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +}enet_descstate_enum; + +/* MSC counters preset mode */ +typedef enum +{ + ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ + ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ + ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ +}enet_msc_preset_enum; + +typedef enum{ + ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ + ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ + ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ + ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ + ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ + ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ + ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ + ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ + ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ + ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ + ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ + ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ +}enet_ptp_function_enum; + +/* structure for initialization of the ENET */ +typedef struct +{ + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +}enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct +{ + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + uint32_t extended_status; /*!< extended status */ + uint32_t reserved; /*!< reserved */ + uint32_t timestamp_low; /*!< timestamp low */ + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct +{ + uint32_t second; /*!< second of system time */ + uint32_t subsecond; /*!< subsecond of system time */ + uint32_t sign; /*!< sign of system time */ +}enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_dbg register value */ +#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ +#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ +#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ +#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ +#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ +#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ +#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ +#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ +#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ +#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ + +#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ + +#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ + +#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ + +#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ + +#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0)) << 8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4)) << 8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ +#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ +#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ +#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ +#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ +#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* ptp_ppsctl register value */ +#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ +#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ +#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ +#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ +#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ +#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ +#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ +#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ +#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ +#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ +#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ +#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ +#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ +#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ +#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ +#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ +#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ +#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ +#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma_rswdc register value */ +#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ +#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ +#else +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + + + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* get the enet debug status from the debug register */ +uint32_t enet_debug_status_get(uint32_t mac_debug); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + + +/* special enhanced mode function */ +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* get the bit of extended status flag in ENET DMA descriptor */ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); +/* configure descriptor to work in enhanced mode */ +void enet_desc_select_enhanced_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); +/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) + +#else + +/* configure descriptor to work in normal mode */ +void enet_desc_select_normal_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* configure MAC statistics counters preset mode */ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure the PPS output frequency */ +void enet_ptp_pps_output_frequency_config(uint32_t freq); + + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); + + +#endif /* GD32F4XX_ENET_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h new file mode 100644 index 0000000..4b05227 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exmc.h @@ -0,0 +1,814 @@ +/*! + \file gd32f4xx_exmc.h + \brief definitions for the EXMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_EXMC_H +#define GD32F4XX_EXMC_H + +#include "gd32f4xx.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ +#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ +#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ +#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ +#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ + +/* SDRAM */ +#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ +#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ + +#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ +#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ + +#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ +#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ +#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ +#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ + +/* SQPI PSRAM */ +#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ +#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ +#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ +#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ +#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ + +/* bits definitions */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1..2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* EXMC_SDCTLx,x=0..1 */ +#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ +#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ +#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ +#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ +#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ +#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ +#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ +#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ +#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ + +/* EXMC_SDTCFGx,x=0..1 */ +#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ +#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ +#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ +#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ +#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ +#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ +#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ + +/* EXMC_SDCMD */ +#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ +#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ +#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ +#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ +#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ + +/* EXMC_SDARI */ +#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ +#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ +#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */ + +/* EXMC_SDSTAT */ +#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ +#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ +#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ +#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ + +/* EXMC_SDRSCTL */ +#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ +#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ +#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ + +/* EXMC_SINIT */ +#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ +#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ +#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ +#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ + +/* EXMC_SRCMD */ +#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ +#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ +#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ +#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ + +/* EXMC_SWCMD */ +#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ +#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ +#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ + +/* EXMC_SIDL */ +#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ + +/* EXMC_SIDH */ +#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize structure */ +typedef struct +{ + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize structure */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + parameters for read if the extendedmode is used. */ + exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ +}exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize structure */ +typedef struct +{ + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +}exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize structure */ +typedef struct +{ + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +}exmc_nand_parameter_struct; + +/* EXMC PC card initialize structure */ +typedef struct +{ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ +}exmc_pccard_parameter_struct; + +/* EXMC SDRAM timing initialize structure */ +typedef struct +{ + uint32_t row_to_column_delay; /*!< configure the row to column delay */ + uint32_t row_precharge_delay; /*!< configure the row precharge delay */ + uint32_t write_recovery_delay; /*!< configure the write recovery delay */ + uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ + uint32_t row_address_select_delay; /*!< configure the row address select delay */ + uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ + uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ +}exmc_sdram_timing_parameter_struct; + +/* EXMC SDRAM initialize structure */ +typedef struct +{ + uint32_t sdram_device; /*!< device of SDRAM */ + uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ + uint32_t burst_read_switch; /*!< enable or disable the burst read */ + uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ + uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ + uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ + uint32_t internal_bank_number; /*!< the number of internal bank */ + uint32_t data_width; /*!< the databus width of SDRAM memory */ + uint32_t row_address_width; /*!< the bit width of a row address */ + uint32_t column_address_width; /*!< the bit width of a column address */ + exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ +}exmc_sdram_parameter_struct; + +/* EXMC SDRAM command initialize structure */ +typedef struct +{ + uint32_t mode_register_content; /*!< the SDRAM mode register content */ + uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */ + uint32_t bank_select; /*!< the bank which command will be sent to */ + uint32_t command; /*!< the commands that will be sent to SDRAM */ +}exmc_sdram_command_parameter_struct; + +/* EXMC SQPISRAM initialize structure */ +typedef struct{ + uint32_t sample_polarity; /*!< read data sample polarity */ + uint32_t id_length; /*!< SPI PSRAM ID length */ + uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */ + uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ +}exmc_sqpipsram_parameter_struct; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ + +#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ +#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ + +/* CRAM page size */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ + +/* SDRAM pipeline delay */ +#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ + +/* SDRAM clock configuration */ +#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) +#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ +#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ +#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ + +/* CAS latency */ +#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) +#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ +#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ +#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ + +/* SDRAM data bus width */ +#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ + +/* SDRAM row address bit width */ +#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ + +/* SDRAM column address bit width */ +#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ +#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ +#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ +#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ + +/* SDRAM number of successive auto-refresh */ +#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ +#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ + +/* SDRAM command selection */ +#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ +#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ +#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ +#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ +#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ +#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ +#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ + +/* SDRAM the delayed sample clock of read data */ +#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ +#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ +#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ +#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ +#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ +#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ +#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ +#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ +#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ +#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ +#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ +#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ +#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ +#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ +#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ +#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ + +/* SPI PSRAM ID length */ +#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) +#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ + +/* SPI PSRAM bit number of address phase */ +#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) +#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ + +/* SPI PSRAM bit number of command phase */ +#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ + +/* SPI PSRAM read command mode */ +#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ + +/* SPI PSRAM write command mode */ +#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC consecutive clock */ +#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ +#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ + +/* EXMC SDRAM bank definition */ +#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ +#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ + +/* EXMC SDRAM internal banks */ +#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ +#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ + +/* SDRAM device0 selection */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */ + +/* SDRAM device1 selection */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */ + +/* SDRAM device status */ +#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ +#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ +#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ + +/* sample cycle of read data */ +#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ + +/* read data sample polarity */ +#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ +#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ + +/* SQPI SRAM command flag */ +#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ +#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ +#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ +#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ +#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ + +/* function declarations */ +/* initialization functions */ +/* NOR/SRAM */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* enable EXMC NOR/SRAM region */ +void exmc_norsram_enable(uint32_t exmc_norsram_region); +/* disable EXMC NOR/SRAM region */ +void exmc_norsram_disable(uint32_t exmc_norsram_region); +/* NAND */ +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize exmc_nand_parameter_struct with the default values */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* enable EXMC NAND bank */ +void exmc_nand_enable(uint32_t exmc_nand_bank); +/* disable EXMC NAND bank */ +void exmc_nand_disable(uint32_t exmc_nand_bank); +/* PC card */ +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize exmc_pccard_parameter_struct with the default values */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* enable EXMC PC card bank */ +void exmc_pccard_enable(void); +/* disable EXMC PC card bank */ +void exmc_pccard_disable(void); +/* SDRAM */ +/* deinitialize EXMC SDRAM device */ +void exmc_sdram_deinit(uint32_t exmc_sdram_device); +/* initialize exmc_sdram_parameter_struct with the default values */ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize EXMC SDRAM device */ +void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); +/* SQPIPSRAM */ +/* deinitialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_deinit(void); +/* initialize exmc_sqpipsram_parameter_struct with the default values */ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* initialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); + +/* function configuration */ +/* NOR/SRAM */ +/* configure consecutive clock */ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); +/* configure CRAM page size */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* NAND */ +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); +/* SDRAM */ +/* enable or disable read sample */ +void exmc_sdram_readsample_enable(ControlStatus newvalue); +/* configure the delayed sample clock of read data */ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); +/* configure the SDRAM memory command */ +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); +/* set auto-refresh interval */ +void exmc_sdram_refresh_count_set(uint32_t exmc_count); +/* set the number of successive auto-refresh command */ +void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); +/* configure the write protection function */ +void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); +/* get the status of SDRAM device0 or device1 */ +uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); +/* SQPIPSRAM */ +/* set the read command */ +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); +/* set the write command */ +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code); +/* send SPI read ID command */ +void exmc_sqpipsram_read_id_command_send(void); +/* send SPI special command which does not have address and data phase */ +void exmc_sqpipsram_write_cmd_send(void); +/* get the EXMC SPI ID low data */ +uint32_t exmc_sqpipsram_low_id_get(void); +/* get the EXMC SPI ID high data */ +uint32_t exmc_sqpipsram_high_id_get(void); +/* get the bit value of EXMC send write command bit or read ID command */ +FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); + +/* interrupt & flag functions */ +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); +/* get EXMC flag status */ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); +/* clear EXMC flag status */ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); +/* get EXMC interrupt flag */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); +/* clear EXMC interrupt flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); + +#endif /* GD32F4XX_EXMC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h new file mode 100644 index 0000000..08a7dc7 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_exti.h @@ -0,0 +1,277 @@ +/*! + \file gd32f4xx_exti.h + \brief definitions for the EXTI + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_EXTI_H +#define GD32F4XX_EXTI_H + +#include "gd32f4xx.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ +#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ +#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ +#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< none EXTI edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); +/* EXTI software interrupt event enable */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* EXTI software interrupt event disable */ +void exti_software_interrupt_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32F4XX_EXTI_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h new file mode 100644 index 0000000..aca5a7d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fmc.h @@ -0,0 +1,415 @@ +/*! + \file gd32f4xx_fmc.h + \brief definitions for the FMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2020-12-20, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_FMC_H +#define GD32F4XX_FMC_H + +#include "gd32f4xx.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option byte base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */ +#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */ +#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */ +#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ + +#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ +#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ +#define OB_SPC REG32((OB) + 0x00010001U) /*!< option byte security protection value */ +#define OB_WP0 REG32((OB) + 0x00010008U) /*!< option byte write protection 0 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WC_WSCNT BITS(0,3) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte key bits */ + +/* FMC_STAT */ +#define FMC_STAT_END BIT(0) /*!< end of operation flag bit */ +#define FMC_STAT_OPERR BIT(1) /*!< flash operation error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< erase/Program protection error flag bit */ +#define FMC_STAT_PGMERR BIT(6) /*!< program size not match error flag bit */ +#define FMC_STAT_PGSERR BIT(7) /*!< program sequence error flag bit */ +#define FMC_STAT_RDDERR BIT(8) /*!< read D-bus protection error flag bit */ +#define FMC_STAT_BUSY BIT(16) /*!< flash busy flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_SER BIT(1) /*!< main flash sector erase command bit */ +#define FMC_CTL_MER0 BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL_SN BITS(3,7) /*!< select which sector number to be erased */ +#define FMC_CTL_PSZ BITS(8,9) /*!< program size bit */ +#define FMC_CTL_MER1 BIT(15) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL_START BIT(16) /*!< send erase command to FMC bit */ +#define FMC_CTL_ENDIE BIT(24) /*!< end of operation interrupt enable bit */ +#define FMC_CTL_ERRIE BIT(25) /*!< error interrupt enable bit */ +#define FMC_CTL_LK BIT(31) /*!< FMC_CTL lock bit */ + +/* FMC_OBCTL0 */ +#define FMC_OBCTL0_OB_LK BIT(0) /*!< FMC_OBCTL0 lock bit */ +#define FMC_OBCTL0_OB_START BIT(1) /*!< send option byte change command to FMC bit */ +#define FMC_OBCTL0_BOR_TH BITS(2,3) /*!< option byte BOR threshold value */ +#define FMC_OBCTL0_BB BIT(4) /*!< option byte boot bank value */ +#define FMC_OBCTL0_NWDG_HW BIT(5) /*!< option byte watchdog value */ +#define FMC_OBCTL0_NRST_DPSLP BIT(6) /*!< option byte deepsleep reset value */ +#define FMC_OBCTL0_NRST_STDBY BIT(7) /*!< option byte standby reset value */ +#define FMC_OBCTL0_SPC BITS(8,15) /*!< option byte Security Protection code */ +#define FMC_OBCTL0_WP0 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ +#define FMC_OBCTL0_DBS BIT(30) /*!< double banks or single bank selection when flash size is 1M bytes */ +#define FMC_OBCTL0_DRP BIT(31) /*!< D-bus read protection bit */ + +/* FMC_OBCTL1 */ +#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ + +/* FMC_PECFG */ +#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */ +#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */ + +/* FMC_PEKEY */ +#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_RDDERR, /*!< read D-bus protection error */ + FMC_PGSERR, /*!< program sequence error */ + FMC_PGMERR, /*!< program size not match error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_OPERR, /*!< operation error */ + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ +#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */ + +#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ +#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ + +/* option byte write protection */ +#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ +#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ + +/* FMC wait state counter */ +#define WC_WSCNT(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WC_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WC_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WC_WSCNT(2) /*!< FMC 2 wait */ +#define WS_WSCNT_3 WC_WSCNT(3) /*!< FMC 3 wait */ +#define WS_WSCNT_4 WC_WSCNT(4) /*!< FMC 4 wait */ +#define WS_WSCNT_5 WC_WSCNT(5) /*!< FMC 5 wait */ +#define WS_WSCNT_6 WC_WSCNT(6) /*!< FMC 6 wait */ +#define WS_WSCNT_7 WC_WSCNT(7) /*!< FMC 7 wait */ +#define WS_WSCNT_8 WC_WSCNT(8) /*!< FMC 8 wait */ +#define WS_WSCNT_9 WC_WSCNT(9) /*!< FMC 9 wait */ +#define WS_WSCNT_10 WC_WSCNT(10) /*!< FMC 10 wait */ +#define WS_WSCNT_11 WC_WSCNT(11) /*!< FMC 11 wait */ +#define WS_WSCNT_12 WC_WSCNT(12) /*!< FMC 12 wait */ +#define WS_WSCNT_13 WC_WSCNT(13) /*!< FMC 13 wait */ +#define WS_WSCNT_14 WC_WSCNT(14) /*!< FMC 14 wait */ +#define WS_WSCNT_15 WC_WSCNT(15) /*!< FMC 15 wait */ + +/* option byte BOR threshold value */ +#define OBCTL0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval))<< 2) +#define OB_BOR_TH_VALUE3 OBCTL0_BOR_TH(0) /*!< BOR threshold value 3 */ +#define OB_BOR_TH_VALUE2 OBCTL0_BOR_TH(1) /*!< BOR threshold value 2 */ +#define OB_BOR_TH_VALUE1 OBCTL0_BOR_TH(2) /*!< BOR threshold value 1 */ +#define OB_BOR_TH_OFF OBCTL0_BOR_TH(3) /*!< no BOR function */ + +/* option byte boot bank value */ +#define OBCTL0_BB(regval) (BIT(4) & ((uint32_t)(regval)<<4)) +#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ +#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ + +/* option byte software/hardware free watch dog timer */ +#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) +#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ +#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ + +/* option byte reset or not entering deep sleep mode */ +#define OBCTL0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval))<< 6) +#define OB_DEEPSLEEP_NRST OBCTL0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST OBCTL0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */ + +/* option byte reset or not entering standby mode */ +#define OBCTL0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval))<< 7) +#define OB_STDBY_NRST OBCTL0_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST OBCTL0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xAAU) /*!< no security protection */ +#define FMC_LSPC ((uint8_t)0xABU) /*!< low security protection */ +#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */ +#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */ + +/* option bytes D-bus read protection */ +#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */ +#define OB_DRP_1 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 1 */ +#define OB_DRP_2 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 2 */ +#define OB_DRP_3 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 3 */ +#define OB_DRP_4 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 4 */ +#define OB_DRP_5 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 5 */ +#define OB_DRP_6 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 6 */ +#define OB_DRP_7 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 7 */ +#define OB_DRP_8 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 8 */ +#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */ +#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */ +#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */ +#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */ +#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */ +#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */ +#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */ +#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */ +#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */ +#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */ +#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */ +#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */ +#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ +#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ +#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ +#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */ + +/* double banks or single bank selection when flash size is 1M bytes */ +#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U)) +#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ +#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ + +/* option bytes D-bus read protection mode */ +#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U)) +#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ +#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ + +/* FMC sectors */ +#define CTL_SN(regval) (BITS(3,7) & ((uint32_t)(regval))<< 3) +#define CTL_SECTOR_NUMBER_0 CTL_SN(0) /*!< sector 0 */ +#define CTL_SECTOR_NUMBER_1 CTL_SN(1) /*!< sector 1 */ +#define CTL_SECTOR_NUMBER_2 CTL_SN(2) /*!< sector 2 */ +#define CTL_SECTOR_NUMBER_3 CTL_SN(3) /*!< sector 3 */ +#define CTL_SECTOR_NUMBER_4 CTL_SN(4) /*!< sector 4 */ +#define CTL_SECTOR_NUMBER_5 CTL_SN(5) /*!< sector 5 */ +#define CTL_SECTOR_NUMBER_6 CTL_SN(6) /*!< sector 6 */ +#define CTL_SECTOR_NUMBER_7 CTL_SN(7) /*!< sector 7 */ +#define CTL_SECTOR_NUMBER_8 CTL_SN(8) /*!< sector 8 */ +#define CTL_SECTOR_NUMBER_9 CTL_SN(9) /*!< sector 9 */ +#define CTL_SECTOR_NUMBER_10 CTL_SN(10) /*!< sector 10 */ +#define CTL_SECTOR_NUMBER_11 CTL_SN(11) /*!< sector 11 */ +#define CTL_SECTOR_NUMBER_24 CTL_SN(12) /*!< sector 24 */ +#define CTL_SECTOR_NUMBER_25 CTL_SN(13) /*!< sector 25 */ +#define CTL_SECTOR_NUMBER_26 CTL_SN(14) /*!< sector 26 */ +#define CTL_SECTOR_NUMBER_27 CTL_SN(15) /*!< sector 27 */ +#define CTL_SECTOR_NUMBER_12 CTL_SN(16) /*!< sector 12 */ +#define CTL_SECTOR_NUMBER_13 CTL_SN(17) /*!< sector 13 */ +#define CTL_SECTOR_NUMBER_14 CTL_SN(18) /*!< sector 14 */ +#define CTL_SECTOR_NUMBER_15 CTL_SN(19) /*!< sector 15 */ +#define CTL_SECTOR_NUMBER_16 CTL_SN(20) /*!< sector 16 */ +#define CTL_SECTOR_NUMBER_17 CTL_SN(21) /*!< sector 17 */ +#define CTL_SECTOR_NUMBER_18 CTL_SN(22) /*!< sector 18 */ +#define CTL_SECTOR_NUMBER_19 CTL_SN(23) /*!< sector 19 */ +#define CTL_SECTOR_NUMBER_20 CTL_SN(24) /*!< sector 20 */ +#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */ +#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */ +#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ + + +/* FMC program size */ +#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U) +#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ +#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ +#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ + +/* FMC interrupt enable */ +#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ +#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ + +/* FMC flags */ +#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */ +#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */ +#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */ +#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */ +#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ + +/* FMC interrupt flags */ +#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */ +#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */ +#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */ +#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */ +#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */ +#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */ + + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_addr); +#endif +/* FMC erase sector */ +fmc_state_enum fmc_sector_erase(uint32_t fmc_sector); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); +/* FMC program a byte at the corresponding address */ +fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* send option byte change command */ +void ob_start(void); +/* erase option byte */ +void ob_erase(void); +/* enable write protect */ +ErrStatus ob_write_protection_enable(uint32_t ob_wp); +/* disable write protect */ +ErrStatus ob_write_protection_disable(uint32_t ob_wp); +/* enable erase/program protection and D-bus read protection */ +void ob_drp_enable(uint32_t ob_drp); +/* disable erase/program protection and D-bus read protection */ +void ob_drp_disable(void); +/* configure security protection level */ +void ob_security_protection_config(uint8_t ob_spc); +/* program the FMC user option byte */ +void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); +/* program the option byte BOR threshold value */ +void ob_user_bor_threshold(uint32_t ob_bor_th); +/* configure the boot mode */ +void ob_boot_mode_config(uint32_t boot_mode); +/* get the FMC user option byte */ +uint8_t ob_user_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection0_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection1_get(void); +/* get the FMC erase/program protection and D-bus read protection option bytes value */ +uint16_t ob_drp0_get(void); +/* get the FMC erase/program protection and D-bus read protection option bytes value */ +uint16_t ob_drp1_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); +/* get the FMC option byte BOR threshold value */ +uint8_t ob_user_bor_threshold_get(void); + +/* FMC interrupts and flags management functions */ +/* get flag set or reset */ +FlagStatus fmc_flag_get(uint32_t fmc_flag); +/* clear the FMC pending flag */ +void fmc_flag_clear(uint32_t fmc_flag); +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t fmc_int); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t fmc_int); +/* get FMC interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag); +/* clear the FMC interrupt flag */ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag); +/* get the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check whether FMC is ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); + +#endif /* GD32F4XX_FMC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h new file mode 100644 index 0000000..af0a897 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_fwdgt.h @@ -0,0 +1,114 @@ +/*! + \file gd32f4xx_fwdgt.h + \brief definitions for the FWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_FWDGT_H +#define GD32F4XX_FWDGT_H + +#include "gd32f4xx.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F4XX_FWDGT_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h new file mode 100644 index 0000000..5a69385 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_gpio.h @@ -0,0 +1,409 @@ +/*! + \file gd32f4xx_gpio.h + \brief definitions for the GPIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_GPIO_H +#define GD32F4XX_GPIO_H + +#include "gd32f4xx.h" + +/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) +#define GPIOH (GPIO_BASE + 0x00001C00U) +#define GPIOI (GPIO_BASE + 0x00002000U) + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ +#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD */ +#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/ pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) + +/* GPIO pull-up/ pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed level */ +#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ +#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ +#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ +#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ +#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ +#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ +#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ +#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ +#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */ +#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */ +#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */ +#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */ +#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */ +#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32F4XX_GPIO_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h new file mode 100644 index 0000000..2a1a88a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_i2c.h @@ -0,0 +1,413 @@ +/*! + \file gd32f4xx_i2c.h + \brief definitions for the I2C + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_I2C_H +#define GD32F4XX_I2C_H + +#include "gd32f4xx.h" + +/* I2Cx(x=0,1,2) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */ +#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* I2Cx_FCTL */ +#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ +#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ + +/* I2Cx_SAMCS */ +#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ +#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ +#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ +#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ +#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ +#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ +#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ +#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + /* flags in SAMCS register */ + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ + /* interrupt flags in SAMCS register */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ + /* interrupt in SAMCS register */ + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ +} i2c_interrupt_enum; + +/* the digital noise filter can filter spikes's length */ +typedef enum { + I2C_DF_DISABLE = 0, /*!< disable digital noise filter */ + I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ + I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ + I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ + I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ + I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ + I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ + I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ + I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ + I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ + I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ + I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ + I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ + I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ + I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ + I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ +} i2c_digital_filter_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ + +/* PEC transfer */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ + +/* function declarations */ +/* initialization functions */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); + +/* application function declarations */ +/* select SMBus type */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* configure software reset of I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); +/* disable analog noise filter */ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph); +/* enable analog noise filter */ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph); +/* configure digital noise filter */ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara); +/* enable SAM_V interface */ +void i2c_sam_enable(uint32_t i2c_periph); +/* disable SAM_V interface */ +void i2c_sam_disable(uint32_t i2c_periph); +/* enable SAM_V interface timeout detect */ +void i2c_sam_timeout_enable(uint32_t i2c_periph); +/* disable SAM_V interface timeout detect */ +void i2c_sam_timeout_disable(uint32_t i2c_periph); + +/* interrupt & flag functions */ +/* get I2C flag status */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag status */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* get I2C interrupt flag status */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag status */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32F4XX_I2C_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h new file mode 100644 index 0000000..22e77d1 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_ipa.h @@ -0,0 +1,381 @@ +/*! + \file gd32f4xx_ipa.h + \brief definitions for the IPA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_IPA_H +#define GD32F4XX_IPA_H + +#include "gd32f4xx.h" + +/* TLI definitions */ +#define IPA IPA_BASE /*!< IPA base address */ + +/* bits definitions */ +/* registers definitions */ +#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */ +#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */ +#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */ +#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */ +#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */ +#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */ +#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */ +#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */ +#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */ +#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */ +#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */ +#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */ +#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */ +#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */ +#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */ +#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */ +#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */ +#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */ +#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */ +#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */ + +/* IPA_CTL */ +#define IPA_CTL_TEN BIT(0) /*!< transfer enable */ +#define IPA_CTL_THU BIT(1) /*!< transfer hang up */ +#define IPA_CTL_TST BIT(2) /*!< transfer stop */ +#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */ +#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */ +#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */ +#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */ +#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */ +#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */ +#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */ + +/* IPA_INTF */ +#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */ +#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */ +#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */ +#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */ +#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */ +#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */ + +/* IPA_INTC */ +#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */ +#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */ +#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */ +#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */ +#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */ +#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */ + +/* IPA_FMADDR */ +#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */ + +/* IPA_FLOFF */ +#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */ + +/* IPA_BMADDR */ +#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */ + +/* IPA_BLOFF */ +#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */ + +/* IPA_FPCTL */ +#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */ +#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */ +#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */ +#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */ +#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */ +#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */ + +/* IPA_FPV */ +#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */ +#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */ +#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */ + +/* IPA_BPCTL */ +#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */ +#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */ +#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */ +#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */ +#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */ +#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */ + +/* IPA_BPV */ +#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */ +#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */ +#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */ + +/* IPA_FLMADDR */ +#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */ + +/* IPA_BLMADDR */ +#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */ + +/* IPA_DPCTL */ +#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ + +/* IPA_DPV */ +/* destination pixel format ARGB8888 */ +#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */ + +/* destination pixel format RGB8888 */ +#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */ + +/* destination pixel format RGB565 */ +#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */ + +/* destination pixel format ARGB1555 */ +#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */ + +/* destination pixel format ARGB4444 */ +#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */ +#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */ +#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */ +#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */ + +/* IPA_DMADDR */ +#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */ + +/* IPA_DLOFF */ +#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */ + +/* IPA_IMS */ +#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */ +#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */ + +/* IPA_LM */ +#define IPA_LM_LM BITS(0,15) /*!< line mark */ + +/* IPA_ITCTL */ +#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */ +#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */ + + +/* constants definitions */ +/* IPA foreground parameter struct definitions */ +typedef struct { + uint32_t foreground_memaddr; /*!< foreground memory base address */ + uint32_t foreground_lineoff; /*!< foreground line offset */ + uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ + uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */ + uint32_t foreground_pf; /*!< foreground pixel format */ + uint32_t foreground_prered; /*!< foreground pre-defined red value */ + uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ + uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ +} ipa_foreground_parameter_struct; + +/* IPA background parameter struct definitions */ +typedef struct { + uint32_t background_memaddr; /*!< background memory base address */ + uint32_t background_lineoff; /*!< background line offset */ + uint32_t background_prealpha; /*!< background pre-defined alpha value */ + uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ + uint32_t background_pf; /*!< background pixel format */ + uint32_t background_prered; /*!< background pre-defined red value */ + uint32_t background_pregreen; /*!< background pre-defined green value */ + uint32_t background_preblue; /*!< background pre-defined blue value */ +} ipa_background_parameter_struct; + +/* IPA destination parameter struct definitions */ +typedef struct { + uint32_t destination_memaddr; /*!< destination memory base address */ + uint32_t destination_lineoff; /*!< destination line offset */ + uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ + uint32_t destination_pf; /*!< destination pixel format */ + uint32_t destination_prered; /*!< destination pre-defined red value */ + uint32_t destination_pregreen; /*!< destination pre-defined green value */ + uint32_t destination_preblue; /*!< destination pre-defined blue value */ + uint32_t image_width; /*!< width of the image to be processed */ + uint32_t image_height; /*!< height of the image to be processed */ +} ipa_destination_parameter_struct; + +/* destination pixel format */ +typedef enum { + IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ + IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ + IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ + IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ + IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ +} ipa_dpf_enum; + +/* LUT pixel format */ +#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */ +#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */ + +/* Inter-timer */ +#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */ +#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */ + +/* IPA pixel format convert mode */ +#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */ +#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */ +#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */ +#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */ + +/* foreground alpha value calculation algorithm */ +#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */ +#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */ +#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */ + +/* background alpha value calculation algorithm */ +#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */ +#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */ +#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */ + +/* foreground pixel format */ +#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */ +#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */ +#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */ +#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */ +#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */ +#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */ +#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */ +#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */ +#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */ +#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */ +#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */ + +/* background pixel format */ +#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) +#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */ +#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */ +#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */ +#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */ +#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */ +#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */ +#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */ +#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */ +#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */ +#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */ +#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */ + +/* IPA flags */ +#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* IPA interrupt enable or disable */ +#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */ +#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */ +#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */ +#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */ +#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */ +#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */ + +/* IPA interrupt flags */ +#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* function declarations */ +/* functions enable or disable, pixel format convert mode set */ +/* deinitialize IPA */ +void ipa_deinit(void); +/* enable IPA transfer */ +void ipa_transfer_enable(void); +/* enable IPA transfer hang up */ +void ipa_transfer_hangup_enable(void); +/* disable IPA transfer hang up */ +void ipa_transfer_hangup_disable(void); +/* enable IPA transfer stop */ +void ipa_transfer_stop_enable(void); +/* disable IPA transfer stop */ +void ipa_transfer_stop_disable(void); +/* enable IPA foreground LUT loading */ +void ipa_foreground_lut_loading_enable(void); +/* enable IPA background LUT loading */ +void ipa_background_lut_loading_enable(void); +/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm); + +/* structure initialization, foreground, background, destination and LUT initialization */ +/* initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct); +/* initialize foreground parameters */ +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct); +/* initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined */ +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct); +/* initialize background parameters */ +void ipa_background_init(ipa_background_parameter_struct *background_struct); +/* initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined */ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct); +/* initialize destination parameters */ +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct); +/* initialize IPA foreground LUT parameters */ +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); +/* initialize IPA background LUT parameters */ +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr); + +/* configuration functions */ +/* configure IPA line mark */ +void ipa_line_mark_config(uint16_t line_num); +/* inter-timer enable or disable */ +void ipa_inter_timer_config(uint8_t timer_cfg); +/* configure the number of clock cycles interval */ +void ipa_interval_clock_num_config(uint8_t clk_num); + +/* flag and interrupt functions */ +/* get IPA flag status in IPA_INTF register */ +FlagStatus ipa_flag_get(uint32_t flag); +/* clear IPA flag in IPA_INTF register */ +void ipa_flag_clear(uint32_t flag); +/* enable IPA interrupt */ +void ipa_interrupt_enable(uint32_t int_flag); +/* disable IPA interrupt */ +void ipa_interrupt_disable(uint32_t int_flag); +/* get IPA interrupt flag */ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag); +/* clear IPA interrupt flag */ +void ipa_interrupt_flag_clear(uint32_t int_flag); + +#endif /* GD32F4XX_IPA_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h new file mode 100644 index 0000000..1b297a0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_iref.h @@ -0,0 +1,187 @@ +/*! + \file gd32f4xx_iref.h + \brief definitions for the IREF + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_IREF_H +#define GD32F4XX_IREF_H + +#include "gd32f4xx.h" + +/* IREF definitions */ +#define IREF IREF_BASE /*!< IREF base address */ + +/* registers definitions */ +#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */ + +/* bits definitions */ +/* IREF_CTL */ +#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ +#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ +#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ +#define IREF_CTL_SSEL BIT(14) /*!< step selection */ +#define IREF_CTL_CREN BIT(15) /*!< current reference enable */ + +/* constants definitions */ +/* IREF current precision trim */ +#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) +#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */ +#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */ +#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */ +#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */ +#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */ +#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */ +#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */ +#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */ +#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */ +#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */ +#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */ +#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */ +#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */ +#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */ +#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */ +#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */ +#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */ +#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */ +#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */ +#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */ +#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */ +#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */ +#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */ +#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */ +#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */ +#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */ +#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */ +#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */ +#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */ +#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */ +#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */ +#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */ + +/* IREF current step */ +#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) +#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */ +#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */ +#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */ +#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */ +#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */ +#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */ +#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */ +#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */ +#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */ +#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */ +#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */ +#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */ +#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */ +#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */ +#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */ +#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */ +#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */ +#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */ +#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */ +#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */ +#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */ +#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */ +#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */ +#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */ +#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */ +#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */ +#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */ +#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */ +#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */ +#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */ +#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */ +#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */ +#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */ +#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */ +#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */ +#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */ +#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */ +#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */ +#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */ +#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */ +#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */ +#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */ +#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */ +#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */ +#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */ +#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */ +#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */ +#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */ +#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */ +#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */ +#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */ +#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */ +#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */ +#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */ +#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */ +#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */ +#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */ +#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */ +#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */ +#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ +#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ +#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ + +/* IREF mode selection */ +#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) +#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ +#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ + +/* IREF sink current mode*/ +#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ +#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ + +/* function declarations */ +/* deinitialize IREF */ +void iref_deinit(void); +/* enable IREF */ +void iref_enable(void); +/* disable IREF */ +void iref_disable(void); + +/* set IREF mode*/ +void iref_mode_set(uint32_t step); +/* set IREF sink current mode*/ +void iref_sink_set(uint32_t sinkmode); +/* set IREF current precision trim value */ +void iref_precision_trim_value_set(uint32_t precisiontrim); +/* set IREF step data*/ +void iref_step_data_config(uint32_t stepdata); + +#endif /* GD32F4XX_IREF_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h new file mode 100644 index 0000000..8624095 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_libopt.h @@ -0,0 +1,81 @@ +/*! + \file gd32f4xx_libopt.h + \brief library optional for gd32f4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_LIBOPT_H +#define GD32F4XX_LIBOPT_H + +#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407) || defined (GD32F470) || defined (GD32F425) || defined (GD32F427) +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_adc.h" +#include "gd32f4xx_can.h" +#include "gd32f4xx_crc.h" +#include "gd32f4xx_ctc.h" +#include "gd32f4xx_dac.h" +#include "gd32f4xx_dbg.h" +#include "gd32f4xx_dci.h" +#include "gd32f4xx_dma.h" +#include "gd32f4xx_exti.h" +#include "gd32f4xx_fmc.h" +#include "gd32f4xx_fwdgt.h" +#include "gd32f4xx_gpio.h" +#include "gd32f4xx_syscfg.h" +#include "gd32f4xx_i2c.h" +#include "gd32f4xx_iref.h" +#include "gd32f4xx_pmu.h" +#include "gd32f4xx_rtc.h" +#include "gd32f4xx_sdio.h" +#include "gd32f4xx_spi.h" +#include "gd32f4xx_timer.h" +#include "gd32f4xx_trng.h" +#include "gd32f4xx_usart.h" +#include "gd32f4xx_wwdgt.h" +#include "gd32f4xx_misc.h" +#endif + +#if defined (GD32F450) || defined (GD32F470) +#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#include "gd32f4xx_ipa.h" +#include "gd32f4xx_tli.h" +#endif + +#if defined (GD32F407) || defined (GD32F427) +#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#endif + +#endif /* GD32F4XX_LIBOPT_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h new file mode 100644 index 0000000..278cca6 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_misc.h @@ -0,0 +1,93 @@ +/*! + \file gd32f4xx_misc.h + \brief definitions for the MISC + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_MISC_H +#define GD32F4XX_MISC_H + +#include "gd32f4xx.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F4XX_MISC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h new file mode 100644 index 0000000..375dbf0 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_pmu.h @@ -0,0 +1,206 @@ +/*! + \file gd32f4xx_pmu.h + \brief definitions for the PMU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_PMU_H +#define GD32F4XX_PMU_H + +#include "gd32f4xx.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ + +/* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */ + +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU low-driver mode when use low power LDO */ +#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU low-driver mode when use normal power LDO */ +#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + + +/* PMU high-driver mode switch */ +#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ + +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU backup SRAM LDO on or off */ +#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) +#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ +#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* LVD functions */ +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* LDO functions */ +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); + +/* functions of low-driver mode and high-driver mode */ +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* backup SRAM LDO on */ +void pmu_backup_ldo_config(uint32_t bkp_ldo); +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); + +#endif /* GD32F4XX_PMU_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h new file mode 100644 index 0000000..2426374 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rcu.h @@ -0,0 +1,1183 @@ +/*! + \file gd32f4xx_rcu.h + \brief definitions for the RCU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_RCU_H +#define GD32F4XX_RCU_H + +#include "gd32f4xx.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */ +#define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */ +#define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */ +#define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */ +#define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */ +#define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */ +#define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */ +#define RCU_AHB1EN REG32(RCU + 0x30U) /*!< AHB1 enable register */ +#define RCU_AHB2EN REG32(RCU + 0x34U) /*!< AHB2 enable register */ +#define RCU_AHB3EN REG32(RCU + 0x38U) /*!< AHB3 enable register */ +#define RCU_APB1EN REG32(RCU + 0x40U) /*!< APB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ +#define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ +#define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ +#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ +#define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ +#define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ +#define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ +#define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ +#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ +#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ +#define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#define RCU_ADDAPB1SPEN REG32(RCU + 0xE8U) /*!< APB1 additional sleep mode enable register */ +#define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL */ +#define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ +#define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ +#define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ +#define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ +#define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ + +/* RCU_PLL */ +#define RCU_PLL_PLLPSC BITS(0,5) /*!< The PLL VCO source clock prescaler */ +#define RCU_PLL_PLLN BITS(6,14) /*!< The PLL VCO clock multi factor */ +#define RCU_PLL_PLLP BITS(16,17) /*!< The PLLP output frequency division factor from PLL VCO clock */ +#define RCU_PLL_PLLSEL BIT(22) /*!< PLL Clock Source Selection */ +#define RCU_PLL_PLLQ BITS(24,27) /*!< The PLL Q output frequency division factor from PLL VCO clock */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(10,12) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(13,15) /*!< APB2 prescaler selection */ +#define RCU_CFG0_RTCDIV BITS(16,20) /*!< RTC clock divider factor */ +#define RCU_CFG0_CKOUT0SEL BITS(21,22) /*!< CKOUT0 Clock Source Selection */ +#define RCU_CFG0_I2SSEL BIT(23) /*!< I2S Clock Source Selection */ +#define RCU_CFG0_CKOUT0DIV BITS(24,26) /*!< The CK_OUT0 divider which the CK_OUT0 frequency can be reduced */ +#define RCU_CFG0_CKOUT1DIV BITS(27,29) /*!< The CK_OUT1 divider which the CK_OUT1 frequency can be reduced */ +#define RCU_CFG0_CKOUT1SEL BITS(30,31) /*!< CKOUT1 Clock Source Selection */ + +/* RCU_INT */ +#define RCU_INT_IRC32KSTBIF BIT(0) /*!< IRC32K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC16MSTBIF BIT(2) /*!< IRC16M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLLI2SSTBIF BIT(5) /*!< PLLI2S stabilization interrupt flag */ +#define RCU_INT_PLLSAISTBIF BIT(6) /*!< PLLSAI stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC32KSTBIE BIT(8) /*!< IRC32K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC16MSTBIE BIT(10) /*!< IRC16M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLLI2SSTBIE BIT(13) /*!< PLLI2S Stabilization Interrupt Enable */ +#define RCU_INT_PLLSAISTBIE BIT(14) /*!< PLLSAI Stabilization Interrupt Enable */ +#define RCU_INT_IRC32KSTBIC BIT(16) /*!< IRC32K Stabilization Interrupt Clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization Interrupt Clear */ +#define RCU_INT_IRC16MSTBIC BIT(18) /*!< IRC16M Stabilization Interrupt Clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization Interrupt Clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization Interrupt Clear */ +#define RCU_INT_PLLI2SSTBIC BIT(21) /*!< PLLI2S stabilization Interrupt Clear */ +#define RCU_INT_PLLSAISTBIC BIT(22) /*!< PLLSAI stabilization Interrupt Clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL Clock Stuck Interrupt Clear */ + +/* RCU_AHB1RST */ +#define RCU_AHB1RST_PARST BIT(0) /*!< GPIO port A reset */ +#define RCU_AHB1RST_PBRST BIT(1) /*!< GPIO port B reset */ +#define RCU_AHB1RST_PCRST BIT(2) /*!< GPIO port C reset */ +#define RCU_AHB1RST_PDRST BIT(3) /*!< GPIO port D reset */ +#define RCU_AHB1RST_PERST BIT(4) /*!< GPIO port E reset */ +#define RCU_AHB1RST_PFRST BIT(5) /*!< GPIO port F reset */ +#define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ +#define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ +#define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ +#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ +#define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ +#define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ +#define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ +#define RCU_AHB1RST_ENETRST BIT(25) /*!< ENET reset */ +#define RCU_AHB1RST_USBHSRST BIT(29) /*!< USBHS reset */ + +/* RCU_AHB2RST */ +#define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ +#define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ +#define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ + +/* RCU_AHB3RST */ +#define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_I2C2RST BIT(23) /*!< I2C2 reset */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ +#define RCU_APB1RST_UART6RST BIT(30) /*!< UART6 reset */ +#define RCU_APB1RST_UART7RST BIT(31) /*!< UART7 reset */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ +#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ +#define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ +#define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_SPI3RST BIT(13) /*!< SPI3 reset */ +#define RCU_APB2RST_SYSCFGRST BIT(14) /*!< SYSCFG reset */ +#define RCU_APB2RST_TIMER8RST BIT(16) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(17) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(18) /*!< TIMER10 reset */ +#define RCU_APB2RST_SPI4RST BIT(20) /*!< SPI4 reset */ +#define RCU_APB2RST_SPI5RST BIT(21) /*!< SPI5 reset */ +#define RCU_APB2RST_TLIRST BIT(26) /*!< TLI reset */ + +/* RCU_AHB1EN */ +#define RCU_AHB1EN_PAEN BIT(0) /*!< GPIO port A clock enable */ +#define RCU_AHB1EN_PBEN BIT(1) /*!< GPIO port B clock enable */ +#define RCU_AHB1EN_PCEN BIT(2) /*!< GPIO port C clock enable */ +#define RCU_AHB1EN_PDEN BIT(3) /*!< GPIO port D clock enable */ +#define RCU_AHB1EN_PEEN BIT(4) /*!< GPIO port E clock enable */ +#define RCU_AHB1EN_PFEN BIT(5) /*!< GPIO port F clock enable */ +#define RCU_AHB1EN_PGEN BIT(6) /*!< GPIO port G clock enable */ +#define RCU_AHB1EN_PHEN BIT(7) /*!< GPIO port H clock enable */ +#define RCU_AHB1EN_PIEN BIT(8) /*!< GPIO port I clock enable */ +#define RCU_AHB1EN_CRCEN BIT(12) /*!< CRC clock enable */ +#define RCU_AHB1EN_BKPSRAMEN BIT(18) /*!< BKPSRAM clock enable */ +#define RCU_AHB1EN_TCMSRAMEN BIT(20) /*!< TCMSRAM clock enable */ +#define RCU_AHB1EN_DMA0EN BIT(21) /*!< DMA0 clock enable */ +#define RCU_AHB1EN_DMA1EN BIT(22) /*!< DMA1 clock enable */ +#define RCU_AHB1EN_IPAEN BIT(23) /*!< IPA clock enable */ +#define RCU_AHB1EN_ENETEN BIT(25) /*!< ENET clock enable */ +#define RCU_AHB1EN_ENETTXEN BIT(26) /*!< Ethernet TX clock enable */ +#define RCU_AHB1EN_ENETRXEN BIT(27) /*!< Ethernet RX clock enable */ +#define RCU_AHB1EN_ENETPTPEN BIT(28) /*!< Ethernet PTP clock enable */ +#define RCU_AHB1EN_USBHSEN BIT(29) /*!< USBHS clock enable */ +#define RCU_AHB1EN_USBHSULPIEN BIT(30) /*!< USBHS ULPI clock enable */ + +/* RCU_AHB2EN */ +#define RCU_AHB2EN_DCIEN BIT(0) /*!< DCI clock enable */ +#define RCU_AHB2EN_TRNGEN BIT(6) /*!< TRNG clock enable */ +#define RCU_AHB2EN_USBFSEN BIT(7) /*!< USBFS clock enable */ + +/* RCU_AHB3EN */ +#define RCU_AHB3EN_EXMCEN BIT(0) /*!< EXMC clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_I2C2EN BIT(23) /*!< I2C2 clock enable */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ +#define RCU_APB1EN_UART6EN BIT(30) /*!< UART6 clock enable */ +#define RCU_APB1EN_UART7EN BIT(31) /*!< UART7 clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_TIMER0EN BIT(0) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(1) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(4) /*!< USART0 clock enable */ +#define RCU_APB2EN_USART5EN BIT(5) /*!< USART5 clock enable */ +#define RCU_APB2EN_ADC0EN BIT(8) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(9) /*!< ADC1 clock enable */ +#define RCU_APB2EN_ADC2EN BIT(10) /*!< ADC2 clock enable */ +#define RCU_APB2EN_SDIOEN BIT(11) /*!< SDIO clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_SPI3EN BIT(13) /*!< SPI3 clock enable */ +#define RCU_APB2EN_SYSCFGEN BIT(14) /*!< SYSCFG clock enable */ +#define RCU_APB2EN_TIMER8EN BIT(16) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(17) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(18) /*!< TIMER10 clock enable */ +#define RCU_APB2EN_SPI4EN BIT(20) /*!< SPI4 clock enable */ +#define RCU_APB2EN_SPI5EN BIT(21) /*!< SPI5 clock enable */ +#define RCU_APB2EN_TLIEN BIT(26) /*!< TLI clock enable */ + +/* RCU_AHB1SPEN */ +#define RCU_AHB1SPEN_PASPEN BIT(0) /*!< GPIO port A clock enable when sleep mode */ +#define RCU_AHB1SPEN_PBSPEN BIT(1) /*!< GPIO port B clock enable when sleep mode */ +#define RCU_AHB1SPEN_PCSPEN BIT(2) /*!< GPIO port C clock enable when sleep mode */ +#define RCU_AHB1SPEN_PDSPEN BIT(3) /*!< GPIO port D clock enable when sleep mode */ +#define RCU_AHB1SPEN_PESPEN BIT(4) /*!< GPIO port E clock enable when sleep mode */ +#define RCU_AHB1SPEN_PFSPEN BIT(5) /*!< GPIO port F clock enable when sleep mode */ +#define RCU_AHB1SPEN_PGSPEN BIT(6) /*!< GPIO port G clock enable when sleep mode */ +#define RCU_AHB1SPEN_PHSPEN BIT(7) /*!< GPIO port H clock enable when sleep mode */ +#define RCU_AHB1SPEN_PISPEN BIT(8) /*!< GPIO port I clock enable when sleep mode */ +#define RCU_AHB1SPEN_CRCSPEN BIT(12) /*!< CRC clock enable when sleep mode */ +#define RCU_AHB1SPEN_FMCSPEN BIT(15) /*!< FMC clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM0SPEN BIT(16) /*!< SRAM0 clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM1SPEN BIT(17) /*!< SRAM1 clock enable when sleep mode */ +#define RCU_AHB1SPEN_BKPSRAMSPEN BIT(18) /*!< BKPSRAM clock enable when sleep mode */ +#define RCU_AHB1SPEN_SRAM2SPEN BIT(19) /*!< SRAM2 clock enable when sleep mode */ +#define RCU_AHB1SPEN_DMA0SPEN BIT(21) /*!< DMA0 clock when sleep mode enable */ +#define RCU_AHB1SPEN_DMA1SPEN BIT(22) /*!< DMA1 clock when sleep mode enable */ +#define RCU_AHB1SPEN_IPASPEN BIT(23) /*!< IPA clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETSPEN BIT(25) /*!< ENET clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETTXSPEN BIT(26) /*!< Ethernet TX clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETRXSPEN BIT(27) /*!< Ethernet RX clock enable when sleep mode */ +#define RCU_AHB1SPEN_ENETPTPSPEN BIT(28) /*!< Ethernet PTP clock enable when sleep mode */ +#define RCU_AHB1SPEN_USBHSSPEN BIT(29) /*!< USBHS clock enable when sleep mode */ +#define RCU_AHB1SPEN_USBHSULPISPEN BIT(30) /*!< USBHS ULPI clock enable when sleep mode */ + +/* RCU_AHB2SPEN */ +#define RCU_AHB2SPEN_DCISPEN BIT(0) /*!< DCI clock enable when sleep mode */ +#define RCU_AHB2SPEN_TRNGSPEN BIT(6) /*!< TRNG clock enable when sleep mode */ +#define RCU_AHB2SPEN_USBFSSPEN BIT(7) /*!< USBFS clock enable when sleep mode */ + +/* RCU_AHB3SPEN */ +#define RCU_AHB3SPEN_EXMCSPEN BIT(0) /*!< EXMC clock enable when sleep mode */ + +/* RCU_APB1SPEN */ +#define RCU_APB1SPEN_TIMER1SPEN BIT(0) /*!< TIMER1 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER2SPEN BIT(1) /*!< TIMER2 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER3SPEN BIT(2) /*!< TIMER3 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER4SPEN BIT(3) /*!< TIMER4 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER5SPEN BIT(4) /*!< TIMER5 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER6SPEN BIT(5) /*!< TIMER6 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER11SPEN BIT(6) /*!< TIMER11 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER12SPEN BIT(7) /*!< TIMER12 clock enable when sleep mode */ +#define RCU_APB1SPEN_TIMER13SPEN BIT(8) /*!< TIMER13 clock enable when sleep mode */ +#define RCU_APB1SPEN_WWDGTSPEN BIT(11) /*!< WWDGT clock enable when sleep mode */ +#define RCU_APB1SPEN_SPI1SPEN BIT(14) /*!< SPI1 clock enable when sleep mode */ +#define RCU_APB1SPEN_SPI2SPEN BIT(15) /*!< SPI2 clock enable when sleep mode */ +#define RCU_APB1SPEN_USART1SPEN BIT(17) /*!< USART1 clock enable when sleep mode*/ +#define RCU_APB1SPEN_USART2SPEN BIT(18) /*!< USART2 clock enable when sleep mode*/ +#define RCU_APB1SPEN_UART3SPEN BIT(19) /*!< UART3 clock enable when sleep mode*/ +#define RCU_APB1SPEN_UART4SPEN BIT(20) /*!< UART4 clock enable when sleep mode */ +#define RCU_APB1SPEN_I2C0SPEN BIT(21) /*!< I2C0 clock enable when sleep mode */ +#define RCU_APB1SPEN_I2C1SPEN BIT(22) /*!< I2C1 clock enable when sleep mode*/ +#define RCU_APB1SPEN_I2C2SPEN BIT(23) /*!< I2C2 clock enable when sleep mode */ +#define RCU_APB1SPEN_CAN0SPEN BIT(25) /*!< CAN0 clock enable when sleep mode*/ +#define RCU_APB1SPEN_CAN1SPEN BIT(26) /*!< CAN1 clock enable when sleep mode */ +#define RCU_APB1SPEN_PMUSPEN BIT(28) /*!< PMU clock enable when sleep mode */ +#define RCU_APB1SPEN_DACSPEN BIT(29) /*!< DAC clock enable when sleep mode */ +#define RCU_APB1SPEN_UART6SPEN BIT(30) /*!< UART6 clock enable when sleep mode */ +#define RCU_APB1SPEN_UART7SPEN BIT(31) /*!< UART7 clock enable when sleep mode */ + +/* RCU_APB2SPEN */ +#define RCU_APB2SPEN_TIMER0SPEN BIT(0) /*!< TIMER0 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER7SPEN BIT(1) /*!< TIMER7 clock enable when sleep mode */ +#define RCU_APB2SPEN_USART0SPEN BIT(4) /*!< USART0 clock enable when sleep mode */ +#define RCU_APB2SPEN_USART5SPEN BIT(5) /*!< USART5 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC0SPEN BIT(8) /*!< ADC0 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC1SPEN BIT(9) /*!< ADC1 clock enable when sleep mode */ +#define RCU_APB2SPEN_ADC2SPEN BIT(10) /*!< ADC2 clock enable when sleep mode */ +#define RCU_APB2SPEN_SDIOSPEN BIT(11) /*!< SDIO clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI0SPEN BIT(12) /*!< SPI0 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI3SPEN BIT(13) /*!< SPI3 clock enable when sleep mode */ +#define RCU_APB2SPEN_SYSCFGSPEN BIT(14) /*!< SYSCFG clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER8SPEN BIT(16) /*!< TIMER8 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER9SPEN BIT(17) /*!< TIMER9 clock enable when sleep mode */ +#define RCU_APB2SPEN_TIMER10SPEN BIT(18) /*!< TIMER10 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI4SPEN BIT(20) /*!< SPI4 clock enable when sleep mode */ +#define RCU_APB2SPEN_SPI5SPEN BIT(21) /*!< SPI5 clock enable when sleep mode */ +#define RCU_APB2SPEN_TLISPEN BIT(26) /*!< TLI clock enable when sleep mode*/ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BIT(3) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC32KEN BIT(0) /*!< IRC32K enable */ +#define RCU_RSTSCK_IRC32KSTB BIT(1) /*!< IRC32K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_BORRSTF BIT(25) /*!< BOR reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_PLLSSCTL */ +#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria + must be met: MODSTEP*MODCNT=215-1 */ +#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria + must be met: MODSTEP*MODCNT=215-1 */ +#define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ +#define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ + +/* RCU_PLLI2S */ +#define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ +#define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ + +/* RCU_PLLSAI */ +#define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ +#define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PLLSAIRDIV BITS(16,17) /*!< the divider factor from PLLSAIR clock */ +#define RCU_CFG1_TIMERSEL BIT(24) /*!< TIMER clock selection */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ +#define RCU_ADDCTL_PLL48MSEL BIT(1) /*!< PLL48M clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ +#define RCU_ADDAPB1RST_IREFRST BIT(31) /*!< IREF reset */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ +#define RCU_ADDAPB1EN_IREFEN BIT(31) /*!< IREF interface clock enable */ + +/* RCU_ADDAPB1SPEN */ +#define RCU_ADDAPB1SPEN_CTCSPEN BIT(27) /*!< CTC clock enable during sleep mode */ +#define RCU_ADDAPB1SPEN_IREFSPEN BIT(31) /*!< IREF interface clock enable during sleep mode */ + +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) /*!< RCU_DSV key register */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +/* define the voltage key unlock value */ +#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) + +/* register offset */ +/* peripherals enable */ +#define AHB1EN_REG_OFFSET 0x30U /*!< AHB1 enable register offset */ +#define AHB2EN_REG_OFFSET 0x34U /*!< AHB2 enable register offset */ +#define AHB3EN_REG_OFFSET 0x38U /*!< AHB3 enable register offset */ +#define APB1EN_REG_OFFSET 0x40U /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x44U /*!< APB2 enable register offset */ +#define AHB1SPEN_REG_OFFSET 0x50U /*!< AHB1 sleep mode enable register offset */ +#define AHB2SPEN_REG_OFFSET 0x54U /*!< AHB2 sleep mode enable register offset */ +#define AHB3SPEN_REG_OFFSET 0x58U /*!< AHB3 sleep mode enable register offset */ +#define APB1SPEN_REG_OFFSET 0x60U /*!< APB1 sleep mode enable register offset */ +#define APB2SPEN_REG_OFFSET 0x64U /*!< APB2 sleep mode enable register offset */ +#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ +#define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ + +/* peripherals reset */ +#define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ +#define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ +#define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ +#define APB1RST_REG_OFFSET 0x20U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x24U /*!< APB2 reset register offset */ +#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ +#define RSTSCK_REG_OFFSET 0x74U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x70U /*!< backup domain control register offset */ +#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x0CU /*!< clock interrupt register offset */ +#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ + +/* configuration register */ +#define PLL_REG_OFFSET 0x04U /*!< PLL register offset */ +#define CFG0_REG_OFFSET 0x08U /*!< clock configuration register 0 offset */ +#define PLLSSCTL_REG_OFFSET 0x80U /*!< PLL clock spread spectrum control register offset */ +#define PLLI2S_REG_OFFSET 0x84U /*!< PLLI2S register offset */ +#define PLLSAI_REG_OFFSET 0x88U /*!< PLLSAI register offset */ +#define CFG1_REG_OFFSET 0x8CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 0U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 1U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 2U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 3U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 4U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 5U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 6U), /*!< GPIOG clock */ + RCU_GPIOH = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 7U), /*!< GPIOH clock */ + RCU_GPIOI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 8U), /*!< GPIOI clock */ + RCU_CRC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 12U), /*!< CRC clock */ + RCU_BKPSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ + RCU_TCMSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 20U), /*!< TCMSRAM clock */ + RCU_DMA0 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 21U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 22U), /*!< DMA1 clock */ + RCU_IPA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 23U), /*!< IPA clock */ + RCU_ENET = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 25U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 26U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 27U), /*!< ENETRX clock */ + RCU_ENETPTP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 28U), /*!< ENETPTP clock */ + RCU_USBHS = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 29U), /*!< USBHS clock */ + RCU_USBHSULPI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ + /* AHB2 peripherals */ + RCU_DCI = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 0U), /*!< DCI clock */ + RCU_TRNG = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 6U), /*!< TRNG clock */ + RCU_USBFS = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 7U), /*!< USBFS clock */ + /* AHB3 peripherals */ + RCU_EXMC = RCU_REGIDX_BIT(AHB3EN_REG_OFFSET, 0U), /*!< EXMC clock */ + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_UART6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 30U), /*!< UART6 clock */ + RCU_UART7 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 31U), /*!< UART7 clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + /* APB2 peripherals */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< TIMER0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< USART0 clock */ + RCU_USART5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< USART5 clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC1 clock */ + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC2 clock */ + RCU_SDIO = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< SDIO clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_SPI3 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< SPI3 clock */ + RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< SYSCFG clock */ + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 16U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 17U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 18U), /*!< TIMER10 clock */ + RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ + RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ + RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ + /* APB1 additional peripherals */ + RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ + RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 0U), /*!< GPIOA clock */ + RCU_GPIOB_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 1U), /*!< GPIOB clock */ + RCU_GPIOC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 2U), /*!< GPIOC clock */ + RCU_GPIOD_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 3U), /*!< GPIOD clock */ + RCU_GPIOE_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 4U), /*!< GPIOE clock */ + RCU_GPIOF_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 5U), /*!< GPIOF clock */ + RCU_GPIOG_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 6U), /*!< GPIOG clock */ + RCU_GPIOH_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 7U), /*!< GPIOH clock */ + RCU_GPIOI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 8U), /*!< GPIOI clock */ + RCU_CRC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 12U), /*!< CRC clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 15U), /*!< FMC clock */ + RCU_SRAM0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 16U), /*!< SRAM0 clock */ + RCU_SRAM1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 17U), /*!< SRAM1 clock */ + RCU_BKPSRAM_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ + RCU_SRAM2_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 19U), /*!< SRAM2 clock */ + RCU_DMA0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 21U), /*!< DMA0 clock */ + RCU_DMA1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 22U), /*!< DMA1 clock */ + RCU_IPA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 23U), /*!< IPA clock */ + RCU_ENET_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 25U), /*!< ENET clock */ + RCU_ENETTX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 26U), /*!< ENETTX clock */ + RCU_ENETRX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 27U), /*!< ENETRX clock */ + RCU_ENETPTP_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 28U), /*!< ENETPTP clock */ + RCU_USBHS_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 29U), /*!< USBHS clock */ + RCU_USBHSULPI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ + /* AHB2 peripherals */ + RCU_DCI_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 0U), /*!< DCI clock */ + RCU_TRNG_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 6U), /*!< TRNG clock */ + RCU_USBFS_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 7U), /*!< USBFS clock */ + /* AHB3 peripherals */ + RCU_EXMC_SLP = RCU_REGIDX_BIT(AHB3SPEN_REG_OFFSET, 0U), /*!< EXMC clock */ + /* APB1 peripherals */ + RCU_TIMER1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_UART6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 30U), /*!< UART6 clock */ + RCU_UART7_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 31U), /*!< UART7 clock */ + /* APB2 peripherals */ + RCU_TIMER0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 0U), /*!< TIMER0 clock */ + RCU_TIMER7_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 1U), /*!< TIMER7 clock */ + RCU_USART0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 4U), /*!< USART0 clock */ + RCU_USART5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 5U), /*!< USART5 clock */ + RCU_ADC0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 8U), /*!< ADC0 clock */ + RCU_ADC1_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 9U), /*!< ADC1 clock */ + RCU_ADC2_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 10U), /*!< ADC2 clock */ + RCU_SDIO_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 11U), /*!< SDIO clock */ + RCU_SPI0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_SPI3_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 13U), /*!< SPI3 clock */ + RCU_SYSCFG_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 14U), /*!< SYSCFG clock */ + RCU_TIMER8_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 16U), /*!< TIMER8 clock */ + RCU_TIMER9_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 17U), /*!< TIMER9 clock */ + RCU_TIMER10_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 18U), /*!< TIMER10 clock */ + RCU_SPI4_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 20U), /*!< SPI4 clock */ + RCU_SPI5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 21U), /*!< SPI5 clock */ + RCU_TLI_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 26U), /*!< TLI clock */ + /* APB1 additional peripherals */ + RCU_CTC_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 27U), /*!< CTC clock */ + RCU_IREF_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 31U), /*!< IREF clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB1 peripherals */ + RCU_GPIOARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 0U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 1U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 2U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 3U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 4U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 5U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 6U), /*!< GPIOG clock reset */ + RCU_GPIOHRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 7U), /*!< GPIOH clock reset */ + RCU_GPIOIRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 8U), /*!< GPIOI clock reset */ + RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ + RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ + RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ + RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ + RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ + /* AHB2 peripherals */ + RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ + RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 6U), /*!< TRNG clock reset */ + RCU_USBFSRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 7U), /*!< USBFS clock reset */ + /* AHB3 peripherals */ + RCU_EXMCRST = RCU_REGIDX_BIT(AHB3RST_REG_OFFSET, 0U), /*!< EXMC clock reset */ + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ + RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + RCU_UART6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 30U), /*!< UART6 clock reset */ + RCU_UART7RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 31U), /*!< UART7 clock reset */ + /* APB2 peripherals */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< TIMER0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< USART0 clock reset */ + RCU_USART5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< USART5 clock reset */ + RCU_ADCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< ADCs all clock reset */ + RCU_SDIORST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< SDIO clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_SPI3RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< SPI3 clock reset */ + RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< SYSCFG clock reset */ + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 16U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 17U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 18U), /*!< TIMER10 clock reset */ + RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ + RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ + RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ + /* APB1 additional peripherals */ + RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ + RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + /* clock stabilization flags */ + RCU_FLAG_IRC16MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC16M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLLI2S stabilization flags */ + RCU_FLAG_PLLSAISTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLLSAI stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC32KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC32K stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ + /* reset source flags */ + RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< BOR reset flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< External PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< Software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< Low-power reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ + RCU_INT_FLAG_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLLSAI stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC32KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC32K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC16MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC16M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLI2SSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLLI2S stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSAISTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLLSAI stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ + RCU_INT_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLLSAI stabilization interrupt */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ +}rcu_int_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC16M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC16M */ + RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ + RCU_IRC32K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC32K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ + RCU_PLLI2S_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLLI2S */ + RCU_PLLSAI_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLLSAI */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +}rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC16M CFG0_SCS(0) /*!< system clock source select IRC16M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLLP CFG0_SCS(2) /*!< system clock source select PLLP */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC16M CFG0_SCSS(0) /*!< system clock source select IRC16M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLLP CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* RTC clock divider factor from HXTAL clock */ +#define CFG0_RTCDIV(regval) (BITS(16,20) & ((uint32_t)(regval) << 16)) +#define RCU_RTC_HXTAL_NONE CFG0_RTCDIV(0) /*!< no clock for RTC */ +#define RCU_RTC_HXTAL_DIV2 CFG0_RTCDIV(2) /*!< RTCDIV clock select CK_HXTAL/2 */ +#define RCU_RTC_HXTAL_DIV3 CFG0_RTCDIV(3) /*!< RTCDIV clock select CK_HXTAL/3 */ +#define RCU_RTC_HXTAL_DIV4 CFG0_RTCDIV(4) /*!< RTCDIV clock select CK_HXTAL/4 */ +#define RCU_RTC_HXTAL_DIV5 CFG0_RTCDIV(5) /*!< RTCDIV clock select CK_HXTAL/5 */ +#define RCU_RTC_HXTAL_DIV6 CFG0_RTCDIV(6) /*!< RTCDIV clock select CK_HXTAL/6 */ +#define RCU_RTC_HXTAL_DIV7 CFG0_RTCDIV(7) /*!< RTCDIV clock select CK_HXTAL/7 */ +#define RCU_RTC_HXTAL_DIV8 CFG0_RTCDIV(8) /*!< RTCDIV clock select CK_HXTAL/8 */ +#define RCU_RTC_HXTAL_DIV9 CFG0_RTCDIV(9) /*!< RTCDIV clock select CK_HXTAL/9 */ +#define RCU_RTC_HXTAL_DIV10 CFG0_RTCDIV(10) /*!< RTCDIV clock select CK_HXTAL/10 */ +#define RCU_RTC_HXTAL_DIV11 CFG0_RTCDIV(11) /*!< RTCDIV clock select CK_HXTAL/11 */ +#define RCU_RTC_HXTAL_DIV12 CFG0_RTCDIV(12) /*!< RTCDIV clock select CK_HXTAL/12 */ +#define RCU_RTC_HXTAL_DIV13 CFG0_RTCDIV(13) /*!< RTCDIV clock select CK_HXTAL/13 */ +#define RCU_RTC_HXTAL_DIV14 CFG0_RTCDIV(14) /*!< RTCDIV clock select CK_HXTAL/14 */ +#define RCU_RTC_HXTAL_DIV15 CFG0_RTCDIV(15) /*!< RTCDIV clock select CK_HXTAL/15 */ +#define RCU_RTC_HXTAL_DIV16 CFG0_RTCDIV(16) /*!< RTCDIV clock select CK_HXTAL/16 */ +#define RCU_RTC_HXTAL_DIV17 CFG0_RTCDIV(17) /*!< RTCDIV clock select CK_HXTAL/17 */ +#define RCU_RTC_HXTAL_DIV18 CFG0_RTCDIV(18) /*!< RTCDIV clock select CK_HXTAL/18 */ +#define RCU_RTC_HXTAL_DIV19 CFG0_RTCDIV(19) /*!< RTCDIV clock select CK_HXTAL/19 */ +#define RCU_RTC_HXTAL_DIV20 CFG0_RTCDIV(20) /*!< RTCDIV clock select CK_HXTAL/20 */ +#define RCU_RTC_HXTAL_DIV21 CFG0_RTCDIV(21) /*!< RTCDIV clock select CK_HXTAL/21 */ +#define RCU_RTC_HXTAL_DIV22 CFG0_RTCDIV(22) /*!< RTCDIV clock select CK_HXTAL/22 */ +#define RCU_RTC_HXTAL_DIV23 CFG0_RTCDIV(23) /*!< RTCDIV clock select CK_HXTAL/23 */ +#define RCU_RTC_HXTAL_DIV24 CFG0_RTCDIV(24) /*!< RTCDIV clock select CK_HXTAL/24 */ +#define RCU_RTC_HXTAL_DIV25 CFG0_RTCDIV(25) /*!< RTCDIV clock select CK_HXTAL/25 */ +#define RCU_RTC_HXTAL_DIV26 CFG0_RTCDIV(26) /*!< RTCDIV clock select CK_HXTAL/26 */ +#define RCU_RTC_HXTAL_DIV27 CFG0_RTCDIV(27) /*!< RTCDIV clock select CK_HXTAL/27 */ +#define RCU_RTC_HXTAL_DIV28 CFG0_RTCDIV(28) /*!< RTCDIV clock select CK_HXTAL/28 */ +#define RCU_RTC_HXTAL_DIV29 CFG0_RTCDIV(29) /*!< RTCDIV clock select CK_HXTAL/29 */ +#define RCU_RTC_HXTAL_DIV30 CFG0_RTCDIV(30) /*!< RTCDIV clock select CK_HXTAL/30 */ +#define RCU_RTC_HXTAL_DIV31 CFG0_RTCDIV(31) /*!< RTCDIV clock select CK_HXTAL/31 */ + +/* CKOUT0 Clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define RCU_CKOUT0SRC_IRC16M CFG0_CKOUT0SEL(0) /*!< internal 16M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_LXTAL CFG0_CKOUT0SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_PLLP CFG0_CKOUT0SEL(3) /*!< CK_PLLP clock selected */ + +/* I2S Clock source selection */ +#define RCU_I2SSRC_PLLI2S ((uint32_t)0x00000000U) /*!< PLLI2S output clock selected as I2S source clock */ +#define RCU_I2SSRC_I2S_CKIN RCU_CFG0_I2SSEL /*!< external I2S_CKIN pin selected as I2S source clock */ + +/* The CK_OUT0 divider */ +#define CFG0_CKOUT0DIV(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0_DIV1 CFG0_CKOUT0DIV(0) /*!< CK_OUT0 is divided by 1 */ +#define RCU_CKOUT0_DIV2 CFG0_CKOUT0DIV(4) /*!< CK_OUT0 is divided by 2 */ +#define RCU_CKOUT0_DIV3 CFG0_CKOUT0DIV(5) /*!< CK_OUT0 is divided by 3 */ +#define RCU_CKOUT0_DIV4 CFG0_CKOUT0DIV(6) /*!< CK_OUT0 is divided by 4 */ +#define RCU_CKOUT0_DIV5 CFG0_CKOUT0DIV(7) /*!< CK_OUT0 is divided by 5 */ + +/* The CK_OUT1 divider */ +#define CFG0_CKOUT1DIV(regval) (BITS(27,29) & ((uint32_t)(regval) << 27)) +#define RCU_CKOUT1_DIV1 CFG0_CKOUT1DIV(0) /*!< CK_OUT1 is divided by 1 */ +#define RCU_CKOUT1_DIV2 CFG0_CKOUT1DIV(4) /*!< CK_OUT1 is divided by 2 */ +#define RCU_CKOUT1_DIV3 CFG0_CKOUT1DIV(5) /*!< CK_OUT1 is divided by 3 */ +#define RCU_CKOUT1_DIV4 CFG0_CKOUT1DIV(6) /*!< CK_OUT1 is divided by 4 */ +#define RCU_CKOUT1_DIV5 CFG0_CKOUT1DIV(7) /*!< CK_OUT1 is divided by 5 */ + +/* CKOUT1 Clock source selection */ +#define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) +#define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ +#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ +#define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ + +/* RCU_CFG1 register bit define */ +/* the divider factor from PLLI2SQ clock */ +#define CFG1_PLLI2SQDIV(regval) (BITS(0,4) & ((uint32_t)(regval) << 0)) +#define RCU_PLLI2SQ_DIV1 CFG1_PLLI2SQDIV(0) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/1 */ +#define RCU_PLLI2SQ_DIV2 CFG1_PLLI2SQDIV(1) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/2 */ +#define RCU_PLLI2SQ_DIV3 CFG1_PLLI2SQDIV(2) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/3 */ +#define RCU_PLLI2SQ_DIV4 CFG1_PLLI2SQDIV(3) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/4 */ +#define RCU_PLLI2SQ_DIV5 CFG1_PLLI2SQDIV(4) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/5 */ +#define RCU_PLLI2SQ_DIV6 CFG1_PLLI2SQDIV(5) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/6 */ +#define RCU_PLLI2SQ_DIV7 CFG1_PLLI2SQDIV(6) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/7 */ +#define RCU_PLLI2SQ_DIV8 CFG1_PLLI2SQDIV(7) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/8 */ +#define RCU_PLLI2SQ_DIV9 CFG1_PLLI2SQDIV(8) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/9 */ +#define RCU_PLLI2SQ_DIV10 CFG1_PLLI2SQDIV(9) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/10 */ +#define RCU_PLLI2SQ_DIV11 CFG1_PLLI2SQDIV(10) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/11 */ +#define RCU_PLLI2SQ_DIV12 CFG1_PLLI2SQDIV(11) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/12 */ +#define RCU_PLLI2SQ_DIV13 CFG1_PLLI2SQDIV(12) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/13 */ +#define RCU_PLLI2SQ_DIV14 CFG1_PLLI2SQDIV(13) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/14 */ +#define RCU_PLLI2SQ_DIV15 CFG1_PLLI2SQDIV(14) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/15 */ +#define RCU_PLLI2SQ_DIV16 CFG1_PLLI2SQDIV(15) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/16 */ +#define RCU_PLLI2SQ_DIV17 CFG1_PLLI2SQDIV(16) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/17 */ +#define RCU_PLLI2SQ_DIV18 CFG1_PLLI2SQDIV(17) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/18 */ +#define RCU_PLLI2SQ_DIV19 CFG1_PLLI2SQDIV(18) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/19 */ +#define RCU_PLLI2SQ_DIV20 CFG1_PLLI2SQDIV(19) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/20 */ +#define RCU_PLLI2SQ_DIV21 CFG1_PLLI2SQDIV(20) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/21 */ +#define RCU_PLLI2SQ_DIV22 CFG1_PLLI2SQDIV(21) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/22 */ +#define RCU_PLLI2SQ_DIV23 CFG1_PLLI2SQDIV(22) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/23 */ +#define RCU_PLLI2SQ_DIV24 CFG1_PLLI2SQDIV(23) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/24 */ +#define RCU_PLLI2SQ_DIV25 CFG1_PLLI2SQDIV(24) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/25 */ +#define RCU_PLLI2SQ_DIV26 CFG1_PLLI2SQDIV(25) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/26 */ +#define RCU_PLLI2SQ_DIV27 CFG1_PLLI2SQDIV(26) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/27 */ +#define RCU_PLLI2SQ_DIV28 CFG1_PLLI2SQDIV(27) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/28 */ +#define RCU_PLLI2SQ_DIV29 CFG1_PLLI2SQDIV(28) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/29 */ +#define RCU_PLLI2SQ_DIV30 CFG1_PLLI2SQDIV(29) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/30 */ +#define RCU_PLLI2SQ_DIV31 CFG1_PLLI2SQDIV(30) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/31 */ +#define RCU_PLLI2SQ_DIV32 CFG1_PLLI2SQDIV(31) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/32 */ + +/* the divider factor from PLLSAIR clock */ +#define CFG1_PLLSAIRDIV(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define RCU_PLLSAIR_DIV2 CFG1_PLLSAIRDIV(0) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/2 */ +#define RCU_PLLSAIR_DIV4 CFG1_PLLSAIRDIV(1) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/4 */ +#define RCU_PLLSAIR_DIV8 CFG1_PLLSAIRDIV(2) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/8 */ +#define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ + +/* TIMER clock selection */ +#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ +#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ + +/* RCU_PLLSSCTL register bit define */ +/* PLL spread spectrum modulation type select */ +#define RCU_SS_TYPE_CENTER ((uint32_t)0x00000000U) /*!< center type is selected */ +#define RCU_SS_TYPE_DOWN RCU_PLLSSCTL_SS_TYPE /*!< down type is selected */ + +/* RCU_PLL register bit define */ +/* The PLL VCO source clock prescaler */ +#define RCU_PLLPSC_DIV_MIN ((uint32_t)2U) /*!< PLLPSC_DIV min value */ +#define RCU_PLLPSC_DIV_MAX ((uint32_t)63U) /*!< PLLPSC_DIV max value */ + +/* The PLL VCO clock multi factor */ +#define RCU_PLLN_MUL_MIN ((uint32_t)64U) /*!< PLLN_MUL min value */ +#define RCU_PLLN_MUL_MAX ((uint32_t)500U) /*!< PLLN_MUL max value */ +#define RCU_SS_MODULATION_CENTER_INC ((uint32_t)5U) /*!< minimum factor of PLLN in center mode */ +#define RCU_SS_MODULATION_DOWN_INC ((uint32_t)7U) /*!< minimum factor of PLLN in down mode */ + +/* The PLLP output frequency division factor from PLL VCO clock */ +#define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ +#define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ + +/* PLL Clock Source Selection */ +#define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ +#define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ + +/* The PLL Q output frequency division factor from PLL VCO clock */ +#define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ +#define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ + +#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) +#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) +#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) + +/* RCU_BDCTL register bit define */ +/* LXTAL drive capability */ +#define RCU_LXTALDRI_LOWER_DRIVE ((uint32_t)0x00000000) /*!< LXTAL drive capability is selected lower */ +#define RCU_LXTALDRI_HIGHER_DRIVE RCU_BDCTL_LXTALDRI /*!< LXTAL drive capability is selected higher */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC32K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC32K */ +#define RCU_RTCSRC_HXTAL_DIV_RTCDIV BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/RTCDIV */ + +/* RCU_PLLI2S register bit define */ +/* The PLLI2S VCO clock multi factor */ +#define RCU_PLLI2SN_MUL_MIN 50U +#define RCU_PLLI2SN_MUL_MAX 500U + +/* The PLLI2S Q output frequency division factor from PLLI2S VCO clock */ +#define RCU_PLLI2SQ_DIV_MIN 2U +#define RCU_PLLI2SQ_DIV_MAX 15U + +/* The PLLI2S R output frequency division factor from PLLI2S VCO clock */ +#define RCU_PLLI2SR_DIV_MIN 2U +#define RCU_PLLI2SR_DIV_MAX 7U + +/* RCU_PLLSAI register bit define */ +/* The PLLSAI VCO clock multi factor */ +#define RCU_PLLSAIN_MUL_MIN 50U +#define RCU_PLLSAIN_MUL_MAX 500U + +/* The PLLSAI P output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIP_DIV_MIN 2U +#define RCU_PLLSAIP_DIV_MAX 8U + +/* The PLLSAI Q output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIQ_DIV_MIN 2U +#define RCU_PLLSAIQ_DIV_MAX 15U + +/* The PLLSAI R output frequency division factor from PLLSAI VCO clock */ +#define RCU_PLLSAIR_DIV_MIN 2U +#define RCU_PLLSAIR_DIV_MAX 7U + +#define CHECK_PLLI2S_PSC_VALID(val) (((val) >= RCU_PLLI2SPSC_DIV_MIN)&&((val) <= RCU_PLLI2SPSC_DIV_MAX)) +#define CHECK_PLLI2S_N_VALID(val) (((val) >= RCU_PLLI2SN_MUL_MIN)&&((val) <= RCU_PLLI2SN_MUL_MAX)) +#define CHECK_PLLI2S_Q_VALID(val) (((val) >= RCU_PLLI2SQ_DIV_MIN)&&((val) <= RCU_PLLI2SQ_DIV_MAX)) +#define CHECK_PLLI2S_R_VALID(val) (((val) >= RCU_PLLI2SR_DIV_MIN)&&((val) <= RCU_PLLI2SR_DIV_MAX)) + +#define CHECK_PLLSAI_N_VALID(val) (((val) >= (RCU_PLLSAIN_MUL_MIN))&&((val) <= RCU_PLLSAIN_MUL_MAX)) +#define CHECK_PLLSAI_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLLSAI_Q_VALID(val) (((val) >= RCU_PLLSAIQ_DIV_MIN)&&((val) <= RCU_PLLSAIQ_DIV_MAX)) +#define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) + +/* RCU_ADDCTL register bit define */ +/* 48MHz clock selection */ +#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ + +/* PLL48M clock selection */ +#define RCU_PLL48MSRC_PLLQ ((uint32_t)0x00000000U) /*!< PLL48M source clock select PLLQ */ +#define RCU_PLL48MSRC_PLLSAIP RCU_ADDCTL_PLL48MSEL /*!< PLL48M source clock select PLLSAIP */ + +/* Deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/ + + +/* function declarations */ +/* peripherals clock configure functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP */ +void rcu_bkp_reset_enable(void); +/* disable the BKP reset */ +void rcu_bkp_reset_disable(void); + +/* system and peripherals clock source, system reset configure functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div); +/* configure the CK_OUT1 clock source and divider */ +void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); +/* configure the PLL clock source selection and PLL multiply factor */ +ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); +/* configure the PLLI2S clock */ +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); +/* configure the PLLSAI clock */ +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ +void rcu_rtc_div_config(uint32_t rtc_div); +/* configure the I2S clock source selection */ +void rcu_i2s_clock_config(uint32_t i2s_clock_source); +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); +/* configure the PLL48M clock selection */ +void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); +/* configure the TIMER clock prescaler selection */ +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); +/* configure the TLI clock division selection */ +void rcu_tli_clock_div_config(uint32_t pllsai_r_div); + +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* set the IRC16M adjust value */ +void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); +/* configure the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); +/* enable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_enable(void); +/* disable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_disable(void); + +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +/* flag & interrupt functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum interrupt); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum interrupt); + +#endif /* GD32F4XX_RCU_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h new file mode 100644 index 0000000..283abc6 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_rtc.h @@ -0,0 +1,641 @@ +/*! + \file gd32f4xx_rtc.c + \brief definitions for the RTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_RTC_H +#define GD32F4XX_RTC_H + +#include "gd32f4xx.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */ +#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */ +#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */ +#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */ +#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */ +#define RTC_WUT REG32((RTC) + 0x14U) /*!< RTC wakeup timer regiser */ +#define RTC_COSC REG32((RTC) + 0x18U) /*!< RTC coarse calibration register */ +#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */ +#define RTC_ALRM1TD REG32((RTC) + 0x20U) /*!< RTC alarm 1 time and date register */ +#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */ +#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */ +#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */ +#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */ +#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */ +#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */ +#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */ +#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */ +#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */ +#define RTC_ALRM1SS REG32((RTC) + 0x48U) /*!< RTC alarm 1 sub second register */ +#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */ +#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */ +#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */ +#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */ +#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */ +#define RTC_BKP5 REG32((RTC) + 0x64U) /*!< RTC backup register */ +#define RTC_BKP6 REG32((RTC) + 0x68U) /*!< RTC backup register */ +#define RTC_BKP7 REG32((RTC) + 0x6CU) /*!< RTC backup register */ +#define RTC_BKP8 REG32((RTC) + 0x70U) /*!< RTC backup register */ +#define RTC_BKP9 REG32((RTC) + 0x74U) /*!< RTC backup register */ +#define RTC_BKP10 REG32((RTC) + 0x78U) /*!< RTC backup register */ +#define RTC_BKP11 REG32((RTC) + 0x7CU) /*!< RTC backup register */ +#define RTC_BKP12 REG32((RTC) + 0x80U) /*!< RTC backup register */ +#define RTC_BKP13 REG32((RTC) + 0x84U) /*!< RTC backup register */ +#define RTC_BKP14 REG32((RTC) + 0x88U) /*!< RTC backup register */ +#define RTC_BKP15 REG32((RTC) + 0x8CU) /*!< RTC backup register */ +#define RTC_BKP16 REG32((RTC) + 0x90U) /*!< RTC backup register */ +#define RTC_BKP17 REG32((RTC) + 0x94U) /*!< RTC backup register */ +#define RTC_BKP18 REG32((RTC) + 0x98U) /*!< RTC backup register */ +#define RTC_BKP19 REG32((RTC) + 0x9CU) /*!< RTC backup register */ + +/* bits definitions */ +/* RTC_TIME */ +#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DATE */ +#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ +#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ +#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ + +/* RTC_CTL */ +#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */ +#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ +#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ +#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ +#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ +#define RTC_CTL_CCEN BIT(7) /*!< coarse calibration function enable */ +#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */ +#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */ +#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */ +#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ +#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */ +#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */ +#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */ +#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ +#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ +#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ +#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ +#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ +#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ +#define RTC_CTL_OS BITS(21,22) /*!< output selection */ +#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ + +/* RTC_STAT */ +#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */ +#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */ +#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */ +#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ +#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ +#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ +#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ +#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ +#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */ +#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */ +#define RTC_STAT_WTF BIT(10) /*!< wakeup timer occurs flag */ +#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ +#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ +#define RTC_STAT_TP0F BIT(13) /*!< RTC tamper 0 detected flag */ +#define RTC_STAT_TP1F BIT(14) /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCPF BIT(16) /*!< smooth calibration pending flag */ + +/* RTC_PSC */ +#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ +#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ + +/* RTC_WUT */ +#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */ + +/* RTC_COSC */ +#define RTC_COSC_COSS BITS(0,4) /*!< coarse calibration step */ +#define RTC_COSC_COSD BIT(7) /*!< coarse calibration direction */ + +/* RTC_ALRMxTD */ +#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */ +#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */ +#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */ +#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */ +#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour units in BCD code */ +#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */ +#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */ +#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ +#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */ +#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */ +#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */ + +/* RTC_WPK */ +#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ + +/* RTC_SS */ +#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ + +/* RTC_SHIFTCTL */ +#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ +#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ + +/* RTC_TTS */ +#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ +#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DTS */ +#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ + +/* RTC_SSTS */ +#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ + +/* RTC_HRFC */ +#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ +#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ + +/* RTC_TAMP */ +#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ +#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ +#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ +#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ +#define RTC_TAMP_TP1EG BIT(4) /*!< Tamper 1 event trigger edge for RTC tamp 1 input */ +#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ +#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ +#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ +#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ +#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ +#define RTC_TAMP_TP0SEL BIT(16) /*!< Tamper 0 function input mapping selection */ +#define RTC_TAMP_TSSEL BIT(17) /*!< Timestamp input mapping selection */ +#define RTC_TAMP_AOT BIT(18) /*!< RTC_ALARM output Type */ + +/* RTC_ALRM0SS */ +#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */ +#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* RTC_ALRM1SS */ +#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */ +#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* constants definitions */ +/* structure for initialization of the RTC */ +typedef struct +{ + uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ + uint8_t month; /*!< RTC month value */ + uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ + uint8_t day_of_week; /*!< RTC weekday value */ + uint8_t hour; /*!< RTC hour value */ + uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ + uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ + uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ + uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ + uint32_t am_pm; /*!< RTC AM/PM value */ + uint32_t display_format; /*!< RTC time notation */ +}rtc_parameter_struct; + +/* structure for RTC alarm configuration */ +typedef struct +{ + uint32_t alarm_mask; /*!< RTC alarm mask */ + uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */ + uint8_t alarm_day; /*!< RTC alarm date or weekday value*/ + uint8_t alarm_hour; /*!< RTC alarm hour value */ + uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ + uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ + uint32_t am_pm; /*!< RTC alarm AM/PM value */ +}rtc_alarm_struct; + +/* structure for RTC time-stamp configuration */ +typedef struct +{ + uint8_t timestamp_month; /*!< RTC time-stamp month value */ + uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ + uint8_t timestamp_day; /*!< RTC time-stamp weekday value */ + uint8_t timestamp_hour; /*!< RTC time-stamp hour value */ + uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ + uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ + uint32_t am_pm; /*!< RTC time-stamp AM/PM value */ +}rtc_timestamp_struct; + +/* structure for RTC tamper configuration */ +typedef struct +{ + uint32_t tamper_source; /*!< RTC tamper source */ + uint32_t tamper_trigger; /*!< RTC tamper trigger */ + uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ + uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ + ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ + uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ + ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ +}rtc_tamper_struct; + +/* time register value */ +#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ +#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ + +#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */ +#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ + +#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */ +#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ + +#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ +#define RTC_PM RTC_TIME_PM /*!< PM format */ + +/* date register value */ +#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */ +#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ + +#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */ +#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ +#define RTC_JAN ((uint8_t)0x01U) /*!< janurary */ +#define RTC_FEB ((uint8_t)0x02U) /*!< february */ +#define RTC_MAR ((uint8_t)0x03U) /*!< march */ +#define RTC_APR ((uint8_t)0x04U) /*!< april */ +#define RTC_MAY ((uint8_t)0x05U) /*!< may */ +#define RTC_JUN ((uint8_t)0x06U) /*!< june */ +#define RTC_JUL ((uint8_t)0x07U) /*!< july */ +#define RTC_AUG ((uint8_t)0x08U) /*!< august */ +#define RTC_SEP ((uint8_t)0x09U) /*!< september */ +#define RTC_OCT ((uint8_t)0x10U) /*!< october */ +#define RTC_NOV ((uint8_t)0x11U) /*!< november */ +#define RTC_DEC ((uint8_t)0x12U) /*!< december */ + +#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */ +#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ +#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */ +#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */ +#define RTC_WEDSDAY ((uint8_t)0x03) /*!< wednesday */ +#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */ +#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */ +#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */ +#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */ + +#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */ +#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ + +/* ctl register value */ +#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */ +#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ +#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */ +#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */ +#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */ + +#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ +#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ +#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */ +#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/ +#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */ +#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/ +#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */ +#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/ + +#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ +#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ + +#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ +#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ + +/* psc register value */ +#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */ +#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ + +#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */ +#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ + +/* alrmtd register value */ +#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */ +#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */ + +#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */ +#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */ + +#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */ +#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */ + +#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */ +#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */ + +#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ +#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */ +#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */ +#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */ +#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */ +#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */ + +#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ +#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */ + +/* wpk register value */ +#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */ + +/* ss register value */ +#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */ + +/* shiftctl register value */ +#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ + +#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ +#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ + +/* tts register value */ +#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */ +#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ + +#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */ +#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ + +#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */ +#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ + +/* dts register value */ +#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */ +#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ + +#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ + +#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ +#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ + +/* ssts register value */ +#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */ + +/* hrfc register value */ +#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */ + +#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ + +#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ +#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ + +/* tamp register value */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ + +#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */ +#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ +#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ +#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ +#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ + +#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */ +#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ + +#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ +#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ + +#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ +#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ + +#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ + +#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ +#define RTC_ALARM_OUTPUT_PP RTC_TAMP_AOT /*!< RTC alarm output push-pull mode */ + +/* ALRMXSS register value */ +#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */ + +#define ALRMXSS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MASKSSC bit field */ +#define RTC_MASKSSC_0_14 ALRMXSS_MASKSSC(0) /*!< mask alarm subsecond configuration */ +#define RTC_MASKSSC_1_14 ALRMXSS_MASKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */ +#define RTC_MASKSSC_2_14 ALRMXSS_MASKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */ +#define RTC_MASKSSC_3_14 ALRMXSS_MASKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */ +#define RTC_MASKSSC_4_14 ALRMXSS_MASKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */ +#define RTC_MASKSSC_5_14 ALRMXSS_MASKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */ +#define RTC_MASKSSC_6_14 ALRMXSS_MASKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */ +#define RTC_MASKSSC_7_14 ALRMXSS_MASKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_8_14 ALRMXSS_MASKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_9_14 ALRMXSS_MASKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */ +#define RTC_MASKSSC_10_14 ALRMXSS_MASKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */ +#define RTC_MASKSSC_11_14 ALRMXSS_MASKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */ +#define RTC_MASKSSC_12_14 ALRMXSS_MASKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */ +#define RTC_MASKSSC_13_14 ALRMXSS_MASKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */ +#define RTC_MASKSSC_14 ALRMXSS_MASKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */ +#define RTC_MASKSSC_NONE ALRMXSS_MASKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */ + +/* RTC interrupt source */ +#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ +#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */ +#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */ +#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ +#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */ + +/* write protect key */ +#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ +#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ +#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ + +/* registers reset value */ +#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ +#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ +#define RTC_STAT_RESET ((uint32_t)0x00000000U) /*!< RTC_STAT register reset value */ +#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ +#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ + +/* RTC alarm */ +#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ +#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ + +/* RTC coarse calibration direction */ +#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ +#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ + +/* RTC wakeup timer clock */ +#define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) +#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */ +#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */ +#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */ +#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ +#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ +#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ + +/* RTC_AF pin */ +#define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ +#define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ +#define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */ +#define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ + +/* RTC flags */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ +#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ +#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */ +#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */ +#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ +#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ +#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ +#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ +#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ +#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */ + +/* function declarations */ +/* reset most of the RTC registers */ +ErrStatus rtc_deinit(void); +/* initialize RTC registers */ +ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); +/* enter RTC init mode */ +ErrStatus rtc_init_mode_enter(void); +/* exit RTC init mode */ +void rtc_init_mode_exit(void); +/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ +ErrStatus rtc_register_sync_wait(void); + +/* get current time and date */ +void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); +/* get current subsecond value */ +uint32_t rtc_subsecond_get(void); + +/* configure RTC alarm */ +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time); +/* configure subsecond of RTC alarm */ +void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond); +/* get RTC alarm */ +void rtc_alarm_get(uint8_t rtc_alarm,rtc_alarm_struct* rtc_alarm_time); +/* get RTC alarm subsecond */ +uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm); +/* enable RTC alarm */ +void rtc_alarm_enable(uint8_t rtc_alarm); +/* disable RTC alarm */ +ErrStatus rtc_alarm_disable(uint8_t rtc_alarm); + +/* enable RTC time-stamp */ +void rtc_timestamp_enable(uint32_t edge); +/* disable RTC time-stamp */ +void rtc_timestamp_disable(void); +/* get RTC timestamp time and date */ +void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); +/* get RTC time-stamp subsecond */ +uint32_t rtc_timestamp_subsecond_get(void); +/* RTC time-stamp pin map */ +void rtc_timestamp_pin_map(uint32_t rtc_af); + +/* enable RTC tamper */ +void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); +/* disable RTC tamper */ +void rtc_tamper_disable(uint32_t source); +/* RTC tamper0 pin map */ +void rtc_tamper0_pin_map(uint32_t rtc_af); + +/* enable specified RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disble specified RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* check specified flag */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear specified flag */ +void rtc_flag_clear(uint32_t flag); + +/* configure RTC alarm output source */ +void rtc_alarm_output_config(uint32_t source, uint32_t mode); +/* configure RTC calibration output source */ +void rtc_calibration_output_config(uint32_t source); + +/* adjust the daylight saving time by adding or substracting one hour from the current time */ +void rtc_hour_adjust(uint32_t operation); +/* adjust RTC second or subsecond value of current time */ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); + +/* enable RTC bypass shadow registers function */ +void rtc_bypass_shadow_enable(void); +/* disable RTC bypass shadow registers function */ +void rtc_bypass_shadow_disable(void); + +/* enable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_enable(void); +/* disable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_disable(void); + +/* enable RTC wakeup timer */ +void rtc_wakeup_enable(void); +/* disable RTC wakeup timer */ +ErrStatus rtc_wakeup_disable(void); +/* set auto wakeup timer clock */ +ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock); +/* set auto wakeup timer value */ +ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer); +/* get auto wakeup timer value */ +uint16_t rtc_wakeup_timer_get(void); + +/* configure RTC smooth calibration */ +ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); +/* enable RTC coarse calibration */ +ErrStatus rtc_coarse_calibration_enable(void); +/* disable RTC coarse calibration */ +ErrStatus rtc_coarse_calibration_disable(void); +/* configure RTC coarse calibration direction and step */ +ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step); + +#endif /* GD32F4XX_RTC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h new file mode 100644 index 0000000..1d88e45 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_sdio.h @@ -0,0 +1,434 @@ +/*! + \file gd32f4xx_sdio.h + \brief definitions for the SDIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_SDIO_H +#define GD32F4XX_SDIO_H + +#include "gd32f4xx.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ +#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ +#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ +#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command functions */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t sdio_responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* flag and interrupt functions */ +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* SD I/O card functions */ +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* CE-ATA functions */ +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F4XX_SDIO_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h new file mode 100644 index 0000000..ce96da3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_spi.h @@ -0,0 +1,379 @@ +/*! + \file gd32f4xx_spi.h + \brief definitions for the SPI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F4XX_SPI_H +#define GD32F4XX_SPI_H + +#include "gd32f4xx.h" + +/* SPIx(x=0,1,2,3,4,5) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) +#define SPI3 (SPI_BASE + 0x0000FC00U) +#define SPI4 (SPI_BASE + 0x00011800U) +#define SPI5 (SPI_BASE + 0x00011C00U) + +/* I2Sx_ADD(x=1,2) definitions */ +#define I2S1_ADD I2S_ADD_BASE +#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ + +/* I2S_ADD registers definitions */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2S_PSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_SPI_QCTL(only SPI5) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct { + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI nss control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +} spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock polarity and phase */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl); +/* configure I2S prescale */ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI nss output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI nss output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI nss pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI nss pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* SPI DMA functions */ +/* enable SPI DMA send or receive */ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma); +/* diable SPI DMA send or receive */ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma); + +/* SPI/I2S transfer configure functions */ +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void spi_quad_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void spi_quad_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void spi_quad_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void spi_quad_read_enable(uint32_t spi_periph); +/* enable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); + +/* flag & interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int); +/* get SPI and I2S interrupt status*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F4XX_SPI_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h new file mode 100644 index 0000000..b3c598e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_syscfg.h @@ -0,0 +1,182 @@ +/*! + \file gd32f4xx_syscfg.h + \brief definitions for the SYSCFG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_SYSCFG_H +#define GD32F4XX_SYSCFG_H + +#include "gd32f4xx.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ +#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U) /*!< system I/O compensation control register */ + +/* SYSCFG_CFG0 bits definitions */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,2) /*!< SYSCFG memory remap config */ +#define SYSCFG_CFG0_FMC_SWP BIT(8) /*!< FMC memory swap config */ +#define SYSCFG_CFG0_EXMC_SWP BITS(10,11) /*!< EXMC memory swap config */ + +/* SYSCFG_CFG1 bits definitions */ +#define SYSCFG_CFG1_ENET_PHY_SEL BIT(23) /*!< Ethernet PHY selection config */ + +/* SYSCFG_EXTISS0 bits definitions */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 bits definitions */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 bits definitions */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 bits definitions */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SYSCFG_CPSCTL bits definitions */ +#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +/* boot mode definitions */ +#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< main flash memory remap */ +#define SYSCFG_BOOTMODE_BOOTLOADER ((uint8_t)0x01U) /*!< boot loader remap */ +#define SYSCFG_BOOTMODE_EXMC_SRAM ((uint8_t)0x02U) /*!< SRAM/NOR 0 and 1 of EXMC remap */ +#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< SRAM0 of on-chip SRAM remap */ +#define SYSCFG_BOOTMODE_EXMC_SDRAM ((uint8_t)0x04U) /*!< SDRAM bank0 of EXMC remap */ + +/* FMC swap definitions */ +#define SYSCFG_FMC_SWP_BANK0 ((uint32_t)0x00000000U) /*!< main flash Bank 0 is mapped at address 0x08000000 */ +#define SYSCFG_FMC_SWP_BANK1 ((uint32_t)0x00000100U) /*!< main flash Bank 1 is mapped at address 0x08000000 */ + +/* EXMC swap enable/disable */ +#define SYSCFG_EXMC_SWP_ENABLE ((uint32_t)0x00000400U) /*!< SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card */ +#define SYSCFG_EXMC_SWP_DISABLE ((uint32_t)0x00000000U) /*!< no memory mapping swap */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select GPIOx pin 0~3 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select GPIOx pin 4~7 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select GPIOx pin 8~11 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ +#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ +#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */ +#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */ +#define EXTI_SOURCE_GPIOI ((uint8_t)0x08U) /*!< EXTI GPIOI configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* ethernet PHY selection */ +#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */ +#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */ + +/* I/O compensation cell enable/disable */ +#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */ +#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */ + +/* function declarations */ +/* initialization functions */ +/* deinit syscfg module */ +void syscfg_deinit(void); + +/* function configuration */ +/* configure the boot mode */ +void syscfg_bootmode_config(uint8_t syscfg_bootmode); +/* configure FMC memory mapping swap */ +void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); +/* configure the EXMC swap */ +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); +/* configure the PHY interface for the ethernet MAC */ +void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface); +/* configure the I/O compensation cell */ +void syscfg_compensation_config(uint32_t syscfg_compensation); + +/* interrupt & flag functions */ +/* check the I/O compensation cell is ready or not */ +FlagStatus syscfg_flag_get(void); + +#endif /* GD32F4XX_SYSCFG_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h new file mode 100644 index 0000000..f83d281 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_timer.h @@ -0,0 +1,779 @@ +/*! + \file gd32f4xx_timer.h + \brief definitions for the TIMER + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TIMER_H +#define GD32F4XX_TIMER_H + +#include "gd32f4xx.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00010000U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00010400U) +#define TIMER8 (TIMER_BASE + 0x00014000U) +#define TIMER9 (TIMER_BASE + 0x00014400U) +#define TIMER10 (TIMER_BASE + 0x00014800U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ +#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ +#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ +#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER1_IRMP_ITI1_RMP BITS(10,11) /*!< TIMER1 internal trigger input 1 remap */ +#define TIMER4_IRMP_CI3_RMP BITS(6,7) /*!< TIMER4 channel 3 input remap */ +#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ + +/* timer1 internal trigger input1 remap */ +#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) +#define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ +#define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ +#define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ +#define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ + +/* timer4 channel 3 input remap */ +#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) +#define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ +#define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ +#define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ +#define TIMER4_CI3_RMP_RTC_WAKEUP_INT TIMER4_IRMP(3) /*!< timer4 channel 3 input remap to RTC wakeup interrupt */ + +/* timer10 internal trigger input1 remap */ +#define TIMER10_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER10_ITI1_RMP_GPIO TIMER10_IRMP(0) /*!< timer10 internal trigger input1 remap based on GPIO setting */ +#define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ + +/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* the output value selection */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ + +/* function declarations */ +/* TIMER timebase*/ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* timer DMA and event*/ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +/* TIMER interrupt and flag*/ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); + +#endif /* GD32F4XX_TIMER_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h new file mode 100644 index 0000000..e261acc --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_tli.h @@ -0,0 +1,373 @@ +/*! + \file gd32f4xx_tli.h + \brief definitions for the TLI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TLI_H +#define GD32F4XX_TLI_H + +#include "gd32f4xx.h" + +/* TLI definitions */ +#define TLI TLI_BASE /*!< TLI base address */ +/* TLI layer definitions */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */ + +/* registers definitions */ +#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */ +#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */ +#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */ +#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */ +#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */ +#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */ +#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */ +#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */ +#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */ +#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */ +#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */ +#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */ +#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */ +#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */ +#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */ +#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */ +#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */ +#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */ +#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */ +#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */ +#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */ +#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */ +#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */ +#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */ +#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */ + +/* bits definitions */ +/* TLI_SPSZ */ +#define TLI_SPSZ_VPSZ BITS(0,11) /*!< size of the vertical synchronous pulse */ +#define TLI_SPSZ_HPSZ BITS(16,27) /*!< size of the horizontal synchronous pulse */ + +/* TLI_BPSZ */ +#define TLI_BPSZ_VBPSZ BITS(0,11) /*!< size of the vertical back porch plus synchronous pulse */ +#define TLI_BPSZ_HBPSZ BITS(16,27) /*!< size of the horizontal back porch plus synchronous pulse */ + +/* TLI_ASZ */ +#define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */ +#define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */ + +/* TLI_SPSZ */ +#define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */ +#define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */ + +/* TLI_CTL */ +#define TLI_CTL_TLIEN BIT(0) /*!< TLI enable bit */ +#define TLI_CTL_BDB BITS(4,6) /*!< blue channel dither bits number */ +#define TLI_CTL_GDB BITS(8,10) /*!< green channel dither bits number */ +#define TLI_CTL_RDB BITS(12,14) /*!< red channel dither bits number */ +#define TLI_CTL_DFEN BIT(16) /*!< dither function enable */ +#define TLI_CTL_CLKPS BIT(28) /*!< pixel clock polarity selection */ +#define TLI_CTL_DEPS BIT(29) /*!< data enable polarity selection */ +#define TLI_CTL_VPPS BIT(30) /*!< vertical pulse polarity selection */ +#define TLI_CTL_HPPS BIT(31) /*!< horizontal pulse polarity selection */ + +/* TLI_RL */ +#define TLI_RL_RQR BIT(0) /*!< request reload */ +#define TLI_RL_FBR BIT(1) /*!< frame blank reload */ + +/* TLI_BGC */ +#define TLI_BGC_BVB BITS(0,7) /*!< background value blue */ +#define TLI_BGC_BVG BITS(8,15) /*!< background value green */ +#define TLI_BGC_BVR BITS(16,23) /*!< background value red */ + +/* TLI_INTEN */ +#define TLI_INTEN_LMIE BIT(0) /*!< line mark interrupt enable */ +#define TLI_INTEN_FEIE BIT(1) /*!< FIFO error interrupt enable */ +#define TLI_INTEN_TEIE BIT(2) /*!< transaction error interrupt enable */ +#define TLI_INTEN_LCRIE BIT(3) /*!< layer configuration reloaded interrupt enable */ + +/* TLI_INTF */ +#define TLI_INTF_LMF BIT(0) /*!< line mark flag */ +#define TLI_INTF_FEF BIT(1) /*!< FIFO error flag */ +#define TLI_INTF_TEF BIT(2) /*!< transaction error flag */ +#define TLI_INTF_LCRF BIT(3) /*!< layer configuration reloaded flag */ + +/* TLI_INTC */ +#define TLI_INTC_LMC BIT(0) /*!< line mark flag clear */ +#define TLI_INTC_FEC BIT(1) /*!< FIFO error flag clear */ +#define TLI_INTC_TEC BIT(2) /*!< transaction error flag clear */ +#define TLI_INTC_LCRC BIT(3) /*!< layer configuration reloaded flag clear */ + +/* TLI_LM */ +#define TLI_LM_LM BITS(0,10) /*!< line mark value */ + +/* TLI_CPPOS */ +#define TLI_CPPOS_VPOS BITS(0,15) /*!< vertical position */ +#define TLI_CPPOS_HPOS BITS(16,31) /*!< horizontal position */ + +/* TLI_STAT */ +#define TLI_STAT_VDE BIT(0) /*!< current VDE status */ +#define TLI_STAT_HDE BIT(1) /*!< current HDE status */ +#define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */ +#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */ + +/* TLI_LxCTL */ +#define TLI_LxCTL_LEN BIT(0) /*!< layer enable */ +#define TLI_LxCTL_CKEYEN BIT(1) /*!< color keying enable */ +#define TLI_LxCTL_LUTEN BIT(4) /*!< LUT enable */ + +/* TLI_LxHPOS */ +#define TLI_LxHPOS_WLP BITS(0,11) /*!< window left position */ +#define TLI_LxHPOS_WRP BITS(16,27) /*!< window right position */ + +/* TLI_LxVPOS */ +#define TLI_LxVPOS_WTP BITS(0,11) /*!< window top position */ +#define TLI_LxVPOS_WBP BITS(16,27) /*!< window bottom position */ + +/* TLI_LxCKEY */ +#define TLI_LxCKEY_CKEYB BITS(0,7) /*!< color key blue */ +#define TLI_LxCKEY_CKEYG BITS(8,15) /*!< color key green */ +#define TLI_LxCKEY_CKEYR BITS(16,23) /*!< color key red */ + +/* TLI_LxPPF */ +#define TLI_LxPPF_PPF BITS(0,2) /*!< packeted pixel format */ + +/* TLI_LxSA */ +#define TLI_LxSA_SA BITS(0,7) /*!< specified alpha */ + +/* TLI_LxDC */ +#define TLI_LxDC_DCB BITS(0,7) /*!< the default color blue */ +#define TLI_LxDC_DCG BITS(8,15) /*!< the default color green */ +#define TLI_LxDC_DCR BITS(16,23) /*!< the default color red */ +#define TLI_LxDC_DCA BITS(24,31) /*!< the default color alpha */ + +/* TLI_LxBLEND */ +#define TLI_LxBLEND_ACF2 BITS(0,2) /*!< alpha calculation factor 2 of blending method */ +#define TLI_LxBLEND_ACF1 BITS(8,10) /*!< alpha calculation factor 1 of blending method */ + +/* TLI_LxFBADDR */ +#define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */ + +/* TLI_LxFLLEN */ +#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */ +#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */ + +/* TLI_LxFTLN */ +#define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */ + +/* TLI_LxLUT */ +#define TLI_LxLUT_TB BITS(0,7) /*!< blue channel of a LUT entry */ +#define TLI_LxLUT_TG BITS(8,15) /*!< green channel of a LUT entry */ +#define TLI_LxLUT_TR BITS(16,23) /*!< red channel of a LUT entry */ +#define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */ + +/* constants definitions */ +/* TLI parameter struct definitions */ +typedef struct { + uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ + uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ + uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ + uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ + uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ + uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ + uint32_t totalsz_vtsz; /*!< vertical total size of the display */ + uint32_t totalsz_htsz; /*!< horizontal total size of the display */ + uint32_t backcolor_red; /*!< background value red */ + uint32_t backcolor_green; /*!< background value green */ + uint32_t backcolor_blue; /*!< background value blue */ + uint32_t signalpolarity_hs; /*!< horizontal pulse polarity selection */ + uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ + uint32_t signalpolarity_de; /*!< data enable polarity selection */ + uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ +} tli_parameter_struct; + +/* TLI layer parameter struct definitions */ +typedef struct { + uint16_t layer_window_rightpos; /*!< window right position */ + uint16_t layer_window_leftpos; /*!< window left position */ + uint16_t layer_window_bottompos; /*!< window bottom position */ + uint16_t layer_window_toppos; /*!< window top position */ + uint32_t layer_ppf; /*!< packeted pixel format */ + uint8_t layer_sa; /*!< specified alpha */ + uint8_t layer_default_alpha; /*!< the default color alpha */ + uint8_t layer_default_red; /*!< the default color red */ + uint8_t layer_default_green; /*!< the default color green */ + uint8_t layer_default_blue; /*!< the default color blue */ + uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ + uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ + uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ + uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ + uint16_t layer_frame_line_length; /*!< frame line length */ + uint16_t layer_frame_total_line_number; /*!< frame total line number */ +} tli_layer_parameter_struct; + +/* TLI layer LUT parameter struct definitions */ +typedef struct { + uint32_t layer_table_addr; /*!< look up table write address */ + uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ + uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ + uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ +} tli_layer_lut_parameter_struct; + +/* packeted pixel format */ +typedef enum { + LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +} tli_layer_ppf_enum; + +/* TLI flags */ +#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ +#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */ +#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */ +#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */ +#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */ +#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */ +#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */ +#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */ + +/* TLI interrupt enable or disable */ +#define TLI_INT_LM BIT(0) /*!< line mark interrupt */ +#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */ +#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */ +#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */ + +/* TLI interrupt flag */ +#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */ +#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */ +#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */ +#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */ + +/* layer reload configure */ +#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ +#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ + +/* dither function */ +#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ +#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ + +/* horizontal pulse polarity selection */ +#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ +#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ + +/* vertical pulse polarity selection */ +#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ +#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ + +/* pixel clock polarity selection */ +#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ +#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ + +/* data enable polarity selection */ +#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ +#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ + +/* alpha calculation factor 1 of blending method */ +#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) +#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ +#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ + +/* alpha calculation factor 2 of blending method */ +#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ +#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ + +/* function declarations */ +/* initialization functions, TLI enable or disable, TLI reload mode configuration */ +/* deinitialize TLI registers */ +void tli_deinit(void); +/* initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined */ +void tli_struct_para_init(tli_parameter_struct *tli_struct); +/* initialize TLI */ +void tli_init(tli_parameter_struct *tli_struct); +/* configure TLI dither function */ +void tli_dither_config(uint8_t dither_stat); +/* enable TLI */ +void tli_enable(void); +/* disable TLI */ +void tli_disable(void); +/* configurate TLI reload mode */ +void tli_reload_config(uint8_t reload_mod); + +/* TLI layer configuration functions */ +/* initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined */ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); +/* initialize TLI layer */ +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct); +/* reconfigure window position */ +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined */ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer LUT */ +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer color key */ +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey); +/* enable TLI layer */ +void tli_layer_enable(uint32_t layerx); +/* disable TLI layer */ +void tli_layer_disable(uint32_t layerx); +/* enable TLI layer color keying */ +void tli_color_key_enable(uint32_t layerx); +/* disable TLI layer color keying */ +void tli_color_key_disable(uint32_t layerx); +/* enable TLI layer LUT */ +void tli_lut_enable(uint32_t layerx); +/* disable TLI layer LUT */ +void tli_lut_disable(uint32_t layerx); + +/* set line mark value */ +void tli_line_mark_set(uint16_t line_num); +/* get current displayed position */ +uint32_t tli_current_pos_get(void); + +/* flag and interrupt functions */ +/* enable TLI interrupt */ +void tli_interrupt_enable(uint32_t int_flag); +/* disable TLI interrupt */ +void tli_interrupt_disable(uint32_t int_flag); +/* get TLI interrupt flag */ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag); +/* clear TLI interrupt flag */ +void tli_interrupt_flag_clear(uint32_t int_flag); +/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ +FlagStatus tli_flag_get(uint32_t flag); + +#endif /* GD32F4XX_TLI_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h new file mode 100644 index 0000000..5c1ce6e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_trng.h @@ -0,0 +1,103 @@ +/*! + \file gd32f4xx_trng.h + \brief definitions for the TRNG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_TRNG_H +#define GD32F4XX_TRNG_H + +#include "gd32f4xx.h" + +/* TRNG definitions */ +#define TRNG TRNG_BASE + +/* registers definitions */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ + +/* bits definitions */ +/* TRNG_CTL */ +#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ + +/* TRNG_STAT */ +#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ +#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */ +#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */ +#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */ +#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ + +/* TRNG_DATA */ +#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */ + +/* constants definitions */ +/* TRNG status flag */ +typedef enum { + TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ + TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ + TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ +} trng_flag_enum; + +/* TRNG inerrupt flag */ +typedef enum { + TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ + TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ +} trng_int_flag_enum; + +/* function declarations */ +/* initialization functions */ +/* reset TRNG */ +void trng_deinit(void); +/* enable TRNG */ +void trng_enable(void); +/* disable TRNG */ +void trng_disable(void); +/* get the true random data */ +uint32_t trng_get_true_random_data(void); + +/* interrupt & flag functions */ +/* enable TRNG interrupt */ +void trng_interrupt_enable(void); +/* disable TRNG interrupt */ +void trng_interrupt_disable(void); +/* get TRNG flag status */ +FlagStatus trng_flag_get(trng_flag_enum flag); +/* get TRNG interrupt flag status */ +FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); +/* clear TRNG interrupt flag status */ +void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); + +#endif /* GD32F4XX_TRNG_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h new file mode 100644 index 0000000..9e8fb17 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_usart.h @@ -0,0 +1,492 @@ +/*! + \file gd32f4xx_usart.h + \brief definitions for the USART + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_USART_H +#define GD32F4XX_USART_H + +#include "gd32f4xx.h" + +/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ +#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ +#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ +#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */ +#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */ +#define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */ +#define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */ + +/* registers definitions */ +#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ +#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ +#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ +#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ +#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ +#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ + +/* bits definitions */ +/* USARTx_STAT0 */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_CTL3 */ +#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_STAT1 */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ + +/* USARTx_CHC */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ +#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ + +/* USART flags */ +typedef enum { + /* flags in STAT0 register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in STAT1 register */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ + /* flags in CHC register */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ +} usart_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in CTL3 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ +} usart_interrupt_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ +} usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ +} usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversampling mode definitions */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */ +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART one sample bit method configure */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ +#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ + +/* break frame coherence mode */ +#define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */ +#define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */ + +/* USART parity check coherence mode */ +#define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1)) +#define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */ +#define USART_PCM_EN CHC_PCM(1) /*!< check the parity */ + +/* USART hardware flow control coherence mode */ +#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ +#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure usart baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure usart parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure usart word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure usart stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable usart */ +void usart_enable(uint32_t usart_periph); +/* disable usart */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable CK pin in synchronous mode */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* disable CK pin in synchronous mode */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* coherence control */ +/* configure break frame coherence mode */ +void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm); +/* configure parity check coherence mode */ +void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); +/* configure hardware flow control coherence mode */ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); + +/* DMA communication */ +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag & interrupt functions */ +/* get flag in STAT0/STAT1 register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT0/STAT1 register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); + +#endif /* GD32F4XX_USART_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h new file mode 100644 index 0000000..7a7735c --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/gd32f4xx_wwdgt.h @@ -0,0 +1,94 @@ +/*! + \file gd32f4xx_wwdgt.h + \brief definitions for the WWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F4XX_WWDGT_H +#define GD32F4XX_WWDGT_H + +#include "gd32f4xx.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); + +#endif /* GD32F4XX_WWDGT_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h new file mode 100644 index 0000000..56f64bf --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/system_gd32f4xx.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f4xx.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F4xx Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F4XX_H +#define SYSTEM_GD32F4XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F4XX_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h new file mode 100644 index 0000000..a64d10c --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/cdc_acm_core.h @@ -0,0 +1,68 @@ +/*! + \file cdc_acm_core.h + \brief the header file of cdc acm driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CDC_ACM_CORE_H +#define __CDC_ACM_CORE_H + +#include "usbd_enum.h" +#include "usb_cdc.h" + +#define USB_CDC_RX_LEN USB_CDC_DATA_PACKET_SIZE + +typedef struct { + uint8_t packet_sent; + uint8_t packet_receive; + + uint8_t data[USB_CDC_RX_LEN]; + uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; + + uint32_t receive_length; + + acm_line line_coding; +} usb_cdc_handler; + +extern usb_desc cdc_desc; +extern usb_class_core cdc_class; + +/* function declarations */ +/* check CDC ACM is ready for data transfer */ +uint8_t cdc_acm_check_ready(usb_dev *udev); +/* send CDC ACM data */ +void cdc_acm_data_send(usb_dev *udev); +/* receive CDC ACM data */ +void cdc_acm_data_receive(usb_dev *udev); + +#endif /* __CDC_ACM_CORE_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h new file mode 100644 index 0000000..fa6bd8e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_core.h @@ -0,0 +1,358 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#ifdef USE_DEVICE_MODE + #include "usbd_conf.h" +#endif /* USE_DEVICE_MODE */ + +#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */ +#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */ + +enum _usb_mode { + DEVICE_MODE = 0U, /*!< device mode */ + HOST_MODE, /*!< host mode */ + OTG_MODE /*!< OTG mode */ +}; + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0U, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0U, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ + uint8_t lpm_enable; /*!< USB link power mode(LPM) */ + uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */ + uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */ + uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */ + uint32_t base_reg; /*!< base register address */ +} usb_core_basic; + +#ifdef USE_DEVICE_MODE + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configure descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */ + uint8_t *qualifier_desc; /*!< qualifier descriptor */ +#endif + + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero length package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet length */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet length */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ + + uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out) (usb_dev *udev); + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_control control; /*!< USB control information */ + usb_desc *desc; /*!< USB descriptors pointer */ + usb_class_core *class_core; /*!< class driver */ + void *class_data[USBD_ITF_MAX_NUM]; /*!< class data pointer */ + void *user_data; /*!< user data pointer */ + void *pdata; /*!< reserved data pointer */ +} usb_perp_dev; + +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + +typedef enum _usb_pipe_status +{ + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_urb_state +{ + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL, + URB_PING +} usb_urb_state; + +typedef struct _usb_pipe +{ + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + __IO uint8_t supp_ping; + __IO uint8_t do_ping; + __IO uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + +typedef struct _usb_host_drv +{ + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; + void *data; +} usb_host_drv; + +#endif /* USE_HOST_MODE */ + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + +#ifdef USE_DEVICE_MODE + usb_perp_dev dev; /*!< USB peripheral device */ +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + usb_host_drv host; +#endif /* USE_HOST_MODE */ +} usb_core_driver; + +/* static inline function definitions */ + +/*! + \brief get the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; +} + +/*! + \brief set USB RX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] size: assigned FIFO size + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size) +{ + usb_regs->gr->GRFLEN = size; +} + +/*! + \brief enable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs) +{ + /* enable USB global interrupt */ + usb_regs->gr->GAHBCS |= GAHBCS_GINTEN; +} + +/*! + \brief disable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) +{ + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; +} + +/* function declarations */ +/* configure core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); +/* set endpoint or channel TX FIFO size */ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); +/* set USB current mode */ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode); + +#endif /* __DRV_USB_CORE_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h new file mode 100644 index 0000000..d891b43 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_dev.h @@ -0,0 +1,199 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "usbd_conf.h" +#include "drv_usb_core.h" + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +/* static inline function definitions */ + +/*! + \brief configure the USB device to be disconnected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief configure the USB device to be connected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to USB device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4U; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16U; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + +/*! + \brief set remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/* function declarations */ +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); +/* active the USB endpoint 0 transaction */ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc); +/* active the USB transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); +/* deactivate the USB transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); +/* set the USB transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); +/* clear the USB transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); +/* active remote wakeup signaling */ +void usb_rwkup_active (usb_core_driver *udev); +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); +/* USB device suspend */ +void usb_dev_suspend (usb_core_driver *udev); +/* stop the device and clean up FIFOs */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h new file mode 100644 index 0000000..bd1c89c --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_hw.h @@ -0,0 +1,64 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* function declarations */ +/* configure USB clock */ +void usb_rcu_config (void); +/* configure USB data line gpio */ +void usb_gpio_config (void); +/* configure USB interrupt */ +void usb_intr_config (void); +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); +/* delay in milliseconds */ +void usb_mdelay (const uint32_t msec); +/* configures system clock after wakeup from STOP mode */ +void system_clk_config_stop(void); +#ifdef USE_HOST_MODE +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h new file mode 100644 index 0000000..4c57347 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usb_regs.h @@ -0,0 +1,664 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ +#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ +#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum +{ + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH, /*!< USB speed high */ +}; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct +{ + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + + +typedef struct +{ + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct +{ + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct +{ + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< device threshold control 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ +} usb_erout; + +typedef struct _usb_regs +{ + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ +#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_DMAER BIT(2) /*!< DMA error */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* host channel-x DMA address register bits definitions */ +#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[2]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x DMA address register bits definitions */ +#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device OUT endpoint-x DMA address register bits definitions */ +#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /* OUT data packet received */ +#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2U /*!< embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ +#define EP4_OUT ((uint8_t)0x04) /*!< endpoint out 4 */ +#define EP4_IN ((uint8_t)0x84) /*!< endpoint in 4 */ +#define EP5_OUT ((uint8_t)0x05) /*!< endpoint out 5 */ +#define EP5_IN ((uint8_t)0x85) /*!< endpoint in 5 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h new file mode 100644 index 0000000..c118785 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/drv_usbd_int.h @@ -0,0 +1,54 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +void usbd_isr (usb_core_driver *udev); + +#ifdef USB_HS_DEDICATED_EP1_ENABLED +/* USB dedicated IN endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev); +/* USB dedicated OUT endpoint 1 interrupt service routine handler */ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev); +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +#endif /* __DRV_USBD_INT_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h new file mode 100644 index 0000000..7301eac --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_cdc.h @@ -0,0 +1,182 @@ +/*! + \file usb_cdc.h + \brief the header file of communication device class standard + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#include "usb_ch9_std.h" + +/* communications device class code */ +#define USB_CLASS_CDC 0x02U + +/* communications interface class control protocol codes */ +#define USB_CDC_PROTOCOL_NONE 0x00U +#define USB_CDC_PROTOCOL_AT 0x01U +#define USB_CDC_PROTOCOL_VENDOR 0xFFU + +/* data interface class code */ +#define USB_CLASS_DATA 0x0AU + +#define USB_DESCTYPE_CDC_ACM 0x21U +#define USB_DESCTYPE_CS_INTERFACE 0x24U + +#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43U + +/* class-specific notification codes for pstn subclasses */ +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20U + +/* class-specific request codes */ +#define SEND_ENCAPSULATED_COMMAND 0x00U +#define GET_ENCAPSULATED_RESPONSE 0x01U +#define SET_COMM_FEATURE 0x02U +#define GET_COMM_FEATURE 0x03U +#define CLEAR_COMM_FEATURE 0x04U + +#define SET_AUX_LINE_STATE 0x10U +#define SET_HOOK_STATE 0x11U +#define PULSE_SETUP 0x12U +#define SEND_PULSE 0x13U +#define SET_PULSE_TIME 0x14U +#define RING_AUX_JACK 0x15U + +#define SET_LINE_CODING 0x20U +#define GET_LINE_CODING 0x21U +#define SET_CONTROL_LINE_STATE 0x22U +#define SEND_BREAK 0x23U +#define NO_CMD 0xFFU + +#define SET_RINGER_PARMS 0x30U +#define GET_RINGER_PARMS 0x31U +#define SET_OPERATION_PARMS 0x32U +#define GET_OPERATION_PARMS 0x33U +#define SET_LINE_PARMS 0x34U +#define GET_LINE_PARMS 0x35U +#define DIAL_DIGITS 0x36U +#define SET_UNIT_PARAMETER 0x37U +#define GET_UNIT_PARAMETER 0x38U +#define CLEAR_UNIT_PARAMETER 0x39U +#define GET_PROFILE 0x3AU + +#define SET_ETHERNET_MULTICAST_FILTERS 0x40U +#define SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41U +#define GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42U +#define SET_ETHERNET_PACKET_FILTER 0x43U +#define GET_ETHERNET_STATISTIC 0x44U + +#define SET_ATM_DATA_FORMAT 0x50U +#define GET_ATM_DEVICE_STATISTICS 0x51U +#define SET_ATM_DEFAULT_VC 0x52U +#define GET_ATM_VC_STATISTICS 0x53U + +/* wValue for set control line state */ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002U +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000U +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001U +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000U + +/* CDC subclass code */ +enum usb_cdc_subclass { + USB_CDC_SUBCLASS_RESERVED = 0U, /*!< reserved */ + USB_CDC_SUBCLASS_DLCM, /*!< direct line control mode */ + USB_CDC_SUBCLASS_ACM, /*!< abstract control mode */ + USB_CDC_SUBCLASS_TCM, /*!< telephone control mode */ + USB_CDC_SUBCLASS_MCM, /*!< multichannel control model */ + USB_CDC_SUBCLASS_CCM, /*!< CAPI control model */ + USB_CDC_SUBCLASS_ENCM, /*!< ethernet networking control model */ + USB_CDC_SUBCLASS_ANCM /*!< ATM networking control model */ +}; + +#pragma pack(1) + +/* cdc acm line coding structure */ +typedef struct { + uint32_t dwDTERate; /*!< data terminal rate */ + uint8_t bCharFormat; /*!< stop bits */ + uint8_t bParityType; /*!< parity */ + uint8_t bDataBits; /*!< data bits */ +} acm_line; + +/* notification structure */ +typedef struct { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bNotification; /*!< communication interface class notifications */ + uint16_t wValue; /*!< value of notification */ + uint16_t wIndex; /*!< index of interface */ + uint16_t wLength; /*!< length of notification data */ +} acm_notification; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */ + uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */ +} usb_desc_header_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */ + uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */ +} usb_desc_call_managment_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D1 */ +} usb_desc_acm_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union function descriptor */ + uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */ + uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */ +} usb_desc_union_func; + +#pragma pack() + +typedef struct { + usb_desc_config config; + usb_desc_itf cmd_itf; + usb_desc_header_func cdc_header; + usb_desc_call_managment_func cdc_call_managment; + usb_desc_acm_func cdc_acm; + usb_desc_union_func cdc_union; + usb_desc_ep cdc_cmd_endpoint; + usb_desc_itf cdc_data_interface; + usb_desc_ep cdc_out_endpoint; + usb_desc_ep cdc_in_endpoint; +} usb_cdc_desc_config_set; + +#endif /* __USB_CDC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h new file mode 100644 index 0000000..89e6164 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usb_ch9_std.h @@ -0,0 +1,250 @@ +/*! + \file usb_ch9_std.h + \brief USB 2.0 standard defines + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CH9_STD_H +#define __USB_CH9_STD_H + +#include "usb_conf.h" + +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ +#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ +#define USB_IAD_DESC_LEN 0x08U /*!< USB IAD descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ +#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ +#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ +#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ +#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ + +#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ +#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ + +/* bit 4..0 of bmRequestType: recipient type */ +enum _usb_recp_type { + USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ + USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ + USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ + USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ +}; + +/* bRequest value */ +enum _usb_request { + USB_GET_STATUS = 0x0U, /*!< USB get status request */ + USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ + USB_RESERVED2 = 0x2U, + USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ + USB_RESERVED4 = 0x4U, + USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ + USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ + USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ + USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ + USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ + USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ + USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ + USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ +}; + +/* descriptor types of USB specifications */ +enum _usb_desctype { + USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ + USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ + USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ + USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ + USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ + USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualifier descriptor type */ + USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ + USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ + USB_DESCTYPE_IAD = 0xBU, /*!< USB interface association descriptor type */ + USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ +}; + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +/* bits 1..0 : transfer type */ +enum _usbx_type { + USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ + USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ + USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ + USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ +}; + +/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_NOSYNC 0x00U /*!< No Synchronization */ +#define USB_EP_ATTR_ASYNC 0x04U /*!< Asynchronous */ +#define USB_EP_ATTR_ADAPTIVE 0x08U /*!< Adaptive */ +#define USB_EP_ATTR_SYNC 0x0CU /*!< Synchronous */ +#define USB_EP_ATTR_SYNCTYPE 0x0CU /*!< Synchronous type */ + +/* bits 5..4 : usage type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_DATA 0x00U /*!< Data endpoint */ +#define USB_EP_ATTR_FEEDBACK 0x10U /*!< Feedback endpoint */ +#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20U /*!< Implicit feedback Data endpoint */ +#define USB_EP_ATTR_USAGETYPE 0x30U /*!< Usage type */ + +/* endpoint max packet size bits12..11 */ +#define USB_EP_MPS_ADD_0 (0x00 << 11) /*!< None(1 transaction per microframe */ +#define USB_EP_MPS_ADD_1 (0x01 << 11) /*!< 1 additional(2 transaction per microframe */ +#define USB_EP_MPS_ADD_2 (0x02 << 11) /*!< 2 additional(3 transaction per microframe */ + +#define FEATURE_SELECTOR_EP 0x00U /*!< USB endpoint feature selector */ +#define FEATURE_SELECTOR_DEV 0x01U /*!< USB device feature selector */ +#define FEATURE_SELECTOR_REMOTEWAKEUP 0x01U /*!< USB feature selector remote wakeup */ + +#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) +#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DEFAULT_CONFIG 0U + +/* USB classes */ +#define USB_CLASS_HID 0x03U /*!< USB HID class */ +#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ + +/* use the following values when USB host need to get descriptor */ +#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) + +/* as per USB specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#pragma pack(1) + +/* USB standard device request structure */ +typedef struct _usb_req { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ +} usb_req; + +/* USB setup packet define */ +typedef union _usb_setup { + uint8_t data[8]; + + usb_req req; +} usb_setup; + +/* USB descriptor defines */ + +typedef struct _usb_desc_header { + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_desc_header; + +typedef struct _usb_desc_dev { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_desc_dev; + +typedef struct _usb_desc_config { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_desc_config; + +typedef struct _usb_desc_itf { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_desc_itf; + +typedef struct _usb_desc_ep { + usb_desc_header header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_desc_ep; + +typedef struct _usb_desc_LANGID { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +} usb_desc_LANGID; + +typedef struct _usb_desc_str { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t unicode_string[128]; /*!< unicode string data */ +} usb_desc_str; + +#pragma pack() + +/* compute string descriptor length */ +#define USB_STRING_LEN(unicode_chars) (sizeof(usb_desc_header) + ((unicode_chars) << 1U)) + +#endif /* __USB_CH9_STD_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h new file mode 100644 index 0000000..e39a38f --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_core.h @@ -0,0 +1,105 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions prototype + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0U, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1U, /*!< default status */ + USBD_ADDRESSED = 2U, /*!< address send status */ + USBD_CONFIGURED = 3U, /*!< configured status */ + USBD_SUSPENDED = 4U /*!< suspended status */ +}; + +/* static inline function definitions */ + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +__STATIC_INLINE void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +__STATIC_INLINE uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return (uint16_t)udev->dev.transc_out[ep_num].xfer_count; +} + +/* function declarations */ +/* initializes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core); +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); +/* device connect */ +void usbd_connect (usb_core_driver *udev); +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +#endif /* __USBD_CORE_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h new file mode 100644 index 0000000..bd83cce --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_enum.h @@ -0,0 +1,103 @@ +/*! + \file usbd_enum.h + \brief USB enumeration definitions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_ENUM_H +#define __USBD_ENUM_H + +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +#ifndef NULL + #define NULL 0U +#endif + +typedef enum _usb_reqsta { + REQ_SUPP = 0x0U, /* request support */ + REQ_NOTSUPP = 0x1U, /* request not support */ +} usb_reqsta; + +/* string descriptor index */ +enum _str_index +{ + STR_IDX_LANGID = 0x0U, /* language ID string index */ + STR_IDX_MFC = 0x1U, /* manufacturer string index */ + STR_IDX_PRODUCT = 0x2U, /* product string index */ + STR_IDX_SERIAL = 0x3U, /* serial string index */ + STR_IDX_CONFIG = 0x4U, /* configuration string index */ + STR_IDX_ITF = 0x5U, /* interface string index */ + STR_IDX_MAX = 0xEFU, /* string maximum index */ +}; + +typedef enum _usb_pwrsta { + USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ + USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ +} usb_pwrsta; + +typedef enum _usb_feature +{ + USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ + USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ + USB_FEATURE_TEST_MODE = 0x2U, /* USB has endpoint test mode feature */ +} usb_feature; + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +/* USB device exported macros */ +#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) + +#define DEVICE_ID1 (0x1FFF7A10U) /* device ID1 */ +#define DEVICE_ID2 (0x1FFF7A14U) /* device ID2 */ +#define DEVICE_ID3 (0x1FFF7A18U) /* device ID3 */ + +#define DEVICE_ID (0x40023D00U) + +/* function declarations */ +/* handle USB standard device request */ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req); +/* handle USB device class request */ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req); +/* handle USB vendor request */ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req); +/* handle USB enumeration error */ +void usbd_enum_error (usb_core_driver *udev, usb_req *req); +/* convert hex 32bits value into unicode char */ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len); +/* get serial string */ +void serial_string_get (uint16_t *unicode_str); + +#endif /* __USBD_ENUM_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h new file mode 100644 index 0000000..caba07b --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/inc/usb/usbd_transc.h @@ -0,0 +1,58 @@ +/*! + \file usbd_transc.h + \brief USB transaction core functions prototype + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_TRANSC_H +#define __USBD_TRANSC_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB send data in the control transaction */ +usbd_status usbd_ctl_send (usb_core_driver *udev); +/* USB receive data in control transaction */ +usbd_status usbd_ctl_recev (usb_core_driver *udev); +/* USB send control transaction status */ +usbd_status usbd_ctl_status_send (usb_core_driver *udev); +/* USB control receive status */ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev); +/* USB setup stage processing */ +uint8_t usbd_setup_transc (usb_core_driver *udev); +/* data out stage processing */ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num); +/* data in stage processing */ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_TRANSC_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c new file mode 100644 index 0000000..be2524f --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_adc.c @@ -0,0 +1,1203 @@ +/*! + \file gd32f4xx_adc.c + \brief ADC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_adc.h" + +#define ROUTINE_TRIGGER_MODE ((uint32_t)28U) +#define INSERTED_TRIGGER_MODE ((uint32_t)20U) +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC routine channel macro */ +#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) + +/*! + \brief reset ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_deinit(void) +{ + rcu_periph_reset_enable(RCU_ADCRST); + rcu_periph_reset_disable(RCU_ADCRST); +} + +/*! + \brief configure the ADC clock for all the ADCs + \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: + \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 + \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 + \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 + \arg ADC_ADCCK_PCLK2_DIV8: PCLK2 div8 + \arg ADC_ADCCK_HCLK_DIV5: HCLK div5 + \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 + \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 + \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 + \param[out] none + \retval none +*/ +void adc_clock_config(uint32_t prescaler) +{ + ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_ADCCK); + ADC_SYNCCTL |= (uint32_t) prescaler; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + if(0U != (function & ADC_SCAN_MODE)) { + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* enable inserted sequence convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + } else { + if(0U != (function & ADC_SCAN_MODE)) { + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* disable inserted sequence convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)) { + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment) { + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + } else { + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { + } +} + +/*! + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: + \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 + \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { + /* enable ADC0 Vbat channel */ + ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { + /* enable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; + } + } else { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { + /* disable ADC0 Vbat channel */ + ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { + /* disable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; + } + } +} + +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) +{ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief when DMA=1, the DMA engine issues a request at end of each routine conversion + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); +} + +/*! + \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for routine sequence ,the number has no effect for inserted sequence + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) +{ + /* disable discontinuous mode of routine & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + if((length <= 8U) && (length >= 1U)) { + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + /* enable routine sequence discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted sequence discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of routine & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of routine sequence or inserted sequence + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] length: the length of the channel + routine channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + if((length >= 1U) && (length <= 16U)) { + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + case ADC_INSERTED_CHANNEL: + if((length >= 1U) && (length <= 4U)) { + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + default: + break; + } +} + +/*! + \brief configure ADC routine channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq, sampt; + + /* ADC routine sequence config */ + if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) { + /* the routine sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)); + ADC_RSQ2(adc_periph) = rsq; + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) { + /* the routine sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) { + /* the routine sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + } else { + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the routine sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the routine sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + /* get inserted sequence length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */ + if(rank < 4U) { + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the inserted sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the inserted sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH) { + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source + for routine sequence: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence + for inserted sequence: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC external trigger + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] trigger_mode: external trigger mode + only one parameter can be selected which is shown as below: + \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable + \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger + \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger + \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE); + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE); + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence) +{ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* enable ADC routine sequence software trigger */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; + break; + case ADC_INSERTED_CHANNEL: + /* enable ADC inserted sequence software trigger */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; + break; + default: + break; + } +} + +/*! + \brief configure end of conversion mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] end_selection: end of conversion mode + only one parameter can be selected which is shown as below: + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically. + \param[out] none + \retval none +*/ +void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) +{ + switch(end_selection) { + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of routine conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; + } +} + +/*! + \brief read ADC routine data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_routine_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted data register + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel) { + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief disable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); +} + +/*! + \brief enable ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); + + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; +} + +/*! + \brief configure ADC analog watchdog sequence channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: the sequence use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence + \param[out] none + \retval none +*/ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* routine channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_ROUTINE_INSERTED_CHANNEL: + /* routine and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: the sequence use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence) +{ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* disable ADC analog watchdog routine sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); + break; + case ADC_INSERTED_CHANNEL: + /* disable ADC analog watchdog inserted sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); + break; + case ADC_ROUTINE_INSERTED_CHANNEL: + /* disable ADC analog watchdog routine and inserted sequence */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); + break; + default: + break; + } +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + /* configure ADC analog watchdog low threshold */ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + /* configure ADC analog watchdog high threshold */ + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag) { + reval = SET; + } + return reval; + +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)) { + reval = SET; + } + return reval; +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt) { + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of sequence conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted sequence conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_ROVF: + /* get the ADC routine data register overflow interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; + if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc status flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + switch(adc_interrupt) { + case ADC_INT_WDE: + /* enable analog watchdog interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + break; + case ADC_INT_EOC: + /* enable end of sequence conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + break; + case ADC_INT_EOIC: + /* enable end of inserted sequence conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_ROVFIE; + break; + default: + break; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + switch(adc_interrupt) { + /* select the interrupt source */ + case ADC_INT_WDE: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); + break; + case ADC_INT_EOC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOCIE); + break; + case ADC_INT_EOIC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOICIE); + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ROVFIE); + break; + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] sync_mode: ADC sync mode + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode + \arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode + \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode + \arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode + \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode + \param[out] none + \retval none +*/ +void adc_sync_mode_config(uint32_t sync_mode) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCM); + ADC_SYNCCTL |= sync_mode; +} + +/*! + \brief configure the delay between 2 sampling phases in ADC sync modes + \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles + \param[out] none + \retval none +*/ +void adc_sync_delay_config(uint32_t sample_delay) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDLY); + ADC_SYNCCTL |= sample_delay; +} + +/*! + \brief configure ADC sync DMA mode selection + \param[in] dma_mode: ADC sync DMA mode + only one parameter can be selected which is shown as below: + \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 + \param[out] none + \retval none +*/ +void adc_sync_dma_config(uint32_t dma_mode) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDMA); + ADC_SYNCCTL |= dma_mode; +} + +/*! + \brief configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] none + \param[out] none + \retval none +*/ +void adc_sync_dma_request_after_last_enable(void) +{ + ADC_SYNCCTL |= ADC_SYNCCTL_SYNCDDM; +} + +/*! + \brief configure ADC sync DMA engine issues requests according to the SYNCDMA bits + \param[in] none + \param[out] none + \retval none +*/ +void adc_sync_dma_request_after_last_disable(void) +{ + ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDDM); +} + +/*! + \brief read ADC sync routine data register + \param[in] none + \param[out] none + \retval sync routine data +*/ +uint32_t adc_sync_routine_data_read(void) +{ + return (uint32_t)ADC_SYNCDATA; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c new file mode 100644 index 0000000..f0ccaf7 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_can.c @@ -0,0 +1,1021 @@ +/*! + \file gd32f4xx_can.c + \brief CAN driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-07-14, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2021-12-28, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_can.h" + +#define CAN_ERROR_HANDLE(s) do{}while(1) + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ + if(CAN0 == can_periph) { + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } else { + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +} + +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[out] p_struct: the pointer of the specific struct + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void *p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type) { + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = ENABLE; + ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = ENABLE; + ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct *)p_struct)->rx_efid = 0U; + ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct *)p_struct)->rx_fi = 0U; + ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x0400 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered) { + CAN_CTL(can_periph) |= CAN_CTL_TTC; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off management */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery) { + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up) { + CAN_CTL(can_periph) |= CAN_CTL_AWU; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode disable */ + if(ENABLE == can_parameter_init->auto_retrans) { + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; + } + /* receive FIFO overwrite mode disable */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + } + /* transmit FIFO order */ + if(ENABLE == can_parameter_init->trans_fifo_order) { + CAN_CTL(can_periph) |= CAN_CTL_TFO; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + /* check exit initialize mode */ + if(0U != timeout) { + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + } else { + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + } else { + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable) { + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 filter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; + + if(CAN0 == can_periph) { + dbg_periph_enable(DBG_CAN0_HOLD); + } else { + dbg_periph_enable(DBG_CAN1_HOLD); + } +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; + + if(CAN0 == can_periph) { + dbg_periph_disable(DBG_CAN0_HOLD); + } else { + dbg_periph_disable(DBG_CAN1_HOLD); + } +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the TTC mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TTC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlen: 0 - 8 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { + mailbox_number = CAN_MAILBOX0; + } else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { + mailbox_number = CAN_MAILBOX1; + } else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { + mailbox_number = CAN_MAILBOX2; + } else { + mailbox_number = CAN_NOMAILBOX; + } + /* return no mailbox empty */ + if(CAN_NOMAILBOX == mailbox_number) { + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff) { + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + } else { + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + /* check selected mailbox state */ + switch(mailbox_number) { + /* mailbox0 */ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + /* mailbox1 */ + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + /* mailbox2 */ + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + + switch(val) { + /* transmit pending */ + case(CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* mailbox0 transmit succeeded */ + case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + /* mailbox1 transmit succeeded */ + case(CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + /* mailbox2 transmit succeeded */ + case(CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + /* transmit failed */ + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { + } + } else if(CAN_MAILBOX1 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { + } + } else if(CAN_MAILBOX2 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { + } + } else { + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlen: 0 - 8 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff) { + /* get standard identifier */ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + } else { + /* get extended identifier */ + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* filtering index */ + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get receive data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else if(CAN_FIFO1 == fifo_number) { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } else { + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number) { + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + } else if(CAN_FIFO1 == fifo_number) { + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + } else { + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_working_mode + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode) { + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if(CAN_MODE_NORMAL == working_mode) { + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if(CAN_MODE_SLEEP == working_mode) { + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else { + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { + timeout--; + } + /* check state */ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_RXL: RX level + \arg CAN_FLAG_LASTRX: last sample value of RX pin + \arg CAN_FLAG_RS: receiving state + \arg CAN_FLAG_TS: transmitting state + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_SLPWS: sleep working state + \arg CAN_FLAG_IWS: initial working state + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO + \arg CAN_FLAG_TME2: transmit mailbox 2 empty + \arg CAN_FLAG_TME1: transmit mailbox 1 empty + \arg CAN_FLAG_TME0: transmit mailbox 0 empty + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + /* get flag and interrupt enable state */ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag + \arg CAN_INT_FLAG_ERRN: error number interrupt flag + \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag + \arg CAN_INT_FLAG_PERR: passive error interrupt flag + \arg CAN_INT_FLAG_WERR: warning error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + /* get the status of interrupt flag */ + if(flag == CAN_INT_FLAG_RFL0) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); + } else if(flag == CAN_INT_FLAG_RFL1) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); + } else if(flag == CAN_INT_FLAG_ERRN) { + ret1 = can_error_get(can_periph); + } else { + ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); + } + /* get the status of interrupt enable bit */ + ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); + if(ret1 && ret2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c new file mode 100644 index 0000000..753d5f2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_crc.c @@ -0,0 +1,130 @@ +/*! + \file gd32f4xx_crc.c + \brief CRC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_crc.h" + +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the value of the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the value of the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write data to the free data register + \param[in] free_data: specified 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values + \param[in] size: size of the array + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++) { + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c new file mode 100644 index 0000000..16573b9 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ctc.c @@ -0,0 +1,391 @@ +/*! + \file gd32f4xx_ctc.c + \brief CTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/* CTC register bit offset */ +#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) +#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) +#define CTC_REFCAP_OFFSET ((uint32_t)16U) +#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \arg 0x00 - 0x3F + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] hardmode: + only one parameter can be selected which is shown as below: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)hardmode; +} + +/*! + \brief configure reference signal source polarity + \param[in] polarity: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)polarity; +} + +/*! + \brief select reference signal source + \param[in] refs: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] prescaler: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00 - 0xFF + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); +} + +/*! + \brief configure CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000 - 0xFFFF + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)reload_value; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t interrupt) +{ + CTC_CTL0 |= (uint32_t)interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t interrupt) +{ + CTC_CTL0 &= (uint32_t)(~interrupt); +} + +/*! + \brief get CTC interrupt flag + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t interrupt_flag = 0U, intenable = 0U; + + /* check whether the interrupt is enabled */ + if(RESET != (int_flag & CTC_FLAG_MASK)) { + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; + } else { + intenable = CTC_CTL0 & int_flag; + } + + /* get interrupt flag status */ + interrupt_flag = CTC_STAT & int_flag; + + if(interrupt_flag && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC interrupt flag + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t int_flag) +{ + if(RESET != (int_flag & CTC_FLAG_MASK)) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= int_flag; + } +} + +/*! + \brief get CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t flag) +{ + if(RESET != (CTC_STAT & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t flag) +{ + if(RESET != (flag & CTC_FLAG_MASK)) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= flag; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c new file mode 100644 index 0000000..cea8620 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dac.c @@ -0,0 +1,678 @@ +/*! + \file gd32f4xx_dac.c + \brief DAC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dac.h" + +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DEN0; + } else { + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DEN0; + } else { + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDMAEN0; + } else { + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDMAEN0; + } else { + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DBOFF0; + } else { + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DBOFF0; + } else { + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph) { + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + } else { + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8 bit alignment + \arg DAC_ALIGN_12B_R: data right 12 bit alignment + \arg DAC_ALIGN_12B_L: data left 12 bit alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph) { + switch(dac_align) { + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + } else { + switch(dac_align) { + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DTEN0; + } else { + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DTEN0; + } else { + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph: DACx(x = 0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + } else { + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_SWT |= DAC_SWT_SWTR0; + } else { + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_SWT &= ~DAC_SWT_SWTR0; + } else { + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] wave_mode: noise wave mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + } else { + /* configure DAC1 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph: DACx(x = 0,1) + \param[in] bit_width: noise wave bit width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + } else { + /* configure DAC1 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + } else { + /* configure DAC1 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] amplitude: triangle amplitude in DAC triangle noise mode + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph) { + /* configure DAC0 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + } else { + /* configure DAC1 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} + +/*! + \brief enable DAC concurrent interrupt funcution + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_interrupt_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent interrupt funcution + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_interrupt_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; + DAC_CTL &= (~ctl); +} + +/*! + \brief get the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dac_flag_get(uint32_t dac_periph) +{ + FlagStatus temp_flag = RESET; + if(DAC0 == dac_periph) { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)) { + temp_flag = SET; + } + } else { + /* check the DMA underrun flag */ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)) { + temp_flag = SET; + } + } + return temp_flag; +} + +/*! + \brief clear the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_flag_clear(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_STAT |= DAC_STAT_DDUDR0; + } else { + DAC_STAT |= DAC_STAT_DDUDR1; + } +} + +/*! + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDUDRIE0; + } else { + DAC_CTL |= DAC_CTL_DDUDRIE1; + } +} + +/*! + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + } else { + DAC_CTL &= ~DAC_CTL_DDUDRIE1; + } +} + +/*! + \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) +{ + FlagStatus temp_flag = RESET; + uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + + if(DAC0 == dac_periph) { + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { + temp_flag = SET; + } + } else { + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { + temp_flag = SET; + } + } + return temp_flag; +} + +/*! + \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_flag_clear(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_STAT |= DAC_STAT_DDUDR0; + } else { + DAC_STAT |= DAC_STAT_DDUDR1; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c new file mode 100644 index 0000000..c786be2 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dbg.c @@ -0,0 +1,183 @@ +/*! + \file gd32f4xx_dbg.c + \brief DBG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dbg.h" + +#define DBG_RESET_VAL 0x00000000U + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c new file mode 100644 index 0000000..2bce769 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dci.c @@ -0,0 +1,346 @@ +/*! + \file gd32f4xx_dci.c + \brief DCI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dci.h" + +/*! + \brief DCI deinit + \param[in] none + \param[out] none + \retval none +*/ +void dci_deinit(void) +{ + rcu_periph_reset_enable(RCU_DCIRST); + rcu_periph_reset_disable(RCU_DCIRST); +} + +/*! + \brief initialize DCI registers + \param[in] dci_struct: DCI parameter initialization structure + members of the structure and the member values are shown as below: + capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT + colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING + hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH + vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH + frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4 + interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS, + DCI_INTERFACE_FORMAT_12BITS, DCI_INTERFACE_FORMAT_14BITS + \param[out] none + \retval none +*/ +void dci_init(dci_parameter_struct *dci_struct) +{ + uint32_t reg = 0U; + /* disable capture function and DCI */ + DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN); + /* configure DCI parameter */ + reg |= dci_struct->capture_mode; + reg |= dci_struct->clock_polarity; + reg |= dci_struct->hsync_polarity; + reg |= dci_struct->vsync_polarity; + reg |= dci_struct->frame_rate; + reg |= dci_struct->interface_format; + + DCI_CTL = reg; +} + +/*! + \brief enable DCI function + \param[in] none + \param[out] none + \retval none +*/ +void dci_enable(void) +{ + DCI_CTL |= DCI_CTL_DCIEN; +} + +/*! + \brief disable DCI function + \param[in] none + \param[out] none + \retval none +*/ +void dci_disable(void) +{ + DCI_CTL &= ~DCI_CTL_DCIEN; +} + +/*! + \brief enable DCI capture + \param[in] none + \param[out] none + \retval none +*/ +void dci_capture_enable(void) +{ + DCI_CTL |= DCI_CTL_CAP; +} + +/*! + \brief disable DCI capture + \param[in] none + \param[out] none + \retval none +*/ +void dci_capture_disable(void) +{ + DCI_CTL &= ~DCI_CTL_CAP; +} + +/*! + \brief enable DCI jpeg mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_jpeg_enable(void) +{ + DCI_CTL |= DCI_CTL_JM; +} + +/*! + \brief disable DCI jpeg mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_jpeg_disable(void) +{ + DCI_CTL &= ~DCI_CTL_JM; +} + +/*! + \brief enable cropping window function + \param[in] none + \param[out] none + \retval none +*/ +void dci_crop_window_enable(void) +{ + DCI_CTL |= DCI_CTL_WDEN; +} + +/*! + \brief disable cropping window function + \param[in] none + \param[out] none + \retval none +*/ +void dci_crop_window_disable(void) +{ + DCI_CTL &= ~DCI_CTL_WDEN; +} + +/*! + \brief configure DCI cropping window + \param[in] start_x: window horizontal start position + \param[in] start_y: window vertical start position + \param[in] size_width: window horizontal size + \param[in] size_height: window vertical size + \param[out] none + \retval none +*/ +void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) +{ + DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16)); + DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16)); +} + +/*! + \brief enable embedded synchronous mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_embedded_sync_enable(void) +{ + DCI_CTL |= DCI_CTL_ESM; +} + +/*! + \brief disble embedded synchronous mode + \param[in] none + \param[out] none + \retval none +*/ +void dci_embedded_sync_disable(void) +{ + DCI_CTL &= ~DCI_CTL_ESM; +} +/*! + \brief config synchronous codes in embedded synchronous mode + \param[in] frame_start: frame start code in embedded synchronous mode + \param[in] line_start: line start code in embedded synchronous mode + \param[in] line_end: line end code in embedded synchronous mode + \param[in] frame_end: frame end code in embedded synchronous mode + \param[out] none + \retval none +*/ +void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) +{ + DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); +} + +/*! + \brief config synchronous codes unmask in embedded synchronous mode + \param[in] frame_start: frame start code unmask bits in embedded synchronous mode + \param[in] line_start: line start code unmask bits in embedded synchronous mode + \param[in] line_end: line end code unmask bits in embedded synchronous mode + \param[in] frame_end: frame end code unmask bits in embedded synchronous mode + \param[out] none + \retval none +*/ +void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) +{ + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); +} + +/*! + \brief read DCI data register + \param[in] none + \param[out] none + \retval data +*/ +uint32_t dci_data_read(void) +{ + return DCI_DATA; +} + +/*! + \brief get specified flag + \param[in] flag: + \arg DCI_FLAG_HS: HS line status + \arg DCI_FLAG_VS: VS line status + \arg DCI_FLAG_FV:FIFO valid + \arg DCI_FLAG_EF: end of frame flag + \arg DCI_FLAG_OVR: FIFO overrun flag + \arg DCI_FLAG_ESE: embedded synchronous error flag + \arg DCI_FLAG_VSYNC: vsync flag + \arg DCI_FLAG_EL: end of line flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_flag_get(uint32_t flag) +{ + uint32_t stat = 0U; + + if(flag >> 31) { + /* get flag status from DCI_STAT1 register */ + stat = DCI_STAT1; + } else { + /* get flag status from DCI_STAT0 register */ + stat = DCI_STAT0; + } + + if(flag & stat) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief enable specified DCI interrupt + \param[in] interrupt: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_enable(uint32_t interrupt) +{ + DCI_INTEN |= interrupt; +} + +/*! + \brief disable specified DCI interrupt + \param[in] interrupt: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_disable(uint32_t interrupt) +{ + DCI_INTEN &= ~interrupt; +} + +/*! + \brief clear specified interrupt flag + \param[in] int_flag: + \arg DCI_INT_EF: end of frame interrupt + \arg DCI_INT_OVR: FIFO overrun interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt + \arg DCI_INT_EL: end of line interrupt + \param[out] none + \retval none +*/ +void dci_interrupt_flag_clear(uint32_t int_flag) +{ + DCI_INTC |= int_flag; +} + +/*! + \brief get specified interrupt flag + \param[in] int_flag: + \arg DCI_INT_FLAG_EF: end of frame interrupt flag + \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag + \arg DCI_INT_FLAG_EL: end of line interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_interrupt_flag_get(uint32_t int_flag) +{ + if(RESET == (DCI_INTF & int_flag)) { + return RESET; + } else { + return SET; + } +} + + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c new file mode 100644 index 0000000..c5a1f9e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_dma.c @@ -0,0 +1,904 @@ +/*! + \file gd32f4xx_dma.c + \brief DMA driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_dma.h" + +/* DMA register bit offset */ +#define CHXCTL_PERIEN_OFFSET ((uint32_t)25U) + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE; + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } +} + +/*! + \brief initialize the DMA single data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->periph_memory_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize the DMA multi data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->memory_burst_width = 0U; + init_struct->periph_burst_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA single data mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA_CHx(x=0..7) + \param[in] init_struct: the data needed to initialize DMA single data mode + periph_addr: peripheral base address + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + memory0_addr: memory base address + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct *init_struct) +{ + uint32_t ctl; + + /* select single data mode */ + DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_MDMEN; + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + + /* configure peripheral and memory transfer width,channel priotity,transfer mode */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); + ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure DMA circular mode */ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; + } +} + +/*! + \brief initialize DMA multi data mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA_CHx(x=0..7) + \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode + periph_addr: peripheral base address + periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + memory0_addr: memory0 base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT + periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT + critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct *init_struct) +{ + uint32_t ctl; + + /* select multi data mode and configure FIFO critical value */ + DMA_CHFCTL(dma_periph, channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = init_struct->number; + + /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); + ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | + init_struct->periph_burst_width); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure DMA circular mode */ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; + } +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + \arg DMA_CHx(x=0..7) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA Memory0 base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set Memory base address + \arg DMA_CHx(x=0..7) + \param[in] memory_flag: DMA_MEMORY_x(x=0,1) + \param[in] address: Memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) +{ + if(memory_flag) { + DMA_CHM1ADDR(dma_periph, channelx) = address; + } else { + DMA_CHM0ADDR(dma_periph, channelx) = address; + } +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(dma_periph, channelx) = number; +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA_CHx(x=0..7) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] mbeat: transfer burst beats + \arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst + \arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst + \arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst + \arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_memory_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MBURST; + ctl |= mbeat; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer burst beats of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] pbeat: transfer burst beats + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst + \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst + \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst + \arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst + \param[out] none + \retval none +*/ +void dma_periph_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PBURST; + ctl |= pbeat; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= msize; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] msize: transfer data size of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= psize; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure memory address generation generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode + \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode + \param[out] none + \retval none +*/ +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } +} + +/*! + \brief configure peripheral address generation_algorithm + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode + \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode + \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed + \param[out] none + \retval none +*/ +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) +{ + if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral + \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_TM; + ctl |= direction; + + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief DMA switch buffer mode config + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] memory1_addr: memory1 base address + \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) +{ + /* configure memory1 base address */ + DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr; + + if(DMA_MEMORY_0 == memory_select) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS; + } +} + +/*! + \brief DMA using memory get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) { + return DMA_MEMORY_1; + } else { + return DMA_MEMORY_0; + } +} + +/*! + \brief DMA channel peripheral select + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] sub_periph: specify DMA channel peripheral + \arg DMA_SUBPERIx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) +{ + uint32_t ctl; + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PERIEN; + ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); + + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief DMA flow controller configure + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] controller: specify DMA flow controler + only one parameter can be selected which is shown as below: + \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller + \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller + \param[out] none + \retval none +*/ +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) +{ + if(DMA_FLOW_CONTROLLER_DMA == controller) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_TFCS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_TFCS; + } +} + +/*! + \brief DMA switch buffer mode enable + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + /* switch buffer mode enable */ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_SBMEN; + } else { + /* switch buffer mode disable */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_SBMEN; + } +} + +/*! + \brief DMA FIFO status get + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval the using memory +*/ +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + return (DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FCNT); +} + +/*! + \brief get DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA_CHx(x=0..7) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + if(channelx < DMA_CH4) { + if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { + return SET; + } else { + return RESET; + } + } else { + channelx -= (dma_channel_enum)4; + if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { + return SET; + } else { + return RESET; + } + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA_CHx(x=0..7) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to enbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) |= source; + } else { + DMA_CHFCTL(dma_periph, channelx) |= source; + } +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to disbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) &= ~source; + } else { + DMA_CHFCTL(dma_periph, channelx) &= ~source; + } +} + +/*! + \brief get DMA interrupt flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get interrupt flag + \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + dma_channel_enum channel_flag_offset = channelx; + if(channelx < DMA_CH4) { + switch(interrupt) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE); + break; + default: + break; + } + } else { + channel_flag_offset -= (dma_channel_enum)4; + switch(interrupt) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + default: + break; + } + } + + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear DMA a channel interrupt flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear interrupt flag + \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) +{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } else { + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c new file mode 100644 index 0000000..39afe43 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_enet.c @@ -0,0 +1,3510 @@ +/*! + \file gd32f4xx_enet.c + \brief ENET driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_enet.h" + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static uint32_t enet_unknow_err = 0U; +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; + +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum + only one parameter can be selected which is shown as below + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX + - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ + ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; + - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE ; + - ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ; + - ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ; + - ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ; + - ENET_ACTIVE_THRESHOLD_1792BYTES ; + - ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ; + - ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ; + - ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ; + - ENET_DEACTIVE_THRESHOLD_1792BYTES . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch(option) { + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + +#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE + para &= ~ENET_ENHANCED_DESCRIPTOR; +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, refer to enet_frmrecept_enum + only one parameter can be selected which is shown as below + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state = ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if(ERROR == enet_phy_config()) { + _ENET_DELAY_(PHY_RESETDELAY); + if(ERROR == enet_phy_config()) { + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { + /* wait for PHY_LINKED_STATUS bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + } while((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { + media_temp = ENET_MODE_FULLDUPLEX; + } else { + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { + media_temp |= ENET_SPEEDMODE_10M; + } else { + media_temp |= ENET_SPEEDMODE_100M; + } + } else { + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); + temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); + temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + + reg_value = ENET_DMA_BCTL; + temp = reg_temp; + /* configure ENET_DMA_BCTL register */ + reg_value &= (~ENET_DMA_BCTL_DFM); + temp &= ENET_DMA_BCTL_DFM; + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do { + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#else + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#endif + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + } else { + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); + } + + } else { + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt,, refer to enet_int_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, refer to enet_int_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if(max > limit) { + max = limit; + } + + for(; offset < max; offset++) { + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief get the enet debug status from the debug register + \param[in] mac_debug: enet debug status + only one parameter can be selected which is shown as below + \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state + \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation + \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status + \arg ENET_RXFIFO_STATE: RxFIFO state + \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state + \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter + \arg ENET_PAUSE_CONDITION_STATUS: pause condition status + \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation + \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty + \arg ENET_TXFIFO_FULL: TxFIFO is full + \param[out] none + \retval value of the status users want to get +*/ +uint32_t enet_debug_status_get(uint32_t mac_debug) +{ + uint32_t temp_state = 0U; + + switch(mac_debug) { + case ENET_RX_ASYNCHRONOUS_FIFO_STATE: + temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_STATE: + temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); + break; + case ENET_MAC_TRANSMITTER_STATUS: + temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); + break; + case ENET_TXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); + break; + default: + if(RESET != (ENET_MAC_DBG & mac_debug)) { + temp_state = 0x1U; + } + break; + } + return temp_state; +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { + reg |= ENET_MDC_HCLK_DIV16; + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { + reg |= ENET_MDC_HCLK_DIV26; + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { + reg |= ENET_MDC_HCLK_DIV42; + } else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) { + reg |= ENET_MDC_HCLK_DIV62; + } else if((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV102; + } else { + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + + /* PHY reset complete */ + if(RESET == (phy_value & PHY_RESET)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0000 - 0x001F + \param[in] phy_reg: 0x0000 - 0x001F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if(ENET_PHY_WRITE == direction) { + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do { + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction) { + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state = ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if(RESET == temp) { + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically + this value must make sure to be less than configured pause time + only one parameter can be selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control + this value should always be less than active flow control value + only one parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control + only one parameter can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if(ENET_DMA_TX == direction) { + ENET_DMA_TPEN = 0U; + } else { + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(RESET == flush_state) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) + (uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(info_get) { + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + if(reval > 4U) { + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { + reval = reval + 4U; + } + } else { + reval = 0U; + } + + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_EXSV: extended status valid + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_TSV: timestamp valid + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if((uint32_t)RESET != (desc->status & desc_flag)) { + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \param[in] desc: the descriptor pointer which users want to configure + \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) + \param[out] none + \retval none +*/ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; + ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } + + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/*! + \brief get the bit of extended status flag in ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get the extended status flag + \param[in] desc_status: the extended status want to get + only one parameter can be selected which is shown as below + \arg ENET_RDES4_IPPLDT: IP frame payload type + \arg ENET_RDES4_IPHERR: IP frame header error + \arg ENET_RDES4_IPPLDERR: IP frame payload error + \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed + \arg ENET_RDES4_IPF4: IP frame in version 4 + \arg ENET_RDES4_IPF6: IP frame in version 6 + \arg ENET_RDES4_PTPMT: PTP message type + \arg ENET_RDES4_PTPOEF: PTP on ethernet frame + \arg ENET_RDES4_PTPVF: PTP version format + \param[out] none + \retval value of extended status +*/ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(desc_status) { + case ENET_RDES4_IPPLDT: + reval = GET_RDES4_IPPLDT(desc->extended_status); + break; + case ENET_RDES4_PTPMT: + reval = GET_RDES4_PTPMT(desc->extended_status); + break; + default: + if((uint32_t)RESET != (desc->extended_status & desc_status)) { + reval = 1U; + } else { + reval = 0U; + } + } + + return reval; +} + +/*! + \brief configure descriptor to work in enhanced mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_enhanced_mode(void) +{ + ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configuration each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + uint32_t timeout = 0U; + uint32_t rdes0_tsv_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + } + } else { + return ERROR; + } + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and + write to the RDES6 and RDES7 */ + do { + rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); + timeout++; + } while((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_RDES0_TSV flag */ + dma_current_rxdesc->status &= ~ENET_RDES0_TSV; + /* get the timestamp value of the received frame */ + timestamp[0] = dma_current_rxdesc->timestamp_low; + timestamp[1] = dma_current_rxdesc->timestamp_high; + } + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* Clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0; + uint32_t dma_tbu_flag, dma_tu_flag; + uint32_t tdes0_ttmss_flag; + uint32_t timeout = 0; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0; offset < length; offset++) { + (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* Clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->timestamp_low; + timestamp[1] = dma_current_txdesc->timestamp_high; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +#else + +/*! + \brief configure descriptor to work in normal mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_normal_mode(void) +{ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if(ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + } else { + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum + only one parameter can be selected which is shown as below + \arg ENET_MSC_PRESET_NONE: do not preset MSC counter + \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value + \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value + \param[out] none + \retval none +*/ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode) +{ + ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; + ENET_MSC_CTL |= (uint32_t)mode; +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: the function of PTP timestamp + only one parameter can be selected which is shown as below + \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp + \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp + \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp + \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode + \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode + \arg ENET_SNOOPING_PTP_VERSION_2: version 2 + \arg ENET_SNOOPING_PTP_VERSION_1: version 1 + \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + management and signaling message + \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message + \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch(func) { + case ENET_CKNT_ORDINARY: + case ENET_CKNT_BOUNDARY: + case ENET_CKNT_END_TO_END: + case ENET_CKNT_PEER_TO_PEER: + ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; + ENET_PTP_TSCTL |= (uint32_t)func; + break; + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + subsecond: 0x0 - 0x7FFF FFFF + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure the PPS output frequency + \param[in] freq: PPS output frequency + only one parameter can be selected which is shown as below + \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency + \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency + \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency + \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency + \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency + \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency + \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency + \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency + \param[out] none + \retval none +*/ +void enet_ptp_pps_output_frequency_config(uint32_t freq) +{ + ENET_PTP_PPSCTL = freq; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + __IO uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--) { + } +} +#endif /* USE_DELAY */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c new file mode 100644 index 0000000..0595672 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exmc.c @@ -0,0 +1,1252 @@ +/*! + \file gd32f4xx_exmc.c + \brief EXMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL_RESET ((uint32_t)0x000030DAU) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask */ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) + +/* EXMC bank3 register reset mask */ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFFFFFFFFU) + +/* EXMC SDRAM device register reset mask */ +#define SDRAM_DEVICE_SDCTL_RESET ((uint32_t)0x000002D0U) +#define SDRAM_DEVICE_SDTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define SDRAM_DEVICE_SDCMD_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDARI_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDSTAT_RESET ((uint32_t)0x00000000U) +#define SDRAM_DEVICE_SDRSCTL_RESET ((uint32_t)0x00000000U) + +/* EXMC bank0 SQPI-PSRAM register reset mask */ +#define BANK0_SQPI_SINIT_RESET ((uint32_t)0x18010000U) +#define BANK0_SQPI_SRCMD_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SWCMD_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SIDL_RESET ((uint32_t)0x00000000U) +#define BANK0_SQPI_SIDH_RESET ((uint32_t)0x00000000U) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define SDCTL_WPEN_OFFSET ((uint32_t)9U) +#define SDCTL_BRSTRD_OFFSET ((uint32_t)12U) + +#define SDTCFG_XSRD_OFFSET ((uint32_t)4U) +#define SDTCFG_RASD_OFFSET ((uint32_t)8U) +#define SDTCFG_ARFD_OFFSET ((uint32_t)12U) +#define SDTCFG_WRD_OFFSET ((uint32_t)16U) +#define SDTCFG_RPD_OFFSET ((uint32_t)20U) +#define SDTCFG_RCD_OFFSET ((uint32_t)24U) + +#define SDCMD_NARF_OFFSET ((uint32_t)5U) +#define SDCMD_MRC_OFFSET ((uint32_t)9U) + +#define SDARI_ARINTV_OFFSET ((uint32_t)1U) + +#define SDSTAT_STA0_OFFSET ((uint32_t)1U) +#define SDSTAT_STA1_OFFSET ((uint32_t)3U) + +#define SRCMD_RWAITCYCLE_OFFSET ((uint32_t)16U) +#define SWCMD_WWAITCYCLE_OFFSET ((uint32_t)16U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t exmc_norsram_region) +{ + /* reset the registers */ + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; + EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + /* configure the structure with default values */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* configure read/write timing */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* configure write timing, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 + write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE, EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW, EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B, EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM, EXMC_MEMORY_TYPE_PSRAM, EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU + write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WEN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX)); + + /* configure control bits */ + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + /* configure timing */ + sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* enable nor flash access */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* configure extended mode */ + if(ENABLE == exmc_norsram_init_struct->extended_mode) { + snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | + (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + } else { + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] exmc_nand_bank: select the bank of NAND + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t exmc_nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + /* configure the structure with default values */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief enable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize exmc_pccard_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the structure with default values */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFFU + holdtime: 0x01U~0xFFU + waittime: 0x02U~0x100U + setuptime: 0x01U~0x100U + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief deinitialize EXMC SDRAM device + \param[in] exmc_sdram_device: select the SRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0, 1) + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sdram_deinit(uint32_t exmc_sdram_device) +{ + /* reset SDRAM registers */ + EXMC_SDCTL(exmc_sdram_device) = SDRAM_DEVICE_SDCTL_RESET; + EXMC_SDTCFG(exmc_sdram_device) = SDRAM_DEVICE_SDTCFG_RESET; + EXMC_SDCMD = SDRAM_DEVICE_SDCMD_RESET; + EXMC_SDARI = SDRAM_DEVICE_SDARI_RESET; + EXMC_SDRSCTL = SDRAM_DEVICE_SDRSCTL_RESET; +} + +/*! + \brief initialize exmc_sdram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) +{ + /* configure the structure with default values */ + exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; + exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; + exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; + exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; + exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; + exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; + exmc_sdram_init_struct->write_protection = ENABLE; + exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; + exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; + + exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; + exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; + exmc_sdram_init_struct->timing->row_address_select_delay = 16U; + exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; + exmc_sdram_init_struct->timing->write_recovery_delay = 16U; + exmc_sdram_init_struct->timing->row_precharge_delay = 16U; + exmc_sdram_init_struct->timing->row_to_column_delay = 16U; +} + +/*! + \brief initialize EXMC SDRAM device + \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter + sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 + pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 + burst_read_switch: ENABLE or DISABLE + sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK + write_protection: ENABLE or DISABLE + cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 + internal_bank_number: EXMC_SDRAM_2_INTER_BANK,EXMC_SDRAM_4_INTER_BANK + data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B + row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 + column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 + timing: exmc_sdram_timing_parameter_struct set the time + row_to_column_delay: 1U~16U + row_precharge_delay: 1U~16U + write_recovery_delay: 1U~16U + auto_refresh_delay: 1U~16U + row_address_select_delay: 1U~16U + exit_selfrefresh_delay: 1U~16U + load_mode_register_delay: 1U~16U + \param[out] none + \retval none +*/ +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) +{ + uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; + + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + /* configure EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + } else { + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* some bits in the EXMC_SDCTL1 register are reserved */ + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); + + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); + + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; + EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; + + /* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + /* some bits in the EXMC_SDTCFG1 register are reserved */ + sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); + + sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET)); + + sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET)); + + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; + EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; + } +} + +/*! + \brief initialize exmc_sdram_struct_command_para_init with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer + \retval none +*/ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; +} + +/*! + \brief deinitialize exmc SQPIPSRAM + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_deinit(void) +{ + /* reset the registers */ + EXMC_SINIT = BANK0_SQPI_SINIT_RESET; + EXMC_SRCMD = BANK0_SQPI_SRCMD_RESET; + EXMC_SWCMD = BANK0_SQPI_SWCMD_RESET; + EXMC_SIDL = BANK0_SQPI_SIDL_RESET; + EXMC_SIDH = BANK0_SQPI_SIDH_RESET; +} + +/*! + \brief initialize exmc_sqpipsram_parameter_struct with the default values + \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) +{ + /* configure the structure with default values */ + exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; + exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; + exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; + exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; +} + +/*! + \brief initialize EXMC SQPIPSRAM + \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter + sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE + id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 + address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 + command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 + \param[out] none + \retval none +*/ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) +{ + /* initialize SQPI controller */ + EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; +} + +/*! + \brief configure consecutive clock + \param[in] clock_mode: specify when the clock is generated + only one parameter can be selected which is shown as below: + \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access + \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally + \param[out] none + \retval none +*/ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) +{ + if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) { + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; + } else { + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; + } +} + +/*! + \brief configure CRAM page size + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + only one parameter can be selected which is shown as below: + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes + \param[out] none + \retval none +*/ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) +{ + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; + } else { + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; + } +} + +/*! + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) +{ + return(EXMC_NECC(exmc_nand_bank)); +} + +/*! + \brief enable or disable read sample + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_enable(ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; + } else { + EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); + } +} + +/*! + \brief configure the delayed sample clock of read data + \param[in] delay_cell: SDRAM the delayed sample clock of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) + \param[in] extra_hclk: sample cycle of read data + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) +{ + uint32_t sdrsctl = 0U; + + /* reset the bits */ + sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); + /* set the bits */ + sdrsctl |= (uint32_t)(delay_cell | extra_hclk); + EXMC_SDRSCTL = sdrsctl; +} + +/*! + \brief configure the SDRAM memory command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + mode_register_content: + auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY + \param[out] none + \retval none +*/ +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure command register */ + EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | + (exmc_sdram_command_init_struct->bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content) << SDCMD_MRC_OFFSET)); +} + +/*! + \brief set auto-refresh interval + \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF + \param[out] none + \retval none +*/ +void exmc_sdram_refresh_count_set(uint32_t exmc_count) +{ + uint32_t sdari; + sdari = EXMC_SDARI & (~EXMC_SDARI_ARINTV); + EXMC_SDARI = sdari | (uint32_t)((exmc_count << SDARI_ARINTV_OFFSET) & EXMC_SDARI_ARINTV); +} + +/*! + \brief set the number of successive auto-refresh command + \param[in] exmc_number: the number of successive Auto-refresh cycles will be send, 1~15 + \param[out] none + \retval none +*/ +void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) +{ + uint32_t sdcmd; + sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); + EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; +} + +/*! + \brief configure the write protection function + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; + } else { + EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); + } + +} + +/*! + \brief get the status of SDRAM device0 or device1 + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[out] none + \retval the status of SDRAM device +*/ +uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) +{ + uint32_t sdstat = 0U; + + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); + } else { + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); + } + + return sdstat; +} + +/*! + \brief set the read command + \param[in] read_command_mode: configure SPI PSRAM read command mode + only one parameter can be selected which is shown as below: + \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode + \arg EXMC_SQPIPSRAM_READ_MODE_QPI: QPI mode + \param[in] read_wait_cycle: wait cycle number after address phase,0..15 + \param[in] read_command_code: read command for AHB read transfer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code) +{ + uint32_t srcmd; + + srcmd = (uint32_t) read_command_mode | + ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | + ((read_command_code & EXMC_SRCMD_RCMD)); + EXMC_SRCMD = srcmd; +} + +/*! + \brief set the write command + \param[in] write_command_mode: configure SPI PSRAM write command mode + only one parameter can be selected which is shown as below: + \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode + \arg EXMC_SQPIPSRAM_WRITE_MODE_QPI: QPI mode + \param[in] write_wait_cycle: wait cycle number after address phase,0..15 + \param[in] write_command_code: read command for AHB read transfer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code) +{ + uint32_t swcmd; + + swcmd = (uint32_t) write_command_mode | + ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | + ((write_command_code & EXMC_SWCMD_WCMD)); + EXMC_SWCMD = swcmd; +} + +/*! + \brief send SPI read ID command + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_read_id_command_send(void) +{ + EXMC_SRCMD |= EXMC_SRCMD_RDID; +} + +/*! + \brief send SPI special command which does not have address and data phase + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sqpipsram_write_cmd_send(void) +{ + EXMC_SWCMD |= EXMC_SWCMD_SC; +} + +/*! + \brief get the EXMC SPI ID low data + \param[in] none + \param[out] none + \retval the ID low data +*/ +uint32_t exmc_sqpipsram_low_id_get(void) +{ + return (EXMC_SIDL); +} + +/*! + \brief get the EXMC SPI ID high data + \param[in] none + \param[out] none + \retval the ID high data +*/ +uint32_t exmc_sqpipsram_high_id_get(void) +{ + return (EXMC_SIDH); +} + +/*! + \brief get the bit value of EXMC send write command bit or read ID command + \param[in] send_command_flag: the send command flag + only one parameter can be selected which is shown as below: + \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit + \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit + \param[out] none + \retval the new value of send command flag +*/ +FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) +{ + uint32_t flag = 0x00000000U; + + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag) { + flag = EXMC_SRCMD; + } else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag) { + flag = EXMC_SWCMD; + } else { + } + + if(flag & send_command_flag) { + /* flag is set */ + return SET; + } else { + /* flag is reset */ + return RESET; + } +} + +/*! + \brief enable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REIE; + } +} + +/*! + \brief disable EXMC interrupt + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~interrupt; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI &= ~EXMC_SDARI_REIE; + } +} + +/*! + \brief get EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag + \arg EXMC_SDRAM_FLAG_NREADY: not ready status + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) +{ + uint32_t status = 0x00000000U; + + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + } else { + /* SDRAM device0 or device1 */ + status = EXMC_SDSTAT; + } + + if((status & flag) != (uint32_t)flag) { + /* flag is reset */ + return RESET; + } else { + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag + \arg EXMC_SDRAM_FLAG_NREADY: not ready status + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~flag; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDSTAT &= ~flag; + } +} + +/*! + \brief get EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) +{ + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; + + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); + } else { + /* SDRAM device0 or device1 */ + status = EXMC_SDARI; + interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); + } + + interrupt_enable = (status & interrupt); + + if((interrupt_enable) && (interrupt_state)) { + /* interrupt flag is set */ + return SET; + } else { + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REC; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c new file mode 100644 index 0000000..93b4688 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_exti.c @@ -0,0 +1,256 @@ +/*! + \file gd32f4xx_exti.c + \brief EXTI driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x00000000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, \ + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c new file mode 100644 index 0000000..b1b48a9 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fmc.c @@ -0,0 +1,1048 @@ +/*! + \file gd32f4xx_fmc.c + \brief FMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_fmc.h" + +/*! + \brief set the FMC wait state counter + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: + \arg WS_WSCNT_0: FMC 0 wait + \arg WS_WSCNT_1: FMC 1 wait + \arg WS_WSCNT_2: FMC 2 wait + \arg WS_WSCNT_3: FMC 3 wait + \arg WS_WSCNT_4: FMC 4 wait + \arg WS_WSCNT_5: FMC 5 wait + \arg WS_WSCNT_6: FMC 6 wait + \arg WS_WSCNT_7: FMC 7 wait + \arg WS_WSCNT_8: FMC 8 wait + \arg WS_WSCNT_9: FMC 9 wait + \arg WS_WSCNT_10: FMC 10 wait + \arg WS_WSCNT_11: FMC 11 wait + \arg WS_WSCNT_12: FMC 12 wait + \arg WS_WSCNT_13: FMC 13 wait + \arg WS_WSCNT_14: FMC 14 wait + \arg WS_WSCNT_15: FMC 15 wait + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WC_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { + /* write the FMC key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit*/ + FMC_CTL |= FMC_CTL_LK; +} + +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) + +/*! + \brief FMC erase page + \param[in] page_addr: the page address to be erased. + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_page_erase(uint32_t page_addr) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* unlock page erase operation */ + FMC_PEKEY = UNLOCK_PE_KEY; + + /* start page erase */ + FMC_PECFG = FMC_PE_EN | page_addr; + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= FMC_CTL_SER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + FMC_PECFG &= ~FMC_PE_EN; + FMC_CTL &= ~FMC_CTL_SER; + } + + /* return the FMC state */ + return fmc_state; +} + +#endif + +/*! + \brief FMC erase sector + \param[in] fmc_sector: select the sector to erase + only one parameter can be selected which is shown as below: + \arg CTL_SECTOR_NUMBER_0: sector 0 + \arg CTL_SECTOR_NUMBER_1: sector 1 + \arg CTL_SECTOR_NUMBER_2: sector 2 + \arg CTL_SECTOR_NUMBER_3: sector 3 + \arg CTL_SECTOR_NUMBER_4: sector 4 + \arg CTL_SECTOR_NUMBER_5: sector 5 + \arg CTL_SECTOR_NUMBER_6: sector 6 + \arg CTL_SECTOR_NUMBER_7: sector 7 + \arg CTL_SECTOR_NUMBER_8: sector 8 + \arg CTL_SECTOR_NUMBER_9: sector 9 + \arg CTL_SECTOR_NUMBER_10: sector 10 + \arg CTL_SECTOR_NUMBER_11: sector 11 + \arg CTL_SECTOR_NUMBER_12: sector 12 + \arg CTL_SECTOR_NUMBER_13: sector 13 + \arg CTL_SECTOR_NUMBER_14: sector 14 + \arg CTL_SECTOR_NUMBER_15: sector 15 + \arg CTL_SECTOR_NUMBER_16: sector 16 + \arg CTL_SECTOR_NUMBER_17: sector 17 + \arg CTL_SECTOR_NUMBER_18: sector 18 + \arg CTL_SECTOR_NUMBER_19: sector 19 + \arg CTL_SECTOR_NUMBER_20: sector 20 + \arg CTL_SECTOR_NUMBER_21: sector 21 + \arg CTL_SECTOR_NUMBER_22: sector 22 + \arg CTL_SECTOR_NUMBER_23: sector 23 + \arg CTL_SECTOR_NUMBER_24: sector 24 + \arg CTL_SECTOR_NUMBER_25: sector 25 + \arg CTL_SECTOR_NUMBER_26: sector 26 + \arg CTL_SECTOR_NUMBER_27: sector 27 + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start sector erase */ + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= (FMC_CTL_SER | fmc_sector); + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the SER bit */ + FMC_CTL &= (~FMC_CTL_SER); + FMC_CTL &= ~FMC_CTL_SN; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief FMC erase whole chip + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start whole chip erase */ + FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bits */ + FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief FMC erase whole bank0 + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start FMC bank0 erase */ + FMC_CTL |= FMC_CTL_MER0; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER0 bit */ + FMC_CTL &= (~FMC_CTL_MER0); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief FMC erase whole bank1 + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start FMC bank1 erase */ + FMC_CTL |= FMC_CTL_MER1; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER1 bit */ + FMC_CTL &= (~FMC_CTL_MER1); + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_WORD; + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program(0x0000 - 0xFFFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_HALF_WORD; + FMC_CTL |= FMC_CTL_PG; + + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a byte at the corresponding address + \param[in] address: address to program + \param[in] data: byte to program(0x00 - 0xFF) + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL &= ~FMC_CTL_PSZ; + FMC_CTL |= CTL_PSZ_BYTE; + FMC_CTL |= FMC_CTL_PG; + + REG8(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)) { + /* write the FMC key */ + FMC_OBKEY = OB_UNLOCK_KEY0; + FMC_OBKEY = OB_UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OB_LK bit */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_LK; +} + +/*! + \brief send option byte change command + \param[in] none + \param[out] none + \retval none +*/ +void ob_start(void) +{ + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; +} + +/*! + \brief erase option byte + \param[in] none + \param[out] none + \retval none +*/ +void ob_erase(void) +{ + uint32_t reg, reg1; + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; + + if(FMC_READY == fmc_state) { + + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + /* reset the BOR level */ + reg |= FMC_OBCTL0_BOR_TH; + /* reset option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + /* reset option byte dbs value */ + reg &= ~FMC_OBCTL0_DBS; + + /* reset drp and wp value */ + reg |= FMC_OBCTL0_WP0; + reg &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + FMC_OBCTL0 = reg; + } +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector + \param[out] none + \retval SUCCESS or ERROR +*/ +ErrStatus ob_write_protection_enable(uint32_t ob_wp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; + } + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + reg0 &= (~((uint32_t)ob_wp << 16U)); + reg1 &= (~(ob_wp & 0xFFFF0000U)); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; + } +} + +/*! + \brief disable write protection + \param[in] ob_wp: specify sector to be write protected + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector + \param[out] none + \retval SUCCESS or ERROR +*/ +ErrStatus ob_write_protection_disable(uint32_t ob_wp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; + } + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + reg0 |= ((uint32_t)ob_wp << 16U); + reg1 |= (ob_wp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; + } +} + +/*! + \brief enable erase/program protection and D-bus read protection + \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector + \param[out] none + \retval none +*/ +void ob_drp_enable(uint32_t ob_drp) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; + uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; + uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + if(RESET == drp_state) { + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + } + reg0 |= ((uint32_t)ob_drp << 16U); + reg0 |= FMC_OBCTL0_DRP; + reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + } +} + +/*! + \brief disable erase/program protection and D-bus read protection + \param[in] none + \param[out] none + \retval none +*/ +void ob_drp_disable(void) +{ + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + if(((uint8_t)(reg0 >> 8U)) == (uint8_t)FMC_NSPC) { + /* security protection should be set as low level protection before disable D-BUS read protection */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_LSPC << 8U); + FMC_OBCTL0 = reg0; + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; + } + + /* it is necessary to disable the security protection at the same time when D-BUS read protection is disabled */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_NSPC << 8U); + reg0 |= FMC_OBCTL0_WP0; + reg0 &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg0; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + } +} + +/*! + \brief configure security protection level + \param[in] ob_spc: specify security protection level + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval none +*/ +void ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + uint32_t reg; + + reg = FMC_OBCTL0; + /* reset the OBCTL0_SPC, set according to ob_spc */ + reg &= ~FMC_OBCTL0_SPC; + reg |= ((uint32_t)ob_spc << 8U); + FMC_OBCTL0 = reg; + } +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + only one parameter can be selected which is shown as below: + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + only one parameter can be selected which is shown as below: + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + only one parameter can be selected which is shown as below: + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[out] none + \retval none +*/ +void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + uint32_t reg; + + reg = FMC_OBCTL0; + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg &= ~(FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + FMC_OBCTL0 = (reg | ob_fwdgt | ob_deepsleep | ob_stdby); + } +} + +/*! + \brief program the option byte BOR threshold value + \param[in] ob_bor_th: user option byte + only one parameter can be selected which is shown as below: + \arg OB_BOR_TH_VALUE3: BOR threshold value 3 + \arg OB_BOR_TH_VALUE2: BOR threshold value 2 + \arg OB_BOR_TH_VALUE1: BOR threshold value 1 + \arg OB_BOR_TH_OFF: no BOR function + \param[out] none + \retval none +*/ +void ob_user_bor_threshold(uint32_t ob_bor_th) +{ + uint32_t reg; + + reg = FMC_OBCTL0; + /* set the BOR level */ + reg &= ~FMC_OBCTL0_BOR_TH; + FMC_OBCTL0 = (reg | ob_bor_th); +} + +/*! + \brief configure the option byte boot bank value + \param[in] boot_mode: specifies the option byte boot bank value + only one parameter can be selected which is shown as below: + \arg OB_BB_DISABLE: boot from bank0 + \arg OB_BB_ENABLE: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval none +*/ +void ob_boot_mode_config(uint32_t boot_mode) +{ + uint32_t reg; + + reg = FMC_OBCTL0; + /* set option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + FMC_OBCTL0 = (reg | boot_mode); +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5U) & 0x07U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint16_t ob_write_protection0_get(void) +{ + /* return the FMC write protection option byte value */ + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint16_t ob_write_protection1_get(void) +{ + /* return the the FMC write protection option byte value */ + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); +} + +/*! + \brief get the FMC erase/program protection and D-bus read protection option bytes value + \param[in] none + \param[out] none + \retval the FMC erase/program protection and D-bus read protection option bytes value +*/ +uint16_t ob_drp0_get(void) +{ + /* return the FMC erase/program protection and D-bus read protection option bytes value */ + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } +} + +/*! + \brief get the FMC erase/program protection and D-bus read protection option bytes value + \param[in] none + \param[out] none + \retval the FMC erase/program protection and D-bus read protection option bytes value +*/ +uint16_t ob_drp1_get(void) +{ + /* return the FMC erase/program protection and D-bus read protection option bytes value */ + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } +} + +/*! + \brief get option byte security protection code value + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(((uint8_t)(FMC_OBCTL0 >> 8U)) != FMC_NSPC) { + spc_state = SET; + } else { + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief get the FMC option byte BOR threshold value + \param[in] none + \param[out] none + \retval the FMC BOR threshold value:OB_BOR_TH_OFF,OB_BOR_TH_VALUE1,OB_BOR_TH_VALUE2,OB_BOR_TH_VALUE3 +*/ +uint8_t ob_user_bor_threshold_get(void) +{ + /* return the FMC BOR threshold value */ + return (uint8_t)((uint8_t)FMC_OBCTL0 & 0x0CU); +} + +/*! + \brief get flag set or reset + \param[in] fmc_flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t fmc_flag) +{ + if(FMC_STAT & fmc_flag) { + return SET; + } + /* return the state of corresponding FMC flag */ + return RESET; +} + +/*! + \brief clear the FMC pending flag + \param[in] FMC_flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit + \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit + \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit + \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t fmc_flag) +{ + /* clear the flags */ + FMC_STAT = fmc_flag; +} + +/*! + \brief enable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t fmc_int) +{ + FMC_CTL |= fmc_int; +} + +/*! + \brief disable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: disable FMC end of program interrupt + \arg FMC_INT_ERR: disable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t fmc_int) +{ + FMC_CTL &= ~(uint32_t)fmc_int; +} + +/*! + \brief get FMC interrupt flag set or reset + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag) +{ + if(FMC_FLAG_END == fmc_int_flag) { + /* end of operation interrupt flag */ + if(FMC_CTL & FMC_CTL_ENDIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } else { + /* error interrupt flags */ + if(FMC_CTL & FMC_CTL_ERRIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } + + return RESET; +} + +/*! + \brief clear the FMC interrupt flag + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag) +{ + /* clear the interrupt flag */ + FMC_STAT = fmc_int_flag; +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error +*/ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + uint32_t temp_val = FMC_STAT; + + if(RESET != (temp_val & FMC_FLAG_BUSY)) { + fmc_state = FMC_BUSY; + } else if(RESET != (temp_val & FMC_FLAG_RDDERR)) { + fmc_state = FMC_RDDERR; + } else if(RESET != (temp_val & FMC_FLAG_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if(RESET != (temp_val & FMC_FLAG_PGMERR)) { + fmc_state = FMC_PGMERR; + } else if(RESET != (temp_val & FMC_FLAG_WPERR)) { + fmc_state = FMC_WPERR; + } else if(RESET != (temp_val & FMC_FLAG_OPERR)) { + fmc_state = FMC_OPERR; + } else { + fmc_state = FMC_READY; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] none + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(0U == timeout) { + fmc_state = FMC_TOERR; + } + + /* return the FMC state */ + return fmc_state; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c new file mode 100644 index 0000000..36af0dd --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_fwdgt.c @@ -0,0 +1,218 @@ +/*! + \file gd32f4xx_fwdgt.c + \brief FWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(RESET != (FWDGT_STAT & flag)){ + return SET; + } + + return RESET; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c new file mode 100644 index 0000000..ee490f9 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_gpio.c @@ -0,0 +1,434 @@ +/*! + \file gd32f4xx_gpio.c + \brief GPIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + case GPIOH: + /* reset GPIOH */ + rcu_periph_reset_enable(RCU_GPIOHRST); + rcu_periph_reset_disable(RCU_GPIOHRST); + break; + case GPIOI: + /* reset GPIOI */ + rcu_periph_reset_enable(RCU_GPIOIRST); + rcu_periph_reset_disable(RCU_GPIOIRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] mode: GPIO pin mode + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: GPIO pin with pull-up or pull-down resistor + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] otype: GPIO pin output mode + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: GPIO pin output max speed + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_25MHZ: output max speed 25MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeedr; + + if(GPIO_OTYPE_OD == otype) { + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + } else { + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeedr = GPIO_OSPD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin output speed bits */ + ospeedr &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeedr |= GPIO_OSPEED_SET(i, speed); + } + } + GPIO_OSPD(gpio_periph) = ospeedr; +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of GPIO pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval input status of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of GPIO pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none + \retval output status of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] alt_func_num: GPIO pin af function + \arg GPIO_AF_0: SYSTEM + \arg GPIO_AF_1: TIMER0, TIMER1 + \arg GPIO_AF_2: TIMER2, TIMER3, TIMER4 + \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 + \arg GPIO_AF_4: I2C0, I2C1, I2C2 + \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 + \arg GPIO_AF_6: SPI2, SPI3, SPI4 + \arg GPIO_AF_7: USART0, USART1, USART2, SPI1, SPI2 + \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13, I2C1, I2C2, CTC + \arg GPIO_AF_10: USB_FS, USB_HS + \arg GPIO_AF_11: ENET + \arg GPIO_AF_12: EXMC, SDIO, USB_HS + \arg GPIO_AF_13: DCI + \arg GPIO_AF_14: TLI + \arg GPIO_AF_15: EVENTOUT + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i, alt_func_num); + } + } + + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c new file mode 100644 index 0000000..e2103b6 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_hw.c @@ -0,0 +1,313 @@ +/*! + \file gd32f4xx_hw.c + \brief USB hardware configuration for GD32F4xx + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" + +#define TIM_MSEC_DELAY 0x01U +#define TIM_USEC_DELAY 0x02U + +__IO uint32_t delay_time = 0U; +__IO uint16_t timer_prescaler = 5U; + +/* local function prototypes ('static') */ +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ +#ifdef USE_USB_FS + rcu_pll48m_clock_config(RCU_PLL48MSRC_PLLQ); + rcu_ck48m_clock_config(RCU_CK48MSRC_PLL48M); + + rcu_periph_clock_enable(RCU_USBFS); +#elif defined(USE_USB_HS) + #ifdef USE_EMBEDDED_PHY + rcu_pll48m_clock_config(RCU_PLL48MSRC_PLLQ); + rcu_ck48m_clock_config(RCU_CK48MSRC_PLL48M); + #elif defined(USE_ULPI_PHY) + rcu_periph_clock_enable(RCU_USBHSULPI); + #endif /* USE_EMBEDDED_PHY */ + + rcu_periph_clock_enable(RCU_USBHS); +#endif /* USB_USBFS */ +} + +/*! + \brief configure USB data line GPIO + \param[in] none + \param[out] none + \retval none +*/ +void usb_gpio_config(void) +{ + rcu_periph_clock_enable(RCU_SYSCFG); + +#ifdef USE_USB_FS + + rcu_periph_clock_enable(RCU_GPIOA); + + /* USBFS_DM(PA11) and USBFS_DP(PA12) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11 | GPIO_PIN_12); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11 | GPIO_PIN_12); + + gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_11 | GPIO_PIN_12); + +#elif defined(USE_USB_HS) + + #ifdef USE_ULPI_PHY + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOH); + rcu_periph_clock_enable(RCU_GPIOI); + + /* ULPI_STP(PC0) GPIO pin configuration */ + gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_0); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_0); + + /* ULPI_CK(PA5) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_5); + + /* ULPI_NXT(PH4) GPIO pin configuration */ + gpio_mode_set(GPIOH, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); + gpio_output_options_set(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_4); + + /* ULPI_DIR(PI11) GPIO pin configuration */ + gpio_mode_set(GPIOI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); + gpio_output_options_set(GPIOI, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11); + + /* ULPI_D1(PB0), ULPI_D2(PB1), ULPI_D3(PB10), ULPI_D4(PB11) \ + ULPI_D5(PB12), ULPI_D6(PB13) and ULPI_D7(PB5) GPIO pin configuration */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, \ + GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, \ + GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + + /* ULPI_D0(PA3) GPIO pin configuration */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_3); + + gpio_af_set(GPIOC, GPIO_AF_10, GPIO_PIN_0); + gpio_af_set(GPIOH, GPIO_AF_10, GPIO_PIN_4); + gpio_af_set(GPIOI, GPIO_AF_10, GPIO_PIN_11); + gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_5 | GPIO_PIN_3); + gpio_af_set(GPIOB, GPIO_AF_10, GPIO_PIN_5 | GPIO_PIN_13 | GPIO_PIN_12 |\ + GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_1 | GPIO_PIN_0); + #elif defined(USE_EMBEDDED_PHY) + rcu_periph_clock_enable(RCU_GPIOB); + + /* USBHS_DM(PB14) and USBHS_DP(PB15) GPIO pin configuration */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_14 | GPIO_PIN_15); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_14 | GPIO_PIN_15); + gpio_af_set(GPIOB, GPIO_AF_12, GPIO_PIN_14 | GPIO_PIN_15); + #endif /* USE_ULPI_PHY */ + +#endif /* USE_USBFS */ +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ +// nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + +#ifdef USE_USB_FS + nvic_irq_enable((uint8_t)USBFS_IRQn, 2U, 0U); + + #if USBFS_LOW_POWER + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + nvic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 0U, 0U); + #endif /* USBFS_LOW_POWER */ +#elif defined(USE_USB_HS) + nvic_irq_enable((uint8_t)USBHS_IRQn, 2U, 0U); + + #if USBHS_LOW_POWER + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_20); + exti_init(EXTI_20, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_20); + + nvic_irq_enable((uint8_t)USBHS_WKUP_IRQn, 0U, 0U); + #endif /* USBHS_LOW_POWER */ +#endif /* USE_USB_FS */ + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + nvic_irq_enable(USBHS_EP1_Out_IRQn, 1, 0); + nvic_irq_enable(USBHS_EP1_In_IRQn, 1, 0); +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + /* configure the priority group to 2 bits */ + //nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + + /* enable the TIMER6 global interrupt */ + nvic_irq_enable((uint8_t)TIMER6_IRQn, 1U, 0U); + + rcu_periph_clock_enable(RCU_TIMER6); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milliseconds + \param[in] msec: value of delay required in milliseconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief timer base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_interrupt_flag_get(TIMER6, TIMER_INT_FLAG_UP)){ + timer_interrupt_flag_clear(TIMER6, TIMER_INT_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER6); + } + } +} + +/*! + \brief delay routine based on TIMER6 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = milliseconds / microseconds + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER6); +} + +/*! + \brief configures TIMER for delay routine based on Timer2 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_basestructure; + + timer_prescaler = ((rcu_clock_freq_get(CK_APB1)/1000000*2)/12) - 1; + + timer_disable(TIMER6); + timer_interrupt_disable(TIMER6, TIMER_INT_UP); + + if(TIM_USEC_DELAY == unit) { + timer_basestructure.period = 11U; + } else if(TIM_MSEC_DELAY == unit) { + timer_basestructure.period = 11999U; + } else { + /* no operation */ + } + + timer_basestructure.prescaler = timer_prescaler; + timer_basestructure.alignedmode = TIMER_COUNTER_EDGE; + timer_basestructure.counterdirection = TIMER_COUNTER_UP; + timer_basestructure.clockdivision = TIMER_CKDIV_DIV1; + timer_basestructure.repetitioncounter = 0U; + + timer_init(TIMER6, &timer_basestructure); + + timer_interrupt_flag_clear(TIMER6, TIMER_INT_FLAG_UP); + + timer_auto_reload_shadow_enable(TIMER6); + + /* TIMER6 interrupt enable */ + timer_interrupt_enable(TIMER6, TIMER_INT_UP); + + /* TIMER6 enable counter */ + timer_enable(TIMER6); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c new file mode 100644 index 0000000..3b2adfd --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_i2c.c @@ -0,0 +1,840 @@ +/*! + \file gd32f4xx_i2c.c + \brief I2C driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + case I2C2: + /* reset I2C2 */ + rcu_periph_reset_enable(RCU_I2C2RST); + rcu_periph_reset_disable(RCU_I2C2RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + \param[in] dutycyc: duty cycle in fast mode + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if(400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief select SMBus type + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + uint32_t ctl = 0U; + /* configure I2C POAP position */ + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief configure I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode + \param[out] none + \retval none +*/ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure software reset of I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C PEC calculation + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pecstate: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value + \param[out] none + \retval none +*/ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); +} + +/*! + \brief configure I2C alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* configure smubus alert through SMBA pin */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C ARP protocol in SMBus + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief disable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_disable(uint32_t i2c_periph) +{ + I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; +} + +/*! + \brief enable analog noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_analog_noise_filter_enable(uint32_t i2c_periph) +{ + I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); +} + +/*! + \brief configure digital noise filter + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] dfilterpara: refer to i2c_digital_filter_enum + only one parameter can be selected which is shown as below: + \arg I2C_DF_DISABLE: disable digital noise filter + \arg I2C_DF_1PCLK: enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 + \arg I2C_DF_2PCLK: enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 + \arg I2C_DF_3PCLK: enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 + \arg I2C_DF_4PCLK: enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 + \arg I2C_DF_5PCLK: enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 + \arg I2C_DF_6PCLK: enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 + \arg I2C_DF_7PCLK: enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 + \arg I2C_DF_8PCLK: enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 + \arg I2C_DF_9PCLK: enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 + \arg I2C_DF_10PCLK: enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 + \arg I2C_DF_11CLK: enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 + \arg I2C_DF_12CLK: enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 + \arg I2C_DF_13PCLK: enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 + \arg I2C_DF_14PCLK: enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 + \arg I2C_DF_15PCLK: enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 + \param[out] none + \retval none +*/ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara) +{ + I2C_FCTL(i2c_periph) |= dfilterpara; +} + +/*! + \brief enable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; +} + +/*! + \brief disable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); +} + +/*! + \brief enable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; +} + +/*! + \brief disable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); +} + +/*! + \brief get I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition sent out in master mode + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief get I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { + intenable = 1U; + } else { + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c new file mode 100644 index 0000000..02e8e85 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_ipa.c @@ -0,0 +1,639 @@ +/*! + \file gd32f4xx_ipa.c + \brief IPA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_ipa.h" + +#define IPA_DEFAULT_VALUE 0x00000000U + +/*! + \brief deinitialize IPA registers + \param[in] none + \param[out] none + \retval none +*/ +void ipa_deinit(void) +{ + rcu_periph_reset_enable(RCU_IPARST); + rcu_periph_reset_disable(RCU_IPARST); +} + +/*! + \brief enable IPA transfer + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_enable(void) +{ + IPA_CTL |= IPA_CTL_TEN; +} + +/*! + \brief enable IPA transfer hang up + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_hangup_enable(void) +{ + IPA_CTL |= IPA_CTL_THU; +} + +/*! + \brief disable IPA transfer hang up + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_hangup_disable(void) +{ + IPA_CTL &= ~(IPA_CTL_THU); +} + +/*! + \brief enable IPA transfer stop + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_stop_enable(void) +{ + IPA_CTL |= IPA_CTL_TST; +} + +/*! + \brief disable IPA transfer stop + \param[in] none + \param[out] none + \retval none +*/ +void ipa_transfer_stop_disable(void) +{ + IPA_CTL &= ~(IPA_CTL_TST); +} +/*! + \brief enable IPA foreground LUT loading + \param[in] none + \param[out] none + \retval none +*/ +void ipa_foreground_lut_loading_enable(void) +{ + IPA_FPCTL |= IPA_FPCTL_FLLEN; +} + +/*! + \brief enable IPA background LUT loading + \param[in] none + \param[out] none + \retval none +*/ +void ipa_background_lut_loading_enable(void) +{ + IPA_BPCTL |= IPA_BPCTL_BLLEN; +} + +/*! + \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled + \param[in] pfcm: pixel format convert mode + only one parameter can be selected which is shown as below: + \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert + \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert + \arg IPA_FGBGTODE: blending foreground and background memory to destination memory + \arg IPA_FILL_UP_DE: fill up destination memory with specific color + \param[out] none + \retval none +*/ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm) +{ + IPA_CTL &= ~(IPA_CTL_PFCM); + IPA_CTL |= pfcm; +} + +/*! + \brief initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined + \param[in] none + \param[out] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \retval none +*/ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct) +{ + /* initialize the struct parameters with default values */ + foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; + foreground_struct->foreground_lineoff = IPA_DEFAULT_VALUE; + foreground_struct->foreground_prealpha = IPA_DEFAULT_VALUE; + foreground_struct->foreground_alpha_algorithm = IPA_FG_ALPHA_MODE_0; + foreground_struct->foreground_pf = FOREGROUND_PPF_ARGB8888; + foreground_struct->foreground_prered = IPA_DEFAULT_VALUE; + foreground_struct->foreground_pregreen = IPA_DEFAULT_VALUE; + foreground_struct->foreground_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize foreground parameters + \param[in] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \param[out] none + \retval none +*/ +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* foreground memory base address configuration */ + IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); + IPA_FMADDR = foreground_struct->foreground_memaddr; + /* foreground line offset configuration */ + IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); + IPA_FLOFF = foreground_struct->foreground_lineoff; + /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV | IPA_FPCTL_FAVCA | IPA_FPCTL_FPF); + IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U); + IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; + IPA_FPCTL |= foreground_struct->foreground_pf; + /* foreground pre-defined red green blue configuration */ + IPA_FPV &= ~(IPA_FPV_FPDRV | IPA_FPV_FPDGV | IPA_FPV_FPDBV); + IPA_FPV |= ((foreground_struct->foreground_prered << 16U) | (foreground_struct->foreground_pregreen << 8U) + | (foreground_struct->foreground_preblue)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined + \param[in] none + \param[out] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_BG_ALPHA_MODE_1,IPA_BG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \retval none +*/ +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct) +{ + /* initialize the struct parameters with default values */ + background_struct->background_memaddr = IPA_DEFAULT_VALUE; + background_struct->background_lineoff = IPA_DEFAULT_VALUE; + background_struct->background_prealpha = IPA_DEFAULT_VALUE; + background_struct->background_alpha_algorithm = IPA_BG_ALPHA_MODE_0; + background_struct->background_pf = BACKGROUND_PPF_ARGB8888; + background_struct->background_prered = IPA_DEFAULT_VALUE; + background_struct->background_pregreen = IPA_DEFAULT_VALUE; + background_struct->background_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize background parameters + \param[in] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \param[out] none + \retval none +*/ +void ipa_background_init(ipa_background_parameter_struct *background_struct) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* background memory base address configuration */ + IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); + IPA_BMADDR = background_struct->background_memaddr; + /* background line offset configuration */ + IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); + IPA_BLOFF = background_struct->background_lineoff; + /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF); + IPA_BPCTL |= (background_struct->background_prealpha << 24U); + IPA_BPCTL |= background_struct->background_alpha_algorithm; + IPA_BPCTL |= background_struct->background_pf; + /* background pre-defined red green blue configuration */ + IPA_BPV &= ~(IPA_BPV_BPDRV | IPA_BPV_BPDGV | IPA_BPV_BPDBV); + IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U) + | (background_struct->background_preblue)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined + \param[in] none + \param[out] destination_struct: the data needed to initialize destination parameter + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \retval none +*/ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct) +{ + /* initialize the struct parameters with default values */ + destination_struct->destination_pf = IPA_DPF_ARGB8888; + destination_struct->destination_lineoff = IPA_DEFAULT_VALUE; + destination_struct->destination_prealpha = IPA_DEFAULT_VALUE; + destination_struct->destination_prered = IPA_DEFAULT_VALUE; + destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; + destination_struct->destination_preblue = IPA_DEFAULT_VALUE; + destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; + destination_struct->image_width = IPA_DEFAULT_VALUE; + destination_struct->image_height = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize destination parameters + \param[in] destination_struct: the data needed to initialize destination parameters + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \param[out] none + \retval none +*/ +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct) +{ + uint32_t destination_pixelformat; + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + + /* destination pixel format configuration */ + IPA_DPCTL &= ~(IPA_DPCTL_DPF); + IPA_DPCTL = destination_struct->destination_pf; + destination_pixelformat = destination_struct->destination_pf; + /* destination pixel format ARGB8888 */ + switch(destination_pixelformat) { + case IPA_DPF_ARGB8888: + IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U) + | (destination_struct->destination_prealpha << 24U)); + break; + /* destination pixel format RGB888 */ + case IPA_DPF_RGB888: + IPA_DPV &= ~(IPA_DPV_DPDBV_1 | (IPA_DPV_DPDGV_1) | (IPA_DPV_DPDRV_1)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U)); + break; + /* destination pixel format RGB565 */ + case IPA_DPF_RGB565: + IPA_DPV &= ~(IPA_DPV_DPDBV_2 | (IPA_DPV_DPDGV_2) | (IPA_DPV_DPDRV_2)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 11U)); + break; + /* destination pixel format ARGB1555 */ + case IPA_DPF_ARGB1555: + IPA_DPV &= ~(IPA_DPV_DPDBV_3 | (IPA_DPV_DPDGV_3) | (IPA_DPV_DPDRV_3) | (IPA_DPV_DPDAV_3)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 10U) + | (destination_struct->destination_prealpha << 15U)); + break; + /* destination pixel format ARGB4444 */ + case IPA_DPF_ARGB4444: + IPA_DPV &= ~(IPA_DPV_DPDBV_4 | (IPA_DPV_DPDGV_4) | (IPA_DPV_DPDRV_4) | (IPA_DPV_DPDAV_4)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 4U) + | (destination_struct->destination_prered << 8U) + | (destination_struct->destination_prealpha << 12U)); + break; + default: + break; + } + /* destination memory base address configuration */ + IPA_DMADDR &= ~(IPA_DMADDR_DMADDR); + IPA_DMADDR = destination_struct->destination_memaddr; + /* destination line offset configuration */ + IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); + IPA_DLOFF = destination_struct->destination_lineoff; + /* image size configuration */ + IPA_IMS &= ~(IPA_IMS_HEIGHT | IPA_IMS_WIDTH); + IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height)); + + if(SET == tempflag) { + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize IPA foreground LUT parameters + \param[in] fg_lut_num: foreground LUT number of pixel + \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] fg_lut_addr: foreground LUT memory base address + \param[out] none + \retval none +*/ +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)) { + tempflag = SET; + /* reset the FLLEN in order to configure the following bits */ + IPA_FPCTL &= ~IPA_FPCTL_FLLEN; + } + + /* foreground LUT number of pixel configuration */ + IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U); + /* foreground LUT pixel format configuration */ + if(IPA_LUT_PF_RGB888 == fg_lut_pf) { + IPA_FPCTL |= IPA_FPCTL_FLPF; + } else { + IPA_FPCTL &= ~(IPA_FPCTL_FLPF); + } + /* foreground LUT memory base address configuration */ + IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); + IPA_FLMADDR = fg_lut_addr; + + if(SET == tempflag) { + /* restore the state of FLLEN */ + IPA_FPCTL |= IPA_FPCTL_FLLEN; + } +} + +/*! + \brief initialize IPA background LUT parameters + \param[in] bg_lut_num: background LUT number of pixel + \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] bg_lut_addr: background LUT memory base address + \param[out] none + \retval none +*/ +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) +{ + FlagStatus tempflag = RESET; + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)) { + tempflag = SET; + /* reset the BLLEN in order to configure the following bits */ + IPA_BPCTL &= ~IPA_BPCTL_BLLEN; + } + + /* background LUT number of pixel configuration */ + IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U); + /* background LUT pixel format configuration */ + if(IPA_LUT_PF_RGB888 == bg_lut_pf) { + IPA_BPCTL |= IPA_BPCTL_BLPF; + } else { + IPA_BPCTL &= ~(IPA_BPCTL_BLPF); + } + /* background LUT memory base address configuration */ + IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); + IPA_BLMADDR = bg_lut_addr; + + if(SET == tempflag) { + /* restore the state of BLLEN */ + IPA_BPCTL |= IPA_BPCTL_BLLEN; + } +} + +/*! + \brief configure IPA line mark + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void ipa_line_mark_config(uint16_t line_num) +{ + IPA_LM &= ~(IPA_LM_LM); + IPA_LM = line_num; +} + +/*! + \brief inter-timer enable or disable + \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE + \param[out] none + \retval none +*/ +void ipa_inter_timer_config(uint8_t timer_cfg) +{ + if(IPA_INTER_TIMER_ENABLE == timer_cfg) { + IPA_ITCTL |= IPA_ITCTL_ITEN; + } else { + IPA_ITCTL &= ~(IPA_ITCTL_ITEN); + } +} + +/*! + \brief configure the number of clock cycles interval + \param[in] clk_num: the number of clock cycles + \param[out] none + \retval none +*/ +void ipa_interval_clock_num_config(uint8_t clk_num) +{ + /* NCCI[7:0] bits have no meaning if ITEN is '0' */ + IPA_ITCTL &= ~(IPA_ITCTL_NCCI); + IPA_ITCTL |= ((uint32_t)clk_num << 8U); +} + +/*! + \brief get IPA flag status in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_flag_get(uint32_t flag) +{ + if(RESET != (IPA_INTF & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear IPA flag in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +void ipa_flag_clear(uint32_t flag) +{ + IPA_INTC |= (flag); +} + +/*! + \brief enable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_enable(uint32_t int_flag) +{ + IPA_CTL |= (int_flag); +} + +/*! + \brief disable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt + \param[out] none + \retval none +*/ +void ipa_interrupt_disable(uint32_t int_flag) +{ + IPA_CTL &= ~(int_flag); +} + +/*! + \brief get IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) +{ + if(0U != (IPA_INTF & int_flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +void ipa_interrupt_flag_clear(uint32_t int_flag) +{ + IPA_INTC |= (int_flag); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c new file mode 100644 index 0000000..731d4fc --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_iref.c @@ -0,0 +1,127 @@ +/*! + \file gd32f4xx_iref.c + \brief IREF driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_iref.h" + +/*! + \brief deinitialize IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_deinit(void) +{ + rcu_periph_reset_enable(RCU_IREFRST); + rcu_periph_reset_disable(RCU_IREFRST); +} + +/*! + \brief enable IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_enable(void) +{ + IREF_CTL |= IREF_CTL_CREN; +} + +/*! + \brief disable IREF + \param[in] none + \param[out] none + \retval none +*/ +void iref_disable(void) +{ + IREF_CTL &= ~IREF_CTL_CREN; +} + +/*! + \brief set IREF mode + \param[in] step + \arg IREF_MODE_LOW_POWER: 1uA step + \arg IREF_MODE_HIGH_CURRENT: 8uA step + \param[out] none + \retval none +*/ +void iref_mode_set(uint32_t step) +{ + IREF_CTL &= ~IREF_CTL_SSEL; + IREF_CTL |= step; +} + +/*! + \brief set IREF precision_trim_value + \param[in] precisiontrim + \arg IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)% + \param[out] none + \retval none +*/ +void iref_precision_trim_value_set(uint32_t precisiontrim) +{ + IREF_CTL &= ~IREF_CTL_CPT; + IREF_CTL |= precisiontrim; +} + +/*! + \brief set IREF sink mode + \param[in] sinkmode + \arg IREF_SOURCE_CURRENT : source current. + \arg IREF_SINK_CURRENT: sink current + \param[out] none + \retval none +*/ +void iref_sink_set(uint32_t sinkmode) +{ + IREF_CTL &= ~IREF_CTL_SCMOD; + IREF_CTL |= sinkmode; +} + +/*! + \brief set IREF step data + \param[in] stepdata + \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x + \param[out] none + \retval none +*/ + +void iref_step_data_config(uint32_t stepdata) +{ + IREF_CTL &= ~IREF_CTL_CSDT; + IREF_CTL |= stepdata; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c new file mode 100644 index 0000000..3198d4a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_misc.c @@ -0,0 +1,175 @@ +/*! + \file gd32f4xx_misc.c + \brief MISC driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + /* use the priority group value to get the temp_pre and the temp_sub */ + if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) { + temp_pre = 0U; + temp_sub = 0x4U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) { + temp_pre = 1U; + temp_sub = 0x3U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) { + temp_pre = 2U; + temp_sub = 0x2U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) { + temp_pre = 3U; + temp_sub = 0x1U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) { + temp_pre = 4U; + temp_sub = 0x0U; + } else { + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + } + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } else { + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c new file mode 100644 index 0000000..229a557 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_pmu.c @@ -0,0 +1,412 @@ +/*! + \file gd32f4xx_pmu.c + \brief PMU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_pmu.h" +#include "core_cm4.h" + +/*! + \brief reset PMU registers + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to pmu_lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL + \param[in] ldo_output: + \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode + \arg PMU_LDOVS_MID: mid-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: high-driver mode disable in deep-sleep mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] highdr_switch: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag set */ + while(SET != pmu_flag_get(PMU_FLAG_HDRF)) { + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief enable low-driver mode in deep-sleep + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_LDEN; +} + +/*! + \brief disable low-driver mode in deep-sleep + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief in deep-sleep mode, driver mode when use low power LDO + \param[in] mode: + \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief in deep-sleep mode, driver mode when use normal power LDO + \param[in] mode: + \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work in sleep mode + \param[in] sleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __WFE(); + } +} + +/*! + \brief PMU work in deep-sleep mode + \param[in] ldo + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deep-sleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode + \param[in] deepsleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) +{ + static uint32_t reg_snap[4]; + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* configure low drive mode in deep-sleep mode */ + if(PMU_LOWDRIVER_ENABLE == lowdrive) { + if(PMU_LDO_NORMAL == ldo) { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP); + } else { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP); + } + } + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFF7FF831U; + REG32(0xE000E184U) = 0XBFFFF8FFU; + REG32(0xE000E188U) = 0xFFFFEFFFU; + + /* select WFI or WFE command to enter deep-sleep mode */ + if(WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + + REG32(0xE000E010U) = reg_snap[0]; + REG32(0xE000E100U) = reg_snap[1]; + REG32(0xE000E104U) = reg_snap[2]; + REG32(0xE000E108U) = reg_snap[3]; + + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work in standby mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_to_standbymode(void) +{ + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); +} + +/*! + \brief enable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} + +/*! + \brief backup SRAM LDO on + \param[in] bkp_ldo: + \arg PMU_BLDOON_OFF: backup SRAM LDO closed + \arg PMU_BLDOON_ON: open the backup SRAM LDO + \param[out] none + \retval none +*/ +void pmu_backup_ldo_config(uint32_t bkp_ldo) +{ + PMU_CS &= ~PMU_CS_BLDOON; + PMU_CS |= bkp_ldo; +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag) +{ + switch(flag) { + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c new file mode 100644 index 0000000..6e8dddd --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rcu.c @@ -0,0 +1,1332 @@ +/*! + \file gd32f4xx_rcu.c + \brief RCU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_rcu.h" + +/* define clock source */ +#define SEL_IRC16M ((uint16_t)0U) /* IRC16M is selected as CK_SYS */ +#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ +#define SEL_PLLP ((uint16_t)2U) /* PLLP is selected as CK_SYS */ +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000fffffU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0fffffffU) + +/* RCU IRC16M adjust value mask and offset*/ +#define RCU_IRC16M_ADJUST_MASK ((uint8_t)0x1FU) +#define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + rcu_osci_stab_wait(RCU_IRC16M); + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN + | RCU_CTL_PLLSAIEN); + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + /* reset CFG0 register */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | + RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); + /* reset PLL register */ + RCU_PLL = 0x24003010U; + /* reset PLLI2S register */ + RCU_PLLI2S = 0x24003000U; + /* reset PLLSAI register */ + RCU_PLLSAI = 0x24003010U; + /* reset INT register */ + RCU_INT = 0x00000000U; + /* reset CFG1 register */ + RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC: CRC clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_TCMSRAM: TCMSRAM clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_IPA: IPA clock + \arg RCU_ENET: ENET clock + \arg RCU_ENETTX: ENETTX clock + \arg RCU_ENETRX: ENETRX clock + \arg RCU_ENETPTP: ENETPTP clock + \arg RCU_USBHS: USBHS clock + \arg RCU_USBHSULPI: USBHSULPI clock + \arg RCU_DCI: DCI clock + \arg RCU_TRNG: TRNG clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock + \arg RCU_SDIO: SDIO clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_TLI: TLI clock + \arg RCU_CTC: CTC clock + \arg RCU_IREF: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC: CRC clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_TCMSRAM: TCMSRAM clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_IPA: IPA clock + \arg RCU_ENET: ENET clock + \arg RCU_ENETTX: ENETTX clock + \arg RCU_ENETRX: ENETRX clock + \arg RCU_ENETPTP: ENETPTP clock + \arg RCU_USBHS: USBHS clock + \arg RCU_USBHSULPI: USBHSULPI clock + \arg RCU_DCI: DCI clock + \arg RCU_TRNG: TRNG clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock + \arg RCU_SDIO: SDIO clock + \arg RCU_SYSCFG: SYSCFG clock + \arg RCU_TLI: TLI clock + \arg RCU_CTC: CTC clock + \arg RCU_IREF: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC_SLP: CRC clock + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM0_SLP: SRAM0 clock + \arg RCU_SRAM1_SLP: SRAM1 clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_SRAM2_SLP: SRAM2 clock + \arg RCU_DMAx_SLP (x=0,1): DMA clock + \arg RCU_IPA_SLP: IPA clock + \arg RCU_ENET_SLP: ENET clock + \arg RCU_ENETTX_SLP: ENETTX clock + \arg RCU_ENETRX_SLP: ENETRX clock + \arg RCU_ENETPTP_SLP: ENETPTP clock + \arg RCU_USBHS_SLP: USBHS clock + \arg RCU_USBHSULPI_SLP: USBHSULPI clock + \arg RCU_DCI_SLP: DCI clock + \arg RCU_TRNG_SLP: TRNG clock + \arg RCU_USBFS_SLP: USBFS clock + \arg RCU_EXMC_SLP: EXMC clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT_SLP: WWDGT clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock + \arg RCU_PMU_SLP: PMU clock + \arg RCU_DAC_SLP: DAC clock + \arg RCU_RTC_SLP: RTC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock + \arg RCU_SDIO_SLP: SDIO clock + \arg RCU_SYSCFG_SLP: SYSCFG clock + \arg RCU_TLI_SLP: TLI clock + \arg RCU_CTC_SLP: CTC clock + \arg RCU_IREF_SLP: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock + \arg RCU_CRC_SLP: CRC clock + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM0_SLP: SRAM0 clock + \arg RCU_SRAM1_SLP: SRAM1 clock + \arg RCU_BKPSRAM: BKPSRAM clock + \arg RCU_SRAM2_SLP: SRAM2 clock + \arg RCU_DMAx_SLP (x=0,1): DMA clock + \arg RCU_IPA_SLP: IPA clock + \arg RCU_ENET_SLP: ENET clock + \arg RCU_ENETTX_SLP: ENETTX clock + \arg RCU_ENETRX_SLP: ENETRX clock + \arg RCU_ENETPTP_SLP: ENETPTP clock + \arg RCU_USBHS_SLP: USBHS clock + \arg RCU_USBHSULPI_SLP: USBHSULPI clock + \arg RCU_DCI_SLP: DCI clock + \arg RCU_TRNG_SLP: TRNG clock + \arg RCU_USBFS_SLP: USBFS clock + \arg RCU_EXMC_SLP: EXMC clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock + \arg RCU_WWDGT_SLP: WWDGT clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock + \arg RCU_PMU_SLP: PMU clock + \arg RCU_DAC_SLP: DAC clock + \arg RCU_RTC_SLP: RTC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock + \arg RCU_SDIO_SLP: SDIO clock + \arg RCU_SYSCFG_SLP: SYSCFG clock + \arg RCU_TLI_SLP: TLI clock + \arg RCU_CTC_SLP: CTC clock + \arg RCU_IREF_SLP: IREF clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports + \arg RCU_CRCRST: reset CRC + \arg RCU_DMAxRST (x=0,1): reset DMA + \arg RCU_IPARST: reset IPA + \arg RCU_ENETRST: reset ENET + \arg RCU_USBHSRST: reset USBHS + \arg RCU_DCIRST: reset DCI + \arg RCU_TRNGRST: reset TRNG + \arg RCU_USBFSRST: reset USBFS + \arg RCU_EXMCRST: reset EXMC + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC + \arg RCU_SDIORST: reset SDIO + \arg RCU_SYSCFGRST: reset SYSCFG + \arg RCU_TLIRST: reset TLI + \arg RCU_CTCRST: reset CTC + \arg RCU_IREFRST: reset IREF + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports + \arg RCU_CRCRST: reset CRC + \arg RCU_DMAxRST (x=0,1): reset DMA + \arg RCU_IPARST: reset IPA + \arg RCU_ENETRST: reset ENET + \arg RCU_USBHSRST: reset USBHS + \arg RCU_DCIRST: reset DCI + \arg RCU_TRNGRST: reset TRNG + \arg RCU_USBFSRST: reset USBFS + \arg RCU_EXMCRST: reset EXMC + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC + \arg RCU_SDIORST: reset SDIO + \arg RCU_SYSCFGRST: reset SYSCFG + \arg RCU_TLIRST: reset TLI + \arg RCU_CTCRST: reset CTC + \arg RCU_IREFRST: reset IREF + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC16M: select CK_IRC16M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLLP: select CK_PLLP as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC16M: CK_IRC16M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLLP: CK_PLLP is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB / 2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB / 4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB / 8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB / 16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB / 2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB / 4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB / 8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB / 16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source and divider + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_IRC16M: IRC16M selected + \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_PLLP: PLLP selected + \param[in] ckout0_div: CK_OUT0 divider + \arg RCU_CKOUT0_DIVx(x = 1, 2, 3, 4, 5): CK_OUT0 is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ + reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV); + RCU_CFG0 = (reg | ckout0_src | ckout0_div); +} + +/*! + \brief configure the CK_OUT1 clock source and divider + \param[in] ckout1_src: CK_OUT1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected + \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected + \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT1SRC_PLLP: PLLP selected + \param[in] ckout1_div: CK_OUT1 divider + \arg RCU_CKOUT1_DIVx(x = 1, 2, 3, 4, 5): CK_OUT1 is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ + reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); + RCU_CFG0 = (reg | ckout1_src | ckout1_div); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock + \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock + \param[in] pll_psc: the PLL VCO source clock prescaler + \arg this parameter should be selected between 2 and 63 + \param[in] pll_n: the PLL VCO clock multi factor + \arg this parameter should be selected between 64 and 500 + \param[in] pll_p: the PLLP output frequency division factor from PLL VCO clock + \arg this parameter should be selected 2,4,6,8 + \param[in] pll_q: the PLL Q output frequency division factor from PLL VCO clock + \arg this parameter should be selected between 2 and 15 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q) +{ + uint32_t ss_modulation_inc; + uint32_t ss_modulation_reg; + + ss_modulation_inc = 0U; + ss_modulation_reg = RCU_PLLSSCTL; + + /* calculate the minimum factor of PLLN */ + if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON) { + if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN) { + ss_modulation_inc += RCU_SS_MODULATION_DOWN_INC; + } else { + ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; + } + } + + /* check the function parameter */ + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n, ss_modulation_inc) && + CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)) { + RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | + (pll_src) | (pll_q << 24); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the PLLI2S clock + \param[in] plli2s_n: the PLLI2S VCO clock multi factor + \arg this parameter should be selected between 50 and 500 + \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock + \arg this parameter should be selected between 2 and 7 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) +{ + /* check the function parameter */ + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)) { + RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the PLLSAI clock + \param[in] pllsai_n: the PLLSAI VCO clock multi factor + \arg this parameter should be selected between 50 and 500 + \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock + \arg this parameter should be selected 2,4,6,8 + \param[in] pllsai_r: the PLLSAI R output frequency division factor from PLL VCO clock + \arg this parameter should be selected between 2 and 7 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) +{ + /* check the function parameter */ + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)) { + RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); + } else { + /* return status */ + return ERROR; + } + + /* return status */ + return SUCCESS; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL / RTCDIV selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +/*! + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \param[in] rtc_div: RTC clock frequency division + only one parameter can be selected which is shown as below: + \arg RCU_RTC_HXTAL_NONE: no clock for RTC + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL / x, x = 2....31 + \param[out] none + \retval none +*/ +void rcu_rtc_div_config(uint32_t rtc_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the RTCDIV bits and set according to rtc_div value */ + reg &= ~RCU_CFG0_RTCDIV; + RCU_CFG0 = (reg | rtc_div); +} + + +/*! + \brief configure the I2S clock source selection + \param[in] i2s_clock_source: I2S clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2SSRC_PLLI2S: CK_PLLI2S selected as I2S source clock + \arg RCU_I2SSRC_I2S_CKIN: external i2s_ckin pin selected as I2S source clock + \param[out] none + \retval none +*/ +void rcu_i2s_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the I2SSEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG0_I2SSEL; + RCU_CFG0 = (reg | i2s_clock_source); +} + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to i2s_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief configure the PLL48M clock source selection + \param[in] pll48m_clock_source: PLL48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLL48MSRC_PLLQ: CK_PLLQ selected as PLL48M source clock + \arg RCU_PLL48MSRC_PLLSAIP: CK_PLLSAIP selected as PLL48M source clock + \param[out] none + \retval none +*/ +void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ + reg &= ~RCU_ADDCTL_PLL48MSEL; + RCU_ADDCTL = (reg | pll48m_clock_source); +} + +/*! + \brief configure the TIMER clock prescaler selection + \param[in] timer_clock_prescaler: TIMER clock selection + only one parameter can be selected which is shown as below: + \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) + \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) + \param[out] none + \retval none +*/ +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) +{ + /* configure the TIMERSEL bit and select the TIMER clock prescaler */ + if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) { + RCU_CFG1 &= timer_clock_prescaler; + } else { + RCU_CFG1 |= timer_clock_prescaler; + } +} + +/*! + \brief configure the PLLSAIR divider used as input of TLI + \param[in] pllsai_r_div: PLLSAIR divider used as input of TLI + only one parameter can be selected which is shown as below: + \arg RCU_PLLSAIR_DIVx(x=2,4,8,16): PLLSAIR divided x used as input of TLI + \param[out] none + \retval none +*/ +void rcu_tli_clock_div_config(uint32_t pllsai_r_div) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ + reg &= ~RCU_CFG1_PLLSAIRDIV; + RCU_CFG1 = (reg | pllsai_r_div); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTALDRI_LOWER_DRIVE: lower driving capability + \arg RCU_LXTALDRI_HIGHER_DRIVE: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + uint32_t reg; + + reg = RCU_BDCTL; + + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + reg &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL = (reg | lxtal_dricap); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci) { + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC16M stable */ + case RCU_IRC16M: + while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC48M stable */ + case RCU_IRC48M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC32K stable */ + case RCU_IRC32K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) { + reval = SUCCESS; + } + break; + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + /* wait PLLI2S stable */ + case RCU_PLLI2S_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)) { + reval = SUCCESS; + } + break; + /* wait PLLSAI stable */ + case RCU_PLLSAI_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); + stb_cnt++; + } + + /* check whether flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)) { + reval = SUCCESS; + } + break; + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC16M: IRC16M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC32K: IRC32K + \arg RCU_PLL_CK: PLL + \arg RCU_PLLI2S_CK: PLLI2S + \arg RCU_PLLSAI_CK: PLLSAI + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC16M: + case RCU_IRC48M: + case RCU_IRC32K: + case RCU_PLL_CK: + case RCU_PLLI2S_CK: + case RCU_PLLSAI_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci) { + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC16M: + case RCU_IRC48M: + case RCU_IRC32K: + case RCU_PLL_CK: + case RCU_PLLI2S_CK: + case RCU_PLLSAI_CK: + break; + default: + break; + } +} + +/*! + \brief set the IRC16M adjust value + \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F + \arg 0x00 - 0x1F + \param[out] none + \retval none +*/ +void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC16MADJ bits and set according to irc16m_adjval */ + reg &= ~RCU_CTL_IRC16MADJ; + RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); +} + +/*! + \brief configure the spread spectrum modulation for the main PLL clock + \param[in] spread_spectrum_type: PLL spread spectrum modulation type select + \arg RCU_SS_TYPE_CENTER: center spread type is selected + \arg RCU_SS_TYPE_DOWN: down spread type is selected + \param[in] modstep: configure PLL spread spectrum modulation profile amplitude and frequency + \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 + \param[in] modcnt: configure PLL spread spectrum modulation profile amplitude and frequency + \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) +{ + uint32_t reg; + + reg = RCU_PLLSSCTL; + /* reset the RCU_PLLSSCTL register bits */ + reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); + RCU_PLLSSCTL = (reg | spread_spectrum_type | modstep << 13 | modcnt); +} + +/*! + \brief enable the PLL spread spectrum modulation + \param[in] none + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_enable(void) +{ + RCU_PLLSSCTL |= RCU_PLLSSCTL_SSCGON; +} + +/*! + \brief disable the PLL spread spectrum modulation + \param[in] none + \param[out] none + \retval none +*/ +void rcu_spread_spectrum_disable(void) +{ + RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON; +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; + + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws) { + /* IRC16M is selected as CK_SYS */ + case SEL_IRC16M: + cksys_freq = IRC16M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLLP is selected as CK_SYS */ + case SEL_PLLP: + /* get the value of PLLPSC[5:0] */ + pllpsc = GET_BITS(RCU_PLL, 0U, 5U); + plln = GET_BITS(RCU_PLL, 6U, 14U); + pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; + /* PLL clock source selection, HXTAL or IRC16M/2 */ + pllsel = (RCU_PLL & RCU_PLL_PLLSEL); + if(RCU_PLLSRC_HXTAL == pllsel) { + ck_src = HXTAL_VALUE; + } else { + ck_src = IRC16M_VALUE; + } + cksys_freq = ((ck_src / pllpsc) * plln) / pllp; + break; + /* IRC16M is selected as CK_SYS */ + default: + cksys_freq = IRC16M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 10, 12); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 13, 15); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag + \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flags + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: Power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c new file mode 100644 index 0000000..d965f78 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_rtc.c @@ -0,0 +1,1294 @@ +/*! + \file gd32f4xx_rtc.c + \brief RTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_rtc.h" + +/* RTC timeout value */ +#define RTC_WTWF_TIMEOUT ((uint32_t)0x00004000U) /*!< wakeup timer can be write flag timeout */ +#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ +#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ +#define RTC_HRFC_TIMEOUT ((uint32_t)0x20000000U) /*!< recalibration pending flag timeout */ +#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ +#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ + +/*! + \brief reset most of the RTC registers + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_deinit(void) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* RTC_TAMP register is not under write protection */ + RTC_TAMP = RTC_REGISTER_RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + /* reset RTC_CTL register, but RTC_CTL[2��0] */ + RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); + /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. + in order to read calendar from shadow register, not the real registers being reset */ + RTC_TIME = RTC_REGISTER_RESET; + RTC_DATE = RTC_DATE_RESET; + + RTC_PSC = RTC_PSC_RESET; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_CTL &= RTC_REGISTER_RESET; + RTC_WUT = RTC_WUT_RESET; + RTC_COSC = RTC_REGISTER_RESET; + /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ + RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM1TD = RTC_REGISTER_RESET; + RTC_ALRM0SS = RTC_REGISTER_RESET; + RTC_ALRM1SS = RTC_REGISTER_RESET; + /* reset RTC_STAT register, also exit init mode. + at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ + RTC_STAT = RTC_STAT_RESET; + /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ + RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_HRFC = RTC_REGISTER_RESET; + error_status = rtc_register_sync_wait(); + } + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief initialize RTC registers + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + year: 0x0 - 0x99(BCD format) + month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + date: 0x1 - 0x31(BCD format) + day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + minute: 0x0 - 0x59(BCD format) + second: 0x0 - 0x59(BCD format) + factor_asyn: 0x0 - 0x7F + factor_syn: 0x0 - 0x7FFF + am_pm: RTC_AM, RTC_PM + display_format: RTC_24HOUR, RTC_12HOUR + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) +{ + ErrStatus error_status = ERROR; + uint32_t reg_time = 0U, reg_date = 0U; + + reg_date = (DATE_YR(rtc_initpara_struct->year) | \ + DATE_DOW(rtc_initpara_struct->day_of_week) | \ + DATE_MON(rtc_initpara_struct->month) | \ + DATE_DAY(rtc_initpara_struct->date)); + + reg_time = (rtc_initpara_struct->am_pm | \ + TIME_HR(rtc_initpara_struct->hour) | \ + TIME_MN(rtc_initpara_struct->minute) | \ + TIME_SC(rtc_initpara_struct->second)); + + /* 1st: disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* 2nd: enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \ + PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); + + RTC_TIME = (uint32_t)reg_time; + RTC_DATE = (uint32_t)reg_date; + + RTC_CTL &= (uint32_t)(~RTC_CTL_CS); + RTC_CTL |= rtc_initpara_struct->display_format; + + /* 3rd: exit init mode */ + rtc_init_mode_exit(); + + /* 4th: wait the RSYNF flag to set */ + error_status = rtc_register_sync_wait(); + } + + /* 5th: enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enter RTC init mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init_mode_enter(void) +{ + volatile uint32_t time_index = RTC_INITM_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + /* check whether it has been in init mode */ + if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { + RTC_STAT |= RTC_STAT_INITM; + + /* wait until the INITF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + } else { + error_status = SUCCESS; + } + return error_status; +} + +/*! + \brief exit RTC init mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_init_mode_exit(void) +{ + RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); +} + +/*! + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + registers are updated + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_register_sync_wait(void) +{ + volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* firstly clear RSYNF flag */ + RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); + + /* wait until RSYNF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_RSYNF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + } else { + error_status = SUCCESS; + } + + return error_status; +} + +/*! + \brief get current time and date + \param[in] none + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + year: 0x0 - 0x99(BCD format) + month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + date: 0x1 - 0x31(BCD format) + day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + minute: 0x0 - 0x59(BCD format) + second: 0x0 - 0x59(BCD format) + factor_asyn: 0x0 - 0x7F + factor_syn: 0x0 - 0x7FFF + am_pm: RTC_AM, RTC_PM + display_format: RTC_24HOUR, RTC_12HOUR + \retval none +*/ +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) +{ + uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; + + temp_tr = (uint32_t)RTC_TIME; + temp_dr = (uint32_t)RTC_DATE; + temp_pscr = (uint32_t)RTC_PSC; + temp_ctlr = (uint32_t)RTC_CTL; + + /* get current time and construct rtc_parameter_struct structure */ + rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); + rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); + rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); + rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); + rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); + rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); + rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); + rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); + rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); + rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); +} + +/*! + \brief get current subsecond value + \param[in] none + \param[out] none + \retval current subsecond value +*/ +uint32_t rtc_subsecond_get(void) +{ + uint32_t reg = 0U; + /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ + reg = (uint32_t)RTC_SS; + /* read RTC_DATE to unlock the 3 shadow registers */ + (void)(RTC_DATE); + + return reg; +} + +/*! + \brief configure RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + alarm_minute: 0x0 - 0x59(BCD format) + alarm_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrmtd = 0U; + + reg_alrmtd = (rtc_alarm_time->alarm_mask | \ + rtc_alarm_time->weekday_or_date | \ + rtc_alarm_time->am_pm | \ + ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ + ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ + ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ + ALRMTD_SC(rtc_alarm_time->alarm_second)); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_ALRM0TD = (uint32_t)reg_alrmtd; + + } else { + RTC_ALRM1TD = (uint32_t)reg_alrmtd; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure subsecond of RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[in] mask_subsecond: alarm subsecond mask + \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration + \arg RTC_MASKSSC_1_14: mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared + \arg RTC_MASKSSC_2_14: mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared + \arg RTC_MASKSSC_3_14: mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared + \arg RTC_MASKSSC_4_14: mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared + \arg RTC_MASKSSC_5_14: mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared + \arg RTC_MASKSSC_6_14: mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared + \arg RTC_MASKSSC_7_14: mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared + \arg RTC_MASKSSC_8_14: mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared + \arg RTC_MASKSSC_9_14: mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared + \arg RTC_MASKSSC_10_14: mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared + \arg RTC_MASKSSC_11_14: mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared + \arg RTC_MASKSSC_12_14: mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared + \arg RTC_MASKSSC_13_14: mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared + \arg RTC_MASKSSC_14: mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared + \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared + \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) + \param[out] none + \retval none +*/ +void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_ALRM0SS = mask_subsecond | subsecond; + } else { + RTC_ALRM1SS = mask_subsecond | subsecond; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + alarm_minute: 0x0 - 0x59(BCD format) + alarm_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrmtd = 0U; + + /* get the value of RTC_ALRM0TD register */ + if(RTC_ALARM0 == rtc_alarm) { + reg_alrmtd = RTC_ALRM0TD; + } else { + reg_alrmtd = RTC_ALRM1TD; + } + /* get alarm parameters and construct the rtc_alarm_struct structure */ + rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; + rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); + rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); + rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); + rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); + rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); + rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); +} + +/*! + \brief get RTC alarm subsecond + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval RTC alarm subsecond value +*/ +uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) +{ + if(RTC_ALARM0 == rtc_alarm) { + return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); + } else { + return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); + } +} + +/*! + \brief enable RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval none +*/ +void rtc_alarm_enable(uint8_t rtc_alarm) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + if(RTC_ALARM0 == rtc_alarm) { + RTC_CTL |= RTC_CTL_ALRM0EN; + } else { + RTC_CTL |= RTC_CTL_ALRM1EN; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC alarm + \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) +{ + volatile uint32_t time_index = RTC_ALRMXWF_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the state of alarm */ + if(RTC_ALARM0 == rtc_alarm) { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + /* wait until ALRM0WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM0WF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } else { + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); + /* wait until ALRM1WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM1WF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC time-stamp + \param[in] edge: specify which edge to detect of time-stamp + \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event + \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event + \param[out] none + \retval none +*/ +void rtc_timestamp_enable(uint32_t edge) +{ + uint32_t reg_ctl = 0U; + + /* clear the bits to be configured in RTC_CTL */ + reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); + + /* new configuration */ + reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL = (uint32_t)reg_ctl; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC time-stamp + \param[in] none + \param[out] none + \retval none +*/ +void rtc_timestamp_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the TSEN bit */ + RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC timestamp time and date + \param[in] none + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + parameters for RTC time-stamp configuration + members of the structure and the member values are shown as below: + timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + timestamp_date: 0x1 - 0x31(BCD format) + timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + timestamp_minute: 0x0 - 0x59(BCD format) + timestamp_second: 0x0 - 0x59(BCD format) + am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) +{ + uint32_t temp_tts = 0U, temp_dts = 0U; + + /* get the value of time_stamp registers */ + temp_tts = (uint32_t)RTC_TTS; + temp_dts = (uint32_t)RTC_DTS; + + /* get timestamp time and construct the rtc_timestamp_struct structure */ + rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); + rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); + rtc_timestamp->timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); + rtc_timestamp->timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); + rtc_timestamp->timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); + rtc_timestamp->timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); + rtc_timestamp->timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); +} + +/*! + \brief get RTC time-stamp subsecond + \param[in] none + \param[out] none + \retval RTC time-stamp subsecond value +*/ +uint32_t rtc_timestamp_subsecond_get(void) +{ + return ((uint32_t)RTC_SSTS); +} + +/*! + \brief RTC time-stamp mapping + \param[in] rtc_af: + \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp + \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp + \param[out] none + \retval none +*/ +void rtc_timestamp_pin_map(uint32_t rtc_af) +{ + RTC_TAMP &= ~RTC_TAMP_TSSEL; + RTC_TAMP |= rtc_af; +} + +/*! + \brief enable RTC tamper + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + parameters for RTC tamper configuration + members of the structure and the member values are shown as below: + detecting tamper event can using edge mode or level mode + (1) using edge mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING + tamper_filter: RTC_FLT_EDGE + tamper_with_timestamp: DISABLE, ENABLE + (2) using level mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, + RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, + RTC_FREQ_DIV512, RTC_FREQ_DIV256 + tamper_precharge_enable: DISABLE, ENABLE + tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C + tamper_with_timestamp: DISABLE, ENABLE + \param[out] none + \retval none +*/ +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); + + /* tamper filter must be used when the tamper source is voltage level detection */ + RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; + + /* the tamper source is voltage level detection */ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); + + /* check if the tamper pin need precharge, if need, then configure the precharge time */ + if(DISABLE == rtc_tamper->tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); + } + + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + } else { + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + } + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + if(DISABLE != rtc_tamper->tamper_with_timestamp) { + /* the tamper event also cause a time-stamp event */ + RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; + } + /* enable tamper */ + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); +} + +/*! + \brief disable RTC tamper + \param[in] source: specify which tamper source to be disabled + \arg RTC_TAMPER0 + \arg RTC_TAMPER1 + \param[out] none + \retval none +*/ +void rtc_tamper_disable(uint32_t source) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~source; + +} + +/*! + \brief RTC tamper0 mapping + \param[in] rtc_af: + \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 + \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 + \param[out] none + \retval none +*/ +void rtc_tamper0_pin_map(uint32_t rtc_af) +{ + RTC_TAMP &= ~(RTC_TAMP_TP0EN | RTC_TAMP_TP0SEL); + RTC_TAMP |= rtc_af; +} + +/*! + \brief enable specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be enabled + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM0: alarm0 interrupt + \arg RTC_INT_ALARM1: alarm1 interrupt + \arg RTC_INT_TAMP: tamper detection interrupt + \arg RTC_INT_WAKEUP: wakeup timer interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enable the interrupts in RTC_CTL register */ + RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* enable the interrupts in RTC_TAMP register */ + RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disble specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be disabled + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM0: alarm interrupt + \arg RTC_INT_ALARM1: alarm interrupt + \arg RTC_INT_TAMP: tamper detection interrupt + \arg RTC_INT_WAKEUP: wakeup timer interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* disable the interrupts in RTC_CTL register */ + RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* disable the interrupts in RTC_TAMP register */ + RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief check specified flag + \param[in] flag: specify which flag to check + \arg RTC_STAT_SCP: smooth calibration pending flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_ALRM0: alarm0 occurs flag + \arg RTC_FLAG_ALRM1: alarm1 occurs flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_INIT: initialization state flag + \arg RTC_FLAG_RSYN: register synchronization flag + \arg RTC_FLAG_YCM: year configuration mark status flag + \arg RTC_FLAG_SOP: shift function operation pending flag + \arg RTC_FLAG_ALRM0W: alarm0 configuration can be write flag + \arg RTC_FLAG_ALRM1W: alarm1 configuration can be write flag + \arg RTC_FLAG_WTW: wakeup timer can be write flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + FlagStatus flag_state = RESET; + + if((uint32_t)RESET != (RTC_STAT & flag)) { + flag_state = SET; + } + return flag_state; +} + +/*! + \brief clear specified flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_RSYN: register synchronization flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + RTC_STAT &= (uint32_t)(~flag); +} + +/*! + \brief configure rtc alarm output source + \param[in] source: specify signal to output + \arg RTC_ALARM0_HIGH: when the alarm0 flag is set, the output pin is high + \arg RTC_ALARM0_LOW: when the alarm0 flag is set, the output pin is low + \arg RTC_ALARM1_HIGH: when the alarm1 flag is set, the output pin is high + \arg RTC_ALARM1_LOW: when the alarm1 flag is set, the output pin is low + \arg RTC_WAKEUP_HIGH: when the wakeup flag is set, the output pin is high + \arg RTC_WAKEUP_LOW: when the wakeup flag is set, the output pin is low + \param[in] mode: specify the output pin mode when output alarm signal + \arg RTC_ALARM_OUTPUT_OD: open drain mode + \arg RTC_ALARM_OUTPUT_PP: push pull mode + \param[out] none + \retval none +*/ +void rtc_alarm_output_config(uint32_t source, uint32_t mode) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= ~(RTC_CTL_OS | RTC_CTL_OPOL); + RTC_TAMP &= ~RTC_TAMP_AOT; + + RTC_CTL |= (uint32_t)(source); + /* alarm output */ + RTC_TAMP |= (uint32_t)(mode); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure rtc calibration output source + \param[in] source: specify signal to output + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal + \param[out] none + \retval none +*/ +void rtc_calibration_output_config(uint32_t source) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_COS); + + RTC_CTL |= (uint32_t)(source); + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief adjust the daylight saving time by adding or substracting one hour from the current time + \param[in] operation: hour adjustment operation + \arg RTC_CTL_A1H: add one hour + \arg RTC_CTL_S1H: substract one hour + \param[out] none + \retval none +*/ +void rtc_hour_adjust(uint32_t operation) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint32_t)(operation); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief adjust RTC second or subsecond value of current time + \param[in] add: add 1s to current time or not + \arg RTC_SHIFT_ADD1S_RESET: no effect + \arg RTC_SHIFT_ADD1S_SET: add 1s to current time + \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) +{ + volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + uint32_t temp = 0U; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a shift operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SOPF; + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + /* check if the function of reference clock detection is disabled */ + temp = RTC_CTL & RTC_CTL_REFEN; + if((RESET == flag_status) && (RESET == temp)) { + RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= ~RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_enable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief disable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_disable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC auto wakeup function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_wakeup_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_WTEN; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC auto wakeup function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_disable(void) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + RTC_CTL &= ~RTC_CTL_WTEN; + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief set RTC auto wakeup timer clock + \param[in] wakeup_clock: + \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 + \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 + \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 + \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 + \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre + \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; + RTC_CTL |= (uint32_t)wakeup_clock; + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief set wakeup timer value + \param[in] wakeup_timer: 0x0000-0xffff + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) +{ + ErrStatus error_status = ERROR; + volatile uint32_t time_index = RTC_WTWF_TIMEOUT; + uint32_t flag_status = RESET; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* wait until the WTWF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET == flag_status) { + error_status = ERROR; + } else { + RTC_WUT = (uint32_t)wakeup_timer; + error_status = SUCCESS; + } + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief get wakeup timer value + \param[in] none + \param[out] none + \retval wakeup timer value +*/ +uint16_t rtc_wakeup_timer_get(void) +{ + return (uint16_t)RTC_WUT; +} + +/*! + \brief configure RTC smooth calibration + \param[in] window: select calibration window + \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz + \param[in] plus: add RTC clock or not + \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock + \arg RTC_CALIBRATION_PLUS_RESET: no effect + \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) +{ + volatile uint32_t time_index = RTC_HRFC_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a smooth calibration operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SCPF; + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET == flag_status) { + RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC coarse calibration + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_enable(void) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_CCEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief disable RTC coarse calibration + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_disable(void) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + return error_status; +} + +/*! + \brief config coarse calibration direction and step + \param[in] direction: CALIB_INCREASE or CALIB_DECREASE + \param[in] step: 0x00-0x1F + COSD=0: + 0x00:+0 PPM + 0x01:+4 PPM + 0x02:+8 PPM + .... + 0x1F:+126 PPM + COSD=1: + 0x00:-0 PPM + 0x01:-2 PPM + 0x02:-4 PPM + .... + 0x1F:-63 PPM + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) +{ + ErrStatus error_status = ERROR; + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + if(CALIB_DECREASE == direction) { + RTC_COSC |= (uint32_t)RTC_COSC_COSD; + } else { + RTC_COSC &= (uint32_t)~RTC_COSC_COSD; + } + RTC_COSC &= ~RTC_COSC_COSS; + RTC_COSC |= (uint32_t)((uint32_t)step & 0x1FU); + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c new file mode 100644 index 0000000..867e97d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_sdio.c @@ -0,0 +1,804 @@ +/*! + \file gd32f4xx_sdio.c + \brief SDIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_sdio.h" + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + rcu_periph_reset_enable(RCU_SDIORST); + rcu_periph_reset_disable(RCU_SDIORST); +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 512 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); + /* if the clock division is greater or equal to 256, set the DIV[8] */ + if(clock_division >= 256U) { + clock_config |= SDIO_CLKCTL_DIV8; + clock_division -= 256U; + } + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* disable the CSM */ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] sdio_responsex: SDIO response + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t sdio_responsex) +{ + uint32_t resp_content = 0U; + switch(sdio_responsex) { + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & int_flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if(SDIO_READWAITTYPE_CLK == readwait_type) { + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + } else { + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c new file mode 100644 index 0000000..68daff8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_spi.c @@ -0,0 +1,880 @@ +/*! + \file gd32f4xx_spi.c + \brief SPI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_spi.h" +#include "gd32f4xx_rcu.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ +#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */ + +/* default value */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ + +/*! + \brief deinitialize SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph) { + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1,I2S1 and I2S1_ADD */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2,I2S2 and I2S2_ADD */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + case SPI3: + /* reset SPI3 */ + rcu_periph_reset_enable(RCU_SPI3RST); + rcu_periph_reset_disable(RCU_SPI3RST); + break; + case SPI4: + /* reset SPI4 */ + rcu_periph_reset_enable(RCU_SPI4RST); + rcu_periph_reset_disable(RCU_SPI4RST); + break; + case SPI5: + /* reset SPI5 */ + rcu_periph_reset_enable(RCU_SPI5RST); + rcu_periph_reset_disable(RCU_SPI5RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with default values + \param[in] none + \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the structure with default value */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; + spi_struct->endian = SPI_ENDIAN_MSB; +} +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE. + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI nss use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)i2s_mode; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescale + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] i2s_frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] i2s_mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + +#ifndef I2S_EXTERNAL_CLOCK_IN + uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; +#endif /* I2S_EXTERNAL_CLOCK_IN */ + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + +#ifdef I2S_EXTERNAL_CLOCK_IN + rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN); + + /* set the I2S clock to the external clock input value */ + i2sclock = I2S_EXTERNAL_CLOCK_IN; +#else + + /* turn on the oscillator HXTAL */ + rcu_osci_on(RCU_HXTAL); + /* wait for oscillator stabilization flags is SET */ + rcu_osci_stab_wait(RCU_HXTAL); + /* turn on the PLLI2S */ + rcu_osci_on(RCU_PLLI2S_CK); + /* wait for PLLI2S flags is SET */ + rcu_osci_stab_wait(RCU_PLLI2S_CK); + /* configure the I2S clock source selection */ + rcu_i2s_clock_config(RCU_I2SSRC_PLLI2S); + + /* get the RCU_PLL_PLLPSC value */ + plli2sm = (uint32_t)(RCU_PLL & RCU_PLL_PLLPSC); + /* get the RCU_PLLI2S_PLLI2SN value */ + plli2sn = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SN) >> 6); + /* get the RCU_PLLI2S_PLLI2SR value */ + plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28); + + if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); + } else { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); + } +#endif /* I2S_EXTERNAL_CLOCK_IN */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == i2s_mckout) { + clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / i2s_audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / i2s_audiosample); + } + } + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI nss output + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI nss output + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI nss pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI nss pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma) { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + } else { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief diable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) +{ + if(SPI_DMA_TRANSMIT == spi_dma) { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + } else { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc) +{ + if(SPI_CRC_TX == spi_crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief configure i2s full duplex mode + \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) + \param[in] i2s_mode: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[in] i2s_frameformat: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[out] none + \retval none +*/ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, + uint32_t i2s_ckpl, uint32_t i2s_frameformat) +{ + uint32_t reg = 0U, tmp = 0U; + + reg = I2S_ADD_I2SCTL(i2s_add_periph); + reg &= I2S_FULL_DUPLEX_MASK; + + /* get the mode of the extra I2S module I2Sx_ADD */ + if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { + tmp = I2S_MODE_SLAVERX; + } else { + tmp = I2S_MODE_SLAVETX; + } + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)tmp; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + /* configure data frame format */ + reg |= (uint32_t)i2s_frameformat; + + /* write to SPI_I2SCTL register */ + I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt flag status + only one parameter can be selected which are shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(spi_i2s_int) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE : + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE : + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR : + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR : + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR : + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR : + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR : + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if(reg1 && reg2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) +{ + if(SPI_STAT(spi_periph) & spi_i2s_flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c new file mode 100644 index 0000000..6b11c01 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_syscfg.c @@ -0,0 +1,205 @@ +/*! + \file gd32f4xx_syscfg.c + \brief SYSCFG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_syscfg.h" + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_SYSCFGRST); + rcu_periph_reset_disable(RCU_SYSCFGRST); +} + +/*! + \brief configure the boot mode + \param[in] syscfg_bootmode: selects the memory remapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_SRAM: SRAM0 of on-chip SRAM (0x20000000~0x2001BFFF) is mapped at address 0x00000000 + \arg SYSCFG_BOOTMODE_EXMC_SDRAM: SDRAM bank0 of EXMC (0xC0000000~0xC7FFFFFF) is mapped at address 0x00000000 + \param[out] none + \retval none +*/ +void syscfg_bootmode_config(uint8_t syscfg_bootmode) +{ + /* reset the SYSCFG_CFG0_BOOT_MODE bit and set according to syscfg_bootmode */ + SYSCFG_CFG0 &= ~SYSCFG_CFG0_BOOT_MODE; + SYSCFG_CFG0 |= (uint32_t)syscfg_bootmode; +} + +/*! + \brief FMC memory mapping swap + \param[in] syscfg_fmc_swap: selects the interal flash bank swapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 + \arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000 + \param[out] none + \retval none +*/ +void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) +{ + uint32_t reg; + reg = SYSCFG_CFG0; + /* reset the FMC_SWP bit and set according to syscfg_fmc_swap */ + reg &= ~SYSCFG_CFG0_FMC_SWP; + SYSCFG_CFG0 = (reg | syscfg_fmc_swap); +} + +/*! + \brief EXMC memory mapping swap + \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping + only one parameter can be selected which is shown as below: + \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card + \arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap + \param[out] none + \retval none +*/ +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) +{ + uint32_t reg; + + reg = SYSCFG_CFG0; + /* reset the SYSCFG_CFG0_EXMC_SWP bits and set according to syscfg_exmc_swap */ + reg &= ~SYSCFG_CFG0_EXMC_SWP; + SYSCFG_CFG0 = (reg | syscfg_exmc_swap); +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port + \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP) { + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief configure the PHY interface for the ethernet MAC + \param[in] syscfg_enet_phy_interface: specifies the media interface mode. + only one parameter can be selected which is shown as below: + \arg SYSCFG_ENET_PHY_MII: MII mode is selected + \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected + \param[out] none + \retval none +*/ +void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) +{ + uint32_t reg; + + reg = SYSCFG_CFG1; + /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ + reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; + SYSCFG_CFG1 = (reg | syscfg_enet_phy_interface); +} + +/*! + \brief configure the I/O compensation cell + \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: + \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void syscfg_compensation_config(uint32_t syscfg_compensation) +{ + uint32_t reg; + + reg = SYSCFG_CPSCTL; + /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ + reg &= ~SYSCFG_CPSCTL_CPS_EN; + SYSCFG_CPSCTL = (reg | syscfg_compensation); +} + +/*! + \brief checks whether the I/O compensation cell ready flag is set or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus syscfg_flag_get(void) +{ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) { + return SET; + } else { + return RESET; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c new file mode 100644 index 0000000..a04d72d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_timer.c @@ -0,0 +1,2064 @@ +/*! + \file gd32f4xx_timer.c + \brief TIMER driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f4xx_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct *initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,(TIMER1,TIMER4,32 bit) + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value,0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value,0~65535 + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value,0~65535 + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel) { + /* read TIMER channel 0 capture compare register value */ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + /* read TIMER channel 1 capture compare register value */ + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + /* read TIMER channel 2 capture compare register value */ + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + /* read TIMER channel 3 capture compare register value */ + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11)) + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel remap function + \param[in] timer_periph: TIMERx(x=1,4,10) + \param[in] remap: + only one parameter can be selected which is shown as below: + \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO + \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP + \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF + \arg TIMER1_ITI1_RMP_USB_HS_SOF: timer1 internal trigger input1 remap to USB HS SOF + \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin + \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K + \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL + \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt + \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting + \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if(TIMER_CHVSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] outsel: + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if(TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c new file mode 100644 index 0000000..04f9e31 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_tli.c @@ -0,0 +1,598 @@ +/*! + \file gd32f4xx_tli.c + \brief TLI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_tli.h" + +#define TLI_DEFAULT_VALUE 0x00000000U +#define TLI_OPAQUE_VALUE 0x000000FFU + +/*! + \brief deinitialize TLI registers + \param[in] none + \param[out] none + \retval none +*/ +void tli_deinit(void) +{ + rcu_periph_reset_enable(RCU_TLIRST); + rcu_periph_reset_disable(RCU_TLIRST); +} + +/*! + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined + \param[in] none + \param[out] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \retval none +*/ +void tli_struct_para_init(tli_parameter_struct *tli_struct) +{ + /* initialize the struct parameters with default values */ + tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; + tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; + tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; + tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; + tli_struct->backcolor_red = TLI_DEFAULT_VALUE; + tli_struct->backcolor_green = TLI_DEFAULT_VALUE; + tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; + tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; + tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; +} + +/*! + \brief initialize TLI display timing parameters + \param[in] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \param[out] none + \retval none +*/ +void tli_init(tli_parameter_struct *tli_struct) +{ + /* synchronous pulse size configuration */ + TLI_SPSZ &= ~(TLI_SPSZ_VPSZ | TLI_SPSZ_HPSZ); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz | ((uint32_t)tli_struct->synpsz_hpsz << 16U)); + /* back-porch size configuration */ + TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); + /* active size configuration */ + TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); + TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); + /* total size configuration */ + TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); + TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); + /* background color configuration */ + TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); + TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); + TLI_CTL &= ~(TLI_CTL_HPPS | TLI_CTL_VPPS | TLI_CTL_DEPS | TLI_CTL_CLKPS); + TLI_CTL |= (tli_struct->signalpolarity_hs | tli_struct->signalpolarity_vs | \ + tli_struct->signalpolarity_de | tli_struct->signalpolarity_pixelck); + +} + +/*! + \brief configure TLI dither function + \param[in] dither_stat + only one parameter can be selected which is shown as below: + \arg TLI_DITHER_ENABLE + \arg TLI_DITHER_DISABLE + \param[out] none + \retval none +*/ +void tli_dither_config(uint8_t dither_stat) +{ + if(TLI_DITHER_ENABLE == dither_stat) { + TLI_CTL |= TLI_CTL_DFEN; + } else { + TLI_CTL &= ~(TLI_CTL_DFEN); + } +} + +/*! + \brief enable TLI + \param[in] none + \param[out] none + \retval none +*/ +void tli_enable(void) +{ + TLI_CTL |= TLI_CTL_TLIEN; +} + +/*! + \brief disable TLI + \param[in] none + \param[out] none + \retval none +*/ +void tli_disable(void) +{ + TLI_CTL &= ~(TLI_CTL_TLIEN); +} + +/*! + \brief configure TLI reload mode + \param[in] reload_mod + only one parameter can be selected which is shown as below: + \arg TLI_FRAME_BLANK_RELOAD_EN + \arg TLI_REQUEST_RELOAD_EN + \param[out] none + \retval none +*/ +void tli_reload_config(uint8_t reload_mod) +{ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod) { + /* the layer configuration will be reloaded at frame blank */ + TLI_RL |= TLI_RL_FBR; + } else { + /* the layer configuration will be reloaded after this bit sets */ + TLI_RL |= TLI_RL_RQR; + } +} + +/*! + \brief initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined + \param[in] none + \param[out] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number + \retval none +*/ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) +{ + /* initialize the struct parameters with default values */ + layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; + layer_struct->layer_ppf = LAYER_PPF_ARGB8888; + layer_struct->layer_sa = TLI_OPAQUE_VALUE; + layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; + layer_struct->layer_default_red = TLI_DEFAULT_VALUE; + layer_struct->layer_default_green = TLI_DEFAULT_VALUE; + layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; + layer_struct->layer_acf1 = LAYER_ACF1_PASA; + layer_struct->layer_acf2 = LAYER_ACF2_PASA; + layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[in] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number + \param[out] none + \retval none +*/ +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct) +{ + /* configure layer window horizontal position */ + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos | ((uint32_t)layer_struct->layer_window_rightpos << 16U)); + /* configure layer window vertical position */ + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos | ((uint32_t)layer_struct->layer_window_bottompos << 16U)); + /* configure layer packeted pixel format */ + TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); + TLI_LxPPF(layerx) = layer_struct->layer_ppf; + /* configure layer specified alpha */ + TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); + TLI_LxSA(layerx) = layer_struct->layer_sa; + /* configure layer default color */ + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB | (TLI_LxDC_DCG) | (TLI_LxDC_DCR) | (TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | ((uint32_t)layer_struct->layer_default_green << 8U) + | ((uint32_t)layer_struct->layer_default_red << 16U) + | ((uint32_t)layer_struct->layer_default_alpha << 24U)); + + /* configure layer alpha calculation factors */ + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2 | (TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2) | (layer_struct->layer_acf1)); + /* configure layer frame buffer base address */ + TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); + TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); + /* configure layer frame line length */ + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL | (TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length | ((uint32_t)layer_struct->layer_frame_buf_stride_offset << 16U)); + /* configure layer frame total line number */ + TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); + TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); + +} + +/*! + \brief reconfigure window position + \param[in] layerx: LAYERx(x=0,1) + \param[in] offset_x: new horizontal offset + \param[in] offset_y: new vertical offset + \param[out] none + \retval none +*/ +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y) +{ + /* configure window start position */ + uint32_t layer_ppf, line_num, hstart, vstart; + uint32_t line_length = 0U; + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x + (((TLI_BPSZ & TLI_BPSZ_HBPSZ) >> 16U) + 1U); + vstart = (uint32_t)offset_y + ((TLI_BPSZ & TLI_BPSZ_VBPSZ) + 1U); + line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); + layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); + /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ + switch(layer_ppf) { + case LAYER_PPF_ARGB8888: + /* each pixel includes 4bytes, when pixel format is ARGB8888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 4U); + break; + case LAYER_PPF_RGB888: + /* each pixel includes 3bytes, when pixel format is RGB888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 3U); + break; + case LAYER_PPF_RGB565: + case LAYER_PPF_ARGB1555: + case LAYER_PPF_ARGB4444: + case LAYER_PPF_AL88: + /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 2U); + break; + case LAYER_PPF_L8: + case LAYER_PPF_AL44: + /* each pixel includes 1byte, when pixel format is L8 or AL44 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U)); + break; + default: + break; + } + /* reconfigure window position */ + TLI_LxHPOS(layerx) = (hstart | ((hstart + line_length - 1U) << 16U)); + TLI_LxVPOS(layerx) = (vstart | ((vstart + line_num - 1U) << 16U)); +} + +/*! + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined + \param[in] none + \param[out] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \retval none +*/ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) +{ + /* initialize the struct parameters with default values */ + lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[in] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \param[out] none + \retval none +*/ +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct) +{ + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) + | ((uint32_t)lut_struct->layer_lut_channel_red << 16U + | ((uint32_t)lut_struct->layer_table_addr << 24U))); +} + +/*! + \brief initialize TLI layer color key + \param[in] layerx: LAYERx(x=0,1) + \param[in] redkey: color key red + \param[in] greenkey: color key green + \param[in] bluekey: color key blue + \param[out] none + \retval none +*/ +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey) +{ + TLI_LxCKEY(layerx) = (((uint32_t)bluekey) | ((uint32_t)greenkey << 8U) | ((uint32_t)redkey << 16U)); +} + +/*! + \brief enable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; +} + +/*! + \brief disable TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_layer_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); +} + +/*! + \brief enable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; +} + +/*! + \brief disable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); +} + +/*! + \brief enable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; +} + +/*! + \brief disable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); +} + +/*! + \brief set line mark value + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void tli_line_mark_set(uint16_t line_num) +{ + TLI_LM &= ~(TLI_LM_LM); + TLI_LM = (uint32_t)line_num; +} + +/*! + \brief get current displayed position + \param[in] none + \param[out] none + \retval position of current pixel +*/ +uint32_t tli_current_pos_get(void) +{ + return TLI_CPPOS; +} + +/*! + \brief enable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_enable(uint32_t int_flag) +{ + TLI_INTEN |= (int_flag); +} + +/*! + \brief disable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_disable(uint32_t int_flag) +{ + TLI_INTEN &= ~(int_flag); +} + +/*! + \brief get TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state; + state = TLI_INTF; + if(state & int_flag) { + state = TLI_INTEN; + if(state & int_flag) { + return SET; + } + } + return RESET; +} + +/*! + \brief clear TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval none +*/ +void tli_interrupt_flag_clear(uint32_t int_flag) +{ + TLI_INTC |= (int_flag); +} + +/*! + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \param[in] flag: TLI flags or states + only one parameter can be selected which is shown as below: + \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_HDE: current HDE state + \arg TLI_FLAG_VS: current VS status of the TLI + \arg TLI_FLAG_HS: current HS status of the TLI + \arg TLI_FLAG_LM: line mark interrupt flag + \arg TLI_FLAG_FE: FIFO error interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_flag_get(uint32_t flag) +{ + uint32_t stat; + /* choose which register to get flag or state */ + if(flag >> 31U) { + stat = TLI_INTF; + } else { + stat = TLI_STAT; + } + if(flag & stat) { + return SET; + } else { + return RESET; + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c new file mode 100644 index 0000000..8330a57 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_trng.c @@ -0,0 +1,156 @@ +/*! + \file gd32f4xx_trng.c + \brief TRNG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_trng.h" + +/*! + \brief reset TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_deinit(void) +{ + rcu_periph_reset_enable(RCU_TRNGRST); + rcu_periph_reset_disable(RCU_TRNGRST); +} + +/*! + \brief enable TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_enable(void) +{ + TRNG_CTL |= TRNG_CTL_TRNGEN; +} + +/*! + \brief disable TRNG + \param[in] none + \param[out] none + \retval none +*/ +void trng_disable(void) +{ + TRNG_CTL &= ~TRNG_CTL_TRNGEN; +} + +/*! + \brief get the true random data + \param[in] none + \param[out] none + \retval uint32_t: 0x0-0xFFFFFFFF +*/ +uint32_t trng_get_true_random_data(void) +{ + return (TRNG_DATA); +} + +/*! + \brief enable TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_enable(void) +{ + TRNG_CTL |= TRNG_CTL_TRNGIE; +} + +/*! + \brief disable TRNG interrupt + \param[in] none + \param[out] none + \retval none +*/ +void trng_interrupt_disable(void) +{ + TRNG_CTL &= ~TRNG_CTL_TRNGIE; +} + +/*! + \brief get TRNG flag status + \param[in] flag: TRNG flag + only one parameter can be selected which is shown as below: + \arg TRNG_FLAG_DRDY: random Data ready status + \arg TRNG_FLAG_CECS: clock error current status + \arg TRNG_FLAG_SECS: seed error current status + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus trng_flag_get(trng_flag_enum flag) +{ + if(RESET != (TRNG_STAT & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag + only one parameter can be selected which is shown as below: + \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) +{ + if(RESET != (TRNG_STAT & int_flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag + only one parameter can be selected which is shown as below: + \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag + \param[out] none + \retval none +*/ +void trng_interrupt_flag_clear(trng_int_flag_enum int_flag) +{ + TRNG_STAT &= ~(uint32_t)int_flag; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c new file mode 100644 index 0000000..d7fc2bc --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_usart.c @@ -0,0 +1,1009 @@ +/*! + \file gd32f4xx_usart.c + \brief USART driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_usart.h" + +/* USART register bit offset */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph) { + case USART0: + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case USART5: + rcu_periph_reset_enable(RCU_USART5RST); + rcu_periph_reset_disable(RCU_USART5RST); + break; + case UART3: + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + case UART6: + rcu_periph_reset_enable(RCU_UART6RST); + rcu_periph_reset_disable(RCU_UART6RST); + break; + case UART7: + rcu_periph_reset_enable(RCU_UART7RST); + rcu_periph_reset_disable(RCU_UART7RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ + case USART0: + uclk = rcu_clock_freq_get(CK_APB2); + break; + case USART5: + uclk = rcu_clock_freq_get(CK_APB2); + break; + case USART1: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case USART2: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART3: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART4: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART6: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART7: + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { + /* when oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U * uclk) + baudval / 2U) / baudval; + intdiv = udiv & 0xfff0U; + fradiv = (udiv >> 1U) & 0x7U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } else { + /* when oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; + intdiv = udiv & 0xfff0U; + fradiv = udiv & 0xfU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_EVEN: even parity + \arg USART_PM_ODD: odd parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN Bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL3(usart_periph); + ctl &= ~(USART_CTL3_MSBF); + ctl |= msbf; + /* configure data transmitted/received mode */ + USART_CTL3(usart_periph) = ctl; +} + +/*! + \brief configure USART inversion + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] invertpara: refer to enum USART_INVERT_CONFIG + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + /* inverted or not the specified siginal */ + switch(invertpara) { + case USART_DINV_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_DINV; + break; + case USART_TXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_TINV; + break; + case USART_RXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_RINV; + break; + case USART_DINV_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); + break; + case USART_TXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); + break; + case USART_RXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); + break; + default: + break; + } +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: 8 bits + \arg USART_OVSMOD_16: 16 bits + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure sample bit method + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] obsm: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1bit: 1 bit + \arg USART_OSB_3bit: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= obsm; +} + +/*! + \brief enable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) |= USART_CTL3_RTEN; +} + +/*! + \brief disable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); +} + +/*! + \brief set the receiver timeout threshold of USART + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] rtimeout: 0-0x00FFFFFF + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] wmehtod: two method be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmehtod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] clen: CK length + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] guat: guard time value, 0-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] scrtnum: smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << CTL3_SCRTNUM_OFFSET)); +} + +/*! + \brief configure block length in Smartcard T=1 reception + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] bl: block length + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] psc: 0-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure break frame coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] bcm: + only one parameter can be selected which is shown as below: + \arg USART_BCM_NONE: no parity error is detected + \arg USART_BCM_EN: parity error is detected + \param[out] none + \retval none +*/ +void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_BCM); + USART_CHC(usart_periph) |= (USART_CHC_BCM & bcm); +} + +/*! + \brief configure parity check coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] pcm: + only one parameter can be selected which is shown as below: + \arg USART_PCM_NONE: not check parity + \arg USART_PCM_EN: check the parity + \param[out] none + \retval none +*/ +void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_PCM); + USART_CHC(usart_periph) |= (USART_CHC_PCM & pcm); +} + +/*! + \brief configure hardware flow control coherence mode + \param[in] usart_periph: USARTx(x=0,1,2,5) + \param[in] hcm: + only one parameter can be selected which is shown as below: + \arg USART_HCM_NONE: nRTS signal equals to the rxne status register + \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled + \param[out] none + \retval none +*/ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_HCM); + USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT0/STAT1/CHC register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag in STAT0/STAT1/CHC register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag + \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c new file mode 100644 index 0000000..8b85c68 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/gd32f4xx_wwdgt.c @@ -0,0 +1,129 @@ +/*! + \file gd32f4xx_wwdgt.c + \brief WWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f4xx_wwdgt.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + /* configure WIN and PSC bits, configure CNT bit */ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT = (uint32_t)(RESET); +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s new file mode 100644 index 0000000..4e08f72 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425.s @@ -0,0 +1,423 @@ +;/*! +; \file startup_gd32f405_425.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD 0 ; 64:Reserved + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD 0 ; 77:Reserved + DCD 0 ; 78:Reserved + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT DMA0_Channel7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT USBHS_EP1_Out_IRQHandler [WEAK] + EXPORT USBHS_EP1_In_IRQHandler [WEAK] + EXPORT USBHS_WKUP_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT DCI_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +DMA0_Channel7_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_DAC_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +USART5_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +USBHS_EP1_Out_IRQHandler +USBHS_EP1_In_IRQHandler +USBHS_WKUP_IRQHandler +USBHS_IRQHandler +DCI_IRQHandler +TRNG_IRQHandler +FPU_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S new file mode 100644 index 0000000..f5a8ba1 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/startup_gd32f405_425_gas.S @@ -0,0 +1,522 @@ +/** \file startup_gd32f405_425_gas.S *************************************** + * + * Startup code for GD32F405 / GD32F425 + * To be used with GCC / GNU Assembler + * and linker scripts gd32f425.ld / gd32f425-tmcm.ld. + * + * Revision History: + * 2023_01_05 Rev 1.00 Olav Kahlbaum File created + * + * -------------------------------------------------------------------- */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + + .global g_pfnVectors + + .word _sidata + .word _sdata + .word _edata + .word _sbss + .word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* top of stack */ + .word Reset_Handler /* Reset Handler */ + .word NMI_Handler /* NMI Handler */ + .word HardFault_Handler /* Hard Fault Handler */ + .word MemManage_Handler /* MPU Fault Handler */ + .word BusFault_Handler /* Bus Fault Handler */ + .word UsageFault_Handler /* Usage Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* SVCall Handler */ + .word DebugMon_Handler /* Debug Monitor Handler */ + .word 0 /* Reserved */ + .word PendSV_Handler /* PendSV Handler */ + .word SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */ + .word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */ + .word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp Interrupt */ + .word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */ + .word FMC_IRQHandler /* Vector Number 20,FMC */ + .word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC*/ + .word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */ + .word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */ + .word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */ + .word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */ + .word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */ + .word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel 0 */ + .word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel 1 */ + .word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel 2 */ + .word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel 3 */ + .word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel 4 */ + .word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel 5 */ + .word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel 6 */ + .word ADC_IRQHandler /* Vector Number 34,ADC0 and ADC1 */ + .word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */ + .word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */ + .word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */ + .word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */ + .word EXTI5_9_IRQHandler /* Vector Number 39,EXTI Line 5 to EXTI Line 9 */ + .word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 global */ + .word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 global */ + .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global */ + .word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */ + .word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */ + .word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */ + .word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */ + .word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */ + .word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */ + .word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */ + .word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */ + .word SPI0_IRQHandler /* Vector Number 51,SPI0 */ + .word SPI1_IRQHandler /* Vector Number 52,SPI1 */ + .word USART0_IRQHandler /* Vector Number 53,USART0 */ + .word USART1_IRQHandler /* Vector Number 54,USART1 */ + .word USART2_IRQHandler /* Vector Number 55,USART2 */ + .word EXTI10_15_IRQHandler /* Vector Number 56,EXTI Line 10 to EXTI Line 15 */ + .word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm through EXTI Line */ + .word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS WakeUp from suspend through EXTI Line */ + .word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break Interrupt and TIMER11 global */ + .word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update Interrupt and TIMER12 global */ + .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 */ + .word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */ + .word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */ + .word 0 /* Vector Number 64,Reserverd */ + .word SDIO_IRQHandler /* Vector Number 65,SDIO */ + .word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */ + .word SPI2_IRQHandler /* Vector Number 67,SPI2 */ + .word UART3_IRQHandler /* Vector Number 68,UART3 */ + .word UART4_IRQHandler /* Vector Number 69,UART4 */ + .word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC */ + .word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */ + .word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */ + .word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */ + .word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */ + .word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */ + .word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */ + .word 0 /* Vector Number 77,Reserved */ + .word 0 /* Vector Number 78,Reserved */ + .word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */ + .word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX 0*/ + .word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */ + .word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */ + .word USBFS_IRQHandler /* Vector Number 83,USBFS */ + .word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */ + .word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */ + .word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */ + .word USART5_IRQHandler /* Vector Number 87,USART5 */ + .word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */ + .word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */ + .word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */ + .word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 In */ + .word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through ETXI Line */ + .word USBHS_IRQHandler /* Vector Number 93,USBHS */ + .word DCI_IRQHandler /* Vector Number 94,DCI */ + .word 0 /* Vector Number 95,Reserved */ + .word TRNG_IRQHandler /* Vector Number 96,TRNG */ + .word FPU_IRQHandler /* Vector Number 97,FPU */ + +/************************************ + * Default interrupt handlers. +*************************************/ + + .weak NMI_Handler +NMI_Handler: + b NMI_Handler + + .weak HardFault_Handler +HardFault_Handler: + b HardFault_Handler + + .weak MemManage_Handler +MemManage_Handler: + b MemManage_Handler + + .weak BusFault_Handler +BusFault_Handler: + b BusFault_Handler + + .weak UsageFault_Handler +UsageFault_Handler: + b UsageFault_Handler + + .weak SVC_Handler +SVC_Handler: + b SVC_Handler + + .weak DebugMon_Handler +DebugMon_Handler: + b DebugMon_Handler + + .weak PendSV_Handler +PendSV_Handler: + b PendSV_Handler + + .weak SysTick_Handler +SysTick_Handler: + b SysTick_Handler + + .weak WWDGT_IRQHandler +WWDGT_IRQHandler: + b WWDGT_IRQHandler + + .weak LVD_IRQHandler +LVD_IRQHandler: + b LVD_IRQHandler + + .weak TAMPER_STAMP_IRQHandler +TAMPER__STAMP_IRQHandler: + b TAMPER_STAMP_IRQHandler + + .weak RTC_WKUP_IRQHandler +RTC_WKUP_IRQHandler: + b RTC_WKUP_IRQHandler + + .weak FMC_IRQHandler +FMC_IRQHandler: + b FMC_IRQHandler + + .weak RCU_CTC_IRQHandler +RCU_CTC_IRQHandler: + b RCU_CTC_IRQHandler + + .weak EXTI0_IRQHandler +EXTI0_IRQHandler: + b EXTI0_IRQHandler + + .weak EXTI1_IRQHandler +EXTI1_IRQHandler: + b EXTI1_IRQHandler + + .weak EXTI2_IRQHandler +EXTI2_IRQHandler: + b EXTI2_IRQHandler + + .weak EXTI3_IRQHandler +EXTI3_IRQHandler: + b EXTI3_IRQHandler + + .weak EXTI4_IRQHandler +EXTI4_IRQHandler: + b EXTI4_IRQHandler + + .weak DMA0_Channel0_IRQHandler +DMA0_Channel0_IRQHandler: + b DMA0_Channel0_IRQHandler + + .weak DMA0_Channel1_IRQHandler +DMA0_Channel1_IRQHandler: + b DMA0_Channel1_IRQHandler + + .weak DMA0_Channel2_IRQHandler +DMA0_Channel2_IRQHandler: + b DMA0_Channel2_IRQHandler + + .weak DMA0_Channel3_IRQHandler +DMA0_Channel3_IRQHandler: + b DMA0_Channel3_IRQHandler + + .weak DMA0_Channel4_IRQHandler +DMA0_Channel4_IRQHandler: + b DMA0_Channel4_IRQHandler + + .weak DMA0_Channel5_IRQHandler +DMA0_Channel5_IRQHandler: + b DMA0_Channel5_IRQHandler + + .weak DMA0_Channel6_IRQHandler +DMA0_Channel6_IRQHandler: + b DMA0_Channel6_IRQHandler + + .weak ADC_IRQHandler +ADC_IRQHandler: + b ADC_IRQHandler + + .weak CAN0_TX_IRQHandler +CAN0_TX_IRQHandler: + b CAN0_TX_IRQHandler + + .weak CAN0_RX0_IRQHandler +CAN0_RX0_IRQHandler: + b CAN0_RX0_IRQHandler + + .weak CAN0_RX1_IRQHandler +CAN0_RX1_IRQHandler: + b CAN0_RX1_IRQHandler + + .weak CAN0_EWMC_IRQHandler +CAN0_EWMC_IRQHandler: + b CAN0_EWMC_IRQHandler + + .weak EXTI5_9_IRQHandler +EXTI5_9_IRQHandler: + b EXTI5_9_IRQHandler + + .weak TIMER0_BRK_TIMER8_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler: + b TIMER0_BRK_TIMER8_IRQHandler + + .weak TIMER0_UP_TIMER9_IRQHandler +TIMER0_UP_TIMER9_IRQHandler: + b TIMER0_UP_TIMER9_IRQHandler + + .weak TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler: + b TIMER0_TRG_CMT_TIMER10_IRQHandler + + .weak TIMER0_Channel_IRQHandler +TIMER0_Channel_IRQHandler: + b TIMER0_Channel_IRQHandler + + .weak TIMER1_IRQHandler +TIMER1_IRQHandler: + b TIMER1_IRQHandler + + .weak TIMER2_IRQHandler +TIMER2_IRQHandler: + b TIMER2_IRQHandler + + .weak TIMER3_IRQHandler +TIMER3_IRQHandler: + b TIMER3_IRQHandler + + .weak I2C0_EV_IRQHandler +I2C0_EV_IRQHandler: + b I2C0_EV_IRQHandler + + .weak I2C0_ER_IRQHandler +I2C0_ER_IRQHandler: + b I2C0_ER_IRQHandler + + .weak I2C1_EV_IRQHandler +I2C1_EV_IRQHandler: + b I2C1_EV_IRQHandler + + .weak I2C1_ER_IRQHandler +I2C1_ER_IRQHandler: + b I2C1_ER_IRQHandler + + .weak SPI0_IRQHandler +SPI0_IRQHandler: + b SPI0_IRQHandler + + .weak SPI1_IRQHandler +SPI1_IRQHandler: + b SPI1_IRQHandler + + .weak USART0_IRQHandler +USART0_IRQHandler: + b USART0_IRQHandler + + .weak USART1_IRQHandler +USART1_IRQHandler: + b USART1_IRQHandler + + .weak USART2_IRQHandler +USART2_IRQHandler: + b USART2_IRQHandler + + .weak EXTI10_15_IRQHandler +EXTI10_15_IRQHandler: + b EXTI10_15_IRQHandler + + .weak RTC_Alarm_IRQHandler +RTC_Alarm_IRQHandler: + b RTC_Alarm_IRQHandler + + .weak USBFS_WKUP_IRQHandler +USBFS_WKUP_IRQHandler: + b USBFS_WKUP_IRQHandler + + .weak TIMER7_BRK_TIMER11_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler: + b TIMER7_BRK_TIMER11_IRQHandler + + .weak TIMER7_UP_TIMER12_IRQHandler +TIMER7_UP_TIMER12_IRQHandler: + b TIMER7_UP_TIMER12_IRQHandler + + .weak TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler: + b TIMER7_TRG_CMT_TIMER13_IRQHandler + + .weak TIMER7_Channel_IRQHandler +TIMER7_Channel_IRQHandler: + b TIMER7_Channel_IRQHandler + + .weak DMA0_Channel7_IRQHandler +DMA0_Channel7_IRQHandler: + b DMA0_Channel7_IRQHandler + + .weak SDIO_IRQHandler +SDIO_IRQHandler: + b SDIO_IRQHandler + + .weak TIMER4_IRQHandler +TIMER4_IRQHandler: + b TIMER4_IRQHandler + + .weak SPI2_IRQHandler +SPI2_IRQHandler: + b SPI2_IRQHandler + + .weak UART3_IRQHandler +UART3_IRQHandler: + b UART3_IRQHandler + + .weak UART4_IRQHandler +UART4_IRQHandler: + b UART4_IRQHandler + + .weak TIMER5_DAC_IRQHandler +TIMER5_DAC_IRQHandler: + b TIMER5_DAC_IRQHandler + + .weak TIMER6_IRQHandler +TIMER6_IRQHandler: + b TIMER6_IRQHandler + + .weak DMA1_Channel0_IRQHandler +DMA1_Channel0_IRQHandler: + b DMA1_Channel0_IRQHandler + + .weak DMA1_Channel1_IRQHandler +DMA1_Channel1_IRQHandler: + b DMA1_Channel1_IRQHandler + + .weak DMA1_Channel2_IRQHandler +DMA1_Channel2_IRQHandler: + b DMA1_Channel2_IRQHandler + + .weak DMA1_Channel3_IRQHandler +DMA1_Channel3_IRQHandler: + b DMA1_Channel3_IRQHandler + + .weak DMA1_Channel4_IRQHandler +DMA1_Channel4_IRQHandler: + b DMA1_Channel4_IRQHandler + + .weak CAN1_TX_IRQHandler +CAN1_TX_IRQHandler: + b CAN1_TX_IRQHandler + + .weak CAN1_RX0_IRQHandler +CAN1_RX0_IRQHandler: + b CAN1_RX0_IRQHandler + + .weak CAN1_RX1_IRQHandler +CAN1_RX1_IRQHandler: + b CAN1_RX1_IRQHandler + + .weak CAN1_EWMC_IRQHandler +CAN1_EWMC_IRQHandler: + b CAN1_EWMC_IRQHandler + + .weak USBFS_IRQHandler +USBFS_IRQHandler: + b USBFS_IRQHandler + + .weak DMA1_Channel5_IRQHandler +DMA1_Channel5_IRQHandler: + b DMA1_Channel5_IRQHandler + + .weak DMA1_Channel6_IRQHandler +DMA1_Channel6_IRQHandler: + b DMA1_Channel6_IRQHandler + + .weak DMA1_Channel7_IRQHandler +DMA1_Channel7_IRQHandler: + b DMA1_Channel7_IRQHandler + + .weak USART5_IRQHandler +USART5_IRQHandler: + b USART5_IRQHandler + + .weak I2C2_EV_IRQHandler +I2C2_EV_IRQHandler: + b I2C2_EV_IRQHandler + + .weak I2C2_ER_IRQHandler +I2C2_ER_IRQHandler: + b I2C2_ER_IRQHandler + + .weak USBHS_EP1_Out_IRQHandler +USBHS_EP1_Out_IRQHandler: + b USBHS_EP1_Out_IRQHandler + + .weak USBHS_EP1_In_IRQHandler +USBHS_EP1_In_IRQHandler: + b USBHS_EP1_In_IRQHandler + + .weak USBHS_WKUP_IRQHandler +USBHS_WKUP_IRQHandler: + b USBHS_WKUP_IRQHandler + + .weak USBHS_IRQHandler +USBHS_IRQHandler: + b USBHS_IRQHandler + + .weak DCI_IRQHandler +DCI_IRQHandler: + b DCI_IRQHandler + + .weak TRNG_IRQHandler +TRNG_IRQHandler: + b TRNG_IRQHandler + + .weak FPU_IRQHandler +FPU_IRQHandler: + b FPU_IRQHandler diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c new file mode 100644 index 0000000..712cf2a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/system_gd32f4xx.c @@ -0,0 +1,1450 @@ +/*! + \file system_gd32f4xx.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F4xx Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f4xx.h" + +/* system frequency define */ +#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M) +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_16M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000) +//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_16M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) +//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_16M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_240M_PLL_IRC16M (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000) +#define __SYSTEM_CLOCK_240M_PLL_16M_HXTAL (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) + +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + +#define SEL_IRC16M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLLP 0x02U + +extern uint32_t g_pfnVectors; + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_IRC16M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M; +static void system_clock_16m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M; +static void system_clock_120m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL; +static void system_clock_120m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_16M_HXTAL; +static void system_clock_120m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL; +static void system_clock_120m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M; +static void system_clock_168m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL; +static void system_clock_168m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_16M_HXTAL; +static void system_clock_168m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL; +static void system_clock_168m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M; +static void system_clock_200m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL; +static void system_clock_200m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_16M_HXTAL; +static void system_clock_200m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL; +static void system_clock_200m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_IRC16M; +static void system_clock_240m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_8M_HXTAL; +static void system_clock_240m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_16M_HXTAL; +static void system_clock_240m_16m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_25M_HXTAL; +static void system_clock_240m_25m_hxtal(void); + +#endif /* __SYSTEM_CLOCK_IRC16M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ + SCB->VTOR=(uint32_t) &g_pfnVectors; + + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCU clock configuration to the default reset state */ + /* Set IRC16MEN bit */ + RCU_CTL |= RCU_CTL_IRC16MEN; + while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + } + RCU_MODIFY(0x50); + + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* Reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + + /* Reset HSEBYP bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* Reset CFG0 register */ + RCU_CFG0 = 0x00000000U; + + /* wait until IRC16M is selected as system clock */ + while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ + } + + /* Reset PLLCFGR register */ + RCU_PLL = 0x24003010U; + + /* Disable all interrupts */ + RCU_INT = 0x00000000U; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + system_clock_config(); + SystemCoreClockUpdate(); +} +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_IRC16M + system_clock_16m_irc16m(); +#elif defined (__SYSTEM_CLOCK_HXTAL) + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) + system_clock_120m_irc16m(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) + system_clock_120m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) + system_clock_120m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) + system_clock_120m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) + system_clock_168m_irc16m(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) + system_clock_168m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) + system_clock_168m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) + system_clock_168m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) + system_clock_200m_irc16m(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) + system_clock_200m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) + system_clock_200m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) + system_clock_200m_25m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) + system_clock_240m_irc16m(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) + system_clock_240m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) + system_clock_240m_16m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) + system_clock_240m_25m_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC16M */ +} + +#ifdef __SYSTEM_CLOCK_IRC16M +/*! + \brief configure the system clock to 16M by IRC16M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_16m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC16M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; + + /* wait until IRC16M is selected as system clock */ + while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ + } +} + +#elif defined (__SYSTEM_CLOCK_HXTAL) +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) +/*! + \brief configure the system clock to 120M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (5U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) +/*! + \brief configure the system clock to 168M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (7U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){ + } + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7 << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(16M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){ + } + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (16U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7 << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_168m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (7U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) +/*! + \brief configure the system clock to 200M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_200m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +/*! + \brief configure the system clock to 240M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (8U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_16M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_16m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (25U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} +#endif /* __SYSTEM_CLOCK_IRC16M */ +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t sws; + uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; + + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC16M is selected as CK_SYS */ + case SEL_IRC16M: + SystemCoreClock = IRC16M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLLP is selected as CK_SYS */ + case SEL_PLLP: + /* get the value of PLLPSC[5:0] */ + pllpsc = GET_BITS(RCU_PLL, 0U, 5U); + plln = GET_BITS(RCU_PLL, 6U, 14U); + pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_PLL & RCU_PLL_PLLSEL); + if (RCU_PLLSRC_HXTAL == pllsel) { + ck_src = HXTAL_VALUE; + } else { + ck_src = IRC16M_VALUE; + } + SystemCoreClock = ((ck_src / pllpsc) * plln) / pllp; + break; + /* IRC16M is selected as CK_SYS */ + default: + SystemCoreClock = IRC16M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock = SystemCoreClock >> clk_exp; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c new file mode 100644 index 0000000..e301175 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/cdc_acm_core.c @@ -0,0 +1,532 @@ +/*! + \file cdc_acm_core.c + \brief CDC ACM driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "cdc_acm_core.h" + +#define USBD_VID 0x2A3CU //Trinamic +#define USBD_PID 0x0700U //Evaluation Device + +/* note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev cdc_dev_desc __ALIGN_END = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +__ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .cmd_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0x00U + }, + + .cdc_header = + { + .header = + { + .bLength = sizeof(usb_desc_header_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x00U, + .bcdCDC = 0x0110U + }, + + .cdc_call_managment = + { + .header = + { + .bLength = sizeof(usb_desc_call_managment_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bmCapabilities = 0x00U, + .bDataInterface = 0x01U + }, + + .cdc_acm = + { + .header = + { + .bLength = sizeof(usb_desc_acm_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bmCapabilities = 0x02U, + }, + + .cdc_union = + { + .header = + { + .bLength = sizeof(usb_desc_union_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x06U, + .bMasterInterface = 0x00U, + .bSlaveInterface0 = 0x01U, + }, + + .cdc_cmd_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = USB_CDC_CMD_PACKET_SIZE, + .bInterval = 0x0AU + }, + + .cdc_data_interface = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = USB_CDC_PROTOCOL_NONE, + .iInterface = 0x00U + }, + + .cdc_out_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_DATA_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + }, + + .cdc_in_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_DATA_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID Descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(23), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'T', 'r', 'i', 'n', 'a', 'm', 'i', 'c', ' ', 'M', 'o', 't', 'i', 'o', 'n', ' ', 'C', 'o', 'n', 't', 'r', 'o', 'l'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(17), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'E', 'v', 'a', 'l', 'u', 'a', 't', 'i', 'o', 'n', ' ', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(7), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'T','M','C','E','V','A','L'} +}; + +/* USB string descriptor set */ +void *const usbd_cdc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc cdc_desc = +{ + .dev_desc = (uint8_t *) &cdc_dev_desc, + .config_desc = (uint8_t *) &cdc_config_desc, + .strings = usbd_cdc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req); +static uint8_t cdc_acm_ctlx_out (usb_dev *udev); +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num); + +/* USB CDC device class callbacks structure */ +usb_class_core cdc_class = +{ + .command = NO_CMD, + .alter_set = 0U, + + .init = cdc_acm_init, + .deinit = cdc_acm_deinit, + .req_proc = cdc_acm_req, + .ctlx_out = cdc_acm_ctlx_out, + .data_in = cdc_acm_in, + .data_out = cdc_acm_out +}; + +/*! + \brief check CDC ACM is ready for data transfer + \param[in] udev: pointer to USB device instance + \param[out] none + \retval 0 if CDC is ready, 5 else +*/ +uint8_t cdc_acm_check_ready(usb_dev *udev) +{ + if (udev->dev.class_data[CDC_COM_INTERFACE] != NULL) { + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) { + return 0U; + } + } + + return 1U; +} + +/*! + \brief send CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_send (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (0U != cdc->receive_length) { + cdc->packet_sent = 0U; + + usbd_ep_send (udev, CDC_DATA_IN_EP, (uint8_t*)(cdc->data), cdc->receive_length); + + cdc->receive_length = 0U; + } +} + +/*! + \brief receive CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_receive (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 0U; + cdc->packet_sent = 0U; + + usbd_ep_recev (udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); +} + +/*! + \brief initialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) +{ + static __ALIGN_BEGIN usb_cdc_handler cdc_handler __ALIGN_END; + + /* initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_in_endpoint)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_out_endpoint)); + + /* initialize the command Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_cmd_endpoint)); + + /* initialize CDC handler structure */ + cdc_handler.packet_receive = 1U; + cdc_handler.packet_sent = 1U; + cdc_handler.receive_length = 0U; + + cdc_handler.line_coding = (acm_line){ + .dwDTERate = 115200U, + .bCharFormat = 0U, + .bParityType = 0U, + .bDataBits = 0x08U + }; + + udev->dev.class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler; + + return USBD_OK; +} + +/*! + \brief deinitialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear (udev, CDC_DATA_IN_EP); + usbd_ep_clear (udev, CDC_DATA_OUT_EP); + + /* deinitialize the command Tx endpoint */ + usbd_ep_clear (udev, CDC_CMD_EP); + + return USBD_OK; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + usb_transc *transc = NULL; + + switch (req->bRequest) { + case SEND_ENCAPSULATED_COMMAND: + /* no operation for this driver */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* no operation for this driver */ + break; + + case SET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case GET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case CLEAR_COMM_FEATURE: + /* no operation for this driver */ + break; + + case SET_LINE_CODING: + transc = &udev->dev.transc_out[0]; + + /* set the value of the current command to be processed */ + udev->dev.class_core->alter_set = req->bRequest; + + /* enable EP0 prepare to receive command data packet */ + transc->remain_len = req->wLength; + transc->xfer_buf = cdc->cmd; + break; + + case GET_LINE_CODING: + transc = &udev->dev.transc_in[0]; + + cdc->cmd[0] = (uint8_t)(cdc->line_coding.dwDTERate); + cdc->cmd[1] = (uint8_t)(cdc->line_coding.dwDTERate >> 8); + cdc->cmd[2] = (uint8_t)(cdc->line_coding.dwDTERate >> 16); + cdc->cmd[3] = (uint8_t)(cdc->line_coding.dwDTERate >> 24); + cdc->cmd[4] = cdc->line_coding.bCharFormat; + cdc->cmd[5] = cdc->line_coding.bParityType; + cdc->cmd[6] = cdc->line_coding.bDataBits; + + transc->xfer_buf = cdc->cmd; + transc->remain_len = 7U; + break; + + case SET_CONTROL_LINE_STATE: + /* no operation for this driver */ + break; + + case SEND_BREAK: + /* no operation for this driver */ + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief command data received on control endpoint + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_ctlx_out (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (udev->dev.class_core->alter_set != NO_CMD) { + /* process the command data */ + cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | + ((uint32_t)cdc->cmd[1] << 8U) | + ((uint32_t)cdc->cmd[2] << 16U) | + ((uint32_t)cdc->cmd[3] << 24U)); + + cdc->line_coding.bCharFormat = cdc->cmd[4]; + cdc->line_coding.bParityType = cdc->cmd[5]; + cdc->line_coding.bDataBits = cdc->cmd[6]; + + udev->dev.class_core->alter_set = NO_CMD; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data in + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) { + usbd_ep_send (udev, ep_num, NULL, 0U); + } else { + cdc->packet_sent = 1U; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data out + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 1U; + cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; + + return USBD_OK; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c new file mode 100644 index 0000000..0382fbe --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_core.c @@ -0,0 +1,374 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/* local function prototypes ('static') */ +static void usb_core_reset (usb_core_regs *usb_regs); + +/*! + \brief configure USB core basic + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + /* configure USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = (uint8_t)USB_SPEED_FULL; + + usb_basic->core_enum = (uint8_t)usb_core; + + switch (usb_core) { + case USB_CORE_ENUM_HS: + usb_basic->base_reg = (uint32_t)USBHS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBHS_MAX_EP_COUNT; + +#ifdef USB_ULPI_PHY_ENABLED + usb_basic->phy_itf = USB_ULPI_PHY; +#else + usb_basic->phy_itf = USB_EMBEDDED_PHY; +#endif /* USB_ULPI_PHY_ENABLED */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + usb_basic->transfer_mode = USB_USE_DMA; +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ + +#ifdef USB_HS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBHS_SOF_OUTPUT; + usb_basic->low_power = USBHS_LOW_POWER; +#endif /* USB_HS_CORE */ + break; + + case USB_CORE_ENUM_FS: + usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + +#ifdef USB_FS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBFS_SOF_OUTPUT; + usb_basic->low_power = USBFS_LOW_POWER; +#endif /* USB_FS_CORE */ + break; + + default: + return USB_FAIL; + } + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (uint8_t i = 0U; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + if (USB_ULPI_PHY == usb_basic.phy_itf) { + usb_regs->gr->GCCFG &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + /* initialize the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif /* USBHS_EXTERNAL_VBUS_ENABLED */ + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable VBUS sensing */ + usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + usb_regs->gr->GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + usb_mdelay(20U); + } + + if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0U) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0U) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks*/ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks */ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief set endpoint or channel TX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo: TX FIFO number + \param[in] size: assigned TX FIFO size + \param[out] none + \retval none +*/ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) +{ + uint32_t tx_offset; + + tx_offset = usb_regs->gr->GRFLEN; + + if(0U == fifo) { + usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; + + for (uint8_t i = 0U; i < (fifo - 1U); i++) { + tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16); + } + + /* multiply Tx_Size by 2 to get higher performance */ + usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } +} + +/*! + \brief set USB current mode + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode) +{ + usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + + if (DEVICE_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FDM; + } else if (HOST_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FHM; + } else { + /* OTG mode and other mode can not be here! */ + } +} + +/*! + \brief configure USB core to soft reset + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) { + /* no operation */ + } + + /* wait for additional 3 PHY clocks */ + usb_udelay(3U); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c new file mode 100644 index 0000000..2998f80 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usb_dev.c @@ -0,0 +1,666 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#endif /* USBFS_CORE */ + +#ifdef USB_HS_CORE + +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_HS_SIZE, + (uint16_t)TX1_FIFO_HS_SIZE, + (uint16_t)TX2_FIFO_HS_SIZE, + (uint16_t)TX3_FIFO_HS_SIZE, + (uint16_t)TX4_FIFO_HS_SIZE, + (uint16_t)TX5_FIFO_HS_SIZE +}; + +#endif /* USBHS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint8_t i; + + /* restart the PHY clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* configure periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); + + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ + for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + if (udev->bp.core_enum == USB_CORE_ENUM_HS) { + if (udev->bp.phy_itf == USB_ULPI_PHY) { + udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; + } else {/* set High speed PHY in Full speed mode */ + udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; + } + + /* Set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_HS_SIZE); + + /* Set endpoint 0 to 6's TX FIFO length and RAM address */ + for (i = 0; i < USBHS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBHS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + (void)usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush entire Rx FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0U; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN; + + (void)usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + return USB_OK; +} + +/*! + \brief active the USB endpoint0 transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB endpoint0 transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + if (ep_num) { + /* not endpoint 0 */ + return USB_FAIL; + } + + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[0]->DIEPCTL; + } else { + reg_addr = &udev->regs.er_out[0]->DOEPCTL; + } + + /* endpoint 0 is activated after USB clock is enabled */ + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint 0 maximum packet length */ + *reg_addr |= EP0_MAXLEN[enum_speed]; + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + + return USB_OK; +} + +/*! + \brief active the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + uint32_t epinten = 0U; + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1U << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1U << (16U + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[enum_speed]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN |= epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + } + + return USB_OK; +} + +/*! + \brief deactivate the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1U << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1U << (ep_num + 16U); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1U) && (udev->bp.core_enum == USB_CORE_ENUM_HS)) { + udev->regs.dr->DEP1INTEN &= ~epinten; + } + else +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + { + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + } + + return USB_OK; +} + +/*! + \brief configure USB transaction to start IN transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB IN transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1U << 19U; + } else { + eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) { + epctl |= DEPCTL_SEVNFRM; + } else { + epctl |= DEPCTL_SODDFRM; + } + } + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0U) { + udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; + } + } else { + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len); + } + } + + return status; +} + +/*! + \brief configure USB transaction to start OUT transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len; + + eplen |= packet_count << 19U; + eplen |= packet_count * transc->max_len; + +#ifdef INT_HIGH_BW + if (transc->ep_type == (uint8_t)USB_EPTYPE_INTR) { + eplen |= DIEPLEN_MCNT & (3U << 29U); + } +#endif /* INT_HIGH_BW */ + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt value +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask, commonintmask; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief active remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5U); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* ungate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief USB device suspend + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); + } +} + +/*! + \brief stop the device and clean up FIFOs + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1U; + + /* clear all interrupt flag and enable bits */ + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + (void)usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c new file mode 100644 index 0000000..309f712 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/drv_usbd_int.c @@ -0,0 +1,590 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +/* local function prototypes ('static') */ +static uint32_t usbd_int_epout (usb_core_driver *udev); +static uint32_t usbd_int_epin (usb_core_driver *udev); +static uint32_t usbd_int_rxfifo (usb_core_driver *udev); +static uint32_t usbd_int_reset (usb_core_driver *udev); +static uint32_t usbd_int_enumfinish (usb_core_driver *udev); +static uint32_t usbd_int_suspend (usb_core_driver *udev); +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_isr (usb_core_driver *udev) +{ + if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if (!intr) { + return; + } + + /* OUT endpoints interrupts */ + if (intr & GINTF_OEPIF) { + (void)usbd_int_epout (udev); + } + + /* IN endpoints interrupts */ + if (intr & GINTF_IEPIF) { + (void)usbd_int_epin (udev); + } + + /* suspend interrupt */ + if (intr & GINTF_SP) { + (void)usbd_int_suspend (udev); + } + + /* wakeup interrupt */ + if (intr & GINTF_WKUPIF) { + /* inform upper layer by the resume event */ + udev->dev.cur_status = USBD_CONFIGURED; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* start of frame interrupt */ + if (intr & GINTF_SOF) { + if (udev->dev.class_core->SOF) { + (void)udev->dev.class_core->SOF(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if (intr & GINTF_RXFNEIF) { + (void)usbd_int_rxfifo (udev); + } + + /* USB reset interrupt */ + if (intr & GINTF_RST) { + (void)usbd_int_reset (udev); + } + + /* enumeration has been done interrupt */ + if (intr & GINTF_ENUMFIF) { + (void)usbd_int_enumfinish (udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if (intr & GINTF_ISOINCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_in) { + (void)udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if (intr & GINTF_ISOONCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_out) { + (void)udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if (intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif /* VBUS_SENSING_ENABLED */ + } +} + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + +/*! + \brief USB dedicated OUT endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev) +{ + uint32_t oepintr = 0U; + uint32_t oeplen = 0U; + + oepintr = udev->regs.er_out[1]->DOEPINTF; + oepintr &= udev->regs.dr->DOEP1INTEN; + + /* transfer complete */ + if(oepintr & DOEPINTF_TF){ + /* clear the bit in DOEPINTn for this interrupt */ + udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; + + if(USB_USE_DMA == udev->bp.transfer_mode){ + oeplen = udev->regs.er_out[1]->DOEPLEN; + + /* to do : handle more than one single max packet size packet */ + udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].max_len - \ + (oeplen & DEPLEN_TLEN); + } + + /* rx complete */ + usbd_out_transc (udev, 1U); + } + + return 1U; +} + +/*! + \brief USB dedicated IN endpoint 1 interrupt service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev) +{ + uint32_t inten, intr, emptyen; + + inten = udev->regs.dr->DIEP1INTEN; + emptyen = udev->regs.dr->DIEPFEINTEN; + + inten |= ((emptyen >> 1 ) & 0x1) << 7; + + intr = udev->regs.er_in[1]->DIEPINTF & inten; + + if(intr & DIEPINTF_TF){ + udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF; + + /* TX complete */ + usbd_in_transc (udev, 1); + } + + if(intr & DIEPINTF_TXFE){ + usbd_emptytxfifo_write(udev, 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE; + } + + return 1; +} + +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x01U) { + __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num); + + /* transfer complete interrupt */ + if (oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ + (eplen & DEPLEN_TLEN); + } + + /* inform upper layer: data ready */ + (void)usbd_out_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + /* setup phase finished interrupt (control endpoints) */ + if (oepintr & DOEPINTF_STPF) { + /* inform the upper layer that a setup packet is available */ + (void)usbd_setup_transc (udev); + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + } + } + } + + return 1U; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num); + + if (iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmission is completed */ + (void)usbd_in_transc (udev, ep_num); + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + if (iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write (udev, (uint32_t)ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1U; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo (usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0U; + uint32_t bcount = 0U; + + __IO uint32_t devrxstat = 0U; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM); + + transc = &udev->dev.transc_out[ep_num]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; + data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + #ifndef USE_450Z_EVAL + /* ensure no-DMA mode can work */ + if (0U == (udev->regs.er_out[ep_num]->DOEPLEN & DEPLEN_PCNT)) { + uint32_t devepctl = udev->regs.er_out[ep_num]->DOEPCTL; + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + udev->regs.er_out[ep_num]->DOEPCTL = devepctl; + } + #endif /* USE_450Z_EVAL */ +#endif /* USE_USB_HS && USE_ULPI_PHY */ + + switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if (bcount > 0U) { + (void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + (void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount); + + transc->xfer_count += bcount; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset (usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + (void)usb_txfifo_flush (&udev->regs, 0U); + + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16U); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + udev->regs.dr->DIEP1INTEN = DIEPINTEN_TFEN; +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout (udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1U + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_in[0]); + + /* upon reset call user call back */ + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + + return 1U; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish (usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) { + udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09U << 10U; + } else { + udev->bp.core_speed = (uint8_t)USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05U << 10U; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1U; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend (usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the OTG clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num) +{ + uint32_t len; + uint32_t word_count; + + usb_transc *transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if (len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3U) / 4U; + + while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if (len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3U) / 4U; + + /* write the FIFO */ + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if (transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num); + } + } + + return 1U; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c new file mode 100644 index 0000000..d904084 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_core.c @@ -0,0 +1,324 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_enum.h" +#include "drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = (uint32_t)USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = (uint32_t)USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = (uint32_t)USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = (uint32_t)USB_EPTYPE_ISOC +}; + +/*! + \brief initializes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: USB core type + \param[in] desc: pointer to USB descriptor + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core) +{ + udev->dev.desc = desc; + + /* class callbacks */ + udev->dev.class_core = class_core; + +#if USB_USE_UNIQUE_SERIAL_NUMBER + /* create serial string */ + serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]); +#endif + + /* configure USB capabilities */ + (void)usb_basic_init (&udev->bp, &udev->regs, core); + + usb_globalint_disable(&udev->regs); + + /* initializes the USB core*/ + (void)usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + +#ifndef USE_OTG_MODE + usb_curmode_set(&udev->regs, DEVICE_MODE); +#endif /* USE_OTG_MODE */ + + /* initializes device mode */ + (void)usb_devcore_init (udev); + + usb_globalint_enable(&udev->regs); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint16_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = (uint8_t)ep_type[ep_desc->bmAttributes & (uint8_t)USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + (void)usb_transc_active (udev, transc); + + return 0U; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactivate USB endpoint function */ + (void)usb_transc_deactivate (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_outxfer (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_inxfer (udev, transc); + + return 0U; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1U; + + (void)usb_transc_stall (udev, transc); + + return (0U); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0U; + + (void)usb_transc_clrstall (udev, transc); + + return (0U); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + (void)usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + (void)usb_rxfifo_flush (&udev->regs); + } + + return (0U); +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c new file mode 100644 index 0000000..95718bb --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_enum.c @@ -0,0 +1,820 @@ +/*! + \file usbd_enum.c + \brief USB enumeration function + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +#ifdef WINUSB_EXEMPT_DRIVER + +extern usbd_status usbd_OEM_req(usb_dev *udev, usb_req *req); + +#endif /* WINUSB_EXEMPT_DRIVER */ + +/* local function prototypes ('static') */ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#endif +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); + +static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = +{ + [USB_GET_STATUS] = _usb_std_getstatus, + [USB_CLEAR_FEATURE] = _usb_std_clearfeature, + [USB_RESERVED2] = _usb_std_reserved, + [USB_SET_FEATURE] = _usb_std_setfeature, + [USB_RESERVED4] = _usb_std_reserved, + [USB_SET_ADDRESS] = _usb_std_setaddress, + [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, + [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, + [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, + [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, + [USB_GET_INTERFACE] = _usb_std_getinterface, + [USB_SET_INTERFACE] = _usb_std_setinterface, + [USB_SYNCH_FRAME] = _usb_std_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { + [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, + [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, + [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get, +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + [(uint8_t)USB_DESCTYPE_DEV_QUALIFIER - 3U] = _usb_qualifier_desc_get, + [(uint8_t)USB_DESCTYPE_OTHER_SPD_CONFIG - 3U] = _usb_other_speed_config_desc_get, +#endif +}; + +/*! + \brief handle USB standard device request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req) +{ + return (*_std_dev_req[req->bRequest])(udev, req); +} + +/*! + \brief handle USB device class request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req) +{ + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + return (usb_reqsta)udev->dev.class_core->req_proc(udev, req); + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB vendor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* added by user... */ +#ifdef WINUSB_EXEMPT_DRIVER + usbd_OEM_req(udev, req); +#endif + + return REQ_SUPP; +} + +/*! + \brief handle USB enumeration error + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + (void)usbd_ep_stall (udev, 0x80U); + (void)usbd_ep_stall (udev, 0x00U); + + usb_ctlep_startout(udev); +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] value: hex 32bits value + \param[in] pbuf: buffer pointer to store unicode char + \param[in] len: value length + \param[out] none + \retval none +*/ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len) +{ + uint8_t index; + + for (index = 0U; index < len; index++) { + if ((value >> 28U) < 0x0AU) { + pbuf[2U * index] = (uint8_t)((value >> 28U) + '0'); + } else { + pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); + } + + value = value << 4U; + + pbuf[2U * index + 1U] = 0U; + } +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] unicode_str: pointer to unicode string + \param[out] none + \retval none +*/ +void serial_string_get (uint16_t *unicode_str) +{ + if ((unicode_str[0] & 0x00FFU) != 6U) { + uint32_t DeviceSerial0, DeviceSerial1, DeviceSerial2; + + DeviceSerial0 = *(uint32_t*)DEVICE_ID1; + DeviceSerial1 = *(uint32_t*)DEVICE_ID2; + DeviceSerial2 = *(uint32_t*)DEVICE_ID3; + + DeviceSerial0 += DeviceSerial2; + + if (0U != DeviceSerial0) { + int_to_unicode(DeviceSerial0, (uint8_t*)&(unicode_str[1]), 8U); + int_to_unicode(DeviceSerial1, (uint8_t*)&(unicode_str[9]), 4U); + } + } else { + uint32_t device_serial = *(uint32_t*)DEVICE_ID; + + if(0U != device_serial) { + unicode_str[1] = (uint16_t)(device_serial & 0x0000FFFFU); + unicode_str[2] = (uint16_t)((device_serial & 0xFFFF0000U) >> 16U); + + } + } +} + +/*! + \brief no operation, just for reserved + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no operation... */ + + return REQ_NOTSUPP; +} + +/*! + \brief get the device descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->dev_desc[0]; + + return udev->dev.desc->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->config_desc[2] | (udev->dev.desc->config_desc[3]<< 8U); + + return udev->dev.desc->config_desc; +} + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->other_speed_config_desc[2]; + + return udev->dev.desc->other_speed_config_desc; +} + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->qualifier_desc[0]; + + return udev->dev.desc->qualifier_desc; +} + +#endif /* USE_USB_HS && USE_ULPI_PHY */ + +/*! + \brief get the BOS descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->bos_desc[2]; + + return udev->dev.desc->bos_desc; +} + +/*! + \brief get string descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] len: pointer to string length + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + uint8_t *desc = udev->dev.desc->strings[index]; + + *len = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req) +{ + uint8_t recp = BYTE_LOW(req->wIndex); + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + static uint8_t status[2] = {0}; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + if (udev->dev.pm.power_mode) { + status[0] = USB_STATUS_SELF_POWERED; + } else { + status[0] = 0U; + } + + if (udev->dev.pm.dev_remote_wakeup) { + status[0] |= USB_STATUS_REMOTE_WAKEUP; + } else { + status[0] = 0U; + } + + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + if (((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_EP: + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (0x80U == (recp & 0x80U)) { + status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; + } else { + status[0] = udev->dev.transc_out[recp].ep_stall; + } + + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = status; + transc->remain_len = 2U; + } + + return req_status; +} + +/*! + \brief handle USB Clear_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + /* clear device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 0U; + + return REQ_SUPP; + } + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* clear endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall_clear (udev, ep); + + (void)udev->dev.class_core->req_proc (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch (req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + /* set device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 1U; + } + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* set endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall (udev, ep); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Address request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (udev->dev.cur_status != (uint8_t)USBD_CONFIGURED) { + usbd_addr_set (udev, udev->dev.dev_addr); + + if (udev->dev.dev_addr) { + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else { + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + } + + return REQ_SUPP; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) +{ + uint8_t desc_type = 0U; + uint8_t desc_index = 0U; + + usb_reqsta status = REQ_NOTSUPP; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* get device standard descriptor */ + switch (req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + desc_type = BYTE_HIGH(req->wValue); + desc_index = BYTE_LOW(req->wValue); + + switch (desc_type) { + case USB_DESCTYPE_DEV: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + + if (64U == req->wLength) { + transc->remain_len = 8U; + } + break; + + case USB_DESCTYPE_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_STR: + if (desc_index < (uint8_t)STR_IDX_MAX) { + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + } + break; + + case USB_DESCTYPE_ITF: + case USB_DESCTYPE_EP: + break; + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + case USB_DESCTYPE_DEV_QUALIFIER: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_OTHER_SPD_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; +#endif + + case USB_DESCTYPE_ITF_POWER: + break; + + case USB_DESCTYPE_BOS: + transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + default: + break; + } + break; + + case USB_RECPTYPE_ITF: + /* get device class special descriptor */ + status = (usb_reqsta)(udev->dev.class_core->req_proc(udev, req)); + break; + + case USB_RECPTYPE_EP: + break; + + default: + break; + } + + if ((0U != transc->remain_len) && (0U != req->wLength)) { + if (transc->remain_len < req->wLength) { + if ((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { + udev->dev.control.ctl_zlp = 1U; + } + } else { + transc->remain_len = req->wLength; + } + + status = REQ_SUPP; + } + + return status; +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB Get_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (USB_DEFAULT_CONFIG == udev->dev.config) { + req_status = REQ_SUPP; + } + break; + + case USBD_CONFIGURED: + if (udev->dev.config != USB_DEFAULT_CONFIG) { + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + } + + return req_status; +} + +/*! + \brief handle USB Set_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req) +{ + static uint8_t config; + usb_reqsta status = REQ_NOTSUPP; + + config = (uint8_t)(req->wValue); + + if (config <= USBD_CFG_MAX_NUM) { + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (config){ + (void)udev->dev.class_core->init(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_CONFIGURED; + } + + status = REQ_SUPP; + break; + + case USBD_CONFIGURED: + if (USB_DEFAULT_CONFIG == config) { + (void)udev->dev.class_core->deinit(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else if (config != udev->dev.config) { + /* clear old configuration */ + (void)udev->dev.class_core->deinit(udev, config); + + /* set new configuration */ + udev->dev.config = config; + + (void)udev->dev.class_core->init(udev, config); + } else { + /* no operation */ + } + + status = REQ_SUPP; + break; + + case USBD_DEFAULT: + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief handle USB Get_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + usb_transc *transc = &udev->dev.transc_in[0]; + + transc->xfer_buf = &(udev->dev.class_core->alter_set); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != udev->dev.class_core->set_intf) { + (void)udev->dev.class_core->set_intf (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB SynchFrame request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle */ + return REQ_SUPP; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c new file mode 100644 index 0000000..c8e7adb --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/GigaDevice/lib/src/usb/usbd_transc.c @@ -0,0 +1,266 @@ +/*! + \file usbd_transc.c + \brief USB transaction core functions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_transc.h" + +/*! + \brief USB send data in the control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_send (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + (void)usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_IN; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_IN; + } + + return USBD_OK; +} + +/*! + \brief USB receive data in control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_recev (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + + (void)usbd_ep_recev (udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_OUT; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_OUT; + } + + return USBD_OK; +} + +/*! + \brief USB send control transaction status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_send (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_IN; + + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB control receive status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_OUT; + + (void)usbd_ep_recev (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB setup stage processing + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_setup_transc (usb_core_driver *udev) +{ + usb_reqsta reqstat = REQ_NOTSUPP; + + usb_req req = udev->dev.control.req; + + switch (req.bmRequestType & USB_REQTYPE_MASK) { + /* standard device request */ + case USB_REQTYPE_STRD: + reqstat = usbd_standard_request (udev, &req); + break; + + /* device class request */ + case USB_REQTYPE_CLASS: + reqstat = usbd_class_request (udev, &req); + break; + + /* vendor defined request */ + case USB_REQTYPE_VENDOR: + reqstat = usbd_vendor_request (udev, &req); + break; + + default: + break; + } + + if (REQ_SUPP == reqstat) { + if (0U == req.wLength) { + (void)usbd_ctl_status_send (udev); + } else { + if (req.bmRequestType & 0x80U) { + (void)usbd_ctl_send (udev); + } else { + (void)usbd_ctl_recev (udev); + } + } + } else { + usbd_enum_error (udev, &req); + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_out[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_OUT: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_recev (udev); + break; + + case USB_CTL_LAST_DATA_OUT: + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_out != NULL) { + (void)udev->dev.class_core->ctlx_out (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_send (udev); + break; + + default: + break; + } + } else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)) { + (void)udev->dev.class_core->data_out (udev, ep_num); + } else { + /* no operation */ + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_IN: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_send (udev); + break; + + case USB_CTL_LAST_DATA_IN: + /* last packet is MPS multiple, so send ZLP packet */ + if (udev->dev.control.ctl_zlp) { + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + udev->dev.control.ctl_zlp = 0U; + } else { + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_in != NULL) { + (void)udev->dev.class_core->ctlx_in (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_recev (udev); + } + break; + + default: + break; + } + } else { + if ((udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { + (void)udev->dev.class_core->data_in (udev, ep_num); + } + } + + return (uint8_t)USBD_OK; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h new file mode 100644 index 0000000..de7218d --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/makeFor.h @@ -0,0 +1,9 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef LandungsbrueckeV3 + #define LandungsbrueckeV3 +#endif diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c new file mode 100644 index 0000000..aadc75e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/ADCs.c @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include +#include "hal/HAL.h" +#include "hal/ADCs.h" + +#define ADC1_DR_ADDRESS ((uint32_t)0x4001204C) + +static void init(void); +static void deInit(void); + +ADCTypeDef ADCs = +{ + .AIN0 = &ADCValue[0], + .AIN1 = &ADCValue[1], + .AIN2 = &ADCValue[2], + .DIO4 = &ADCValue[3], + .DIO5 = &ADCValue[4], + .VM = &ADCValue[5], + .AIN_EXT = &ADCValue[6], + .init = init, + .deInit = deInit, +}; + +void init(void) +{ + adc_deinit(); + + rcu_periph_clock_enable(RCU_DMA1); + rcu_periph_clock_enable(RCU_ADC0); + + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->ADC_VM); + + dma_deinit(DMA1, DMA_CH0); + + dma_multi_data_parameter_struct dma_init_struct; + dma_multi_data_para_struct_init(&dma_init_struct); + dma_init_struct.periph_addr = (uint32_t) (ADC0 + 0x4CU); + dma_init_struct.periph_width = DMA_PERIPH_WIDTH_16BIT; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory0_addr = (uint32_t)&ADCValue[0]; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_burst_width = DMA_MEMORY_BURST_SINGLE; + dma_init_struct.periph_burst_width = DMA_PERIPH_BURST_SINGLE; + dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_ENABLE; + dma_init_struct.direction = DMA_PERIPH_TO_MEMORY; + dma_init_struct.number = N_O_ADC_CHANNELS; + dma_init_struct.critical_value = DMA_FIFO_2_WORD; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_multi_data_mode_init(DMA1, DMA_CH0, &dma_init_struct); + + dma_channel_enable(DMA1, DMA_CH0); + + adc_clock_config(ADC_ADCCK_PCLK2_DIV2); + adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT); + adc_sync_delay_config(ADC_SYNC_DELAY_5CYCLE); + adc_resolution_config(ADC0, ADC_RESOLUTION_12B); + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE); + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(ADC0, ADC_ROUTINE_CHANNEL, N_O_ADC_CHANNELS); + adc_dma_mode_enable(ADC0); + + adc_routine_channel_config(ADC0, 0, ADC_CHANNEL_14, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 1, ADC_CHANNEL_15, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 2, ADC_CHANNEL_8, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 3, ADC_CHANNEL_0, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 4, ADC_CHANNEL_1, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 5, ADC_CHANNEL_3, ADC_SAMPLETIME_15); + adc_routine_channel_config(ADC0, 6, ADC_CHANNEL_2, ADC_SAMPLETIME_15); + + adc_dma_request_after_last_enable(ADC0); + + adc_enable(ADC0); + + adc_calibration_enable(ADC0); + + adc_software_trigger_enable(ADC0, ADC_ROUTINE_CHANNEL); +} + +static void deInit(void) +{ + adc_deinit(); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c new file mode 100644 index 0000000..ae93397 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/HAL.c @@ -0,0 +1,101 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/derivative.h" +#include "hal/HAL.h" + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +static void init(void); +static void reset(uint8_t ResetPeripherals); +static void NVIC_DeInit(void); + +uint8_t hwid = 0; + +static const IOsFunctionsTypeDef IOFunctions = +{ + .config = &IOs, + .pins = &IOMap, +}; + +const HALTypeDef HAL = +{ + .init = init, + .reset = reset, + .NVIC_DeInit = NVIC_DeInit, + .SPI = &SPI, + .USB = &USB, + .LEDs = &LEDs, + .ADCs = &ADCs, + .IOs = &IOFunctions, + .RS232 = &RS232, + .WLAN = &WLAN, + .Timer = &Timer, + .UART = &UART +}; + +static void init(void) +{ + nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0); + __enable_irq(); + + systick_init(); + wait(100); + + IOs.init(); + IOMap.init(); + USB.init(); + SPI.init(); + RS232.init(); + LEDs.init(); + ADCs.init(); + WLAN.init(); +} + +static void __attribute((noreturn)) reset(uint8_t ResetPeripherals) +{ + // Disable interrupts + __disable_irq(); + + if(ResetPeripherals) + SCB->AIRCR = AIRCR_VECTKEY_MASK | SCB_AIRCR_SYSRESETREQ_Msk; + else + SCB->AIRCR = AIRCR_VECTKEY_MASK | SCB_AIRCR_VECTRESET_Msk; + + // SYSRESETREQ does not happen instantly since peripheral reset timing is not specified. + // Trap execution here so nothing else happens until the reset completes. + while(1); +} + +static void NVIC_DeInit(void) +{ + uint32_t index; + + for(index=0; index<8; index++) + { + NVIC->ICER[index] = 0xFFFFFFFF; + NVIC->ICPR[index] = 0xFFFFFFFF; + } + + for(index = 0; index < 240; index++) + { + NVIC->IP[index] = 0x00000000; + } +} + +void _exit(int32_t i) // function has the attribute noreturn per default +{ + UNUSED(i); + while(1) {}; +} + +void _kill(void) +{ +} + +void _getpid(void) +{ +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c new file mode 100644 index 0000000..4de6cbd --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOMap.c @@ -0,0 +1,1208 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/IOMap.h" +#include "hal/HAL.h" + +static void init(); + +static IOPinTypeDef *_pins[] = +{ + &IOMap.ID_CLK, // 0 + &IOMap.ID_CH0, // 1 + &IOMap.ID_CH1, // 2 + &IOMap.DIO0, // 3 + &IOMap.DIO1, // 4 + &IOMap.DIO2, // 5 + &IOMap.DIO3, // 6 + &IOMap.DIO4, // 7 + &IOMap.DIO5, // 8 + &IOMap.DIO6, // 9 + &IOMap.DIO7, // 10 + &IOMap.DIO8, // 11 + &IOMap.DIO9, // 12 + &IOMap.DIO10, // 13 + &IOMap.DIO10_PWM_WL, // 14 + &IOMap.DIO10_UART_TX, // 15 + &IOMap.DIO11, // 16 + &IOMap.DIO11_PWM_WH, // 17 + &IOMap.DIO11_UART_RX, // 18 + &IOMap.SW_UART_PWM, // 19 + &IOMap.CLK16, // 20 + &IOMap.SPI2_CSN0, // 21 + &IOMap.SPI2_CSN1, // 22 + &IOMap.SPI2_CSN2, // 23 + &IOMap.SPI2_SCK, // 24 + &IOMap.SPI2_SDO, // 25 + &IOMap.SPI2_SDI, // 26 + &IOMap.SPI1_CSN, // 27 + &IOMap.SPI1_SCK, // 28 + &IOMap.SPI1_SDI, // 29 + &IOMap.SPI1_SDO, // 30 + &IOMap.DIO12, // 31 + &IOMap.DIO13, // 32 + &IOMap.DIO14, // 33 + &IOMap.DIO15, // 34 + &IOMap.DIO16, // 35 + &IOMap.DIO17, // 36 + &IOMap.DIO18, // 37 + &IOMap.DIO19, // 38 + &IOMap.RS232_TX, // 39 + &IOMap.RS232_RX, // 40 + &IOMap.USB_V_BUS, // 41 + &IOMap.USB_V_DM, // 42 + &IOMap.USB_V_DP, // 43 + &IOMap.LED_STAT, // 44 + &IOMap.LED_ERROR, // 45 + &IOMap.EXT0, // 46 + &IOMap.EXT1, // 47 + &IOMap.EXT2, // 48 + &IOMap.EXT3, // 49 + &IOMap.EXT4, // 50 + &IOMap.EEPROM_SCK, // 51 + &IOMap.EEPROM_SI, // 52 + &IOMap.EEPROM_SO, // 53 + &IOMap.EEPROM_NCS, // 54 + &IOMap.ADC_VM, // 56 + &IOMap.AIN0, // 57 + &IOMap.AIN1, // 58 + &IOMap.AIN2, // 59 + &IOMap.WIFI_EN, // 60 + &IOMap.WIFI_RST, // 61 + &IOMap.WIFI_TX, // 62 + &IOMap.WIFI_RX, // 63 + &IOMap.BUTTON, // 64 + &IOMap.DUMMY, // 65 +}; +IOPinMapTypeDef IOMap = +{ + .init = init, + .pins = &_pins[0], + .ID_CLK = // IOPinTypeDef ID_CLK + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ID_CH0 = // IOPinTypeDef ID_CH0 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ID_CH1 = // IOPinTypeDef ID_CH1 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO0 = // IOPinTypeDef DIO0 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 2, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO1 = // IOPinTypeDef DIO1 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO2 = // IOPinTypeDef + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO3 = // IOPinTypeDef DIO3 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO4 = // IOPinTypeDef DIO4 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO5 = // IOPinTypeDef DIO5 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO6 = // IOPinTypeDef DIO6 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO7 = // IOPinTypeDef DIO7 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO8 = // IOPinTypeDef DIO8 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO9 = // IOPinTypeDef DIO9 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO10 = // IOPinTypeDef DIO10 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO10_PWM_WL = // IOPinTypeDef DIO10_PWM_WL + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO10_UART_TX = // IOPinTypeDef DIO10_UART_TX + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO11 = // IOPinTypeDef DIO11 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO11_PWM_WH = // IOPinTypeDef DIO11_PWM_WH + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_13, // uint32_t pinBitWeight + .bit = 13, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .DIO11_UART_RX = // IOPinTypeDef DIO11_UART_RX + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .SW_UART_PWM = // IOPinTypeDef SW_UART_PWM + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 2, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + .CLK16 = // IOPinTypeDef CLK16 + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN0 = // IOPinTypeDef SPI2_CSN0 + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN1 = // IOPinTypeDef SPI2_CSN1 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_14, // uint32_t pinBitWeight + .bit = 14, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_CSN2 = // IOPinTypeDef SPI2_CSN2 + { + .setBitRegister = &(GPIO_BOP(GPIOE)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOE)), // __IO uint16_t *resetBitRegister + .port = GPIOE, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SCK = // IOPinTypeDef SPI2_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SDO = // IOPinTypeDef SPI2_SDO + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI2_SDI = // IOPinTypeDef SPI2_SDI + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_CSN = // IOPinTypeDef SPI1_CSN + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SCK = // IOPinTypeDef SPI1_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_13, // uint32_t pinBitWeight + .bit = 13, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SDI = // IOPinTypeDef SPI1_SDI + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .SPI1_SDO = // IOPinTypeDef SPI1_SDO + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_14, // uint32_t pinBitWeight + .bit = 14, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO12 = // IOPinTypeDef DIO12 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_8, // uint32_t pinBitWeight + .bit = 8, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO13 = // IOPinTypeDef DIO13 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO14 = // IOPinTypeDef DIO14 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO15 = // IOPinTypeDef DIO15 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO16 = // IOPinTypeDef DIO016 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO17 = // IOPinTypeDef DIO017 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO18 = // IOPinTypeDef DIO18 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .DIO19 = // IOPinTypeDef DIO19 + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .RS232_TX = // IOPinTypeDef RS232_TX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .RS232_RX = // IOPinTypeDef RS232_RX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // uint32_t pinBitWeight + .bit = -1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_BUS = // IOPinTypeDef USB_V_BUS + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_9, // uint32_t pinBitWeight + .bit = 9, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_DM = // IOPinTypeDef USB_V_DM + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .USB_V_DP = // IOPinTypeDef USB_V_DP + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .LED_STAT = // IOPinTypeDef LED_STAT + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .LED_ERROR = // IOPinTypeDef LED_ERROR + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_1, // uint32_t pinBitWeight + .bit = 1, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT0 = // IOPinTypeDef EXT0 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT1 = // IOPinTypeDef EXT1 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT2 = // IOPinTypeDef EXT2 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT3 = // IOPinTypeDef EXT3 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EXT4 = // IOPinTypeDef EXT4 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_MAX, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SCK = // IOPinTypeDef EEPROM_SCK + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_10, // uint32_t pinBitWeight + .bit = 10, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SI = // IOPinTypeDef EEPROM_SI + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_12, // uint32_t pinBitWeight + .bit = 12, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_SO = // IOPinTypeDef EEPROM_SO + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_11, // uint32_t pinBitWeight + .bit = 11, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .EEPROM_NCS = // IOPinTypeDef EEPROM_NCS + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_15, // uint32_t pinBitWeight + .bit = 15, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_OUTPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .ADC_VM = // IOPinTypeDef ADC_VM + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN0 = // IOPinTypeDef AIN0 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN1 = // IOPinTypeDef AIN1 + { + .setBitRegister = &(GPIO_BOP(GPIOC)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOC)), // __IO uint16_t *resetBitRegister + .port = GPIOC, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN2 = // IOPinTypeDef AIN2 + { + .setBitRegister = &(GPIO_BOP(GPIOB)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOB)), // __IO uint16_t *resetBitRegister + .port = GPIOB, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_0, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .AIN_EXT = // IOPinTypeDef AIN_EXT + { + .setBitRegister = &(GPIO_BOP(GPIOA)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOA)), // __IO uint16_t *resetBitRegister + .port = GPIOA, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_2, // uint32_t pinBitWeight + .bit = 0, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_ANALOG, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_EN = // IOPinTypeDef WIFI_EN + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_7, // uint32_t pinBitWeight + .bit = 7, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_RST = // IOPinTypeDef WIFI_RST + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_4, // uint32_t pinBitWeight + .bit = 4, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_TX = // IOPinTypeDef WIFI_TX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_5, // uint32_t pinBitWeight + .bit = 5, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .WIFI_RX = // IOPinTypeDef WIFI_RX + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_6, // uint32_t pinBitWeight + .bit = 6, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_AF, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + }, + + .BUTTON = // IOPinTypeDef BUTTON + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = GPIO_PIN_3, // uint32_t pinBitWeight + .bit = 3, // unsigned char bit + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd - There is an external pull-down connected. + } + }, + + .DUMMY = // IOPinTypeDef + { + .setBitRegister = &(GPIO_BOP(GPIOD)), // __IO uint16_t *setBitRegister + .resetBitRegister = &(GPIO_BC(GPIOD)), // __IO uint16_t *resetBitRegister + .port = GPIOD, // GPIO_TypeDef *port + .bitWeight = DUMMY_BITWEIGHT, // invalid + .bit = -1, // invalid + .resetConfiguration = + { + .GPIO_Mode = GPIO_MODE_INPUT, // GPIOMode_TypeDef GPIO_Mode + .GPIO_OType = GPIO_OTYPE_PP, // GPIOSpeed_TypeDef GPIO_Speed + .GPIO_Speed = GPIO_OSPEED_50MHZ, // GPIOOType_TypeDef GPIO_OType + .GPIO_PuPd = GPIO_PUPD_NONE // GPIOPuPd_TypeDef GPIO_PuPd + } + } +}; + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CLK); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH0); + HAL.IOs->config->reset(&HAL.IOs->pins->ID_CH1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO0); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO1); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO3); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO4); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO5); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO6); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO7); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO8); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO9); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_PWM_WL); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_UART_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_PWM_WH); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_UART_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->SW_UART_PWM); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_CSN2); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI2_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_CSN); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDI); + HAL.IOs->config->reset(&HAL.IOs->pins->SPI1_SDO); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO12); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO13); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO14); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO15); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO16); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO19); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->RS232_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_BUS); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DM); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DP); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT0); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT1); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT2); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT3); + HAL.IOs->config->reset(&HAL.IOs->pins->EXT4); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SCK); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SI); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_SO); + HAL.IOs->config->reset(&HAL.IOs->pins->EEPROM_NCS); + HAL.IOs->config->reset(&HAL.IOs->pins->ADC_VM); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN0); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN1); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN2); + HAL.IOs->config->reset(&HAL.IOs->pins->AIN_EXT); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_EN); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_RST); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->WIFI_RX); + HAL.IOs->config->reset(&HAL.IOs->pins->CLK16); + gpio_af_set(HAL.IOs->pins->CLK16.port, GPIO_AF_0, HAL.IOs->pins->CLK16.bitWeight); + // By default DIO10 and DIO11 are connected to DIO10_PWM_WL and DIO11_PWM_WH respectively. + *HAL.IOs->pins->SW_UART_PWM.setBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c new file mode 100644 index 0000000..a913e24 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/IOs.c @@ -0,0 +1,172 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/IOs.h" + + +static void init(); +static void setPinConfiguration(IOPinTypeDef *pin); +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef*to); +static void resetPinConfiguration(IOPinTypeDef *pin); +static void setPin2Output(IOPinTypeDef *pin); +static void setPin2Input(IOPinTypeDef *pin); +static void setPinHigh(IOPinTypeDef *pin); +static void setPinLow(IOPinTypeDef *pin); +static void setPinState(IOPinTypeDef *pin, IO_States state); +static IO_States getPinState(IOPinTypeDef *pin); +static unsigned char isPinHigh(IOPinTypeDef *pin); + +IOsTypeDef IOs = +{ + .init = init, + .set = setPinConfiguration, + .reset = resetPinConfiguration, + .copy = copyPinConfiguration, + .toOutput = setPin2Output, + .toInput = setPin2Input, + .setHigh = setPinHigh, + .setLow = setPinLow, + .setToState = setPinState, + .getState = getPinState, + .isHigh = isPinHigh, + .HIGH_LEVEL_FUNCTIONS = + { + .DEFAULT = IO_DEFAULT, + .DI = IO_DI, + .AI = IO_AI, + .DO = IO_DO, + .PWM = IO_PWM, + .SD = IO_SD, + .CLK16 = IO_CLK16, + .SPI = IO_SPI + } +}; + +static void init() +{ + + rcu_periph_clock_enable(RCU_SYSCFG); + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + rcu_ckout0_config(RCU_CKOUT0SRC_HXTAL, RCU_CKOUT0_DIV1); + +} + +static void setPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + gpio_mode_set(pin->port, pin->configuration.GPIO_Mode, pin->configuration.GPIO_PuPd, pin->bitWeight); + gpio_output_options_set(pin->port, pin->configuration.GPIO_OType, pin->configuration.GPIO_Speed, pin->bitWeight); + +} + +static void setPin2Output(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + setPinConfiguration(pin); +} + +static void setPin2Input(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + pin->configuration.GPIO_Mode = GPIO_MODE_INPUT; + setPinConfiguration(pin); +} + +static void setPinState(IOPinTypeDef *pin, IO_States state) +{ + if(IS_DUMMY_PIN(pin)) + return; + switch(state) + { + case IOS_LOW: + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + *pin->resetBitRegister = pin->bitWeight; + break; + case IOS_HIGH: + pin->configuration.GPIO_Mode = GPIO_MODE_OUTPUT; + *pin->setBitRegister = pin->bitWeight; + break; + case IOS_OPEN: + pin->configuration.GPIO_Mode = GPIO_MODE_ANALOG; + break; + default: + break; + } + + setPinConfiguration(pin); +} + +static IO_States getPinState(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return IOS_OPEN; + + if(pin->configuration.GPIO_Mode == GPIO_MODE_INPUT) + pin->state = (GPIO_ISTAT(pin->port) & pin->bitWeight) ? IOS_HIGH : IOS_LOW; + else if(pin->configuration.GPIO_Mode == GPIO_MODE_OUTPUT) + pin->state = (GPIO_OCTL(pin->port) & pin->bitWeight) ? IOS_HIGH : IOS_LOW; + else + pin->state = IOS_OPEN; + + return pin->state; +} + +static void setPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->setBitRegister = pin->bitWeight; +} + +static void setPinLow(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + *pin->resetBitRegister = pin->bitWeight; +} + +static unsigned char isPinHigh(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return -1; + + return (GPIO_ISTAT(pin->port) & pin->bitWeight)? 1 : 0; +} + +static void copyPinConfiguration(IOPinInitTypeDef *from, IOPinTypeDef *to) +{ + if(IS_DUMMY_PIN(to)) + return; + + to->configuration.GPIO_Mode = from->GPIO_Mode; + to->configuration.GPIO_OType = from->GPIO_OType; + to->configuration.GPIO_PuPd = from->GPIO_PuPd; + to->configuration.GPIO_Speed = from->GPIO_Speed; + setPinConfiguration(to); +} + +static void resetPinConfiguration(IOPinTypeDef *pin) +{ + if(IS_DUMMY_PIN(pin)) + return; + + copyPinConfiguration(&(pin->resetConfiguration), pin); + pin->highLevelFunction = IOs.HIGH_LEVEL_FUNCTIONS.DEFAULT; +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c new file mode 100644 index 0000000..e399e2e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/LEDs.c @@ -0,0 +1,72 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include +#include "hal/HAL.h" +#include "hal/LEDs.h" + +static void init(); +static void onStat(); +static void onError(); +static void offStat(); +static void offError(); +static void toggleStat(); +static void toggleError(); + +LEDsTypeDef LEDs = +{ + .init = init, + .stat = + { + .on = onStat, + .off = offStat, + .toggle = toggleStat, + }, + .error = + { + .on = onError, + .off = offError, + .toggle = toggleError, + }, +}; + +static void init() +{ + HAL.IOs->config->reset(&HAL.IOs->pins->LED_STAT); + HAL.IOs->config->reset(&HAL.IOs->pins->LED_ERROR); + LED_OFF(); + LED_ERROR_OFF(); +} + +static void onStat() +{ + LED_ON(); +} + +static void onError() +{ + LED_ERROR_ON(); +} + +static void offStat() +{ + LED_OFF(); +} + +static void offError() +{ + LED_ERROR_OFF(); +} + +static void toggleStat() +{ + LED_TOGGLE(); +} + +static void toggleError() +{ + LED_ERROR_TOGGLE(); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c new file mode 100644 index 0000000..e0bee27 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RS232.c @@ -0,0 +1,106 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t + rxBuffer[BUFFER_SIZE], + txBuffer[BUFFER_SIZE]; + +static uint32_t available = 0; + +RXTXTypeDef RS232 = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART6_IRQHandler(void); + +static void init() +{ + +} + +static void deInit() +{ + +} + +void USART6_IRQHandler(void) +{ + +} + +static void tx(uint8_t ch) +{ + +} + +static uint8_t rx(uint8_t *ch) +{ +return 0; +} + +static void txN(uint8_t *str, unsigned char number) +{ + +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + return 0; + +} + +static void clearBuffers(void) +{ + +} + +static uint32_t bytesAvailable() +{ + return 0; + +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c new file mode 100644 index 0000000..a4ab307 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/RXTX.c @@ -0,0 +1,11 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/RXTX.h" +#include "hal/WLAN.h" +#include "hal/UART.h" + + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c new file mode 100644 index 0000000..810cb13 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SPI.c @@ -0,0 +1,303 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/SPI.h" + +static void init(void); +static void reset_ch1(); +static void reset_ch2(); + +static unsigned char readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); +static unsigned char spi_ch1_readWrite(uint8_t data, uint8_t lastTransfer); +static unsigned char spi_ch2_readWrite(uint8_t data, uint8_t lastTransfer); +static void spi_ch1_readWriteArray(uint8_t *data, size_t length); +static void spi_ch2_readWriteArray(uint8_t *data, size_t length); + +SPIChannelTypeDef *SPIChannel_1_default; +SPIChannelTypeDef *SPIChannel_2_default; + +static uint16_t SPI_PSC_Factor[16] = { 2, 4, 8, 16, 32, 64, 128, 256}; + +static IOPinTypeDef IODummy = { .bitWeight = DUMMY_BITWEIGHT }; + +SPITypeDef SPI= +{ + .ch1 = + { + .periphery = SPI1, + .CSN = &IODummy, + .readWrite = spi_ch1_readWrite, + .readWriteArray = spi_ch1_readWriteArray, + .reset = reset_ch1 + }, + + .ch2 = + { + .periphery = SPI0, + .CSN = &IODummy, + .readWrite = spi_ch2_readWrite, + .readWriteArray = spi_ch2_readWriteArray, + .reset = reset_ch2 + }, + .init = init +}; + + +static void init(void) +{ + rcu_periph_clock_enable(RCU_SPI1); + rcu_periph_clock_enable(RCU_SPI0); + + // Config + spi_parameter_struct params; + + params.device_mode = SPI_MASTER; + params.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + params.frame_size = SPI_FRAMESIZE_8BIT; + params.nss = SPI_NSS_SOFT; + params.endian = SPI_ENDIAN_MSB; + params.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + params.prescale = SPI_PSC_16; // PCLK for SPI1 is 60MHz => SPI1 freq = 60/16 = 3,75MHz + + spi_init(SPI.ch1.periphery, ¶ms); + + params.prescale = SPI_PSC_32; // PCLK for SPI0 is 120MHz => SPI0 freq = 120/32 = 3,75MHz + + spi_init(SPI.ch2.periphery, ¶ms); + + // Enable + spi_enable(SPI.ch1.periphery); + spi_enable(SPI.ch2.periphery); + + // Set pin AFs + + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_15); + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_14); + gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_13); + + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_7); + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_6); + gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_5); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN0); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN1); + HAL.IOs->config->setHigh(&HAL.IOs->pins->SPI2_CSN2); + + reset_ch1(); + reset_ch2(); + + // configure default SPI channel_1 + SPIChannel_1_default = &HAL.SPI->ch1; + SPIChannel_1_default->CSN = &HAL.IOs->pins->SPI1_CSN; + // configure default SPI channel_2 + SPIChannel_2_default = &HAL.SPI->ch2; + SPIChannel_2_default->CSN = &HAL.IOs->pins->SPI2_CSN0; + +} + +static void reset_ch1() +{ + SPI.ch1.CSN = &IODummy; + SPI.ch1.periphery = SPI1; + SPI.ch1.readWrite = spi_ch1_readWrite; +} + +static void reset_ch2() +{ + SPI.ch2.CSN = &IODummy; + SPI.ch2.periphery = SPI0; + SPI.ch2.readWrite = spi_ch2_readWrite; +} + +uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel) +{ + uint32_t PCLK; + if(SPIChannel->periphery == SPI1 || SPIChannel->periphery == SPI2) + { + PCLK = rcu_clock_freq_get(CK_APB1); + } + else + { + PCLK = rcu_clock_freq_get(CK_APB2); + } + uint8_t PSC_Val = (SPI_CTL0(SPIChannel->periphery) & SPI_CTL0_PSC)>>3; + return PCLK/SPI_PSC_Factor[PSC_Val]; +} + +// Set the SPI frequency to the next-best available frequency (rounding down). +// Returns the actual frequency set or 0 if no suitable frequency was found. +uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency) +{ + uint32_t PCLK; + if(SPIChannel->periphery == SPI1 || SPIChannel->periphery == SPI2) + { + PCLK = rcu_clock_freq_get(CK_APB1); + } + else + { + PCLK = rcu_clock_freq_get(CK_APB2); + } + + uint32_t prescaler; + if(desiredFrequency > 0) + { + prescaler = PCLK/desiredFrequency; + } + else{ + + return 0; + } + + if(prescaler == 1) + { + return PCLK; + } + else if(prescaler>1) + { + // Find the highest frequency that is lower or equal to the desired frequency + for(int32_t i=0; iperiphery) = ( SPI_CTL0(SPIChannel->periphery) & (~SPI_CTL0_PSC) ) | PSC_Val; + return PCLK/prescaler; + } + } + } + // The requested frequency was too small -> do not update the frequency + return 0; +} + +uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel) +{ + if (!SPIChannel) + return 0; + + uint32_t tmp = SPI_CTL0(SPIChannel->periphery); + uint8_t cpol = (tmp & SPI_CTL0_CKPL) != 0; + uint8_t cpha = (tmp & SPI_CTL0_CKPH) != 0; + + return (cpol << 1) | cpha; +} + +bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode) +{ + if (!SPIChannel) + return false; + + if (mode > 3) + return false; + + uint8_t cpol = (mode>>1) & 1; + uint8_t cpha = mode & 1; + + uint32_t tmp = SPI_CTL0(SPIChannel->periphery); + tmp &= ~(SPI_CTL0_CKPL | SPI_CTL0_CKPH); + tmp |= cpol ? SPI_CTL0_CKPL : 0; + tmp |= cpha ? SPI_CTL0_CKPH : 0; + SPI_CTL0(SPIChannel->periphery) = tmp; + + return true; +} + +int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address) +{ + // clear write bit + address &= 0x7F; + + SPIChannel->readWrite(address, false); + int32_t value = SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, false); + value <<= 8; + value |= SPIChannel->readWrite(0, true); + + return value; +} + +int32_t spi_ch1_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_1_default, address); +} + +int32_t spi_ch2_readInt(uint8_t address) +{ + return spi_readInt(SPIChannel_2_default, address); +} + +void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value) +{ + SPIChannel->readWrite(address | 0x80, false); + SPIChannel->readWrite(0xFF & (value>>24), false); + SPIChannel->readWrite(0xFF & (value>>16), false); + SPIChannel->readWrite(0xFF & (value>>8), false); + SPIChannel->readWrite(0xFF & (value>>0), true); +} + +void spi_ch1_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_1_default, address, value); +} + +void spi_ch2_writeInt(uint8_t address, int32_t value) +{ + spi_writeInt(SPIChannel_2_default, address, value); +} + +static unsigned char spi_ch1_readWrite(unsigned char data, unsigned char lastTransfer) +{ + return readWrite(&SPI.ch1, data, lastTransfer); +} + +static unsigned char spi_ch2_readWrite(unsigned char data, unsigned char lastTransfer) +{ + return readWrite(&SPI.ch2, data,lastTransfer); +} + +static void spi_ch1_readWriteArray(uint8_t *data, size_t length) +{ + for(uint32_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch1, data[i], (i == (length - 1))? true:false); + } +} + +static void spi_ch2_readWriteArray(uint8_t *data, size_t length) +{ + for(uint32_t i = 0; i < length; i++) + { + data[i] = readWrite(&SPI.ch2, data[i], (i == (length - 1))? true:false); + } +} + +uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer) +{ + return readWrite(SPIChannel_1_default, data, lastTransfer); +} + +uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + return SPIChannel->readWrite(data, lastTransfer); +} + +static unsigned char readWrite(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer) +{ + if(IS_DUMMY_PIN(SPIChannel->CSN)) + return 0; + + HAL.IOs->config->setLow(SPIChannel->CSN); + + while(spi_i2s_flag_get(SPIChannel->periphery, SPI_FLAG_TBE) == RESET); + spi_i2s_data_transmit(SPIChannel->periphery, data); + while(spi_i2s_flag_get(SPIChannel->periphery, SPI_FLAG_RBNE) == RESET); + if(lastTransfer) + HAL.IOs->config->setHigh(SPIChannel->CSN); + + return spi_i2s_data_receive(SPIChannel->periphery); +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c new file mode 100644 index 0000000..071bc68 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/SysTick.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "gd32f4xx.h" +#include "hal/HAL.h" +#include "hal/SysTick.h" + +volatile uint32_t systick = 0; + +#define SYSTICK_PRE_EMPTION_PRIORITY 3 + +void systick_init(void) +{ + SysTick_Config(SystemCoreClock/(1000)); + NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRE_EMPTION_PRIORITY); + + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CYCCNT = 0; + // Enable the DWT CYCCNT for the µs counter + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; +} + + +void SysTick_Handler(void) +{ + systick++; +} + +uint32_t systick_getMicrosecondTick() +{ + // 240 MHz CYCCNT / 240 -> µs counter + return DWT->CYCCNT / 240; +} + +uint32_t systick_getTick(void) +{ + return systick; +} + +void wait(uint32_t delay) // wait for [delay] ms/systicks +{ + uint32_t startTick = systick; + while((systick-startTick) <= delay) {} +} + +uint32_t timeSince(uint32_t tick) // time difference since the [tick] timestamp in ms/systicks +{ + return timeDiff(systick, tick); +} + +uint32_t timeDiff(uint32_t newTick, uint32_t oldTick) // Time difference between newTick and oldTick timestamps +{ + uint32_t tickDiff = newTick - oldTick; + + // Prevent subtraction underflow - saturate to 0 instead + if(tickDiff != 0) + return tickDiff - 1; + else + return 0; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c new file mode 100644 index 0000000..42d9bb6 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/Timer.c @@ -0,0 +1,331 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/Timer.h" + +/* +HAL Timer channels + +TIMER_CHANNEL_1 = TIMER 0 Channel 2, PWM output DIO11 +TIMER_CHANNEL_2 = TIMER 3 Channel 0, RAMDebug +TIMER_CHANNEL_3 = TIMER 4 Channel 0 +TIMER_CHANNEL_4 = TIMER 0 Channel 1, PWM output DIO9 +TIMER_CHANNEL_5 = TIMER 0 Channel 0, PWM output DIO7 +*/ + +#define TIMER_BASE_CLK 240000000 + +static void init(void); +static void deInit(void); +static void setDuty(timer_channel channel, float duty); +static float getDuty(timer_channel channel); +static void setPeriod(timer_channel channel, uint16_t period); +static uint16_t getPeriod(timer_channel channel); +static void setPeriodMin(timer_channel channel, uint16_t period_min); +static void setFrequency(timer_channel channel, float freq); +static void setFrequencyMin(timer_channel channel, float freq_min); + +static uint16_t period_min_buf[] = { 0, 0, 0 }; +static float freq_min_buf[] = { 0.0f, 0.0f, 0.0f }; + +TimerTypeDef Timer = +{ + .initialized = false, + .init = init, + .deInit = deInit, + .setDuty = setDuty, + .getDuty = getDuty, + .setPeriod = setPeriod, + .getPeriod = getPeriod, + .setPeriodMin = setPeriodMin, + .setFrequency = setFrequency, + .setFrequencyMin = setFrequencyMin, + .overflow_callback = NULL +}; + +static void init(void) +{ + rcu_periph_clock_enable(RCU_TIMER0); + rcu_periph_clock_enable(RCU_TIMER3); + rcu_periph_clock_enable(RCU_TIMER4); + timer_deinit(TIMER0); + timer_deinit(TIMER3); + timer_deinit(TIMER4); + + timer_parameter_struct params; + timer_oc_parameter_struct oc_params; + + // TIMER_CHANNEL_1 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER0, ¶ms); + + timer_channel_output_struct_para_init(&oc_params); + oc_params.ocpolarity = TIMER_OC_POLARITY_HIGH; + oc_params.outputstate = TIMER_CCX_ENABLE; + oc_params.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + oc_params.outputnstate = TIMER_CCXN_DISABLE; + oc_params.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + oc_params.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER0, TIMER_CH_2, &oc_params); + // TIMER_CHANNEL_4 + timer_channel_output_config(TIMER0, TIMER_CH_1, &oc_params); + // TIMER_CHANNEL_5 + timer_channel_output_config(TIMER0, TIMER_CH_0, &oc_params); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + // TIMER_CHANNEL_4 + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + // TIMER_CHANNEL_5 + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, TIMER_MAX >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + timer_primary_output_config(TIMER0, ENABLE); + + timer_auto_reload_shadow_enable(TIMER0); + + timer_enable(TIMER0); + + // TIMER_CHANNEL_2 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER3, ¶ms); + + timer_interrupt_enable(TIMER3, TIMER_INT_UP); + nvic_irq_enable(TIMER3_IRQn, 0, 1); + timer_interrupt_flag_clear(TIMER3, TIMER_INT_FLAG_UP); + timer_auto_reload_shadow_enable(TIMER3); + + timer_enable(TIMER3); + + // TIMER_CHANNEL_3 + + timer_struct_para_init(¶ms); + params.prescaler = 0; + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = TIMER_MAX; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 0; + timer_init(TIMER4, ¶ms); + + timer_auto_reload_shadow_enable(TIMER4); + + timer_enable(TIMER4); + + Timer.initialized = true; +} + +static void deInit(void) +{ + timer_deinit(TIMER0); + timer_deinit(TIMER3); + timer_deinit(TIMER4); +} + +static void setDuty(timer_channel channel, float duty) +{ + duty = (duty < 0.0f) ? 0.0f : duty; + duty = (duty > 1.0f) ? 1.0f : duty; + + switch(channel) { + case TIMER_CHANNEL_1: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, duty * TIMER_CAR(TIMER0)); + break; + case TIMER_CHANNEL_2: + timer_channel_output_pulse_value_config(TIMER3, TIMER_CH_0, duty * TIMER_CAR(TIMER3)); + break; + case TIMER_CHANNEL_3: + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, duty * TIMER_CAR(TIMER4)); + break; + case TIMER_CHANNEL_4: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, duty * TIMER_CAR(TIMER0)); + break; + case TIMER_CHANNEL_5: + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, duty * TIMER_CAR(TIMER0)); + break; + } +} + +static float getDuty(timer_channel channel) +{ + switch(channel) { + case TIMER_CHANNEL_1: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_2)) / TIMER_CAR(TIMER0)); + case TIMER_CHANNEL_2: + return (((float) timer_channel_capture_value_register_read(TIMER3, TIMER_CH_0)) / TIMER_CAR(TIMER3)); + case TIMER_CHANNEL_3: + return (((float) timer_channel_capture_value_register_read(TIMER4, TIMER_CH_0)) / TIMER_CAR(TIMER4)); + case TIMER_CHANNEL_4: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_1)) / TIMER_CAR(TIMER0)); + case TIMER_CHANNEL_5: + return (((float) timer_channel_capture_value_register_read(TIMER0, TIMER_CH_0)) / TIMER_CAR(TIMER0)); + } +} + +static void setPeriod(timer_channel channel, uint16_t period) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + timer_autoreload_value_config(TIMER0, period); + break; + case TIMER_CHANNEL_2: + timer_autoreload_value_config(TIMER3, period); + break; + case TIMER_CHANNEL_3: + timer_autoreload_value_config(TIMER4, period); + break; + } +} + +static uint16_t getPeriod(timer_channel channel) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + return TIMER_CAR(TIMER0); + case TIMER_CHANNEL_2: + return TIMER_CAR(TIMER3); + case TIMER_CHANNEL_3: + return TIMER_CAR(TIMER4); + } +} + +static void setPeriodMin(timer_channel channel, uint16_t period_min) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + period_min_buf[0] = period_min; + break; + case TIMER_CHANNEL_2: + period_min_buf[1] = period_min; + break; + case TIMER_CHANNEL_3: + period_min_buf[2] = period_min; + break; + } +} + +static void setFrequencyMin(timer_channel channel, float freq_min) +{ + switch(channel) { + case TIMER_CHANNEL_1: + case TIMER_CHANNEL_4: + case TIMER_CHANNEL_5: + freq_min_buf[0] = freq_min; + break; + case TIMER_CHANNEL_2: + freq_min_buf[1] = freq_min; + break; + case TIMER_CHANNEL_3: + freq_min_buf[2] = freq_min; + break; + } +} + +static void setFrequency(timer_channel channel, float freq) +{ + float freq_min; + uint16_t period_min; + uint32_t timer; + uint32_t timer_ch; + IRQn_Type irq; + + switch(channel) { + case TIMER_CHANNEL_1: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_2; + irq = TIMER0_Channel_IRQn; + break; + case TIMER_CHANNEL_2: + freq_min = freq_min_buf[1]; + period_min = period_min_buf[1]; + timer = TIMER3; + timer_ch = TIMER_CH_0; + irq = TIMER3_IRQn; + break; + case TIMER_CHANNEL_3: + freq_min = freq_min_buf[2]; + period_min = period_min_buf[2]; + timer = TIMER4; + timer_ch = TIMER_CH_0; + irq = TIMER4_IRQn; + break; + case TIMER_CHANNEL_4: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_1; + irq = TIMER0_Channel_IRQn; + break; + case TIMER_CHANNEL_5: + freq_min = freq_min_buf[0]; + period_min = period_min_buf[0]; + timer = TIMER0; + timer_ch = TIMER_CH_0; + irq = TIMER0_Channel_IRQn; + break; + } + + uint16_t prescaler = 0; + uint16_t period = 0xFFFF; + + if(freq < ((float)TIMER_BASE_CLK / (0x0000FFFF * 0x0000FFFF))) + return; + + if(freq > (float)TIMER_BASE_CLK) + return; + + for(; prescaler < 0xFFFF; prescaler++) + { + if(freq > ((float)TIMER_BASE_CLK / ((prescaler + 1) * period))) + { + period = (float)TIMER_BASE_CLK / ((prescaler + 1) * freq); + if(period < period_min) + period = (float)TIMER_BASE_CLK / (prescaler * freq); + break; + } + } + + timer_prescaler_config(timer, prescaler, TIMER_PSC_RELOAD_NOW); + timer_autoreload_value_config(timer, period); +} + +void TIMER3_IRQHandler(void) +{ + if(timer_flag_get(TIMER3, TIMER_FLAG_UP) == SET) + { + if(Timer.overflow_callback) + Timer.overflow_callback(TIMER_CHANNEL_2); + timer_flag_clear(TIMER3, TIMER_FLAG_UP); + } +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c new file mode 100644 index 0000000..cd33ac3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/UART.c @@ -0,0 +1,448 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/UART.h" + +#define BUFFER_SIZE 1024 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static uint8_t UARTSendFlag; + +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; +static volatile uint32_t usart_periph; +uint8_t volatile nvic_irq; + +static volatile uint32_t available = 0; + +UART_Config UART = +{ + .mode = UART_MODE_DUAL_WIRE, + .pinout = UART_PINS_1, + .rxtx = + { + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable + } +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART2_IRQHandler(void); +void __attribute__ ((interrupt)) UART3_IRQHandler(void); + + +static void init() +{ + + switch(UART.pinout) { + case UART_PINS_2: + //Set MUX_1 and MUX_2 to zero to connect DIO10 and DIO11 to UART pins DIO10_UART_TX and DIO11_UART_RX respectively. + *HAL.IOs->pins->SW_UART_PWM.resetBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + + usart_periph = UART3; + usart_deinit(usart_periph); + //DIO10_UART_TX(TxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + + //DIO11_UART_RX(RxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_AF_8, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_AF_8, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + rcu_periph_clock_enable(RCU_UART3); + nvic_irq = UART3_IRQn; + break; + case UART_PINS_1: + usart_periph = USART2; + usart_deinit(usart_periph); + //DIO17(TxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO17.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO17.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO17.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO17.bitWeight); + + //DIO18(RxD) with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO18.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO18.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO18.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO18.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO17.port, GPIO_AF_7, HAL.IOs->pins->DIO17.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO18.port, GPIO_AF_7, HAL.IOs->pins->DIO18.bitWeight); + rcu_periph_clock_enable(RCU_USART2); + usart_hardware_flow_rts_config(usart_periph, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(usart_periph, USART_CTS_DISABLE); + nvic_irq = USART2_IRQn; + break; + } + + + usart_baudrate_set(usart_periph, 115200); + usart_word_length_set(usart_periph, USART_WL_8BIT); + usart_stop_bit_set(usart_periph, USART_STB_1BIT); + usart_parity_config(usart_periph, USART_PM_NONE); + usart_receive_config(usart_periph, USART_RECEIVE_ENABLE); + usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE); + usart_enable(usart_periph); + usart_interrupt_enable(usart_periph, USART_INT_TBE); + usart_interrupt_enable(usart_periph, USART_INT_TC); + usart_interrupt_enable(usart_periph, USART_INT_RBNE); + + nvic_irq_enable(nvic_irq, INTR_PRI, 0); + + usart_flag_clear(usart_periph, USART_FLAG_CTS); + usart_flag_clear(usart_periph, USART_FLAG_LBD); + usart_flag_clear(usart_periph, USART_FLAG_TBE); + usart_flag_clear(usart_periph, USART_FLAG_TC); + usart_flag_clear(usart_periph, USART_FLAG_RBNE); + usart_flag_clear(usart_periph, USART_FLAG_IDLE); + usart_flag_clear(usart_periph, USART_FLAG_ORERR); + usart_flag_clear(usart_periph, USART_FLAG_NERR); + usart_flag_clear(usart_periph, USART_FLAG_FERR); + usart_flag_clear(usart_periph, USART_FLAG_PERR); + +} + +static void deInit() +{ + usart_disable(usart_periph); + nvic_irq_disable(nvic_irq); + + usart_flag_clear(usart_periph, USART_FLAG_CTS); + usart_flag_clear(usart_periph, USART_FLAG_LBD); + usart_flag_clear(usart_periph, USART_FLAG_TBE); + usart_flag_clear(usart_periph, USART_FLAG_TC); + usart_flag_clear(usart_periph, USART_FLAG_RBNE); + usart_flag_clear(usart_periph, USART_FLAG_IDLE); + usart_flag_clear(usart_periph, USART_FLAG_ORERR); + usart_flag_clear(usart_periph, USART_FLAG_NERR); + usart_flag_clear(usart_periph, USART_FLAG_FERR); + usart_flag_clear(usart_periph, USART_FLAG_PERR); + + clearBuffers(); +} + +void USART2_IRQHandler(void) +{ + uint8_t byte; + usart_periph = USART2; + // Receive interrupt + if(USART_STAT0(usart_periph) & USART_STAT0_RBNE) + { + // One-wire UART communication: + // Ignore received byte when a byte has just been sent (echo). + byte = USART_DATA(usart_periph); + + if(!UARTSendFlag) + { // not sending, received real data instead of echo -> advance ring buffer index and available counter + buffers.rx.buffer[buffers.rx.wrote]=byte; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UARTSendFlag = true; + USART_DATA(usart_periph) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { + usart_interrupt_disable(usart_periph, USART_INT_TBE); + + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TC) + { + //Only if there are no more bytes left in the transmit buffer + if(buffers.tx.read == buffers.tx.wrote) + { + byte = USART_DATA(usart_periph); //Ignore spurios echos of the last sent byte that sometimes occur. + UARTSendFlag = false; + } +// USART_ClearITPendingBit(USART2, USART_IT_TC); + usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); + + } +} + +void UART3_IRQHandler(void) +{ + uint8_t byte; + usart_periph = UART3; + // Receive interrupt + if(USART_STAT0(usart_periph) & USART_STAT0_RBNE) + { + // One-wire UART communication: + // Ignore received byte when a byte has just been sent (echo). + byte = USART_DATA(usart_periph); + + if(!UARTSendFlag) + { // not sending, received real data instead of echo -> advance ring buffer index and available counter + buffers.rx.buffer[buffers.rx.wrote]=byte; + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + } + } + + // Transmit buffer empty interrupt => send next byte if there is something + // to be sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + UARTSendFlag = true; + USART_DATA(usart_periph) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else + { + usart_interrupt_disable(usart_periph, USART_INT_TBE); + + } + } + + // Transmission complete interrupt => do not ignore echo any more + // after last bit has been sent. + if(USART_STAT0(usart_periph) & USART_STAT0_TC) + { + //Only if there are no more bytes left in the transmit buffer + if(buffers.tx.read == buffers.tx.wrote) + { + byte = USART_DATA(usart_periph); //Ignore spurios echos of the last sent byte that sometimes occur. + UARTSendFlag = false; + } +// USART_ClearITPendingBit(USART2, USART_IT_TC); + usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); + + } +} + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(2); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = systick_getTick(); + while(uart->rxtx.bytesAvailable() < readLength) + { + if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + { + // Abort on timeout + return -1; + } + } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value) +{ + uint8_t readData[8], dataRequest[4]; + uint32_t timeout; + + dataRequest[0] = 0x05; // Sync byte + dataRequest[1] = slave; // Slave address + dataRequest[2] = address; // Register address + dataRequest[3] = tmc_CRC8(dataRequest, 3, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + channel->rxtx.txN(dataRequest, ARRAY_SIZE(dataRequest)); + + // Wait for reply with timeout limit + timeout = systick_getTick(); + while(channel->rxtx.bytesAvailable() < ARRAY_SIZE(readData)) + if(timeSince(timeout) > UART_TIMEOUT_VALUE) // Timeout + return; + + channel->rxtx.rxN(readData, ARRAY_SIZE(readData)); + // Check if the received data is correct (CRC, Sync, Slave address, Register address) + // todo CHECK 2: Only keep CRC check? Should be sufficient for wrong transmissions (LH) #1 + if(readData[7] != tmc_CRC8(readData, 7, 1) || readData[0] != 0x05 || readData[1] != 0xFF || readData[2] != address) + return; + + *value = readData[3] << 24 | readData[4] << 16 | readData[5] << 8 | readData[6]; + return; +} + +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value) +{ + uint8_t writeData[8]; + + writeData[0] = 0x05; // Sync byte + writeData[1] = slave; // Slave address + writeData[2] = address | TMC_WRITE_BIT; // Register address with write bit set + writeData[3] = value >> 24; // Register Data + writeData[4] = value >> 16; // Register Data + writeData[5] = value >> 8; // Register Data + writeData[6] = value & 0xFF; // Register Data + writeData[7] = tmc_CRC8(writeData, 7, 1); // Cyclic redundancy check + + channel->rxtx.clearBuffers(); + for(uint32_t i = 0; i < ARRAY_SIZE(writeData); i++) + channel->rxtx.tx(writeData[i]); + + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(2); +} + +void UART_setEnabled(UART_Config *channel, uint8_t enabled) +{ + UNUSED(channel); + switch(channel->pinout) + { + case UART_PINS_2: + if (enabled) + { + + //TxD as open drain output + gpio_mode_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + + //RxD with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO10_UART_TX.port, GPIO_AF_8, HAL.IOs->pins->DIO10_UART_TX.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO11_UART_RX.port, GPIO_AF_8, HAL.IOs->pins->DIO11_UART_RX.bitWeight); + } + else{ + HAL.IOs->config->reset(&HAL.IOs->pins->DIO10_UART_TX); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO11_UART_RX); + } + break; + case UART_PINS_1: + if (enabled) + { + //TxD as open drain output + gpio_mode_set(HAL.IOs->pins->DIO17.port, GPIO_MODE_AF, GPIO_PUPD_NONE, HAL.IOs->pins->DIO17.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO17.port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO17.bitWeight); + + //RxD with pull-up resistor + gpio_mode_set(HAL.IOs->pins->DIO18.port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, HAL.IOs->pins->DIO18.bitWeight); + gpio_output_options_set(HAL.IOs->pins->DIO18.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, HAL.IOs->pins->DIO18.bitWeight); + + gpio_af_set(HAL.IOs->pins->DIO17.port, GPIO_AF_7, HAL.IOs->pins->DIO17.bitWeight); + gpio_af_set(HAL.IOs->pins->DIO18.port, GPIO_AF_7, HAL.IOs->pins->DIO18.bitWeight); + } + else{ + HAL.IOs->config->reset(&HAL.IOs->pins->DIO17); + HAL.IOs->config->reset(&HAL.IOs->pins->DIO18); + } + break; + } + +} + +static void tx(uint8_t ch) +{ + buffers.tx.buffer[buffers.tx.wrote] = ch; + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + usart_interrupt_enable(usart_periph, USART_INT_TBE); + +} + +static uint8_t rx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; + available--; + + return 1; +} + +static void txN(uint8_t *str, unsigned char number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + if(bytesAvailable() < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + __disable_irq(); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + __enable_irq(); +} + +static uint32_t bytesAvailable() +{ + return available; +} + diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c new file mode 100644 index 0000000..5b546dc --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/USB.c @@ -0,0 +1,245 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "gd32f4xx.h" +#include "usb/drv_usbd_int.h" +#include "usb/drv_usb_hw.h" +#include "usb/cdc_acm_core.h" +#include "hal/HAL.h" + +#define BUFFER_SIZE 2048 // KEEP THIS SIZE AS IT MATCHES BUFFERSIZE OF usbd_cdc_core.c + +// Specific functions +static void USBSendData(uint8_t *Buffer, uint32_t Size); +static uint32_t USBGetData(uint8_t *Buffer, size_t amount); +static uint8_t GetUSBCmd(uint8_t *Cmd); +static void InitUSB(void); +static void DetachUSB(void); + +// Interface functions +static void init(void); +static void deInit(void); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *str, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(void); + +static usb_core_driver cdc_acm; +static uint8_t USBDataTxBuffer[256]; +static volatile uint32_t available = 0; + +// static RXTXBufferingTypeDef buffers = +// { +// .rx = +// { +// .read = 0, +// .wrote = 0, +// .buffer = rxBuffer +// }, + +// .tx = +// { +// .read = 0, +// .wrote = 0, +// .buffer = APP_Rx_Buffer +// } +// }; + +RXTXTypeDef USB = +{ + .init = init, + .deInit = deInit, + .rx = NULL, + .tx = NULL, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +void usb_timer_irq (void); + +void TIMER6_IRQHandler(void) +{ + usb_timer_irq(); +} + +void USBFS_IRQHandler(void) +{ + usbd_isr(&cdc_acm); +} + +static void InitUSB(void) +{ + usb_gpio_config(); + usb_rcu_config(); + usb_timer_init(); + usbd_init(&cdc_acm, USB_CORE_ENUM_FS, &cdc_desc, &cdc_class); + usb_intr_config(); +} + +static void DetachUSB(void) +{ + usb_dev_stop(&cdc_acm); +} + +/******************************************************************* + Funktion: USBSendData() + Parameter: Buffer: Array mit den zu sendenden Daten + Size: Anzahl der zu sendenden Bytes + + R�ckgabewert: --- + + Zweck: Senden von Daten �ber USB. +********************************************************************/ +static void USBSendData(uint8_t *Buffer, uint32_t Size) +{ + uint32_t i; + + for(i=0; idev.class_data[CDC_COM_INTERFACE]; + + i=0; + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length >= amount) + { + for(i=0; i < amount; i++) Buffer[i]=cdc->data[i]; + flag = TRUE; + } + cdc->packet_receive = 0; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + return flag; +} + + +/******************************************************************* + Funktion: GetUSBCmd() + Parameter: Cmd: Array (9 Bytes) f�r den TMCL-Befehl. + + R�ckgabewert: TRUE bei Erfolg + FALSE wenn kein Befehl vorhanden + + Zweck: Abholen eines TMCL-Befehls �ber USB. +********************************************************************/ +static uint8_t GetUSBCmd(uint8_t *Cmd) +{ + uint8_t flag; + uint32_t i; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + + flag=FALSE; + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length>=9) + { + for(i=0; i<9; i++) Cmd[i]=cdc->data[i]; + flag=TRUE; + } + cdc->packet_receive=0; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + return flag; +} + +static void init(void) +{ + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DM); + HAL.IOs->config->reset(&HAL.IOs->pins->USB_V_DP); + + InitUSB(); +} + +static void tx(uint8_t ch) +{ + //buffers.tx.buffer[buffers.tx.wrote] = ch; + //buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; + usbd_ep_send((usb_dev *) &cdc_acm, CDC_DATA_IN_EP, &ch, 1); +} + +static uint8_t rx(uint8_t *ch) +{ + uint8_t data = 0; + uint8_t i = 0; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + + if(USBD_CONFIGURED == cdc_acm.dev.cur_status) + { + if(cdc->packet_receive) + { + if(cdc->receive_length > 0) + { + data = cdc->data[0]; + i = 1; + } + cdc->packet_receive--; + usbd_ep_recev((usb_dev *) &cdc_acm, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + } + } + + return i; +} + +static void txN(uint8_t *str, unsigned char number) +{ + USBSendData(str, number); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + return USBGetData(str, number); +} + +static void clearBuffers(void) +{ + // __disable_irq(); + // available = 0; + // buffers.rx.read = 0; + // buffers.rx.wrote = 0; + + // buffers.tx.read = 0; + // buffers.tx.wrote = 0; + // __enable_irq(); +} + +static uint32_t bytesAvailable(void) +{ + return available; + usb_cdc_handler *cdc = (usb_cdc_handler *) (&cdc_acm)->dev.class_data[CDC_COM_INTERFACE]; + return cdc->receive_length; +} + +static void deInit(void) +{ + +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c new file mode 100644 index 0000000..40d174e --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/WLAN.c @@ -0,0 +1,360 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/HAL.h" +#include "hal/RS232.h" +#include "hal/WLAN.h" +#include "hal/RXTX.h" +#include + + +#define BUFFER_SIZE 1024 +#define WLAN_CMD_BUFFER_SIZE 128 // ascii command string buffer + +#define INTR_PRI 6 + +#define CMDBUFFER_END_CHAR '\0' + + +static void init(); +static void deInit(); +static void tx(uint8_t ch); +static uint8_t rx(uint8_t *ch); +static void txN(uint8_t *str, unsigned char number); +static uint8_t rxN(uint8_t *ch, unsigned char number); +static void clearBuffers(void); +static uint32_t bytesAvailable(); + +static volatile uint8_t rxBuffer[BUFFER_SIZE]; +static volatile uint8_t txBuffer[BUFFER_SIZE]; + +static int8_t cmdBuffer[WLAN_CMD_BUFFER_SIZE]; +static uint32_t cmdBufferSize = 0; +static uint32_t cmdEnabledTime; // systick timestamp when command mode sequence has been sent + + +static WLANStateTypedef wlanState = WLAN_DATA_MODE; + + +static volatile uint32_t available = 0; + +RXTXTypeDef WLAN = +{ + .init = init, + .deInit = deInit, + .rx = rx, + .tx = tx, + .rxN = rxN, + .txN = txN, + .clearBuffers = clearBuffers, + .baudRate = 115200, + .bytesAvailable = bytesAvailable +}; + +static RXTXBufferingTypeDef buffers = +{ + .rx = + { + .read = 0, + .wrote = 0, + .buffer = rxBuffer + }, + + .tx = + { + .read = 0, + .wrote = 0, + .buffer = txBuffer + } +}; + +void __attribute__ ((interrupt)) USART1_IRQHandler(void); + + +static void init() +{ + usart_deinit(RCU_USART1); + + HAL.IOs->pins->WIFI_RX.configuration.GPIO_Mode = GPIO_AF_7; + HAL.IOs->pins->WIFI_TX.configuration.GPIO_Mode = GPIO_AF_7; + + HAL.IOs->config->set(&HAL.IOs->pins->WIFI_RX); + HAL.IOs->config->set(&HAL.IOs->pins->WIFI_TX); + gpio_af_set(HAL.IOs->pins->WIFI_RX.port, GPIO_AF_7, HAL.IOs->pins->WIFI_RX.bitWeight); + gpio_af_set(HAL.IOs->pins->WIFI_TX.port, GPIO_AF_7, HAL.IOs->pins->WIFI_TX.bitWeight); + + rcu_periph_clock_enable(RCU_USART1); + + usart_hardware_flow_rts_config(RCU_USART1, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(RCU_USART1, USART_CTS_DISABLE); + + usart_baudrate_set(RCU_USART1, 115200); + usart_word_length_set(RCU_USART1, USART_WL_8BIT); + usart_stop_bit_set(RCU_USART1, USART_STB_1BIT); + usart_parity_config(RCU_USART1, USART_PM_NONE); + usart_receive_config(RCU_USART1, USART_RECEIVE_ENABLE); + usart_transmit_config(RCU_USART1, USART_TRANSMIT_ENABLE); + usart_enable(RCU_USART1); + usart_interrupt_enable(RCU_USART1, USART_INT_TBE); + usart_interrupt_enable(RCU_USART1, USART_INT_TC); + usart_interrupt_enable(RCU_USART1, USART_INT_RBNE); + + nvic_irq_enable(USART1_IRQn, INTR_PRI, 0); + + usart_flag_clear(RCU_USART1, USART_FLAG_CTS); + usart_flag_clear(RCU_USART1, USART_FLAG_LBD); + usart_flag_clear(RCU_USART1, USART_FLAG_TBE); + usart_flag_clear(RCU_USART1, USART_FLAG_TC); + usart_flag_clear(RCU_USART1, USART_FLAG_RBNE); + usart_flag_clear(RCU_USART1, USART_FLAG_IDLE); + usart_flag_clear(RCU_USART1, USART_FLAG_ORERR); + usart_flag_clear(RCU_USART1, USART_FLAG_NERR); + usart_flag_clear(RCU_USART1, USART_FLAG_FERR); + usart_flag_clear(RCU_USART1, USART_FLAG_PERR); + +} + +static void deInit() +{ + usart_disable(RCU_USART1); + nvic_irq_disable(USART1_IRQn); + + usart_flag_clear(RCU_USART1, USART_FLAG_CTS); + usart_flag_clear(RCU_USART1, USART_FLAG_LBD); + usart_flag_clear(RCU_USART1, USART_FLAG_TBE); + usart_flag_clear(RCU_USART1, USART_FLAG_TC); + usart_flag_clear(RCU_USART1, USART_FLAG_RBNE); + usart_flag_clear(RCU_USART1, USART_FLAG_IDLE); + usart_flag_clear(RCU_USART1, USART_FLAG_ORERR); + usart_flag_clear(RCU_USART1, USART_FLAG_NERR); + usart_flag_clear(RCU_USART1, USART_FLAG_FERR); + usart_flag_clear(RCU_USART1, USART_FLAG_PERR); + + clearBuffers(); +} + + +void USART1_IRQHandler(void) +{ + // Receive interrupt + if(USART_STAT0(RCU_USART1) & USART_STAT0_RBNE) + { + buffers.rx.buffer[buffers.rx.wrote] = USART_DATA(RCU_USART1); + buffers.rx.wrote = (buffers.rx.wrote + 1) % BUFFER_SIZE; + available++; + + } + + if(USART_STAT0(RCU_USART1) & USART_STAT0_TBE) + { + if(buffers.tx.read != buffers.tx.wrote) + { + USART_DATA(RCU_USART1) = buffers.tx.buffer[buffers.tx.read]; + buffers.tx.read = (buffers.tx.read + 1) % BUFFER_SIZE; + } + else // empty buffer -> turn off send interrupt + { + usart_interrupt_disable(RCU_USART1, USART_INT_TBE); + } + } + + if(USART_STAT0(RCU_USART1) & USART_STAT0_TC) + { + usart_interrupt_flag_clear(RCU_USART1, USART_INT_FLAG_TC); + + } +} + + +// Send without checking for CMD/Data mode +static void rawTx(uint8_t ch) +{ + if(wlanState == WLAN_INIT_CMD_MODE) + return; + + buffers.tx.buffer[buffers.tx.wrote] = ch; + + buffers.tx.wrote = (buffers.tx.wrote + 1) % BUFFER_SIZE; // Move ring buffer index + + // enable send interrupt + usart_interrupt_enable(RCU_USART1, USART_INT_TBE); +} + +static void tx(uint8_t ch) +{ + if(checkReadyToSend()) + rawTx(ch); +} + +static uint8_t rawRx(uint8_t *ch) +{ + if(buffers.rx.read == buffers.rx.wrote) + return 0; + + *ch = buffers.rx.buffer[buffers.rx.read]; + buffers.rx.read = (buffers.rx.read + 1) % BUFFER_SIZE; // Move ring buffer index + available--; + + return 1; +} + +static uint8_t rx(uint8_t *ch) +{ + if(wlanState != WLAN_DATA_MODE) + return 0; + + return rawRx(ch);} + +static void txN(uint8_t *str, unsigned char number) +{ + for(int32_t i = 0; i < number; i++) + tx(str[i]); +} + +static uint8_t rxN(uint8_t *str, unsigned char number) +{ + if(bytesAvailable() < number) + return 0; + + for(int32_t i = 0; i < number; i++) + rx(&str[i]); + + return 1; +} + +static void clearBuffers(void) +{ + nvic_irq_disable(USART1_IRQn); + available = 0; + buffers.rx.read = 0; + buffers.rx.wrote = 0; + + buffers.tx.read = 0; + buffers.tx.wrote = 0; + nvic_irq_enable(USART1_IRQn, INTR_PRI, 0); +} + +static uint32_t bytesAvailable() +{ + return available; +} + +uint32_t checkReadyToSend() { + + if(checkCmdModeEnabled()) + { + return false; + } + else + { + return (wlanState == WLAN_INIT_CMD_MODE)? false:true; + } +} +void enableWLANCommandMode() +{ /* To enable command mode, the escape character (default: $) needs to be sent 3 times. + * Additionally, both before and after that sequence there should be 250ms without data sent to the module + * Since the configuration mode is supposed to be used as a simple testing tool, + * there is no check for the time span before the write. If the switching fails due to that, + * an error will be returned upon attempted command execution, just try to reenter command mode then. + */ + wlanState = WLAN_CMD_MODE; // Block external write sources + + clearBuffers(); + rawTx('$'); // txN doesn't work, as WLAN_CMD_MODE prevents tx (which txN calls) from writing to the buffer) + rawTx('$'); + rawTx('$'); + wlanState = WLAN_INIT_CMD_MODE; // Block all writes + cmdEnabledTime = systick_getTick(); +} + +uint32_t checkCmdModeEnabled() +{ + if(wlanState == WLAN_CMD_MODE) + return true; + else if(wlanState == WLAN_DATA_MODE) + return false; + + uint8_t reply[4] = { 0 }; // expected reply: {'C','M','D'}, we're appending \0 so we have a NULL-terminated string that we can use in strcmp() + if(rxN(reply, 3)) + { + if(strcmp((const char *)reply, "CMD") == 0) + { + wlanState = WLAN_CMD_MODE; + return true; + } + else + { // Unexpected answer - going back to data mode + wlanState = WLAN_DATA_MODE; + return false; + } + } + else + { + if(timeSince(cmdEnabledTime) > 350) // 250 ms from chip spec + 100ms, just to be safe + { // Too much time passed since attempted cmd mode switching happened - assuming it failed + wlanState = WLAN_DATA_MODE; + return false; + } + else + { // Not enough time passed, we're not in command mode yet but we're still giving the chip time + return false; + } + } +} + +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value) +{ + switch(cmd) + { + case BUFFER_CLEAR: + cmdBufferSize = 0; + break; + case BUFFER_WRITE: + while((value & 0xFF) != CMDBUFFER_END_CHAR) + { + if(cmdBufferSize == WLAN_CMD_BUFFER_SIZE) + { + if((value & 0xFF) != 0) // Any value still remaining -> too much data for buffer -> return an error + return 1; + break; + } + cmdBuffer[cmdBufferSize] = value & 0xFF; + value >>= 8; + cmdBufferSize++; + } + break; + case BUFFER_EXECUTE: + // Abort if not in command mode. IDE/User should switch to command mode before executing + if(!checkCmdModeEnabled()) + return 1; + + for(uint32_t i = 0; i < cmdBufferSize; i++) + rawTx(cmdBuffer[i]); // Can't use txN since its blocked from sending while in command mode + rawTx('\r'); // End of command character + + cmdBufferSize = 0; + break; + } + + return 0; +} + +uint32_t getCMDReply() +{ + uint8_t cmdReply; + uint32_t result = 0; + + for(uint8_t i = 0; i < 4; i++) + { + if(rawRx(&cmdReply) == 0) + cmdReply = 0; + // First character is in the smallest byte of result + result |= cmdReply << 24; + result >>= 8; + } + + return result; +} diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h new file mode 100644 index 0000000..fd4783a --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usb_conf.h @@ -0,0 +1,191 @@ +/*! + \file usb_conf.h + \brief USB core driver basic configuration + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include +#include "gd32f4xx.h" + +#define USE_USB_FS + +/* USB Core and PHY interface configuration */ + +/****************** USB FS PHY CONFIGURATION ******************************* + * The USB FS Core supports one on-chip Full Speed PHY. + * The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor + * when FS core is used. +*******************************************************************************/ + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif /* USE_USB_FS */ + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif /* USE_USB_HS */ + +/******************************************************************************* + * FIFO Size Configuration in Device mode + * + * (i) Receive data FIFO size = RAM for setup packets + + * OUT endpoint control information + + * data OUT packets + miscellaneous + * Space = ONE 32-bits words + * --> RAM for setup packets = 10 spaces + * (n is the nbr of CTRL EPs the device core supports) + * --> OUT EP CTRL info = 1 space + * (one space for status information written to the FIFO along with each + * received packet) + * --> Data OUT packets = (Largest Packet Size / 4) + 1 spaces + * (MINIMUM to receive packets) + * --> OR data OUT packets = at least 2* (Largest Packet Size / 4) + 1 spaces + * (if high-bandwidth EP is enabled or multiple isochronous EPs) + * --> Miscellaneous = 1 space per OUT EP + * (one space for transfer complete status information also pushed to the + * FIFO with each endpoint's last packet) + * + * (ii) MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for + * that particular IN EP. More space allocated in the IN EP Tx FIFO results + * in a better performance on the USB and can hide latencies on the AHB. + * + * (iii) TXn min size = 16 words. (n:Transmit FIFO index) + * + * (iv) When a TxFIFO is not used, the Configuration should be as follows: + * case 1: n > m and Txn is not used (n,m:Transmit FIFO indexes) + * --> Txm can use the space allocated for Txn. + * case 2: n < m and Txn is not used (n,m:Transmit FIFO indexes) + * --> Txn should be configured with the minimum space of 16 words + * + * (v) The FIFO is used optimally when used TxFIFOs are allocated in the top + * of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + * + * (vi) In HS case12 FIFO locations should be reserved for internal DMA registers + * so total FIFO size should be 1012 Only instead of 1024 +*******************************************************************************/ + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 64 + #define TX2_FIFO_FS_SIZE 64 + #define TX3_FIFO_FS_SIZE 0 + + #define USBFS_SOF_OUTPUT 0 + #define USBFS_LOW_POWER 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 128 + #define TX2_FIFO_HS_SIZE 128 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_EMBEDDED_PHY_ENABLED + #endif + +// #define USB_HS_INTERNAL_DMA_ENABLED +// #define USB_HS_DEDICATED_EP1_ENABLED + + #define USBHS_SOF_OUTPUT 0 + #define USBHS_LOW_POWER 0 +#endif /* USB_HS_CORE */ + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined!" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined!" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined!" + #endif +#endif + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN + #else + #define __ALIGN_END + + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__)/* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __packed + #define __packed __attribute__ ((__packed__)) + #endif +#elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned +#endif /* __CC_ARM */ + +#endif /* __USB_CONF_H */ diff --git a/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h new file mode 100644 index 0000000..d70a738 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Landungsbruecke_V3/tmc/usbd_conf.h @@ -0,0 +1,74 @@ +/*! + \file usbd_conf.h + \brief the header file of USB device configuration + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CONF_H +#define __USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 + +#define CDC_COM_INTERFACE 0 + +#define USB_STR_DESC_MAX_SIZE 255 + +#define CDC_DATA_IN_EP EP1_IN /* EP1 for data IN */ +#define CDC_DATA_OUT_EP EP3_OUT /* EP3 for data OUT */ +#define CDC_CMD_EP EP2_IN /* EP2 for CDC commands */ + +#define USB_STRING_COUNT 4 + +#define USB_CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ + +#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer: + APP_RX_DATA_SIZE*8 / MAX_BAUDARATE * 1000 should be > CDC_IN_FRAME_INTERVAL*8 */ + +/* CDC endpoints parameters: you can fine tune these values depending on the needed baud rate and performance */ +#ifdef USE_USB_HS + #ifdef USE_ULPI_PHY + #define USB_CDC_DATA_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 40 /* Number of micro-frames between IN transfers */ + #else + #define USB_CDC_DATA_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ + #endif +#else + #define USB_CDC_DATA_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ + #define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ +#endif /* USE_USB_HS */ + +#endif /* __USBD_CONF_H */ diff --git a/TMC2209/lib/tmc/hal/RS232.h b/TMC2209/lib/tmc/hal/RS232.h new file mode 100644 index 0000000..26956e3 --- /dev/null +++ b/TMC2209/lib/tmc/hal/RS232.h @@ -0,0 +1,17 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __RS232_H_ + #define __RS232_H_ + + #include "RXTX.h" + + extern RXTXTypeDef RS232; + +#endif /* __RS232_H_ */ diff --git a/TMC2209/lib/tmc/hal/RXTX.h b/TMC2209/lib/tmc/hal/RXTX.h new file mode 100644 index 0000000..d697ddd --- /dev/null +++ b/TMC2209/lib/tmc/hal/RXTX.h @@ -0,0 +1,49 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef RXTX_H_ +#define RXTX_H_ + +#include "tmc/helpers/API_Header.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +typedef enum { + UART0_INTERRUPT_UART, + UART0_INTERRUPT_WLAN +} UART0_Interrupt; +extern UART0_Interrupt uart0_interrupt; +#endif + +typedef struct +{ + void (*init)(); + void (*deInit)(void); + void (*tx)(uint8_t ch); + uint8_t (*rx)(uint8_t *ch); + void (*txN)(uint8_t *ch, unsigned char number); + uint8_t (*rxN)(uint8_t *ch, unsigned char number); + void (*clearBuffers)(void); + uint32_t (*bytesAvailable)(void); + uint32_t baudRate; +} RXTXTypeDef; + +typedef struct +{ + uint32_t read; + uint32_t wrote; + volatile uint8_t *buffer; +} BufferingTypeDef; + +typedef struct +{ + BufferingTypeDef tx; + BufferingTypeDef rx; +} RXTXBufferingTypeDef; + +#endif /* RXTX_H_ */ diff --git a/TMC2209/lib/tmc/hal/SPI.h b/TMC2209/lib/tmc/hal/SPI.h new file mode 100644 index 0000000..1bc50d1 --- /dev/null +++ b/TMC2209/lib/tmc/hal/SPI.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SPI_H +#define SPI_H + + #include "derivative.h" + #include "IOs.h" + + typedef struct + { + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + SPI_MemMapPtr periphery; // pointer to freescale SPI memory base pointer + #elif defined(LandungsbrueckeV3) + uint32_t periphery; // GD32 SPI parameters + #endif + + IOPinTypeDef *CSN; + unsigned char (*readWrite) (unsigned char data, unsigned char lastTransfer); + void (*readWriteArray) (uint8_t *data, size_t length); + void (*reset) (void); + } SPIChannelTypeDef; + + typedef struct + { + SPIChannelTypeDef ch1; + SPIChannelTypeDef ch2; + void (*init) (void); + } SPITypeDef; + + extern SPITypeDef SPI; + + uint32_t spi_getFrequency(SPIChannelTypeDef *SPIChannel); + uint32_t spi_setFrequency(SPIChannelTypeDef *SPIChannel, uint32_t desiredFrequency); + + uint8_t spi_getMode(SPIChannelTypeDef *SPIChannel); + bool spi_setMode(SPIChannelTypeDef *SPIChannel, uint8_t mode); + + // read/write 32 bit value at address + int32_t spi_readInt(SPIChannelTypeDef *SPIChannel, uint8_t address); + void spi_writeInt(SPIChannelTypeDef *SPIChannel, uint8_t address, int32_t value); + + // for default channels + uint8_t spi_ch1_readWriteByte(uint8_t data, uint8_t lastTransfer); + // for TM02 + uint8_t spi_ch2_readWriteByte(SPIChannelTypeDef *SPIChannel, uint8_t data, uint8_t lastTransfer); + + + int32_t spi_ch1_readInt(uint8_t address); + void spi_ch1_writeInt(uint8_t address, int32_t value); + + int32_t spi_ch2_readInt(uint8_t address); + void spi_ch2_writeInt(uint8_t address, int32_t value); + +#endif /* SPI_H */ diff --git a/TMC2209/lib/tmc/hal/SysTick.h b/TMC2209/lib/tmc/hal/SysTick.h new file mode 100644 index 0000000..a496f94 --- /dev/null +++ b/TMC2209/lib/tmc/hal/SysTick.h @@ -0,0 +1,25 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef SysTick_H +#define SysTick_H + + #include "tmc/helpers/API_Header.h" + + void systick_init(); + uint32_t systick_getTick(); + void wait(uint32_t delay); + uint32_t timeSince(uint32_t tick); + uint32_t timeDiff(uint32_t newTick, uint32_t oldTick); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + uint32_t systick_getMicrosecondTick(); +#endif + +#endif /* SysTick_H */ diff --git a/TMC2209/lib/tmc/hal/Timer.h b/TMC2209/lib/tmc/hal/Timer.h new file mode 100644 index 0000000..c8385f8 --- /dev/null +++ b/TMC2209/lib/tmc/hal/Timer.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TIMER_H_ +#define TIMER_H_ + +#include "derivative.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +#define TIMER_MAX 8000 +#elif defined(LandungsbrueckeV3) +#define TIMER_MAX 65535 +#endif + +typedef enum { + TIMER_CHANNEL_1, + TIMER_CHANNEL_2, + TIMER_CHANNEL_3, + TIMER_CHANNEL_4, + TIMER_CHANNEL_5 +} timer_channel; + +typedef struct +{ + bool initialized; + void (*init) (void); + void (*deInit) (void); + void (*setDuty) (timer_channel channel, float duty); + float (*getDuty) (timer_channel channel); + void (*setPeriod) (timer_channel channel, uint16_t period); + uint16_t (*getPeriod) (timer_channel channel); + void (*setPeriodMin) (timer_channel channel, uint16_t period_min); + void (*setFrequency) (timer_channel channel, float freq); + void (*setFrequencyMin) (timer_channel channel, float freq_min); + void (*overflow_callback) (timer_channel channel); +} TimerTypeDef; + +extern TimerTypeDef Timer; + +#endif /* TIMER_H_ */ diff --git a/TMC2209/lib/tmc/hal/UART.h b/TMC2209/lib/tmc/hal/UART.h new file mode 100644 index 0000000..3a168bb --- /dev/null +++ b/TMC2209/lib/tmc/hal/UART.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __UART_H_ +#define __UART_H_ + +#include "RXTX.h" + +// Switchable UART pin configuration due to pinout changes in TMC2208 v1.2 -> TMC2208 v1.3 aswell as TMC2209 +typedef enum { + UART_PINS_1, // Default UART pinout (<= TMC2208 v1.2, UART_TXD = DIO17, UART_RXD = DIO18) + UART_PINS_2 // Alternate UART pinout (>= TMC2208 v1.3, UART_TXD = DIO10, UART_RXD = DIO11) +} UART_Pins; + +typedef enum { + UART_MODE_DUAL_WIRE, + UART_MODE_SINGLE_WIRE, + UART_MODE_DUAL_WIRE_PushPull, // Use PushPull for TX instead of OpenDrain +} UART_Mode; + +typedef struct { + UART_Pins pinout; + UART_Mode mode; + RXTXTypeDef rxtx; +} UART_Config; + +extern UART_Config UART; + +void UART0_RX_TX_IRQHandler_UART(void); +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength); +void UART_readInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t *value); +void UART_writeInt(UART_Config *channel, uint8_t slave, uint8_t address, int32_t value); +void UART_setEnabled(UART_Config *channel, uint8_t enabled); + +#endif /* __UART_H_ */ diff --git a/TMC2209/lib/tmc/hal/USB.h b/TMC2209/lib/tmc/hal/USB.h new file mode 100644 index 0000000..1378ff9 --- /dev/null +++ b/TMC2209/lib/tmc/hal/USB.h @@ -0,0 +1,16 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __USB_H + #define __USB_H + + #include "RXTX.h" + extern RXTXTypeDef USB; + +#endif /* __USB_H */ diff --git a/TMC2209/lib/tmc/hal/WLAN.h b/TMC2209/lib/tmc/hal/WLAN.h new file mode 100644 index 0000000..5133e98 --- /dev/null +++ b/TMC2209/lib/tmc/hal/WLAN.h @@ -0,0 +1,38 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef __WLAN_H_ +#define __WLAN_H_ + +#include "RXTX.h" + +extern RXTXTypeDef WLAN; + +typedef enum +{ + BUFFER_CLEAR, + BUFFER_WRITE, + BUFFER_EXECUTE +} BufferCommandTypedef; + +typedef enum +{ + WLAN_INIT_CMD_MODE, // wait time inbetween sending $$$ and entering command mode - writing is disabled completely. rx doesn't read out data - we enter this mode only after a clearBuffer() anyways + WLAN_CMD_MODE, // Command mode - writing is disabled for the HAL tx function, rawTx still writes. rx doesn't read out data, rawRx does + WLAN_DATA_MODE // Data mode - HAL tx/rx functions works normally +} WLANStateTypedef; + +void UART0_RX_TX_IRQHandler_WLAN(void); +uint32_t checkReadyToSend(); +void enableWLANCommandMode(); +uint32_t checkCmdModeEnabled(); +uint32_t handleWLANCommand(BufferCommandTypedef cmd, uint32_t value); +uint32_t getCMDReply(); + +#endif /* __WLAN_H_ */ diff --git a/TMC2209/lib/tmc/hal/derivative.h b/TMC2209/lib/tmc/hal/derivative.h new file mode 100644 index 0000000..d1a7094 --- /dev/null +++ b/TMC2209/lib/tmc/hal/derivative.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef _DERIVATIVE_H_ + #define _DERIVATIVE_H_ + +/* This is purely for the Eclipse parsing. + * while working on Board-specific code you can + * select one of the two boards here. + * The Build process already selects one via makefile & makeFor.h files, + * this choice will therefore not influence the build process. + */ +#if !defined(Landungsbruecke) && !defined(LandungsbrueckeV3) && !defined(LandungsbrueckeSmall) +#warning "No Board selected by makefile, defining one for debug purposes" +//#define Landungsbruecke +// #define LandungsbrueckeV3 +//#define LandungsbrueckeSmall +#endif + + #include "tmc/helpers/API_Header.h" + + #if defined(Landungsbruecke) + #define MODULE_ID "0012" + #include + #include "hal/Landungsbruecke/freescale/Cpu.h" + #include "hal/Landungsbruecke/freescale/nvic.h" + #define CPU_LITTLE_ENDIAN + #define __MK_xxx_H__ + #elif defined(LandungsbrueckeV3) + #define MODULE_ID "0026" + #include "gd32f4xx.h" + #elif defined(LandungsbrueckeSmall) + // The Landungsbruecke (Small) is a normal Landungsbruecke but with a MK20DX256VLL10 µC instead. + // This other µC has less memory. We assign a different module ID, otherwise the functionality + // is identical to the normal Landungsbruecke. + #define MODULE_ID "0016" + #include + #include "hal/Landungsbruecke/freescale/Cpu.h" + #include "hal/Landungsbruecke/freescale/nvic.h" + #define CPU_LITTLE_ENDIAN + #define __MK_xxx_H__ + #else + #error "No Board selected" + #endif + +#endif /* _DERIVATIVE_H_ */ diff --git a/TMC2209/lib/tmc/helpers/API_Header.h b/TMC2209/lib/tmc/helpers/API_Header.h new file mode 100644 index 0000000..03c3619 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/API_Header.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_API_HEADER_H_ +#define TMC_API_HEADER_H_ + +#include "Config.h" +#include "Macros.h" +#include "Constants.h" +#include "Bits.h" +#include "CRC.h" +#include "RegisterAccess.h" +#include +#include "Types.h" + +// TODO: Restructure these. +/* + * Goal: Just give these values here as status back to the IDE when used with EvalSystem. + * Currently, this is obtained by just leaving out implementation specific error bits here. + */ +typedef enum { + TMC_ERROR_NONE = 0x00, + TMC_ERROR_GENERIC = 0x01, + TMC_ERROR_FUNCTION = 0x02, + TMC_ERROR_MOTOR = 0x08, + TMC_ERROR_VALUE = 0x10, + TMC_ERROR_CHIP = 0x40 +} TMCError; + +typedef enum { + TMC_COMM_DEFAULT, + TMC_COMM_SPI, + TMC_COMM_UART +} TMC_Comm_Mode; + +#endif /* TMC_API_HEADER_H_ */ diff --git a/TMC2209/lib/tmc/helpers/Bits.h b/TMC2209/lib/tmc/helpers/Bits.h new file mode 100644 index 0000000..c5be24c --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Bits.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +// BIT DEFINITION +#ifndef TMC_BITS_H_ +#define TMC_BITS_H_ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define BYTE0_MASK 0x00000000000000FF +#define BYTE0_SHIFT 0 +#define BYTE1_MASK 0x000000000000FF00 +#define BYTE1_SHIFT 8 +#define BYTE2_MASK 0x0000000000FF0000 +#define BYTE2_SHIFT 16 +#define BYTE3_MASK 0x00000000FF000000 +#define BYTE3_SHIFT 24 +#define BYTE4_MASK 0x000000FF00000000 +#define BYTE4_SHIFT 32 +#define BYTE5_MASK 0x0000FF0000000000 +#define BYTE5_SHIFT 40 +#define BYTE6_MASK 0x00FF000000000000 +#define BYTE6_SHIFT 48 +#define BYTE7_MASK 0xFF00000000000000 +#define BYTE7_SHIFT 56 + +#define SHORT0_MASK (BYTE0_MASK|BYTE1_MASK) +#define SHORT0_SHIFT BYTE0_SHIFT +#define SHORT1_MASK (BYTE2_MASK|BYTE3_MASK) +#define SHORT1_SHIFT BYTE2_SHIFT +#define SHORT2_MASK (BYTE4_MASK|BYTE5_MASK) +#define SHORT2_SHIFT BYTE4_SHIFT +#define SHORT3_MASK (BYTE6_MASK|BYTE7_MASK) +#define SHORT3_SHIFT BYTE6_SHIFT + +#define WORD0_MASK (SHORT0_MASK|SHORT1_MASK) +#define WORD0_SHIFT SHORT0_SHIFT +#define WORD1_MASK (SHORT2_MASK|SHORT3_MASK) +#define WORD1_SHIFT SHORT2_SHIFT + +#define NIBBLE(value, n) (((value) >> ((n) << 2)) & 0x0F) +#define BYTE(value, n) (((value) >> ((n) << 3)) & 0xFF) +#define SHORT(value, n) (((value) >> ((n) << 4)) & 0xFFFF) +#define WORD(value, n) (((value) >> ((n) << 5)) & 0xFFFFFFFF) + +#define _8_16(__1, __0) (((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) + +#define _8_32(__3, __2, __1, __0) (((__3) << BYTE3_SHIFT) | ((__2) << BYTE2_SHIFT) | ((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) +#define _16_32(__1, __0) (((__1) << SHORT1_SHIFT) | ((__0) << SHORT0_SHIFT)) + +#define _8_64(__7, __6, __5, __4, __3, __2, __1, __0) (((__7) << BYTE7_SHIFT) | ((__6) << BYTE6_SHIFT) | ((__5) << BYTE5_SHIFT) | ((__4) << BYTE4_SHIFT) | ((__3) << BYTE3_SHIFT) | ((__2) << BYTE2_SHIFT) | ((__1) << BYTE1_SHIFT) | ((__0) << BYTE0_SHIFT)) +#define _16_64(__3, __2, __1, __0) (((__3) << SHORT3_SHIFT) | ((__2) << SHORT2_SHIFT) | ((__1) << SHORT1_SHIFT) | ((__0) << SHORT0_SHIFT)) +#define _32_64(__1, __0) (((__1) << WORD1_SHIFT) | ((__0) << WORD0_SHIFT)) + +#endif /* TMC_BITS_H_ */ diff --git a/TMC2209/lib/tmc/helpers/CRC.c b/TMC2209/lib/tmc/helpers/CRC.c new file mode 100644 index 0000000..c796ff9 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/CRC.c @@ -0,0 +1,214 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * This is a generic implementation for a CRC8 generator supporting + * both compile-time (1) and run-time initialized Lookup tables for efficient CRC8 calculation. + * You can store multiple tables for different polynomials and (non-)reflected CRCs. + * The different tables are referenced by an index, with an upper limit set at compile time (CRC_TABLE_COUNT). + * + * To generate CRCs you must first generate the Lookup-table by calling fillCRCTable() + * with any index. CRCs can then be generated from any data buffer by calling CRC() + * with the same index previously given to fillCRCTable(). + * + * The table generation has been optimized for speed so that the runtime + * table generation can even be done during normal operation if required. + * However, as long as the required polynomials are known on initialization, + * the table generation should be done at that time. + * On the Landungsbruecke the initialization of a CRC table takes ~250µs. (2) + * Should your application still have problems with the table calculation time, + * this algorithm could probably be speed up by preparing a 2- or 4-bit lookup table + * to speed up the actual table generation. + * + * (1): For compile-time CRC tables, just fill the table(s) by initializing CRCTables[] to the proper values. + * (2): Tested by toggling a GPIO pin, generating a table in-between and measuring the GPIO pulse width. + */ + +#include "CRC.h" + +typedef struct { + uint8_t table[256]; + uint8_t polynomial; + bool isReflected; +} CRCTypeDef; + +CRCTypeDef CRCTables[CRC_TABLE_COUNT] = { 0 }; + +static uint8_t flipByte(uint8_t value); +static uint32_t flipBitsInBytes(uint32_t value); + +/* This function generates the Lookup table used for CRC calculations. + * + * Arguments: + * uint8_t polynomial: The CRC polynomial for which the table will be generated. + * bool isReflected: Indicator whether the CRC table will be reflected or not. + * uint8_t index: The index of the table to be filled. + * + * How it works: + * A CRC calculation of a byte can be done by taking the byte to be CRC'd, + * shifting it left by one (appending a 0) and - if a 1 has been shifted out - + * XOR-ing in the CRC polynomial. After 8 iterations the result will be the + * CRC of the Byte. + * + * The function below does this in a compact way, by using all 4 bytes of a + * uint32_t to do 4 separate CRC bytes at once. + * For this to work without the Byte shifting interfering with adjacent bytes, + * the polynomial has the 8th bit (0x100) set. That way, if the shifted-out bit + * is 1, the following XOR-ing with the CRC polynomial will set that 1 to a 0, + * resulting in the shifted-in 0 for the adjacent byte. + * This process will go from the the lowest to the highest byte, resulting in + * fully independent byte-wise CRC calculations. For the highest byte, the value + * of the shifted-out byte needs to be stored before shifting the bytes (isMSBSet). + * + * The for-loop that iterates over all uint8_t values starts out with the + * uint8_t values 3 to 0 stored in one uint32_t: 0x03020100 + * for each iteration each uint8_t value will increase by 4.. + * 0 -> 4 -> 8 -> C -> ... + * 1 -> 5 -> 9 -> D -> ... + * 2 -> 6 -> A -> E -> ... + * 3 -> 7 -> B -> F -> ... + * ..resulting in an increase of the uint32_t by 0x04040404: + * 0x03020100 -> 0x07060504 -> 0x0B0A0908 -> 0x0F0E0D0C -> ... + * The loop ends as soon as we have iterated over all uint8_t values. + * We detect that by looking for the byte-wise overflow into the next byte: + * 0xFFFEFDFC <- last uint32_t value to be calculated + * 0xFF, 0xFE, 0xFD, 0xFC <- the corresponding uint8_t values + * 0x103, 0x102, 0x101, 0x100 <- incremented uint8_t values (overflow into the next byte!) + * 0x04030200 <- uint32_t value with the overflowed bytes + * + * We have the lower uint8_t values at the lower bytes of the uint32_t. + * This allows us to simply store the lowest byte of the uint32_t, + * right-shift the uint32_t by 8 and increment the table pointer. + * After 4 iterations of that all 4 bytes of the uint32_t are stored in the table. + */ +uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index) +{ + uint32_t CRCdata; + // Helper pointer for traversing the result table + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + CRCTables[index].polynomial = polynomial; + CRCTables[index].isReflected = isReflected; + table = &CRCTables[index].table[0]; + + // Extend the polynomial to correct byte MSBs shifting into next bytes + uint32_t poly = (uint32_t) polynomial | 0x0100; + + // Iterate over all 256 possible uint8_t values, compressed into a uint32_t (see detailed explanation above) + uint32_t i; + for(i = 0x03020100; i != 0x04030200; i+=0x04040404) + { + // For reflected table: Flip the bits of each input byte + CRCdata = (isReflected)? flipBitsInBytes(i) : i; + + // Iterate over 8 Bits + int j; + for(j = 0; j < 8; j++) + { + // Store value of soon-to-be shifted out byte + uint8_t isMSBSet = (CRCdata & 0x80000000)? 1:0; + + // CRC Shift + CRCdata <<= 1; + + // XOR the bytes when required, lowest to highest + CRCdata ^= (CRCdata & 0x00000100)? (poly ) : 0; + CRCdata ^= (CRCdata & 0x00010000)? (poly << 8 ) : 0; + CRCdata ^= (CRCdata & 0x01000000)? (poly << 16) : 0; + CRCdata ^= (isMSBSet)? (poly << 24) : 0; + } + + // For reflected table: Flip the bits of each output byte + CRCdata = (isReflected)? flipBitsInBytes(CRCdata) : CRCdata; + // Store the CRC result bytes in the table array + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + } + + return 1; +} + +/* This function calculates the CRC from a data buffer + * + * Arguments: + * uint8_t *data: A pointer to the data that will be CRC'd. + * uint32_t bytes: The length of the data buffer. + * uint8_t index: The index of the CRC table to be used. + */ +uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index) +{ + uint8_t result = 0; + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + table = &CRCTables[index].table[0]; + + while(bytes--) + result = table[result ^ *data++]; + + return (CRCTables[index].isReflected)? flipByte(result) : result; +} + +uint8_t tmc_tableGetPolynomial(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return 0; + + return CRCTables[index].polynomial; +} + +bool tmc_tableIsReflected(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return false; + + return CRCTables[index].isReflected; +} + +// Helper functions +static uint8_t flipByte(uint8_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55) | ((value & 0x55) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33) | ((value & 0x33) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F) | ((value & 0x0F) << 4); + + return value; +} + +/* This helper function switches all bits within each byte. + * The byte order remains the same: + * [b31 b30 b29 b28 b27 b26 b25 b24 .. b7 b6 b5 b4 b3 b2 b1 b0] + * || + * \||/ + * \/ + * [b24 b25 b26 b27 b28 b29 b30 b31 .. b0 b1 b2 b3 b4 b5 b6 b7] + */ +static uint32_t flipBitsInBytes(uint32_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55555555) | ((value & 0x55555555) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33333333) | ((value & 0x33333333) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F0F0F0F) | ((value & 0x0F0F0F0F) << 4); + + return value; +} diff --git a/TMC2209/lib/tmc/helpers/CRC.h b/TMC2209/lib/tmc/helpers/CRC.h new file mode 100644 index 0000000..21988d9 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/CRC.h @@ -0,0 +1,25 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CRC_H_ +#define TMC_HELPERS_CRC_H_ + + #include "Types.h" + + // Amount of CRC tables available + // Each table takes ~260 bytes (257 bytes, one bool and structure padding) + #define CRC_TABLE_COUNT 2 + + uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index); + uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index); + + uint8_t tmc_tableGetPolynomial(uint8_t index); + bool tmc_tableIsReflected(uint8_t index); + +#endif /* TMC_HELPERS_CRC_H_ */ diff --git a/TMC2209/lib/tmc/helpers/Config.h b/TMC2209/lib/tmc/helpers/Config.h new file mode 100644 index 0000000..156d9f5 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Config.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CONFIG_H_ +#define TMC_HELPERS_CONFIG_H_ + +#include "Constants.h" +#include "Types.h" + +// Callback functions have IC-dependent parameters +// To store the function pointers we use this dummy type, which is never +// called without casting it to the IC-specific type first. +// (Casting between function pointers is allowed by the C standard) +typedef void (*tmc_callback_config)(void); + +// States of a configuration +typedef enum { + CONFIG_READY, + CONFIG_RESET, + CONFIG_RESTORE +} ConfigState; + +// structure for configuration mechanism +typedef struct +{ + ConfigState state; + uint8_t configIndex; + int32_t shadowRegister[TMC_REGISTER_COUNT]; + uint8_t (*reset) (void); + uint8_t (*restore) (void); + tmc_callback_config callback; + uint8_t channel; +} ConfigurationTypeDef; + +#endif /* TMC_HELPERS_CONFIG_H_ */ diff --git a/TMC2209/lib/tmc/helpers/Constants.h b/TMC2209/lib/tmc/helpers/Constants.h new file mode 100644 index 0000000..fdcd776 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Constants.h @@ -0,0 +1,24 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_HELPERS_CONSTANTS_H_ +#define TMC_HELPERS_CONSTANTS_H_ + +#define TMC_WRITE_BIT 0x80 + +#define TMC_ADDRESS_MASK 0x7F + +#define TMC_DEFAULT_MOTOR 0 + +//#define TMC_DIRECTION_RIGHT TRUE +//#define TMC_DIRECTION_LEFT FALSE + +#define TMC_REGISTER_COUNT 128 // Default register count + +#endif /* TMC_HELPERS_CONSTANTS_H_ */ diff --git a/TMC2209/lib/tmc/helpers/Functions.c b/TMC2209/lib/tmc/helpers/Functions.c new file mode 100644 index 0000000..764102e --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Functions.c @@ -0,0 +1,173 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Functions.h" + +int32_t tmc_limitInt(int32_t value, int32_t min, int32_t max) +{ + if (value > max) + return max; + else if (value < min) + return min; + else + return value; +} + +int64_t tmc_limitS64(int64_t value, int64_t min, int64_t max) +{ + if (value > max) + return max; + else if (value < min) + return min; + else + return value; +} + +/* lookup table for square root function */ +static const unsigned char sqrttable[256] = +{ + 0, 16, 22, 27, 32, 35, 39, 42, 45, 48, 50, 53, 55, 57, 59, 61, + 64, 65, 67, 69, 71, 73, 75, 76, 78, 80, 81, 83, 84, 86, 87, 89, + 90, 91, 93, 94, 96, 97, 98, 99, 101, 102, 103, 104, 106, 107, 108, 109, + 110, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, + 128, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, + 143, 144, 144, 145, 146, 147, 148, 149, 150, 150, 151, 152, 153, 154, 155, 155, + 156, 157, 158, 159, 160, 160, 161, 162, 163, 163, 164, 165, 166, 167, 167, 168, + 169, 170, 170, 171, 172, 173, 173, 174, 175, 176, 176, 177, 178, 178, 179, 180, + 181, 181, 182, 183, 183, 184, 185, 185, 186, 187, 187, 188, 189, 189, 190, 191, + 192, 192, 193, 193, 194, 195, 195, 196, 197, 197, 198, 199, 199, 200, 201, 201, + 202, 203, 203, 204, 204, 205, 206, 206, 207, 208, 208, 209, 209, 210, 211, 211, + 212, 212, 213, 214, 214, 215, 215, 216, 217, 217, 218, 218, 219, 219, 220, 221, + 221, 222, 222, 223, 224, 224, 225, 225, 226, 226, 227, 227, 228, 229, 229, 230, + 230, 231, 231, 232, 232, 233, 234, 234, 235, 235, 236, 236, 237, 237, 238, 238, + 239, 240, 240, 241, 241, 242, 242, 243, 243, 244, 244, 245, 245, 246, 246, 247, + 247, 248, 248, 249, 249, 250, 250, 251, 251, 252, 252, 253, 253, 254, 254, 255 +}; + +int32_t tmc_sqrti(int32_t x) +{ + int32_t xn; + + // Negative parameter? + if (x < 0) + return -1; + + if (x < 0x0100) + return (int32_t) sqrttable[x] >> 4; + + if (x >= 0x00010000) + { + if (x >= 0x01000000) + { + if (x >= 0x10000000) + { + if (x >= 0x40000000) + { + // 0x40000000 <= x < 0x7FFFFFFF + xn = (int32_t) sqrttable[x >> 24] << 8; + } + else + { + // 0x10000000 <= x < 0x40000000 + xn = (int32_t) sqrttable[x >> 22] << 7; + } + } + else + { + if (x >= 0x04000000) + { + // 0x04000000 <= x < 0x10000000 + xn = (int32_t) sqrttable[x >> 20] << 6; + } + else + { + // 0x01000000 <= x < 0x04000000 + xn = (int32_t) sqrttable[x >> 18] << 5; + } + } + + // Two steps of the babylonian method + xn = (xn + 1 + (x / xn)) >> 1; + xn = (xn + 1 + (x / xn)) >> 1; + } + else + { + if (x >= 0x00100000) + { + if (x >= 0x00400000) + { + // 0x00400000 <= x < 0x01000000 + xn = (int32_t) sqrttable[x >> 16] << 4; + } + else + { + // 0x00100000 <= x < 0x00400000 + xn = (int32_t) sqrttable[x >> 14] << 3; + } + } + else + { + if (x >= 0x00040000) + { + // 0x00040000 <= x < 0x00100000 + xn = (int32_t) sqrttable[x >> 12] << 2; + } + else + { + // 0x00010000 <= x < 0x00040000 + xn = (int32_t) sqrttable[x >> 10] << 1; + } + } + + // One step of the babylonian method + xn = (xn + 1 + (x / xn)) >> 1; + } + } + else + { + if (x >= 0x1000) + { + if (x >= 0x4000) + { + // 0x4000 <= x < 0x00010000 + xn = (int32_t) (sqrttable[x >> 8] ) + 1; + } + else + { + // 0x1000 <= x < 0x4000 + xn = (int32_t) (sqrttable[x >> 6] >> 1) + 1; + } + } + else + { + if (x >= 0x0400) + { + // 0x0400 <= x < 0x1000 + xn = (int32_t) (sqrttable[x >> 4] >> 2) + 1; + } + else + { + // 0x0100 <= x < 0x0400 + xn = (int32_t) (sqrttable[x >> 2] >> 3) + 1; + } + } + } + + // Make sure that our result is floored + if ((xn * xn) > x) + xn--; + + return xn; +} + +int32_t tmc_filterPT1(int64_t *akku, int32_t newValue, int32_t lastValue, uint8_t actualFilter, uint8_t maxFilter) +{ + *akku += (newValue-lastValue) << (maxFilter-actualFilter); + return *akku >> maxFilter; +} diff --git a/TMC2209/lib/tmc/helpers/Functions.h b/TMC2209/lib/tmc/helpers/Functions.h new file mode 100644 index 0000000..af92303 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Functions.h @@ -0,0 +1,20 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_FUNCTIONS_H_ +#define TMC_FUNCTIONS_H_ + +#include "API_Header.h" + +int32_t tmc_limitInt(int32_t value, int32_t min, int32_t max); +int64_t tmc_limitS64(int64_t value, int64_t min, int64_t max); +int32_t tmc_sqrti(int32_t x); +int32_t tmc_filterPT1(int64_t *akku, int32_t newValue, int32_t lastValue, uint8_t actualFilter, uint8_t maxFilter); + +#endif /* TMC_FUNCTIONS_H_ */ diff --git a/TMC2209/lib/tmc/helpers/Macros.h b/TMC2209/lib/tmc/helpers/Macros.h new file mode 100644 index 0000000..2914237 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Macros.h @@ -0,0 +1,59 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_MACROS_H_ +#define TMC_MACROS_H_ + +/* Cast a n bit signed int to a 32 bit signed int + * This is done by checking the MSB of the signed int (Bit n). + * If it is 1, the value is negative and the Bits 32 to n+1 are set to 1 + * If it is 0, the value remains unchanged + */ +#define CAST_Sn_TO_S32(value, n) ((value) | (((value) & ((uint32_t)1<<((n)-1)))? ~(((uint32_t)1<<(n))-1) : 0 )) + +// Min/Max macros +#ifndef MIN + #define MIN(a,b) (((a)<(b)) ? (a) : (b)) +#endif +#ifndef MAX + #define MAX(a,b) (((a)>(b)) ? (a) : (b)) +#endif + +// Static Array length +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#endif + +// Generic mask/shift macros +#define FIELD_GET(data, mask, shift) \ + (((data) & (mask)) >> (shift)) +#define FIELD_SET(data, mask, shift, value) \ + (((data) & (~(mask))) | (((value) << (shift)) & (mask))) + +// Register read/write/update macros using Mask/Shift: +#define FIELD_READ(read, motor, address, mask, shift) \ + FIELD_GET(read(motor, address), mask, shift) +#define FIELD_WRITE(write, motor, address, mask, shift, value) \ + (write(motor, address, ((value)<<(shift)) & (mask))) +#define FIELD_UPDATE(read, write, motor, address, mask, shift, value) \ + (write(motor, address, FIELD_SET(read(motor, address), mask, shift, value))) + +// Macro to surpress unused parameter warnings +#ifndef UNUSED + #define UNUSED(x) (void)(x) +#endif + +// Memory access helpers +// Force the compiler to access a location exactly once +#define ACCESS_ONCE(x) *((volatile typeof(x) *) (&x)) + +// Macro to remove write bit for shadow register array access +#define TMC_ADDRESS(x) ((x) & (TMC_ADDRESS_MASK)) + +#endif /* TMC_MACROS_H_ */ diff --git a/TMC2209/lib/tmc/helpers/RegisterAccess.h b/TMC2209/lib/tmc/helpers/RegisterAccess.h new file mode 100644 index 0000000..e0167b3 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/RegisterAccess.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * The permission system aims to allow a general-purpose implementation for + * all common hardware register usages. This includes: + * - Trivial Cases: Read, Write, Read & Write + * + * - Read & Write accesses that route to different values/functions of a chip. + * (e.g. serial communication, where read/write corresponds to RX/TX) + * - Read to clear, write to clear. This does not directly affect the access, + * but can be used to implement a software shadow register for flags + * (ORing the read value into a shadow register instead of overwriting). + * - Registers with default values that are not known (e.g. Factory configuration + * values that should not be overwritten by default). + */ + +#ifndef TMC_HELPERS_REGISTERACCESS_H +#define TMC_HELPERS_REGISTERACCESS_H + +// Register access bits +/* Lower nibble is used for read/write, higher nibble is used for + * special case registers. This makes it easy to identify the read/write + * part of the permissions in a hexadecimal permission number. + * The dirty bit will only ever be set at runtime, so we keep the easily + * readable lower nibble. + */ +#define TMC_ACCESS_NONE 0x00 + +#define TMC_ACCESS_READ 0x01 +#define TMC_ACCESS_WRITE 0x02 + // 0x04 is currently unused +#define TMC_ACCESS_DIRTY 0x08 // Register has been written since reset -> shadow register is valid for restore + +// Special Register bits +#define TMC_ACCESS_RW_SPECIAL 0x10 // Read and write are independent - different values and/or different functions +#define TMC_ACCESS_FLAGS 0x20 // Register has read or write to clear flags. +#define TMC_ACCESS_HW_PRESET 0x40 // Register has hardware presets (e.g. Factory calibrations) - do not write a default value + // 0x80 is currently unused + +// Permission combinations +#define TMC_ACCESS_RW (TMC_ACCESS_READ | TMC_ACCESS_WRITE) // 0x03 - Read and write +#define TMC_ACCESS_RW_SEPARATE (TMC_ACCESS_RW | TMC_ACCESS_RW_SPECIAL) // 0x13 - Read and write, with separate values/functions +#define TMC_ACCESS_R_FLAGS (TMC_ACCESS_READ | TMC_ACCESS_FLAGS) // 0x21 - Read, has flags (read to clear) +#define TMC_ACCESS_RW_FLAGS (TMC_ACCESS_RW | TMC_ACCESS_FLAGS) // 0x23 - Read and write, has flags (read or write to clear) +#define TMC_ACCESS_W_PRESET (TMC_ACCESS_WRITE | TMC_ACCESS_HW_PRESET) // 0x42 - Write, has hardware preset - skipped in reset routine +#define TMC_ACCESS_RW_PRESET (TMC_ACCESS_RW | TMC_ACCESS_HW_PRESET) // 0x43 - Read and write, has hardware presets - skipped in reset routine + +// Helper macros +#define TMC_IS_READABLE(x) ((x) & TMC_ACCESS_READ) +#define TMC_IS_WRITABLE(x) ((x) & TMC_ACCESS_WRITE) +#define TMC_IS_DIRTY(x) ((x) & TMC_ACCESS_DIRTY) +#define TMC_IS_PRESET(x) ((x) & TMC_ACCESS_HW_PRESET) +#define TMC_IS_RESETTABLE(x) (((x) & (TMC_ACCESS_W_PRESET)) == TMC_ACCESS_WRITE) // Write bit set, Hardware preset bit not set +#define TMC_IS_RESTORABLE(x) (((x) & TMC_ACCESS_WRITE) && (!(x & TMC_ACCESS_HW_PRESET) || (x & TMC_ACCESS_DIRTY))) // Write bit set, if it's a hardware preset register, it needs to be dirty + +// Struct for listing registers that have constant contents which we cannot +// obtain by reading them due to the register not being read-back. +typedef struct +{ + uint8_t address; + uint32_t value; +} TMCRegisterConstant; + +// Helper define: +// Most register permission arrays are initialized with 128 values. +// In those fields its quite hard to have an easy overview of available +// registers. For that, ____ is defined to 0, since 4 underscores are +// very easy to distinguish from the 2-digit hexadecimal values. +// This way, the used registers (permission != ACCESS_NONE) are easily spotted +// amongst unused (permission == ACCESS_NONE) registers. +#define ____ 0x00 + +// Helper define: +// Default reset values are not used if the corresponding register has a +// hardware preset. Since this is not directly visible in the default +// register reset values array, N_A is used as an indicator for a preset +// value, where any value will be ignored anyways (N_A: not available). +#define N_A 0 + +#endif /* TMC_HELPERS_REGISTERACCESS_H */ diff --git a/TMC2209/lib/tmc/helpers/Types.h b/TMC2209/lib/tmc/helpers/Types.h new file mode 100644 index 0000000..fccb079 --- /dev/null +++ b/TMC2209/lib/tmc/helpers/Types.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +// Turn off the integer typedefs by uncommenting the following two defines. +// If your IDE (e.g. Arduino IDE) already defines these types, deactivating +// these typedefs will fix errors and/or warnings. +//#define TMC_SKIP_UINT_TYPEDEFS // Disable u8, u16, u32, uint8, uint16 and uint32 typedefs +//#define TMC_SKIP_INT_TYPEDEFS // Disable s8, s16, s32, int8, int16 and int32 typedefs + +#ifndef TMC_TYPES_H_ +#define TMC_TYPES_H_ + +#include +#include +#include + +#ifndef TMC_TYPES_INTEGERS +#define TMC_TYPES_INTEGERS + +// todo: change to standard ISO C99 types (ED) + +// www.open-std.org/JTC1/SC22/WG14/www/docs/n1256.pdf +// ISO C99: 7.18 Integer types 8, 16, 32, or 64 bits +// intN_t = two’s complement signed integer type with width N, no padding bits. +// uintN_t = an unsigned integer type with width N. +// floatN_t = N bit IEE 754 float. +// INT8_MIN, INT8_MAX, INT16_MIN, INT16_MAX, INT32_MIN, INT32_MAX, .... UINT32_MAX + +typedef float float32_t; +typedef double float64_t; + +#ifndef TMC_TYPES_INTEGERS_UNSIGNED +#define TMC_TYPES_INTEGERS_UNSIGNED + +#ifndef TMC_SKIP_UINT_TYPEDEFS +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +typedef uint8_t uint8; +typedef uint16_t uint16; +typedef uint32_t uint32; +#endif /* TMC_SKIP_UINT_TYPEDEFS */ + +#define u8_MAX (uint8_t) 255 +#define u10_MAX (uint16_t) 1023 +#define u12_MAX (uint16_t) 4095 +#define u15_MAX (uint16_t) 32767 +#define u16_MAX (uint16_t) 65535 +#define u18_MAX (uint32_t) 262143uL +#define u20_MAX (uint32_t) 1048575uL +#define u22_MAX (uint32_t) 4194303uL +#define u24_MAX (uint32_t) 16777215uL +#define u32_MAX (uint32_t) 4294967295uL + +#endif /* TMC_TYPES_INTEGERS_UNSIGNED */ + +#ifndef TMC_TYPES_INTEGERS_SIGNED +#define TMC_TYPES_INTEGERS_SIGNED + +#ifndef TMC_SKIP_INT_TYPEDEFS +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; + +typedef int8_t int8; +typedef int16_t int16; +typedef int32_t int32; +#endif /* TMC_SKIP_INT_TYPEDEFS */ + +#define s8_MAX (int8_t) 127 +#define s8_MIN (int8_t) -128 +#define s16_MAX (int16_t) 32767 +#define s16_MIN (int16_t) -32768 +#define s24_MAX (int32_t) 8388607 +#define s24_MIN (int32_t) -8388608 +#define s32_MAX (int32_t) 2147483647 +#define s32_MIN (int32_t) -2147483648 + +#endif /* TMC_TYPES_INTEGERS_SIGNED */ + +#endif /* TMC_TYPES_INTEGERS */ + +#ifndef TMC_TYPES_NULL +#define TMC_TYPES_NULL + +#ifndef NULL +#define NULL ((void *) 0) +#endif /* NULL */ + +#ifndef FALSE +#define FALSE false +#endif + +#ifndef TRUE +#define TRUE true +#endif + +#endif /* TMC_TYPES_NULL */ + +#endif /* TMC_TYPES_H_ */ diff --git a/TMC2209/lib/tmc/ic/TMC2209/TMC2209.c b/TMC2209/lib/tmc/ic/TMC2209/TMC2209.c new file mode 100644 index 0000000..7143558 --- /dev/null +++ b/TMC2209/lib/tmc/ic/TMC2209/TMC2209.c @@ -0,0 +1,492 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMC2209.h" +#include "tmc/hal/UART.h" +#include "tmc/helpers/CRC.h" + + + + + + + + + + +typedef struct { + uint8_t table[256]; + uint8_t polynomial; + bool isReflected; +} CRCTypeDef; + +CRCTypeDef CRCTables[CRC_TABLE_COUNT] = { 0 }; + +static uint8_t flipByte(uint8_t value); +static uint32_t flipBitsInBytes(uint32_t value); + +/* This function generates the Lookup table used for CRC calculations. + * + * Arguments: + * uint8_t polynomial: The CRC polynomial for which the table will be generated. + * bool isReflected: Indicator whether the CRC table will be reflected or not. + * uint8_t index: The index of the table to be filled. + * + * How it works: + * A CRC calculation of a byte can be done by taking the byte to be CRC'd, + * shifting it left by one (appending a 0) and - if a 1 has been shifted out - + * XOR-ing in the CRC polynomial. After 8 iterations the result will be the + * CRC of the Byte. + * + * The function below does this in a compact way, by using all 4 bytes of a + * uint32_t to do 4 separate CRC bytes at once. + * For this to work without the Byte shifting interfering with adjacent bytes, + * the polynomial has the 8th bit (0x100) set. That way, if the shifted-out bit + * is 1, the following XOR-ing with the CRC polynomial will set that 1 to a 0, + * resulting in the shifted-in 0 for the adjacent byte. + * This process will go from the the lowest to the highest byte, resulting in + * fully independent byte-wise CRC calculations. For the highest byte, the value + * of the shifted-out byte needs to be stored before shifting the bytes (isMSBSet). + * + * The for-loop that iterates over all uint8_t values starts out with the + * uint8_t values 3 to 0 stored in one uint32_t: 0x03020100 + * for each iteration each uint8_t value will increase by 4.. + * 0 -> 4 -> 8 -> C -> ... + * 1 -> 5 -> 9 -> D -> ... + * 2 -> 6 -> A -> E -> ... + * 3 -> 7 -> B -> F -> ... + * ..resulting in an increase of the uint32_t by 0x04040404: + * 0x03020100 -> 0x07060504 -> 0x0B0A0908 -> 0x0F0E0D0C -> ... + * The loop ends as soon as we have iterated over all uint8_t values. + * We detect that by looking for the byte-wise overflow into the next byte: + * 0xFFFEFDFC <- last uint32_t value to be calculated + * 0xFF, 0xFE, 0xFD, 0xFC <- the corresponding uint8_t values + * 0x103, 0x102, 0x101, 0x100 <- incremented uint8_t values (overflow into the next byte!) + * 0x04030200 <- uint32_t value with the overflowed bytes + * + * We have the lower uint8_t values at the lower bytes of the uint32_t. + * This allows us to simply store the lowest byte of the uint32_t, + * right-shift the uint32_t by 8 and increment the table pointer. + * After 4 iterations of that all 4 bytes of the uint32_t are stored in the table. + */ +uint8_t tmc_fillCRC8Table(uint8_t polynomial, bool isReflected, uint8_t index) +{ + uint32_t CRCdata; + // Helper pointer for traversing the result table + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + CRCTables[index].polynomial = polynomial; + CRCTables[index].isReflected = isReflected; + table = &CRCTables[index].table[0]; + + // Extend the polynomial to correct byte MSBs shifting into next bytes + uint32_t poly = (uint32_t) polynomial | 0x0100; + + // Iterate over all 256 possible uint8_t values, compressed into a uint32_t (see detailed explanation above) + uint32_t i; + for(i = 0x03020100; i != 0x04030200; i+=0x04040404) + { + // For reflected table: Flip the bits of each input byte + CRCdata = (isReflected)? flipBitsInBytes(i) : i; + + // Iterate over 8 Bits + int j; + for(j = 0; j < 8; j++) + { + // Store value of soon-to-be shifted out byte + uint8_t isMSBSet = (CRCdata & 0x80000000)? 1:0; + + // CRC Shift + CRCdata <<= 1; + + // XOR the bytes when required, lowest to highest + CRCdata ^= (CRCdata & 0x00000100)? (poly ) : 0; + CRCdata ^= (CRCdata & 0x00010000)? (poly << 8 ) : 0; + CRCdata ^= (CRCdata & 0x01000000)? (poly << 16) : 0; + CRCdata ^= (isMSBSet)? (poly << 24) : 0; + } + + // For reflected table: Flip the bits of each output byte + CRCdata = (isReflected)? flipBitsInBytes(CRCdata) : CRCdata; + // Store the CRC result bytes in the table array + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + CRCdata >>= 8; + *table++ = (uint8_t) CRCdata; + } + + return 1; +} + +/* This function calculates the CRC from a data buffer + * + * Arguments: + * uint8_t *data: A pointer to the data that will be CRC'd. + * uint32_t bytes: The length of the data buffer. + * uint8_t index: The index of the CRC table to be used. + */ +uint8_t tmc_CRC8(uint8_t *data, uint32_t bytes, uint8_t index) +{ + uint8_t result = 0; + uint8_t *table; + + if(index >= CRC_TABLE_COUNT) + return 0; + + table = &CRCTables[index].table[0]; + + while(bytes--) + result = table[result ^ *data++]; + + return (CRCTables[index].isReflected)? flipByte(result) : result; +} + +uint8_t tmc_tableGetPolynomial(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return 0; + + return CRCTables[index].polynomial; +} + +bool tmc_tableIsReflected(uint8_t index) +{ + if(index >= CRC_TABLE_COUNT) + return false; + + return CRCTables[index].isReflected; +} + +// Helper functions +static uint8_t flipByte(uint8_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55) | ((value & 0x55) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33) | ((value & 0x33) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F) | ((value & 0x0F) << 4); + + return value; +} + +/* This helper function switches all bits within each byte. + * The byte order remains the same: + * [b31 b30 b29 b28 b27 b26 b25 b24 .. b7 b6 b5 b4 b3 b2 b1 b0] + * || + * \||/ + * \/ + * [b24 b25 b26 b27 b28 b29 b30 b31 .. b0 b1 b2 b3 b4 b5 b6 b7] + */ +static uint32_t flipBitsInBytes(uint32_t value) +{ + // swap odd and even bits + value = ((value >> 1) & 0x55555555) | ((value & 0x55555555) << 1); + // swap consecutive pairs + value = ((value >> 2) & 0x33333333) | ((value & 0x33333333) << 2); + // swap nibbles ... + value = ((value >> 4) & 0x0F0F0F0F) | ((value & 0x0F0F0F0F) << 4); + + return value; +} + + + + + + + + + + + + + + + + + + + + +typedef union { + TMC2209TypeDef tmc2209; +} DriverBoards; + +DriverBoards driverBoards; +#define TMC2209_CRC(data, length) tmc_CRC8(data, length, 1) + +#define TMC2209 (driverBoards.tmc2209) +#define BUFFER_SIZE 32 +#define INTR_PRI 6 +#define UART_TIMEOUT_VALUE 10 +#define WRITE_READ_DELAY 10 +// #include "tmc/boards/Board.h" +// #include "tmc/tmc/StepDir.h" +// // => UART wrapper +// extern void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength); +// // <= UART wrapper + +// // => CRC wrapper +// extern uint8_t tmc2209_CRC8(uint8_t *data, size_t length); +// // <= CRC wrapper + +static UART_Config *TMC2209_UARTChannel; + +static inline TMC2209TypeDef *motorToIC(uint8_t motor) +{ + UNUSED(motor); + + return &TMC2209; +} + +static inline UART_Config *channelToUART(uint8_t channel) +{ + UNUSED(channel); + + return TMC2209_UARTChannel; +} + +// => UART wrapper + +int32_t UART_readWrite(UART_Config *uart, uint8_t *data, size_t writeLength, uint8_t readLength) +{ + uart->rxtx.clearBuffers(); + uart->rxtx.txN(data, writeLength); + /* Workaround: Give the UART time to send. Otherwise another write/readRegister can do clearBuffers() + * before we're done. This currently is an issue with the IDE when using the Register browser and the + * periodic refresh of values gets requested right after the write request. + */ + wait(WRITE_READ_DELAY); + + // Abort early if no data needs to be read back + if (readLength <= 0) + return 0; + + // Wait for reply with timeout limit + uint32_t timestamp = 0; + // while(uart->rxtx.bytesAvailable() < readLength) + // { + // if(timeSince(timestamp) > UART_TIMEOUT_VALUE) + // { + // Abort on timeout + // return -1; + // } + // } + + uart->rxtx.rxN(data, readLength); + + return 0; +} + +void tmc2209_readWriteArray(uint8_t channel, uint8_t *data, size_t writeLength, size_t readLength) +{ + UART_readWrite(channelToUART(channel), data, writeLength, readLength); +} +// <= UART wrapper + +// => CRC wrapper +// Return the CRC8 of [length] bytes of data stored in the [data] array. +uint8_t tmc2209_CRC8(uint8_t *data, size_t length) +{ + return TMC2209_CRC(data, length); +} +// <= CRC wrapper + +void tmc2209_writeRegister(uint8_t motor, uint16_t address, int32_t value) +{ + tmc2209_writeInt(motorToIC(motor), (uint8_t) address, value); + +} + +void tmc2209_readRegister(uint8_t motor, uint16_t address, int32_t *value) +{ + *value = tmc2209_readInt(motorToIC(motor), (uint8_t) address); +} + + +void tmc2209_writeInt(TMC2209TypeDef *tmc2209, uint8_t address, int32_t value) +{ + uint8_t data[8]; + + data[0] = 0x05; + data[1] = tmc2209->slaveAddress; + data[2] = address | TMC_WRITE_BIT; + data[3] = (value >> 24) & 0xFF; + data[4] = (value >> 16) & 0xFF; + data[5] = (value >> 8 ) & 0xFF; + data[6] = (value ) & 0xFF; + data[7] = tmc2209_CRC8(data, 7); + + tmc2209_readWriteArray(tmc2209->config->channel, &data[0], 8, 0); + + // Write to the shadow register and mark the register dirty + address = TMC_ADDRESS(address); + tmc2209->config->shadowRegister[address] = value; + tmc2209->registerAccess[address] |= TMC_ACCESS_DIRTY; +} + +int32_t tmc2209_readInt(TMC2209TypeDef *tmc2209, uint8_t address) +{ + uint8_t data[8] = { 0 }; + + address = TMC_ADDRESS(address); + + if (!TMC_IS_READABLE(tmc2209->registerAccess[address])) + return tmc2209->config->shadowRegister[address]; + + data[0] = 0x05; + data[1] = tmc2209->slaveAddress; + data[2] = address; + data[3] = tmc2209_CRC8(data, 3); + + tmc2209_readWriteArray(tmc2209->config->channel, data, 4, 8); + + // Byte 0: Sync nibble correct? + if (data[0] != 0x05) + return 0; + + // Byte 1: Master address correct? + if (data[1] != 0xFF) + return 0; + + // Byte 2: Address correct? + if (data[2] != address) + return 0; + + // Byte 7: CRC correct? + if (data[7] != tmc2209_CRC8(data, 7)) + return 0; + + return ((uint32_t)data[3] << 24) | ((uint32_t)data[4] << 16) | (data[5] << 8) | data[6]; +} + +void tmc2209_init(TMC2209TypeDef *tmc2209, uint8_t channel, uint8_t slaveAddress, ConfigurationTypeDef *tmc2209_config, const int32_t *registerResetState) +{ + tmc2209->slaveAddress = slaveAddress; + + tmc2209->config = tmc2209_config; + tmc2209->config->callback = NULL; + tmc2209->config->channel = channel; + tmc2209->config->configIndex = 0; + tmc2209->config->state = CONFIG_READY; + + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + { + tmc2209->registerAccess[i] = tmc2209_defaultRegisterAccess[i]; + tmc2209->registerResetState[i] = registerResetState[i]; + } +} + +static void writeConfiguration(TMC2209TypeDef *tmc2209) +{ + uint8_t *ptr = &tmc2209->config->configIndex; + const int32_t *settings; + + if(tmc2209->config->state == CONFIG_RESTORE) + { + settings = tmc2209->config->shadowRegister; + // Find the next restorable register + while((*ptr < TMC2209_REGISTER_COUNT) && !TMC_IS_RESTORABLE(tmc2209->registerAccess[*ptr])) + { + (*ptr)++; + } + } + else + { + settings = tmc2209->registerResetState; + // Find the next resettable register + while((*ptr < TMC2209_REGISTER_COUNT) && !TMC_IS_RESETTABLE(tmc2209->registerAccess[*ptr])) + { + (*ptr)++; + } + } + + if(*ptr < TMC2209_REGISTER_COUNT) + { + tmc2209_writeInt(tmc2209, *ptr, settings[*ptr]); + (*ptr)++; + } + else // Finished configuration + { + if(tmc2209->config->callback) + { + ((tmc2209_callback)tmc2209->config->callback)(tmc2209, tmc2209->config->state); + } + + tmc2209->config->state = CONFIG_READY; + } +} + +void tmc2209_periodicJob(TMC2209TypeDef *tmc2209, uint32_t tick) +{ + UNUSED(tick); + + if(tmc2209->config->state != CONFIG_READY) + { + writeConfiguration(tmc2209); + return; + } +} + +void tmc2209_setRegisterResetState(TMC2209TypeDef *tmc2209, const int32_t *resetState) +{ + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + tmc2209->registerResetState[i] = resetState[i]; +} + +void tmc2209_setCallback(TMC2209TypeDef *tmc2209, tmc2209_callback callback) +{ + tmc2209->config->callback = (tmc_callback_config) callback; +} + +uint8_t tmc2209_reset(TMC2209TypeDef *tmc2209) +{ + if(tmc2209->config->state != CONFIG_READY) + return false; + + // Reset the dirty bits and wipe the shadow registers + for(size_t i = 0; i < TMC2209_REGISTER_COUNT; i++) + { + tmc2209->registerAccess[i] &= ~TMC_ACCESS_DIRTY; + tmc2209->config->shadowRegister[i] = 0; + } + + tmc2209->config->state = CONFIG_RESET; + tmc2209->config->configIndex = 0; + + return true; +} + +uint8_t tmc2209_restore(TMC2209TypeDef *tmc2209) +{ + if(tmc2209->config->state != CONFIG_READY) + return false; + + tmc2209->config->state = CONFIG_RESTORE; + tmc2209->config->configIndex = 0; + + return true; +} + +uint8_t tmc2209_get_slave(TMC2209TypeDef *tmc2209) +{ + return tmc2209->slaveAddress; +} + +void tmc2209_set_slave(TMC2209TypeDef *tmc2209, uint8_t slaveAddress) +{ + tmc2209->slaveAddress = slaveAddress; +} diff --git a/TMC2209/lib/tmc/ic/TMC2209/TMC2209.h b/TMC2209/lib/tmc/ic/TMC2209/TMC2209.h new file mode 100644 index 0000000..d9bdc0e --- /dev/null +++ b/TMC2209/lib/tmc/ic/TMC2209/TMC2209.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_IC_TMC2209_H_ +#define TMC_IC_TMC2209_H_ + +#include "tmc/helpers/Constants.h" +#include "tmc/helpers/API_Header.h" +#include "TMC2209_Register.h" +#include "TMC2209_Constants.h" +#include "TMC2209_Fields.h" + +// Helper macros +#define TMC2209_FIELD_READ(tdef, address, mask, shift) \ + FIELD_GET(tmc2209_readInt(tdef, address), mask, shift) +#define TMC2209_FIELD_UPDATE(tdef, address, mask, shift, value) \ + (tmc2209_writeInt(tdef, address, FIELD_SET(tmc2209_readInt(tdef, address), mask, shift, value))) + +// Usage note: use 1 TypeDef per IC +typedef struct { + ConfigurationTypeDef *config; + + int32_t registerResetState[TMC2209_REGISTER_COUNT]; + uint8_t registerAccess[TMC2209_REGISTER_COUNT]; + + uint8_t slaveAddress; +} TMC2209TypeDef; + +typedef void (*tmc2209_callback)(TMC2209TypeDef*, ConfigState); + +// Default Register values +#define R00 0x00000040 // GCONF +#define R10 0x00071703 // IHOLD_IRUN +#define R11 0x00000014 // TPOWERDOWN +#define R6C 0x10000053 // CHOPCONF +#define R70 0xC10D0024 // PWMCONF + +// Register access permissions: +// 0x00: none (reserved) +// 0x01: read +// 0x02: write +// 0x03: read/write +// 0x13: read/write, separate functions/values for reading or writing +// 0x23: read/write, flag register (write to clear) +// 0x42: write, has hardware presets on reset +static const uint8_t tmc2209_defaultRegisterAccess[TMC2209_REGISTER_COUNT] = +{ +// 0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x03, 0x23, 0x01, 0x02, 0x02, 0x01, 0x01, 0x03, ____, ____, ____, ____, ____, ____, ____, ____, // 0x00 - 0x0F + 0x02, 0x02, 0x01, 0x02, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x10 - 0x1F + ____, ____, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x20 - 0x2F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x30 - 0x3F + 0x02, 0x01, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x40 - 0x4F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x50 - 0x5F + ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, 0x01, 0x01, 0x03, ____, ____, 0x01, // 0x60 - 0x6F + 0x03, 0x01, 0x01, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____ // 0x70 - 0x7F +}; + +static const int32_t tmc2209_defaultRegisterResetState[TMC2209_REGISTER_COUNT] = +{ +// 0 1 2 3 4 5 6 7 8 9 A B C D E F + R00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x00 - 0x0F + R10, R11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x10 - 0x1F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x20 - 0x2F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x30 - 0x3F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x40 - 0x4F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x50 - 0x5F + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R6C, 0, 0, 0, // 0x60 - 0x6F + R70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 // 0x70 - 0x7F +}; + +// Undefine the default register values. +// This prevents warnings in case multiple TMC-API chip headers are included at once +#undef R00 +#undef R10 +#undef R11 +#undef R6C +#undef R70 + +// Communication +void tmc2209_writeInt(TMC2209TypeDef *tmc2209, uint8_t address, int32_t value); +int32_t tmc2209_readInt(TMC2209TypeDef *tmc2209, uint8_t address); + +void tmc2209_init(TMC2209TypeDef *tmc2209, uint8_t channel, uint8_t slaveAddress, ConfigurationTypeDef *tmc2209_config, const int32_t *registerResetState); +uint8_t tmc2209_reset(TMC2209TypeDef *tmc2209); +uint8_t tmc2209_restore(TMC2209TypeDef *tmc2209); +void tmc2209_setRegisterResetState(TMC2209TypeDef *tmc2209, const int32_t *resetState); +void tmc2209_setCallback(TMC2209TypeDef *tmc2209, tmc2209_callback callback); +void tmc2209_periodicJob(TMC2209TypeDef *tmc2209, uint32_t tick); + +uint8_t tmc2209_get_slave(TMC2209TypeDef *tmc2209); +void tmc2209_set_slave(TMC2209TypeDef *tmc2209, uint8_t slaveAddress); + +#endif /* TMC_IC_TMC2209_H_ */ diff --git a/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h new file mode 100644 index 0000000..950dae0 --- /dev/null +++ b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Constants.h @@ -0,0 +1,20 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ +#define TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ + +#define TMC2209_MOTORS 1 +#define TMC2209_REGISTER_COUNT TMC_REGISTER_COUNT +#define TMC2209_WRITE_BIT TMC_WRITE_BIT +#define TMC2209_ADDRESS_MASK TMC_ADDRESS_MASK +#define TMC2209_MAX_VELOCITY s32_MAX +#define TMC2209_MAX_ACCELERATION u24_MAX + +#endif /* TMC_IC_TMC2209_TMC2209_CONSTANTS_H_ */ diff --git a/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h new file mode 100644 index 0000000..946c977 --- /dev/null +++ b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Fields.h @@ -0,0 +1,182 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC2209_FIELDS_H +#define TMC2209_FIELDS_H + +#define TMC2209_I_SCALE_ANALOG_MASK 0x01 // GCONF // I_scale_analog (Reset default=1) +#define TMC2209_I_SCALE_ANALOG_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_INTERNAL_RSENSE_MASK 0x02 // GCONF // internal_Rsense (Reset default: OTP) +#define TMC2209_INTERNAL_RSENSE_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_EN_SPREADCYCLE_MASK 0x04 // GCONF // en_spreadCycle (Reset default: OTP) +#define TMC2209_EN_SPREADCYCLE_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_SHAFT_MASK 0x08 // GCONF // controls motor direction +#define TMC2209_SHAFT_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_INDEX_OTPW_MASK 0x10 // GCONF // index_otpw +#define TMC2209_INDEX_OTPW_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_INDEX_STEP_MASK 0x20 // GCONF // index_step +#define TMC2209_INDEX_STEP_SHIFT 5 // min.: 0, max.: 1, default: 0 +#define TMC2209_PDN_DISABLE_MASK 0x40 // GCONF // pdn_disable +#define TMC2209_PDN_DISABLE_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_MSTEP_REG_SELECT_MASK 0x80 // GCONF // mstep_reg_select +#define TMC2209_MSTEP_REG_SELECT_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_MULTISTEP_FILT_MASK 0x0100 // GCONF // multistep_filt (Reset default=1) +#define TMC2209_MULTISTEP_FILT_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_TEST_MODE_MASK 0x0200 // GCONF // test_mode 0 +#define TMC2209_TEST_MODE_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_RESET_MASK 0x01 // GSTAT // reset +#define TMC2209_RESET_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_DRV_ERR_MASK 0x02 // GSTAT // drv_err +#define TMC2209_DRV_ERR_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_UV_CP_MASK 0x04 // GSTAT // uv_cp +#define TMC2209_UV_CP_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_IFCNT_MASK 0xFF // IFCNT // Interface transmission counter. This register becomes incremented with each successful UART interface write access. Read out to check the serial transmission for lost data. Read accesses do not change the content. The counter wraps around from 255 to 0. +#define TMC2209_IFCNT_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_SLAVECONF_MASK 0x0F00 // SLAVECONF // SENDDELAY for read access (time until reply is sent): 0, 1: 8 bit times 2, 3: 3*8 bit times 4, 5: 5*8 bit times 6, 7: 7*8 bit times 8, 9: 9*8 bit times 10, 11: 11*8 bit times 12, 13: 13*8 bit times 14, 15: 15*8 bit times +#define TMC2209_SLAVECONF_SHIFT 8 // min.: 0, max.: 15, default: 0 +#define TMC2209_OTPBIT_MASK 0x07 // OTP_PROG // Selection of OTP bit to be programmed to the selected byte location (n=0..7: programs bit n to a logic 1) +#define TMC2209_OTPBIT_SHIFT 0 // min.: 0, max.: 7, default: 0 +#define TMC2209_OTPBYTE_MASK 0x30 // OTP_PROG // Selection of OTP programming location (0, 1 or 2) +#define TMC2209_OTPBYTE_SHIFT 4 // min.: 0, max.: 3, default: 0 +#define TMC2209_OTPMAGIC_MASK 0xFF00 // OTP_PROG // Set to 0xBD to enable programming. A programming time of minimum 10ms per bit is recommended (check by reading OTP_READ). +#define TMC2209_OTPMAGIC_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP0_BYTE_0_READ_DATA_MASK 0x01 // OTP_READ // to be detailed +#define TMC2209_OTP0_BYTE_0_READ_DATA_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP1_BYTE_1_READ_DATA_MASK 0x02 // OTP_READ // to be detailed +#define TMC2209_OTP1_BYTE_1_READ_DATA_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_OTP2_BYTE_2_READ_DATA_MASK 0x04 // OTP_READ // to be detailed +#define TMC2209_OTP2_BYTE_2_READ_DATA_SHIFT 16 // min.: 0, max.: 255, default: 0 +#define TMC2209_ENN_MASK 0x01 // IOIN // +#define TMC2209_ENN_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_MS1_MASK 0x04 // IOIN // +#define TMC2209_MS1_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_MS2_MASK 0x08 // IOIN // +#define TMC2209_MS2_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_DIAG_MASK 0x10 // IOIN // +#define TMC2209_DIAG_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_PDN_UART_MASK 0x40 // IOIN // +#define TMC2209_PDN_UART_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_STEP_MASK 0x80 // IOIN // +#define TMC2209_STEP_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_SEL_A_MASK 0x0100 // IOIN // Driver type +#define TMC2209_SEL_A_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_DIR_MASK 0x0200 // IOIN // +#define TMC2209_DIR_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_VERSION_MASK 0xFF000000 // IOIN // VERSION: 0x20=first version of the IC Identical numbers mean full digital compatibility. +#define TMC2209_VERSION_SHIFT 24 // min.: 0, max.: 255, default: 0 +#define TMC2209_FCLKTRIM_MASK 0x1F // FACTORY_CONF // FCLKTRIM (Reset default: OTP) 0-31: Lowest to highest clock frequency. Check at charge pump output. The frequency span is not guaranteed, but it is tested, that tuning to 12MHz internal clock is possible. The devices come preset to 12MHz clock frequency by OTP programming. +#define TMC2209_FCLKTRIM_SHIFT 0 // min.: 0, max.: 31, default: 0 +#define TMC2209_OTTRIM_MASK 0x30 // FACTORY_CONF // OTTRIM (Default: OTP) %00: OT=143°C, OTPW=120°C %01: OT=150°C, OTPW=120°C %10: OT=150°C, OTPW=143°C %11: OT=157°C, OTPW=143°C +#define TMC2209_OTTRIM_SHIFT 8 // min.: 0, max.: 3, default: 0 +#define TMC2209_IHOLD_MASK 0x1F // IHOLD_IRUN // IHOLD (Reset default: OTP) Standstill current (0=1/32...31=32/32) In combination with stealthChop mode, setting IHOLD=0 allows to choose freewheeling or coil short circuit (passive braking) for motor stand still. +#define TMC2209_IHOLD_SHIFT 0 // min.: 0, max.: 31, default: 0 +#define TMC2209_IRUN_MASK 0x1F00 // IHOLD_IRUN // IRUN (Reset default=31) Motor run current (0=1/32...31=32/32) Hint: Choose sense resistors in a way, that normal IRUN is 16 to 31 for best microstep performance. +#define TMC2209_IRUN_SHIFT 8 // min.: 0, max.: 31, default: 0 +#define TMC2209_IHOLDDELAY_MASK 0x0F0000 // IHOLD_IRUN // IHOLDDELAY (Reset default: OTP) Controls the number of clock cycles for motor power down after standstill is detected (stst=1) and TPOWERDOWN has expired. The smooth transition avoids a motor jerk upon power down. 0: instant power down 1..15: Delay per current reduction step in multiple of 2^18 clocks +#define TMC2209_IHOLDDELAY_SHIFT 16 // min.: 0, max.: 15, default: 0 +#define TMC2209_TPOWERDOWN_MASK 0xFF // TPOWERDOWN // (Reset default=20) Sets the delay time from stand still (stst) detection to motor current power down. Time range is about 0 to 5.6 seconds. 0...((2^8)-1) * 2^18 tclk Attention: A minimum setting of 2 is required to allow automatic tuning of stealthChop PWM_OFFS_AUTO. +#define TMC2209_TPOWERDOWN_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_TSTEP_MASK 0x0FFFFF // TSTEP // Actual measured time between two 1/256 microsteps derived from the step input frequency in units of 1/fCLK. Measured value is (2^20)-1 in case of overflow or stand still. The TSTEP related threshold uses a hysteresis of 1/16 of the compare value to compensate for jitter in the clock or the step frequency: (Txxx*15/16)-1 is the lower compare value for each TSTEP based comparison. This means, that the lower switching velocity equals the calculated setting, but the upper switching velocity is higher as defined by the hysteresis setting. +#define TMC2209_TSTEP_SHIFT 0 // min.: 0, max.: 1048575, default: 0 +#define TMC2209_TPWMTHRS_MASK 0x0FFFFF // TPWMTHRS // Sets the upper velocity for stealthChop voltage PWM mode. For TSTEP = TPWMTHRS, stealthChop PWM mode is enabled, if configured. When the velocity exceeds the limit set by TPWMTHRS, the driver switches to spreadCycle. 0 = Disabled +#define TMC2209_TPWMTHRS_SHIFT 0 // min.: 0, max.: 1048575, default: 0 +#define TMC2209_VACTUAL_MASK 0xFFFFFF // VACTUAL // VACTUAL allows moving the motor by UART control. It gives the motor velocity in +-(2^23)-1 [µsteps / t] 0: Normal operation. Driver reacts to STEP input. /=0: Motor moves with the velocity given by VACTUAL. Step pulses can be monitored via INDEX output. The motor direction is controlled by the sign of VACTUAL. +#define TMC2209_VACTUAL_SHIFT 0 // min.: -8388608, max.: 8388607, default: 0 +#define TMC2209_SEMIN_MASK 0x0000000F +#define TMC2209_SEMIN_SHIFT 0 +#define TMC2209_SEUP_MASK 0x00000060 +#define TMC2209_SEUP_SHIFT 5 +#define TMC2209_SEMAX_MASK 0x00000F00 +#define TMC2209_SEMAX_SHIFT 8 +#define TMC2209_SEDN_MASK 0x00006000 +#define TMC2209_SEDN_SHIFT 13 +#define TMC2209_SEIMIN_MASK 0x00008000 +#define TMC2209_SEIMIN_SHIFT 15 +#define TMC2209_MSCNT_MASK 0x03FF // MSCNT // Microstep counter. Indicates actual position in the microstep table for CUR_A. CUR_B uses an offset of 256 into the table. Reading out MSCNT allows determination of the motor position within the electrical wave. +#define TMC2209_MSCNT_SHIFT 0 // min.: 0, max.: 1023, default: 0 +#define TMC2209_CUR_A_MASK 0x01FF // MSCURACT // (signed) Actual microstep current for motor phase A as read from the internal sine wave table (not scaled by current setting) +#define TMC2209_CUR_A_SHIFT 0 // min.: -255, max.: 255, default: 0 +#define TMC2209_CUR_B_MASK 0x01FF0000 // MSCURACT // (signed) Actual microstep current for motor phase B as read from the internal sine wave table (not scaled by current setting) +#define TMC2209_CUR_B_SHIFT 16 // min.: -255, max.: 255, default: 0 +#define TMC2209_TOFF_MASK 0x0F // CHOPCONF // chopper off time and driver enable, Off time setting controls duration of slow decay phase (Nclk = 12 + 32*Toff), %0000: Driver disable, all bridges off %0001: 1 - use only with TBL = 2 %0010 ... %1111: 2 - 15 (Default: OTP, resp. 3 in stealthChop mode) +#define TMC2209_TOFF_SHIFT 0 // min.: 0, max.: 7, default: 0 +#define TMC2209_HSTRT_MASK 0x70 // CHOPCONF // hysteresis start value added to HEND, %000 - %111: Add 1, 2, ..., 8 to hysteresis low value HEND (1/512 of this setting adds to current setting) Attention: Effective HEND+HSTRT <= 16. Hint: Hysteresis decrement is done each 16 clocks. (Default: OTP, resp. 0 in stealthChop mode) +#define TMC2209_HSTRT_SHIFT 4 // min.: 0, max.: 7, default: 0 +#define TMC2209_HEND_MASK 0x0780 // CHOPCONF // hysteresis low value OFFSET sine wave offset, %0000 - %1111: Hysteresis is -3, -2, -1, 0, 1, ..., 12 (1/512 of this setting adds to current setting) This is the hysteresis value which becomes used for the hysteresis chopper. (Default: OTP, resp. 5 in stealthChop mode) +#define TMC2209_HEND_SHIFT 7 // min.: 0, max.: 255, default: 0 +#define TMC2209_TBL_MASK 0x018000 // CHOPCONF // blank time select, %00 - %11: Set comparator blank time to 16, 24, 32 or 40 clocks Hint: %00 or %01 is recommended for most applications (Default: OTP) +#define TMC2209_TBL_SHIFT 15 // min.: 0, max.: 255, default: 0 +#define TMC2209_VSENSE_MASK 0x020000 // CHOPCONF // sense resistor voltage based current scaling +#define TMC2209_VSENSE_SHIFT 17 // min.: 0, max.: 1, default: 0 +#define TMC2209_MRES_MASK 0x0F000000 // CHOPCONF // MRES micro step resolution, %0000: Native 256 microstep setting. %0001 - %1000: 128, 64, 32, 16, 8, 4, 2, FULLSTEP: Reduced microstep resolution. The resolution gives the number of microstep entries per sine quarter wave. When choosing a lower microstep resolution, the driver automatically uses microstep positions which result in a symmetrical wave. Number of microsteps per step pulse = 2^MRES (Selection by pins unless disabled by GCONF. mstep_reg_select) +#define TMC2209_MRES_SHIFT 24 // min.: 0, max.: 255, default: 0 +#define TMC2209_INTPOL_MASK 0x10000000 // CHOPCONF // interpolation to 256 microsteps +#define TMC2209_INTPOL_SHIFT 28 // min.: 0, max.: 1, default: 0 +#define TMC2209_DEDGE_MASK 0x20000000 // CHOPCONF // enable double edge step pulses +#define TMC2209_DEDGE_SHIFT 29 // min.: 0, max.: 1, default: 0 +#define TMC2209_DISS2G_MASK 0x40000000 // CHOPCONF // short to GND protection disable +#define TMC2209_DISS2G_SHIFT 30 // min.: 0, max.: 1, default: 0 +#define TMC2209_DISS2VS_MASK 0x80000000 // CHOPCONF // Low side short protection disable +#define TMC2209_DISS2VS_SHIFT 31 // min.: 0, max.: 1, default: 0 +#define TMC2209_OTPW_MASK 0x01 // DRV_STATUS // overtemperature prewarning flag +#define TMC2209_OTPW_SHIFT 0 // min.: 0, max.: 1, default: 0 +#define TMC2209_OT_MASK 0x02 // DRV_STATUS // overtemperature flag +#define TMC2209_OT_SHIFT 1 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2GA_MASK 0x04 // DRV_STATUS // short to ground indicator phase A +#define TMC2209_S2GA_SHIFT 2 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2GB_MASK 0x08 // DRV_STATUS // short to ground indicator phase B +#define TMC2209_S2GB_SHIFT 3 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2VSA_MASK 0x10 // DRV_STATUS // low side short indicator phase A +#define TMC2209_S2VSA_SHIFT 4 // min.: 0, max.: 1, default: 0 +#define TMC2209_S2VSB_MASK 0x20 // DRV_STATUS // low side short indicator phase B +#define TMC2209_S2VSB_SHIFT 5 // min.: 0, max.: 1, default: 0 +#define TMC2209_OLA_MASK 0x40 // DRV_STATUS // open load indicator phase A +#define TMC2209_OLA_SHIFT 6 // min.: 0, max.: 1, default: 0 +#define TMC2209_OLB_MASK 0x80 // DRV_STATUS // open load indicator phase B +#define TMC2209_OLB_SHIFT 7 // min.: 0, max.: 1, default: 0 +#define TMC2209_T120_MASK 0x0100 // DRV_STATUS // 120°C comparator +#define TMC2209_T120_SHIFT 8 // min.: 0, max.: 1, default: 0 +#define TMC2209_T143_MASK 0x0200 // DRV_STATUS // 143°C comparator +#define TMC2209_T143_SHIFT 9 // min.: 0, max.: 1, default: 0 +#define TMC2209_T150_MASK 0x0400 // DRV_STATUS // 150°C comparator +#define TMC2209_T150_SHIFT 10 // min.: 0, max.: 1, default: 0 +#define TMC2209_T157_MASK 0x0800 // DRV_STATUS // 157°C comparator +#define TMC2209_T157_SHIFT 11 // min.: 0, max.: 1, default: 0 +#define TMC2209_CS_ACTUAL_MASK 0x1F0000 // DRV_STATUS // actual motor current +#define TMC2209_CS_ACTUAL_SHIFT 16 // min.: 0, max.: 31, default: 0 +#define TMC2209_STEALTH_MASK 0x40000000 // DRV_STATUS // stealthChop indicator +#define TMC2209_STEALTH_SHIFT 30 // min.: 0, max.: 1, default: 0 +#define TMC2209_STST_MASK 0x80000000 // DRV_STATUS // standstill indicator +#define TMC2209_STST_SHIFT 31 // min.: 0, max.: 1, default: 0 +#define TMC2209_PWM_OFS_MASK 0xFF // PWMCONF // User defined PWM amplitude offset (0-255) related to full motor current (CS_ACTUAL=31) in stand still. (Reset default=36) When using automatic scaling (pwm_autoscale=1) the value is used for initialization, only. The autoscale function starts with PWM_SCALE_AUTO=PWM_OFS and finds the required offset to yield the target current automatically. PWM_OFS = 0 will disable scaling down motor current below a motor specific lower measurement threshold. This setting should only be used under certain conditions, i.e. when the power supply voltage can vary up and down by a factor of two or more. It prevents the motor going out of regulation, but it also prevents power down below the regulation limit. PWM_OFS > 0 allows automatic scaling to low PWM duty cycles even below the lower regulation threshold. This allows low (standstill) current settings based on the actual (hold) current scale (register IHOLD_IRUN). +#define TMC2209_PWM_OFS_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_GRAD_MASK 0xFF00 // PWMCONF // Velocity dependent gradient for PWM amplitude: PWM_GRAD * 256 / TSTEP This value is added to PWM_AMPL to compensate for the velocity-dependent motor back-EMF. With automatic scaling (pwm_autoscale=1) the value is used for first initialization, only. Set PWM_GRAD to the application specific value (it can be read out from PWM_GRAD_AUTO) to speed up the automatic tuning process. An approximate value can be stored to OTP by programming OTP_PWM_GRAD. +#define TMC2209_PWM_GRAD_SHIFT 8 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_FREQ_MASK 0x030000 // PWMCONF // %00: fPWM=2/1024 fCLK %01: fPWM=2/683 fCLK %10: fPWM=2/512 fCLK %11: fPWM=2/410 fCLK +#define TMC2209_PWM_FREQ_SHIFT 16 // min.: 0, max.: 3, default: 0 +#define TMC2209_PWM_AUTOSCALE_MASK 0x040000 // PWMCONF // +#define TMC2209_PWM_AUTOSCALE_SHIFT 18 // min.: 0, max.: 1, default: 0 +#define TMC2209_PWM_AUTOGRAD_MASK 0x080000 // PWMCONF // +#define TMC2209_PWM_AUTOGRAD_SHIFT 19 // min.: 0, max.: 1, default: 0 +#define TMC2209_FREEWHEEL_MASK 0x300000 // PWMCONF // Stand still option when motor current setting is zero (I_HOLD=0). %00: Normal operation %01: Freewheeling %10: Coil shorted using LS drivers %11: Coil shorted using HS drivers +#define TMC2209_FREEWHEEL_SHIFT 20 // min.: 0, max.: 3, default: 0 +#define TMC2209_PWM_REG_MASK 0x0F000000 // PWMCONF // User defined maximum PWM amplitude change per half wave when using pwm_autoscale=1. (1...15): 1: 0.5 increments (slowest regulation) 2: 1 increment (default with OTP2.1=1) 3: 1.5 increments 4: 2 increments ... 8: 4 increments (default with OTP2.1=0) ... 15: 7.5 increments (fastest regulation) +#define TMC2209_PWM_REG_SHIFT 24 // min.: 0, max.: 25, default: 0 +#define TMC2209_PWM_LIM_MASK 0xF0000000 // PWMCONF // Limit for PWM_SCALE_AUTO when switching back from spreadCycle to stealthChop. This value defines the upper limit for bits 7 to 4 of the automatic current control when switching back. It can be set to reduce the current jerk during mode change back to stealthChop. It does not limit PWM_GRAD or PWM_GRAD_AUTO offset. (Default = 12) +#define TMC2209_PWM_LIM_SHIFT 28 // min.: 0, max.: 15, default: 0 +#define TMC2209_PWM_SCALE_SUM_MASK 0xFF // PWM_SCALE // Actual PWM duty cycle. This value is used for scaling the values CUR_A and CUR_B read from the sine wave table. +#define TMC2209_PWM_SCALE_SUM_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_SCALE_AUTO_MASK 0x01FF0000 // PWM_SCALE // 9 Bit signed offset added to the calculated PWM duty cycle. This is the result of the automatic amplitude regulation based on current measurement. +#define TMC2209_PWM_SCALE_AUTO_SHIFT 16 // min.: -255, max.: 255, default: 0 +#define TMC2209_PWM_OFS_AUTO_MASK 0xFF // PWM_AUTO // Automatically determined offset value +#define TMC2209_PWM_OFS_AUTO_SHIFT 0 // min.: 0, max.: 255, default: 0 +#define TMC2209_PWM_GRAD_AUTO_MASK 0xFF0000 // PWM_AUTO // Automatically determined gradient value +#define TMC2209_PWM_GRAD_AUTO_SHIFT 16 // min.: 0, max.: 255, default: 0 + +#endif /* TMC2209_FIELDS_H */ diff --git a/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h new file mode 100644 index 0000000..427a3a5 --- /dev/null +++ b/TMC2209/lib/tmc/ic/TMC2209/TMC2209_Register.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC2209_REGISTER_H +#define TMC2209_REGISTER_H + +// ===== TMC2209 & 2202 & TMC2209 & 2220 & 2225 "Donkey Kong" family register set ===== + +#define TMC2209_GCONF 0x00 +#define TMC2209_GSTAT 0x01 +#define TMC2209_IFCNT 0x02 +#define TMC2209_SLAVECONF 0x03 +#define TMC2209_OTP_PROG 0x04 +#define TMC2209_OTP_READ 0x05 +#define TMC2209_IOIN 0x06 +#define TMC2209_FACTORY_CONF 0x07 + +#define TMC2209_IHOLD_IRUN 0x10 +#define TMC2209_TPOWERDOWN 0x11 +#define TMC2209_TSTEP 0x12 +#define TMC2209_TPWMTHRS 0x13 +#define TMC2209_TCOOLTHRS 0x14 + +#define TMC2209_VACTUAL 0x22 + +#define TMC2209_SGTHRS 0x40 +#define TMC2209_SG_RESULT 0x41 +#define TMC2209_COOLCONF 0x42 + +#define TMC2209_MSCNT 0x6A +#define TMC2209_MSCURACT 0x6B +#define TMC2209_CHOPCONF 0x6C +#define TMC2209_DRVSTATUS 0x6F +#define TMC2209_PWMCONF 0x70 +#define TMC2209_PWMSCALE 0x71 +#define TMC2209_PWM_AUTO 0x72 + +#endif /* TMC2209_Register */ diff --git a/TMC2209/lib/tmc/ramp/LinearRamp.c b/TMC2209/lib/tmc/ramp/LinearRamp.c new file mode 100644 index 0000000..24eb0c4 --- /dev/null +++ b/TMC2209/lib/tmc/ramp/LinearRamp.c @@ -0,0 +1,165 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * This is a basic proof-of-concept implementation of a linear motion ramp + * generator. It is designed to run with 1 calculation / ms. + * + * + */ +#include "LinearRamp.h" + +void tmc_linearRamp_init(TMC_LinearRamp *linearRamp) +{ + linearRamp->maxVelocity = 0; + linearRamp->targetPosition = 0; + linearRamp->targetVelocity = 0; + linearRamp->rampVelocity = 0; + linearRamp->acceleration = 0; + linearRamp->encoderSteps = u16_MAX; + linearRamp->lastdVRest = 0; + linearRamp->lastdXRest = 0; + linearRamp->rampEnabled = false; +} + +void tmc_linearRamp_computeRampVelocity(TMC_LinearRamp *linearRamp) +{ + if (linearRamp->rampEnabled) + { + // update target velocity according actual set acceleration + // (scaling pre-factor of 1000 used for 1ms velocity ramp handling) + + int32_t dV = linearRamp->acceleration; + + // to ensure that small velocity changes at high set acceleration are also possible + int32_t maxDTV = abs(linearRamp->targetVelocity - linearRamp->rampVelocity); + if (maxDTV < (dV/1000)) + dV = maxDTV*1000; + + dV += linearRamp->lastdVRest; + linearRamp->lastdVRest = dV % 1000; + + if (linearRamp->rampVelocity < linearRamp->targetVelocity) + { + // accelerate motor + linearRamp->rampVelocity += dV/1000; // divide with pre-factor + } + else if (linearRamp->rampVelocity > linearRamp->targetVelocity) + { + // decelerate motor + linearRamp->rampVelocity -= dV/1000; // divide with pre-factor + } + } + else + { + // use target velocity directly + linearRamp->rampVelocity = linearRamp->targetVelocity; + } + + // limit ramp velocity + linearRamp->rampVelocity = tmc_limitInt(linearRamp->rampVelocity, -linearRamp->maxVelocity, linearRamp->maxVelocity); +} + +void tmc_linearRamp_computeRampPosition(TMC_LinearRamp *linearRamp) +{ + if (linearRamp->rampEnabled) + { + // update target position according actual set acceleration and max velocity + // (scaling pre-factor of 1000 used for 1ms position ramp handling) + + // limit position difference for further computations + int32_t targetPositionsDifference = linearRamp->targetPosition-linearRamp->rampPosition; + + // limit the sqrti value in case of high position differences + int64_t sqrtiValue = tmc_limitS64(((int64_t)120 * (int64_t)linearRamp->acceleration * (int64_t)(abs(targetPositionsDifference))) / (int64_t)linearRamp->encoderSteps, 0, (int64_t)linearRamp->maxVelocity*(int64_t)linearRamp->maxVelocity); + + // compute max allowed ramp velocity to ramp down to target + int32_t maxRampStop = tmc_sqrti(sqrtiValue); + + // compute max allowed ramp velocity + int32_t maxRampTargetVelocity = 0; + if (targetPositionsDifference > 0) + { + maxRampTargetVelocity = tmc_limitInt(maxRampStop, 0, (int32_t)linearRamp->maxVelocity); + } + else if (targetPositionsDifference < 0) + { + maxRampTargetVelocity = tmc_limitInt(-maxRampStop, -(int32_t)linearRamp->maxVelocity, 0); + } + else + { + //maxRampTargetVelocity = 0; + } + + int32_t dV = linearRamp->acceleration; // pre-factor ~ 1/1000 + + // to ensure that small velocity changes at high set acceleration are also possible + int32_t maxDTV = abs(maxRampTargetVelocity - linearRamp->rampVelocity); + if (maxDTV < (dV / 1000)) + dV = maxDTV * 1000; + + dV += linearRamp->lastdVRest; + linearRamp->lastdVRest = dV % 1000; + + // do velocity ramping + if (maxRampTargetVelocity > linearRamp->rampVelocity) + { + linearRamp->rampVelocity += dV / 1000; + } + else if (maxRampTargetVelocity < linearRamp->rampVelocity) + { + linearRamp->rampVelocity -= dV / 1000; + } + + // limit positionRampTargetVelocity to maxRampTargetVelocity + //linearRamp->rampVelocity = tmc_limitInt(linearRamp->rampVelocity, -abs(maxRampTargetVelocity), abs(maxRampTargetVelocity)); + + // do position ramping using actual ramp velocity to update dX + int64_t dX = ((int64_t)linearRamp->rampVelocity * (int64_t)linearRamp->encoderSteps) / ((int64_t)60) + linearRamp->lastdXRest; + + // scale actual target position + int64_t tempActualTargetPosition = (int64_t)linearRamp->rampPosition * 1000; + + // reset helper variables if ramp position reached target position + if (abs(linearRamp->targetPosition - linearRamp->rampPosition) <= 10) /*abs(dX)*/ + { + // sync ramp position with target position on small deviations + linearRamp->rampPosition = linearRamp->targetPosition; + + // update actual target position + tempActualTargetPosition = (int64_t)linearRamp->rampPosition * 1000; + + dX = 0; + linearRamp->lastdXRest = 0; + linearRamp->rampVelocity = 0; + } + else + { + // update actual target position + tempActualTargetPosition += dX; + } + + int64_t absTempActualTargetPosition = (tempActualTargetPosition >= 0) ? tempActualTargetPosition : -tempActualTargetPosition; + + if (tempActualTargetPosition >= 0) + linearRamp->lastdXRest = (absTempActualTargetPosition % 1000); + else if (tempActualTargetPosition < 0) + linearRamp->lastdXRest = -(absTempActualTargetPosition % 1000); + + // scale actual target position back + linearRamp->rampPosition = tempActualTargetPosition / 1000; + } + else + { + // use target position directly + linearRamp->rampPosition = linearRamp->targetPosition; + + // hold ramp velocity in reset + linearRamp->rampVelocity = 0; + } +} diff --git a/TMC2209/lib/tmc/ramp/LinearRamp.h b/TMC2209/lib/tmc/ramp/LinearRamp.h new file mode 100644 index 0000000..928ab44 --- /dev/null +++ b/TMC2209/lib/tmc/ramp/LinearRamp.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_LINEAR_RAMP_H_ +#define TMC_LINEAR_RAMP_H_ + + #include "tmc/helpers/API_Header.h" + #include "tmc/helpers/Functions.h" + + typedef struct + { + uint32_t maxVelocity; + int32_t targetPosition; + int32_t rampPosition; + int32_t targetVelocity; + int32_t rampVelocity; + int32_t acceleration; + uint16_t encoderSteps; + int32_t lastdVRest; + int32_t lastdXRest; + uint8_t rampEnabled; + } TMC_LinearRamp; + + void tmc_linearRamp_init(TMC_LinearRamp *linearRamp); + void tmc_linearRamp_computeRampVelocity(TMC_LinearRamp *linearRamp); + void tmc_linearRamp_computeRampPosition(TMC_LinearRamp *linearRamp); + +#endif /* TMC_LINEAR_RAMP_H_ */ diff --git a/TMC2209/lib/tmc/ramp/LinearRamp1.c b/TMC2209/lib/tmc/ramp/LinearRamp1.c new file mode 100644 index 0000000..0f4c41f --- /dev/null +++ b/TMC2209/lib/tmc/ramp/LinearRamp1.c @@ -0,0 +1,303 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "LinearRamp1.h" +#include "tmc/helpers/Functions.h" + +void tmc_ramp_linear_init(TMC_LinearRamp *linearRamp) +{ + linearRamp->maxVelocity = 0; + linearRamp->targetPosition = 0; + linearRamp->targetVelocity = 0; + linearRamp->rampVelocity = 0; + linearRamp->rampPosition = 0; + linearRamp->acceleration = 0; + linearRamp->rampEnabled = true; + linearRamp->accumulatorVelocity = 0; + linearRamp->accumulatorPosition = 0; + linearRamp->rampMode = TMC_RAMP_LINEAR_MODE_VELOCITY; + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + linearRamp->precision = TMC_RAMP_LINEAR_DEFAULT_PRECISION; + linearRamp->homingDistance = TMC_RAMP_LINEAR_DEFAULT_HOMING_DISTANCE; + linearRamp->stopVelocity = TMC_RAMP_LINEAR_DEFAULT_STOP_VELOCITY; +} + +void tmc_ramp_linear_set_enabled(TMC_LinearRamp *linearRamp, bool enabled) +{ + linearRamp->rampEnabled = enabled; +} + +void tmc_ramp_linear_set_maxVelocity(TMC_LinearRamp *linearRamp, uint32_t maxVelocity) +{ + linearRamp->maxVelocity = maxVelocity; +} + +void tmc_ramp_linear_set_targetPosition(TMC_LinearRamp *linearRamp, int32_t targetPosition) +{ + linearRamp->targetPosition = targetPosition; +} + +void tmc_ramp_linear_set_rampPosition(TMC_LinearRamp *linearRamp, int32_t rampPosition) +{ + linearRamp->rampPosition = rampPosition; +} + +void tmc_ramp_linear_set_targetVelocity(TMC_LinearRamp *linearRamp, int32_t targetVelocity) +{ + linearRamp->targetVelocity = targetVelocity; +} + +void tmc_ramp_linear_set_rampVelocity(TMC_LinearRamp *linearRamp, int32_t rampVelocity) +{ + linearRamp->rampVelocity = rampVelocity; +} + +void tmc_ramp_linear_set_acceleration(TMC_LinearRamp *linearRamp, int32_t acceleration) +{ + linearRamp->acceleration = acceleration; +} + +void tmc_ramp_linear_set_mode(TMC_LinearRamp *linearRamp, TMC_LinearRamp_Mode mode) +{ + linearRamp->rampMode = mode; +} + +void tmc_ramp_linear_set_precision(TMC_LinearRamp * linearRamp, uint32_t precision) +{ + linearRamp->precision = precision; +} + +void tmc_ramp_linear_set_homingDistance(TMC_LinearRamp *linearRamp, uint32_t homingDistance) +{ + linearRamp->homingDistance = homingDistance; +} + +void tmc_ramp_linear_set_stopVelocity(TMC_LinearRamp *linearRamp, uint32_t stopVelocity) +{ + linearRamp->stopVelocity = stopVelocity; +} + +bool tmc_ramp_linear_get_enabled(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampEnabled; +} + +uint32_t tmc_ramp_linear_get_maxVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->maxVelocity; +} + +int32_t tmc_ramp_linear_get_targetPosition(TMC_LinearRamp *linearRamp) +{ + return linearRamp->targetPosition; +} + +int32_t tmc_ramp_linear_get_rampPosition(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampPosition; +} + +int32_t tmc_ramp_linear_get_targetVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->targetVelocity; +} + +int32_t tmc_ramp_linear_get_rampVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampVelocity; +} + +int32_t tmc_ramp_linear_get_acceleration(TMC_LinearRamp *linearRamp) +{ + return linearRamp->acceleration; +} + +TMC_LinearRamp_State tmc_ramp_linear_get_state(TMC_LinearRamp *linearRamp) +{ + return linearRamp->state; +} + +TMC_LinearRamp_Mode tmc_ramp_linear_get_mode(TMC_LinearRamp *linearRamp) +{ + return linearRamp->rampMode; +} + +uint32_t tmc_ramp_linear_get_precision(TMC_LinearRamp *linearRamp) +{ + return linearRamp->precision; +} + +// The maximum acceleration depends on the precision value +uint32_t tmc_ramp_linear_get_acceleration_limit(TMC_LinearRamp *linearRamp) +{ + return (0xFFFFFFFFu / linearRamp->precision) * linearRamp->precision; +} + +uint32_t tmc_ramp_linear_get_velocity_limit(TMC_LinearRamp *linearRamp) +{ + return linearRamp->precision; +} + +uint32_t tmc_ramp_linear_get_homingDistance(TMC_LinearRamp *linearRamp) +{ + return linearRamp->homingDistance; +} + +uint32_t tmc_ramp_linear_get_stopVelocity(TMC_LinearRamp *linearRamp) +{ + return linearRamp->stopVelocity; +} + +int32_t tmc_ramp_linear_compute(TMC_LinearRamp *linearRamp) +{ + tmc_ramp_linear_compute_position(linearRamp); + return tmc_ramp_linear_compute_velocity(linearRamp); +} + +int32_t tmc_ramp_linear_compute_velocity(TMC_LinearRamp *linearRamp) +{ + bool accelerating = linearRamp->rampVelocity != linearRamp->targetVelocity; + + if (linearRamp->rampEnabled) + { + // Add current acceleration to accumulator + linearRamp->accumulatorVelocity += linearRamp->acceleration; + + // Calculate the velocity delta value and keep the remainder of the velocity accumulator + int32_t dv = linearRamp->accumulatorVelocity / linearRamp->precision; + linearRamp->accumulatorVelocity = linearRamp->accumulatorVelocity % linearRamp->precision; + + // Add dv to rampVelocity, and regulate to target velocity + if(linearRamp->rampVelocity < linearRamp->targetVelocity) + linearRamp->rampVelocity = MIN(linearRamp->rampVelocity + dv, linearRamp->targetVelocity); + else if(linearRamp->rampVelocity > linearRamp->targetVelocity) + linearRamp->rampVelocity = MAX(linearRamp->rampVelocity - dv, linearRamp->targetVelocity); + } + else + { + // use target velocity directly + linearRamp->rampVelocity = linearRamp->targetVelocity; + // Reset accumulator + linearRamp->accumulatorVelocity = 0; + } + + // Calculate the velocity delta value and keep the remainder of the position accumulator + linearRamp->accumulatorPosition += linearRamp->rampVelocity; + int32_t dx = linearRamp->accumulatorPosition / (int32_t) linearRamp->precision; + linearRamp->accumulatorPosition = linearRamp->accumulatorPosition % (int32_t) linearRamp->precision; + + if(dx == 0) + return dx; + + // Change actual position determined by position change + linearRamp->rampPosition += (dx < 0) ? (-1) : (1); + + // Count acceleration steps needed for decelerating later + linearRamp->accelerationSteps += (abs(linearRamp->rampVelocity) < abs(linearRamp->targetVelocity)) ? accelerating : -accelerating; + if (linearRamp->accelerationSteps < 0) + linearRamp->accelerationSteps = 0; + + return dx; +} + +void tmc_ramp_linear_compute_position(TMC_LinearRamp *linearRamp) +{ + if (!linearRamp->rampEnabled) + return; + + if (linearRamp->rampMode != TMC_RAMP_LINEAR_MODE_POSITION) + return; + + // Calculate steps needed to target + int32_t diffx = 0; + + switch(linearRamp->state) { + case TMC_RAMP_LINEAR_STATE_IDLE: + if(linearRamp->rampVelocity == 0) + linearRamp->accelerationSteps = 0; + + if(linearRamp->rampPosition == linearRamp->targetPosition) + break; + + linearRamp->state = TMC_RAMP_LINEAR_STATE_DRIVING; + break; + case TMC_RAMP_LINEAR_STATE_DRIVING: + // Calculate distance to target (positive = driving towards target) + if(linearRamp->rampVelocity > 0) + diffx = linearRamp->targetPosition - linearRamp->rampPosition; + else if(linearRamp->rampVelocity < 0) + diffx = -(linearRamp->targetPosition - linearRamp->rampPosition); + else + diffx = abs(linearRamp->targetPosition - linearRamp->rampPosition); + + // Steps left required for braking? + // (+ 1 to compensate rounding (flooring) errors of the position accumulator) + if(linearRamp->accelerationSteps + 1 >= diffx) + { + linearRamp->targetVelocity = 0; + linearRamp->state = TMC_RAMP_LINEAR_STATE_BRAKING; + } + else + { // Driving - apply VMAX (this also allows mid-ramp VMAX changes) + linearRamp->targetVelocity = (linearRamp->targetPosition > linearRamp->rampPosition) ? linearRamp->maxVelocity : -linearRamp->maxVelocity; + } + break; + case TMC_RAMP_LINEAR_STATE_BRAKING: + if(linearRamp->targetPosition == linearRamp->rampPosition) + { + if(abs(linearRamp->rampVelocity) <= linearRamp->stopVelocity) + { // Position reached, velocity within cutoff threshold (or zero) + linearRamp->rampVelocity = 0; + linearRamp->targetVelocity = 0; + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + } + else + { + // We're still too fast, we're going to miss the target position + // Let the deceleration continue until velocity is zero, then either + // home when within homing distance or start a new ramp (RAMP_DRIVING) + // towards the target. + } + } + else + { // We're not at the target position + if(linearRamp->rampVelocity != 0) + { // Still decelerating + + // Calculate distance to target (positive = driving towards target) + if(linearRamp->rampVelocity > 0) + diffx = linearRamp->targetPosition - linearRamp->rampPosition; + else if(linearRamp->rampVelocity < 0) + diffx = -(linearRamp->targetPosition - linearRamp->rampPosition); + else + diffx = abs(linearRamp->targetPosition - linearRamp->rampPosition); + + // Enough space to accelerate again? + // (+ 1 to compensate rounding (flooring) errors of the position accumulator) + if(linearRamp->accelerationSteps + 1 < diffx) + { + linearRamp->state = TMC_RAMP_LINEAR_STATE_DRIVING; + } + } + else + { // Standing still (not at the target position) + if(abs(linearRamp->targetPosition - linearRamp->rampPosition) <= linearRamp->homingDistance) + { // Within homing distance - drive with stop velocity + linearRamp->targetVelocity = (linearRamp->targetPosition > linearRamp->rampPosition)? linearRamp->stopVelocity : -linearRamp->stopVelocity; + } + else + { // Not within homing distance - start a new motion by switching to RAMP_IDLE + // Since (targetPosition != actualPosition) a new ramp will be started. + linearRamp->state = TMC_RAMP_LINEAR_STATE_IDLE; + } + } + } + break; + } +} diff --git a/TMC2209/lib/tmc/ramp/LinearRamp1.h b/TMC2209/lib/tmc/ramp/LinearRamp1.h new file mode 100644 index 0000000..de41e98 --- /dev/null +++ b/TMC2209/lib/tmc/ramp/LinearRamp1.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_RAMP_LINEARRAMP1_H_ +#define TMC_RAMP_LINEARRAMP1_H_ + +#include "tmc/helpers/API_Header.h" +#include "Ramp.h" + +// Default precision of the calculations. Internal calculations use a precision +// of 1/TMC_RAMP_LINEAR_PRECISION for acceleration and velocity. +// When using 2**N as precision, this results in N digits of precision. +#define TMC_RAMP_LINEAR_DEFAULT_PRECISION ((uint32_t)1<<17) + +// Position mode: When hitting the target position a velocity below the V_STOP threshold will be cut off to velocity 0 +#define TMC_RAMP_LINEAR_DEFAULT_HOMING_DISTANCE 5 + +// Position mode: When barely missing the target position by HOMING_DISTANCE or less, the remainder will be driven with V_STOP velocity +#define TMC_RAMP_LINEAR_DEFAULT_STOP_VELOCITY 5 + +typedef enum { + TMC_RAMP_LINEAR_MODE_VELOCITY, + TMC_RAMP_LINEAR_MODE_POSITION +} TMC_LinearRamp_Mode; + +typedef enum { + TMC_RAMP_LINEAR_STATE_IDLE, + TMC_RAMP_LINEAR_STATE_DRIVING, + TMC_RAMP_LINEAR_STATE_BRAKING +} TMC_LinearRamp_State; + +typedef struct +{ + uint32_t maxVelocity; + int32_t targetPosition; + int32_t rampPosition; + int32_t targetVelocity; + int32_t rampVelocity; + int32_t acceleration; + bool rampEnabled; + int32_t accumulatorVelocity; + int32_t accumulatorPosition; + TMC_LinearRamp_Mode rampMode; + TMC_LinearRamp_State state; + int32_t accelerationSteps; + uint32_t precision; + uint32_t homingDistance; + uint32_t stopVelocity; +} TMC_LinearRamp; + +void tmc_ramp_linear_init(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_compute(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_compute_velocity(TMC_LinearRamp *linearRamp); +void tmc_ramp_linear_compute_position(TMC_LinearRamp *linearRamp); + +void tmc_ramp_linear_set_enabled(TMC_LinearRamp *linearRamp, bool enabled); +void tmc_ramp_linear_set_maxVelocity(TMC_LinearRamp *linearRamp, uint32_t maxVelocity); +void tmc_ramp_linear_set_targetPosition(TMC_LinearRamp *linearRamp, int32_t targetPosition); +void tmc_ramp_linear_set_rampPosition(TMC_LinearRamp *linearRamp, int32_t rampPosition); +void tmc_ramp_linear_set_targetVelocity(TMC_LinearRamp *linearRamp, int32_t targetVelocity); +void tmc_ramp_linear_set_rampVelocity(TMC_LinearRamp *linearRamp, int32_t rampVelocity); +void tmc_ramp_linear_set_acceleration(TMC_LinearRamp *linearRamp, int32_t acceleration); +void tmc_ramp_linear_set_mode(TMC_LinearRamp *linearRamp, TMC_LinearRamp_Mode mode); +void tmc_ramp_linear_set_precision(TMC_LinearRamp * linearRamp, uint32_t precision); +void tmc_ramp_linear_set_homingDistance(TMC_LinearRamp *linearRamp, uint32_t homingDistance); +void tmc_ramp_linear_set_stopVelocity(TMC_LinearRamp *linearRamp, uint32_t stopVelocity); + +bool tmc_ramp_linear_get_enabled(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_maxVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_targetPosition(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_rampPosition(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_targetVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_rampVelocity(TMC_LinearRamp *linearRamp); +int32_t tmc_ramp_linear_get_acceleration(TMC_LinearRamp *linearRamp); +TMC_LinearRamp_State tmc_ramp_linear_get_state(TMC_LinearRamp *linearRamp); +TMC_LinearRamp_Mode tmc_ramp_linear_get_mode(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_precision(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_acceleration_limit(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_velocity_limit(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_homingDistance(TMC_LinearRamp *linearRamp); +uint32_t tmc_ramp_linear_get_stopVelocity(TMC_LinearRamp *linearRamp); + +#endif /* TMC_RAMP_LINEARRAMP1_H_ */ diff --git a/TMC2209/lib/tmc/ramp/Ramp.c b/TMC2209/lib/tmc/ramp/Ramp.c new file mode 100644 index 0000000..7fbf726 --- /dev/null +++ b/TMC2209/lib/tmc/ramp/Ramp.c @@ -0,0 +1,91 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "Ramp.h" + +void tmc_ramp_init(void *ramp, TMC_RampType type) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_init((TMC_LinearRamp *)ramp); + break; + } +} + +int32_t tmc_ramp_compute(void *ramp, TMC_RampType type, uint32_t delta) +{ + uint32_t i; + int32_t dxSum = 0; + + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + for (i = 0; i < delta; i++) + { + dxSum += tmc_ramp_linear_compute((TMC_LinearRamp *)ramp); + } + break; + } + + return dxSum; +} + +int32_t tmc_ramp_get_rampVelocity(void *ramp, TMC_RampType type) +{ + int32_t v = 0; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + v = tmc_ramp_linear_get_rampVelocity((TMC_LinearRamp *)ramp); + break; + } + return v; +} + +int32_t tmc_ramp_get_rampPosition(void *ramp, TMC_RampType type) +{ + int32_t x = 0; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + x = tmc_ramp_linear_get_rampPosition((TMC_LinearRamp *)ramp); + break; + } + return x; +} + +bool tmc_ramp_get_enabled(void *ramp, TMC_RampType type) +{ + bool enabled = false; + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + enabled = tmc_ramp_linear_get_enabled((TMC_LinearRamp *)ramp); + break; + } + return enabled; +} + +void tmc_ramp_set_enabled(void *ramp, TMC_RampType type, bool enabled) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_set_enabled((TMC_LinearRamp *)ramp, enabled); + break; + } +} + +void tmc_ramp_toggle_enabled(void *ramp, TMC_RampType type) +{ + switch(type) { + case TMC_RAMP_TYPE_LINEAR: + default: + tmc_ramp_linear_set_enabled((TMC_LinearRamp *)ramp, !tmc_ramp_get_enabled(ramp, type)); + break; + } +} diff --git a/TMC2209/lib/tmc/ramp/Ramp.h b/TMC2209/lib/tmc/ramp/Ramp.h new file mode 100644 index 0000000..e7cc6a0 --- /dev/null +++ b/TMC2209/lib/tmc/ramp/Ramp.h @@ -0,0 +1,40 @@ +/******************************************************************************* +* Copyright © 2018 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_RAMP_RAMP_H_ +#define TMC_RAMP_RAMP_H_ + +#include "LinearRamp1.h" + +typedef enum { + TMC_RAMP_TYPE_LINEAR +} TMC_RampType; + +// Initializes ramp parameters for given type +void tmc_ramp_init(void *ramp, TMC_RampType type); + +// Computes new ramp state after delta ticks have passed +// Note: To call this function periodically with a fixed delta-time, use delta = 1 and +// define the units of acceleration as v/delta-time. If you want to specify a different unit, +// change delta to your preference. +// Returns the position difference of the calculation. +int32_t tmc_ramp_compute(void *ramp, TMC_RampType type, uint32_t delta); + +// Returns the current ramp velocity computed by the given ramp +int32_t tmc_ramp_get_rampVelocity(void *ramp, TMC_RampType type); + +// Returns the current ramp position computed by the given ramp +int32_t tmc_ramp_get_rampPosition(void *ramp, TMC_RampType type); + +// Enable/disable ramps +bool tmc_ramp_get_enabled(void *ramp, TMC_RampType type); +void tmc_ramp_set_enabled(void *ramp, TMC_RampType type, bool enabled); +void tmc_ramp_toggle_enabled(void *ramp, TMC_RampType type); + +#endif /* TMC_RAMP_RAMP_H_ */ diff --git a/TMC2209/lib/tmc/tmc/BLDC.h b/TMC2209/lib/tmc/tmc/BLDC.h new file mode 100644 index 0000000..0b0e942 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/BLDC.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_BLDC_H_ +#define TMC_BLDC_H_ + +#include "tmc/helpers/API_Header.h" +#include "hal/derivative.h" +#include "hal/HAL.h" + +typedef enum { + MEASURE_ONE_PHASE, + MEASURE_THREE_PHASES, +} BLDCMeasurementType; + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW); +void timer_callback(void); + +void BLDC_calibrateADCs(); + +void BLDC_enablePWM(uint8_t enable); +uint8_t BLDC_isPWMenabled(); + +void BLDC_setTargetPWM(int16_t pwm); +int16_t BLDC_getTargetPWM(); + +int32_t BLDC_getMeasuredCurrent(); + +typedef enum { + BLDC_OPENLOOP, + BLDC_HALL, +} BLDCMode; + +void BLDC_setCommutationMode(BLDCMode mode); +BLDCMode BLDC_getCommutationMode(); + +void BLDC_setPolePairs(uint8 polePairs); +uint8_t BLDC_getPolePairs(); + +void BLDC_setOpenloopStepTime(uint16_t stepTime); +uint16_t BLDC_getOpenloopStepTime(); + +int32_t BLDC_getTargetAngle(); +int32_t BLDC_getHallAngle(); + +void BLDC_setTargetOpenloopVelocity(uint32_t velocity); +uint32_t BLDC_getTargetOpenloopVelocity(); +int32_t BLDC_getActualOpenloopVelocity(); +int32_t BLDC_getActualHallVelocity(); + +void BLDC_setHallOrder(uint8_t order); +uint8_t BLDC_getHallOrder(); + +void BLDC_setHallInvert(uint8_t invert); +uint8_t BLDC_getHallInvert(); + +void BLDC_setBBMTime(uint8_t time); +uint8_t BLDC_getBBMTime(); + +#endif /* TMC_BLDC_H_ */ diff --git a/TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c b/TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c new file mode 100644 index 0000000..8eb2f92 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/BLDC_Landungsbruecke.c @@ -0,0 +1,746 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "BLDC.h" +#include "hal/HAL.h" +#include "hal/Timer.h" + +// FTM0_OUTMASK: 0-normal 1-inactive +#define PWM_PHASE_U_ENABLED 0x00 +#define PWM_PHASE_U_DISABLED 0x03 +#define PWM_PHASE_V_ENABLED 0x00 +#define PWM_PHASE_V_DISABLED 0x30 +#define PWM_PHASE_W_ENABLED 0x00 +#define PWM_PHASE_W_DISABLED 0xC0 + +#define VELOCITY_CALC_FREQ 10 // in Hz +#define PWM_FREQ 20000 // in Hz +#define PWM_PERIOD (48000000 / PWM_FREQ) // 48MHz/2*20kHz = 2500 + +typedef enum { + ADC_PHASE_U, + ADC_PHASE_V, + ADC_PHASE_W, +} ADC_Channel; + +uint8_t adcPhases[3] = { 0 }; +uint8_t adcCount = 3; +volatile ADC_Channel adc = ADC_PHASE_U; + +int16_t targetPWM = 0; +uint32_t openloopVelocity = 60; // mechanical RPM +uint16_t openloopStepTime = 0; // Calculate on init +BLDCMode commutationMode = BLDC_OPENLOOP; +uint8_t pwmEnabled = 0; +uint8_t bbmTime = 50; +uint8_t motorPolePairs = 1; + +int32_t targetAngle = 0; +int32_t hallAngle = 0; + +int32_t actualHallVelocity = 0; // electrical RPM + +volatile int32_t adcSamples[8] = { 0 }; +uint8_t adcSampleIndex = 0; + +int32_t adcOffset[3] = { 0 }; +uint32_t sampleCount[3] = { 0 }; + +int32_t currentScalingFactor = 256; // u24q8 format + +#define ADC_SAMPLES 100 + +typedef enum { + HALL_INVALID_0 = 0, + + HALL_001 = 1, + HALL_010 = 2, + HALL_011 = 3, + HALL_100 = 4, + HALL_101 = 5, + HALL_110 = 6, + + HALL_INVALID_1 = 7, +} HallStates; + +static int16_t hallStateToAngle(HallStates hallState); +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2); + +// Hall parameters +uint8_t hallOrder = 0; +uint8_t hallInvert = 0; + +volatile enum { + ADC_INIT, + ADC_READY +} adcState[3] = { ADC_INIT, ADC_INIT, ADC_INIT }; + +typedef struct +{ + IOPinTypeDef *HALL_U; + IOPinTypeDef *HALL_V; + IOPinTypeDef *HALL_W; + IOPinTypeDef *PWM_UL; + IOPinTypeDef *PWM_UH; + IOPinTypeDef *PWM_VL; + IOPinTypeDef *PWM_VH; + IOPinTypeDef *PWM_WL; + IOPinTypeDef *PWM_WH; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2) +{ + uint8_t tmp; + HallStates retVal = HALL_INVALID_0; + + if (hallInvert) + { + // Swap in_1 and in_2 + tmp = in_1; + in_1 = in_2; + in_2 = tmp; + } + + switch(hallOrder) + { + case 0: // U/V/W + retVal = in_0 << 0 + | in_1 << 1 + | in_2 << 2; + break; + case 1: // V/W/U + retVal = in_0 << 1 + | in_1 << 2 + | in_2 << 0; + break; + case 2: // W/U/V + retVal = in_0 << 2 + | in_1 << 0 + | in_2 << 1; + break; + } + + return retVal; +} + +static int16_t hallStateToAngle(HallStates hallState) +{ + switch (hallState) + { + case HALL_001: + return 0; + break; + case HALL_011: + return 60; + break; + case HALL_010: + return 120; + break; + case HALL_110: + return 180; + break; + case HALL_100: + return 240; + break; + case HALL_101: + return 300; + break; + default: + break; + } + + return 0; +} + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW) +{ + if (type == MEASURE_THREE_PHASES) + { + // Three phase measurement + adcCount = 3; + adcPhases[0] = ADC_SC1_ADCH(1); // ADC1_DP1 = AIN0 + adcPhases[1] = ADC_SC1_ADCH(3); // ADC1_DP3 = AIN1 + adcPhases[2] = ADC_SC1_ADCH(0); // ADC1_DP0 = AIN2 + } + else if (type == MEASURE_ONE_PHASE) + { + // One phase measurement + adcCount = 1; + adcPhases[0] = ADC_SC1_ADCH(0); // ADC1_DP0 = AIN2 + } + + Pins.PWM_UL = &HAL.IOs->pins->DIO6; + Pins.PWM_UH = &HAL.IOs->pins->DIO7; + Pins.PWM_VL = &HAL.IOs->pins->DIO8; + Pins.PWM_VH = &HAL.IOs->pins->DIO9; + Pins.PWM_WL = &HAL.IOs->pins->DIO10; + Pins.PWM_WH = &HAL.IOs->pins->DIO11; + + currentScalingFactor = currentScaling; + + Pins.HALL_U = hallU; + Pins.HALL_V = hallV; + Pins.HALL_W = hallW; + + HAL.IOs->config->toInput(Pins.HALL_U); + HAL.IOs->config->toInput(Pins.HALL_V); + HAL.IOs->config->toInput(Pins.HALL_W); + + // Calculate the openloop step time by setting the velocity + BLDC_setTargetOpenloopVelocity(openloopVelocity); + + // --- PDB --- + // Enable clock for programmable delay block (PDB) + SIM_SCGC6 |= SIM_SCGC6_PDB_MASK; + + PDB0_MOD = PWM_PERIOD - 10; + + PDB0_CH1C1 = PDB_C1_TOS(0x01) + | PDB_C1_EN(0x01); + + PDB0_CH1DLY0 = 0; + + PDB0_SC = PDB_SC_LDMOD(3) + | PDB_SC_PDBEN_MASK // enable PDB + | PDB_SC_TRGSEL(0x08) // 0x08 = FTM0 + | PDB_SC_LDOK_MASK + | PDB_SC_PDBEIE_MASK; + + enable_irq(INT_PDB0 - 16); + + // --- ADC --- + // Enable clock for ADC1 + SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK; + + // Input DADP1 + ADC1_SC1A = adcPhases[adc] | ADC_SC1_AIEN_MASK; + + // Single-ended 16 bit conversion, ADCK = Bus Clock/2 + ADC1_CFG1 = ADC_CFG1_MODE(0x03) | ADC_CFG1_ADICLK(1); + + ADC1_CFG2 = ADC_CFG2_ADHSC_MASK; + + // Hardware trigger + ADC1_SC2 = ADC_SC2_ADTRG_MASK; + + ADC1_SC3 = ADC_SC3_CAL_MASK; + while(ADC1_SC3 & ADC_SC3_CAL_MASK); + + // set ADC1 interrupt handler + enable_irq(INT_ADC1-16); + + // --- FTM --- + // Deinitialize the timer, as we're going to take FTM0 over + Timer.deInit(); + + // enable clock for FTM0 + SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; + + // disable write protection + FTM0_MODE |= FTM_MODE_WPDIS_MASK; + + FTM0_CONF |= FTM_CONF_BDMMODE(3); // let counter run in BDM mode + + // FAULTM = 11 - Fault control is enabled for all channels (automatic fault clearing) + // FTMEN = 1 - all registers are available for use with no restrictions + FTM0_MODE |= FTM_MODE_FAULTM_MASK | FTM_MODE_FTMEN_MASK; + + // setting for Center Aligned PWM in Combine Mode + FTM0_MOD = PWM_PERIOD-1; + FTM0_CNTIN = 0x00; + FTM0_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; // set enhanced PWM sync mode + + FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK; // use FTM0_MOD as max loading point + FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK; // use software trigger as pwm synchronization trigger + + // disable all channels outputs + FTM0_OUTMASK = FTM_OUTMASK_CH7OM_MASK | FTM_OUTMASK_CH6OM_MASK | + FTM_OUTMASK_CH5OM_MASK | FTM_OUTMASK_CH4OM_MASK | + FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK; + + // COMBINE = 1 - combine mode set, COMP = 1 - complementary PWM set, + // DTEN = 1 - deadtime enabled, SYNCEN = 1 - PWM update synchronization enabled, + // FAULTEN = 1 - fault control enabled + FTM0_COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DTEN0_MASK + | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_COMBINE0_MASK + | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_DTEN2_MASK + | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_COMBINE2_MASK + | FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_DTEN3_MASK + | FTM_COMBINE_COMP3_MASK | FTM_COMBINE_COMBINE3_MASK + | FTM_COMBINE_FAULTEN0_MASK | FTM_COMBINE_FAULTEN2_MASK | FTM_COMBINE_FAULTEN3_MASK; + + // set dead time prescaler (divisor 1) and dead time + FTM0_DEADTIME = FTM_DEADTIME_DTPS(0) | FTM_DEADTIME_DTVAL(bbmTime); + + /* Initial setting of value registers */ + FTM0_C0V = 0; + FTM0_C1V = 0; + FTM0_C4V = 0; + FTM0_C5V = 0; + FTM0_C6V = 0; + FTM0_C7V = 0; + + // set channel mode to generate positive PWM + FTM0_C0SC |= FTM_CnSC_ELSB_MASK; + FTM0_C1SC |= FTM_CnSC_ELSB_MASK; + FTM0_C4SC |= FTM_CnSC_ELSB_MASK; + FTM0_C5SC |= FTM_CnSC_ELSB_MASK; + FTM0_C6SC |= FTM_CnSC_ELSB_MASK; + FTM0_C7SC |= FTM_CnSC_ELSB_MASK; + + // enable loading of the MOD, CNTIN, and CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; + + // enable the generation of the trigger when the FTM counter is equal to the CNTIN register + FTM0_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK; + FTM0_MODE |= FTM_MODE_INIT_MASK; + + // set system clock as source for FTM0 (CLKS[1:0] = 01) + FTM0_SC |= FTM_SC_CLKS(1); + + // enable all PWM output channels of FTM0 + FTM0_OUTMASK = 0; + + // enable FTM0 interrupt + FTM0_SC |= (uint32_t)(FTM_SC_TOIE_MASK); + + // set FTM0 interrupt handler + Timer.overflow_callback = timer_callback; + enable_irq(INT_FTM0-16); +} + +void BLDC_calibrateADCs() +{ + // Only do the offset compensation if PWM is off + if (targetPWM != 0) + return; + + // Temporarily disable the FTM interrupt to prevent it from overriding + // the adc phase selection + disable_irq(INT_FTM0-16); + + for (uint8_t myadc = 0; myadc < adcCount; myadc++) + { + adc = myadc % 3; + // Select the ADC phase for offset compensation + ADC1_SC1A = (ADC1_SC1A & (~ADC_SC1_ADCH_MASK)) | adcPhases[adc]; + + // Reset the ADC state + adcOffset[adc] = 0; + adcState[adc] = ADC_INIT; + + // Wait until the ADC is initialized again + while (adcState[adc] == ADC_INIT); + } + + enable_irq(INT_FTM0-16); +} + +void PDB0_IRQHandler() +{ + PDB0_CH1S &= ~PDB_S_ERR_MASK; + + // Re-enable the pre-trigger to clear the hardware lock + // Refer to 37.4.1: "PDB pre-trigger and trigger outputs" of the K20P100M100SF2V2RM manual + PDB0_CH1C1 &= ~PDB_C1_EN(1); + PDB0_CH1C1 |= PDB_C1_EN(1); +} + +void ADC1_IRQHandler() +{ + int32_t tmp = ADC1_RA; + static ADC_Channel lastChannel = ADC_PHASE_U; + + switch(adcState[lastChannel]) + { + case ADC_INIT: + if (sampleCount[lastChannel] < ADC_SAMPLES) + { + // Store a calibration sample + adcOffset[lastChannel] += tmp; + + sampleCount[lastChannel]++; + } + else + { + // Finished collection of calibration samples + // Calculate offset + adcOffset[lastChannel] /= ADC_SAMPLES; + + adcState[lastChannel] = ADC_READY; + sampleCount[lastChannel] = 0; + } + break; + case ADC_READY: + adcSamples[adcSampleIndex] = (tmp - adcOffset[lastChannel]) * currentScalingFactor / 65536; + adcSampleIndex = (adcSampleIndex + 1) % ARRAY_SIZE(adcSamples); + + break; + } + + if (lastChannel != adc) + { + // Update the channel + lastChannel = adc; + ADC1_SC1A = (ADC1_SC1A & (~ADC_SC1_ADCH_MASK)) | adcPhases[adc]; + } +} + +void timer_callback(void) +{ + // clear timer overflow flag + //FTM0_SC &= ~FTM_SC_TOF_MASK; + + static int32_t commutationCounter = 0; + static int32_t velocityCounter = 0; + + static int32_t lastHallAngle = 0; + static int32_t hallAngleDiffAccu = 0; + + // Measure the hall sensor + HallStates actualHallState = inputToHallState(HAL.IOs->config->isHigh(Pins.HALL_U), HAL.IOs->config->isHigh(Pins.HALL_V), HAL.IOs->config->isHigh(Pins.HALL_W)); + hallAngle = hallStateToAngle(actualHallState); + + // Calculate the hall angle difference + int32_t hallAngleDiff = (hallAngle - lastHallAngle); // [-300 ; +360) + hallAngleDiff = (hallAngleDiff + 360) % 360; // [ 0 ; +360) + hallAngleDiff = ((hallAngleDiff + 180) % 360) - 180; // [-180 ; +180) + lastHallAngle = hallAngle; + + // Accumulate the hall angle for velocity measurement + hallAngleDiffAccu += hallAngleDiff; + + // Calculate the velocity + if (++velocityCounter >= PWM_FREQ / VELOCITY_CALC_FREQ) + { + actualHallVelocity = hallAngleDiffAccu * 60 * VELOCITY_CALC_FREQ / 360; // electrical rotations per minute + + hallAngleDiffAccu = 0; + velocityCounter = 0; + } + + if (commutationMode == BLDC_OPENLOOP) + { + // open loop mode + if (openloopStepTime) + { + if (++commutationCounter >= openloopStepTime) + { + if (targetPWM > 0) + targetAngle = (targetAngle + 60) % 360; + else if (targetPWM < 0) + targetAngle = (targetAngle - 60 + 360) % 360; + + commutationCounter = 0; + } + } + } + else if (commutationMode == BLDC_HALL) + { + if (targetPWM > 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + targetAngle = ((hallAngle + 30) + 90) % 360; + } + else if (targetPWM < 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + // The +360 are to prevent a negative operand for the modulo. + targetAngle = ((hallAngle + 30) - 90 + 360) % 360; + } + else + { + targetAngle = hallAngle; + } + } + + // update commutation step + int16_t duty = ((int32_t)targetPWM * ((int32_t)PWM_PERIOD-1))/(int32_t)s16_MAX; + + if (duty < 0) + duty = -duty; + + switch (targetAngle % 360) + { + case 0: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | // off + PWM_PHASE_V_ENABLED | // high with pwm + PWM_PHASE_W_ENABLED; // low + + FTM0_C1V = 0; + FTM0_C5V = duty; + FTM0_C7V = 0; + + adc = ADC_PHASE_W; + break; + case 60: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // low + PWM_PHASE_V_ENABLED | // high with pwm + PWM_PHASE_W_DISABLED; // off + + FTM0_C1V = 0; + FTM0_C5V = duty; + FTM0_C7V = 0; + + adc = ADC_PHASE_U; + break; + case 120: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // low + PWM_PHASE_V_DISABLED | // off + PWM_PHASE_W_ENABLED; // high with pwm + + FTM0_C1V = 0; + FTM0_C5V = 0; + FTM0_C7V = duty; + + adc = ADC_PHASE_U; + break; + case 180: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | // off + PWM_PHASE_V_ENABLED | // low + PWM_PHASE_W_ENABLED; // high with pwm + + FTM0_C1V = 0; + FTM0_C5V = 0; + FTM0_C7V = duty; + + adc = ADC_PHASE_V; + break; + case 240: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // high with pwm + PWM_PHASE_V_ENABLED | // low + PWM_PHASE_W_DISABLED; // off + + FTM0_C1V = duty; + FTM0_C5V = 0; + FTM0_C7V = 0; + + adc = ADC_PHASE_V; + break; + case 300: + FTM0_OUTMASK = PWM_PHASE_U_ENABLED | // high with pwm + PWM_PHASE_V_DISABLED | // off + PWM_PHASE_W_ENABLED; // low + + FTM0_C1V = duty; + FTM0_C5V = 0; + FTM0_C7V = 0; + + adc = ADC_PHASE_W; + break; + default: + FTM0_OUTMASK = PWM_PHASE_U_DISABLED | PWM_PHASE_V_DISABLED | PWM_PHASE_W_DISABLED; + break; + } + + // For one-phase measurement always use the same phase + if (adcCount == 1) + { + adc = ADC_PHASE_U; + } + + // Update PDB timing + if (duty < PWM_PERIOD/2) + { + PDB0_CH1DLY0 = duty + (PWM_PERIOD-duty)/2; + } + else + { + PDB0_CH1DLY0 = duty/2; + } + + // Update PDB and FTM registers + PDB0_SC |= PDB_SC_LDOK_MASK; + FTM0_SYNC |= FTM_SYNC_REINIT_MASK; + + // LOAD Enable: enables the loading of the MOD, CNTIN, and + // CV registers with the values of their write buffers + FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; +} + +void BLDC_enablePWM(uint8_t enable) +{ + if (enable) + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_Mode_AF4; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OType_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PuPd_NOPULL; + HAL.IOs->config->set(Pins.PWM_UH); + + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 1; + } + else + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_Mode_IN; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OType_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PuPd_DOWN; + + HAL.IOs->config->set(Pins.PWM_UH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 0; + } +} + +uint8_t BLDC_isPWMenabled() +{ + return pwmEnabled; +} + +void BLDC_setTargetPWM(int16_t pwm) +{ + targetPWM = pwm; +} + +int16_t BLDC_getTargetPWM() +{ + return targetPWM; +} + +int32_t BLDC_getMeasuredCurrent() +{ + int32_t sum = 0; + for (uint8_t i = 0; i < ARRAY_SIZE(adcSamples); i++) + { + sum += adcSamples[i]; + } + + return sum / (int32_t) ARRAY_SIZE(adcSamples); +} + +void BLDC_setCommutationMode(BLDCMode mode) +{ + commutationMode = mode; +} + +BLDCMode BLDC_getCommutationMode() +{ + return commutationMode; +} + +void BLDC_setPolePairs(uint8 polePairs) +{ + if (polePairs == 0) + return; + + motorPolePairs = polePairs; +} + +uint8_t BLDC_getPolePairs() +{ + return motorPolePairs; +} + +void BLDC_setOpenloopStepTime(uint16_t stepTime) +{ + openloopStepTime = stepTime; +} + +uint16_t BLDC_getOpenloopStepTime() +{ + return openloopStepTime; +} + +int32_t BLDC_getTargetAngle() +{ + return targetAngle; +} + +int32_t BLDC_getHallAngle() +{ + return hallAngle; +} + +// Set the open loop velocity in RPM +void BLDC_setTargetOpenloopVelocity(uint32_t velocity) +{ + // 1 [RPM] = polePairs [eRPM] + // [eRPM] = [1/60 eRPS] = 6/60 [steps/s] + // steps/s = fpwm / openloopStepTime + // + // openloopStepTime = fpwm * 60 / 6 / velocity / polePairs + openloopStepTime = PWM_FREQ * 10 / velocity / motorPolePairs; + + // Store the requested velocity for accurate reading + // Otherwise we see rounding errors when reading back. + openloopVelocity = velocity; +} + +uint32_t BLDC_getTargetOpenloopVelocity() +{ + return openloopVelocity; +} + +int32_t BLDC_getActualOpenloopVelocity() +{ + if (commutationMode != BLDC_OPENLOOP) + return 0; + + if (targetPWM > 0) + return openloopVelocity; + else if (targetPWM < 0) + return -openloopVelocity; + else + return 0; +} + +// Velocity measured by hall in RPM +int32_t BLDC_getActualHallVelocity() +{ + return actualHallVelocity / motorPolePairs; +} + +void BLDC_setHallOrder(uint8_t order) +{ + if (order < 3) + { + hallOrder = order; + } +} + +uint8_t BLDC_getHallOrder() +{ + return hallOrder; +} + +void BLDC_setHallInvert(uint8_t invert) +{ + hallInvert = (invert)? 1:0; +} + +uint8_t BLDC_getHallInvert() +{ + return hallInvert; +} + +void BLDC_setBBMTime(uint8_t time) +{ + // Clip to the maximum value instead of overflowing + bbmTime = MIN(time, 63); + + // Set dead time prescaler (divisor 1) and dead time + FTM0_DEADTIME = FTM_DEADTIME_DTPS(0) | FTM_DEADTIME_DTVAL(bbmTime); +} + +uint8_t BLDC_getBBMTime() +{ + return bbmTime; +} diff --git a/TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c b/TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c new file mode 100644 index 0000000..a9933de --- /dev/null +++ b/TMC2209/lib/tmc/tmc/BLDC_LandungsbrueckeV3.c @@ -0,0 +1,760 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "BLDC.h" +#include "hal/HAL.h" +#include "hal/Timer.h" +#include "hal/ADCs.h" + +#define VELOCITY_CALC_FREQ 10 // in Hz +#define PWM_FREQ 20000 // in Hz + + /* Timer0 Frequency: + * + * CK_TIMER0 = 2 x CK_APB2 = 240MHz (APB1PSC/APB2PSC in RCU_CFG0 register is 0b101) + * + * CLK_TIMER 240MHz + * ----------- = ----- = 80MHz + * Prescaler 3 + * + */ +#define PWM_PERIOD (80000000 / PWM_FREQ)-1 + +typedef enum { + PWM_PHASE_U = TIMER_CH_0, + PWM_PHASE_V = TIMER_CH_1, + PWM_PHASE_W = TIMER_CH_2, +} PWM_Phase; + +typedef enum { + ADC_PHASE_U, + ADC_PHASE_V, + ADC_PHASE_W, +} ADC_Channel; + +uint8_t adcPhases[3] = { 0 }; +uint8_t adcCount = 3; +volatile ADC_Channel adc = ADC_PHASE_U; + +int16_t targetPWM = 0; +uint32_t openloopVelocity = 60; // mechanical RPM +uint16_t openloopStepTime = 0; // Calculate on init +BLDCMode commutationMode = BLDC_OPENLOOP; +uint8_t pwmEnabled = 0; +uint8_t bbmTime = 50; +uint8_t motorPolePairs = 1; + +int32_t targetAngle = 0; +int32_t hallAngle = 0; + +int32_t actualHallVelocity = 0; // electrical RPM + +volatile int32_t adcSamples[8] = { 0 }; +uint8_t adcSampleIndex = 0; + +int32_t adcOffset[3] = { 0 }; +uint32_t sampleCount[3] = { 0 }; + +int32_t currentScalingFactor = 256; // u24q8 format + +#define ADC_SAMPLES 100 + +typedef enum { + HALL_INVALID_0 = 0, + + HALL_001 = 1, + HALL_010 = 2, + HALL_011 = 3, + HALL_100 = 4, + HALL_101 = 5, + HALL_110 = 6, + + HALL_INVALID_1 = 7, +} HallStates; + +static int16_t hallStateToAngle(HallStates hallState); +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2); + +// Hall parameters +uint8_t hallOrder = 0; +uint8_t hallInvert = 0; + +volatile enum { + ADC_INIT, + ADC_READY +} adcState[3] = { ADC_INIT, ADC_INIT, ADC_INIT }; + +typedef struct +{ + IOPinTypeDef *HALL_U; + IOPinTypeDef *HALL_V; + IOPinTypeDef *HALL_W; + IOPinTypeDef *PWM_UL; + IOPinTypeDef *PWM_UH; + IOPinTypeDef *PWM_VL; + IOPinTypeDef *PWM_VH; + IOPinTypeDef *PWM_WL; + IOPinTypeDef *PWM_WH; +} PinsTypeDef; + +static PinsTypeDef Pins; + +static HallStates inputToHallState(uint8_t in_0, uint8_t in_1, uint8_t in_2) +{ + uint8_t tmp; + HallStates retVal = HALL_INVALID_0; + + if (hallInvert) + { + // Swap in_1 and in_2 + tmp = in_1; + in_1 = in_2; + in_2 = tmp; + } + + switch(hallOrder) + { + case 0: // U/V/W + retVal = in_0 << 0 + | in_1 << 1 + | in_2 << 2; + break; + case 1: // V/W/U + retVal = in_0 << 1 + | in_1 << 2 + | in_2 << 0; + break; + case 2: // W/U/V + retVal = in_0 << 2 + | in_1 << 0 + | in_2 << 1; + break; + } + + return retVal; +} + +static int16_t hallStateToAngle(HallStates hallState) +{ + switch (hallState) + { + case HALL_001: + return 0; + break; + case HALL_011: + return 60; + break; + case HALL_010: + return 120; + break; + case HALL_110: + return 180; + break; + case HALL_100: + return 240; + break; + case HALL_101: + return 300; + break; + default: + break; + } + + return 0; +} + +void BLDC_init(BLDCMeasurementType type, uint32_t currentScaling, IOPinTypeDef *hallU, IOPinTypeDef *hallV, IOPinTypeDef *hallW) +{ + if (type == MEASURE_THREE_PHASES) + { + // Three phase measurement + adcCount = 3; + adcPhases[0] = ADC_CHANNEL_14; // AIN0 + adcPhases[1] = ADC_CHANNEL_15; // AIN1 + adcPhases[2] = ADC_CHANNEL_8; // AIN2 + } + else if (type == MEASURE_ONE_PHASE) + { + // One phase measurement + adcCount = 1; + adcPhases[0] = ADC_CHANNEL_8; // AIN2 + } + + //Set MUX_1 and MUX_2 to one to connect DIO10 and DIO11 to PWM pins DIO10_A and DIO11_A respectively. +// *HAL.IOs->pins->SW_UART_PWM.setBitRegister = HAL.IOs->pins->SW_UART_PWM.bitWeight; + HAL.IOs->config->toOutput(&HAL.IOs->pins->SW_UART_PWM); + + HAL.IOs->config->setHigh(&HAL.IOs->pins->SW_UART_PWM); + + + Pins.PWM_UL = &HAL.IOs->pins->DIO6; + Pins.PWM_UH = &HAL.IOs->pins->DIO7; + Pins.PWM_VL = &HAL.IOs->pins->DIO8; + Pins.PWM_VH = &HAL.IOs->pins->DIO9; + Pins.PWM_WL = &HAL.IOs->pins->DIO10_PWM_WL; + Pins.PWM_WH = &HAL.IOs->pins->DIO11_PWM_WH; + + currentScalingFactor = currentScaling; + + Pins.HALL_U = hallU; + Pins.HALL_V = hallV; + Pins.HALL_W = hallW; + + HAL.IOs->config->toInput(Pins.HALL_U); + HAL.IOs->config->toInput(Pins.HALL_V); + HAL.IOs->config->toInput(Pins.HALL_W); + + // Calculate the openloop step time by setting the velocity + BLDC_setTargetOpenloopVelocity(openloopVelocity); + + // ADC + // Operation mode: Continuous mode on single selected channel + + rcu_periph_clock_enable(RCU_ADC1); + + adc_clock_config(ADC_ADCCK_PCLK2_DIV2); + adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT); + adc_sync_delay_config(ADC_SYNC_DELAY_5CYCLE); + adc_resolution_config(ADC1, ADC_RESOLUTION_12B); + adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE); + adc_external_trigger_config(ADC1, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_DISABLE); + adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(ADC1, ADC_ROUTINE_CHANNEL, 1); + + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + + adc_interrupt_enable(ADC1, ADC_INT_EOC); + nvic_irq_enable(ADC_IRQn, 0, 1); + + adc_enable(ADC1); + + adc_calibration_enable(ADC1); + + adc_software_trigger_enable(ADC1, ADC_ROUTINE_CHANNEL); + + // Timer + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_parameter_struct params; + timer_oc_parameter_struct oc_params; + timer_break_parameter_struct break_params; + timer_deinit(TIMER0); + + timer_struct_para_init(¶ms); + params.prescaler = 2; // Divides the timer freq by (prescaler + 1) => 3 + params.alignedmode = TIMER_COUNTER_EDGE; + params.counterdirection = TIMER_COUNTER_UP; + params.period = PWM_PERIOD; + params.clockdivision = TIMER_CKDIV_DIV1; + params.repetitioncounter = 1; + timer_init(TIMER0, ¶ms); + + + + timer_channel_output_struct_para_init(&oc_params); + oc_params.ocpolarity = TIMER_OC_POLARITY_HIGH; + oc_params.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + oc_params.outputstate = TIMER_CCX_ENABLE; + oc_params.outputnstate = TIMER_CCXN_ENABLE; + oc_params.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + oc_params.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; + timer_channel_output_config(TIMER0, TIMER_CH_0, &oc_params); + timer_channel_output_config(TIMER0, TIMER_CH_1, &oc_params); + timer_channel_output_config(TIMER0, TIMER_CH_2, &oc_params); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, PWM_PERIOD >> 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_break_struct_para_init(&break_params); + break_params.runoffstate = TIMER_ROS_STATE_ENABLE; + break_params.ideloffstate = TIMER_IOS_STATE_ENABLE; + break_params.deadtime = bbmTime; + break_params.breakpolarity = TIMER_BREAK_POLARITY_HIGH; + break_params.outputautostate = TIMER_OUTAUTO_ENABLE; + break_params.breakstate = TIMER_BREAK_DISABLE; + timer_break_config(TIMER0, &break_params); + + + timer_primary_output_config(TIMER0, ENABLE); + + timer_auto_reload_shadow_enable(TIMER0); + + timer_interrupt_enable(TIMER0, TIMER_INT_UP); + timer_update_event_enable(TIMER0); + nvic_irq_enable(TIMER0_UP_TIMER9_IRQn, 0, 1); + timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP); + + timer_enable(TIMER0); +} + +void BLDC_calibrateADCs() +{ + // Only do the offset compensation if PWM is off + if (targetPWM != 0) + return; + + // Temporarily disable the FTM interrupt to prevent it from overriding + // the adc phase selection + nvic_irq_disable(TIMER0_UP_TIMER9_IRQn); + + for (uint8_t myadc = 0; myadc < adcCount; myadc++) + { + adc = myadc % 3; + // Select the ADC phase for offset compensation + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + + // Reset the ADC state + adcOffset[adc] = 0; + adcState[adc] = ADC_INIT; + + // Wait until the ADC is initialized again + while (adcState[adc] == ADC_INIT); + } + + nvic_irq_enable(TIMER0_UP_TIMER9_IRQn, 0, 1); +} + +void ADC_IRQHandler() +{ + if(adc_interrupt_flag_get(ADC1, ADC_INT_FLAG_EOC) == SET) + { + uint16_t tmp = adc_routine_data_read(ADC1); + static ADC_Channel lastChannel = ADC_PHASE_U; + + switch(adcState[lastChannel]) + { + case ADC_INIT: + if (sampleCount[lastChannel] < ADC_SAMPLES) + { + // Store a calibration sample + adcOffset[lastChannel] += tmp; + + sampleCount[lastChannel]++; + } + else + { + // Finished collection of calibration samples + // Calculate offset + adcOffset[lastChannel] /= ADC_SAMPLES; + + adcState[lastChannel] = ADC_READY; + sampleCount[lastChannel] = 0; + } + break; + case ADC_READY: + adcSamples[adcSampleIndex] = (tmp - adcOffset[lastChannel]) * currentScalingFactor / 65536; + adcSampleIndex = (adcSampleIndex + 1) % ARRAY_SIZE(adcSamples); + + break; + } + + if (lastChannel != adc) + { + // Update the channel + lastChannel = adc; + + adc_routine_channel_config(ADC1, 0, adcPhases[adc], ADC_SAMPLETIME_15); + } + + adc_interrupt_flag_clear(ADC1, ADC_INT_FLAG_EOC); + } +} + +void TIMER0_UP_TIMER9_IRQHandler(void) +{ + if(timer_interrupt_flag_get(TIMER0, TIMER_INT_FLAG_UP) == SET) + { + static int32_t commutationCounter = 0; + static int32_t velocityCounter = 0; + + static int32_t lastHallAngle = 0; + static int32_t hallAngleDiffAccu = 0; + + // Measure the hall sensor + HallStates actualHallState = inputToHallState(HAL.IOs->config->isHigh(Pins.HALL_U), HAL.IOs->config->isHigh(Pins.HALL_V), HAL.IOs->config->isHigh(Pins.HALL_W)); + hallAngle = hallStateToAngle(actualHallState); + + // Calculate the hall angle difference + int32_t hallAngleDiff = (hallAngle - lastHallAngle); // [-300 ; +360) + hallAngleDiff = (hallAngleDiff + 360) % 360; // [ 0 ; +360) + hallAngleDiff = ((hallAngleDiff + 180) % 360) - 180; // [-180 ; +180) + lastHallAngle = hallAngle; + + // Accumulate the hall angle for velocity measurement + hallAngleDiffAccu += hallAngleDiff; + + // Calculate the velocity + if (++velocityCounter >= PWM_FREQ / VELOCITY_CALC_FREQ) + { + actualHallVelocity = hallAngleDiffAccu * 60 * VELOCITY_CALC_FREQ / 360; // electrical rotations per minute + + hallAngleDiffAccu = 0; + velocityCounter = 0; + } + + if (commutationMode == BLDC_OPENLOOP) + { + // open loop mode + if (openloopStepTime) + { + if (++commutationCounter >= openloopStepTime) + { + if (targetPWM > 0) + targetAngle = (targetAngle + 60) % 360; + else if (targetPWM < 0) + targetAngle = (targetAngle - 60 + 360) % 360; + + commutationCounter = 0; + } + } + } + else if (commutationMode == BLDC_HALL) + { + if (targetPWM > 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + targetAngle = ((hallAngle + 30) + 90) % 360; + } + else if (targetPWM < 0) + { + // The +30 are to compensate hall getting rounded to the nearest 60° step + // The +360 are to prevent a negative operand for the modulo. + targetAngle = ((hallAngle + 30) - 90 + 360) % 360; + } + else + { + targetAngle = hallAngle; + } + } + + // update commutation step + int16_t duty = ((int32_t)targetPWM * ((int32_t)PWM_PERIOD))/(int32_t)s16_MAX; + + if (duty < 0) + duty = -duty; + + switch (targetAngle % 360) + { + case 0: + // U: Disabled + // V: PWM + // W: GND + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_W; + break; + case 60: + // U: GND + // V: PWM + // W: Disabled + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_U; + break; + case 120: + // U: GND + // V: Disabled + // W: PWM + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, duty); + + adc = ADC_PHASE_U; + break; + case 180: + // U: Disabled + // V: GND + // W: PWM + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, duty); + + adc = ADC_PHASE_V; + break; + case 240: + // U: PWM + // V: GND + // W: Disabled + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_V; + break; + case 300: + // U: PWM + // V: Disabled + // W: GND + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_ENABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_U, duty); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_V, 0); + timer_channel_output_pulse_value_config(TIMER0, PWM_PHASE_W, 0); + + adc = ADC_PHASE_W; + break; + default: + // Disable all phases + timer_channel_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_U, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_V, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, PWM_PHASE_W, TIMER_CCXN_DISABLE); + break; + } + + // For one-phase measurement always use the same phase + if (adcCount == 1) + { + adc = ADC_PHASE_U; + } + + timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP); + } +} + +void BLDC_enablePWM(uint8_t enable) +{ + if (enable) + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_MODE_AF; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OTYPE_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PUPD_NONE; + gpio_af_set(Pins.PWM_UH->port, GPIO_AF_1, Pins.PWM_UH->bitWeight); + HAL.IOs->config->set(Pins.PWM_UH); + + gpio_af_set(Pins.PWM_UL->port, GPIO_AF_1, Pins.PWM_UL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + gpio_af_set(Pins.PWM_VH->port, GPIO_AF_1, Pins.PWM_VH->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + gpio_af_set(Pins.PWM_VL->port, GPIO_AF_1, Pins.PWM_VL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + gpio_af_set(Pins.PWM_WH->port, GPIO_AF_1, Pins.PWM_WH->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + gpio_af_set(Pins.PWM_WL->port, GPIO_AF_1, Pins.PWM_WL->bitWeight); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 1; + } + else + { + Pins.PWM_UH->configuration.GPIO_Mode = GPIO_MODE_INPUT; + Pins.PWM_UH->configuration.GPIO_OType = GPIO_OTYPE_PP; + Pins.PWM_UH->configuration.GPIO_PuPd = GPIO_PUPD_PULLDOWN; + + HAL.IOs->config->set(Pins.PWM_UH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_UL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_VL); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WH); + HAL.IOs->config->copy(&Pins.PWM_UH->configuration, Pins.PWM_WL); + + pwmEnabled = 0; + } +} + +uint8_t BLDC_isPWMenabled() +{ + return pwmEnabled; +} + +void BLDC_setTargetPWM(int16_t pwm) +{ + targetPWM = pwm; +} + +int16_t BLDC_getTargetPWM() +{ + return targetPWM; +} + +int32_t BLDC_getMeasuredCurrent() +{ + int32_t sum = 0; + for (uint8_t i = 0; i < ARRAY_SIZE(adcSamples); i++) + { + sum += adcSamples[i]; + } + + return sum / (int32_t) ARRAY_SIZE(adcSamples); +} + +void BLDC_setCommutationMode(BLDCMode mode) +{ + commutationMode = mode; +} + +BLDCMode BLDC_getCommutationMode() +{ + return commutationMode; +} + +void BLDC_setPolePairs(uint8 polePairs) +{ + if (polePairs == 0) + return; + + motorPolePairs = polePairs; +} + +uint8_t BLDC_getPolePairs() +{ + return motorPolePairs; +} + +void BLDC_setOpenloopStepTime(uint16_t stepTime) +{ + openloopStepTime = stepTime; +} + +uint16_t BLDC_getOpenloopStepTime() +{ + return openloopStepTime; +} + +int32_t BLDC_getTargetAngle() +{ + return targetAngle; +} + +int32_t BLDC_getHallAngle() +{ + return hallAngle; +} + +// Set the open loop velocity in RPM +void BLDC_setTargetOpenloopVelocity(uint32_t velocity) +{ + // 1 [RPM] = polePairs [eRPM] + // [eRPM] = [1/60 eRPS] = 6/60 [steps/s] + // steps/s = fpwm / openloopStepTime + // + // openloopStepTime = fpwm * 60 / 6 / velocity / polePairs + openloopStepTime = PWM_FREQ * 10 / velocity / motorPolePairs; + + // Store the requested velocity for accurate reading + // Otherwise we see rounding errors when reading back. + openloopVelocity = velocity; +} + +uint32_t BLDC_getTargetOpenloopVelocity() +{ + return openloopVelocity; +} + +int32_t BLDC_getActualOpenloopVelocity() +{ + if (commutationMode != BLDC_OPENLOOP) + return 0; + + if (targetPWM > 0) + return openloopVelocity; + else if (targetPWM < 0) + return -openloopVelocity; + else + return 0; +} + +// Velocity measured by hall in RPM +int32_t BLDC_getActualHallVelocity() +{ + return actualHallVelocity / motorPolePairs; +} + +void BLDC_setHallOrder(uint8_t order) +{ + if (order < 3) + { + hallOrder = order; + } +} + +uint8_t BLDC_getHallOrder() +{ + return hallOrder; +} + +void BLDC_setHallInvert(uint8_t invert) +{ + hallInvert = (invert)? 1:0; +} + +uint8_t BLDC_getHallInvert() +{ + return hallInvert; +} + +void BLDC_setBBMTime(uint8_t time) +{ + // Clip to the maximum value instead of overflowing + bbmTime = MAX(127, time); + + TIMER_CCHP(TIMER0) = (TIMER_CCHP(TIMER0) & (~(uint32_t)TIMER_CCHP_DTCFG)) | + (((uint32_t)TIMER_CCHP_DTCFG) & bbmTime); +} + +uint8_t BLDC_getBBMTime() +{ + return bbmTime; +} diff --git a/TMC2209/lib/tmc/tmc/BoardAssignment.c b/TMC2209/lib/tmc/tmc/BoardAssignment.c new file mode 100644 index 0000000..33bcb14 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/BoardAssignment.c @@ -0,0 +1,193 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "hal/derivative.h" +#include "hal/HAL.h" + +#include "TMCL.h" +#include "IdDetection.h" +#include "EEPROM.h" +#include "BoardAssignment.h" + +static uint8_t assignCh1(uint8_t id, uint8_t justCheck); +static uint8_t assignCh2(uint8_t id, uint8_t justCheck); +static void hookDriverSPI(IdAssignmentTypeDef *ids); +static void unassign(IdAssignmentTypeDef *ids); + +int32_t Board_assign(IdAssignmentTypeDef *ids) +{ + int32_t out = 0; + + // Test mode // todo REM 2: still needed? (LH) + if((ids->ch1.id == 0xFF) || (ids->ch2.id == 0xFF)) + { + if((Evalboards.ch1.id != 0) || (Evalboards.ch2.id != 0) || (ids->ch1.id != ids->ch2.id)) + { + ids->ch1.state = ID_STATE_NOT_IN_FW; + ids->ch2.state = ID_STATE_NOT_IN_FW; + out |= ids->ch2.state << 24; + out |= ids->ch2.id << 16; + out |= ids->ch1.state << 8; + out |= ids->ch1.id << 0; + return out; + } + } + + // Assign motion controller + if((Evalboards.ch1.id == ids->ch1.id) && (ids->ch1.id != 0)) + { // todo CHECK 2: Evalboards.ch_.id only gets written at the end of this function - so the only way we can reach this case by calling this function multiple times. + // Therefor, the else case always runs before, which means any information returned by the justCheck = true call here would have already been + // given by the previous call of this function. This entire ID detection procedure is kinda messy, maybe we can actually completely rework it (LH) + ids->ch1.state = assignCh1(ids->ch1.id, true); + } + else + { + Evalboards.ch1.deInit(); // todo REM 2: Hot-Unplugging is not maintained currently, should probably be removed (LH) #1 + if(ids->ch1.state == ID_STATE_DONE) + ids->ch1.state = assignCh1(ids->ch1.id, false); + Evalboards.ch1.config->reset(); + } + + // Assign driver + if((Evalboards.ch2.id == ids->ch2.id) && (ids->ch2.id != 0)) + { + ids->ch2.state = assignCh2(ids->ch2.id, true); + } + else + { + Evalboards.ch2.deInit(); // todo REM 2: Hot-Unplugging is not maintained currently, should probably be removed (LH) #2 + if(ids->ch2.state == ID_STATE_DONE) + ids->ch2.state = assignCh2(ids->ch2.id, false); + Evalboards.ch2.config->reset(); + } + + // Reroute SPI 2 (that the driver uses) to run through the motion controller if required + // This allows the chaining of a motion controller and a driver. + // Note that the motion controller has to invoke reset() or restore() of the driver + // in order to have settings sent through the hooked SPI. + // This is currently done on completed motion controller reset/restore + hookDriverSPI(ids); + + Evalboards.ch1.id = ids->ch1.id; + Evalboards.ch2.id = ids->ch2.id; + + out |= (ids->ch2.state << 24) & 0xFF; + out |= (ids->ch2.id << 16) & 0xFF; + out |= (ids->ch1.state << 8) & 0xFF; + out |= (ids->ch1.id << 0) & 0xFF; + + return out; +} + +int32_t Board_supported(IdAssignmentTypeDef *ids) +{ + int32_t out = 0; + + ids->ch1.state = assignCh1(ids->ch1.id, true); + ids->ch2.state = assignCh2(ids->ch2.id, true); + + out |= ids->ch2.state << 24; + out |= ids->ch2.id << 16; + out |= ids->ch1.state << 8; + out |= ids->ch1.id << 0; + + return out; +} + +static uint8_t assignCh1(uint8_t id, uint8_t justCheck) +{ + uint8_t ok = ID_STATE_NOT_IN_FW; + if(!justCheck) + tmcmotioncontroller_init(); + + for(size_t i = 0, sz = ARRAY_SIZE(init_ch1); i < sz; i++) + { + if(init_ch1[i].id == id) + { + if(!justCheck) + init_ch1[i].init(); + ok = ID_STATE_DONE; + break; + } + } + + return ok; +} + +static uint8_t assignCh2(uint8_t id, uint8_t justCheck) +{ + uint8_t ok = ID_STATE_NOT_IN_FW; + +// if(!justCheck) +// tmcdriver_init(); + + for(size_t i = 0, sz = ARRAY_SIZE(init_ch2); i < sz; i++) + { + if(init_ch2[i].id == id) + { + if(!justCheck) + init_ch2[i].init(); + ok = ID_STATE_DONE; + break; + } + } + + return ok; +} + +// Reroute the driver's SPI to run through the motion controller if required +// This also handles special case logic for the motion controller + driver chain (different pins etc.) +static void hookDriverSPI(IdAssignmentTypeDef *ids) +{ + if(ids->ch1.id == ID_TMC4361A) + { + // Redirect ch2 SPI to the SPI cover function of the TMC43XX Board + HAL.SPI->ch2.readWrite = Evalboards.ch1.cover; + + if(ids->ch2.id == ID_TMC2660) + { + // TMC2660: Disable the continuous mode via userFunction + int32_t value = 1; + Evalboards.ch2.userFunction(0, 0, &value); + } + } + + + if (ids->ch1.id == ID_TMC4361A) + { + if (ids->ch2.id == ID_TMC2130) + { + Evalboards.ch2.userFunction(6, 0, NULL); + } + } +} + +static void unassign(IdAssignmentTypeDef *ids) +{ + UNUSED(ids); +} + +void periodicJob(uint32_t tick) +{ + UNUSED(tick); +} + +void deInit(void) +{ + IdAssignmentTypeDef ids; + Evalboards.ch1.deInit(); + Evalboards.ch2.deInit(); + + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + unassign(&ids); + + tmcdriver_init(); + tmcmotioncontroller_init(); +} diff --git a/TMC2209/lib/tmc/tmc/BoardAssignment.h b/TMC2209/lib/tmc/tmc/BoardAssignment.h new file mode 100644 index 0000000..1421c65 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/BoardAssignment.h @@ -0,0 +1,187 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef BOARD_ASSIGNMENT_H +#define BOARD_ASSIGNMENT_H + +#include "boards/Board.h" + +typedef enum { + FOUND_BY_NONE, + FOUND_BY_MONOFLOP, + FOUND_BY_EEPROM +} IDFinder; + +typedef struct +{ + uint8_t state; // detection state of this board + uint8_t id; // id of board + IDFinder detectedBy; // Holds the method used to detect the ID (Monoflop or EEPROM) + uint32_t counter_1; // Timer cycles elapsed on ID pulse rising edge + uint32_t counter_2; // Timer cycles elapsed on ID pulse falling edge + uint32_t timer_1; // Current timer value on ID pulse rising edge + uint32_t timer_2; // Current timer value on ID pulse falling edge +} IdStateTypeDef; // interface for id and detection state of a board + +typedef struct +{ + IdStateTypeDef ch1; // interface for id and detection state for the driver board + IdStateTypeDef ch2; // interface for id and detection state for the motion controller board +} IdAssignmentTypeDef; // interface for id and detection state of driver and motion controller board + +extern IdAssignmentTypeDef IdState; + +int32_t Board_assign(IdAssignmentTypeDef *ids); // ids and states of assigned driver and motion controller board +int32_t Board_supported(IdAssignmentTypeDef *ids); // ids and states of supported driver and motion controller board + +#include "boards/SelfTest.h" + +// ids for channel 0 +#define ID_ERROR 0 +#define ID_TMC5031 2 +#define ID_TMC5130 5 +#define ID_TMC5041 6 +#define ID_TMC5072 7 +#define ID_TMC4361A 11 +#define ID_TMC4671 13 +#define ID_TMC5160 16 +#define ID_TMC5062 25 +#define ID_TMC8460 8 +#define ID_TMC8461 26 +#define ID_TMC8462 27 +#define ID_TMC5240 28 +#define ID_TMC5272 29 +#define ID_TMC5271 31 +#define ID_TMC2130_TQFP48 0xFE +#define ID_SELFTEST 255 + +// ids for channel 1 +#define ID_TMC2660 1 +#define ID_TMC2130 3 +#define ID_TMC2100 4 +#define ID_TMC2208 6 +#define ID_TMC2224 7 +#define ID_TMC6200 10 +#define ID_TMC2160 11 +#define ID_TMC2240 28 +#define ID_TMC7300 12 +#define ID_TMC2590 13 +#define ID_TMC6100 19 +#define ID_TMC6100_BOB 25 // For the TMC4671+TMC6100-BOB +#define ID_TMC2210 29 +#define ID_TMC2209 8 +#define ID_TMC2225 18 +#define ID_TMC2300 14 +#define ID_TMC2226 22 +#define ID_MAX22216_EVAL 30 +#define ID_MAX22216_BOB 31 +#define ID_MAX22204_EVAL 32 +#define ID_MAX22210_EVAL 33 +#define ID_TMC6300 21 +#define ID_TMC6140 23 +#define ID_TMC8100 34 + + +// init() functions for all boards - function definitions are in the respective _eval file of a chip +extern void MAX22216_init(); +extern void MAX22204_init(); +extern void MAX22210_init(); +extern void TMC2100_init(); +extern void TMC2130_init(); +extern void TMC2160_init(); +extern void TMC2208_init(); +extern void TMC2209_init(); +extern void TMC2210_init(); +extern void TMC2224_init(); +extern void TMC2225_init(); +extern void TMC2226_init(); +extern void TMC2240_init(); +extern void TMC2300_init(); +extern void TMC2590_init(); +extern void TMC2660_init(); +extern void TMC4361A_init(); +extern void TMC4671_init(); +extern void TMC5031_init(); +extern void TMC5041_init(); +extern void TMC5062_init(); +extern void TMC5072_init(); +extern void TMC5130_init(); +extern void TMC5160_init(); +extern void TMC5240_init(); +extern void TMC5271_init(); +extern void TMC5272_init(); +extern void TMC6100_init(); +extern void TMC6100_BOB_init(); +extern void TMC6140_init(); +extern void TMC6200_init(); +extern void TMC6300_init(); +extern void TMC7300_init(); +extern void TMC8100_init(); +extern void TMC8461_init_ch1(); +extern void TMC8461_init_ch2(); +extern void TMC8462_init_ch1(); +extern void TMC8462_init_ch2(); +extern void SelfTest_init(); + +#if defined(LandungsbrueckeV3) + extern void PD8_IRQHandler(); +#endif + +typedef struct { + uint16_t id; + void (*init)(void); +} init_assignment; + +static const init_assignment init_ch1[] = +{ + { .id = ID_TMC5031, .init = TMC5031_init }, + { .id = ID_TMC5130, .init = TMC5130_init }, + { .id = ID_TMC5041, .init = TMC5041_init }, + { .id = ID_TMC5072, .init = TMC5072_init }, + { .id = ID_TMC4361A, .init = TMC4361A_init }, + { .id = ID_TMC4671, .init = TMC4671_init }, + { .id = ID_TMC5160, .init = TMC5160_init }, + { .id = ID_TMC5240, .init = TMC5240_init }, + { .id = ID_TMC5271, .init = TMC5271_init }, + { .id = ID_TMC5272, .init = TMC5272_init }, + { .id = ID_TMC5062, .init = TMC5062_init }, + { .id = ID_TMC8461, .init = TMC8461_init_ch1 }, + { .id = ID_TMC8462, .init = TMC8462_init_ch1 }, + { .id = ID_SELFTEST, .init = SelfTest_init } +}; + +static const init_assignment init_ch2[] = +{ + { .id = ID_TMC2660, .init = TMC2660_init }, + { .id = ID_TMC2130, .init = TMC2130_init }, + { .id = ID_TMC2100, .init = TMC2100_init }, + { .id = ID_TMC2208, .init = TMC2208_init }, + { .id = ID_TMC2224, .init = TMC2224_init }, + { .id = ID_TMC2240, .init = TMC2240_init }, + { .id = ID_TMC2590, .init = TMC2590_init }, + { .id = ID_TMC6100, .init = TMC6100_init }, + { .id = ID_TMC6100_BOB, .init = TMC6100_BOB_init }, + { .id = ID_TMC6200, .init = TMC6200_init }, + { .id = ID_TMC7300, .init = TMC7300_init }, + { .id = ID_TMC2160, .init = TMC2160_init }, + { .id = ID_TMC2210, .init = TMC2210_init }, + { .id = ID_MAX22216_EVAL, .init = MAX22216_init }, + { .id = ID_MAX22216_BOB, .init = MAX22216_init }, + { .id = ID_MAX22204_EVAL, .init = MAX22204_init }, + { .id = ID_MAX22210_EVAL, .init = MAX22210_init }, + { .id = ID_TMC2209, .init = TMC2209_init }, + { .id = ID_TMC2225, .init = TMC2225_init }, + { .id = ID_TMC2226, .init = TMC2226_init }, + { .id = ID_TMC2300, .init = TMC2300_init }, + { .id = ID_TMC6300, .init = TMC6300_init }, + { .id = ID_TMC6140, .init = TMC6140_init }, + { .id = ID_TMC8100, .init = TMC8100_init }, +}; + +#endif /* BOARD_ASSIGNMENT_H */ diff --git a/TMC2209/lib/tmc/tmc/EEPROM.c b/TMC2209/lib/tmc/tmc/EEPROM.c new file mode 100644 index 0000000..19dc666 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/EEPROM.c @@ -0,0 +1,322 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "EEPROM.h" +#include + +EEPROM_Channels EEPROM = +{ + .ch1 = + { + .init = false, + .name = { 0 }, + .id = 0, + .hw = 0, + .magic = 0 + }, + .ch2 = + { + .init = false, + .name = { 0 }, + .id = 0, + .hw = 0, + .magic = 0 + } +}; + +// Perform initial scan and store to struct +void eeprom_init(SPIChannelTypeDef *SPIChannel) +{ + uint8_t buffer[EEPROM_SIZE_META] = { 0 }; + EEPROM_Data *eep = (SPIChannel == &SPI.ch1) ? &EEPROM.ch1 : &EEPROM.ch2; + eeprom_read_array(SPIChannel, EEPROM_ADDR_META, buffer, EEPROM_SIZE_META); + memcpy(eep->name, &buffer[EEPROM_ADDR_NAME - EEPROM_ADDR_META], EEPROM_SIZE_NAME); + eep->id = _8_16(buffer[EEPROM_ADDR_ID - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_ID + 1) - EEPROM_ADDR_META]); + eep->hw = _8_16(buffer[EEPROM_ADDR_HW - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_HW + 1) - EEPROM_ADDR_META]); + eep->magic = _8_16(buffer[EEPROM_ADDR_MAGIC - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_MAGIC + 1) - EEPROM_ADDR_META]); + eep->init = true; +// eeprom_read_array(&SPI.ch2, EEPROM_ADDR_META, buffer, EEPROM_SIZE_META); +// memcpy(EEPROM.ch2.name, &buffer[EEPROM_ADDR_NAME - EEPROM_ADDR_META], EEPROM_SIZE_NAME); +// EEPROM.ch2.id = _8_16(buffer[EEPROM_ADDR_ID - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_ID + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.hw = _8_16(buffer[EEPROM_ADDR_HW - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_HW + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.magic = _8_16(buffer[EEPROM_ADDR_MAGIC - EEPROM_ADDR_META], buffer[(EEPROM_ADDR_MAGIC + 1) - EEPROM_ADDR_META]); +// EEPROM.ch2.init = true; +} + +/******************************************************************* + Function: eeprom_check + Parameters: SPI channel the Eeprom should be checked on + + Returns: false when an Eeprom has been successfully detected and is in ready status + The status of the eeprom otherwise + + Purpose: checking whether Eeprom is connected and ready +********************************************************************/ +uint8_t eeprom_check(SPIChannelTypeDef *SPIChannel) +{ + // Prüfen, ob der SPI-Bus schon funktioniert: Im Status-Register des EEPROMs + // müssen Bit 6, 5, 4 und 0 auf jedem Fall 0 sein und nicht 1. + // Watchdog darf an dieser Stelle ruhig zuschlagen. + + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + uint8_t out = SPIChannel->readWrite(0x00, true); + // check whether bits 6, 5, 4 and 0 are cleared + if((out & 0x71) != 0) + goto end; + + out = 0; + + //check for magic number in eeprom + uint8_t number[2]; + + eeprom_read_array(SPIChannel, EEPROM_ADDR_MAGIC, number, 2); + + if(number[0] != MAGICNUMBER_LOW || number[1] != MAGICNUMBER_HIGH) + { + out = ID_CHECKERROR_MAGICNUMBER; + } + + end: + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; + + if(out && ((SPIChannel == &SPI.ch1 && !EEPROM.ch1.init) + || (SPIChannel == &SPI.ch2 && !EEPROM.ch2.init))) { + eeprom_init(SPIChannel); + } + + return out; +} + + +/******************************************************************* + Funktion: eeprom_write_byte + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + value: der zu schreibende Wert + + Rückgabewert: --- + + Zweck: Schreiben eines Bytes in das EEPROM auf dem Evalboard. +********************************************************************/ +void eeprom_write_byte(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t value) +{ + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + EEPROM.ch1.init = false; + } else { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + EEPROM.ch2.init = false; + } + + IOs.toOutput(SPIChannel->CSN); + + // Schreiben erlauben + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) == 0x00); // Warte bis "Write Enable"-Bit gesetzt ist + + // Eigentliches Schreiben + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + SPIChannel->readWrite(value, true); + + // Warten bis Schreibvorgang beendet ist + do + { + SPIChannel->readWrite(0x05, false); //Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + //block writing + SPIChannel->readWrite(0x04, true); //Befehl "Write Disable" + do + { + SPIChannel->readWrite(0x05, false); //Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) != 0x00); //Warte bis "Write Enable"-Bit zurückgesetzt wird + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} + + +/******************************************************************* + Funktion: eeprom_write_array + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + data: Startadresse des zu schreibenden Blocks + size: Länge des Blocks in Bytes + + Rückgabewert: --- + + Zweck: Schreiben mehrerer Bytes in das EEPROM auf dem Evalboard. + Dabei können beliebig viele Bytes (also auch das gesamte EEPROM + beschrieben werden (die speziellen Eigenschaften des 25128 werden + dabei beachtet). +********************************************************************/ +void eeprom_write_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size) +{ + uint16_t i; + + //select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + EEPROM.ch1.init = false; + } else { + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + EEPROM.ch2.init = false; + } + + IOs.toOutput(SPIChannel->CSN); + + // Schreiben erlauben + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite( 0x05, false); //Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02)==0x00); //Warte bis "Write Enable"-Bit gesetzt + + // Schreibvorgang (Startadresse) + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + // Eigentliches Schreiben der Daten + for(i = 0; i < size; i++) + { + // Adresse mitzählen und bei Ãœberlauf der untersten sechs Bits das EEPROM deselektieren + // und neuen Write-Befehl senden (bzw. beim letzten Datenbyte einfach nur EEPROM + // deselektieren). + // Dies ist erforderlich, da beim Beschreiben im 25128 nur die untersten sechs Bits der + // Adresse hochgezählt werden (anders als beim Lesen). + address++; + SPIChannel->readWrite(*(data+i), (address & 0x0000003F)==0 || i==size-1); + if((address & 0x0000003F)==0 && ireadWrite(0x05, false); // Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + // Neuer "Write Enable"-Befehl + SPIChannel->readWrite(0x06, true); // Befehl "Write Enable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02)==0x00); //Warte bis "Write Enable"-Bit gesetzt + + // Neuer "Write"-Befehl (mit der nächsten Adresse) + SPIChannel->readWrite(0x02, false); // Befehl "Write" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + } + } + + // Warte bis Schreibvorgang beendet + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while(SPIChannel->readWrite(0x00, true) & 0x01); + + // block writing + SPIChannel->readWrite(0x04, true); // Befehl "Write Disable" + do + { + SPIChannel->readWrite(0x05, false); // Befehl "Get Status" + } while((SPIChannel->readWrite(0x00, true) & 0x02) != 0x00); // Warte bis "Write Enable"-Bit zurückgesetzt wird + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} + + +/******************************************************************* + Funktion: eeprom_read_byte + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + + Rückgabewert: der gelesene Wert + + Zweck: Lesen eines Bytes aus dem EEPROM des Evalboards. +********************************************************************/ +uint8_t eeprom_read_byte(SPIChannelTypeDef *SPIChannel, uint16_t address) +{ + //select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x03, false); //Befehl "Read" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + uint8_t out = SPIChannel->readWrite(0, true); + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; + + return out; +} + + +/******************************************************************* + Funktion: eeprom_read_array + Parameter: Channel: EEP_CH1 oder EEP_CH2 + address: Adresse im EEPROM (0..16383) + data: Startadresse des zu lesenden Blocks + size: Länge des Blocks in Bytes + + Rückgabewert: --- + + Zweck: Lesen mehrerer Bytes aus dem Konfigurations-EEPROM. + Dabei dürfen ab beliebiger Adresse beliebig viele Bytes gelesen + werden. +********************************************************************/ +void eeprom_read_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size) +{ + uint16_t i; + + // select CSN of eeprom + IOPinTypeDef* io = SPIChannel->CSN; + if(SPIChannel == &SPI.ch1) + SPIChannel->CSN = &HAL.IOs->pins->ID_CH0; + else + SPIChannel->CSN = &HAL.IOs->pins->ID_CH1; + + IOs.toOutput(SPIChannel->CSN); + + SPIChannel->readWrite(0x03, false); // Befehl "Read" + SPIChannel->readWrite(address >> 8, false); + SPIChannel->readWrite(address & 0xFF, false); + + for(i = 0; i < size; i++) + *(data+i) = SPIChannel->readWrite(0, i == size-1); // beim letzten Byte EEPROM deselektieren + + HAL.IOs->config->toInput(SPIChannel->CSN); + SPIChannel->CSN = io; +} diff --git a/TMC2209/lib/tmc/tmc/EEPROM.h b/TMC2209/lib/tmc/tmc/EEPROM.h new file mode 100644 index 0000000..f9a23b4 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/EEPROM.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMC_EEPROM_H_ +#define TMC_EEPROM_H_ + +#include "tmc/helpers/API_Header.h" + +#include "hal/SPI.h" +#include "hal/HAL.h" + +#define EEPROM_ADDR_NAME 0 +#define EEPROM_ADDR_ID 16 +#define EEPROM_ADDR_HW 18 +#define EEPROM_ADDR_MAGIC 20 +#define EEPROM_ADDR_META 0 + +#define EEPROM_SIZE_NAME 16 +#define EEPROM_SIZE_ID 2 +#define EEPROM_SIZE_HW 2 +#define EEPROM_SIZE_MAGIC 2 +#define EEPROM_SIZE_META (EEPROM_SIZE_NAME + EEPROM_SIZE_ID + EEPROM_SIZE_HW + EEPROM_SIZE_MAGIC) + +#define MAGICNUMBER_LOW 0x12 +#define MAGICNUMBER_HIGH 0x34 + +#define ID_CHECKERROR_MAGICNUMBER 2 + +typedef struct { + bool init; + uint8_t name[EEPROM_SIZE_NAME]; + uint16_t id; + uint16_t hw; + uint16_t magic; +} EEPROM_Data; + +typedef struct { + EEPROM_Data ch1; + EEPROM_Data ch2; +} EEPROM_Channels; + +extern EEPROM_Channels EEPROM; + +void eeprom_init(SPIChannelTypeDef *SPIChannel); + +uint8_t eeprom_check(SPIChannelTypeDef *SPIChannel); + +void eeprom_write_byte(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t value); +void eeprom_write_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *data, uint16_t size); + +uint8_t eeprom_read_byte(SPIChannelTypeDef *SPIChannel, uint16_t address); +void eeprom_read_array(SPIChannelTypeDef *SPIChannel, uint16_t address, uint8_t *block, uint16_t size); + +#endif /* TMC_EEPROM_H_ */ diff --git a/TMC2209/lib/tmc/tmc/IdDetection.h b/TMC2209/lib/tmc/tmc/IdDetection.h new file mode 100644 index 0000000..22e1b4c --- /dev/null +++ b/TMC2209/lib/tmc/tmc/IdDetection.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef ID_DETECTION_H +#define ID_DETECTION_H + + #include "BoardAssignment.h" + + // id detection state definitions + #define ID_STATE_WAIT_LOW 0 // id detection waiting for first edge (currently low) + #define ID_STATE_WAIT_HIGH 1 // id detection waiting for second edge (currently high) + #define ID_STATE_DONE 2 // id detection finished successfully + #define ID_STATE_INVALID 3 // id detection failed - we got an answer, but no corresponding ID (invalid ID pulse length) + #define ID_STATE_NO_ANSWER 4 // id detection failed - board doesn't answer + #define ID_STATE_TIMEOUT 5 // id detection failed - board id pulse went high but not low + #define ID_STATE_NOT_IN_FW 6 // id detection detected a valid id that is not supported in this firmware + + void IDDetection_init(void); + void IDDetection_deInit(void); + uint8_t IDDetection_detect(IdAssignmentTypeDef *out); + void IDDetection_initialScan(IdAssignmentTypeDef *ids); + +#endif /* ID_DETECTION_H */ diff --git a/TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c b/TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c new file mode 100644 index 0000000..883b643 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/IdDetection_Landungsbruecke.c @@ -0,0 +1,415 @@ +/******************************************************************************* +* Copyright © 2013 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * Calling IDDetection_detect(IdAssignmentTypeDef *result) will start the ID detection process. + * The function returns the ID Results through the IdAssignmentTypeDef struct result points to. + * The detection will be done by monoflop pulse duration measurement or via EEPROM readout. + * While this process is still ongoing the function will return ID_STATE_WAIT_HIGH. Once the + * ID detection of both channels has been finished, ID_STATE_DONE will be returned. + * + * Calling the function again after the detection has finished will start another scan. + */ + +#include "tmc/helpers/API_Header.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "BoardAssignment.h" +#include "EEPROM.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "TMCL.h" + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids); +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids); + +// Helper macros +#define ID_CLK_LOW() HAL.IOs->config->setLow(&HAL.IOs->pins->ID_CLK); // set id clk signal to low +#define ID_CLK_HIGH() HAL.IOs->config->setHigh(&HAL.IOs->pins->ID_CLK); // set id clk signal to high +#define IDSTATE_SCAN_DONE(ID_STATE) \ + ( \ + (ID_STATE.ch1.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch1.state != ID_STATE_WAIT_HIGH) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_HIGH) \ + ) + +static uint8_t assign(uint32_t pulse); + +typedef enum { + MONOFLOP_INIT, + MONOFLOP_SCANNING, + MONOFLOP_DONE, + + MONOFLOP_END +} State_MonoflopDetection; + +State_MonoflopDetection monoflopState = MONOFLOP_INIT; + +/* Timer Frequency: + * System Clock 48MHz + * ------------ = ----- = 6MHz + * Prescaler 8 + * + * Calculate time interval (t_id) in 0.1µs from the timer tick difference (ticks): + * 0.1s 10s + * t_id * 0.1µs = ---- = ticks * 6MHz * --- <--- Tick Conversion factor: 10/6 + * 10^6 6 + */ +#define TICK_FACTOR 10/6 + +IdAssignmentTypeDef IdState = { 0 }; + +// Interrupt: Edge on GPIO Port B +void PORTB_IRQHandler(void) +{ + // Store the timing values + uint32_t timerVal = FTM2_CNT; + + // Store the interrupt flag state and then reset the flags + uint32_t interruptFlags = PORTB_ISFR; + PORTB_ISFR = PORT_ISFR_ISF_MASK; + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + // ======== CH0 ========== + // Check if Pin ID_CH0 generated the interrupt + if(interruptFlags & PORT_ISFR_ISF(HAL.IOs->pins->ID_CH0.bitWeight)) + { + if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Second ID pulse edge - store timer values -> state DONE + IdState.ch1.timer_2 = timerVal; + IdState.ch1.counter_2 = 0; + IdState.ch1.state = ID_STATE_DONE; + } + else + { // First ID pulse edge - store timer values -> state WAIT_HIGH + IdState.ch1.timer_1 = timerVal; + IdState.ch1.counter_1 = 0; + IdState.ch1.state = ID_STATE_WAIT_HIGH; + } + } + + // ======== CH1 ========== + // Check if Pin ID_CH1 generated the interrupt + if(interruptFlags & PORT_ISFR_ISF(HAL.IOs->pins->ID_CH1.bitWeight)) + { + if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Second ID pulse edge - store timer values -> state DONE + IdState.ch2.timer_2 = timerVal; + IdState.ch2.counter_2 = 0; + IdState.ch2.state = ID_STATE_DONE; + } + else + { // First ID pulse edge - store timer values -> state WAIT_HIGH + IdState.ch2.timer_1 = timerVal; + IdState.ch2.counter_1 = 0; + IdState.ch2.state = ID_STATE_WAIT_HIGH; + } + } +} + +void FTM2_IRQHandler() +{ + // clear timer overflow flag + FTM2_SC &= ~FTM_SC_TOF_MASK; + + // Stop the timer + FTM2_SC &= ~FTM_SC_CLKS_MASK; + + // Abort if we're not scanning + if(monoflopState == MONOFLOP_SCANNING) + { + monoflopState = MONOFLOP_DONE; + return; + } +} + +void IDDetection_init(void) +{ + monoflopState = MONOFLOP_INIT; + + + // ====== Timer initialisation ======= + // Enable clock for FTM2 + SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; + + // Disable write protection, FTM specific registers are available + FTM2_MODE |= FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK | FTM_MODE_FAULTM_MASK; + + // Clear the CLKS field to avoid buffered write issues for MOD + FTM2_SC &= ~FTM_SC_CLKS_MASK; + + // Use the full time period available + FTM2_MOD = 0xFFFF; + FTM2_CNTIN = 0; + FTM2_CNT = 0; + + // Clock source: System Clock (48 MHz), Prescaler: 8 -> 6 MHz Timer clock + FTM2_SC |= FTM_SC_CLKS(1) | FTM_SC_PS(3); + + // The TOF bit is set for each counter overflow + FTM2_CONF |= FTM_CONF_NUMTOF(0); + + // Edge-Aligned PWM (EPWM) mode + FTM2_C0SC |= FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK; + + // Enable FTM2 Timer Overflow interrupt + FTM2_SC |= FTM_SC_TOIE_MASK; + + // Set FTM2 interrupt handler + enable_irq(INT_FTM2 - 16); + + // ====== Pin initialisation ====== + // Enable Clock gating on port B + SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; + + // Configure Pin + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CLK); + + // Enable GPIO, edge-triggered interrupt, and PullUp + PORT_PCR_REG(HAL.IOs->pins->ID_CH0.portBase, HAL.IOs->pins->ID_CH0.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + PORT_PCR_REG(HAL.IOs->pins->ID_CH1.portBase, HAL.IOs->pins->ID_CH1.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + + // Clear interrupt flags + PORTB_ISFR = -1; + + // Enable interrupt + enable_irq(INT_PORTB - 16); +} + +void IDDetection_deInit() +{ + disable_irq(INT_FTM2 - 16); + FTM2_SC &= ~FTM_SC_CLKS_MASK; + FTM2_SC &= ~FTM_SC_TOF_MASK; + + disable_irq(INT_PORTB - 16); + PORTB_ISFR = -1; +} + +//returns ID assigned to given pulse (length in 0.1us) +static uint8_t assign(uint32_t pulse) +{ + if( pulse < 5 ) return 0; // error + else if(pulse < 110 ) return 1; + else if(pulse < 135 ) return 2; + else if(pulse < 165 ) return 3; + else if(pulse < 200 ) return 4; + else if(pulse < 245 ) return 5; + else if(pulse < 300 ) return 6; + else if(pulse < 360 ) return 7; + else if(pulse < 430 ) return 8; + else if(pulse < 515 ) return 9; + else if(pulse < 620 ) return 10; + else if(pulse < 750 ) return 11; + else if(pulse < 910 ) return 12; + else if(pulse < 1100 ) return 13; + else if(pulse < 1350 ) return 14; + else if(pulse < 1650 ) return 15; + else if(pulse < 2000 ) return 16; + else if(pulse < 2450 ) return 17; + else if(pulse < 3000 ) return 18; + else if(pulse < 3600 ) return 19; + else if(pulse < 4300 ) return 20; + else if(pulse < 5150 ) return 21; + else if(pulse < 6200 ) return 22; + else if(pulse < 7500 ) return 23; + else if(pulse < 9100 ) return 24; + else if(pulse < 11000 ) return 25; + else if(pulse < 13500 ) return 26; + else if(pulse < 16500 ) return 27; + else if(pulse < 20000 ) return 28; + else if(pulse < 24500 ) return 29; + else if(pulse < 30000 ) return 30; + else if(pulse < 36000 ) return 31; + else if(pulse < 43000 ) return 32; + else if(pulse < 51500 ) return 33; + else if(pulse < 62000 ) return 34; + else if(pulse < 75000 ) return 35; + else if(pulse < 91000 ) return 36; + + return 0; // error +} + +// Detect IDs of attached boards - returns true when done +uint8_t IDDetection_detect(IdAssignmentTypeDef *out) +{ + // Try to identify the IDs via monoflop pulse duration + if (!detectID_Monoflop(out)) + return false; + + // Try to identify the IDs via EEPROM readout + detectID_EEPROM(out); + + // Detection finished + return true; +} + +void IDDetection_initialScan(IdAssignmentTypeDef *ids) +{ + while(!IDDetection_detect(ids)) + { + vitalsignsmonitor_checkVitalSigns(); + tmcl_process(); + } +} + + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids) +{ + switch (monoflopState) + { + case MONOFLOP_INIT: + FTM2_SC &= ~FTM_SC_CLKS_MASK; // stop timer + FTM2_CNT = 0; // clear counter + + IdState.ch1.state = ID_STATE_WAIT_LOW; + IdState.ch1.detectedBy = FOUND_BY_NONE; + IdState.ch2.state = ID_STATE_WAIT_LOW; + IdState.ch2.detectedBy = FOUND_BY_NONE; + + // Update the monoflop state before activating the timer. Otherwise bad + // luck with other unrelated interrupts might cause enough delay to + // trigger the timer overflow after starting the timer before updating + // this state - which results in the timeout no longer working. + monoflopState = MONOFLOP_SCANNING; + + FTM2_SC |= FTM_SC_CLKS(1); // start timer + ID_CLK_HIGH(); + break; + case MONOFLOP_SCANNING: + if(IDSTATE_SCAN_DONE(IdState)) + { + monoflopState = MONOFLOP_DONE; + } + break; + case MONOFLOP_DONE: + // Scan complete + ID_CLK_LOW(); + FTM2_SC &= ~FTM_SC_CLKS_MASK; // stop timer + + // ======== CH0 ========== + // Assign ID detection state for this channel + ids->ch1.state = IdState.ch1.state; + + if(IdState.ch1.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + uint32_t tickDiff = IdState.ch1.timer_2 - IdState.ch1.timer_1; + ids->ch1.id = assign(tickDiff * TICK_FACTOR); + + if(ids->ch1.id) + IdState.ch1.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch1.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + ids->ch1.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch1.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + ids->ch1.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch1.id = 0; + } + + // ======== CH1 ========== + // Assign ID detection state for this channel + ids->ch2.state = IdState.ch2.state; + + if(IdState.ch2.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + uint32_t tickDiff = IdState.ch2.timer_2 - IdState.ch2.timer_1; + ids->ch2.id = assign(tickDiff * TICK_FACTOR); + + if(ids->ch2.id) + IdState.ch2.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch2.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + ids->ch2.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch2.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + ids->ch2.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch2.id = 0; + } + + monoflopState = MONOFLOP_INIT; + return true; + break; + default: + break; + } + + return false; +} + +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids) +{ + // ====== EEPROM Check ====== + // EEPROM spec reserves 2 bytes for the ID buffer. + // Currently we only use one byte for IDs, both here in the firmware + // and in the IDE - once we deplete that ID pool, this needs to be extended + // (uint8_t to uint16_t and change EEPROM read to read two bytes instead of one) + uint8_t idBuffer[2]; + // ====== CH1 ====== + if(ids->ch1.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch1)) + { + eeprom_read_array(&SPI.ch1, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch1.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch1.id) + { + ids->ch1.state = ID_STATE_DONE; + IdState.ch1.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH0 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #1 + PORT_PCR_REG(HAL.IOs->pins->ID_CH0.portBase, HAL.IOs->pins->ID_CH0.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + } + + // ====== CH2 ====== + if(ids->ch2.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch2)) + { + eeprom_read_array(&SPI.ch2, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch2.id = idBuffer[0]; + //id was correctly detected via EEPROM + if(ids->ch2.id) + { + ids->ch2.state = ID_STATE_DONE; + IdState.ch2.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH1 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #2 + PORT_PCR_REG(HAL.IOs->pins->ID_CH1.portBase, HAL.IOs->pins->ID_CH1.bit) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + } + + return true; +} diff --git a/TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c b/TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c new file mode 100644 index 0000000..647c2bb --- /dev/null +++ b/TMC2209/lib/tmc/tmc/IdDetection_LandungsbrueckeV3.c @@ -0,0 +1,446 @@ +/******************************************************************************* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * Calling IDDetection_detect(IdAssignmentTypeDef *result) will start the ID detection process. + * The function returns the ID Results through the IdAssignmentTypeDef struct result points to. + * The detection will be done by monoflop pulse duration measurement or via EEPROM readout. + * While this process is still ongoing the function will return ID_STATE_WAIT_HIGH. Once the + * ID detection of both channels has been finished, ID_STATE_DONE will be returned. + * + * Calling the function again after the detection has finished will start another scan. + */ + +#include "IdDetection.h" + +#include "hal/derivative.h" +#include "hal/HAL.h" +#include "BoardAssignment.h" +#include "EEPROM.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "TMCL.h" + +// Helper functions +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids); +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids); + +// Helper macros +#define ID_CLK_LOW() HAL.IOs->config->setLow(&HAL.IOs->pins->ID_CLK) // set id clk signal to low +#define ID_CLK_HIGH() HAL.IOs->config->setHigh(&HAL.IOs->pins->ID_CLK) // set id clk signal to high +#define ID_CLK_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CLK) == IOS_HIGH) // get id clk signal level +#define ID_CH0_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CH0) == IOS_HIGH) // get id signal level for this channel +#define ID_CH1_STATE (HAL.IOs->config->getState(&HAL.IOs->pins->ID_CH1) == IOS_HIGH) // get id signal level for this channel +#define IDSTATE_SCAN_DONE(ID_STATE) \ + ( \ + (ID_STATE.ch1.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_LOW) && \ + (ID_STATE.ch1.state != ID_STATE_WAIT_HIGH) && \ + (ID_STATE.ch2.state != ID_STATE_WAIT_HIGH) \ + ) + +static uint8_t assign(uint32_t pulse); + +typedef enum { + MONOFLOP_INIT, + MONOFLOP_SCANNING, + MONOFLOP_DONE, + + MONOFLOP_END +} State_MonoflopDetection; + +State_MonoflopDetection monoflopState = MONOFLOP_INIT; + +IdAssignmentTypeDef IdState = { 0 }; + +/* pin changed interrupt to detect edges of ID pulse for both channels */ +void PC7_8_IRQHandler(void) +{ + // Abort if the EXTI line isn't set + if((exti_flag_get(EXTI_8) != SET) && (exti_flag_get(EXTI_7) != SET)){ + return; + } + + if(exti_flag_get(EXTI_8) == SET) + { + exti_flag_clear(EXTI_8); + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + if(ID_CH0_STATE) // Capture time of rising edge on ID_CH0 + { + TIMER_SWEVG(TIMER1) |= TIMER_SWEVG_CH0G; + IdState.ch1.state = ID_STATE_WAIT_HIGH; + } + else // Capture time of falling edge on ID_CH0 + { + TIMER_SWEVG(TIMER1) |= TIMER_SWEVG_CH1G; + IdState.ch1.state = ID_STATE_DONE; + } + } + else if(exti_flag_get(EXTI_7) == SET) + { + exti_flag_clear(EXTI_7); + + // Abort if we're not scanning + if(monoflopState != MONOFLOP_SCANNING) + return; + + if(ID_CH1_STATE) // Capture time of rising edge on ID_CH1 + { + TIMER_SWEVG(TIMER1) = TIMER_SWEVG_CH2G; + IdState.ch2.state = ID_STATE_WAIT_HIGH; + } + else // Capture time of falling edge on ID_CH1 + { + TIMER_SWEVG(TIMER1) = TIMER_SWEVG_CH3G; + IdState.ch2.state = ID_STATE_DONE; + } + } + + + +} + +void __attribute__ ((interrupt)) EXTI5_9_IRQHandler(void) +{ + + if(GET_BITS(SYSCFG_EXTISS2,0,3) == 3){ + PD8_IRQHandler(); // For TMC6140-eval diagnostics + } + else if(GET_BITS(SYSCFG_EXTISS2,0,3) == 2 || GET_BITS(SYSCFG_EXTISS1,12,15) == 2){ + PC7_8_IRQHandler(); // For idDetection + } +} + +/* timer interrupt to determine timeout on ID detection (missing boards, errors) */ +void TIMER1_IRQHandler(void) +{ + // Abort if the interrupt isn't set + if(timer_flag_get(TIMER1, TIMER_FLAG_UP) != SET) + return; + + timer_flag_clear(TIMER1, TIMER_FLAG_UP); + + if(monoflopState == MONOFLOP_SCANNING) + { + monoflopState = MONOFLOP_DONE; + return; + } +} + +/* Initialise timer and GPIO edge-triggered interrupts */ +void IDDetection_init(void) +{ + monoflopState = MONOFLOP_INIT; + + // ====== Pin initialisation ====== + // Pin ID_CLK + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CLK); + + // Pin ID_CH0 + gpio_mode_set(HAL.IOs->pins->ID_CH0.port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, HAL.IOs->pins->ID_CH0.bitWeight); + + + syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN8); + + exti_init(EXTI_8, EXTI_INTERRUPT, EXTI_TRIG_BOTH); + nvic_irq_enable(EXTI5_9_IRQn, 0, 1); + exti_interrupt_flag_clear(EXTI_8); + + // Pin ID_CH1 + gpio_mode_set(HAL.IOs->pins->ID_CH1.port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, HAL.IOs->pins->ID_CH1.bitWeight); + syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN7); + + exti_init(EXTI_7, EXTI_INTERRUPT, EXTI_TRIG_BOTH); + nvic_irq_enable(EXTI5_9_IRQn, 0, 1); + exti_interrupt_flag_clear(EXTI_7); + + // ====== Timer initialisation + + /* Timer Frequency: + * CLK_TIMER 120MHz + * ----------- = ----- = 10MHz = 0.1us <= COUNTER_CLK + * Prescaler 12 + * + */ + + rcu_periph_clock_enable(RCU_TIMER1); + rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL2); // CK_TIMER1 = 2 x CK_APB1 + timer_internal_clock_config(TIMER1); + timer_deinit(TIMER1); + + timer_counter_value_config(TIMER1, 0); + + + + timer_ic_parameter_struct *icpara_rising; + timer_ic_parameter_struct *icpara_falling; + + icpara_rising->icpolarity = TIMER_IC_POLARITY_RISING; + icpara_rising->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara_rising->icprescaler = TIMER_IC_PSC_DIV1; + icpara_rising->icfilter = 0U; + + icpara_falling->icpolarity = TIMER_IC_POLARITY_FALLING; + icpara_falling->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara_falling->icprescaler = TIMER_IC_PSC_DIV1; + icpara_falling->icfilter = 0U; + + timer_input_capture_config(TIMER1, TIMER_CH_0, icpara_rising); + timer_input_capture_config(TIMER1, TIMER_CH_1, icpara_falling); + timer_input_capture_config(TIMER1, TIMER_CH_2, icpara_rising); + timer_input_capture_config(TIMER1, TIMER_CH_3, icpara_falling); + + // Setting the prescaler i.e 11 + timer_prescaler_config(TIMER1, 11, TIMER_PSC_RELOAD_NOW); // Divides the timer freq by (prescaler + 1) + + timer_autoreload_value_config(TIMER1,100000); // timeout -> 10ms --TIM auto-reload register + + + timer_update_event_enable(TIMER1); + TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG; //generate update event + + timer_interrupt_enable(TIMER1, TIMER_INT_UP); + + // Enable timer interrupt + nvic_irq_enable(TIMER1_IRQn, 0xF, 0xF); + + +} + +void IDDetection_deInit() +{ + + nvic_irq_disable(TIMER1_IRQn); + nvic_irq_disable(EXTI5_9_IRQn); + timer_deinit(TIMER1); + exti_deinit(); +} + +// Returns ID assigned to given pulse (length in 0.1us) +static uint8_t assign(uint32_t pulse) +{ + if( pulse < 5) return 0; // error + else if(pulse < 110) return 1; + else if(pulse < 135) return 2; + else if(pulse < 165) return 3; + else if(pulse < 200) return 4; + else if(pulse < 245) return 5; + else if(pulse < 300) return 6; + else if(pulse < 360) return 7; + else if(pulse < 430) return 8; + else if(pulse < 515) return 9; + else if(pulse < 620) return 10; + else if(pulse < 750) return 11; + else if(pulse < 910) return 12; + else if(pulse < 1100) return 13; + else if(pulse < 1350) return 14; + else if(pulse < 1650) return 15; + else if(pulse < 2000) return 16; + else if(pulse < 2450) return 17; + else if(pulse < 3000) return 18; + else if(pulse < 3600) return 19; + else if(pulse < 4300) return 20; + else if(pulse < 5150) return 21; + else if(pulse < 6200) return 22; + else if(pulse < 7500) return 23; + else if(pulse < 9100) return 24; + else if(pulse < 11000) return 25; + else if(pulse < 13500) return 26; + else if(pulse < 16500) return 27; + else if(pulse < 20000) return 28; + else if(pulse < 24500) return 29; + else if(pulse < 30000) return 30; + else if(pulse < 36000) return 31; + else if(pulse < 43000) return 32; + else if(pulse < 51500) return 33; + else if(pulse < 62000) return 34; + else if(pulse < 75000) return 35; + else if(pulse < 91000) return 36; + + return 0; // error +} + +// Detect IDs of attached boards - returns true when done +uint8_t IDDetection_detect(IdAssignmentTypeDef *ids) +{ + // Change the exti source back to PC8 (It could be changed by TMC6140-eval to PD8) +// syscfg_exti_line_config(EXTI_SOURCE_GPIOC, EXTI_SOURCE_PIN8); + + // Try to identify the IDs via monoflop pulse duration + if (!detectID_Monoflop(ids)) + return false; + + // Try to identify the IDs via EEPROM readout + detectID_EEPROM(ids); + + // Detection finished + return true; + +} + +void IDDetection_initialScan(IdAssignmentTypeDef *ids) +{ + while(!IDDetection_detect(ids)) + { + vitalsignsmonitor_checkVitalSigns(); + tmcl_process(); + } + +} + +static int32_t detectID_Monoflop(IdAssignmentTypeDef *ids) +{ + switch(monoflopState) + { + case MONOFLOP_INIT: + timer_disable(TIMER1); // stop the timer + timer_counter_value_config(TIMER1, 0); // clear counter + + IdState.ch1.state = ID_STATE_WAIT_LOW; + IdState.ch1.detectedBy = FOUND_BY_NONE; + IdState.ch2.state = ID_STATE_WAIT_LOW; + IdState.ch2.detectedBy = FOUND_BY_NONE; + + // Update the monoflop state before activating the timer. Otherwise bad + // luck with other unrelated interrupts might cause enough delay to + // trigger the timer overflow after starting the timer before updating + // this state - which results in the timeout no longer working. + monoflopState = MONOFLOP_SCANNING; + + timer_enable(TIMER1); // start timer + ID_CLK_HIGH(); + break; + case MONOFLOP_SCANNING: + if (IDSTATE_SCAN_DONE(IdState)) + { + monoflopState = MONOFLOP_DONE; + } + break; + case MONOFLOP_DONE: + // Scan complete, disable ID_CLK and the timer + ID_CLK_LOW(); + timer_disable(TIMER1); + + // ======== CH1 ========== + // Assign ID detection state for this channel + ids->ch1.state = IdState.ch1.state; + + if(IdState.ch1.state == ID_STATE_DONE) + { + uint32_t pulse=timer_channel_capture_value_register_read(TIMER1, TIMER_CH_1) - timer_channel_capture_value_register_read(TIMER1, TIMER_CH_0); + + // Assign the ID derived from the ID pulse duration + ids->ch1.id = assign(pulse); + + + if(ids->ch1.id) + IdState.ch1.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch1.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch1.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + IdState.ch1.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch1.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + IdState.ch1.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch1.id = 0; + } + + + + // ======== CH2 ========== + // Assign ID detection state for this channel + ids->ch2.state = IdState.ch2.state; + + if(IdState.ch2.state == ID_STATE_DONE) + { + // Assign the ID derived from the ID pulse duration + ids->ch2.id = assign(timer_channel_capture_value_register_read(TIMER1, TIMER_CH_3) - timer_channel_capture_value_register_read(TIMER1, TIMER_CH_2)); + + if(ids->ch2.id) + IdState.ch2.detectedBy = FOUND_BY_MONOFLOP; + else + ids->ch2.state = ID_STATE_INVALID; // Invalid ID pulse detected + } + else if(IdState.ch2.state == ID_STATE_WAIT_HIGH) + { // Only detected ID pulse rising edge -> Timeout + IdState.ch2.state = ID_STATE_TIMEOUT; + } + else if(IdState.ch2.state == ID_STATE_WAIT_LOW) + { // Did not detect any edge -> No answer + IdState.ch2.state = ID_STATE_NO_ANSWER; + } + else + { + ids->ch2.id = 0; + } + + monoflopState = MONOFLOP_INIT; + return true; + break; + default: + break; + } + + return false; +} + +static int32_t detectID_EEPROM(IdAssignmentTypeDef *ids) +{ + // ====== EEPROM Check ====== + // EEPROM spec reserves 2 bytes for the ID buffer. + // Currently we only use one byte for IDs, both here in the firmware + // and in the IDE - once we deplete that ID pool, this needs to be extended + // (uint8_t to uint16_t and change EEPROM read to read two bytes instead of one) + uint8_t idBuffer[2]; + // ====== CH1 ====== + if(ids->ch1.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch1)) + { + eeprom_read_array(&SPI.ch1, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch1.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch1.id) + { + ids->ch1.state = ID_STATE_DONE; + IdState.ch1.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH0 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #3 + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CH0); + } + + // ====== CH2 ====== + if(ids->ch2.state != ID_STATE_DONE) + { + // EEPROM is not ready -> assume it is not connected -> skip EEPROM ID read + if(!eeprom_check(&SPI.ch2)) + { + eeprom_read_array(&SPI.ch2, EEPROM_ADDR_ID, &idBuffer[0], 1); + ids->ch2.id = idBuffer[0]; + // ID was correctly detected via EEPROM + if(ids->ch2.id) + { + ids->ch2.state = ID_STATE_DONE; + IdState.ch2.detectedBy = FOUND_BY_EEPROM; + } + } + // EEPROM access changes the ID_CH1 pin configuration -> write it again // todo CHECK 2: workaround, do this better later (LH) #4 + HAL.IOs->config->toOutput(&HAL.IOs->pins->ID_CH1); + } + + return true; +} diff --git a/TMC2209/lib/tmc/tmc/RAMDebug.c b/TMC2209/lib/tmc/tmc/RAMDebug.c new file mode 100644 index 0000000..427a229 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/RAMDebug.c @@ -0,0 +1,631 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "RAMDebug.h" + +#include "boards/Board.h" +#include "hal/SysTick.h" +#include "hal/HAL.h" + +#include + +// === RAM debugging =========================================================== + +// Debug parameters +#define RAMDEBUG_MAX_CHANNELS 4 +#define RAMDEBUG_BUFFER_SIZE 32768 +#define RAMDEBUG_BUFFER_ELEMENTS (RAMDEBUG_BUFFER_SIZE / 4) + +bool captureEnabled = false; + +// Sample Buffer +uint32_t debug_buffer[RAMDEBUG_BUFFER_ELEMENTS] = { 0 }; +uint32_t debug_write_index = 0; +uint32_t debug_read_index = 0; +uint32_t pre_index = 0; + +RAMDebugState state = RAMDEBUG_IDLE; + +static bool global_enable = false; +static bool processing = false; +static bool use_next_process = true; +static bool next_process = false; + +// Sampling options +static uint32_t prescaler = 1; +static uint32_t frequency = RAMDEBUG_FREQUENCY; +static uint32_t sampleCount = RAMDEBUG_BUFFER_ELEMENTS; +static uint32_t sampleCountPre = 0; + +typedef struct { + RAMDebugSource type; + uint8_t eval_channel; + uint32_t address; +} Channel; + +Channel channels[RAMDEBUG_MAX_CHANNELS]; + +typedef struct { + Channel channel; + RAMDebugTrigger type; + uint32_t threshold; + uint32_t mask; + uint8_t shift; +} Trigger; + +Trigger trigger; + +// Store whether the last sampling point was above or below the trigger threshold +static bool wasAboveSigned = 0; +static bool wasAboveUnsigned = 0; + +// Function declarations +static uint32_t readChannel(Channel channel); + +// === Capture and trigger logic =============================================== + +// This function only gets called by the interrupt handler. +void handleTriggering() +{ + // Abort if not in the right state + if (state != RAMDEBUG_TRIGGER) + return; + + // Read the trigger channel value and apply mask/shift values + uint32_t value_raw = readChannel(trigger.channel); + value_raw = (value_raw & trigger.mask) >> trigger.shift; + + // Create a signed version of the trigger value + int32_t value = value_raw; + // Create a mask with only the highest bit of the trigger channel mask set + uint32_t msbMask = (trigger.mask>>trigger.shift) ^ (trigger.mask>>(trigger.shift+1)); + // Check if our value has that bit set. + if (value_raw & msbMask) + { + // If yes, sign-extend it + value |= ~(trigger.mask>>trigger.shift); + } + + bool isAboveSigned = value > (int32_t) trigger.threshold; + bool isAboveUnsigned = value_raw > (uint32_t) trigger.threshold; + + switch(trigger.type) + { + case TRIGGER_UNCONDITIONAL: + state = RAMDEBUG_CAPTURE; + break; + case TRIGGER_RISING_EDGE_SIGNED: + if (!wasAboveSigned && isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_FALLING_EDGE_SIGNED: + if (wasAboveSigned && !isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_DUAL_EDGE_SIGNED: + if (wasAboveSigned != isAboveSigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_RISING_EDGE_UNSIGNED: + if (!wasAboveUnsigned && isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_FALLING_EDGE_UNSIGNED: + if (wasAboveUnsigned && !isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + case TRIGGER_DUAL_EDGE_UNSIGNED: + if (wasAboveUnsigned != isAboveUnsigned) + { + state = RAMDEBUG_CAPTURE; + } + break; + default: + break; + } + + // Store the last threshold comparison value + wasAboveSigned = isAboveSigned; + wasAboveUnsigned = isAboveUnsigned; +} + +// This function only gets called by the interrupt handler. +void handleDebugging() +{ + int32_t i; + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type == CAPTURE_DISABLED) + continue; + + if(state == RAMDEBUG_CAPTURE) + { + // Add the sample value to the buffer + debug_buffer[debug_write_index++] = readChannel(channels[i]); + + if (debug_write_index >= sampleCount) + { + // End the capture + state = RAMDEBUG_COMPLETE; + captureEnabled = false; + break; + } + } + else if((state != RAMDEBUG_COMPLETE) && (sampleCountPre > 0)) + { + debug_buffer[pre_index] = readChannel(channels[i]); + pre_index = (pre_index + 1) % sampleCountPre; + } + } +} + +void debug_process() +{ + static uint32_t prescalerCount = 0; + + if(!global_enable) + return; + + if(processing) + return; + + if(use_next_process && (!next_process)) + return; + + next_process = false; + + if (captureEnabled == false) + return; + + handleTriggering(); + + // Increment and check the prescaler counter + if (++prescalerCount < prescaler) + return; + + processing = true; + + // Reset the prescaler counter + prescalerCount = 0; + + handleDebugging(); + processing = false; +} + +static inline uint32_t readChannel(Channel channel) +{ + uint32_t sample = 0; + + switch (channel.type) + { + case CAPTURE_PARAMETER: + { + uint8_t motor = (channel.address >> 24) & 0xFF; + uint8_t type = (channel.address >> 0) & 0xFF; + + ((channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1))->GAP(type, motor, (int32_t *)&sample); + + break; + } + case CAPTURE_REGISTER: + { + uint8_t motor = channel.address >> 24; + + ((channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1))->readRegister(motor, channel.address, (int32_t *)&sample); + + break; + } + case CAPTURE_STACKED_REGISTER: + { + uint8_t motor = channel.address >> 24; + uint8_t stackedRegisterValue = channel.address >> 16; + uint8_t stackedRegisterAddress = channel.address >> 8; + uint8_t dataRegisterAddress = channel.address >> 0; + + EvalboardFunctionsTypeDef *ch = (channel.eval_channel == 1) ? (&Evalboards.ch2) : (&Evalboards.ch1); + + // Backup the stacked address + uint32_t oldAddress = 0; + ch->readRegister(motor, stackedRegisterAddress, (int32_t *)&oldAddress); + + // Write the new stacked address + ch->writeRegister(motor, stackedRegisterAddress, stackedRegisterValue); + + // Read the stacked data register + ch->readRegister(motor, dataRegisterAddress, (int32_t *)&sample); + + // Restore the stacked address + ch->writeRegister(motor, stackedRegisterAddress, oldAddress); + break; + } + case CAPTURE_SYSTICK: + sample = systick_getTick();//systick_getTimer10ms(); + break; + case CAPTURE_ANALOG_INPUT: + // Use same indices as in TMCL.c GetInput() + switch(channel.address) { + case 0: + sample = *HAL.ADCs->AIN0; + break; + case 1: + sample = *HAL.ADCs->AIN1; + break; + case 2: + sample = *HAL.ADCs->AIN2; + break; + case 3: + sample = *HAL.ADCs->DIO4; + break; + case 4: + sample = *HAL.ADCs->DIO5; + break; + case 6: + sample = *HAL.ADCs->VM; + break; + } + break; + default: + sample = 0; + break; + } + + return sample; +} + +// === Interfacing with the debugger =========================================== +void debug_init() +{ + int32_t i; + + // Disable data capture before changing the configuration + captureEnabled = false; + + // Reset the RAMDebug state + state = RAMDEBUG_IDLE; + + // Wipe the RAM debug buffer + for (i = 0; i < RAMDEBUG_BUFFER_ELEMENTS; i++) + { + debug_buffer[i] = 0; + } + debug_read_index = 0; + debug_write_index = 0; + + // Set default values for the capture configuration + prescaler = 1; + sampleCount = RAMDEBUG_BUFFER_ELEMENTS; + sampleCountPre = 0; + + // Reset the channel configuration + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + channels[i].type = CAPTURE_DISABLED; + channels[i].eval_channel = 0; + channels[i].address = 0; + } + + // Reset the trigger + trigger.channel.type = CAPTURE_DISABLED; + trigger.channel.address = 0; + trigger.mask = 0xFFFFFFFF; + trigger.shift = 0; + + global_enable = true; +} + +bool debug_setChannel(uint8_t type, uint32_t channel_value) +{ + return ( + debug_setEvalChannel((channel_value >> 16) & 0x01) && + debug_setAddress(channel_value) && + debug_setType(type) + ); +} + +bool debug_setTriggerChannel(uint8_t type, uint32_t channel_value) +{ + return ( + debug_setTriggerType(type) && + debug_setTriggerEvalChannel((channel_value >> 16) & 0x01) && + debug_setTriggerAddress(channel_value) + ); +} + +bool debug_setType(uint8_t type) +{ + int32_t i; + + if (type >= CAPTURE_END) + return false; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].type = type; + + return true; + } + + return false; +} + +bool debug_setEvalChannel(uint8_t eval_channel) +{ + int32_t i; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].eval_channel = eval_channel; + + return true; + } + + return false; +} + +bool debug_setAddress(uint32_t address) +{ + int32_t i; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + for (i = 0; i < RAMDEBUG_MAX_CHANNELS; i++) + { + if (channels[i].type != CAPTURE_DISABLED) + continue; + + // Add the configuration to the found channel + channels[i].address = address; + + return true; + } + + return false; +} + +int32_t debug_getChannelType(uint8_t index, uint8_t *type) +{ + if (index == 0xFF) + { + *type = trigger.channel.type; + return 1; + } + + if (index >= RAMDEBUG_MAX_CHANNELS) + return 0; + + *type = channels[index].type; + + return 1; +} + +int32_t debug_getChannelAddress(uint8_t index, uint32_t *address) +{ + if (index == 0xFF) + { + *address = trigger.channel.address; + return 1; + } + + if (index >= RAMDEBUG_MAX_CHANNELS) + return 0; + + *address = channels[index].address; + + return 1; +} + +bool debug_setTriggerType(uint8_t type) +{ + if (type >= CAPTURE_END) + return false; + + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.type = type; + + return true; +} + +bool debug_setTriggerEvalChannel(uint8_t eval_channel) +{ + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.eval_channel = eval_channel; + + return true; +} + +bool debug_setTriggerAddress(uint32_t address) +{ + if (state != RAMDEBUG_IDLE) + return false; + + // ToDo: Type-specific address verification logic? + + // Store the trigger configuration + trigger.channel.address = address; + + return true; +} + +void debug_setTriggerMaskShift(uint32_t mask, uint8_t shift) +{ + trigger.mask = mask; + trigger.shift = shift; +} + +int32_t debug_enableTrigger(uint8_t type, uint32_t threshold) +{ + // Parameter validation + if (type >= TRIGGER_END) + return 0; + + if (state != RAMDEBUG_IDLE) + return 0; + + // Do not allow the edge triggers with channel still missing + if (type != TRIGGER_UNCONDITIONAL && trigger.channel.type == CAPTURE_DISABLED) + return 0; + + // Store the trigger configuration + trigger.type = type; + trigger.threshold = threshold; + + // Initialize the trigger helper variable + // Read out the trigger value and apply the mask/shift + int32_t triggerValue = (readChannel(trigger.channel) & trigger.mask) >> trigger.shift; + wasAboveSigned = (int32_t) triggerValue > (int32_t) trigger.threshold; + wasAboveUnsigned = (uint32_t) triggerValue > (uint32_t) trigger.threshold; + + // Enable the trigger + state = RAMDEBUG_TRIGGER; + + // Enable the capturing IRQ + captureEnabled = true; + + return 1; +} + +void debug_setPrescaler(uint32_t divider) +{ + prescaler = divider; +} + +void debug_setSampleCount(uint32_t count) +{ + if (count > RAMDEBUG_BUFFER_ELEMENTS) + count = RAMDEBUG_BUFFER_ELEMENTS; + + sampleCount = count; +} + +uint32_t debug_getSampleCount() +{ + return sampleCount; +} + +void debug_setPretriggerSampleCount(uint32_t count) +{ + if (count > sampleCount) + count = sampleCount; + + sampleCountPre = count; + debug_write_index = count; +} + +uint32_t debug_getPretriggerSampleCount() +{ + return sampleCountPre; +} + +int32_t debug_getSample(uint32_t index, uint32_t *value) +{ + if (index >= debug_write_index) + return 0; + + if(index < sampleCountPre) + { + *value = debug_buffer[(pre_index + index) % sampleCountPre]; + } + else + { + *value = debug_buffer[index]; + } + + return 1; +} + +void debug_updateFrequency(uint32_t freq) +{ + frequency = freq; +} + +int32_t debug_getState(void) +{ + return state; +} + +int32_t debug_getInfo(uint32_t type) +{ + switch(type) + { + case 0: + return RAMDEBUG_MAX_CHANNELS; + break; + case 1: + return RAMDEBUG_BUFFER_ELEMENTS; + break; + case 2: + // PWM/Sampling Frequency + return frequency; // RAMDEBUG_FREQUENCY; + break; + case 3: + return debug_write_index; + break; + default: + break; + } + + return -1; +} + +void debug_useNextProcess(bool enable) +{ + use_next_process = enable; +} + +void debug_nextProcess(void) +{ + next_process = true; +} + +void debug_setGlobalEnable(bool enable) +{ + global_enable = enable; +} diff --git a/TMC2209/lib/tmc/tmc/RAMDebug.h b/TMC2209/lib/tmc/tmc/RAMDebug.h new file mode 100644 index 0000000..792be99 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/RAMDebug.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* Copyright © 2020 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef RAMDEBUG_H +#define RAMDEBUG_H + +#include +#include + +#define RAMDEBUG_FREQUENCY 1000/*0*/ + +// Capture state +typedef enum { + RAMDEBUG_IDLE = 0, + RAMDEBUG_TRIGGER = 1, + RAMDEBUG_CAPTURE = 2, + RAMDEBUG_COMPLETE = 3 +} RAMDebugState; + +// Capture channel configuration +typedef enum { + CAPTURE_DISABLED = 0, + + CAPTURE_PARAMETER = 1, + CAPTURE_REGISTER = 2, + CAPTURE_STACKED_REGISTER = 3, + CAPTURE_SYSTICK = 4, + CAPTURE_RAMDEBUG_PARAMETER = 5, // For modules that do not support registers + CAPTURE_ANALOG_INPUT = 6, + + CAPTURE_END +} RAMDebugSource; + +// Trigger configuration +typedef enum { + TRIGGER_UNCONDITIONAL = 0, + TRIGGER_RISING_EDGE_SIGNED = 1, + TRIGGER_FALLING_EDGE_SIGNED = 2, + TRIGGER_DUAL_EDGE_SIGNED = 3, + TRIGGER_RISING_EDGE_UNSIGNED = 4, + TRIGGER_FALLING_EDGE_UNSIGNED = 5, + TRIGGER_DUAL_EDGE_UNSIGNED = 6, + + TRIGGER_END +} RAMDebugTrigger; + +void debug_init(); +void debug_process(); +bool debug_setChannel(uint8_t type, uint32_t channel_value); +bool debug_setTriggerChannel(uint8_t type, uint32_t channel_value); +bool debug_setType(uint8_t type); +bool debug_setEvalChannel(uint8_t eval_channel); +bool debug_setAddress(uint32_t address); +int32_t debug_getChannelType(uint8_t index, uint8_t *type); +int32_t debug_getChannelAddress(uint8_t index, uint32_t *address); + +bool debug_setTriggerType(uint8_t type); +bool debug_setTriggerEvalChannel(uint8_t eval_channel); +bool debug_setTriggerAddress(uint32_t address); +void debug_setTriggerMaskShift(uint32_t mask, uint8_t shift); +int32_t debug_enableTrigger(uint8_t type, uint32_t threshold); + +void debug_setPrescaler(uint32_t divider); +void debug_setSampleCount(uint32_t count); +uint32_t debug_getSampleCount(); +void debug_setPretriggerSampleCount(uint32_t count); +uint32_t debug_getPretriggerSampleCount(); + +int32_t debug_getSample(uint32_t index, uint32_t *value); +void debug_updateFrequency(uint32_t freq); +int32_t debug_getState(void); +int32_t debug_getInfo(uint32_t type); + +void debug_useNextProcess(bool enable); +void debug_nextProcess(void); +void debug_setGlobalEnable(bool enable); + +#endif /* RAMDEBUG_H */ diff --git a/TMC2209/lib/tmc/tmc/StepDir.c b/TMC2209/lib/tmc/tmc/StepDir.c new file mode 100644 index 0000000..a85cc4d --- /dev/null +++ b/TMC2209/lib/tmc/tmc/StepDir.c @@ -0,0 +1,763 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + +/* + * StepDir.c + * + * This is a basic implementation of a StepDir generator, capable of generating + * velocity (reaching a target velocity with linear acceleration) and position + * (reach a target position with linear acc-/decceleration and a maximum velocity) + * ramps. + * + * ***** HOW IT WORKS ***** + * + * General: + * A high frequency (2^17 Hz) Interrupt calculates acceleration, velocity and + * position. Position and velocity are calculated with 17 binary decimal places + * of precision. + * + * Velocity mode: + * In velocity mode, the generator will accelerate towards a target velocity. + * Acceleration and velocity can be changed at any point of the ramp. The position + * is tracked and resettable (useful for setting a reference point via a switch). + * + * Position mode: + * In position mode, a linearly accelerated ramp is used to reach the position. + * Parameters for the ramp are acceleration and maximum velocity. The generator + * will always increase the velocity towards the maximum velocity until the + * remaining distance to the target is required for the deceleration ramp. + * Acceleration, maximum velocity and target position can all be changed during + * the ramp. Note that decreasing acceleration or changing target position may + * lead to overshooting the target. In that case the generator will start a new + * ramp to the target, while always staying within the bounds of acceleration and + * velocity. + * + * Due to imprecision in the deceleration distance calculations, a small tolerance + * window is used, where the motor will set the velocity to zero if the velocity is + * small enough and the position is reached (V_STOP). If the position is barely + * missed (HOMING_DISTANCE) and the velocity is zero, the generator will home in + * towards the target position at a low velocity (V_STOP). + * Changing the actual position value is not possible while in position mode + * the generator is not idle (target position reached, velocity zero). + * Changing the acceleration to zero is not possible in position mode. + * Acceleration value changes require a recalculation of the braking distance. + * This can result in more frequent near-misses of the target position, which the + * generator will compensate with starting new ramps or homing in (see above). + * + * If overshooting the target by any step is not permitted, it is recommended to + * drive to the target without changing parameters during the ramp. Alternatively, + * driving to a point shortly before the actual target point and then starting + * another small ramp allows for parameter changes during the first ramp, only + * requiring a small distance drive with 'locked' parameters. + * + * Overshooting from calculation errors is mostly limited to single digit + * position differences. Decreasing acceleration or moving the target position + * towards the actual position might result in bigger misses of the target. + * + * StallGuard: + * The StepDir generator supports the StallGuard feature, either by a input pin + * signal or with external monitoring. The function periodicJob() will check, + * whether the velocity is above the set StallGuard threshold velocity, set a + * status flag (usable for external StallGuard monitoring) and - if present - + * check the input pin for indicated stalls. + * Make sure that periodicJob() is called frequently to allow quick stall + * detection. The function can also be called by an interrupt to guarantee + * quick detection [1]. The interrupt should have a lower priority than the + * Step-Generator interrupt. + * + * When using external monitoring, for example by checking a chip register, + * you can use the STATUS_STALLGUARD_ACTIVE bit of getStatus() to see if + * StallGuard is active. In case of a stall, calling stop(STOP_STALL) will + * trigger the stall mechanism, shutting down the generator without loosing + * further steps. + * Clearing a stall condition is done by setting the stall velocity threshold + * to any value. + * Position mode will start a new ramp towards the target after a stall. + * + * Emergency Stop: + * The stop function implements an emergency stop. This will result in the + * channel immediately stopping any movements. No parameters are updated to + * allow for diagnostics. The only way to clear the emergency stop event is + * to init() the StepDir generator again [2]. + * + * ***** LIMITATIONS ***** + * + * The frequency of the StepDir generator is limited by the processor. On the + * Landungsbrücke, the worst case of two motors/channels (TMC2041) is able to + * still run at 2^17 Hz. Since the bulk of the calculation is per-motor/channel, + * using a chip with only one motor/channel would allow a frequency of 2^18 Hz. + * (Note that quite a few calculations have to divide by the frequency, so + * choosing a power of two simplifies those to right-shifts.) + * + * The limit on Step pulses is one generated pulse per interrupt. + * The maximum velocity therefore is equal to the interrupt frequency: + * Max Velocity: 2^17 pps = 131072 pps + * + * Each tick the acceleration value gets added to the velocity accumulator + * variable (uint32_t). The upper 15 digits are added to the velocity, the lower + * 17 digits are kept in the accumulator between ticks. The maximum + * acceleration will result in the upper 15 digits being 1 each tick, increasing + * the velocity by 32767 (0x7FFF) per tick. The accumulator digits stay unchanged, + * otherwise the overflow of the lower 17 accumulator digits into the upper 15 + * digits would cause the uint32_t to overflow, loosing an acceleration tick. + * In other words: The upper 15 digits are 1, the lower 17 digits are 0: + * Max Acceleration: 0xFFFE0000 = 4294836224 pps^2 + * + * A change from lowest to highest (or vice-versa) velocity would take 9 ticks at + * maximum acceleration: + * ceil( (VMAX- (-VMAX)) / AMAX) = ceil(8,000244) = 9 + * + * ***** Side notes ****** + * [1]: Technically periodicJob() is not interrupt-safe, since it updates the + * haltingCondition bitfield. Read-Modify-Write cycles of the main code + * could result in the changes of interrupts to the bitfield to be lost. + * In practice, the interrupt should just rewrite the stall bit on the next + * check though due to the nature of StallGuard. + * [2]: Emergency stop does not have a graceful recovery method by design. + * Clearing the emergency stop via init() will result in all channels + * being reset. + */ + +#include "StepDir.h" +#include "hal/derivative.h" + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define TIMER_INTERRUPT FTM1_IRQHandler +#elif defined(LandungsbrueckeV3) + #define TIMER_INTERRUPT TIMER2_IRQHandler +#endif + +#define STEP_DIR_CHANNELS 2 + +// Reset value for stallguard threshold. Since Stallguard is motor/application-specific we can't choose a good value here, +// so this value is rather randomly chosen. Leaving it at zero means stall detection turned off. +#define STALLGUARD_THRESHOLD 0 + +StepDirectionTypedef StepDir[STEP_DIR_CHANNELS]; + +IOPinTypeDef DummyPin = { .bitWeight = DUMMY_BITWEIGHT }; + +// Helper functions +static int32_t calculateStepDifference(int32_t velocity, uint32_t oldAccel, uint32_t newAccel); +// These helper functions are for optimizing the interrupt without duplicating +// logic for both interrupt and main loop. We save time in them by omitting +// safety checks needed only for the main loop in these functions. +// The main loop then uses functions that wrap these functions together with the +// necessary safety checks. +static inline void checkStallguard(StepDirectionTypedef *channel, bool stallSignalActive); +static inline void stop(StepDirectionTypedef *channel, StepDirStop stopType); + +void TIMER_INTERRUPT() +{ +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + FTM1_SC &= ~FTM_SC_TOF_MASK; // clear timer overflow flag +#elif defined(LandungsbrueckeV3) + if(timer_interrupt_flag_get(TIMER2, TIMER_INT_FLAG_UP) == RESET) + return; + timer_interrupt_flag_clear(TIMER2, TIMER_INT_FLAG_UP); +#endif + + for (uint8_t ch = 0; ch < STEP_DIR_CHANNELS; ch++) + { + // Temporary variable for the current channel + StepDirectionTypedef *currCh = &StepDir[ch]; + + // If any halting condition is present, abort immediately + if (currCh->haltingCondition) + continue; + + // Reset step output (falling edge of last pulse) + + //*currCh->stepPin->resetBitRegister = currCh->stepPin->bitWeight; + HAL.IOs->config->setLow(currCh->stepPin); + + // Check if StallGuard pin is high + // Note: If no stall pin is registered, isStallSignalHigh becomes FALSE + // and checkStallguard won't do anything. +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + bool isStallSignalHigh = (GPIO_PDIR_REG(currCh->stallGuardPin->GPIOBase) & currCh->stallGuardPin->bitWeight) != 0; +#elif defined(LandungsbrueckeV3) + bool isStallSignalHigh = HAL.IOs->config->isHigh(currCh->stallGuardPin); +#endif + checkStallguard(currCh, isStallSignalHigh); + + // Compute ramp + int32_t dx = tmc_ramp_linear_compute(&currCh->ramp); + + // Step + if (dx == 0) // No change in position -> skip step generation + goto skipStep; + + // Direction + *((dx > 0) ? currCh->dirPin->resetBitRegister : currCh->dirPin->setBitRegister) = currCh->dirPin->bitWeight; + + // Set step output (rising edge of step pulse) + *currCh->stepPin->setBitRegister = currCh->stepPin->bitWeight; + +skipStep: + // Synchronised Acceleration update + switch(currCh->syncFlag) + { + case SYNC_SNAPSHOT_REQUESTED: + // Apply the new acceleration + tmc_ramp_linear_set_acceleration(&currCh->ramp, currCh->newAcceleration); + // Save a snapshot of the velocity + currCh->oldVelocity = tmc_ramp_linear_get_rampVelocity(&currCh->ramp); + + currCh->syncFlag = SYNC_SNAPSHOT_SAVED; + break; + case SYNC_UPDATE_DATA: + currCh->ramp.accelerationSteps += currCh->stepDifference; + currCh->syncFlag = SYNC_IDLE; + break; + default: + break; + } + } +} + +void StepDir_rotate(uint8_t channel, int32_t velocity) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + // Set the rampmode first - other way around might cause issues + tmc_ramp_linear_set_mode(&StepDir[channel].ramp, TMC_RAMP_LINEAR_MODE_VELOCITY); + switch(StepDir[channel].mode) { + case STEPDIR_INTERNAL: + tmc_ramp_linear_set_targetVelocity(&StepDir[channel].ramp, MIN(STEPDIR_MAX_VELOCITY, velocity)); + break; + case STEPDIR_EXTERNAL: + default: + tmc_ramp_linear_set_targetVelocity(&StepDir[channel].ramp, velocity); + break; + } +} + +void StepDir_moveTo(uint8_t channel, int32_t position) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_mode(&StepDir[channel].ramp, TMC_RAMP_LINEAR_MODE_POSITION); + tmc_ramp_linear_set_targetPosition(&StepDir[channel].ramp, position); +} + +void StepDir_periodicJob(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + // Check stallguard velocity threshold + if ((StepDir[channel].stallGuardThreshold != 0) && (abs(tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp)) >= StepDir[channel].stallGuardThreshold)) + { + StepDir[channel].stallGuardActive = true; + } + else + { + StepDir[channel].stallGuardActive = false; + } +} + +void StepDir_stop(uint8_t channel, StepDirStop stopType) +{ + stop(&StepDir[channel], stopType); +} + +uint8_t StepDir_getStatus(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + uint8_t status = StepDir[channel].haltingCondition; + + int32_t targetPosition = tmc_ramp_linear_get_targetPosition(&StepDir[channel].ramp); + int32_t actualPosition = tmc_ramp_linear_get_rampPosition(&StepDir[channel].ramp); + + status |= (targetPosition == actualPosition) ? STATUS_TARGET_REACHED : 0; + status |= (StepDir[channel].stallGuardActive) ? STATUS_STALLGUARD_ACTIVE : 0; + status |= (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_VELOCITY) ? STATUS_MODE : 0; + + return status; +} + +// Register the pins to be used by a StepDir channel. NULL will leave the pin unchanged +void StepDir_setPins(uint8_t channel, IOPinTypeDef *stepPin, IOPinTypeDef *dirPin, IOPinTypeDef *stallPin) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (stepPin) + { + if (IS_DUMMY_PIN(stepPin)) + { + // Set the halting condition before changing the pin + StepDir[channel].haltingCondition |= STATUS_NO_STEP_PIN; + } + StepDir[channel].stepPin = stepPin; + if (!IS_DUMMY_PIN(stepPin)) + { + // Clear the halting condition after setting the pin + StepDir[channel].haltingCondition &= ~STATUS_NO_STEP_PIN; + } + } + + if (dirPin) + { + if (IS_DUMMY_PIN(dirPin)) + { + // Set the halting condition before changing the pin + StepDir[channel].haltingCondition |= STATUS_NO_DIR_PIN; + } + StepDir[channel].dirPin = dirPin; + if (!IS_DUMMY_PIN(dirPin)) + { + // Clear the halting condition after setting the pin + StepDir[channel].haltingCondition &= ~STATUS_NO_DIR_PIN; + } + } + + if (stallPin) + { + StepDir[channel].stallGuardPin = stallPin; + } +} + +void StepDir_stallGuard(uint8_t channel, bool stall) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + checkStallguard(&StepDir[channel], stall); +} + +// ===== Setters ===== +// The setters are responsible to access their respective variables while keeping the ramp generation stable + +// Set actual and target position (Not during an active position ramp) +void StepDir_setActualPosition(uint8_t channel, int32_t actualPosition) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_POSITION) + { + // In position mode: If we're not idle -> abort +// if ((StepDir[channel].actualVelocity != 0) || +// (StepDir[channel].actualPosition != StepDir[channel].targetPosition)) +// { +// return; +// } + + // todo CHECK 2: Use a haltingCondition to prevent movement instead of VMAX? (LH) + // Temporarity set VMAX to 0 to prevent movement between setting actualPosition and targetPosition +// uint32_t tmp = StepDir[channel].velocityMax; +// StepDir[channel].velocityMax = 0; + + // Also update target position to prevent movement + tmc_ramp_linear_set_targetPosition(&StepDir[channel].ramp, actualPosition); + tmc_ramp_linear_set_rampPosition(&StepDir[channel].ramp, actualPosition); + + // Restore VMAX +// StepDir[channel].velocityMax = tmp; + } + else + { + // In velocity mode the position is not relevant so we can just update it without precautions + tmc_ramp_linear_set_rampPosition(&StepDir[channel].ramp, actualPosition); + } +} + +void StepDir_setAcceleration(uint8_t channel, uint32_t acceleration) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + if (tmc_ramp_linear_get_mode(&StepDir[channel].ramp) == TMC_RAMP_LINEAR_MODE_VELOCITY) + { // Velocity mode does not require any special actions + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + return; + } + + // Position mode does not allow acceleration 0 + if (acceleration == 0) + return; + + // Store the old acceleration + uint32_t oldAcceleration = tmc_ramp_linear_get_acceleration(&StepDir[channel].ramp); + + // Update the acceleration + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + + // If the channel is not halted we need to synchronise with the interrupt + if (StepDir[channel].haltingCondition == 0) + { + // Sync mechanism: store the new acceleration value and request + // a snapshot from the interrupt + StepDir[channel].newAcceleration = acceleration; + StepDir[channel].syncFlag = SYNC_SNAPSHOT_REQUESTED; + // Wait for the flag update from the interrupt. + while (ACCESS_ONCE(StepDir[channel].syncFlag) != SYNC_SNAPSHOT_SAVED); // todo CHECK 2: Timeout to prevent deadlock? (LH) #1 + } + else + { // Channel is halted -> access data directly without sync mechanism + //StepDir[channel].acceleration = acceleration; + tmc_ramp_linear_set_acceleration(&StepDir[channel].ramp, acceleration); + StepDir[channel].oldVelocity = tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp); + } + + int32_t stepDifference = calculateStepDifference(StepDir[channel].oldVelocity, oldAcceleration, acceleration); + + if (StepDir[channel].haltingCondition == 0) + { + StepDir[channel].stepDifference = stepDifference; + StepDir[channel].syncFlag = SYNC_UPDATE_DATA; + + // Wait for interrupt to set flag to SYNC_IDLE + while (ACCESS_ONCE(StepDir[channel].syncFlag) != SYNC_IDLE); // todo CHECK 2: Timeout to prevent deadlock? (LH) #2 + } + else + { // Channel is halted -> access data directly without sync mechanism + StepDir[channel].ramp.accelerationSteps += stepDifference; + } +} + +void StepDir_setVelocityMax(uint8_t channel, int32_t velocityMax) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_maxVelocity(&StepDir[channel].ramp, velocityMax); +} + +// Set the velocity threshold for active StallGuard. Also reset the stall flag +void StepDir_setStallGuardThreshold(uint8_t channel, int32_t stallGuardThreshold) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].stallGuardThreshold = stallGuardThreshold; + StepDir[channel].haltingCondition &= ~STATUS_STALLED; +} + +void StepDir_setMode(uint8_t channel, StepDirMode mode) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].mode = mode; + + if (mode == STEPDIR_INTERNAL) + { + StepDir_setFrequency(channel, STEPDIR_FREQUENCY); + } +} + +void StepDir_setFrequency(uint8_t channel, uint32_t frequency) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + StepDir[channel].frequency = frequency; +} + +void StepDir_setPrecision(uint8_t channel, uint32_t precision) +{ + if (channel >= STEP_DIR_CHANNELS) + return; + + tmc_ramp_linear_set_precision(&StepDir[channel].ramp, precision); +} + +// ===== Getters ===== +int32_t StepDir_getActualPosition(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_rampPosition(&StepDir[channel].ramp); +} + +int32_t StepDir_getTargetPosition(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_targetPosition(&StepDir[channel].ramp); +} + +int32_t StepDir_getActualVelocity(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_rampVelocity(&StepDir[channel].ramp); +} + +int32_t StepDir_getTargetVelocity(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_targetVelocity(&StepDir[channel].ramp); +} + +uint32_t StepDir_getAcceleration(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_acceleration(&StepDir[channel].ramp); +} + +int32_t StepDir_getVelocityMax(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return tmc_ramp_linear_get_maxVelocity(&StepDir[channel].ramp); +} + +int32_t StepDir_getStallGuardThreshold(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].stallGuardThreshold; +} + +StepDirMode StepDir_getMode(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].mode; +} + +uint32_t StepDir_getFrequency(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + return StepDir[channel].frequency; +} + +uint32_t StepDir_getPrecision(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return 0; + + return tmc_ramp_linear_get_precision(&StepDir[channel].ramp); +} + +int32_t StepDir_getMaxAcceleration(uint8_t channel) +{ + if (channel >= STEP_DIR_CHANNELS) + return -1; + + if (StepDir[channel].mode == STEPDIR_INTERNAL) + return STEPDIR_MAX_ACCELERATION; + + // STEPDIR_EXTERNAL -> no limitation from this generator + return s32_MAX; +} + +// =================== + +void StepDir_init(uint32_t precision) +{ + if (precision == 0) + { + // Use default precision + precision = STEPDIR_FREQUENCY; + } + + // StepDir Channel initialisation + for (uint8_t i = 0; i < STEP_DIR_CHANNELS; i++) + { + StepDir[i].oldVelAccu = 0; + StepDir[i].oldVelocity = 0; + StepDir[i].newAcceleration = 0; + + // Set the no-pin halting conditions before changing the pins + // to avoid a race condition with the interrupt + StepDir[i].haltingCondition = STATUS_NO_STEP_PIN | STATUS_NO_DIR_PIN; + StepDir[i].stallGuardPin = &DummyPin; + StepDir[i].stepPin = &DummyPin; + StepDir[i].dirPin = &DummyPin; + + StepDir[i].stallGuardThreshold = STALLGUARD_THRESHOLD; + + StepDir[i].mode = STEPDIR_INTERNAL; + StepDir[i].frequency = precision; + + tmc_ramp_linear_init(&StepDir[i].ramp); + tmc_ramp_linear_set_precision(&StepDir[i].ramp, precision); + tmc_ramp_linear_set_maxVelocity(&StepDir[i].ramp, STEPDIR_DEFAULT_VELOCITY); + tmc_ramp_linear_set_acceleration(&StepDir[i].ramp, STEPDIR_DEFAULT_ACCELERATION); + } + + // Chip-specific hardware peripheral initialisation + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // enable clock for FTM1 + SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; + + FTM1_MODE |= FTM_MODE_WPDIS_MASK; // disable write protection, FTM specific register are available + + FTM1_MODE |= FTM_MODE_FTMEN_MASK | FTM_MODE_FAULTM_MASK; //enable interrupt and select all faults + + // Timer frequency = Bus clk frequency / (MOD - CNTIN + 1) + // => MOD = (f_bus / f_timer) + CNTIN - 1 + // The datasheet documents the FTM using the system/core clock, but it's + // actually using the bus clock + FTM1_CNTIN = 0; + FTM1_MOD = (48000000 / precision) - 1; + + // Select Bus clock as clock source, set prescaler divisor to 2^0 = 1, + // enable timer overflow interrupt + FTM1_SC |= FTM_SC_CLKS(1) | FTM_SC_PS(0) | FTM_SC_TOIE_MASK; + + // set FTM1 interrupt handler + enable_irq(INT_FTM1-16); + #elif defined(LandungsbrueckeV3) + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + timer_parameter_struct tps; + timer_struct_para_init(&tps); + + tps.period = 914; + + timer_init(TIMER2, &tps); + timer_interrupt_enable(TIMER2, TIMER_INT_UP); + timer_update_event_enable(TIMER2); + timer_enable(TIMER2); + + nvic_irq_enable(TIMER2_IRQn, 1, 1); + #endif +} + +void StepDir_deInit() +{ + #if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // Only disable the module if it has been enabled before + if (SIM_SCGC6 & SIM_SCGC6_FTM1_MASK) + { + // Disable interrupt in FTM module + FTM1_SC &= ~FTM_SC_TOIE_MASK; + + // Disable the FTM module + FTM1_MODE &= ~FTM_MODE_FTMEN_MASK; + + // Disable the interrupt + disable_irq(INT_FTM1-16); + + // Ensure that the module is disabled BEFORE clock gating gets disabled. + // Without this the processor can crash under heavy FTM interrupt load. + asm volatile("DMB"); + + // Disable clock gating for the FTM module + SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; + SIM_SCGC6 &= ~SIM_SCGC6_FTM1_MASK; + } + #endif +} + +// ===== Helper function ===== +/* The required calculation to do is the difference of the required + * amount of steps to reach a given velocity, using two different + * given accelerations with an evenly accelerated ramp. + * + * Calculation: + * v1: Start velocity + * v2: Target velocity + * a: Acceleration + * t: Time required to reach the target velocity + * s: distance traveled while accelerating + * + * t = (v2 - v1) / a + * The distance can be calculated with the average velocity v_avrg: + * v_avrg = (v2 + v1) / 2 + * s = v_avrg * t + * = (v2 + v1) / 2 * (v2 - v1) / a + * = (v2 + v1) * (v2 - v1) / (2*a) + * = (v2^2 - v1^2) / (2*a) + * + * Our calculation assumes that the starting velocity v1 is zero: + * v1 := 0 + * s = (v2^2 - 0^2) / (2*a) + * = v2^2 / (2*a) + * + * Calculating velocities with an accumulator results in the velocity + * being equal or up to 1 below the theoretical velocity (distributed evenly). + * To reduce the maximum error in the result of the step calculation, + * the velocity will be increased by 0.5, so that the velocity error + * will be within [0.5, -0.5). + * s = (v+0.5)^2 / (2*a) + * Change to using integer math: + * s = ((v+0.5)*2/2)^2 / (2*a) + * = ((v*2 + 1)/2)^2 / (2*a) + * = (v*2 + 1)^2 / 2^2 / (2*a) + * = (v*2 + 1)^2 / (8a) + * + * The result we need is the difference s2 - s1, using a2 and a1 respectively. + * Only changing the acceleration allows us to reuse most of the calculation: + * We define + * x := (v*2 + 1)^2 / 8 + * so that + * s = x/a + * + * Variables <=> Formula: + * oldAccel: a2 + * newAccel: a1 + * velocity: v + * oldSteps: s1 + * newSteps: s2 + */ +static int32_t calculateStepDifference(int32_t velocity, uint32_t oldAccel, uint32_t newAccel) +{ + int64_t tmp = velocity; + tmp = tmp * 2 + 1; + tmp = (tmp * tmp) / 4; + tmp = tmp / 2; + uint32_t oldSteps = tmp / oldAccel; + uint32_t newSteps = tmp / newAccel; + + return newSteps - oldSteps; +} + +// This helper function implements stallguard logic that is used both in the +// interrupt and main loop code. It is used to optimize the interrupt case. +static inline void checkStallguard(StepDirectionTypedef *channel, bool stallSignalActive) +{ + if (channel->stallGuardActive && stallSignalActive) + { + stop(channel, STOP_STALL); + } +} + +static inline void stop(StepDirectionTypedef *channel, StepDirStop stopType) +{ + switch(stopType) + { + case STOP_NORMAL: + tmc_ramp_linear_set_targetVelocity(&channel->ramp, 0); + tmc_ramp_linear_set_mode(&channel->ramp, TMC_RAMP_LINEAR_MODE_VELOCITY); + break; + case STOP_EMERGENCY: + channel->haltingCondition |= STATUS_EMERGENCY_STOP; + break; + case STOP_STALL: + channel->haltingCondition |= STATUS_STALLED; + tmc_ramp_linear_set_rampVelocity(&channel->ramp, 0); + channel->ramp.accumulatorVelocity = 0; + tmc_ramp_linear_set_targetVelocity(&channel->ramp, 0); + channel->ramp.accelerationSteps = 0; + break; + } +} diff --git a/TMC2209/lib/tmc/tmc/StepDir.h b/TMC2209/lib/tmc/tmc/StepDir.h new file mode 100644 index 0000000..bf64ae1 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/StepDir.h @@ -0,0 +1,110 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef STEP_DIR_H_ +#define STEP_DIR_H_ + + #include "tmc/helpers/API_Header.h" + #include "tmc/ramp/LinearRamp1.h" + + #include "tmc/hal/HAL.h" + + #define STEPDIR_FREQUENCY (1 << 17) + #define STEPDIR_MAX_VELOCITY STEPDIR_FREQUENCY // Limit: 1 Step per interrupt (2^17 Hz) -> 2^17 pps + #define STEPDIR_MAX_ACCELERATION 2147418111 // Limit: Highest value above accumulator digits (0xFFFE0000). + // Any value above would lead to acceleration overflow whenever the accumulator digits overflow + + #define STEPDIR_DEFAULT_ACCELERATION 100000 + #define STEPDIR_DEFAULT_VELOCITY STEPDIR_MAX_VELOCITY + + typedef enum { + STEPDIR_INTERNAL = 0, + STEPDIR_EXTERNAL = 1 + } StepDirMode; // Has to be set explicitly here because IDE relies on this number. + + typedef enum { + STOP_NORMAL, + STOP_EMERGENCY, + STOP_STALL + } StepDirStop; + + typedef enum { + SYNC_IDLE, // Sync mechanism not running + SYNC_SNAPSHOT_REQUESTED, // Main code saved the new acceleration and is waiting for the interrupt to save the velocity and apply the acceleration (atomically, from the StepDir generator perspective). + SYNC_SNAPSHOT_SAVED, // Interrupt saved the velocity + SYNC_UPDATE_DATA // Main code calculated an accelerationSteps difference which the interrupt needs to apply. + } StepDirSync; + + // StepDir status bits + #define STATUS_EMERGENCY_STOP 0x01 // Halting condition - Emergency Off + #define STATUS_NO_STEP_PIN 0x02 // Halting condition - No pin set for Step output + #define STATUS_NO_DIR_PIN 0x04 // Halting condition - No pin set for Direction output + #define STATUS_STALLED 0x08 // Halting condition - Stall detected (while Stallguard is enabled) + #define STATUS_TARGET_REACHED 0x10 // Position mode status - target reached + #define STATUS_STALLGUARD_ACTIVE 0x20 // Stallguard status - Velocity threshold reached, Stallguard enabled + #define STATUS_MODE 0x40 // 0: Positioning mode, 1: Velocity mode + + typedef struct + { // Generic parameters + uint8_t haltingCondition; + // StallGuard + bool stallGuardActive; + int32_t stallGuardThreshold; + IOPinTypeDef *stallGuardPin; + // StepDir Pins + IOPinTypeDef *stepPin; + IOPinTypeDef *dirPin; + // Acceleration updating sync mechanism (see acceleration setter for details) + StepDirSync syncFlag; // Synchronisation flag between main code & interrupt + // Snapshot data + // Interrupt -> main code + int32_t oldVelocity; + int32_t oldVelAccu; + // Main code -> interrupt + uint32_t newAcceleration; + int32_t stepDifference; + StepDirMode mode; + uint32_t frequency; + + TMC_LinearRamp ramp; + } StepDirectionTypedef; + + void StepDir_rotate(uint8_t channel, int32_t velocity); + void StepDir_moveTo(uint8_t channel, int32_t position); + void StepDir_periodicJob(uint8_t channel); + void StepDir_stop(uint8_t channel, StepDirStop stopType); + uint8_t StepDir_getStatus(uint8_t channel); + void StepDir_setPins(uint8_t channel, IOPinTypeDef *stepPin, IOPinTypeDef *dirPin, IOPinTypeDef *stallPin); + void StepDir_stallGuard(uint8_t channel, bool stall); + + // ===== Setters ===== + void StepDir_setActualPosition(uint8_t channel, int32_t actualPosition); + void StepDir_setAcceleration(uint8_t channel, uint32_t actualAcceleration); + void StepDir_setVelocityMax(uint8_t channel, int32_t velocityMax); + void StepDir_setStallGuardThreshold(uint8_t channel, int32_t stallGuardThreshold); + void StepDir_setMode(uint8_t channel, StepDirMode mode); + void StepDir_setFrequency(uint8_t channel, uint32_t frequency); + void StepDir_setPrecision(uint8_t channel, uint32_t precision); + // ===== Getters ===== + int32_t StepDir_getActualPosition(uint8_t channel); + int32_t StepDir_getTargetPosition(uint8_t channel); + int32_t StepDir_getActualVelocity(uint8_t channel); + int32_t StepDir_getTargetVelocity(uint8_t channel); + uint32_t StepDir_getAcceleration(uint8_t channel); + int32_t StepDir_getVelocityMax(uint8_t channel); + int32_t StepDir_getStallGuardThreshold(uint8_t channel); + StepDirMode StepDir_getMode(uint8_t channel); + uint32_t StepDir_getFrequency(uint8_t channel); + uint32_t StepDir_getPrecision(uint8_t channel); + int32_t StepDir_getMaxAcceleration(uint8_t channel); + + void StepDir_init(uint32_t precision); + void StepDir_deInit(void); + +#endif /* STEP_DIR_H_ */ diff --git a/TMC2209/lib/tmc/tmc/TMCL.c b/TMC2209/lib/tmc/tmc/TMCL.c new file mode 100644 index 0000000..450b0e9 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/TMCL.c @@ -0,0 +1,1171 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "TMCL.h" +#include "BoardAssignment.h" +#include "hal/derivative.h" +#include "IdDetection.h" +#include "VitalSignsMonitor.h" +#include "tmc/StepDir.h" +#include "EEPROM.h" +#include "RAMDebug.h" +#include "hal/Timer.h" + +// these addresses are fixed +#define SERIAL_MODULE_ADDRESS 1 +#define SERIAL_HOST_ADDRESS 2 + +// todo CHECK 2: these are unused - delete? (LH) #11 +// tmcl interpreter states +#define TM_IDLE 0 +#define TM_RUN 1 +#define TM_STEP 2 +#define TM_RESET 3 // unused +#define TM_DOWNLOAD 4 +#define TM_DEBUG 5 // wie TM_IDLE, es wird jedoch der Akku nicht modifiziert bei GAP etc. + +// todo CHECK 2: these are unused - delete? (LH) #12 +#define TCS_IDLE 0 +#define TCS_CAN7 1 +#define TCS_CAN8 2 +#define TCS_UART 3 +#define TCS_UART_ERROR 4 +#define TCS_UART_II 5 +#define TCS_UART_II_ERROR 6 +#define TCS_USB 7 +#define TCS_USB_ERROR 8 +#define TCS_MEM 9 + +// TMCL commands +#define TMCL_ROR 1 +#define TMCL_ROL 2 +#define TMCL_MST 3 +#define TMCL_MVP 4 +#define TMCL_SAP 5 +#define TMCL_GAP 6 +#define TMCL_STAP 7 +#define TMCL_RSAP 8 +#define TMCL_SGP 9 +#define TMCL_GGP 10 +#define TMCL_STGP 11 +#define TMCL_RSGP 12 +#define TMCL_RFS 13 +#define TMCL_SIO 14 +#define TMCL_GIO 15 +#define TMCL_CALC 19 +#define TMCL_COMP 20 +#define TMCL_JC 21 +#define TMCL_JA 22 +#define TMCL_CSUB 23 +#define TMCL_RSUB 24 +#define TMCL_EI 25 +#define TMCL_DI 26 +#define TMCL_WAIT 27 +#define TMCL_STOP 28 +#define TMCL_SAC 29 +#define TMCL_SCO 30 +#define TMCL_GCO 31 +#define TMCL_CCO 32 +#define TMCL_CALCX 33 +#define TMCL_AAP 34 +#define TMCL_AGP 35 +#define TMCL_CLE 36 +#define TMCL_VECT 37 +#define TMCL_RETI 38 +#define TMCL_ACO 39 + +#define TMCL_UF0 64 +#define TMCL_UF1 65 +#define TMCL_UF2 66 +#define TMCL_UF3 67 +#define TMCL_UF4 68 +#define TMCL_UF5 69 +#define TMCL_UF6 70 +#define TMCL_UF7 71 +#define TMCL_UF8 72 + +#define TMCL_ApplStop 128 +#define TMCL_ApplRun 129 +#define TMCL_ApplStep 130 +#define TMCL_ApplReset 131 +#define TMCL_DownloadStart 132 +#define TMCL_DownloadEnd 133 +#define TMCL_ReadMem 134 +#define TMCL_GetStatus 135 +#define TMCL_GetVersion 136 +#define TMCL_FactoryDefault 137 +#define TMCL_SetEvent 138 +#define TMCL_SetASCII 139 +#define TMCL_SecurityCode 140 +#define TMCL_Breakpoint 141 +#define TMCL_RamDebug 142 +#define TMCL_GetIds 143 +#define TMCL_UF_CH1 144 +#define TMCL_UF_CH2 145 +#define TMCL_writeRegisterChannel_1 146 +#define TMCL_writeRegisterChannel_2 147 +#define TMCL_readRegisterChannel_1 148 +#define TMCL_readRegisterChannel_2 149 + +#define TMCL_BoardMeasuredSpeed 150 +#define TMCL_BoardError 151 +#define TMCL_BoardReset 152 + +#define TMCL_WLAN 160 +#define TMCL_WLAN_CMD 160 +#define TMCL_WLAN_IS_RTS 161 +#define TMCL_WLAN_CMDMODE_EN 162 +#define TMCL_WLAN_IS_CMDMODE 163 + +#define TMCL_MIN 170 +#define TMCL_MAX 171 +#define TMCL_OTP 172 + +#define TMCL_Boot 242 +#define TMCL_SoftwareReset 255 + +// Command type variants +#define MVP_ABS 0 +#define MVP_REL 1 +#define MVP_PRF 2 + +// GetVersion() Format types +#define VERSION_FORMAT_ASCII 0 +#define VERSION_FORMAT_BINARY 1 +#define VERSION_BOOTLOADER 2 // todo CHECK 2: implemented this way in IDE - probably means getting the bootloader version. Not implemented in firmware (LH) +#define VERSION_SIGNATURE 3 // todo CHECK 2: implemented under "Signature" in IDE. Not sure what to return for that. Not implemented in firmware (LH) +#define VERSION_BOARD_DETECT_SRC 4 // todo CHECK 2: This doesn't really fit under GetVersion, but its implemented there in the IDE - change or leave this way? (LH) +#define VERSION_BUILD 5 + +//Statuscodes +#define REPLY_OK 100 +#define REPLY_CMD_LOADED 101 +#define REPLY_CHKERR 1 +#define REPLY_INVALID_CMD 2 +#define REPLY_INVALID_TYPE 3 +#define REPLY_INVALID_VALUE 4 +#define REPLY_EEPROM_LOCKED 5 +#define REPLY_CMD_NOT_AVAILABLE 6 +#define REPLY_CMD_LOAD_ERROR 7 +#define REPLY_WRITE_PROTECTED 8 +#define REPLY_MAX_EXCEEDED 9 +#define REPLY_DOWNLOAD_NOT_POSSIBLE 10 +#define REPLY_CHIP_READ_FAILED 11 +#define REPLY_DELAYED 128 +#define REPLY_ACTIVE_COMM 129 + +// TMCL communication status +#define TMCL_RX_ERROR_NONE 0 +#define TMCL_RX_ERROR_NODATA 1 +#define TMCL_RX_ERROR_CHECKSUM 2 + +extern const char *VersionString; + +// TMCL request +typedef struct +{ + uint8_t Opcode; + uint8_t Type; + uint8_t Motor; + uint32_t Error; + union + { + uint8_t Byte[4]; + uint32_t UInt32; + int32_t Int32; + float32_t Float32; + } Value; +} TMCLCommandTypeDef; + +// TMCL reply +typedef struct +{ + uint8_t Status; + uint8_t Opcode; + union + { + uint8_t Byte[4]; + uint32_t UInt32; + int32_t Int32; + float32_t Float32; + } Value; + + uint8_t Special[9]; + uint8_t IsSpecial; // next transfer will not use the serial address and the checksum bytes - instead the whole datagram is filled with data (used to transmit ASCII version string) +} TMCLReplyTypeDef; + +void ExecuteActualCommand(); +uint8_t setTMCLStatus(uint8_t evalError); +void rx(RXTXTypeDef *RXTX); +void tx(RXTXTypeDef *RXTX); + +static uint16_t getExtendedAddress(TMCLCommandTypeDef *tmclCommand) +{ + return (((uint16_t) tmclCommand->Motor >> 4) << 8) | tmclCommand->Type; +} + +// Helper functions - used to prevent ExecuteActualCommand() from getting too big. +// No parameters or return value are used. +static void readIdEeprom(void); +static void writeIdEeprom(void); +static void SetGlobalParameter(void); +static void GetGlobalParameter(void); +static void boardAssignment(void); +static void boardsErrors(void); +static void boardsReset(void); +static void boardsMeasuredSpeed(void); +static void setDriversEnable(void); +static void checkIDs(void); +static void SoftwareReset(void); +static void GetVersion(void); +static void GetInput(void); +static void HandleWlanCommand(void); +static void handleRamDebug(void); +static void handleOTP(void); + +TMCLCommandTypeDef ActualCommand; +TMCLReplyTypeDef ActualReply; +RXTXTypeDef interfaces[4]; +uint32_t numberOfInterfaces; +uint32_t resetRequest = 0; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + // ToDo: Remove the duplicate declaration of the struct here and in main.c + struct BootloaderConfig { + uint32_t BLMagic; + uint32_t drvEnableResetValue; + }; + + extern struct BootloaderConfig BLConfig; +#elif defined(LandungsbrueckeV3) + // ToDo: Remove the duplicate declaration of the struct here and in main.c + struct BootloaderConfig { + uint32_t BLMagic; + }; + + extern struct BootloaderConfig BLConfig; +#endif + +// Sets TMCL status from Evalboard error. Returns the parameter given to allow for compact error handling +uint8_t setTMCLStatus(uint8_t evalError) +{ + if(evalError == TMC_ERROR_NONE) ActualReply.Status = REPLY_OK; + else if(evalError & TMC_ERROR_FUNCTION) ActualReply.Status = REPLY_INVALID_CMD; + else if(evalError & TMC_ERROR_TYPE) ActualReply.Status = REPLY_INVALID_TYPE; + else if(evalError & TMC_ERROR_MOTOR) ActualReply.Status = REPLY_INVALID_TYPE; // todo CHECK ADD 2: Different errors for Evalboard type/motor errors? (LH) #1 + else if(evalError & TMC_ERROR_VALUE) ActualReply.Status = REPLY_INVALID_VALUE; + else if(evalError & TMC_ERROR_NOT_DONE) ActualReply.Status = REPLY_DELAYED; + else if(evalError & TMC_ERROR_CHIP) ActualReply.Status = REPLY_EEPROM_LOCKED; + return evalError; +} + +void ExecuteActualCommand() +{ + ActualReply.Opcode = ActualCommand.Opcode; + ActualReply.Status = REPLY_OK; + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + + if(ActualCommand.Error == TMCL_RX_ERROR_CHECKSUM) + { + ActualReply.Value.Int32 = 0; + ActualReply.Status = REPLY_CHKERR; + return; + } + + switch(ActualCommand.Opcode) + { + case TMCL_ROR: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.right(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.right(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_ROL: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.left(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.left(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_MST: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.stop(ActualCommand.Motor)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.stop(ActualCommand.Motor)); + } + break; + case TMCL_MVP: + // if function doesn't exist for ch1 try ch2 + switch(ActualCommand.Type) + { + case MVP_ABS: // move absolute + if(setTMCLStatus(Evalboards.ch1.moveTo(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveTo(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case MVP_REL: // move relative + if(setTMCLStatus(Evalboards.ch1.moveBy(ActualCommand.Motor, &ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveBy(ActualCommand.Motor, &ActualCommand.Value.Int32)); + } + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case MVP_PRF: + if(setTMCLStatus(Evalboards.ch1.moveProfile(ActualCommand.Motor, ActualCommand.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.moveProfile(ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } + break; + case TMCL_SAP: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.SAP(ActualCommand.Type, ActualCommand.Motor, ActualCommand.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.SAP(ActualCommand.Type, ActualCommand.Motor, ActualCommand.Value.Int32)); + } + break; + case TMCL_GAP: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.GAP(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.GAP(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_SGP: + SetGlobalParameter(); + break; + case TMCL_GGP: + GetGlobalParameter(); + break; + case TMCL_GIO: + GetInput(); + break; + case TMCL_UF0: + setDriversEnable(); + break; + case TMCL_UF1: + readIdEeprom(); + break; + case TMCL_UF2: + writeIdEeprom(); + break; + case TMCL_UF4: + // if function doesn't exist for ch1 try ch2 + if(setTMCLStatus(Evalboards.ch1.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32)) & TMC_ERROR_FUNCTION) + { + setTMCLStatus(Evalboards.ch2.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_UF5: + // if function doesn't exist for ch1 try ch2 // todo CHECK REM 2: We have TMCL_writeRegisterChannel_1, we dont need this. Make sure it isnt used in IDE (LH) #1 + Evalboards.ch1.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_UF6: + // if function doesn't exist for ch1 try ch2 // todo CHECK REM 2: We have TMCL_readRegisterChannel_1, we dont need this. Make sure it isnt used in IDE (LH) #2 + Evalboards.ch1.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + break; + case TMCL_UF8: + // user function for reading Motor0_XActual and Motor1_XActual + Evalboards.ch1.userFunction(ActualCommand.Type, 0, &ActualCommand.Value.Int32); + int32_t m0XActual = ActualCommand.Value.Int32; + Evalboards.ch1.userFunction(ActualCommand.Type, 1, &ActualCommand.Value.Int32); + int32_t m1XActual = ActualCommand.Value.Int32; + ActualReply.Value.Byte[0]= m1XActual & 0xFF; + ActualReply.Value.Byte[1]= (m1XActual & 0xFF00)>>8; + ActualReply.Value.Byte[2]= (m1XActual & 0xFF0000)>>16; + ActualReply.Value.Byte[3]= m0XActual & 0xFF; + ActualReply.Opcode= (m0XActual & 0xFF00)>>8; + ActualReply.Status= (m0XActual & 0xFF0000)>>16; + break; + case TMCL_GetVersion: + GetVersion(); + break; + case TMCL_GetIds: + boardAssignment(); + break; + case TMCL_UF_CH1: + // user function for motionController board + setTMCLStatus(Evalboards.ch1.userFunction(ActualCommand.Type, ActualCommand.Motor, &ActualCommand.Value.Int32)); + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case TMCL_UF_CH2: + // user function for driver board + setTMCLStatus(Evalboards.ch2.userFunction(ActualCommand.Type, ActualCommand.Motor, &ActualCommand.Value.Int32)); + ActualReply.Value.Int32 = ActualCommand.Value.Int32; + break; + case TMCL_writeRegisterChannel_1: + Evalboards.ch1.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_writeRegisterChannel_2: + Evalboards.ch2.writeRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), ActualCommand.Value.Int32); + break; + case TMCL_readRegisterChannel_1: + // Do not allow reads during brownout to prevent garbage data being used + // in read-modify-write operations. Bypass this safety with motor = 255 + if ((VitalSignsMonitor.brownOut & VSM_ERRORS_BROWNOUT_CH1) && ActualCommand.Motor != 255) + { + ActualReply.Status = REPLY_CHIP_READ_FAILED; + } + else + { + Evalboards.ch1.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + } + break; + case TMCL_readRegisterChannel_2: + // Do not allow reads during brownout to prevent garbage data being used + // in read-modify-write operations. Bypass this safety with motor = 255 + if ((VitalSignsMonitor.brownOut & VSM_ERRORS_BROWNOUT_CH2) && ActualCommand.Motor != 255) + ActualReply.Status = REPLY_CHIP_READ_FAILED; + else + Evalboards.ch2.readRegister(ActualCommand.Motor & 0x0F, getExtendedAddress(&ActualCommand), &ActualReply.Value.Int32); + break; + case TMCL_BoardMeasuredSpeed: + // measured speed from motionController board or driver board depending on type + boardsMeasuredSpeed(); + break; + case TMCL_BoardError: + // errors of motionController board or driver board depending on type + boardsErrors(); + break; + case TMCL_BoardReset: + // reset of motionController board or driver board depending on type + boardsReset(); + break; + case TMCL_WLAN: + HandleWlanCommand(); + break; + case TMCL_RamDebug: + handleRamDebug(); + break; + case TMCL_OTP: + handleOTP(); + break; + case TMCL_MIN: + if(setTMCLStatus(Evalboards.ch1.getMin(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.getMin(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_MAX: + if(setTMCLStatus(Evalboards.ch1.getMax(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)) & (TMC_ERROR_TYPE | TMC_ERROR_FUNCTION)) + { + setTMCLStatus(Evalboards.ch2.getMax(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32)); + } + break; + case TMCL_Boot: + if(ActualCommand.Type != 0x81) break; + if(ActualCommand.Motor != 0x92) break; + if(ActualCommand.Value.Byte[3] != 0xA3) break; + if(ActualCommand.Value.Byte[2] != 0xB4) break; + if(ActualCommand.Value.Byte[1] != 0xC5) break; + if(ActualCommand.Value.Byte[0] != 0xD6) break; + tmcl_boot(); + break; + case TMCL_SoftwareReset: + SoftwareReset(); + break; + default: + ActualReply.Status = REPLY_INVALID_CMD; + break; + } +} + +void tmcl_init() +{ + ActualCommand.Error = TMCL_RX_ERROR_NODATA; + interfaces[0] = *HAL.USB; + interfaces[1] = *HAL.RS232; + interfaces[2] = *HAL.WLAN; + numberOfInterfaces = 3; +} + +void tmcl_process() +{ + static int32_t currentInterface = 0; + + if(ActualCommand.Error != TMCL_RX_ERROR_NODATA) + tx(&interfaces[currentInterface]); + + if(resetRequest) + HAL.reset(true); + + ActualReply.IsSpecial = 0; + + for(uint32_t i = 0; i < numberOfInterfaces; i++) + { + rx(&interfaces[i]); + if(ActualCommand.Error != TMCL_RX_ERROR_NODATA) + { + currentInterface = i; + ExecuteActualCommand(); + return; + } + } +} + +void tx(RXTXTypeDef *RXTX) +{ + uint8_t checkSum = 0; + + uint8_t reply[9]; + + if(ActualReply.IsSpecial) + { + for(uint8_t i = 0; i < 9; i++) + reply[i] = ActualReply.Special[i]; + } + else + { + checkSum += SERIAL_HOST_ADDRESS; + checkSum += SERIAL_MODULE_ADDRESS; + checkSum += ActualReply.Status; + checkSum += ActualReply.Opcode; + checkSum += ActualReply.Value.Byte[3]; + checkSum += ActualReply.Value.Byte[2]; + checkSum += ActualReply.Value.Byte[1]; + checkSum += ActualReply.Value.Byte[0]; + + reply[0] = SERIAL_HOST_ADDRESS; + reply[1] = SERIAL_MODULE_ADDRESS; + reply[2] = ActualReply.Status; + reply[3] = ActualReply.Opcode; + reply[4] = ActualReply.Value.Byte[3]; + reply[5] = ActualReply.Value.Byte[2]; + reply[6] = ActualReply.Value.Byte[1]; + reply[7] = ActualReply.Value.Byte[0]; + reply[8] = checkSum; + } + + RXTX->txN(reply, 9); +} + +void rx(RXTXTypeDef *RXTX) +{ + uint8_t checkSum = 0; + uint8_t cmd[9]; + + if(!RXTX->rxN(cmd, 9)) + { + ActualCommand.Error = TMCL_RX_ERROR_NODATA; + return; + } + + // todo ADD CHECK 2: check for SERIAL_MODULE_ADDRESS byte ( cmd[0] ) ? (LH) + + for(uint8_t i = 0; i < 8; i++) + checkSum += cmd[i]; + + if(checkSum != cmd[8]) + { + ActualCommand.Error = TMCL_RX_ERROR_CHECKSUM; + return; + } + + ActualCommand.Opcode = cmd[1]; + ActualCommand.Type = cmd[2]; + ActualCommand.Motor = cmd[3]; + ActualCommand.Value.Byte[3] = cmd[4]; + ActualCommand.Value.Byte[2] = cmd[5]; + ActualCommand.Value.Byte[1] = cmd[6]; + ActualCommand.Value.Byte[0] = cmd[7]; + ActualCommand.Error = TMCL_RX_ERROR_NONE; +} + +void tmcl_boot() +{ +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + if(Evalboards.ch1.id == ID_TMC4671) + { + // Driver Enable has to be set low by the bootloader for these ICs + BLConfig.drvEnableResetValue = 0; + } + else + { + // Default: Driver Enable is set to high + BLConfig.drvEnableResetValue = 1; + } +#endif + Evalboards.driverEnable = DRIVER_DISABLE; + Evalboards.ch1.enableDriver(DRIVER_DISABLE); // todo CHECK 2: the ch1/2 deInit() calls should already disable the drivers - keep this driver disabling to be sure or remove it and leave the disabling to deInit? (LH) + Evalboards.ch2.enableDriver(DRIVER_DISABLE); + + Evalboards.ch1.deInit(); + Evalboards.ch2.deInit(); + + HAL.USB->deInit(); + + wait(500); + + HAL.Timer->deInit(); + HAL.RS232->deInit(); + HAL.WLAN->deInit(); + HAL.ADCs->deInit(); + + // todo: CHECK 2: Muss api_deInit hier dazu? (ED) + StepDir_deInit(); + + IDDetection_deInit(); + + HAL.NVIC_DeInit(); + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) || defined(LandungsbrueckeV3) + BLConfig.BLMagic = 0x12345678; + HAL.reset(true); +#endif +} + +/* + * Reads four bytes from the eeprom. + * + * @param channel Id of SPI channel to be used with 1 = SPI.ch1 and 2 = SPI.ch2 + * @param address Address the byte should be read from. + * + * @return The bytes read with byte0 = lowest byte or 0 if reading went unsuccessful + */ +static void readIdEeprom(void) +{ + SPIChannelTypeDef *spi; + if(ActualCommand.Type == 1) + spi = &SPI.ch1; + else if(ActualCommand.Type == 2) + spi = &SPI.ch2; + else + { + ActualReply.Status = REPLY_INVALID_TYPE; + return; + } + + uint8_t array[4]; + eeprom_read_array(spi, ActualCommand.Value.Int32, array, 4); + ActualReply.Value.Int32 = array[3] << 24 | array[2] << 16 | array[1] << 8 | array[0]; +} + +/* + * Writes one byte into the eeprom for id detection. + * + * @param channel Id of SPI channel to be used with 1 = SPI.ch1 and 2 = SPI.ch2 + * @param address Address the byte should be written to. + * @param bytes Pointer to byte array that are to be written. The first byte is always written + * following bytes are written as long as they are not null. + * + * @return false if everything went successful + * 1 if selected channel is not available + * the status bits of the eeprom if eeprom is not ready + */ +static void writeIdEeprom(void) +{ + SPIChannelTypeDef *spi; + if(ActualCommand.Type == 1) + spi = &SPI.ch1; + else if(ActualCommand.Type == 2) + spi = &SPI.ch2; + else + { + ActualReply.Status = REPLY_INVALID_TYPE; + return; + } + + uint8_t out = eeprom_check(spi); + // ignore when check did not find magic number, quit on other errors + if(out != ID_CHECKERROR_MAGICNUMBER && out != 0) + { + ActualReply.Status = REPLY_EEPROM_LOCKED; // todo CHECK 2: Not sure which error to send here, this one sounded ok (LH) + return; + } + + eeprom_write_byte(spi, ActualCommand.Value.Int32, ActualCommand.Motor); + + return; +} + +static void SetGlobalParameter() +{ + switch(ActualCommand.Type) + { + case 1: + VitalSignsMonitor.errorMask = ActualCommand.Value.Int32; + break; + case 2: + setDriversEnable(); + break; + case 3: + switch(ActualCommand.Value.Int32) + { + case 0: // normal operation + VitalSignsMonitor.debugMode = 0; + break; + case 1: // FREE ERROR LED + VitalSignsMonitor.debugMode = 1; + HAL.LEDs->error.off(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } + break; + case 6: + if(Evalboards.ch1.onPinChange(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32) + && Evalboards.ch2.onPinChange(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32)) + HAL.IOs->config->setToState(HAL.IOs->pins->pins[ActualCommand.Motor], ActualCommand.Value.UInt32); + break; + case 7: + ActualReply.Value.UInt32 = spi_setFrequency(&HAL.SPI->ch1, ActualCommand.Value.UInt32); + break; + case 8: + ActualReply.Value.UInt32 = spi_setFrequency(&HAL.SPI->ch2, ActualCommand.Value.UInt32); + break; + case 9: + if (!spi_setMode(&HAL.SPI->ch1, ActualCommand.Value.UInt32)) + { + ActualReply.Status = REPLY_INVALID_VALUE; + break; + } + break; + case 10: + if (!spi_setMode(&HAL.SPI->ch2, ActualCommand.Value.UInt32)) + { + ActualReply.Status = REPLY_INVALID_VALUE; + break; + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void GetGlobalParameter() +{ + switch(ActualCommand.Type) + { + case 1: + ActualReply.Value.Int32 = VitalSignsMonitor.errors; + break; + case 2: + ActualReply.Value.Int32 = (Evalboards.driverEnable == DRIVER_ENABLE)? 1:0; + break; + case 3: + ActualReply.Value.Int32 = VitalSignsMonitor.debugMode; + break; + case 4: + { + IdAssignmentTypeDef ids; + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + ActualReply.Value.Int32 = Board_supported(&ids); + } + break; + case 5: // Get hardware ID + ActualReply.Value.Int32 = hwid; + break; + case 6: + ActualReply.Value.UInt32 = HAL.IOs->config->getState(HAL.IOs->pins->pins[ActualCommand.Motor]); + break; + case 7: + ActualReply.Value.UInt32 = spi_getFrequency(&HAL.SPI->ch1); + break; + case 8: + ActualReply.Value.UInt32 = spi_getFrequency(&HAL.SPI->ch2); + break; + case 9: + ActualReply.Value.UInt32 = spi_getMode(&HAL.SPI->ch1); + break; + case 10: + ActualReply.Value.UInt32 = spi_getMode(&HAL.SPI->ch2); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardAssignment(void) +{ + uint8_t testOnly = 0; + + IdAssignmentTypeDef ids; + ids.ch1.id = (ActualCommand.Value.Int32 >> 0) & 0xFF; + ids.ch1.state = (ActualCommand.Value.Int32 >> 8) & 0xFF; + ids.ch2.id = (ActualCommand.Value.Int32 >> 16) & 0xFF; + ids.ch2.state = (ActualCommand.Value.Int32 >> 24) & 0xFF; + + switch(ActualCommand.Type) + { + case 0: // auto detect and assign + checkIDs(); + return; + break; + case 1: // id for channel 2 not changed, reset maybe + ids.ch2.id = Evalboards.ch2.id; + ids.ch2.state = ID_STATE_WAIT_LOW; + break; + case 2: // id for channel 1 not changed, reset maybe + ids.ch2.id = (ActualCommand.Value.Int32 >> 0) & 0xFF; + ids.ch2.state = (ActualCommand.Value.Int32 >> 8) & 0xFF; + ids.ch1.id = Evalboards.ch1.id; + ids.ch1.state = ID_STATE_WAIT_LOW; + break; + case 3: // id for both channels + break; + case 4: // test if ids are in firmware + testOnly = 1; + if(ActualReply.Value.Int32 == 0) + { + ids.ch1.id = Evalboards.ch1.id; + ids.ch2.id = Evalboards.ch2.id; + } + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + return; + break; + } + + IdAssignmentTypeDef ids_buff; + ids_buff.ch1.id = ids.ch1.id; + ids_buff.ch1.state = ID_STATE_DONE; + ids_buff.ch2.id = ids.ch2.id; + ids_buff.ch2.state = ID_STATE_DONE; + + if(!testOnly) + ActualReply.Value.Int32 = Board_assign(&ids_buff); + else + ActualReply.Value.Int32 = Board_supported(&ids_buff); +} + +static void boardsErrors(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = Evalboards.ch1.errors; + break; + case 1: + ActualReply.Value.Int32 = Evalboards.ch2.errors; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardsReset(void) +{ + switch(ActualCommand.Type) + { + case 0: + if(!Evalboards.ch1.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + case 1: + if(!Evalboards.ch2.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + case 2: + if(!Evalboards.ch1.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + if(!Evalboards.ch2.config->reset()) + ActualReply.Status = REPLY_WRITE_PROTECTED; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void boardsMeasuredSpeed(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Status = Evalboards.ch1.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32); + break; + case 1: + ActualReply.Status = Evalboards.ch2.getMeasuredSpeed(ActualCommand.Motor, &ActualReply.Value.Int32); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void setDriversEnable() +{ + vitalsignsmonitor_clearOvervoltageErrors(); + + Evalboards.driverEnable = (ActualCommand.Value.Int32) ? DRIVER_ENABLE : DRIVER_DISABLE; + Evalboards.ch1.enableDriver(DRIVER_USE_GLOBAL_ENABLE); + Evalboards.ch2.enableDriver(DRIVER_USE_GLOBAL_ENABLE); +} + +static void checkIDs(void) +{ + IdAssignmentTypeDef ids = { 0 }; + + if(IDDetection_detect(&ids)) + { + ActualReply.Value.Int32 = (uint32_t) + ( + (ids.ch1.id) + | (ids.ch1.state << 8) + | (ids.ch2.id << 16) + | (ids.ch2.state << 24) + ); + + Board_assign(&ids); + } + else + { + ActualReply.Status = REPLY_DELAYED; + } +} + +static void SoftwareReset(void) +{ + if(ActualCommand.Value.Int32 == 1234) + resetRequest = true; +} + +static void GetVersion(void) +{ + if(ActualCommand.Type == VERSION_FORMAT_ASCII) + { + ActualReply.IsSpecial = 1; + ActualReply.Special[0] = SERIAL_HOST_ADDRESS; + + for(uint8_t i = 0; i < 8; i++) + ActualReply.Special[i+1] = VersionString[i]; + } + else if(ActualCommand.Type == VERSION_FORMAT_BINARY) + { + uint8_t tmpVal; + + // module version high + tmpVal = (uint8_t) VersionString[0] - '0'; // Ascii digit - '0' = digit value + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[1] - '0'; + ActualReply.Value.Byte[3] = tmpVal; + + // module version low + tmpVal = (uint8_t) VersionString[2] - '0'; + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[3] - '0'; + ActualReply.Value.Byte[2] = tmpVal; + + // fw version high + ActualReply.Value.Byte[1] = (uint8_t) VersionString[5] - '0'; + + // fw version low + tmpVal = (uint8_t) VersionString[6] - '0'; + tmpVal *= 10; + tmpVal += (uint8_t) VersionString[7] - '0'; + ActualReply.Value.Byte[0] = tmpVal; + } + //how were the boards detected? // todo CHECK 2: Doesn't fit into GetVersion. Move somewhere else? Or maybe change GetVersion to GetBoardInfo or something (LH) + else if(ActualCommand.Type == VERSION_BOARD_DETECT_SRC) + { + ActualReply.Value.Byte[0] = IdState.ch1.detectedBy; + ActualReply.Value.Byte[1] = IdState.ch2.detectedBy; + } + else if(ActualCommand.Type == VERSION_BUILD) { + ActualReply.Value.UInt32 = BUILD_VERSION; + } +} + +static void GetInput(void) +{ + if((Evalboards.ch1.GIO(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32) == TMC_ERROR_NONE) + || (Evalboards.ch2.GIO(ActualCommand.Type, ActualCommand.Motor, &ActualReply.Value.Int32) == TMC_ERROR_NONE)) + return; + + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = *HAL.ADCs->AIN0; + break; + case 1: + ActualReply.Value.Int32 = *HAL.ADCs->AIN1; + break; + case 2: + ActualReply.Value.Int32 = *HAL.ADCs->AIN2; + break; + case 3: + ActualReply.Value.Int32 = *HAL.ADCs->DIO4; + break; + case 4: + ActualReply.Value.Int32 = *HAL.ADCs->DIO5; + break; + case 5: + ActualReply.Value.Int32 = VitalSignsMonitor.VM; + break; + case 6: // Raw VM ADC value, no scaling calculation done // todo QOL 2: Switch this case with case 5? That way we have the raw Values from 0-5, then 6 for scaled VM value. Requires IDE changes (LH) + ActualReply.Value.Int32 = *HAL.ADCs->VM; + break; + case 7: + ActualReply.Value.Int32 = *HAL.ADCs->AIN_EXT; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void HandleWlanCommand(void) +{ + switch(ActualCommand.Type) + { + case 0: + ActualReply.Value.Int32 = handleWLANCommand(ActualCommand.Motor, ActualCommand.Value.Int32); + break; + case 1: + enableWLANCommandMode(); + break; + case 2: + ActualReply.Value.Int32 = checkReadyToSend(); + break; + case 3: + ActualReply.Value.Int32 = checkCmdModeEnabled(); + break; + case 4: + ActualReply.Value.Int32 = getCMDReply(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void handleRamDebug(void) +{ + switch (ActualCommand.Type) + { + case 0: + debug_init(); + break; + case 1: + debug_setSampleCount(ActualCommand.Value.Int32); + break; + case 2: + /* Placeholder: Set sampling time reference*/ + if (ActualCommand.Value.Int32 != 0) + ActualReply.Status = REPLY_INVALID_VALUE; + break; + case 3: + // RAMDebug expects a divisor value where 1 is original capture frequency, + // 2 is halved capture frequency etc. + // The TMCL-IDE sends prescaling values that are one lower than that. + debug_setPrescaler(ActualCommand.Value.Int32 + 1); + break; + case 4: + if (!debug_setChannel(ActualCommand.Motor, ActualCommand.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 5: + if (!debug_setTriggerChannel(ActualCommand.Motor, ActualCommand.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 6: + debug_setTriggerMaskShift(ActualCommand.Value.Int32, ActualCommand.Motor); + break; + case 7: + debug_enableTrigger(ActualCommand.Motor, ActualCommand.Value.Int32); + break; + case 8: + ActualReply.Value.Int32 = debug_getState(); + break; + case 9: + if (!debug_getSample(ActualCommand.Value.Int32, (uint32_t *)&ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 10: + ActualReply.Value.Int32 = debug_getInfo(ActualCommand.Value.Int32); + break; + case 11: + if (!debug_getChannelType(ActualCommand.Motor, (uint8_t *) &ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 12: + if (!debug_getChannelAddress(ActualCommand.Motor, (uint32_t *) &ActualReply.Value.Int32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 13: + debug_setPretriggerSampleCount(ActualCommand.Value.UInt32); + break; + case 14: + ActualReply.Value.UInt32 = debug_getPretriggerSampleCount(); + break; + case 15: + if(Timer.initialized) { + Timer.setFrequency(TIMER_CHANNEL_2, ActualCommand.Value.UInt32); + ActualReply.Value.UInt32 = Timer.getPeriod(TIMER_CHANNEL_2); + } + break; + case 16: + if (!debug_setType(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 17: + if (!debug_setEvalChannel(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 18: + if (!debug_setAddress(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 19: + if (!debug_setTriggerType(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 20: + if (!debug_setTriggerEvalChannel(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + case 21: + if (!debug_setTriggerAddress(ActualCommand.Value.UInt32)) + ActualReply.Status = REPLY_MAX_EXCEEDED; + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} + +static void handleOTP(void) +{ + switch (ActualCommand.Type) + { + case 0: // OTP_INIT + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_init(); + break; + case 1: // OTP_ADDRESS + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_address(ActualCommand.Value.UInt32); + break; + case 2: // OTP_VALUE + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_value(ActualCommand.Value.UInt32); + break; + case 3: // OTP_PROGRAM + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_program(); + break; + case 4: // OTP_LOCK + ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_lock(); + break; + case 5: // OTP_STATUS + ActualReply.Value.UInt32 = ((ActualCommand.Motor == 1) ? &Evalboards.ch2 : &Evalboards.ch1)->OTP_status(); + break; + default: + ActualReply.Status = REPLY_INVALID_TYPE; + break; + } +} diff --git a/TMC2209/lib/tmc/tmc/TMCL.h b/TMC2209/lib/tmc/tmc/TMCL.h new file mode 100644 index 0000000..3bd6bd1 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/TMCL.h @@ -0,0 +1,19 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef TMCL_H +#define TMCL_H + +#include "tmc/helpers/API_Header.h" + +void tmcl_init(); +void tmcl_process(); +void tmcl_boot(); + +#endif /* TMCL_H */ diff --git a/TMC2209/lib/tmc/tmc/VitalSignsMonitor.c b/TMC2209/lib/tmc/tmc/VitalSignsMonitor.c new file mode 100644 index 0000000..b7092f8 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/VitalSignsMonitor.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#include "VitalSignsMonitor.h" + +#include "hal/derivative.h" +#include "boards/Board.h" +#include "hal/HAL.h" + +#define VM_MIN_INTERFACE_BOARD 70 // minimum motor supply voltage for system in [100mV] +#define VM_MAX_INTERFACE_BOARD 700 // maximum motor supply voltage for system in [100mV] + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) +#define VM_FACTOR 713 // ADC reaches limit at VM = 71.3V => VM Factor (in 100mV) = 713 +#elif defined(LandungsbrueckeV3) +#define VM_FACTOR 744 +#endif + + +// Status LED frequencies +// Values are time in ms between LED toggles +#define VSM_HEARTRATE_NORMAL 500 // Normal: 1 Hz +#define VSM_HEARTRATE_FAST 50 // Busy: 10 Hz + +#define VSM_BROWNOUT_DELAY 100 // Delay (in 10ms) between voltage (re-)application and configuration restoration + +VitalSignsMonitorTypeDef VitalSignsMonitor = +{ + .brownOut = 0, // motor supply to low + .VM = 0, // actual measured motor supply VM + .heartRate = VSM_HEARTRATE_NORMAL, // status LED blinking frequency + .errorMask = 0xFFFFFFFF, // error mask, each bit stands for one error bit, 1 means error will be reported + .busy = 0, // if module is busy, status LED is blinking fast + .debugMode = 0, // debug mode e.g. releases error LED for debug purpose + .errors = 0 // actual error bits +}; + +#if defined(Landungsbruecke) || defined(LandungsbrueckeSmall) + #define ADC_VM_RES 65535 +#elif defined(LandungsbrueckeV3) + #define ADC_VM_RES 4095 +#endif + +// Make the status LED blink +// Frequency informs about normal operation or busy state +void heartBeat(uint32_t tick) +{ + static uint32_t lastTick = 0; + + if(VitalSignsMonitor.heartRate == 0) + return; + + if((tick - lastTick) > VitalSignsMonitor.heartRate) + { + LED_TOGGLE(); + lastTick = tick; + } +} + +// Check for over/undervoltage of motor supply VM +void checkVM() +{ + int32_t VM; + static uint8_t stable = VSM_BROWNOUT_DELAY + 1; // delay value + 1 is the state during normal voltage levels - set here to prevent restore shortly after boot + static uint8_t vio_state = 1; + + VM = *HAL.ADCs->VM; // read ADC value for motor supply VM + VM = (VM*VM_FACTOR)/ADC_VM_RES; // calculate voltage from ADC value + + VitalSignsMonitor.VM = VM; // write to interface + VitalSignsMonitor.overVoltage = 0; // reset overvoltage status + VitalSignsMonitor.brownOut = 0; // reset undervoltage status + + // check for over/undervoltage and set according status if necessary + if(VM > VM_MAX_INTERFACE_BOARD) VitalSignsMonitor.overVoltage |= VSM_CHX; + if(VM > Evalboards.ch1.VMMax) VitalSignsMonitor.overVoltage |= VSM_CHX | VSM_CH1; + if(VM > Evalboards.ch2.VMMax) VitalSignsMonitor.overVoltage |= VSM_CHX | VSM_CH2; + + // check for over/undervoltage and set according status if necessary + if (Evalboards.ch1.VMMin > 0) + if(VM < Evalboards.ch1.VMMin) VitalSignsMonitor.brownOut |= VSM_CHX | VSM_CH1; + if (Evalboards.ch2.VMMin > 0) + if(VM < Evalboards.ch2.VMMin) VitalSignsMonitor.brownOut |= VSM_CHX | VSM_CH2; + // Global minimum voltage check (skipped if a minimum voltage of 0 is set by a board) + if(Evalboards.ch1.VMMin && Evalboards.ch2.VMMin) + if(VM < VM_MIN_INTERFACE_BOARD) VitalSignsMonitor.brownOut |= VSM_CHX; + + if((VitalSignsMonitor.errors & VSM_ERRORS_CH1) || (VitalSignsMonitor.errors & VSM_ERRORS_CH2)) // VIO low in CH1 + { + if((Evalboards.ch1.errors & VSM_ERRORS_VIO_LOW) || (Evalboards.ch2.errors & VSM_ERRORS_VIO_LOW)) + { + vio_state = 0; + } + } + else if(vio_state == 0) // VIO high + { + Evalboards.ch2.config->reset(); + Evalboards.ch1.config->reset(); + vio_state = 1; + } + + // after brownout all settings are restored to the boards + // this happens after supply was stable for a set delay (checkVM() is called every 10 ms/systicks) + if(VitalSignsMonitor.brownOut) + { + stable = 0; + } + else + { + if(stable < VSM_BROWNOUT_DELAY) + { + stable++; + } + else if(stable == VSM_BROWNOUT_DELAY) + { + Evalboards.ch2.config->restore(); + Evalboards.ch1.config->restore(); + + stable++; + } + } +} + +/* Routine to frequently check system for errors */ +void vitalsignsmonitor_checkVitalSigns() +{ + int32_t errors = 0; + static uint32_t lastTick = 0; + uint32_t tick; + + tick = systick_getTick(); + + // Check motor supply VM every 10ms + if((tick - lastTick) >= 10) + { + checkVM(); + lastTick = tick; + } + + // Check for board errors + Evalboards.ch2.checkErrors(tick); + Evalboards.ch1.checkErrors(tick); + + // Status LED + heartBeat(tick); + + // reset all error bits but not the voltage errors + errors = VitalSignsMonitor.errors & (VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2); + + // collect errors from board channels + if(Evalboards.ch1.errors) + errors |= VSM_ERRORS_CH1; + if(Evalboards.ch2.errors) + errors |= VSM_ERRORS_CH2; + + if(VitalSignsMonitor.busy) + errors |= VSM_BUSY; + if(Evalboards.ch1.config->state != CONFIG_READY) + errors |= VSM_BUSY | VSM_BUSY_CH1; + if(Evalboards.ch2.config->state != CONFIG_READY) + errors |= VSM_BUSY | VSM_BUSY_CH2; + + if(VitalSignsMonitor.brownOut) + errors |= VSM_WARNING_CPU_SUPPLY_LOW; + if(VitalSignsMonitor.brownOut & VSM_CH1 ) + errors |= VSM_ERRORS_VM | VSM_ERRORS_BROWNOUT_CH1; + if(VitalSignsMonitor.brownOut & VSM_CH2 ) + errors |= VSM_ERRORS_VM | VSM_ERRORS_BROWNOUT_CH2; + + if(VitalSignsMonitor.overVoltage) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE; + if(VitalSignsMonitor.overVoltage & VSM_CH1) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1; + if(VitalSignsMonitor.overVoltage & VSM_CH2) + errors |= VSM_ERRORS_VM | VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH2; + + VitalSignsMonitor.errors = errors & VitalSignsMonitor.errorMask; // write collected errors to interface + + // disable drivers on overvoltage + if(errors & (VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2)) + { + Evalboards.driverEnable = DRIVER_DISABLE; // set global driver enable to disabled + Evalboards.ch1.enableDriver(DRIVER_DISABLE); // disable driver for motion controller board + Evalboards.ch2.enableDriver(DRIVER_DISABLE); // disable driver for driver + } + + // set debug LED if not in debug mode + // set status LED if not in debug mode + if(!VitalSignsMonitor.debugMode) + { + if(VitalSignsMonitor.errors & (~(VSM_BUSY | VSM_BUSY_CH1 | VSM_BUSY_CH2 | VSM_WARNING_CPU_SUPPLY_LOW))) + HAL.LEDs->error.on(); + else + HAL.LEDs->error.off(); + + if(VitalSignsMonitor.errors & (VSM_BUSY | VSM_BUSY_CH1 | VSM_BUSY_CH2)) + VitalSignsMonitor.heartRate = VSM_HEARTRATE_FAST; + else + VitalSignsMonitor.heartRate = VSM_HEARTRATE_NORMAL; + } +} + +void vitalsignsmonitor_clearOvervoltageErrors() +{ + VitalSignsMonitor.errors &= ~(VSM_ERRORS_OVERVOLTAGE | VSM_ERRORS_OVERVOLTAGE_CH1 | VSM_ERRORS_OVERVOLTAGE_CH2); +} diff --git a/TMC2209/lib/tmc/tmc/VitalSignsMonitor.h b/TMC2209/lib/tmc/tmc/VitalSignsMonitor.h new file mode 100644 index 0000000..7829fb1 --- /dev/null +++ b/TMC2209/lib/tmc/tmc/VitalSignsMonitor.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG +* (now owned by Analog Devices Inc.), +* +* Copyright © 2023 Analog Devices Inc. All Rights Reserved. This software is +* proprietary & confidential to Analog Devices, Inc. and its licensors. +*******************************************************************************/ + + +#ifndef VITAL_SIGNS_MONITOR_H +#define VITAL_SIGNS_MONITOR_H + +#include "tmc/helpers/API_Header.h" + +typedef struct +{ + int8_t debugMode; // while debugMode is set, the error LED does not get set by VSM and status LED heartrate does not get updated + int8_t busy; // if module is busy, the status LED is blinking fast + uint8_t brownOut; // Undervoltage condition flags + uint8_t overVoltage; // Overvoltage condition flags + int32_t errorMask; // error mask, each bit stands for one error bit, 1 means error will be reported + int32_t errors; // actual error bits + uint32_t heartRate; // status LED blinking frequency + uint32_t VM; // actual measured motor supply VM +} VitalSignsMonitorTypeDef; + +extern VitalSignsMonitorTypeDef VitalSignsMonitor; // global implementation of interface for system + +// error bits +#define VSM_CHX (1<<0) // any errors on the evalboards +#define VSM_CH1 (1<<1) // any errors on motion controller board +#define VSM_CH2 (1<<2) // any errors on driver board + +#define VSM_ERRORS_VM (1<<0) // something's wrong with the motor supply VM for any board +#define VSM_ERRORS_CH1 (1<<1) // something's wrong with the motor supply VM for motion controller board +#define VSM_ERRORS_CH2 (1<<2) // something's wrong with the motor supply VM for driver board +#define VSM_BUSY (1<<3) // any board is busy +#define VSM_BUSY_CH1 (1<<4) // motion controller board is busy +#define VSM_BUSY_CH2 (1<<5) // driver board is busy +#define VSM_WARNING_CPU_SUPPLY_LOW (1<<6) // motor supply VM is to low for the processor -> Supply over USB needed +#define VSM_ERRORS_BROWNOUT_CH1 (1<<7) // motor supply VM is to low for motion controller board +#define VSM_ERRORS_BROWNOUT_CH2 (1<<8) // motor supply VM is to low for driver board +#define VSM_ERRORS_OVERVOLTAGE (1<<9) // motor supply VM is to high for any board +#define VSM_ERRORS_OVERVOLTAGE_CH1 (1<<10) // motor supply VM is to high for motion controller board +#define VSM_ERRORS_OVERVOLTAGE_CH2 (1<<11) // motor supply VM is to high for driver board + +#define VSM_ERRORS_VIO_LOW (1 << 1) + +void vitalsignsmonitor_checkVitalSigns(); +void vitalsignsmonitor_clearOvervoltageErrors(); + +#endif /* VITAL_SIGNS_MONITOR_H */ diff --git a/TMC2209/main.c b/TMC2209/main.c new file mode 100644 index 0000000..cd0585d --- /dev/null +++ b/TMC2209/main.c @@ -0,0 +1,224 @@ + + +#include +#include "pico/stdlib.h" +#include "hardware/uart.h" +#include "hardware/irq.h" // Inclure le fichier d'en-tête pour les interruptions +#include "Tmc_uart.h" +#include "Tmc2209.h" + +#include "hardware/gpio.h" +#include "unistd.h" + + +TMC_UART uart_instance; +TMC2209 Tmc2209; + + + +void test_movement(){ + const uint LED_PIN = 7; + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + gpio_put(LED_PIN, 0); + + sleep_ms(1000); + int max = 1600; + for (int i = 100; i <= max; i += 100) { + set_vactual(&Tmc2209,i*256); + sleep_us(1); + int stg = get_stallguard(&Tmc2209); + int tstep = get_tstep(&Tmc2209); + + printf("Stg : %d , %d \n",stg,tstep); + } + + uint32_t start_time = time_us_32(); + uint32_t current_time = start_time; + + while (current_time - start_time < 1000000000) { // 10 secondes en microsecondes + int stg = get_stallguard(&Tmc2209); + int tstep = get_tstep(&Tmc2209); + + printf("Stg : %d , %d \n",stg,tstep); + current_time = time_us_32(); + + } + + + + for (int i = max; i >= 100; i -= 100) { + set_vactual(&Tmc2209,i*256); + sleep_us(1); + int stg = get_stallguard(&Tmc2209); + int tstep = get_tstep(&Tmc2209); + + printf("Stg : %d , %d \n",stg,tstep); + } + set_vactual(&Tmc2209,0); + + // sleep_ms(10000); + gpio_put(LED_PIN, 1); + +} + + +void setup(){ + clear_general_stat(&Tmc2209); + // sleep_ms(2000); + set_voltage_sense(&Tmc2209, false); + // sleep_ms(2000); + set_current_flow(&Tmc2209, 100, 0.5, 10, 5.4); + // sleep_ms(2000); + set_iscale_analog(&Tmc2209, false); + // sleep_ms(2000); + set_interpolation(&Tmc2209, true); + // sleep_ms(2000); + set_internal_resistor_sense(&Tmc2209, false); + // sleep_ms(2000); + set_spread_cycle(&Tmc2209, true); + // sleep_ms(2000); + set_microstepping_resolution(&Tmc2209,256); + // sleep_ms(2000); + set_microstep_resolution_regselect(&Tmc2209, true); + int32_t resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution begin : %ld\n", resolution); +} + +void test_direction(){ + int direction = get_direction_shart(&Tmc2209); + printf("Direction 1 : %d\n", direction); + sleep_ms(1000); + + set_direction_shart(&Tmc2209,false); + sleep_ms(1000); + + direction = get_direction_shart(&Tmc2209); + printf("Direction 2 (false): %d\n", direction); + sleep_ms(1000); + + set_direction_shart(&Tmc2209,true); + sleep_ms(1000); + + direction = get_direction_shart(&Tmc2209); + printf("Direction 3 (true): %d\n", direction); +} + + +void test_ustep(){ + int32_t resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution begin : %ld\n", resolution); + sleep_ms(1000); + set_microstepping_resolution(&Tmc2209,256); + sleep_ms(1000); + resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution after new go to 1/256: %ld\n", resolution); + sleep_ms(1000); + set_microstepping_resolution(&Tmc2209,16); + sleep_ms(10); + resolution = get_microstepping_resolution(&Tmc2209); + printf("Microstepping resolution after renew go to 1/16: %ld\n", resolution); + printf(get_microstepping_resolution(&Tmc2209)); +} + +void test_iscale(){ + int iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 1 : %d\n", iscale); + sleep_ms(1000); + set_iscale_analog(&Tmc2209,false); + sleep_ms(1000); + iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 2 (false): %d\n", iscale); + sleep_ms(1000); + set_iscale_analog(&Tmc2209,true); + sleep_ms(1000); + iscale = get_iscale_analog(&Tmc2209); + printf("Iscale 3 (true): %d\n", iscale); +} + +void test_interpolation(){ + int interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 1 : %d\n", interpolation); + sleep_ms(1000); + set_interpolation(&Tmc2209,false); + sleep_ms(1000); + interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 2 (false): %d\n", interpolation); + sleep_ms(1000); + set_interpolation(&Tmc2209,true); + sleep_ms(1000); + interpolation = get_interpolation(&Tmc2209); + printf("Interpolation 3 (true): %d\n", interpolation); +} + +void test_internal_resistor_sense(){ + int resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 1 : %d\n", resistor); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,false); + sleep_ms(1000); + resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 2 (false): %d\n", resistor); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,true); + sleep_ms(1000); + resistor = get_internal_resistor_sense(&Tmc2209); + printf("Internal_resistor_sense 3 (true): %d\n", resistor); +} + +void test_spread_cycle(){ + int spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 1 : %d\n", spread_cycle); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,false); + sleep_ms(1000); + spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 2 (false): %d\n", spread_cycle); + sleep_ms(1000); + set_internal_resistor_sense(&Tmc2209,true); + sleep_ms(1000); + spread_cycle = get_spread_cycle(&Tmc2209); + printf("Spread_cycle 3 (true): %d\n", spread_cycle); +} + + +int main() { + stdio_init_all(); + + + // Initialisation de l'UART avec les paramètres par défaut + + tmc_Uart_Init(&uart_instance, uart1, -1, -1, -1); + + + TMC2209_Init(&Tmc2209,&uart_instance); + + + + sleep_ms(4000); + + + // clear_general_stat(&uart_instance); + printf("UART initialisé avec succès\n"); + + // driver_status(&Tmc2209); + // general_config(&Tmc2209); + // general_stat(&Tmc2209); + + setup(); + + // test_iscale(); + // test_interpolation(); + // test_internal_resistor_sense(); + // test_spread_cycle(); + + // test_direction(); + + // test_ustep(); + + test_movement(); + + + return 0; +} + diff --git a/TMC2209/picowatch.sh b/TMC2209/picowatch.sh new file mode 100644 index 0000000..eebf457 --- /dev/null +++ b/TMC2209/picowatch.sh @@ -0,0 +1,9 @@ +python tools/html_to_hpp.py + +cd build/ +cmake -G "MinGW Makefiles" .. +make beyondmotion +# ss -com:3 -baud:1200 -noc +cp beyondmotion.uf2 F:/ +sleep 1 +# ss -com:3 -baud:115200 -noc \ No newline at end of file diff --git a/Trinamic-library b/Trinamic-library new file mode 160000 index 0000000..a9f1a50 --- /dev/null +++ b/Trinamic-library @@ -0,0 +1 @@ +Subproject commit a9f1a50d7fe511f81ccdbe4387e3a554b1b29f83 diff --git a/rp2_w5100s_20221111_v2.0.0.uf2 b/rp2_w5100s_20221111_v2.0.0.uf2 new file mode 100644 index 0000000..9898762 Binary files /dev/null and b/rp2_w5100s_20221111_v2.0.0.uf2 differ diff --git a/rpi-pico-servo b/rpi-pico-servo new file mode 160000 index 0000000..f319089 --- /dev/null +++ b/rpi-pico-servo @@ -0,0 +1 @@ +Subproject commit f3190893899f6dc25b2f63d654356713472a3979